 @@ -1,39 +1,39 @@
-/*	$NetBSD: sdhc.c,v 1.55 2015/04/14 18:34:29 bouyer Exp $	*/
+/*	$NetBSD: sdhc.c,v 1.56 2015/05/02 12:10:24 jmcneill Exp $	*/
 /*	$OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $	*/
 /*
  * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
+ *
  * Permission to use, copy, modify, and distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
  * copyright notice and this permission notice appear in all copies.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 /*
  * SD Host Controller driver based on the SD Host Controller Standard
  * Simplified Specification Version 1.00 (www.sdcard.com).
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.55 2015/04/14 18:34:29 bouyer Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.56 2015/05/02 12:10:24 jmcneill Exp $");
 #ifdef _KERNEL_OPT
 #include "opt_sdmmc.h"
 #endif
 #include <sys/param.h>
 #include <sys/device.h>
 #include <sys/kernel.h>
 #include <sys/kthread.h>
 #include <sys/malloc.h>
 #include <sys/systm.h>
 #include <sys/mutex.h>
 #include <sys/condvar.h>
 @@ -279,26 +279,30 @@ sdhc_host_found(struct sdhc_softc *sc, b
 	switch (SDHC_SPEC_VERSION(sdhcver)) {
 	case SDHC_SPEC_VERS_100:
 		aprint_normal("1.0");
 		break;
 	case SDHC_SPEC_VERS_200:
 		aprint_normal("2.0");
 		break;
 	case SDHC_SPEC_VERS_300:
 		aprint_normal("3.0");
 		break;
 	case SDHC_SPEC_VERS_400:
 		aprint_normal("4.0");
 		break;
 	default:
 		aprint_normal("unknown version(0x%x)",
 		    SDHC_SPEC_VERSION(sdhcver));
 		break;
+	}
 	aprint_normal(", rev.%u\n", SDHC_VENDOR_VERSION(sdhcver));
 	/*
 	 * Reset the host controller and enable interrupts.
 	 */
 	(void)sdhc_host_reset(hp);
 	/* Determine host capabilities. */
 @@ -319,32 +323,33 @@ sdhc_host_found(struct sdhc_softc *sc, b
 	    (ISSET(sc->sc_flags, SDHC_FLAG_USE_DMA &&
 	     ISSET(caps, SDHC_DMA_SUPPORT)))) {
 		SET(hp->flags, SHF_USE_DMA);
 		if (!ISSET(sc->sc_flags, SDHC_FLAG_EXTERNAL_DMA) ||
 		    ISSET(sc->sc_flags, SDHC_FLAG_EXTDMA_DMAEN))
 			SET(hp->flags, SHF_MODE_DMAEN);
 		aprint_normal_dev(sc->sc_dev, "using DMA transfer\n");
+	}
 	/*
 	 * Determine the base clock frequency. (2.2.24)
 	 */
-	if (hp->specver == SDHC_SPEC_VERS_300) {
+	if (hp->specver >= SDHC_SPEC_VERS_300) {
 		hp->clkbase = SDHC_BASE_V3_FREQ_KHZ(caps);
 	} else {
 		hp->clkbase = SDHC_BASE_FREQ_KHZ(caps);
+	}
-	if (hp->clkbase == 0) {
+	if (hp->clkbase == 0 ||
 	    ISSET(sc->sc_flags, SDHC_FLAG_NO_CLKBASE)) {
 		if (sc->sc_clkbase == 0) {
 			/* The attachment driver must tell us. */
 			aprint_error_dev(sc->sc_dev,
 			    "unknown base clock frequency\n");
 			goto err;
+		}
 		hp->clkbase = sc->sc_clkbase;
+	}
 	if (hp->clkbase < 10000 || hp->clkbase > 10000 * 256) {
 		/* SDHC 1.0 supports only 10-63 MHz. */
 		aprint_error_dev(sc->sc_dev,
 		    "base clock frequency out of range: %u MHz\n",
 		    hp->clkbase / 1000);
 @@ -414,27 +419,27 @@ sdhc_host_found(struct sdhc_softc *sc, b
 	memset(&saa, 0, sizeof(saa));
 	saa.saa_busname = "sdmmc";
 	saa.saa_sct = &sdhc_functions;
 	saa.saa_sch = hp;
 	saa.saa_dmat = hp->dmat;
 	saa.saa_clkmax = hp->clkbase;
 	if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_CGM))
 		saa.saa_clkmin = hp->clkbase / 256 / 2046;
 	else if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_DVS))
 		saa.saa_clkmin = hp->clkbase / 256 / 16;
 	else if (hp->sc->sc_clkmsk != 0)
 		saa.saa_clkmin = hp->clkbase / (hp->sc->sc_clkmsk >>
 		    (ffs(hp->sc->sc_clkmsk) - 1));
-	else if (hp->specver == SDHC_SPEC_VERS_300)
+	else if (hp->specver >= SDHC_SPEC_VERS_300)
 		saa.saa_clkmin = hp->clkbase / 0x3ff;
 	else
 		saa.saa_clkmin = hp->clkbase / 256;
 	saa.saa_caps = SMC_CAPS_4BIT_MODE|SMC_CAPS_AUTO_STOP;
 	if (ISSET(sc->sc_flags, SDHC_FLAG_8BIT_MODE))
 		saa.saa_caps |= SMC_CAPS_8BIT_MODE;
 	if (ISSET(caps, SDHC_HIGH_SPEED_SUPP))
 		saa.saa_caps |= SMC_CAPS_SD_HIGHSPEED;
 	if (ISSET(hp->flags, SHF_USE_DMA)) {
 		saa.saa_caps |= SMC_CAPS_DMA;
 		if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED))
 			saa.saa_caps |= SMC_CAPS_MULTI_SEG_DMA;
+	}
 @@ -817,27 +822,27 @@ sdhc_clock_divisor(struct sdhc_host *hp,
 			roundup |= dvs & 1;
+		}
 		/* No divisor found. */
 		return false;
+	}
 	if (hp->sc->sc_clkmsk != 0) {
 		div = howmany(hp->clkbase, freq);
 		if (div > (hp->sc->sc_clkmsk >> (ffs(hp->sc->sc_clkmsk) - 1)))
 			return false;
 		*divp = div << (ffs(hp->sc->sc_clkmsk) - 1);
 		//freq = hp->clkbase / div;
 		return true;
+	}
-	if (hp->specver == SDHC_SPEC_VERS_300) {
+	if (hp->specver >= SDHC_SPEC_VERS_300) {
 		div = howmany(hp->clkbase, freq);
 		div = div > 1 ? howmany(div, 2) : 0;
 		if (div > 0x3ff)
 			return false;
 		*divp = (((div >> 8) & SDHC_SDCLK_XDIV_MASK)
 			 << SDHC_SDCLK_XDIV_SHIFT) |
 			(((div >> 0) & SDHC_SDCLK_DIV_MASK)
 			 << SDHC_SDCLK_DIV_SHIFT);
 		//freq = hp->clkbase / div;
 		return true;
 	} else {
 		for (div = 1; div <= 256; div *= 2) {
 			if ((hp->clkbase / div) <= freq) {

 @@ -1,14 +1,14 @@
-/*	$NetBSD: sdhcreg.h,v 1.12 2015/01/26 04:56:56 nonaka Exp $	*/
+/*	$NetBSD: sdhcreg.h,v 1.13 2015/05/02 12:10:24 jmcneill Exp $	*/
 /*	$OpenBSD: sdhcreg.h,v 1.4 2006/07/30 17:20:40 fgsch Exp $	*/
 /*
  * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
+ *
  * Permission to use, copy, modify, and distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
  * copyright notice and this permission notice appear in all copies.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 @@ -173,26 +173,27 @@
 #define SDHC_ESDHC_HOST_CTL_VERSION	0xfc	/* eSDHC */
 #define SDHC_HOST_CTL_VERSION		0xfe
 #define  SDHC_SPEC_VERS_SHIFT		0
 #define  SDHC_SPEC_VERS_MASK		0xff
 #define  SDHC_VENDOR_VERS_SHIFT		8
 #define  SDHC_VENDOR_VERS_MASK		0xff
 #define SDHC_DMA_CTL			0x40c	/* eSDHC */
 #define  SDHC_DMA_SNOOP			0x40
 /* SDHC_SPEC_VERS */
 #define SDHC_SPEC_VERS_100		0x00
 #define SDHC_SPEC_VERS_200		0x01
 #define SDHC_SPEC_VERS_300		0x02
 #define SDHC_SPEC_VERS_400		0x03
 /* SDHC_CAPABILITIES decoding */
 #define SDHC_BASE_V3_FREQ_KHZ(cap)					\
 	((((cap) >> SDHC_BASE_FREQ_SHIFT) & SDHC_BASE_V3_FREQ_MASK) * 1000)
 #define SDHC_BASE_FREQ_KHZ(cap)						\
 	((((cap) >> SDHC_BASE_FREQ_SHIFT) & SDHC_BASE_FREQ_MASK) * 1000)
 #define SDHC_TIMEOUT_FREQ(cap)						\
 	(((cap) >> SDHC_TIMEOUT_FREQ_SHIFT) & SDHC_TIMEOUT_FREQ_MASK)
 #define SDHC_TIMEOUT_FREQ_KHZ(cap)					\
 	(((cap) & SDHC_TIMEOUT_FREQ_UNIT) ?				\
 	    SDHC_TIMEOUT_FREQ(cap) * 1000:				\
 	    SDHC_TIMEOUT_FREQ(cap))

 @@ -1,14 +1,14 @@
-/*	$NetBSD: sdhcvar.h,v 1.16 2015/04/14 18:34:29 bouyer Exp $	*/
+/*	$NetBSD: sdhcvar.h,v 1.17 2015/05/02 12:10:24 jmcneill Exp $	*/
 /*	$OpenBSD: sdhcvar.h,v 1.3 2007/09/06 08:01:01 jsg Exp $	*/
 /*
  * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
+ *
  * Permission to use, copy, modify, and distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
  * copyright notice and this permission notice appear in all copies.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 @@ -42,26 +42,27 @@ struct sdhc_softc {
 #define	SDHC_FLAG_HAVE_DVS	0x00000008 /* Freescale ESDHC */
 #define	SDHC_FLAG_32BIT_ACCESS	0x00000010 /* Freescale ESDHC */
 #define	SDHC_FLAG_ENHANCED	0x00000020 /* Freescale ESDHC */
 #define	SDHC_FLAG_8BIT_MODE	0x00000040 /* MMC 8bit mode is supported */
 #define	SDHC_FLAG_HAVE_CGM	0x00000080 /* Netlogic XLP */
 #define	SDHC_FLAG_NO_LED_ON	0x00000100 /* LED_ON unsupported in HOST_CTL */
 #define	SDHC_FLAG_HOSTCAPS	0x00000200 /* No device provided capabilities */
 #define	SDHC_FLAG_RSP136_CRC	0x00000400 /* Resp 136 with CRC and end-bit */
 #define	SDHC_FLAG_SINGLE_ONLY	0x00000800 /* Single transfer only */
 #define	SDHC_FLAG_WAIT_RESET	0x00001000 /* Wait for soft resets to start */
 #define	SDHC_FLAG_NO_HS_BIT	0x00002000 /* Don't set SDHC_HIGH_SPEED bit */
 #define	SDHC_FLAG_EXTERNAL_DMA	0x00004000
 #define	SDHC_FLAG_EXTDMA_DMAEN	0x00008000 /* ext. dma need SDHC_DMA_ENABLE */
 #define	SDHC_FLAG_NO_CLKBASE	0x00020000 /* ignore clkbase register */
 	uint32_t		sc_clkbase;
 	int			sc_clkmsk;	/* Mask for SDCLK */
 	uint32_t		sc_caps;/* attachment provided capabilities */
 	int (*sc_vendor_rod)(struct sdhc_softc *, int);
 	int (*sc_vendor_write_protect)(struct sdhc_softc *);
 	int (*sc_vendor_card_detect)(struct sdhc_softc *);
 	int (*sc_vendor_bus_clock)(struct sdhc_softc *, int);
 	int (*sc_vendor_transfer_data_dma)(struct sdhc_softc *, struct sdmmc_command *);
 };
 /* Host controller functions called by the attachment driver. */