Sun May 17 06:12:40 2015 UTC ()
Add a missing defined(CORTEX_A15)


(matt)
diff -r1.37 -r1.38 src/sys/arch/arm/cortex/a9_mpsubr.S
cvs diff -r1.37 -r1.38 src/sys/arch/arm/cortex/Attic/a9_mpsubr.S (expand / switch to unified diff)

--- src/sys/arch/arm/cortex/Attic/a9_mpsubr.S 2015/05/15 10:57:55 1.37
+++ src/sys/arch/arm/cortex/Attic/a9_mpsubr.S 2015/05/17 06:12:40 1.38
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: a9_mpsubr.S,v 1.37 2015/05/15 10:57:55 skrll Exp $ */ 1/* $NetBSD: a9_mpsubr.S,v 1.38 2015/05/17 06:12:40 matt Exp $ */
2/*- 2/*-
3 * Copyright (c) 2012 The NetBSD Foundation, Inc. 3 * Copyright (c) 2012 The NetBSD Foundation, Inc.
4 * All rights reserved. 4 * All rights reserved.
5 * 5 *
6 * This code is derived from software contributed to The NetBSD Foundation 6 * This code is derived from software contributed to The NetBSD Foundation
7 * by Matt Thomas of 3am Software Foundry. 7 * by Matt Thomas of 3am Software Foundry.
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
11 * are met: 11 * are met:
12 * 1. Redistributions of source code must retain the above copyright 12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer. 13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright 14 * 2. Redistributions in binary form must reproduce the above copyright
@@ -340,27 +340,27 @@ cortex_init: @@ -340,27 +340,27 @@ cortex_init:
340 msr spsr_sxc, r0 // set SPSR[23:8] to known value 340 msr spsr_sxc, r0 // set SPSR[23:8] to known value
341 341
342 XPUTC(#'@') 342 XPUTC(#'@')
343#if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15) || defined(CPU_CORTEXA17) 343#if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15) || defined(CPU_CORTEXA17)
344 // 344 //
345 // If SMP is already enabled, don't do anything. 345 // If SMP is already enabled, don't do anything.
346 // 346 //
347 mrc p15, 0, r0, c1, c0, 1 // ACTLR read 347 mrc p15, 0, r0, c1, c0, 1 // ACTLR read
348 tst r0, #CORTEXA9_AUXCTL_SMP // test SMP 348 tst r0, #CORTEXA9_AUXCTL_SMP // test SMP
349 bxne r10 // return if set 349 bxne r10 // return if set
350#endif 350#endif
351 351
352 mrc p15, 0, r4, c1, c0, 0 // SCTLR read 352 mrc p15, 0, r4, c1, c0, 0 // SCTLR read
353#if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA17) 353#if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15) || defined(CPU_CORTEXA17)
354 // 354 //
355 // Before turning on SMP, turn off the caches and the MMU. 355 // Before turning on SMP, turn off the caches and the MMU.
356 // 356 //
357 dsb 357 dsb
358 movw r1,#(CPU_CONTROL_IC_ENABLE|CPU_CONTROL_DC_ENABLE\ 358 movw r1,#(CPU_CONTROL_IC_ENABLE|CPU_CONTROL_DC_ENABLE\
359 |CPU_CONTROL_MMU_ENABLE) 359 |CPU_CONTROL_MMU_ENABLE)
360 bic r0, r4, r1 // disable icache/dcache/mmu 360 bic r0, r4, r1 // disable icache/dcache/mmu
361 mcr p15, 0, r0, c1, c0, 0 // SCTLR write 361 mcr p15, 0, r0, c1, c0, 0 // SCTLR write
362 dsb 362 dsb
363 isb 363 isb
364#endif 364#endif
365 365
366 mov r0, #0 366 mov r0, #0