| @@ -1,14 +1,14 @@ | | | @@ -1,14 +1,14 @@ |
| 1 | /* $NetBSD: mii.h,v 1.18 2014/06/16 14:43:22 msaitoh Exp $ */ | | 1 | /* $NetBSD: mii.h,v 1.19 2015/07/21 02:04:24 msaitoh Exp $ */ |
| 2 | | | 2 | |
| 3 | /* | | 3 | /* |
| 4 | * Copyright (c) 1997 Manuel Bouyer. All rights reserved. | | 4 | * Copyright (c) 1997 Manuel Bouyer. All rights reserved. |
| 5 | * | | 5 | * |
| 6 | * Modification to match BSD/OS 3.0 MII interface by Jason R. Thorpe, | | 6 | * Modification to match BSD/OS 3.0 MII interface by Jason R. Thorpe, |
| 7 | * Numerical Aerospace Simulation Facility, NASA Ames Research Center. | | 7 | * Numerical Aerospace Simulation Facility, NASA Ames Research Center. |
| 8 | * | | 8 | * |
| 9 | * Redistribution and use in source and binary forms, with or without | | 9 | * Redistribution and use in source and binary forms, with or without |
| 10 | * modification, are permitted provided that the following conditions | | 10 | * modification, are permitted provided that the following conditions |
| 11 | * are met: | | 11 | * are met: |
| 12 | * 1. Redistributions of source code must retain the above copyright | | 12 | * 1. Redistributions of source code must retain the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer. | | 13 | * notice, this list of conditions and the following disclaimer. |
| 14 | * 2. Redistributions in binary form must reproduce the above copyright | | 14 | * 2. Redistributions in binary form must reproduce the above copyright |
| @@ -188,29 +188,29 @@ | | | @@ -188,29 +188,29 @@ |
| 188 | #define GTSR_LP_ASM_DIR 0x0200 /* link partner asym. pause dir. capable */ | | 188 | #define GTSR_LP_ASM_DIR 0x0200 /* link partner asym. pause dir. capable */ |
| 189 | #define GTSR_IDLE_ERR 0x00ff /* IDLE error count */ | | 189 | #define GTSR_IDLE_ERR 0x00ff /* IDLE error count */ |
| 190 | | | 190 | |
| 191 | #define MII_PSECR 0x0b /* PSE control register */ | | 191 | #define MII_PSECR 0x0b /* PSE control register */ |
| 192 | #define PSECR_PACTLMASK 0x000c /* pair control mask */ | | 192 | #define PSECR_PACTLMASK 0x000c /* pair control mask */ |
| 193 | #define PSECR_PSEENMASK 0x0003 /* PSE enable mask */ | | 193 | #define PSECR_PSEENMASK 0x0003 /* PSE enable mask */ |
| 194 | #define PSECR_PINOUTB 0x0008 /* PSE pinout Alternative B */ | | 194 | #define PSECR_PINOUTB 0x0008 /* PSE pinout Alternative B */ |
| 195 | #define PSECR_PINOUTA 0x0004 /* PSE pinout Alternative A */ | | 195 | #define PSECR_PINOUTA 0x0004 /* PSE pinout Alternative A */ |
| 196 | #define PSECR_FOPOWTST 0x0002 /* Force Power Test Mode */ | | 196 | #define PSECR_FOPOWTST 0x0002 /* Force Power Test Mode */ |
| 197 | #define PSECR_PSEEN 0x0001 /* PSE Enabled */ | | 197 | #define PSECR_PSEEN 0x0001 /* PSE Enabled */ |
| 198 | #define PSECR_PSEDIS 0x0000 /* PSE Disabled */ | | 198 | #define PSECR_PSEDIS 0x0000 /* PSE Disabled */ |
| 199 | | | 199 | |
| 200 | #define MII_PSESR 0x0c /* PSE status register */ | | 200 | #define MII_PSESR 0x0c /* PSE status register */ |
| 201 | #define PSESR_PWRDENIED 0x1000 /* Power Deined */ | | 201 | #define PSESR_PWRDENIED 0x1000 /* Power Denied */ |
| 202 | #define PSESR_VALSIG 0x0800 /* Valid PD signature detected */ | | 202 | #define PSESR_VALSIG 0x0800 /* Valid PD signature detected */ |
| 203 | #define PSESR_INVALSIG 0x0400 /* Inalid PD signature detected */ | | 203 | #define PSESR_INVALSIG 0x0400 /* Invalid PD signature detected */ |
| 204 | #define PSESR_SHORTCIRC 0x0200 /* Short circuit condition detected */ | | 204 | #define PSESR_SHORTCIRC 0x0200 /* Short circuit condition detected */ |
| 205 | #define PSESR_OVERLOAD 0x0100 /* Overload condition detected */ | | 205 | #define PSESR_OVERLOAD 0x0100 /* Overload condition detected */ |
| 206 | #define PSESR_MPSABSENT 0x0080 /* MPS absent condition detected */ | | 206 | #define PSESR_MPSABSENT 0x0080 /* MPS absent condition detected */ |
| 207 | #define PSESR_PDCLMASK 0x0070 /* PD Class mask */ | | 207 | #define PSESR_PDCLMASK 0x0070 /* PD Class mask */ |
| 208 | #define PSESR_STATMASK 0x000e /* PSE Status mask */ | | 208 | #define PSESR_STATMASK 0x000e /* PSE Status mask */ |
| 209 | #define PSESR_PAIRCTABL 0x0001 /* PAIR Control Ability */ | | 209 | #define PSESR_PAIRCTABL 0x0001 /* PAIR Control Ability */ |
| 210 | #define PSESR_PDCL_4 (4 << 4) /* Class 4 */ | | 210 | #define PSESR_PDCL_4 (4 << 4) /* Class 4 */ |
| 211 | #define PSESR_PDCL_3 (3 << 4) /* Class 3 */ | | 211 | #define PSESR_PDCL_3 (3 << 4) /* Class 3 */ |
| 212 | #define PSESR_PDCL_2 (2 << 4) /* Class 2 */ | | 212 | #define PSESR_PDCL_2 (2 << 4) /* Class 2 */ |
| 213 | #define PSESR_PDCL_1 (1 << 4) /* Class 1 */ | | 213 | #define PSESR_PDCL_1 (1 << 4) /* Class 1 */ |
| 214 | #define PSESR_PDCL_0 (0 << 4) /* Class 0 */ | | 214 | #define PSESR_PDCL_0 (0 << 4) /* Class 0 */ |
| 215 | | | 215 | |
| 216 | #define MII_MMDACR 0x0d /* MMD access control register */ | | 216 | #define MII_MMDACR 0x0d /* MMD access control register */ |