 @@ -1,14 +1,14 @@
-/*	$NetBSD: if_bge.c,v 1.292 2015/06/14 08:46:33 martin Exp $	*/
+/*	$NetBSD: if_bge.c,v 1.293 2015/07/21 03:15:50 knakahara Exp $	*/
 /*
  * Copyright (c) 2001 Wind River Systems
  * Copyright (c) 1997, 1998, 1999, 2001
  *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
 @@ -69,27 +69,27 @@
  * does not support external SSRAM.
+ *
  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  * brand name, which is functionally similar but lacks PCI-X support.
+ *
  * Without external SSRAM, you can only have at most 4 TX rings,
  * and the use of the mini RX ring is disabled. This seems to imply
  * that these features are simply not available on the BCM5701. As a
  * result, this driver does not implement any support for the mini RX
  * ring.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.292 2015/06/14 08:46:33 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.293 2015/07/21 03:15:50 knakahara Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/callout.h>
 #include <sys/sockio.h>
 #include <sys/mbuf.h>
 #include <sys/malloc.h>
 #include <sys/kernel.h>
 #include <sys/device.h>
 #include <sys/socket.h>
 #include <sys/sysctl.h>
 #include <net/if.h>
 @@ -3331,44 +3331,44 @@ bge_probe(device_t parent, cfdata_t matc
+}
 static void
 bge_attach(device_t parent, device_t self, void *aux)
+{
 	struct bge_softc	*sc = device_private(self);
 	struct pci_attach_args	*pa = aux;
 	prop_dictionary_t dict;
 	const struct bge_product *bp;
 	const struct bge_revision *br;
 	pci_chipset_tag_t	pc;
 #ifndef __HAVE_PCI_MSI_MSIX
 	pci_intr_handle_t	ih;
 #else
 	int counts[PCI_INTR_TYPE_SIZE];
 	pci_intr_type_t intr_type, max_type;
 #endif
 	const char		*intrstr = NULL;
 	uint32_t 		hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5;
 	uint32_t		command;
 	struct ifnet		*ifp;
 	uint32_t		misccfg, mimode;
 	void *			kva;
 	u_char			eaddr[ETHER_ADDR_LEN];
 	pcireg_t		memtype, subid, reg;
 	bus_addr_t		memaddr;
 	uint32_t		pm_ctl;
 	bool			no_seeprom;
 	int			capmask;
 	int			mii_flags;
 	int			map_flags;
 #ifdef __HAVE_PCI_MSI_MSIX
 	int			rv;
 #endif
 	char intrbuf[PCI_INTRSTR_LEN];
 	bp = bge_lookup(pa);
 	KASSERT(bp != NULL);
 	sc->sc_pc = pa->pa_pc;
 	sc->sc_pcitag = pa->pa_tag;
 	sc->bge_dev = self;
 	sc->bge_pa = *pa;
 	pc = sc->sc_pc;
 	subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG);
 @@ -3717,65 +3717,74 @@ bge_attach(device_t parent, device_t sel
 		if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
 			BGE_SRAM_DATA_SIG_MAGIC)) {
 			if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) &
 			    BGE_HWCFG_ASF) {
 				sc->bge_asf_mode |= ASF_ENABLE;
 				sc->bge_asf_mode |= ASF_STACKUP;
 				if (BGE_IS_575X_PLUS(sc))
 					sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
+			}
+		}
+	}
 #ifdef __HAVE_PCI_MSI_MSIX
-	DPRINTFN(5, ("pci_get_capability\n"));
+	counts[PCI_INTR_TYPE_MSI] = 1;
 	counts[PCI_INTR_TYPE_INTX] = 1;
 	/* Check MSI capability */
-	if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSI,
+	if (bge_can_use_msi(sc) != 0) {
-		&sc->bge_msicap, NULL) != 0) {
+		max_type = PCI_INTR_TYPE_MSI;
-		if (bge_can_use_msi(sc) != 0)
+		sc->bge_flags |= BGEF_MSI;
-			sc->bge_flags |= BGEF_MSI;
+	} else
 		max_type = PCI_INTR_TYPE_INTX;
 	rv = -1;
-	if (((sc->bge_flags & BGEF_MSI) != 0) && (pci_msi_count(pa) > 0)) {
+alloc_retry:
-		DPRINTFN(5, ("pci_msi_alloc\n"));
+	if (pci_intr_alloc(pa, &sc->bge_pihp, counts, max_type) != 0) {
-		rv = pci_msi_alloc_exact(pa, &sc->bge_pihp, 1);
+		aprint_error_dev(sc->bge_dev, "couldn't alloc interrupt\n");
-		if (rv != 0)
+		return;
 			sc->bge_flags &= ~BGEF_MSI;
 	if (rv != 0) {
 		DPRINTFN(5, ("pci_intx_alloc\n"));
 		if (pci_intx_alloc(pa, &sc->bge_pihp)) {
 			aprint_error_dev(self, "can't map interrupt\n");
 			return;
 		sc->bge_flags &= ~BGEF_MSI;
+	}
 #else	/* !__HAVE_PCI_MSI_MSIX */
 	DPRINTFN(5, ("pci_intr_map\n"));
 	if (pci_intr_map(pa, &ih)) {
 		aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n");
 		return;
+	}
 #endif
 #ifdef __HAVE_PCI_MSI_MSIX
 	DPRINTFN(5, ("pci_intr_string\n"));
 #ifdef __HAVE_PCI_MSI_MSIX
 	intrstr = pci_intr_string(pc, sc->bge_pihp[0], intrbuf,
 	    sizeof(intrbuf));
 	DPRINTFN(5, ("pci_intr_establish\n"));
 	sc->bge_intrhand = pci_intr_establish(pc, sc->bge_pihp[0], IPL_NET,
 	    bge_intr, sc);
 	if (sc->bge_intrhand == NULL) {
 		intr_type = pci_intr_type(sc->bge_pihp[0]);
 		aprint_error_dev(sc->bge_dev,"unable to establish %s\n",
 		    (intr_type == PCI_INTR_TYPE_MSI) ? "MSI" : "INTx");
 		pci_intr_release(pc, sc->bge_pihp, 1);
 		switch (intr_type) {
 		case PCI_INTR_TYPE_MSI:
 			/* The next try is for INTx: Disable MSI */
 			max_type = PCI_INTR_TYPE_INTX;
 			counts[PCI_INTR_TYPE_INTX] = 1;
 			sc->bge_flags &= ~BGEF_MSI;
 			goto alloc_retry;
 		case PCI_INTR_TYPE_INTX:
 		default:
 			/* See below */
 			break;
+		}
+	}
 #else	/* !__HAVE_PCI_MSI_MSIX */
 	DPRINTFN(5, ("pci_intr_string\n"));
 	intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf));
 	DPRINTFN(5, ("pci_intr_establish\n"));
 	sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc);
 #endif
 	if (sc->bge_intrhand == NULL) {
 		aprint_error_dev(sc->bge_dev,
 		    "couldn't establish interrupt%s%s\n",
 		    intrstr ? " at " : "", intrstr ? intrstr : "");
 		return;
+	}
 	aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr);

 @@ -1,14 +1,14 @@
-/*	$NetBSD: if_wm.c,v 1.339 2015/07/15 07:40:54 msaitoh Exp $	*/
+/*	$NetBSD: if_wm.c,v 1.340 2015/07/21 03:15:50 knakahara Exp $	*/
 /*
  * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
 @@ -71,27 +71,27 @@
  * Device driver for the Intel i8254x family of Gigabit Ethernet chips.
+ *
  * TODO (in order of importance):
+ *
  *	- Check XXX'ed comments
  *	- EEE (Energy Efficiency Ethernet)
  *	- MSI/MSI-X
  *	- Virtual Function
  *	- Set LED correctly (based on contents in EEPROM)
  *	- Rework how parameters are loaded from the EEPROM.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.339 2015/07/15 07:40:54 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.340 2015/07/21 03:15:50 knakahara Exp $");
 #ifdef _KERNEL_OPT
 #include "opt_net_mpsafe.h"
 #endif
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/callout.h>
 #include <sys/mbuf.h>
 #include <sys/malloc.h>
 #include <sys/kernel.h>
 #include <sys/socket.h>
 #include <sys/ioctl.h>
 @@ -145,47 +145,49 @@ __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.
 int	wm_debug = WM_DEBUG_TX | WM_DEBUG_RX | WM_DEBUG_LINK | WM_DEBUG_GMII
     | WM_DEBUG_MANAGE | WM_DEBUG_NVM;
 #define	DPRINTF(x, y)	if (wm_debug & (x)) printf y
 #else
 #define	DPRINTF(x, y)	/* nothing */
 #endif /* WM_DEBUG */
 #ifdef NET_MPSAFE
 #define WM_MPSAFE	1
 #endif
 #ifdef __HAVE_PCI_MSI_MSIX
-#define WM_MSI_MSIX	1 /* Enable by default */
+#if 0 /* off by default */
 #define WM_MSI_MSIX	1
 #endif
 #endif
 /*
  * This device driver divides interrupt to TX, RX and link state.
  * Each MSI-X vector indexes are below.
  */
-#define WM_NINTR		3
+#define WM_MSIX_NINTR		3
-#define WM_TX_INTR_INDEX	0
+#define WM_MSIX_TXINTR_IDX	0
-#define WM_RX_INTR_INDEX	1
+#define WM_MSIX_RXINTR_IDX	1
-#define WM_LINK_INTR_INDEX	2
+#define WM_MSIX_LINKINTR_IDX	2
-#define WM_MAX_NINTR		WM_NINTR
+#define WM_MAX_NINTR		WM_MSIX_NINTR
 /*
  * This device driver set affinity to each interrupts like below (round-robin).
  * If the number CPUs is less than the number of interrupts, this driver usase
  * the same CPU for multiple interrupts.
  */
-#define WM_TX_INTR_CPUID	0
+#define WM_MSIX_TXINTR_CPUID	0
-#define WM_RX_INTR_CPUID	1
+#define WM_MSIX_RXINTR_CPUID	1
-#define WM_LINK_INTR_CPUID	2
+#define WM_MSIX_LINKINTR_CPUID	2
 /*
  * Transmit descriptor list size.  Due to errata, we can only have
  * 256 hardware descriptors in the ring on < 82544, but we use 4096
  * on >= 82544.  We tell the upper layers that they can queue a lot
  * of packets, and we go ahead and manage up to 64 (16 for the i82547)
  * of them at a time.
+ *
  * We allow up to 256 (!) DMA segments per packet.  Pathological packet
  * chains containing many small mbufs have been observed in zero-copy
  * situations with jumbo frames.
  */
 #define	WM_NTXSEGS		256
 @@ -768,26 +770,40 @@ static void	wm_set_eee_i350(struct wm_so
  * Basically, PHY's workarounds are in the PHY drivers.
  */
 static void	wm_kmrn_lock_loss_workaround_ich8lan(struct wm_softc *);
 static void	wm_gig_downshift_workaround_ich8lan(struct wm_softc *);
 static void	wm_hv_phy_workaround_ich8lan(struct wm_softc *);
 static void	wm_lv_phy_workaround_ich8lan(struct wm_softc *);
 static void	wm_k1_gig_workaround_hv(struct wm_softc *, int);
 static void	wm_set_mdio_slow_mode_hv(struct wm_softc *);
 static void	wm_configure_k1_ich8lan(struct wm_softc *, int);
 static void	wm_reset_init_script_82575(struct wm_softc *);
 static void	wm_reset_mdicnfg_82580(struct wm_softc *);
 static void	wm_pll_workaround_i210(struct wm_softc *);
 #ifdef WM_MSI_MSIX
 struct _msix_matrix {
 	const char *intrname;
 	int(*func)(void *);
 	int intridx;
 	int cpuid;
 } msix_matrix[WM_MSIX_NINTR] = {
 	{ "TX", wm_txintr_msix, WM_MSIX_TXINTR_IDX, WM_MSIX_TXINTR_CPUID },
 	{ "RX", wm_rxintr_msix, WM_MSIX_RXINTR_IDX, WM_MSIX_TXINTR_CPUID },
 	{ "LINK", wm_linkintr_msix, WM_MSIX_LINKINTR_IDX,
 	  WM_MSIX_LINKINTR_CPUID },
 };
 #endif
 CFATTACH_DECL3_NEW(wm, sizeof(struct wm_softc),
     wm_match, wm_attach, wm_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN);
 /*
  * Devices supported by this driver.
  */
 static const struct wm_product {
 	pci_vendor_id_t		wmp_vendor;
 	pci_product_id_t	wmp_product;
 	const char		*wmp_name;
 	wm_chip_type		wmp_type;
 	uint32_t		wmp_flags;
 #define	WMP_F_UNKNOWN		WM_MEDIATYPE_UNKNOWN
 @@ -1396,27 +1412,28 @@ wm_match(device_t parent, cfdata_t cf, v
 /* The attach function (ca_attach) */
 static void
 wm_attach(device_t parent, device_t self, void *aux)
+{
 	struct wm_softc *sc = device_private(self);
 	struct pci_attach_args *pa = aux;
 	prop_dictionary_t dict;
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	pci_chipset_tag_t pc = pa->pa_pc;
 #ifndef WM_MSI_MSIX
 	pci_intr_handle_t ih;
 #else
-	bool intr_established = false;
+	int counts[PCI_INTR_TYPE_SIZE];
 	pci_intr_type_t max_type;
 #endif
 	const char *intrstr = NULL;
 	const char *eetype, *xname;
 	bus_space_tag_t memt;
 	bus_space_handle_t memh;
 	bus_size_t memsize;
 	int memh_valid;
 	int i, error;
 	const struct wm_product *wmp;
 	prop_data_t ea;
 	prop_number_t pn;
 	uint8_t enaddr[ETHER_ADDR_LEN];
 	uint16_t cfg1, cfg2, swdpin, nvmword;
 @@ -1587,187 +1604,119 @@ wm_attach(device_t parent, device_t self
 	pci_intr_setattr(pc, &ih, PCI_INTR_MPSAFE, true);
 #endif
 	sc->sc_ihs[0] = pci_intr_establish(pc, ih, IPL_NET, wm_intr_legacy,sc);
 	if (sc->sc_ihs[0] == NULL) {
 		aprint_error_dev(sc->sc_dev, "unable to establish interrupt");
 		if (intrstr != NULL)
 			aprint_error(" at %s", intrstr);
 		aprint_error("\n");
 		return;
+	}
 	aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr);
 	sc->sc_nintrs = 1;
 #else /* WM_MSI_MSIX */
-	if (pci_msix_alloc_exact(pa, &sc->sc_intrs, WM_NINTR) == 0) {
+	/* Allocation settings */
-		/* 1st, try to use MSI-X */
+	max_type = PCI_INTR_TYPE_MSIX;
 	counts[PCI_INTR_TYPE_MSIX] = WM_MAX_NINTR;
 	counts[PCI_INTR_TYPE_MSI] = 1;
 	counts[PCI_INTR_TYPE_INTX] = 1;
 alloc_retry:
 	if (pci_intr_alloc(pa, &sc->sc_intrs, counts, max_type) != 0) {
 		aprint_error_dev(sc->sc_dev, "failed to allocate interrupt\n");
 		return;
+	}
 	if (pci_intr_type(sc->sc_intrs[0]) == PCI_INTR_TYPE_MSIX) {
 		void *vih;
 		kcpuset_t *affinity;
 		kcpuset_create(&affinity, false);
-		/*
+		for (i = 0; i < WM_MSIX_NINTR; i++) {
-		 * for TX
+			intrstr = pci_intr_string(pc,
-		 */
+			    sc->sc_intrs[msix_matrix[i].intridx], intrbuf,
-		intrstr = pci_intr_string(pc, sc->sc_intrs[WM_TX_INTR_INDEX],
+			    sizeof(intrbuf));
 		    intrbuf, sizeof(intrbuf));
 #ifdef WM_MPSAFE
-		pci_intr_setattr(pc, &sc->sc_intrs[WM_TX_INTR_INDEX],
+			pci_intr_setattr(pc,
-		    PCI_INTR_MPSAFE, true);
+			    &sc->sc_intrs[msix_matrix[i].intridx],
-#endif
+			    PCI_INTR_MPSAFE, true);
-		vih = pci_intr_establish(pc, sc->sc_intrs[WM_TX_INTR_INDEX],
+#endif
-		    IPL_NET, wm_txintr_msix, sc);
+			vih = pci_intr_establish(pc,
-		if (vih == NULL) {
+			    sc->sc_intrs[msix_matrix[i].intridx], IPL_NET,
-			aprint_error_dev(sc->sc_dev,
+			    msix_matrix[i].func, sc);
-			    "unable to establish MSI-X(for TX)%s%s\n",
+			if (vih == NULL) {
-			    intrstr ? " at " : "", intrstr ? intrstr : "");
+				aprint_error_dev(sc->sc_dev,
-			pci_intr_release(sc->sc_pc, sc->sc_intrs,
+				    "unable to establish MSI-X(for %s)%s%s\n",
-			    WM_NINTR);
+				    msix_matrix[i].intrname,
-			goto msi;
+				    intrstr ? " at " : "",
 				    intrstr ? intrstr : "");
-		kcpuset_zero(affinity);
+				pci_intr_release(sc->sc_pc, sc->sc_intrs,
-		/* Round-robin affinity */
+				    WM_MSIX_NINTR);
-		kcpuset_set(affinity, WM_TX_INTR_CPUID % ncpu);
+				kcpuset_destroy(affinity);
 		error = pci_intr_distribute(vih, affinity, NULL);
-		if (error == 0) {
+				/* Setup for MSI: Disable MSI-X */
-			aprint_normal_dev(sc->sc_dev,
+				max_type = PCI_INTR_TYPE_MSI;
-			    "for TX interrupting at %s affinity to %u\n",
+				counts[PCI_INTR_TYPE_MSI] = 1;
-			    intrstr, WM_TX_INTR_CPUID % ncpu);
+				counts[PCI_INTR_TYPE_INTX] = 1;
-		} else {
+				goto alloc_retry;
 			aprint_normal_dev(sc->sc_dev,
-			    "for TX interrupting at %s\n",
+			kcpuset_zero(affinity);
-			    intrstr);
+			/* Round-robin affinity */
 			kcpuset_set(affinity, msix_matrix[i].cpuid % ncpu);
-		sc->sc_ihs[WM_TX_INTR_INDEX] = vih;
+			error = pci_intr_distribute(vih, affinity, NULL);
 			if (error == 0) {
-		/*
+				aprint_normal_dev(sc->sc_dev,
-		 * for RX
+				    "for TX interrupting at %s affinity to %u\n",
-		 */
+				    intrstr, msix_matrix[i].cpuid % ncpu);
-		intrstr = pci_intr_string(pc, sc->sc_intrs[WM_RX_INTR_INDEX],
+			} else {
-		    intrbuf, sizeof(intrbuf));
+				aprint_normal_dev(sc->sc_dev,
-#ifdef WM_MPSAFE
+				    "for TX interrupting at %s\n", intrstr);
 		pci_intr_setattr(pc, &sc->sc_intrs[WM_RX_INTR_INDEX],
-		    PCI_INTR_MPSAFE, true);
+			sc->sc_ihs[msix_matrix[i].intridx] = vih;
 #endif
 		vih = pci_intr_establish(pc, sc->sc_intrs[WM_RX_INTR_INDEX],
 		    IPL_NET, wm_rxintr_msix, sc);
 		if (vih == NULL) {
 			aprint_error_dev(sc->sc_dev,
 			    "unable to establish MSI-X(for RX)%s%s\n",
 			    intrstr ? " at " : "", intrstr ? intrstr : "");
 			pci_intr_release(sc->sc_pc, sc->sc_intrs,
 			    WM_NINTR);
 			goto msi;
 		kcpuset_zero(affinity);
 		kcpuset_set(affinity, WM_RX_INTR_CPUID % ncpu);
 		error = pci_intr_distribute(vih, affinity, NULL);
 		if (error == 0) {
 			aprint_normal_dev(sc->sc_dev,
 			    "for RX interrupting at %s affinity to %u\n",
 			    intrstr, WM_RX_INTR_CPUID % ncpu);
 		} else {
 			aprint_normal_dev(sc->sc_dev,
 			    "for RX interrupting at %s\n",
 			    intrstr);
 		sc->sc_ihs[WM_RX_INTR_INDEX] = vih;
 		/*
 		 * for link state changing
 		 */
 		intrstr = pci_intr_string(pc, sc->sc_intrs[WM_LINK_INTR_INDEX],
 		    intrbuf, sizeof(intrbuf));
 #ifdef WM_MPSAFE
 		pci_intr_setattr(pc, &sc->sc_intrs[WM_LINK_INTR_INDEX],
 		    PCI_INTR_MPSAFE, true);
 #endif
 		vih = pci_intr_establish(pc, sc->sc_intrs[WM_LINK_INTR_INDEX],
 		    IPL_NET, wm_linkintr_msix, sc);
 		if (vih == NULL) {
 			aprint_error_dev(sc->sc_dev,
 			    "unable to establish MSI-X(for LINK)%s%s\n",
 			    intrstr ? " at " : "", intrstr ? intrstr : "");
 			pci_intr_release(sc->sc_pc, sc->sc_intrs,
 			    WM_NINTR);
 			goto msi;
 		kcpuset_zero(affinity);
 		kcpuset_set(affinity, WM_LINK_INTR_CPUID % ncpu);
 		error = pci_intr_distribute(vih, affinity, NULL);
 		if (error == 0) {
 			aprint_normal_dev(sc->sc_dev,
 			    "for LINK interrupting at %s affinity to %u\n",
 			    intrstr, WM_LINK_INTR_CPUID % ncpu);
 		} else {
 			aprint_normal_dev(sc->sc_dev,
 			    "for LINK interrupting at %s\n",
 			    intrstr);
+		}
 		sc->sc_ihs[WM_LINK_INTR_INDEX] = vih;
-		sc->sc_nintrs = WM_NINTR;
+		sc->sc_nintrs = WM_MSIX_NINTR;
 		kcpuset_destroy(affinity);
-		intr_established = true;
+	} else {
 		/* MSI or INTx */
 msi:
 	if ((intr_established == false)
 	    && (pci_msi_alloc_exact(pa, &sc->sc_intrs, 1) == 0)) {
 		/* 2nd, try to use MSI */
 		intrstr = pci_intr_string(pc, sc->sc_intrs[0], intrbuf,
 		    sizeof(intrbuf));
 #ifdef WM_MPSAFE
 		pci_intr_setattr(pc, &sc->sc_intrs[0], PCI_INTR_MPSAFE, true);
 #endif
 		sc->sc_ihs[0] = pci_intr_establish(pc, sc->sc_intrs[0],
 		    IPL_NET, wm_intr_legacy, sc);
 		if (sc->sc_ihs[0] == NULL) {
 			aprint_error_dev(sc->sc_dev, "unable to establish MSI\n");
 			pci_intr_release(sc->sc_pc, sc->sc_intrs,
 );
 			goto intx;
 		aprint_normal_dev(sc->sc_dev, "MSI at %s\n", intrstr);
 		sc->sc_nintrs = 1;
 		intr_established = true;
 intx:
 	if ((intr_established == false)
 	    && (pci_intx_alloc(pa, &sc->sc_intrs) == 0)) {
 		/* Last, try to use INTx */
 		intrstr = pci_intr_string(pc, sc->sc_intrs[0], intrbuf,
 		    sizeof(intrbuf));
 #ifdef WM_MPSAFE
 		pci_intr_setattr(pc, &sc->sc_intrs[0], PCI_INTR_MPSAFE, true);
 #endif
 		sc->sc_ihs[0] = pci_intr_establish(pc, sc->sc_intrs[0],
 		    IPL_NET, wm_intr_legacy, sc);
 		if (sc->sc_ihs[0] == NULL) {
-			aprint_error_dev(sc->sc_dev, "unable to establish MSI\n");
+			aprint_error_dev(sc->sc_dev,"unable to establish %s\n",
 			    (pci_intr_type(sc->sc_intrs[0])
 				== PCI_INTR_TYPE_MSI) ? "MSI" : "INTx");
 			pci_intr_release(sc->sc_pc, sc->sc_intrs, 1);
-			goto int_failed;
+			switch (pci_intr_type(sc->sc_intrs[0])) {
 			case PCI_INTR_TYPE_MSI:
 				/* The next try is for INTx: Disable MSI */
 				max_type = PCI_INTR_TYPE_INTX;
 				counts[PCI_INTR_TYPE_INTX] = 1;
 				goto alloc_retry;
 			case PCI_INTR_TYPE_INTX:
 			default:
 				return;
+			}
+		}
-		aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr);
+		aprint_normal_dev(sc->sc_dev, "%s at %s\n",
 		    (pci_intr_type(sc->sc_intrs[0]) == PCI_INTR_TYPE_MSI)
 			? "MSI" : "interrupting", intrstr);
 		sc->sc_nintrs = 1;
 		intr_established = true;
 int_failed:
 	if (intr_established == false) {
 		aprint_error_dev(sc->sc_dev, "failed to allocate interrput\n");
 		return;
+	}
 #endif /* WM_MSI_MSIX */
 	/*
 	 * Check the function ID (unit number of the chip).
 	 */
 	if ((sc->sc_type == WM_T_82546) || (sc->sc_type == WM_T_82546_3)
 	    || (sc->sc_type ==  WM_T_82571) || (sc->sc_type == WM_T_80003)
 	    || (sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
 	    || (sc->sc_type == WM_T_82580)
 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354))
 		sc->sc_funcid = (CSR_READ(sc, WMREG_STATUS)
 		    >> STATUS_FUNCID_SHIFT) & STATUS_FUNCID_MASK;
 @@ -4536,125 +4485,126 @@ wm_init_locked(struct ifnet *ifp)
 	CSR_WRITE(sc, WMREG_RXCSUM, reg);
 	/* Set up MSI-X */
 	if (sc->sc_nintrs > 1) {
 		uint32_t ivar;
 		if (sc->sc_type == WM_T_82575) {
 			/* Interrupt control */
 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
 			reg |= CTRL_EXT_PBA | CTRL_EXT_EIAME | CTRL_EXT_NSICR;
 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
 			/* TX */
-			CSR_WRITE(sc, WMREG_MSIXBM(WM_TX_INTR_INDEX),
+			CSR_WRITE(sc, WMREG_MSIXBM(WM_MSIX_TXINTR_IDX),
 			    EITR_TX_QUEUE0);
 			/* RX */
-			CSR_WRITE(sc, WMREG_MSIXBM(WM_RX_INTR_INDEX),
+			CSR_WRITE(sc, WMREG_MSIXBM(WM_MSIX_RXINTR_IDX),
 			    EITR_RX_QUEUE0);
 			/* Link status */
-			CSR_WRITE(sc, WMREG_MSIXBM(WM_LINK_INTR_INDEX),
+			CSR_WRITE(sc, WMREG_MSIXBM(WM_MSIX_LINKINTR_IDX),
 			    EITR_OTHER);
 		} else if (sc->sc_type == WM_T_82574) {
 			/* Interrupt control */
 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
 			reg |= CTRL_EXT_PBA | CTRL_EXT_EIAME;
 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
 			/* TX, RX and Link status */
-			ivar = __SHIFTIN((IVAR_VALID_82574 | WM_TX_INTR_INDEX),
+			ivar = __SHIFTIN((IVAR_VALID_82574|WM_MSIX_TXINTR_IDX),
 			    IVAR_TX_MASK_Q_82574(0));
-			ivar |= __SHIFTIN((IVAR_VALID_82574 |WM_RX_INTR_INDEX),
+			ivar |= __SHIFTIN((IVAR_VALID_82574
 				| WM_MSIX_RXINTR_IDX),
 			    IVAR_RX_MASK_Q_82574(0));
-			ivar |=__SHIFTIN((IVAR_VALID_82574|WM_LINK_INTR_INDEX),
+			ivar |=__SHIFTIN((IVAR_VALID_82574|WM_MSIX_LINKINTR_IDX),
 			    IVAR_OTHER_MASK);
 			CSR_WRITE(sc, WMREG_IVAR, ivar | IVAR_INT_ON_ALL_WB);
 		} else {
 			/* Interrupt control */
 			CSR_WRITE(sc, WMREG_GPIE, GPIE_NSICR
 			    | GPIE_MULTI_MSIX | GPIE_EIAME
 			    | GPIE_PBA);
 			switch (sc->sc_type) {
 			case WM_T_82580:
 			case WM_T_I350:
 			case WM_T_I354:
 			case WM_T_I210:
 			case WM_T_I211:
 				/* TX */
 				ivar = CSR_READ(sc, WMREG_IVAR_Q(0));
 				ivar &= ~IVAR_TX_MASK_Q(0);
 				ivar |= __SHIFTIN(
-					(WM_TX_INTR_INDEX | IVAR_VALID),
+					(WM_MSIX_TXINTR_IDX | IVAR_VALID),
 					IVAR_TX_MASK_Q(0));
 				CSR_WRITE(sc, WMREG_IVAR_Q(0), ivar);
 				/* RX */
 				ivar = CSR_READ(sc, WMREG_IVAR_Q(0));
 				ivar &= ~IVAR_RX_MASK_Q(0);
 				ivar |= __SHIFTIN(
-					(WM_RX_INTR_INDEX | IVAR_VALID),
+					(WM_MSIX_RXINTR_IDX | IVAR_VALID),
 					IVAR_RX_MASK_Q(0));
 				CSR_WRITE(sc, WMREG_IVAR_Q(0), ivar);
 				break;
 			case WM_T_82576:
 				/* TX */
 				ivar = CSR_READ(sc, WMREG_IVAR_Q_82576(0));
 				ivar &= ~IVAR_TX_MASK_Q_82576(0);
 				ivar |= __SHIFTIN(
-					(WM_TX_INTR_INDEX | IVAR_VALID),
+					(WM_MSIX_TXINTR_IDX | IVAR_VALID),
 					IVAR_TX_MASK_Q_82576(0));
 				CSR_WRITE(sc, WMREG_IVAR_Q_82576(0), ivar);
 				/* RX */
 				ivar = CSR_READ(sc, WMREG_IVAR_Q_82576(0));
 				ivar &= ~IVAR_RX_MASK_Q_82576(0);
 				ivar |= __SHIFTIN(
-					(WM_RX_INTR_INDEX | IVAR_VALID),
+					(WM_MSIX_RXINTR_IDX | IVAR_VALID),
 					IVAR_RX_MASK_Q_82576(0));
 				CSR_WRITE(sc, WMREG_IVAR_Q_82576(0), ivar);
 				break;
 			default:
 				break;
+			}
 			/* Link status */
-			ivar = __SHIFTIN((WM_LINK_INTR_INDEX | IVAR_VALID),
+			ivar = __SHIFTIN((WM_MSIX_LINKINTR_IDX | IVAR_VALID),
 			    IVAR_MISC_OTHER);
 			CSR_WRITE(sc, WMREG_IVAR_MISC, ivar);
+		}
+	}
 	/* Set up the interrupt registers. */
 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
 	sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 |
 	    ICR_RXO | ICR_RXT0;
 	if (sc->sc_nintrs > 1) {
 		uint32_t mask;
 		switch (sc->sc_type) {
 		case WM_T_82574:
 			CSR_WRITE(sc, WMREG_EIAC_82574,
 			    WMREG_EIAC_82574_MSIX_MASK);
 			sc->sc_icr |= WMREG_EIAC_82574_MSIX_MASK;
 			CSR_WRITE(sc, WMREG_IMS, sc->sc_icr);
 			break;
 		default:
 			if (sc->sc_type == WM_T_82575)
 				mask = EITR_RX_QUEUE0 |EITR_TX_QUEUE0
 				    | EITR_OTHER;
 			else
-				mask = (1 << WM_RX_INTR_INDEX)
+				mask = (1 << WM_MSIX_RXINTR_IDX)
-				    | (1 << WM_TX_INTR_INDEX)
+				    | (1 << WM_MSIX_TXINTR_IDX)
-				    | (1 << WM_LINK_INTR_INDEX);
+				    | (1 << WM_MSIX_LINKINTR_IDX);
 			CSR_WRITE(sc, WMREG_EIAC, mask);
 			CSR_WRITE(sc, WMREG_EIAM, mask);
 			CSR_WRITE(sc, WMREG_EIMS, mask);
 			CSR_WRITE(sc, WMREG_IMS, ICR_LSC);
 			break;
+		}
 	} else
 		CSR_WRITE(sc, WMREG_IMS, sc->sc_icr);
 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
 	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) {
 		reg = CSR_READ(sc, WMREG_KABGTXD);
 @@ -6642,45 +6592,45 @@ wm_txintr_msix(void *arg)
+{
 	struct wm_softc *sc = arg;
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	int handled = 0;
 	DPRINTF(WM_DEBUG_TX,
 	    ("%s: TX: got Tx intr\n", device_xname(sc->sc_dev)));
 	if (sc->sc_type == WM_T_82574)
 		CSR_WRITE(sc, WMREG_IMC, ICR_TXQ0); /* 82574 only */
 	else if (sc->sc_type == WM_T_82575)
 		CSR_WRITE(sc, WMREG_EIMC, EITR_TX_QUEUE0);
 	else
-		CSR_WRITE(sc, WMREG_EIMC, 1 << WM_TX_INTR_INDEX);
+		CSR_WRITE(sc, WMREG_EIMC, 1 << WM_MSIX_TXINTR_IDX);
 	WM_TX_LOCK(sc);
 	if (sc->sc_stopping)
 		goto out;
 	WM_EVCNT_INCR(&sc->sc_ev_txdw);
 	handled = wm_txeof(sc);
 out:
 	WM_TX_UNLOCK(sc);
 	if (sc->sc_type == WM_T_82574)
 		CSR_WRITE(sc, WMREG_IMS, ICR_TXQ0); /* 82574 only */
 	else if (sc->sc_type == WM_T_82575)
 		CSR_WRITE(sc, WMREG_EIMS, EITR_TX_QUEUE0);
 	else
-		CSR_WRITE(sc, WMREG_EIMS, 1 << WM_TX_INTR_INDEX);
+		CSR_WRITE(sc, WMREG_EIMS, 1 << WM_MSIX_TXINTR_IDX);
 	if (handled) {
 		/* Try to get more packets going. */
 		ifp->if_start(ifp);
+	}
 	return handled;
+}
 /*
  * wm_rxintr_msix:
+ *
  *	Interrupt service routine for RX interrupt for MSI-X.
 @@ -6688,84 +6638,84 @@ out:
 static int
 wm_rxintr_msix(void *arg)
+{
 	struct wm_softc *sc = arg;
 	DPRINTF(WM_DEBUG_TX,
 	    ("%s: RX: got Rx intr\n", device_xname(sc->sc_dev)));
 	if (sc->sc_type == WM_T_82574)
 		CSR_WRITE(sc, WMREG_IMC, ICR_RXQ0); /* 82574 only */
 	else if (sc->sc_type == WM_T_82575)
 		CSR_WRITE(sc, WMREG_EIMC, EITR_RX_QUEUE0);
 	else
-		CSR_WRITE(sc, WMREG_EIMC, 1 << WM_RX_INTR_INDEX);
+		CSR_WRITE(sc, WMREG_EIMC, 1 << WM_MSIX_RXINTR_IDX);
 	WM_RX_LOCK(sc);
 	if (sc->sc_stopping)
 		goto out;
 	WM_EVCNT_INCR(&sc->sc_ev_rxintr);
 	wm_rxeof(sc);
 out:
 	WM_RX_UNLOCK(sc);
 	if (sc->sc_type == WM_T_82574)
 		CSR_WRITE(sc, WMREG_IMS, ICR_RXQ0);
 	else if (sc->sc_type == WM_T_82575)
 		CSR_WRITE(sc, WMREG_EIMS, EITR_RX_QUEUE0);
 	else
-		CSR_WRITE(sc, WMREG_EIMS, 1 << WM_RX_INTR_INDEX);
+		CSR_WRITE(sc, WMREG_EIMS, 1 << WM_MSIX_RXINTR_IDX);
 	return 1;
+}
 /*
  * wm_linkintr_msix:
+ *
  *	Interrupt service routine for link status change for MSI-X.
  */
 static int
 wm_linkintr_msix(void *arg)
+{
 	struct wm_softc *sc = arg;
 	DPRINTF(WM_DEBUG_TX,
 	    ("%s: LINK: got link intr\n", device_xname(sc->sc_dev)));
 	if (sc->sc_type == WM_T_82574)
 		CSR_WRITE(sc, WMREG_IMC, ICR_OTHER); /* 82574 only */
 	else if (sc->sc_type == WM_T_82575)
 		CSR_WRITE(sc, WMREG_EIMC, EITR_OTHER);
 	else
-		CSR_WRITE(sc, WMREG_EIMC, 1 << WM_LINK_INTR_INDEX);
+		CSR_WRITE(sc, WMREG_EIMC, 1 << WM_MSIX_LINKINTR_IDX);
 	WM_TX_LOCK(sc);
 	if (sc->sc_stopping)
 		goto out;
 	WM_EVCNT_INCR(&sc->sc_ev_linkintr);
 	wm_linkintr(sc, ICR_LSC);
 out:
 	WM_TX_UNLOCK(sc);
 	if (sc->sc_type == WM_T_82574)
 		CSR_WRITE(sc, WMREG_IMS, ICR_OTHER | ICR_LSC); /* 82574 only */
 	else if (sc->sc_type == WM_T_82575)
 		CSR_WRITE(sc, WMREG_EIMS, EITR_OTHER);
 	else
-		CSR_WRITE(sc, WMREG_EIMS, 1 << WM_LINK_INTR_INDEX);
+		CSR_WRITE(sc, WMREG_EIMS, 1 << WM_MSIX_LINKINTR_IDX);
 	return 1;
+}
 #endif /* WM_MSI_MSIX */
 /*
  * Media related.
  * GMII, SGMII, TBI (and SERDES)
  */
 /* Common */
 /*