Thu Jul 23 15:08:19 2015 UTC ()
More defines


(skrll)
diff -r1.2 -r1.3 src/sys/arch/arm/nvidia/tegra_dcreg.h
diff -r1.2 -r1.3 src/sys/arch/arm/nvidia/tegra_hdmireg.h
cvs diff -r1.2 -r1.3 src/sys/arch/arm/nvidia/tegra_dcreg.h (expand / switch to unified diff)

--- src/sys/arch/arm/nvidia/tegra_dcreg.h 2015/07/23 14:31:05 1.2
+++ src/sys/arch/arm/nvidia/tegra_dcreg.h 2015/07/23 15:08:19 1.3
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: tegra_dcreg.h,v 1.2 2015/07/23 14:31:05 jmcneill Exp $ */ 1/* $NetBSD: tegra_dcreg.h,v 1.3 2015/07/23 15:08:19 skrll Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
@@ -129,32 +129,40 @@ @@ -129,32 +129,40 @@
129#define DC_COM_CMU_CSC_KGG_REG 0xcb8 129#define DC_COM_CMU_CSC_KGG_REG 0xcb8
130#define DC_COM_CMU_CSC_KBG_REG 0xcbc 130#define DC_COM_CMU_CSC_KBG_REG 0xcbc
131#define DC_COM_CMU_CSC_KRB_REG 0xcc0 131#define DC_COM_CMU_CSC_KRB_REG 0xcc0
132#define DC_COM_CMU_CSC_KGB_REG 0xcc4 132#define DC_COM_CMU_CSC_KGB_REG 0xcc4
133#define DC_COM_CMU_CSC_KBB_REG 0xcc8 133#define DC_COM_CMU_CSC_KBB_REG 0xcc8
134#define DC_COM_CMU_LUT_MASK_REG 0xccc 134#define DC_COM_CMU_LUT_MASK_REG 0xccc
135#define DC_COM_CMU_LUT1_REG 0xcd8 135#define DC_COM_CMU_LUT1_REG 0xcd8
136#define DC_COM_CMU_LUT2_REG 0xcdc 136#define DC_COM_CMU_LUT2_REG 0xcdc
137 137
138/* 138/*
139 * Display DISP registers 139 * Display DISP registers
140 */ 140 */
141#define DC_DISP_DISP_SIGNAL_OPTIONS0_REG 0x1000 141#define DC_DISP_DISP_SIGNAL_OPTIONS0_REG 0x1000
 142#define DC_DISP_DISP_SIGNAL_OPTIONS0_M1_ENABLE __BIT(26)
 143#define DC_DISP_DISP_SIGNAL_OPTIONS0_M0_ENABLE __BIT(24)
 144#define DC_DISP_DISP_SIGNAL_OPTIONS0_V_PULSE3_ENABLE __BIT(20)
 145#define DC_DISP_DISP_SIGNAL_OPTIONS0_V_PULSE2_ENABLE __BIT(19)
 146#define DC_DISP_DISP_SIGNAL_OPTIONS0_V_PULSE1_ENABLE __BIT(18)
 147#define DC_DISP_DISP_SIGNAL_OPTIONS0_V_PULSE0_ENABLE __BIT(16)
142#define DC_DISP_DISP_SIGNAL_OPTIONS0_H_PULSE2_ENABLE __BIT(12) 148#define DC_DISP_DISP_SIGNAL_OPTIONS0_H_PULSE2_ENABLE __BIT(12)
 149#define DC_DISP_DISP_SIGNAL_OPTIONS0_H_PULSE1_ENABLE __BIT(10)
 150#define DC_DISP_DISP_SIGNAL_OPTIONS0_H_PULSE0_ENABLE __BIT(8)
143 151
144#define DC_DISP_DISP_WIN_OPTIONS_REG 0x1008 152#define DC_DISP_DISP_WIN_OPTIONS_REG 0x1008
145#define DC_DISP_DISP_WIN_OPTIONS_HDMI_ENABLE __BIT(30) 153#define DC_DISP_DISP_WIN_OPTIONS_HDMI_ENABLE __BIT(30)
146#define DC_DISP_DISP_WIN_OPTIONS_DSI_ENABLE __BIT(29) 154#define DC_DISP_DISP_WIN_OPTIONS_DSI_ENABLE __BIT(29)
147#define DC_DISP_DISP_WIN_OPTIONS_SOR_ENABLE __BIT(28) 155#define DC_DISP_DISP_WIN_OPTIONS_SOR_ENABLE __BIT(25)
148#define DC_DISP_DISP_WIN_OPTIONS_CURSOR_ENABLE __BIT(16) 156#define DC_DISP_DISP_WIN_OPTIONS_CURSOR_ENABLE __BIT(16)
149 157
150#define DC_DISP_DISP_TIMING_OPTIONS_REG 0x1014 158#define DC_DISP_DISP_TIMING_OPTIONS_REG 0x1014
151#define DC_DISP_DISP_TIMING_OPTIONS_VSYNC_POS __BITS(11,0) 159#define DC_DISP_DISP_TIMING_OPTIONS_VSYNC_POS __BITS(11,0)
152 160
153#define DC_DISP_REF_TO_SYNC_REG 0x1018 161#define DC_DISP_REF_TO_SYNC_REG 0x1018
154#define DC_DISP_REF_TO_SYNC_V __BITS(28,16) 162#define DC_DISP_REF_TO_SYNC_V __BITS(28,16)
155#define DC_DISP_REF_TO_SYNC_H __BITS(12,0) 163#define DC_DISP_REF_TO_SYNC_H __BITS(12,0)
156 164
157#define DC_DISP_SYNC_WIDTH_REG 0x101c 165#define DC_DISP_SYNC_WIDTH_REG 0x101c
158#define DC_DISP_SYNC_WIDTH_V __BITS(28,16) 166#define DC_DISP_SYNC_WIDTH_V __BITS(28,16)
159#define DC_DISP_SYNC_WIDTH_H __BITS(12,0) 167#define DC_DISP_SYNC_WIDTH_H __BITS(12,0)
160 168
cvs diff -r1.2 -r1.3 src/sys/arch/arm/nvidia/tegra_hdmireg.h (expand / switch to unified diff)

--- src/sys/arch/arm/nvidia/tegra_hdmireg.h 2015/07/23 14:31:05 1.2
+++ src/sys/arch/arm/nvidia/tegra_hdmireg.h 2015/07/23 15:08:19 1.3
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: tegra_hdmireg.h,v 1.2 2015/07/23 14:31:05 jmcneill Exp $ */ 1/* $NetBSD: tegra_hdmireg.h,v 1.3 2015/07/23 15:08:19 skrll Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
@@ -206,27 +206,35 @@ @@ -206,27 +206,35 @@
206#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDB_3 __BIT(7) 206#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDB_3 __BIT(7)
207#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDB_2 __BIT(6) 207#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDB_2 __BIT(6)
208#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDB_1 __BIT(5) 208#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDB_1 __BIT(5)
209#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDB_0 __BIT(4) 209#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDB_0 __BIT(4)
210#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDA_3 __BIT(3) 210#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDA_3 __BIT(3)
211#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDA_2 __BIT(2) 211#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDA_2 __BIT(2)
212#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDA_1 __BIT(1) 212#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDA_1 __BIT(1)
213#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDA_0 __BIT(0) 213#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDA_0 __BIT(0)
214 214
215#define HDMI_NV_PDISP_SOR_LVDS_REG 0x16c 215#define HDMI_NV_PDISP_SOR_LVDS_REG 0x16c
216#define HDMI_NV_PDISP_SOR_CRCA_REG 0x170 216#define HDMI_NV_PDISP_SOR_CRCA_REG 0x170
217#define HDMI_NV_PDISP_SOR_CRCB_REG 0x174 217#define HDMI_NV_PDISP_SOR_CRCB_REG 0x174
218#define HDMI_NV_PDISP_SOR_BLANK_REG 0x178 218#define HDMI_NV_PDISP_SOR_BLANK_REG 0x178
 219
219#define HDMI_NV_PDISP_SOR_SEQ_CTL_REG 0x17c 220#define HDMI_NV_PDISP_SOR_SEQ_CTL_REG 0x17c
 221#define HDMI_NV_PDISP_SOR_SEQ_CTL_SWITCH __BIT(30)
 222#define HDMI_NV_PDISP_SOR_SEQ_CTL_STATUS __BIT(28)
 223#define HDMI_NV_PDISP_SOR_SEQ_CTL_PC __BITS(19,16)
 224#define HDMI_NV_PDISP_SOR_SEQ_CTL_PD_PC_ALT __BITS(15,12)
 225#define HDMI_NV_PDISP_SOR_SEQ_CTL_PD_PC __BITS(11,8)
 226#define HDMI_NV_PDISP_SOR_SEQ_CTL_PU_PC_ALT __BITS(7,4)
 227#define HDMI_NV_PDISP_SOR_SEQ_CTL_PU_PC __BITS(3,0)
220 228
221#define HDMI_NV_PDISP_SOR_SEQ_INST0_REG 0x180 229#define HDMI_NV_PDISP_SOR_SEQ_INST0_REG 0x180
222#define HDMI_NV_PDISP_SOR_SEQ_INST1_REG 0x184 230#define HDMI_NV_PDISP_SOR_SEQ_INST1_REG 0x184
223#define HDMI_NV_PDISP_SOR_SEQ_INST2_REG 0x188 231#define HDMI_NV_PDISP_SOR_SEQ_INST2_REG 0x188
224#define HDMI_NV_PDISP_SOR_SEQ_INST3_REG 0x18c 232#define HDMI_NV_PDISP_SOR_SEQ_INST3_REG 0x18c
225#define HDMI_NV_PDISP_SOR_SEQ_INST4_REG 0x190 233#define HDMI_NV_PDISP_SOR_SEQ_INST4_REG 0x190
226#define HDMI_NV_PDISP_SOR_SEQ_INST5_REG 0x194 234#define HDMI_NV_PDISP_SOR_SEQ_INST5_REG 0x194
227#define HDMI_NV_PDISP_SOR_SEQ_INST6_REG 0x198 235#define HDMI_NV_PDISP_SOR_SEQ_INST6_REG 0x198
228#define HDMI_NV_PDISP_SOR_SEQ_INST7_REG 0x19c 236#define HDMI_NV_PDISP_SOR_SEQ_INST7_REG 0x19c
229#define HDMI_NV_PDISP_SOR_SEQ_INST8_REG 0x1a0 237#define HDMI_NV_PDISP_SOR_SEQ_INST8_REG 0x1a0
230#define HDMI_NV_PDISP_SOR_SEQ_INST9_REG 0x1a4 238#define HDMI_NV_PDISP_SOR_SEQ_INST9_REG 0x1a4
231#define HDMI_NV_PDISP_SOR_SEQ_INSTA_REG 0x1a8 239#define HDMI_NV_PDISP_SOR_SEQ_INSTA_REG 0x1a8
232#define HDMI_NV_PDISP_SOR_SEQ_INSTB_REG 0x1ac 240#define HDMI_NV_PDISP_SOR_SEQ_INSTB_REG 0x1ac