| @@ -1,371 +1,374 @@ | | | @@ -1,371 +1,374 @@ |
1 | /* $NetBSD: a9tmr.c,v 1.13 2015/07/24 05:19:13 ryo Exp $ */ | | 1 | /* $NetBSD: a9tmr.c,v 1.14 2015/07/24 05:20:01 ryo Exp $ */ |
2 | | | 2 | |
3 | /*- | | 3 | /*- |
4 | * Copyright (c) 2012 The NetBSD Foundation, Inc. | | 4 | * Copyright (c) 2012 The NetBSD Foundation, Inc. |
5 | * All rights reserved. | | 5 | * All rights reserved. |
6 | * | | 6 | * |
7 | * This code is derived from software contributed to The NetBSD Foundation | | 7 | * This code is derived from software contributed to The NetBSD Foundation |
8 | * by Matt Thomas | | 8 | * by Matt Thomas |
9 | * | | 9 | * |
10 | * Redistribution and use in source and binary forms, with or without | | 10 | * Redistribution and use in source and binary forms, with or without |
11 | * modification, are permitted provided that the following conditions | | 11 | * modification, are permitted provided that the following conditions |
12 | * are met: | | 12 | * are met: |
13 | * 1. Redistributions of source code must retain the above copyright | | 13 | * 1. Redistributions of source code must retain the above copyright |
14 | * notice, this list of conditions and the following disclaimer. | | 14 | * notice, this list of conditions and the following disclaimer. |
15 | * 2. Redistributions in binary form must reproduce the above copyright | | 15 | * 2. Redistributions in binary form must reproduce the above copyright |
16 | * notice, this list of conditions and the following disclaimer in the | | 16 | * notice, this list of conditions and the following disclaimer in the |
17 | * documentation and/or other materials provided with the distribution. | | 17 | * documentation and/or other materials provided with the distribution. |
18 | * | | 18 | * |
19 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS | | 19 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
20 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED | | 20 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
21 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | | 21 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
22 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS | | 22 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
23 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | | 23 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | | 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | | 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | | 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | | 27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | | 28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
29 | * POSSIBILITY OF SUCH DAMAGE. | | 29 | * POSSIBILITY OF SUCH DAMAGE. |
30 | */ | | 30 | */ |
31 | | | 31 | |
32 | #include <sys/cdefs.h> | | 32 | #include <sys/cdefs.h> |
33 | __KERNEL_RCSID(0, "$NetBSD: a9tmr.c,v 1.13 2015/07/24 05:19:13 ryo Exp $"); | | 33 | __KERNEL_RCSID(0, "$NetBSD: a9tmr.c,v 1.14 2015/07/24 05:20:01 ryo Exp $"); |
34 | | | 34 | |
35 | #include <sys/param.h> | | 35 | #include <sys/param.h> |
36 | #include <sys/bus.h> | | 36 | #include <sys/bus.h> |
37 | #include <sys/device.h> | | 37 | #include <sys/device.h> |
38 | #include <sys/intr.h> | | 38 | #include <sys/intr.h> |
39 | #include <sys/kernel.h> | | 39 | #include <sys/kernel.h> |
40 | #include <sys/proc.h> | | 40 | #include <sys/proc.h> |
41 | #include <sys/systm.h> | | 41 | #include <sys/systm.h> |
42 | #include <sys/timetc.h> | | 42 | #include <sys/timetc.h> |
43 | #include <sys/xcall.h> | | 43 | #include <sys/xcall.h> |
44 | | | 44 | |
45 | #include <prop/proplib.h> | | 45 | #include <prop/proplib.h> |
46 | | | 46 | |
47 | #include <arm/cortex/a9tmr_reg.h> | | 47 | #include <arm/cortex/a9tmr_reg.h> |
48 | #include <arm/cortex/a9tmr_var.h> | | 48 | #include <arm/cortex/a9tmr_var.h> |
49 | | | 49 | |
50 | #include <arm/cortex/mpcore_var.h> | | 50 | #include <arm/cortex/mpcore_var.h> |
51 | | | 51 | |
52 | static int a9tmr_match(device_t, cfdata_t, void *); | | 52 | static int a9tmr_match(device_t, cfdata_t, void *); |
53 | static void a9tmr_attach(device_t, device_t, void *); | | 53 | static void a9tmr_attach(device_t, device_t, void *); |
54 | | | 54 | |
55 | static int clockhandler(void *); | | 55 | static int clockhandler(void *); |
56 | | | 56 | |
57 | static u_int a9tmr_get_timecount(struct timecounter *); | | 57 | static u_int a9tmr_get_timecount(struct timecounter *); |
58 | | | 58 | |
59 | static struct a9tmr_softc a9tmr_sc; | | 59 | static struct a9tmr_softc a9tmr_sc; |
60 | | | 60 | |
61 | static struct timecounter a9tmr_timecounter = { | | 61 | static struct timecounter a9tmr_timecounter = { |
62 | .tc_get_timecount = a9tmr_get_timecount, | | 62 | .tc_get_timecount = a9tmr_get_timecount, |
63 | .tc_poll_pps = 0, | | 63 | .tc_poll_pps = 0, |
64 | .tc_counter_mask = ~0u, | | 64 | .tc_counter_mask = ~0u, |
65 | .tc_frequency = 0, /* set by cpu_initclocks() */ | | 65 | .tc_frequency = 0, /* set by cpu_initclocks() */ |
66 | .tc_name = NULL, /* set by attach */ | | 66 | .tc_name = NULL, /* set by attach */ |
67 | .tc_quality = 500, | | 67 | .tc_quality = 500, |
68 | .tc_priv = &a9tmr_sc, | | 68 | .tc_priv = &a9tmr_sc, |
69 | .tc_next = NULL, | | 69 | .tc_next = NULL, |
70 | }; | | 70 | }; |
71 | | | 71 | |
72 | CFATTACH_DECL_NEW(a9tmr, 0, a9tmr_match, a9tmr_attach, NULL, NULL); | | 72 | CFATTACH_DECL_NEW(a9tmr, 0, a9tmr_match, a9tmr_attach, NULL, NULL); |
73 | | | 73 | |
74 | static inline uint32_t | | 74 | static inline uint32_t |
75 | a9tmr_global_read(struct a9tmr_softc *sc, bus_size_t o) | | 75 | a9tmr_global_read(struct a9tmr_softc *sc, bus_size_t o) |
76 | { | | 76 | { |
77 | return bus_space_read_4(sc->sc_memt, sc->sc_global_memh, o); | | 77 | return bus_space_read_4(sc->sc_memt, sc->sc_global_memh, o); |
78 | } | | 78 | } |
79 | | | 79 | |
80 | static inline void | | 80 | static inline void |
81 | a9tmr_global_write(struct a9tmr_softc *sc, bus_size_t o, uint32_t v) | | 81 | a9tmr_global_write(struct a9tmr_softc *sc, bus_size_t o, uint32_t v) |
82 | { | | 82 | { |
83 | bus_space_write_4(sc->sc_memt, sc->sc_global_memh, o, v); | | 83 | bus_space_write_4(sc->sc_memt, sc->sc_global_memh, o, v); |
84 | } | | 84 | } |
85 | | | 85 | |
86 | | | 86 | |
87 | /* ARGSUSED */ | | 87 | /* ARGSUSED */ |
88 | static int | | 88 | static int |
89 | a9tmr_match(device_t parent, cfdata_t cf, void *aux) | | 89 | a9tmr_match(device_t parent, cfdata_t cf, void *aux) |
90 | { | | 90 | { |
91 | struct mpcore_attach_args * const mpcaa = aux; | | 91 | struct mpcore_attach_args * const mpcaa = aux; |
92 | | | 92 | |
93 | if (a9tmr_sc.sc_dev != NULL) | | 93 | if (a9tmr_sc.sc_dev != NULL) |
94 | return 0; | | 94 | return 0; |
95 | | | 95 | |
96 | if ((armreg_pfr1_read() & ARM_PFR1_GTIMER_MASK) != 0) | | 96 | if ((armreg_pfr1_read() & ARM_PFR1_GTIMER_MASK) != 0) |
97 | return 0; | | 97 | return 0; |
98 | | | 98 | |
99 | if (!CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid) && | | 99 | if (!CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid) && |
100 | !CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid)) | | 100 | !CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid)) |
101 | return 0; | | 101 | return 0; |
102 | | | 102 | |
103 | if (strcmp(mpcaa->mpcaa_name, cf->cf_name) != 0) | | 103 | if (strcmp(mpcaa->mpcaa_name, cf->cf_name) != 0) |
104 | return 0; | | 104 | return 0; |
105 | | | 105 | |
106 | /* | | 106 | /* |
107 | * This isn't present on UP A9s (since CBAR isn't present). | | 107 | * This isn't present on UP A9s (since CBAR isn't present). |
108 | */ | | 108 | */ |
109 | uint32_t mpidr = armreg_mpidr_read(); | | 109 | uint32_t mpidr = armreg_mpidr_read(); |
110 | if (mpidr == 0 || (mpidr & MPIDR_U)) | | 110 | if (mpidr == 0 || (mpidr & MPIDR_U)) |
111 | return 0; | | 111 | return 0; |
112 | | | 112 | |
113 | return 1; | | 113 | return 1; |
114 | } | | 114 | } |
115 | | | 115 | |
116 | static void | | 116 | static void |
117 | a9tmr_attach(device_t parent, device_t self, void *aux) | | 117 | a9tmr_attach(device_t parent, device_t self, void *aux) |
118 | { | | 118 | { |
119 | struct a9tmr_softc *sc = &a9tmr_sc; | | 119 | struct a9tmr_softc *sc = &a9tmr_sc; |
120 | struct mpcore_attach_args * const mpcaa = aux; | | 120 | struct mpcore_attach_args * const mpcaa = aux; |
121 | prop_dictionary_t dict = device_properties(self); | | 121 | prop_dictionary_t dict = device_properties(self); |
122 | char freqbuf[sizeof("XXX SHz")]; | | 122 | char freqbuf[sizeof("XXX SHz")]; |
123 | const char *cpu_type; | | 123 | const char *cpu_type; |
124 | | | 124 | |
125 | /* | | 125 | /* |
126 | * This runs at the ARM PERIPHCLOCK which should be 1/2 of the CPU clock. | | 126 | * This runs at the ARM PERIPHCLOCK which should be 1/2 of the CPU clock. |
127 | * The MD code should have setup our frequency for us. | | 127 | * The MD code should have setup our frequency for us. |
128 | */ | | 128 | */ |
129 | prop_dictionary_get_uint32(dict, "frequency", &sc->sc_freq); | | 129 | prop_dictionary_get_uint32(dict, "frequency", &sc->sc_freq); |
130 | | | 130 | |
131 | humanize_number(freqbuf, sizeof(freqbuf), sc->sc_freq, "Hz", 1000); | | 131 | humanize_number(freqbuf, sizeof(freqbuf), sc->sc_freq, "Hz", 1000); |
132 | | | 132 | |
133 | aprint_naive("\n"); | | 133 | aprint_naive("\n"); |
134 | if (CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid)) { | | 134 | if (CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid)) { |
135 | cpu_type = "A5"; | | 135 | cpu_type = "A5"; |
136 | } else { | | 136 | } else { |
137 | cpu_type = "A9"; | | 137 | cpu_type = "A9"; |
138 | } | | 138 | } |
139 | aprint_normal(": %s Global 64-bit Timer (%s)\n", cpu_type, freqbuf); | | 139 | aprint_normal(": %s Global 64-bit Timer (%s)\n", cpu_type, freqbuf); |
140 | | | 140 | |
141 | self->dv_private = sc; | | 141 | self->dv_private = sc; |
142 | sc->sc_dev = self; | | 142 | sc->sc_dev = self; |
143 | sc->sc_memt = mpcaa->mpcaa_memt; | | 143 | sc->sc_memt = mpcaa->mpcaa_memt; |
144 | sc->sc_memh = mpcaa->mpcaa_memh; | | 144 | sc->sc_memh = mpcaa->mpcaa_memh; |
145 | | | 145 | |
146 | evcnt_attach_dynamic(&sc->sc_ev_missing_ticks, EVCNT_TYPE_MISC, NULL, | | 146 | evcnt_attach_dynamic(&sc->sc_ev_missing_ticks, EVCNT_TYPE_MISC, NULL, |
147 | device_xname(self), "missing interrupts"); | | 147 | device_xname(self), "missing interrupts"); |
148 | | | 148 | |
149 | bus_space_subregion(sc->sc_memt, sc->sc_memh, | | 149 | bus_space_subregion(sc->sc_memt, sc->sc_memh, |
150 | TMR_GLOBAL_BASE, TMR_GLOBAL_SIZE, &sc->sc_global_memh); | | 150 | TMR_GLOBAL_BASE, TMR_GLOBAL_SIZE, &sc->sc_global_memh); |
151 | bus_space_subregion(sc->sc_memt, sc->sc_memh, | | 151 | bus_space_subregion(sc->sc_memt, sc->sc_memh, |
152 | TMR_PRIVATE_BASE, TMR_PRIVATE_SIZE, &sc->sc_private_memh); | | 152 | TMR_PRIVATE_BASE, TMR_PRIVATE_SIZE, &sc->sc_private_memh); |
153 | bus_space_subregion(sc->sc_memt, sc->sc_memh, | | 153 | bus_space_subregion(sc->sc_memt, sc->sc_memh, |
154 | TMR_WDOG_BASE, TMR_WDOG_SIZE, &sc->sc_wdog_memh); | | 154 | TMR_WDOG_BASE, TMR_WDOG_SIZE, &sc->sc_wdog_memh); |
155 | | | 155 | |
156 | sc->sc_global_ih = intr_establish(IRQ_A9TMR_PPI_GTIMER, IPL_CLOCK, | | 156 | sc->sc_global_ih = intr_establish(IRQ_A9TMR_PPI_GTIMER, IPL_CLOCK, |
157 | IST_EDGE | IST_MPSAFE, clockhandler, NULL); | | 157 | IST_EDGE | IST_MPSAFE, clockhandler, NULL); |
158 | if (sc->sc_global_ih == NULL) | | 158 | if (sc->sc_global_ih == NULL) |
159 | panic("%s: unable to register timer interrupt", __func__); | | 159 | panic("%s: unable to register timer interrupt", __func__); |
160 | aprint_normal_dev(sc->sc_dev, "interrupting on irq %d\n", | | 160 | aprint_normal_dev(sc->sc_dev, "interrupting on irq %d\n", |
161 | IRQ_A9TMR_PPI_GTIMER); | | 161 | IRQ_A9TMR_PPI_GTIMER); |
162 | } | | 162 | } |
163 | | | 163 | |
164 | static inline uint64_t | | 164 | static inline uint64_t |
165 | a9tmr_gettime(struct a9tmr_softc *sc) | | 165 | a9tmr_gettime(struct a9tmr_softc *sc) |
166 | { | | 166 | { |
167 | uint32_t lo, hi; | | 167 | uint32_t lo, hi; |
168 | | | 168 | |
169 | do { | | 169 | do { |
170 | hi = a9tmr_global_read(sc, TMR_GBL_CTR_U); | | 170 | hi = a9tmr_global_read(sc, TMR_GBL_CTR_U); |
171 | lo = a9tmr_global_read(sc, TMR_GBL_CTR_L); | | 171 | lo = a9tmr_global_read(sc, TMR_GBL_CTR_L); |
172 | } while (hi != a9tmr_global_read(sc, TMR_GBL_CTR_U)); | | 172 | } while (hi != a9tmr_global_read(sc, TMR_GBL_CTR_U)); |
173 | | | 173 | |
174 | return ((uint64_t)hi << 32) | lo; | | 174 | return ((uint64_t)hi << 32) | lo; |
175 | } | | 175 | } |
176 | | | 176 | |
177 | void | | 177 | void |
178 | a9tmr_init_cpu_clock(struct cpu_info *ci) | | 178 | a9tmr_init_cpu_clock(struct cpu_info *ci) |
179 | { | | 179 | { |
180 | struct a9tmr_softc * const sc = &a9tmr_sc; | | 180 | struct a9tmr_softc * const sc = &a9tmr_sc; |
181 | uint64_t now = a9tmr_gettime(sc); | | 181 | uint64_t now = a9tmr_gettime(sc); |
182 | | | 182 | |
183 | KASSERT(ci == curcpu()); | | 183 | KASSERT(ci == curcpu()); |
184 | | | 184 | |
185 | ci->ci_lastintr = now; | | 185 | ci->ci_lastintr = now; |
186 | | | 186 | |
187 | a9tmr_global_write(sc, TMR_GBL_AUTOINC, sc->sc_autoinc); | | 187 | a9tmr_global_write(sc, TMR_GBL_AUTOINC, sc->sc_autoinc); |
188 | | | 188 | |
189 | /* | | 189 | /* |
190 | * To update the compare register we have to disable comparisions first. | | 190 | * To update the compare register we have to disable comparisions first. |
191 | */ | | 191 | */ |
192 | uint32_t ctl = a9tmr_global_read(sc, TMR_GBL_CTL); | | 192 | uint32_t ctl = a9tmr_global_read(sc, TMR_GBL_CTL); |
193 | if (ctl & TMR_GBL_CTL_CMP_ENABLE) { | | 193 | if (ctl & TMR_GBL_CTL_CMP_ENABLE) { |
194 | a9tmr_global_write(sc, TMR_GBL_CTL, ctl & ~TMR_GBL_CTL_CMP_ENABLE); | | 194 | a9tmr_global_write(sc, TMR_GBL_CTL, |
| | | 195 | ctl & ~TMR_GBL_CTL_CMP_ENABLE); |
195 | } | | 196 | } |
196 | | | 197 | |
197 | /* | | 198 | /* |
198 | * Schedule the next interrupt. | | 199 | * Schedule the next interrupt. |
199 | */ | | 200 | */ |
200 | now += sc->sc_autoinc; | | 201 | now += sc->sc_autoinc; |
201 | a9tmr_global_write(sc, TMR_GBL_CMP_L, (uint32_t) now); | | 202 | a9tmr_global_write(sc, TMR_GBL_CMP_L, (uint32_t) now); |
202 | a9tmr_global_write(sc, TMR_GBL_CMP_H, (uint32_t) (now >> 32)); | | 203 | a9tmr_global_write(sc, TMR_GBL_CMP_H, (uint32_t) (now >> 32)); |
203 | | | 204 | |
204 | /* | | 205 | /* |
205 | * Re-enable the comparator and now enable interrupts. | | 206 | * Re-enable the comparator and now enable interrupts. |
206 | */ | | 207 | */ |
207 | a9tmr_global_write(sc, TMR_GBL_INT, 1); /* clear interrupt pending */ | | 208 | a9tmr_global_write(sc, TMR_GBL_INT, 1); /* clear interrupt pending */ |
208 | ctl |= TMR_GBL_CTL_CMP_ENABLE | TMR_GBL_CTL_INT_ENABLE | TMR_GBL_CTL_AUTO_INC | TMR_CTL_ENABLE; | | 209 | ctl |= TMR_GBL_CTL_CMP_ENABLE | TMR_GBL_CTL_INT_ENABLE | |
| | | 210 | TMR_GBL_CTL_AUTO_INC | TMR_CTL_ENABLE; |
209 | a9tmr_global_write(sc, TMR_GBL_CTL, ctl); | | 211 | a9tmr_global_write(sc, TMR_GBL_CTL, ctl); |
210 | #if 0 | | 212 | #if 0 |
211 | printf("%s: %s: ctl %#x autoinc %u cmp %#x%08x now %#"PRIx64"\n", | | 213 | printf("%s: %s: ctl %#x autoinc %u cmp %#x%08x now %#"PRIx64"\n", |
212 | __func__, ci->ci_data.cpu_name, | | 214 | __func__, ci->ci_data.cpu_name, |
213 | a9tmr_global_read(sc, TMR_GBL_CTL), | | 215 | a9tmr_global_read(sc, TMR_GBL_CTL), |
214 | a9tmr_global_read(sc, TMR_GBL_AUTOINC), | | 216 | a9tmr_global_read(sc, TMR_GBL_AUTOINC), |
215 | a9tmr_global_read(sc, TMR_GBL_CMP_H), | | 217 | a9tmr_global_read(sc, TMR_GBL_CMP_H), |
216 | a9tmr_global_read(sc, TMR_GBL_CMP_L), | | 218 | a9tmr_global_read(sc, TMR_GBL_CMP_L), |
217 | a9tmr_gettime(sc)); | | 219 | a9tmr_gettime(sc)); |
218 | | | 220 | |
219 | int s = splsched(); | | 221 | int s = splsched(); |
220 | uint64_t when = now; | | 222 | uint64_t when = now; |
221 | u_int n = 0; | | 223 | u_int n = 0; |
222 | while ((now = a9tmr_gettime(sc)) < when) { | | 224 | while ((now = a9tmr_gettime(sc)) < when) { |
223 | /* spin */ | | 225 | /* spin */ |
224 | n++; | | 226 | n++; |
225 | KASSERTMSG(n <= sc->sc_autoinc, | | 227 | KASSERTMSG(n <= sc->sc_autoinc, |
226 | "spun %u times but only %"PRIu64" has passed", | | 228 | "spun %u times but only %"PRIu64" has passed", |
227 | n, when - now); | | 229 | n, when - now); |
228 | } | | 230 | } |
229 | printf("%s: %s: status %#x cmp %#x%08x now %#"PRIx64"\n", | | 231 | printf("%s: %s: status %#x cmp %#x%08x now %#"PRIx64"\n", |
230 | __func__, ci->ci_data.cpu_name, | | 232 | __func__, ci->ci_data.cpu_name, |
231 | a9tmr_global_read(sc, TMR_GBL_INT), | | 233 | a9tmr_global_read(sc, TMR_GBL_INT), |
232 | a9tmr_global_read(sc, TMR_GBL_CMP_H), | | 234 | a9tmr_global_read(sc, TMR_GBL_CMP_H), |
233 | a9tmr_global_read(sc, TMR_GBL_CMP_L), | | 235 | a9tmr_global_read(sc, TMR_GBL_CMP_L), |
234 | a9tmr_gettime(sc)); | | 236 | a9tmr_gettime(sc)); |
235 | splx(s); | | 237 | splx(s); |
236 | #elif 0 | | 238 | #elif 0 |
237 | delay(1000000 / hz + 1000); | | 239 | delay(1000000 / hz + 1000); |
238 | #endif | | 240 | #endif |
239 | } | | 241 | } |
240 | | | 242 | |
241 | void | | 243 | void |
242 | cpu_initclocks(void) | | 244 | cpu_initclocks(void) |
243 | { | | 245 | { |
244 | struct a9tmr_softc * const sc = &a9tmr_sc; | | 246 | struct a9tmr_softc * const sc = &a9tmr_sc; |
245 | | | 247 | |
246 | KASSERT(sc->sc_dev != NULL); | | 248 | KASSERT(sc->sc_dev != NULL); |
247 | KASSERT(sc->sc_freq != 0); | | 249 | KASSERT(sc->sc_freq != 0); |
248 | | | 250 | |
249 | sc->sc_autoinc = sc->sc_freq / hz; | | 251 | sc->sc_autoinc = sc->sc_freq / hz; |
250 | | | 252 | |
251 | a9tmr_init_cpu_clock(curcpu()); | | 253 | a9tmr_init_cpu_clock(curcpu()); |
252 | | | 254 | |
253 | a9tmr_timecounter.tc_name = device_xname(sc->sc_dev); | | 255 | a9tmr_timecounter.tc_name = device_xname(sc->sc_dev); |
254 | a9tmr_timecounter.tc_frequency = sc->sc_freq; | | 256 | a9tmr_timecounter.tc_frequency = sc->sc_freq; |
255 | | | 257 | |
256 | tc_init(&a9tmr_timecounter); | | 258 | tc_init(&a9tmr_timecounter); |
257 | } | | 259 | } |
258 | | | 260 | |
259 | static void | | 261 | static void |
260 | a9tmr_update_freq_cb(void *arg1, void *arg2) | | 262 | a9tmr_update_freq_cb(void *arg1, void *arg2) |
261 | { | | 263 | { |
262 | a9tmr_init_cpu_clock(curcpu()); | | 264 | a9tmr_init_cpu_clock(curcpu()); |
263 | } | | 265 | } |
264 | | | 266 | |
265 | void | | 267 | void |
266 | a9tmr_update_freq(uint32_t freq) | | 268 | a9tmr_update_freq(uint32_t freq) |
267 | { | | 269 | { |
268 | struct a9tmr_softc * const sc = &a9tmr_sc; | | 270 | struct a9tmr_softc * const sc = &a9tmr_sc; |
269 | uint64_t xc; | | 271 | uint64_t xc; |
270 | | | 272 | |
271 | KASSERT(sc->sc_dev != NULL); | | 273 | KASSERT(sc->sc_dev != NULL); |
272 | KASSERT(freq != 0); | | 274 | KASSERT(freq != 0); |
273 | | | 275 | |
274 | tc_detach(&a9tmr_timecounter); | | 276 | tc_detach(&a9tmr_timecounter); |
275 | | | 277 | |
276 | sc->sc_freq = freq; | | 278 | sc->sc_freq = freq; |
277 | sc->sc_autoinc = sc->sc_freq / hz; | | 279 | sc->sc_autoinc = sc->sc_freq / hz; |
278 | | | 280 | |
279 | xc = xc_broadcast(0, a9tmr_update_freq_cb, NULL, NULL); | | 281 | xc = xc_broadcast(0, a9tmr_update_freq_cb, NULL, NULL); |
280 | xc_wait(xc); | | 282 | xc_wait(xc); |
281 | | | 283 | |
282 | a9tmr_timecounter.tc_frequency = sc->sc_freq; | | 284 | a9tmr_timecounter.tc_frequency = sc->sc_freq; |
283 | tc_init(&a9tmr_timecounter); | | 285 | tc_init(&a9tmr_timecounter); |
284 | } | | 286 | } |
285 | | | 287 | |
286 | void | | 288 | void |
287 | a9tmr_delay(unsigned int n) | | 289 | a9tmr_delay(unsigned int n) |
288 | { | | 290 | { |
289 | struct a9tmr_softc * const sc = &a9tmr_sc; | | 291 | struct a9tmr_softc * const sc = &a9tmr_sc; |
290 | | | 292 | |
291 | KASSERT(sc != NULL); | | 293 | KASSERT(sc != NULL); |
292 | | | 294 | |
293 | uint32_t freq = sc->sc_freq ? sc->sc_freq : curcpu()->ci_data.cpu_cc_freq / 2; | | 295 | uint32_t freq = sc->sc_freq ? sc->sc_freq : |
| | | 296 | curcpu()->ci_data.cpu_cc_freq / 2; |
294 | KASSERT(freq != 0); | | 297 | KASSERT(freq != 0); |
295 | | | 298 | |
296 | /* | | 299 | /* |
297 | * not quite divide by 1000000 but close enough | | 300 | * not quite divide by 1000000 but close enough |
298 | * (higher by 1.3% which means we wait 1.3% longer). | | 301 | * (higher by 1.3% which means we wait 1.3% longer). |
299 | */ | | 302 | */ |
300 | const uint64_t incr_per_us = (freq >> 20) + (freq >> 24); | | 303 | const uint64_t incr_per_us = (freq >> 20) + (freq >> 24); |
301 | | | 304 | |
302 | const uint64_t delta = n * incr_per_us; | | 305 | const uint64_t delta = n * incr_per_us; |
303 | const uint64_t base = a9tmr_gettime(sc); | | 306 | const uint64_t base = a9tmr_gettime(sc); |
304 | const uint64_t finish = base + delta; | | 307 | const uint64_t finish = base + delta; |
305 | | | 308 | |
306 | while (a9tmr_gettime(sc) < finish) { | | 309 | while (a9tmr_gettime(sc) < finish) { |
307 | /* spin */ | | 310 | /* spin */ |
308 | } | | 311 | } |
309 | } | | 312 | } |
310 | | | 313 | |
311 | /* | | 314 | /* |
312 | * clockhandler: | | 315 | * clockhandler: |
313 | * | | 316 | * |
314 | * Handle the hardclock interrupt. | | 317 | * Handle the hardclock interrupt. |
315 | */ | | 318 | */ |
316 | static int | | 319 | static int |
317 | clockhandler(void *arg) | | 320 | clockhandler(void *arg) |
318 | { | | 321 | { |
319 | struct clockframe * const cf = arg; | | 322 | struct clockframe * const cf = arg; |
320 | struct a9tmr_softc * const sc = &a9tmr_sc; | | 323 | struct a9tmr_softc * const sc = &a9tmr_sc; |
321 | struct cpu_info * const ci = curcpu(); | | 324 | struct cpu_info * const ci = curcpu(); |
322 | | | 325 | |
323 | const uint64_t now = a9tmr_gettime(sc); | | 326 | const uint64_t now = a9tmr_gettime(sc); |
324 | uint64_t delta = now - ci->ci_lastintr; | | 327 | uint64_t delta = now - ci->ci_lastintr; |
325 | | | 328 | |
326 | a9tmr_global_write(sc, TMR_GBL_INT, 1); // Ack the interrupt | | 329 | a9tmr_global_write(sc, TMR_GBL_INT, 1); /* Ack the interrupt */ |
327 | | | 330 | |
328 | #if 0 | | 331 | #if 0 |
329 | printf("%s(%p): %s: now %#"PRIx64" delta %"PRIu64"\n", | | 332 | printf("%s(%p): %s: now %#"PRIx64" delta %"PRIu64"\n", |
330 | __func__, cf, ci->ci_data.cpu_name, now, delta); | | 333 | __func__, cf, ci->ci_data.cpu_name, now, delta); |
331 | #endif | | 334 | #endif |
332 | KASSERTMSG(delta > sc->sc_autoinc / 64, | | 335 | KASSERTMSG(delta > sc->sc_autoinc / 64, |
333 | "%s: interrupting too quickly (delta=%"PRIu64")", | | 336 | "%s: interrupting too quickly (delta=%"PRIu64")", |
334 | ci->ci_data.cpu_name, delta); | | 337 | ci->ci_data.cpu_name, delta); |
335 | | | 338 | |
336 | ci->ci_lastintr = now; | | 339 | ci->ci_lastintr = now; |
337 | | | 340 | |
338 | hardclock(cf); | | 341 | hardclock(cf); |
339 | | | 342 | |
340 | if (delta > sc->sc_autoinc) { | | 343 | if (delta > sc->sc_autoinc) { |
341 | u_int ticks = hz; | | 344 | u_int ticks = hz; |
342 | for (delta -= sc->sc_autoinc; | | 345 | for (delta -= sc->sc_autoinc; |
343 | delta >= sc->sc_autoinc && ticks > 0; | | 346 | delta >= sc->sc_autoinc && ticks > 0; |
344 | delta -= sc->sc_autoinc, ticks--) { | | 347 | delta -= sc->sc_autoinc, ticks--) { |
345 | #if 0 | | 348 | #if 0 |
346 | /* | | 349 | /* |
347 | * Try to make up up to a seconds amount of | | 350 | * Try to make up up to a seconds amount of |
348 | * missed clock interrupts | | 351 | * missed clock interrupts |
349 | */ | | 352 | */ |
350 | hardclock(cf); | | 353 | hardclock(cf); |
351 | #else | | 354 | #else |
352 | sc->sc_ev_missing_ticks.ev_count++; | | 355 | sc->sc_ev_missing_ticks.ev_count++; |
353 | #endif | | 356 | #endif |
354 | } | | 357 | } |
355 | } | | 358 | } |
356 | | | 359 | |
357 | return 1; | | 360 | return 1; |
358 | } | | 361 | } |
359 | | | 362 | |
360 | void | | 363 | void |
361 | setstatclockrate(int newhz) | | 364 | setstatclockrate(int newhz) |
362 | { | | 365 | { |
363 | } | | 366 | } |
364 | | | 367 | |
365 | static u_int | | 368 | static u_int |
366 | a9tmr_get_timecount(struct timecounter *tc) | | 369 | a9tmr_get_timecount(struct timecounter *tc) |
367 | { | | 370 | { |
368 | struct a9tmr_softc * const sc = tc->tc_priv; | | 371 | struct a9tmr_softc * const sc = tc->tc_priv; |
369 | | | 372 | |
370 | return (u_int) (a9tmr_gettime(sc)); | | 373 | return (u_int) (a9tmr_gettime(sc)); |
371 | } | | 374 | } |