Sat Jul 25 15:50:42 2015 UTC ()
Add HDMI audio support


(jmcneill)
diff -r1.23 -r1.24 src/sys/arch/arm/nvidia/tegra_car.c
diff -r1.19 -r1.20 src/sys/arch/arm/nvidia/tegra_carreg.h
diff -r1.5 -r1.6 src/sys/arch/arm/nvidia/tegra_hdmi.c
diff -r1.3 -r1.4 src/sys/arch/arm/nvidia/tegra_hdmireg.h
cvs diff -r1.23 -r1.24 src/sys/arch/arm/nvidia/Attic/tegra_car.c (switch to unified diff)

--- src/sys/arch/arm/nvidia/Attic/tegra_car.c 2015/07/23 18:22:05 1.23
+++ src/sys/arch/arm/nvidia/Attic/tegra_car.c 2015/07/25 15:50:42 1.24
@@ -1,818 +1,821 @@ @@ -1,818 +1,821 @@
1/* $NetBSD: tegra_car.c,v 1.23 2015/07/23 18:22:05 jmcneill Exp $ */ 1/* $NetBSD: tegra_car.c,v 1.24 2015/07/25 15:50:42 jmcneill Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
15 * 15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE. 26 * SUCH DAMAGE.
27 */ 27 */
28 28
29#include "locators.h" 29#include "locators.h"
30 30
31#include <sys/cdefs.h> 31#include <sys/cdefs.h>
32__KERNEL_RCSID(0, "$NetBSD: tegra_car.c,v 1.23 2015/07/23 18:22:05 jmcneill Exp $"); 32__KERNEL_RCSID(0, "$NetBSD: tegra_car.c,v 1.24 2015/07/25 15:50:42 jmcneill Exp $");
33 33
34#include <sys/param.h> 34#include <sys/param.h>
35#include <sys/bus.h> 35#include <sys/bus.h>
36#include <sys/device.h> 36#include <sys/device.h>
37#include <sys/intr.h> 37#include <sys/intr.h>
38#include <sys/systm.h> 38#include <sys/systm.h>
39#include <sys/kernel.h> 39#include <sys/kernel.h>
40#include <sys/rndpool.h> 40#include <sys/rndpool.h>
41#include <sys/rndsource.h> 41#include <sys/rndsource.h>
42 42
43#include <arm/nvidia/tegra_reg.h> 43#include <arm/nvidia/tegra_reg.h>
44#include <arm/nvidia/tegra_carreg.h> 44#include <arm/nvidia/tegra_carreg.h>
45#include <arm/nvidia/tegra_pmcreg.h> 45#include <arm/nvidia/tegra_pmcreg.h>
46#include <arm/nvidia/tegra_var.h> 46#include <arm/nvidia/tegra_var.h>
47 47
48static int tegra_car_match(device_t, cfdata_t, void *); 48static int tegra_car_match(device_t, cfdata_t, void *);
49static void tegra_car_attach(device_t, device_t, void *); 49static void tegra_car_attach(device_t, device_t, void *);
50 50
51struct tegra_car_softc { 51struct tegra_car_softc {
52 device_t sc_dev; 52 device_t sc_dev;
53 bus_space_tag_t sc_bst; 53 bus_space_tag_t sc_bst;
54 bus_space_handle_t sc_bsh; 54 bus_space_handle_t sc_bsh;
55 55
56 kmutex_t sc_intr_lock; 56 kmutex_t sc_intr_lock;
57 kmutex_t sc_rnd_lock; 57 kmutex_t sc_rnd_lock;
58 u_int sc_bytes_wanted; 58 u_int sc_bytes_wanted;
59 void *sc_sih; 59 void *sc_sih;
60 krndsource_t sc_rndsource; 60 krndsource_t sc_rndsource;
61}; 61};
62 62
63static void tegra_car_init(struct tegra_car_softc *); 63static void tegra_car_init(struct tegra_car_softc *);
64static void tegra_car_rnd_attach(device_t); 64static void tegra_car_rnd_attach(device_t);
65static void tegra_car_rnd_intr(void *); 65static void tegra_car_rnd_intr(void *);
66static void tegra_car_rnd_callback(size_t, void *); 66static void tegra_car_rnd_callback(size_t, void *);
67 67
68static struct tegra_car_softc *pmc_softc = NULL; 68static struct tegra_car_softc *pmc_softc = NULL;
69 69
70CFATTACH_DECL_NEW(tegra_car, sizeof(struct tegra_car_softc), 70CFATTACH_DECL_NEW(tegra_car, sizeof(struct tegra_car_softc),
71 tegra_car_match, tegra_car_attach, NULL, NULL); 71 tegra_car_match, tegra_car_attach, NULL, NULL);
72 72
73static int 73static int
74tegra_car_match(device_t parent, cfdata_t cf, void *aux) 74tegra_car_match(device_t parent, cfdata_t cf, void *aux)
75{ 75{
76 return 1; 76 return 1;
77} 77}
78 78
79static void 79static void
80tegra_car_attach(device_t parent, device_t self, void *aux) 80tegra_car_attach(device_t parent, device_t self, void *aux)
81{ 81{
82 struct tegra_car_softc * const sc = device_private(self); 82 struct tegra_car_softc * const sc = device_private(self);
83 struct tegraio_attach_args * const tio = aux; 83 struct tegraio_attach_args * const tio = aux;
84 const struct tegra_locators * const loc = &tio->tio_loc; 84 const struct tegra_locators * const loc = &tio->tio_loc;
85 85
86 sc->sc_dev = self; 86 sc->sc_dev = self;
87 sc->sc_bst = tio->tio_bst; 87 sc->sc_bst = tio->tio_bst;
88 bus_space_subregion(tio->tio_bst, tio->tio_bsh, 88 bus_space_subregion(tio->tio_bst, tio->tio_bsh,
89 loc->loc_offset, loc->loc_size, &sc->sc_bsh); 89 loc->loc_offset, loc->loc_size, &sc->sc_bsh);
90 90
91 KASSERT(pmc_softc == NULL); 91 KASSERT(pmc_softc == NULL);
92 pmc_softc = sc; 92 pmc_softc = sc;
93 93
94 aprint_naive("\n"); 94 aprint_naive("\n");
95 aprint_normal(": CAR\n"); 95 aprint_normal(": CAR\n");
96 96
97 tegra_car_init(sc); 97 tegra_car_init(sc);
98 98
99 aprint_verbose_dev(self, "PLLX = %u Hz\n", tegra_car_pllx_rate()); 99 aprint_verbose_dev(self, "PLLX = %u Hz\n", tegra_car_pllx_rate());
100 aprint_verbose_dev(self, "PLLC = %u Hz\n", tegra_car_pllc_rate()); 100 aprint_verbose_dev(self, "PLLC = %u Hz\n", tegra_car_pllc_rate());
101 aprint_verbose_dev(self, "PLLE = %u Hz\n", tegra_car_plle_rate()); 101 aprint_verbose_dev(self, "PLLE = %u Hz\n", tegra_car_plle_rate());
102 aprint_verbose_dev(self, "PLLU = %u Hz\n", tegra_car_pllu_rate()); 102 aprint_verbose_dev(self, "PLLU = %u Hz\n", tegra_car_pllu_rate());
103 aprint_verbose_dev(self, "PLLP0 = %u Hz\n", tegra_car_pllp0_rate()); 103 aprint_verbose_dev(self, "PLLP0 = %u Hz\n", tegra_car_pllp0_rate());
104 aprint_verbose_dev(self, "PLLD2 = %u Hz\n", tegra_car_plld2_rate()); 104 aprint_verbose_dev(self, "PLLD2 = %u Hz\n", tegra_car_plld2_rate());
105 105
106 config_interrupts(self, tegra_car_rnd_attach); 106 config_interrupts(self, tegra_car_rnd_attach);
107} 107}
108 108
109static void 109static void
110tegra_car_init(struct tegra_car_softc *sc) 110tegra_car_init(struct tegra_car_softc *sc)
111{ 111{
112 bus_space_tag_t bst = sc->sc_bst; 112 bus_space_tag_t bst = sc->sc_bst;
113 bus_space_handle_t bsh = sc->sc_bsh; 113 bus_space_handle_t bsh = sc->sc_bsh;
114 114
115 tegra_reg_set_clear(bst, bsh, CAR_PLLD2_BASE_REG, 115 tegra_reg_set_clear(bst, bsh, CAR_PLLD2_BASE_REG,
116 __SHIFTIN(1, CAR_PLLD2_BASE_MDIV) | 116 __SHIFTIN(1, CAR_PLLD2_BASE_MDIV) |
117 __SHIFTIN(99, CAR_PLLD2_BASE_NDIV) | 117 __SHIFTIN(99, CAR_PLLD2_BASE_NDIV) |
118 __SHIFTIN(1, CAR_PLLD2_BASE_PLDIV), 118 __SHIFTIN(1, CAR_PLLD2_BASE_PLDIV),
119 CAR_PLLD2_BASE_REF_SRC_SEL | 119 CAR_PLLD2_BASE_REF_SRC_SEL |
120 CAR_PLLD2_BASE_PLDIV | CAR_PLLD2_BASE_NDIV | CAR_PLLD2_BASE_MDIV); 120 CAR_PLLD2_BASE_PLDIV | CAR_PLLD2_BASE_NDIV | CAR_PLLD2_BASE_MDIV);
121} 121}
122 122
123static void 123static void
124tegra_car_rnd_attach(device_t self) 124tegra_car_rnd_attach(device_t self)
125{ 125{
126 struct tegra_car_softc * const sc = device_private(self); 126 struct tegra_car_softc * const sc = device_private(self);
127 127
128 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SERIAL); 128 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SERIAL);
129 mutex_init(&sc->sc_rnd_lock, MUTEX_DEFAULT, IPL_SERIAL); 129 mutex_init(&sc->sc_rnd_lock, MUTEX_DEFAULT, IPL_SERIAL);
130 sc->sc_bytes_wanted = 0; 130 sc->sc_bytes_wanted = 0;
131 sc->sc_sih = softint_establish(SOFTINT_SERIAL|SOFTINT_MPSAFE, 131 sc->sc_sih = softint_establish(SOFTINT_SERIAL|SOFTINT_MPSAFE,
132 tegra_car_rnd_intr, sc); 132 tegra_car_rnd_intr, sc);
133 if (sc->sc_sih == NULL) { 133 if (sc->sc_sih == NULL) {
134 aprint_error_dev(sc->sc_dev, "couldn't establish softint\n"); 134 aprint_error_dev(sc->sc_dev, "couldn't establish softint\n");
135 return; 135 return;
136 } 136 }
137 137
138 rndsource_setcb(&sc->sc_rndsource, tegra_car_rnd_callback, sc); 138 rndsource_setcb(&sc->sc_rndsource, tegra_car_rnd_callback, sc);
139 rnd_attach_source(&sc->sc_rndsource, device_xname(sc->sc_dev), 139 rnd_attach_source(&sc->sc_rndsource, device_xname(sc->sc_dev),
140 RND_TYPE_RNG, RND_FLAG_COLLECT_VALUE|RND_FLAG_HASCB); 140 RND_TYPE_RNG, RND_FLAG_COLLECT_VALUE|RND_FLAG_HASCB);
141} 141}
142 142
143static void 143static void
144tegra_car_rnd_intr(void *priv) 144tegra_car_rnd_intr(void *priv)
145{ 145{
146 struct tegra_car_softc * const sc = priv; 146 struct tegra_car_softc * const sc = priv;
147 uint16_t buf[512]; 147 uint16_t buf[512];
148 uint32_t cnt; 148 uint32_t cnt;
149 149
150 mutex_enter(&sc->sc_intr_lock); 150 mutex_enter(&sc->sc_intr_lock);
151 while (sc->sc_bytes_wanted) { 151 while (sc->sc_bytes_wanted) {
152 const u_int nbytes = MIN(sc->sc_bytes_wanted, 1024); 152 const u_int nbytes = MIN(sc->sc_bytes_wanted, 1024);
153 for (cnt = 0; cnt < sc->sc_bytes_wanted / 2; cnt++) { 153 for (cnt = 0; cnt < sc->sc_bytes_wanted / 2; cnt++) {
154 buf[cnt] = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 154 buf[cnt] = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
155 CAR_PLL_LFSR_REG) & 0xffff; 155 CAR_PLL_LFSR_REG) & 0xffff;
156 } 156 }
157 mutex_exit(&sc->sc_intr_lock); 157 mutex_exit(&sc->sc_intr_lock);
158 mutex_enter(&sc->sc_rnd_lock); 158 mutex_enter(&sc->sc_rnd_lock);
159 rnd_add_data(&sc->sc_rndsource, buf, nbytes, nbytes * NBBY); 159 rnd_add_data(&sc->sc_rndsource, buf, nbytes, nbytes * NBBY);
160 mutex_exit(&sc->sc_rnd_lock); 160 mutex_exit(&sc->sc_rnd_lock);
161 mutex_enter(&sc->sc_intr_lock); 161 mutex_enter(&sc->sc_intr_lock);
162 sc->sc_bytes_wanted -= MIN(sc->sc_bytes_wanted, nbytes); 162 sc->sc_bytes_wanted -= MIN(sc->sc_bytes_wanted, nbytes);
163 } 163 }
164 explicit_memset(buf, 0, sizeof(buf)); 164 explicit_memset(buf, 0, sizeof(buf));
165 mutex_exit(&sc->sc_intr_lock); 165 mutex_exit(&sc->sc_intr_lock);
166} 166}
167 167
168static void 168static void
169tegra_car_rnd_callback(size_t bytes_wanted, void *priv) 169tegra_car_rnd_callback(size_t bytes_wanted, void *priv)
170{ 170{
171 struct tegra_car_softc * const sc = priv; 171 struct tegra_car_softc * const sc = priv;
172 172
173 mutex_enter(&sc->sc_intr_lock); 173 mutex_enter(&sc->sc_intr_lock);
174 if (sc->sc_bytes_wanted == 0) { 174 if (sc->sc_bytes_wanted == 0) {
175 softint_schedule(sc->sc_sih); 175 softint_schedule(sc->sc_sih);
176 } 176 }
177 if (bytes_wanted > (UINT_MAX - sc->sc_bytes_wanted)) { 177 if (bytes_wanted > (UINT_MAX - sc->sc_bytes_wanted)) {
178 sc->sc_bytes_wanted = UINT_MAX; 178 sc->sc_bytes_wanted = UINT_MAX;
179 } else { 179 } else {
180 sc->sc_bytes_wanted += bytes_wanted; 180 sc->sc_bytes_wanted += bytes_wanted;
181 } 181 }
182 mutex_exit(&sc->sc_intr_lock); 182 mutex_exit(&sc->sc_intr_lock);
183} 183}
184 184
185static void 185static void
186tegra_car_get_bs(bus_space_tag_t *pbst, bus_space_handle_t *pbsh) 186tegra_car_get_bs(bus_space_tag_t *pbst, bus_space_handle_t *pbsh)
187{ 187{
188 if (pmc_softc) { 188 if (pmc_softc) {
189 *pbst = pmc_softc->sc_bst; 189 *pbst = pmc_softc->sc_bst;
190 *pbsh = pmc_softc->sc_bsh; 190 *pbsh = pmc_softc->sc_bsh;
191 } else { 191 } else {
192 *pbst = &armv7_generic_bs_tag; 192 *pbst = &armv7_generic_bs_tag;
193 bus_space_subregion(*pbst, tegra_ppsb_bsh, 193 bus_space_subregion(*pbst, tegra_ppsb_bsh,
194 TEGRA_CAR_OFFSET, TEGRA_CAR_SIZE, pbsh); 194 TEGRA_CAR_OFFSET, TEGRA_CAR_SIZE, pbsh);
195 } 195 }
196} 196}
197 197
198u_int 198u_int
199tegra_car_osc_rate(void) 199tegra_car_osc_rate(void)
200{ 200{
201 return TEGRA_REF_FREQ; 201 return TEGRA_REF_FREQ;
202} 202}
203 203
204static u_int 204static u_int
205tegra_car_pll_rate(u_int base_reg, u_int divm_mask, u_int divn_mask, 205tegra_car_pll_rate(u_int base_reg, u_int divm_mask, u_int divn_mask,
206 u_int divp_mask) 206 u_int divp_mask)
207{ 207{
208 bus_space_tag_t bst; 208 bus_space_tag_t bst;
209 bus_space_handle_t bsh; 209 bus_space_handle_t bsh;
210 uint64_t rate; 210 uint64_t rate;
211 211
212 tegra_car_get_bs(&bst, &bsh); 212 tegra_car_get_bs(&bst, &bsh);
213 213
214 const uint32_t base = bus_space_read_4(bst, bsh, base_reg); 214 const uint32_t base = bus_space_read_4(bst, bsh, base_reg);
215 const u_int divm = __SHIFTOUT(base, divm_mask); 215 const u_int divm = __SHIFTOUT(base, divm_mask);
216 const u_int divn = __SHIFTOUT(base, divn_mask); 216 const u_int divn = __SHIFTOUT(base, divn_mask);
217 const u_int divp = __SHIFTOUT(base, divp_mask); 217 const u_int divp = __SHIFTOUT(base, divp_mask);
218 218
219 rate = (uint64_t)tegra_car_osc_rate() * divn; 219 rate = (uint64_t)tegra_car_osc_rate() * divn;
220 220
221 return rate / (divm << divp); 221 return rate / (divm << divp);
222} 222}
223 223
224void 224void
225tegra_car_pllx_set_rate(u_int divm, u_int divn, u_int divp) 225tegra_car_pllx_set_rate(u_int divm, u_int divn, u_int divp)
226{ 226{
227 bus_space_tag_t bst; 227 bus_space_tag_t bst;
228 bus_space_handle_t bsh; 228 bus_space_handle_t bsh;
229 uint32_t base, bp; 229 uint32_t base, bp;
230 230
231 tegra_car_get_bs(&bst, &bsh); 231 tegra_car_get_bs(&bst, &bsh);
232 232
233 bp = bus_space_read_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG); 233 bp = bus_space_read_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG);
234 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 234 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE;
235 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE, 235 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE,
236 CAR_CCLKG_BURST_POLICY_CPU_STATE); 236 CAR_CCLKG_BURST_POLICY_CPU_STATE);
237 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 237 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE;
238 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM, 238 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM,
239 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 239 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE);
240 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 240 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp);
241 241
242 base = bus_space_read_4(bst, bsh, CAR_PLLX_BASE_REG); 242 base = bus_space_read_4(bst, bsh, CAR_PLLX_BASE_REG);
243 base &= ~CAR_PLLX_BASE_DIVM; 243 base &= ~CAR_PLLX_BASE_DIVM;
244 base &= ~CAR_PLLX_BASE_DIVN; 244 base &= ~CAR_PLLX_BASE_DIVN;
245 base &= ~CAR_PLLX_BASE_DIVP; 245 base &= ~CAR_PLLX_BASE_DIVP;
246 base |= __SHIFTIN(divm, CAR_PLLX_BASE_DIVM); 246 base |= __SHIFTIN(divm, CAR_PLLX_BASE_DIVM);
247 base |= __SHIFTIN(divn, CAR_PLLX_BASE_DIVN); 247 base |= __SHIFTIN(divn, CAR_PLLX_BASE_DIVN);
248 base |= __SHIFTIN(divp, CAR_PLLX_BASE_DIVP); 248 base |= __SHIFTIN(divp, CAR_PLLX_BASE_DIVP);
249 bus_space_write_4(bst, bsh, CAR_PLLX_BASE_REG, base); 249 bus_space_write_4(bst, bsh, CAR_PLLX_BASE_REG, base);
250 250
251 tegra_reg_set_clear(bst, bsh, CAR_PLLX_MISC_REG, 251 tegra_reg_set_clear(bst, bsh, CAR_PLLX_MISC_REG,
252 CAR_PLLX_MISC_LOCK_ENABLE, 0); 252 CAR_PLLX_MISC_LOCK_ENABLE, 0);
253 do { 253 do {
254 delay(2); 254 delay(2);
255 base = bus_space_read_4(bst, bsh, CAR_PLLX_BASE_REG); 255 base = bus_space_read_4(bst, bsh, CAR_PLLX_BASE_REG);
256 } while ((base & CAR_PLLX_BASE_LOCK) == 0); 256 } while ((base & CAR_PLLX_BASE_LOCK) == 0);
257 delay(100); 257 delay(100);
258 258
259 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE; 259 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE;
260 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN, 260 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN,
261 CAR_CCLKG_BURST_POLICY_CPU_STATE); 261 CAR_CCLKG_BURST_POLICY_CPU_STATE);
262 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE; 262 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE;
263 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ, 263 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ,
264 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE); 264 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE);
265 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp); 265 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp);
266} 266}
267 267
268u_int 268u_int
269tegra_car_pllx_rate(void) 269tegra_car_pllx_rate(void)
270{ 270{
271 return tegra_car_pll_rate(CAR_PLLX_BASE_REG, CAR_PLLX_BASE_DIVM, 271 return tegra_car_pll_rate(CAR_PLLX_BASE_REG, CAR_PLLX_BASE_DIVM,
272 CAR_PLLX_BASE_DIVN, CAR_PLLX_BASE_DIVP); 272 CAR_PLLX_BASE_DIVN, CAR_PLLX_BASE_DIVP);
273} 273}
274 274
275u_int 275u_int
276tegra_car_pllc_rate(void) 276tegra_car_pllc_rate(void)
277{ 277{
278 return tegra_car_pll_rate(CAR_PLLC_BASE_REG, CAR_PLLC_BASE_DIVM, 278 return tegra_car_pll_rate(CAR_PLLC_BASE_REG, CAR_PLLC_BASE_DIVM,
279 CAR_PLLC_BASE_DIVN, CAR_PLLC_BASE_DIVP); 279 CAR_PLLC_BASE_DIVN, CAR_PLLC_BASE_DIVP);
280} 280}
281 281
282u_int 282u_int
283tegra_car_plle_rate(void) 283tegra_car_plle_rate(void)
284{ 284{
285 return tegra_car_pll_rate(CAR_PLLE_BASE_REG, CAR_PLLE_BASE_DIVM, 285 return tegra_car_pll_rate(CAR_PLLE_BASE_REG, CAR_PLLE_BASE_DIVM,
286 CAR_PLLE_BASE_DIVN, CAR_PLLE_BASE_DIVP_CML); 286 CAR_PLLE_BASE_DIVN, CAR_PLLE_BASE_DIVP_CML);
287} 287}
288 288
289u_int 289u_int
290tegra_car_pllu_rate(void) 290tegra_car_pllu_rate(void)
291{ 291{
292 bus_space_tag_t bst; 292 bus_space_tag_t bst;
293 bus_space_handle_t bsh; 293 bus_space_handle_t bsh;
294 uint64_t rate; 294 uint64_t rate;
295 295
296 tegra_car_get_bs(&bst, &bsh); 296 tegra_car_get_bs(&bst, &bsh);
297 297
298 rate = tegra_car_osc_rate();  298 rate = tegra_car_osc_rate();
299 const uint32_t base = bus_space_read_4(bst, bsh, CAR_PLLU_BASE_REG); 299 const uint32_t base = bus_space_read_4(bst, bsh, CAR_PLLU_BASE_REG);
300 const u_int divm = __SHIFTOUT(base, CAR_PLLU_BASE_DIVM); 300 const u_int divm = __SHIFTOUT(base, CAR_PLLU_BASE_DIVM);
301 const u_int divn = __SHIFTOUT(base, CAR_PLLU_BASE_DIVN); 301 const u_int divn = __SHIFTOUT(base, CAR_PLLU_BASE_DIVN);
302 const u_int divp = __SHIFTOUT(base, CAR_PLLU_BASE_VCO_FREQ) ? 0 : 1; 302 const u_int divp = __SHIFTOUT(base, CAR_PLLU_BASE_VCO_FREQ) ? 0 : 1;
303 303
304 rate = (uint64_t)tegra_car_osc_rate() * divn; 304 rate = (uint64_t)tegra_car_osc_rate() * divn;
305 305
306 return rate / (divm << divp); 306 return rate / (divm << divp);
307} 307}
308 308
309u_int 309u_int
310tegra_car_pllp0_rate(void) 310tegra_car_pllp0_rate(void)
311{ 311{
312 return tegra_car_pll_rate(CAR_PLLP_BASE_REG, CAR_PLLP_BASE_DIVM, 312 return tegra_car_pll_rate(CAR_PLLP_BASE_REG, CAR_PLLP_BASE_DIVM,
313 CAR_PLLP_BASE_DIVN, CAR_PLLP_BASE_DIVP); 313 CAR_PLLP_BASE_DIVN, CAR_PLLP_BASE_DIVP);
314} 314}
315 315
316u_int 316u_int
317tegra_car_plld2_rate(void) 317tegra_car_plld2_rate(void)
318{ 318{
319 return tegra_car_pll_rate(CAR_PLLD2_BASE_REG, CAR_PLLD2_BASE_MDIV, 319 return tegra_car_pll_rate(CAR_PLLD2_BASE_REG, CAR_PLLD2_BASE_MDIV,
320 CAR_PLLD2_BASE_NDIV, CAR_PLLD2_BASE_PLDIV); 320 CAR_PLLD2_BASE_NDIV, CAR_PLLD2_BASE_PLDIV);
321} 321}
322 322
323u_int 323u_int
324tegra_car_uart_rate(u_int port) 324tegra_car_uart_rate(u_int port)
325{ 325{
326 bus_space_tag_t bst; 326 bus_space_tag_t bst;
327 bus_space_handle_t bsh; 327 bus_space_handle_t bsh;
328 bus_size_t src_reg; 328 bus_size_t src_reg;
329 u_int src_rate; 329 u_int src_rate;
330 330
331 tegra_car_get_bs(&bst, &bsh); 331 tegra_car_get_bs(&bst, &bsh);
332 332
333 switch (port) { 333 switch (port) {
334 case 0: src_reg = CAR_CLKSRC_UARTA_REG; break; 334 case 0: src_reg = CAR_CLKSRC_UARTA_REG; break;
335 case 1: src_reg = CAR_CLKSRC_UARTB_REG; break; 335 case 1: src_reg = CAR_CLKSRC_UARTB_REG; break;
336 case 2: src_reg = CAR_CLKSRC_UARTC_REG; break; 336 case 2: src_reg = CAR_CLKSRC_UARTC_REG; break;
337 case 3: src_reg = CAR_CLKSRC_UARTD_REG; break; 337 case 3: src_reg = CAR_CLKSRC_UARTD_REG; break;
338 default: return 0; 338 default: return 0;
339 } 339 }
340 340
341 const uint32_t src = bus_space_read_4(bst, bsh, src_reg); 341 const uint32_t src = bus_space_read_4(bst, bsh, src_reg);
342 switch (__SHIFTOUT(src, CAR_CLKSRC_UART_SRC)) { 342 switch (__SHIFTOUT(src, CAR_CLKSRC_UART_SRC)) {
343 case 0: 343 case 0:
344 src_rate = tegra_car_pllp0_rate(); 344 src_rate = tegra_car_pllp0_rate();
345 break; 345 break;
346 default: 346 default:
347 panic("%s: unsupported src %#x", __func__, src); 347 panic("%s: unsupported src %#x", __func__, src);
348 } 348 }
349 349
350 if (__SHIFTOUT(src, CAR_CLKSRC_UART_DIV_ENB)) { 350 if (__SHIFTOUT(src, CAR_CLKSRC_UART_DIV_ENB)) {
351 const u_int div = (__SHIFTOUT(src, CAR_CLKSRC_UART_DIV) / 2) + 1; 351 const u_int div = (__SHIFTOUT(src, CAR_CLKSRC_UART_DIV) / 2) + 1;
352 return src_rate / div; 352 return src_rate / div;
353 } else { 353 } else {
354 return src_rate; 354 return src_rate;
355 } 355 }
356} 356}
357 357
358u_int 358u_int
359tegra_car_periph_sdmmc_rate(u_int port) 359tegra_car_periph_sdmmc_rate(u_int port)
360{ 360{
361 bus_space_tag_t bst; 361 bus_space_tag_t bst;
362 bus_space_handle_t bsh; 362 bus_space_handle_t bsh;
363 bus_size_t src_reg; 363 bus_size_t src_reg;
364 364
365 tegra_car_get_bs(&bst, &bsh); 365 tegra_car_get_bs(&bst, &bsh);
366 366
367 switch (port) { 367 switch (port) {
368 case 0: src_reg = CAR_CLKSRC_SDMMC1_REG; break; 368 case 0: src_reg = CAR_CLKSRC_SDMMC1_REG; break;
369 case 1: src_reg = CAR_CLKSRC_SDMMC2_REG; break; 369 case 1: src_reg = CAR_CLKSRC_SDMMC2_REG; break;
370 case 2: src_reg = CAR_CLKSRC_SDMMC3_REG; break; 370 case 2: src_reg = CAR_CLKSRC_SDMMC3_REG; break;
371 case 3: src_reg = CAR_CLKSRC_SDMMC4_REG; break; 371 case 3: src_reg = CAR_CLKSRC_SDMMC4_REG; break;
372 default: return 0; 372 default: return 0;
373 } 373 }
374 374
375 const uint32_t src = bus_space_read_4(bst, bsh, src_reg); 375 const uint32_t src = bus_space_read_4(bst, bsh, src_reg);
376 376
377 const u_int div = __SHIFTOUT(src, CAR_CLKSRC_SDMMC_DIV) + 2; 377 const u_int div = __SHIFTOUT(src, CAR_CLKSRC_SDMMC_DIV) + 2;
378 378
379 return (tegra_car_pllp0_rate() * 2) / div; 379 return (tegra_car_pllp0_rate() * 2) / div;
380} 380}
381 381
382int 382int
383tegra_car_periph_sdmmc_set_rate(u_int port, u_int rate) 383tegra_car_periph_sdmmc_set_rate(u_int port, u_int rate)
384{ 384{
385 bus_space_tag_t bst; 385 bus_space_tag_t bst;
386 bus_space_handle_t bsh; 386 bus_space_handle_t bsh;
387 bus_size_t src_reg, rst_reg, enb_reg; 387 bus_size_t src_reg, rst_reg, enb_reg;
388 u_int dev_bit; 388 u_int dev_bit;
389 uint32_t src; 389 uint32_t src;
390 390
391 KASSERT(rate > 0); 391 KASSERT(rate > 0);
392 392
393 tegra_car_get_bs(&bst, &bsh); 393 tegra_car_get_bs(&bst, &bsh);
394 394
395 switch (port) { 395 switch (port) {
396 case 0: 396 case 0:
397 src_reg = CAR_CLKSRC_SDMMC1_REG; 397 src_reg = CAR_CLKSRC_SDMMC1_REG;
398 rst_reg = CAR_RST_DEV_L_SET_REG; 398 rst_reg = CAR_RST_DEV_L_SET_REG;
399 enb_reg = CAR_CLK_ENB_L_SET_REG; 399 enb_reg = CAR_CLK_ENB_L_SET_REG;
400 dev_bit = CAR_DEV_L_SDMMC1; 400 dev_bit = CAR_DEV_L_SDMMC1;
401 break; 401 break;
402 case 1: 402 case 1:
403 src_reg = CAR_CLKSRC_SDMMC2_REG; 403 src_reg = CAR_CLKSRC_SDMMC2_REG;
404 rst_reg = CAR_RST_DEV_L_SET_REG; 404 rst_reg = CAR_RST_DEV_L_SET_REG;
405 enb_reg = CAR_CLK_ENB_L_SET_REG; 405 enb_reg = CAR_CLK_ENB_L_SET_REG;
406 dev_bit = CAR_DEV_L_SDMMC2; 406 dev_bit = CAR_DEV_L_SDMMC2;
407 break; 407 break;
408 case 2: 408 case 2:
409 src_reg = CAR_CLKSRC_SDMMC3_REG; 409 src_reg = CAR_CLKSRC_SDMMC3_REG;
410 rst_reg = CAR_RST_DEV_U_SET_REG; 410 rst_reg = CAR_RST_DEV_U_SET_REG;
411 enb_reg = CAR_CLK_ENB_U_SET_REG; 411 enb_reg = CAR_CLK_ENB_U_SET_REG;
412 dev_bit = CAR_DEV_U_SDMMC3; 412 dev_bit = CAR_DEV_U_SDMMC3;
413 break; 413 break;
414 case 3: 414 case 3:
415 src_reg = CAR_CLKSRC_SDMMC4_REG; 415 src_reg = CAR_CLKSRC_SDMMC4_REG;
416 rst_reg = CAR_RST_DEV_L_SET_REG; 416 rst_reg = CAR_RST_DEV_L_SET_REG;
417 enb_reg = CAR_CLK_ENB_L_SET_REG; 417 enb_reg = CAR_CLK_ENB_L_SET_REG;
418 dev_bit = CAR_DEV_L_SDMMC4; 418 dev_bit = CAR_DEV_L_SDMMC4;
419 break; 419 break;
420 default: return EINVAL; 420 default: return EINVAL;
421 } 421 }
422 422
423 /* enter reset */ 423 /* enter reset */
424 bus_space_write_4(bst, bsh, rst_reg, dev_bit); 424 bus_space_write_4(bst, bsh, rst_reg, dev_bit);
425 /* enable clk */ 425 /* enable clk */
426 bus_space_write_4(bst, bsh, enb_reg, dev_bit); 426 bus_space_write_4(bst, bsh, enb_reg, dev_bit);
427 427
428 const u_int div = howmany(tegra_car_pllp0_rate() * 2, rate) - 2; 428 const u_int div = howmany(tegra_car_pllp0_rate() * 2, rate) - 2;
429 429
430 /* update clk div */ 430 /* update clk div */
431 src = __SHIFTIN(CAR_CLKSRC_SDMMC_SRC_PLLP_OUT0, 431 src = __SHIFTIN(CAR_CLKSRC_SDMMC_SRC_PLLP_OUT0,
432 CAR_CLKSRC_SDMMC_SRC); 432 CAR_CLKSRC_SDMMC_SRC);
433 src |= __SHIFTIN(div, CAR_CLKSRC_SDMMC_DIV); 433 src |= __SHIFTIN(div, CAR_CLKSRC_SDMMC_DIV);
434 bus_space_write_4(bst, bsh, src_reg, src); 434 bus_space_write_4(bst, bsh, src_reg, src);
435 435
436 /* leave reset */ 436 /* leave reset */
437 bus_space_write_4(bst, bsh, rst_reg+4, dev_bit); 437 bus_space_write_4(bst, bsh, rst_reg+4, dev_bit);
438 438
439 return 0; 439 return 0;
440} 440}
441 441
442int 442int
443tegra_car_periph_usb_enable(u_int port) 443tegra_car_periph_usb_enable(u_int port)
444{ 444{
445 bus_space_tag_t bst; 445 bus_space_tag_t bst;
446 bus_space_handle_t bsh; 446 bus_space_handle_t bsh;
447 bus_size_t rst_reg, enb_reg; 447 bus_size_t rst_reg, enb_reg;
448 uint32_t dev_bit; 448 uint32_t dev_bit;
449 449
450 tegra_car_get_bs(&bst, &bsh); 450 tegra_car_get_bs(&bst, &bsh);
451 switch (port) { 451 switch (port) {
452 case 0: 452 case 0:
453 rst_reg = CAR_RST_DEV_L_SET_REG; 453 rst_reg = CAR_RST_DEV_L_SET_REG;
454 enb_reg = CAR_CLK_ENB_L_SET_REG; 454 enb_reg = CAR_CLK_ENB_L_SET_REG;
455 dev_bit = CAR_DEV_L_USBD; 455 dev_bit = CAR_DEV_L_USBD;
456 break; 456 break;
457 case 1: 457 case 1:
458 rst_reg = CAR_RST_DEV_H_SET_REG; 458 rst_reg = CAR_RST_DEV_H_SET_REG;
459 enb_reg = CAR_CLK_ENB_H_SET_REG; 459 enb_reg = CAR_CLK_ENB_H_SET_REG;
460 dev_bit = CAR_DEV_H_USB2; 460 dev_bit = CAR_DEV_H_USB2;
461 break; 461 break;
462 case 2: 462 case 2:
463 rst_reg = CAR_RST_DEV_H_SET_REG; 463 rst_reg = CAR_RST_DEV_H_SET_REG;
464 enb_reg = CAR_CLK_ENB_H_SET_REG; 464 enb_reg = CAR_CLK_ENB_H_SET_REG;
465 dev_bit = CAR_DEV_H_USB3; 465 dev_bit = CAR_DEV_H_USB3;
466 break; 466 break;
467 default: 467 default:
468 return EINVAL; 468 return EINVAL;
469 } 469 }
470 470
471 /* enter reset */ 471 /* enter reset */
472 bus_space_write_4(bst, bsh, rst_reg, dev_bit); 472 bus_space_write_4(bst, bsh, rst_reg, dev_bit);
473 /* enable clk */ 473 /* enable clk */
474 bus_space_write_4(bst, bsh, enb_reg, dev_bit); 474 bus_space_write_4(bst, bsh, enb_reg, dev_bit);
475 475
476 /* leave reset */ 476 /* leave reset */
477 bus_space_write_4(bst, bsh, rst_reg+4, dev_bit); 477 bus_space_write_4(bst, bsh, rst_reg+4, dev_bit);
478 478
479 return 0; 479 return 0;
480} 480}
481 481
482void 482void
483tegra_car_utmip_init(void) 483tegra_car_utmip_init(void)
484{ 484{
485 const u_int enable_dly_count = 0x02; 485 const u_int enable_dly_count = 0x02;
486 const u_int stable_count = 0x33; 486 const u_int stable_count = 0x33;
487 const u_int active_dly_count = 0x09; 487 const u_int active_dly_count = 0x09;
488 const u_int xtal_freq_count = 0x7f; 488 const u_int xtal_freq_count = 0x7f;
489 bus_space_tag_t bst; 489 bus_space_tag_t bst;
490 bus_space_handle_t bsh; 490 bus_space_handle_t bsh;
491 491
492 tegra_car_get_bs(&bst, &bsh); 492 tegra_car_get_bs(&bst, &bsh);
493 493
494 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 494 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG,
495 __SHIFTIN(stable_count, CAR_UTMIP_PLL_CFG2_STABLE_COUNT) | 495 __SHIFTIN(stable_count, CAR_UTMIP_PLL_CFG2_STABLE_COUNT) |
496 __SHIFTIN(active_dly_count, CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT), 496 __SHIFTIN(active_dly_count, CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT),
497 CAR_UTMIP_PLL_CFG2_STABLE_COUNT | 497 CAR_UTMIP_PLL_CFG2_STABLE_COUNT |
498 CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT); 498 CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT);
499 499
500 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 500 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG,
501 __SHIFTIN(enable_dly_count, CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT) | 501 __SHIFTIN(enable_dly_count, CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT) |
502 __SHIFTIN(xtal_freq_count, CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT), 502 __SHIFTIN(xtal_freq_count, CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT),
503 CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT | 503 CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT |
504 CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT); 504 CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT);
505 505
506 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 506 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG,
507 0, 507 0,
508 CAR_UTMIP_PLL_CFG1_PLLU_POWERDOWN | 508 CAR_UTMIP_PLL_CFG1_PLLU_POWERDOWN |
509 CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN); 509 CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN);
510} 510}
511 511
512void 512void
513tegra_car_utmip_enable(u_int port) 513tegra_car_utmip_enable(u_int port)
514{ 514{
515 bus_space_tag_t bst; 515 bus_space_tag_t bst;
516 bus_space_handle_t bsh; 516 bus_space_handle_t bsh;
517 uint32_t bit = 0; 517 uint32_t bit = 0;
518 518
519 tegra_car_get_bs(&bst, &bsh); 519 tegra_car_get_bs(&bst, &bsh);
520 520
521 switch (port) { 521 switch (port) {
522 case 0: bit = CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN; break; 522 case 0: bit = CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN; break;
523 case 1: bit = CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN; break; 523 case 1: bit = CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN; break;
524 case 2: bit = CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN; break; 524 case 2: bit = CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN; break;
525 } 525 }
526 526
527 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 0, bit); 527 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 0, bit);
528} 528}
529 529
530void 530void
531tegra_car_periph_hda_enable(void) 531tegra_car_periph_hda_enable(void)
532{ 532{
533 bus_space_tag_t bst; 533 bus_space_tag_t bst;
534 bus_space_handle_t bsh; 534 bus_space_handle_t bsh;
535 535
536 tegra_car_get_bs(&bst, &bsh); 536 tegra_car_get_bs(&bst, &bsh);
537 537
538 /* HDA */ 
539 bus_space_write_4(bst, bsh, CAR_RST_DEV_V_SET_REG, CAR_DEV_V_HDA); 538 bus_space_write_4(bst, bsh, CAR_RST_DEV_V_SET_REG, CAR_DEV_V_HDA);
540 bus_space_write_4(bst, bsh, CAR_CLK_ENB_V_SET_REG, CAR_DEV_V_HDA); 539 bus_space_write_4(bst, bsh, CAR_CLK_ENB_V_SET_REG, CAR_DEV_V_HDA);
541 bus_space_write_4(bst, bsh, CAR_RST_DEV_V_CLR_REG, CAR_DEV_V_HDA); 
542 
543 /* HDA2CODEC_2X */ 
544 bus_space_write_4(bst, bsh, CAR_RST_DEV_V_SET_REG, 540 bus_space_write_4(bst, bsh, CAR_RST_DEV_V_SET_REG,
545 CAR_DEV_V_HDA2CODEC_2X); 541 CAR_DEV_V_HDA2CODEC_2X);
546 bus_space_write_4(bst, bsh, CAR_CLK_ENB_V_SET_REG, 542 bus_space_write_4(bst, bsh, CAR_CLK_ENB_V_SET_REG,
547 CAR_DEV_V_HDA2CODEC_2X); 543 CAR_DEV_V_HDA2CODEC_2X);
548 bus_space_write_4(bst, bsh, CAR_RST_DEV_V_CLR_REG, 
549 CAR_DEV_V_HDA2CODEC_2X); 
550 
551 /* HDA2HDMICODEC */ 
552 bus_space_write_4(bst, bsh, CAR_RST_DEV_W_SET_REG, 544 bus_space_write_4(bst, bsh, CAR_RST_DEV_W_SET_REG,
553 CAR_DEV_W_HDA2HDMICODEC); 545 CAR_DEV_W_HDA2HDMICODEC);
554 bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, 546 bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG,
555 CAR_DEV_W_HDA2HDMICODEC); 547 CAR_DEV_W_HDA2HDMICODEC);
 548
 549 /* configure HDA2CODEC_2X for 48 MHz */
 550 const u_int div = howmany(tegra_car_pllp0_rate() * 2, 48000000) - 2;
 551 bus_space_write_4(bst, bsh, CAR_CLKSRC_HDA2CODEC_2X_REG,
 552 __SHIFTIN(CAR_CLKSRC_HDA2CODEC_2X_SRC_PLLP_OUT0,
 553 CAR_CLKSRC_HDA2CODEC_2X_SRC) |
 554 __SHIFTIN(div, CAR_CLKSRC_HDA2CODEC_2X_DIV));
 555
 556 bus_space_write_4(bst, bsh, CAR_RST_DEV_V_CLR_REG, CAR_DEV_V_HDA);
 557 bus_space_write_4(bst, bsh, CAR_RST_DEV_V_CLR_REG,
 558 CAR_DEV_V_HDA2CODEC_2X);
556 bus_space_write_4(bst, bsh, CAR_RST_DEV_W_CLR_REG, 559 bus_space_write_4(bst, bsh, CAR_RST_DEV_W_CLR_REG,
557 CAR_DEV_W_HDA2HDMICODEC); 560 CAR_DEV_W_HDA2HDMICODEC);
558} 561}
559 562
560void 563void
561tegra_car_periph_sata_enable(void) 564tegra_car_periph_sata_enable(void)
562{ 565{
563 bus_space_tag_t bst; 566 bus_space_tag_t bst;
564 bus_space_handle_t bsh; 567 bus_space_handle_t bsh;
565 568
566 tegra_car_get_bs(&bst, &bsh); 569 tegra_car_get_bs(&bst, &bsh);
567 570
568 /* Assert resets */ 571 /* Assert resets */
569 bus_space_write_4(bst, bsh, CAR_RST_DEV_V_SET_REG, CAR_DEV_V_SATA); 572 bus_space_write_4(bst, bsh, CAR_RST_DEV_V_SET_REG, CAR_DEV_V_SATA);
570 bus_space_write_4(bst, bsh, CAR_RST_DEV_W_SET_REG, CAR_DEV_W_SATACOLD); 573 bus_space_write_4(bst, bsh, CAR_RST_DEV_W_SET_REG, CAR_DEV_W_SATACOLD);
571 574
572 /* Disable software control of SATA PLL */ 575 /* Disable software control of SATA PLL */
573 tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG, 576 tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG,
574 0, CAR_SATA_PLL_CFG0_PADPLL_RESET_SWCTL); 577 0, CAR_SATA_PLL_CFG0_PADPLL_RESET_SWCTL);
575 578
576 /* Set SATA_OOB clock source to PLLP, 204MHz */ 579 /* Set SATA_OOB clock source to PLLP, 204MHz */
577 const u_int sataoob_div = 2; 580 const u_int sataoob_div = 2;
578 bus_space_write_4(bst, bsh, CAR_CLKSRC_SATA_OOB_REG, 581 bus_space_write_4(bst, bsh, CAR_CLKSRC_SATA_OOB_REG,
579 __SHIFTIN(CAR_CLKSRC_SATA_OOB_SRC_PLLP_OUT0, 582 __SHIFTIN(CAR_CLKSRC_SATA_OOB_SRC_PLLP_OUT0,
580 CAR_CLKSRC_SATA_OOB_SRC) | 583 CAR_CLKSRC_SATA_OOB_SRC) |
581 __SHIFTIN((sataoob_div - 1) * 2, CAR_CLKSRC_SATA_OOB_DIV)); 584 __SHIFTIN((sataoob_div - 1) * 2, CAR_CLKSRC_SATA_OOB_DIV));
582 585
583 /* Set SATA clock source to PLLP, 102MHz */ 586 /* Set SATA clock source to PLLP, 102MHz */
584 const u_int sata_div = 4; 587 const u_int sata_div = 4;
585 bus_space_write_4(bst, bsh, CAR_CLKSRC_SATA_REG, 588 bus_space_write_4(bst, bsh, CAR_CLKSRC_SATA_REG,
586 CAR_CLKSRC_SATA_AUX_CLK_ENB | 589 CAR_CLKSRC_SATA_AUX_CLK_ENB |
587 __SHIFTIN(CAR_CLKSRC_SATA_SRC_PLLP_OUT0, 590 __SHIFTIN(CAR_CLKSRC_SATA_SRC_PLLP_OUT0,
588 CAR_CLKSRC_SATA_SRC) | 591 CAR_CLKSRC_SATA_SRC) |
589 __SHIFTIN((sata_div - 1) * 2, CAR_CLKSRC_SATA_DIV)); 592 __SHIFTIN((sata_div - 1) * 2, CAR_CLKSRC_SATA_DIV));
590 593
591 /* Ungate SAX partition in the PMC */ 594 /* Ungate SAX partition in the PMC */
592 tegra_pmc_power(PMC_PARTID_SAX, true); 595 tegra_pmc_power(PMC_PARTID_SAX, true);
593 delay(20); 596 delay(20);
594 597
595 /* Remove clamping from SAX partition in the PMC */ 598 /* Remove clamping from SAX partition in the PMC */
596 tegra_pmc_remove_clamping(PMC_PARTID_SAX); 599 tegra_pmc_remove_clamping(PMC_PARTID_SAX);
597 delay(20); 600 delay(20);
598 601
599 /* De-assert reset to SATA PADPLL */ 602 /* De-assert reset to SATA PADPLL */
600 tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG, 603 tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG,
601 0, CAR_SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE); 604 0, CAR_SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE);
602 delay(15); 605 delay(15);
603 606
604 /* Enable CML clock for SATA */ 607 /* Enable CML clock for SATA */
605 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 608 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG,
606 CAR_PLLE_AUX_CML1_OEN, 0); 609 CAR_PLLE_AUX_CML1_OEN, 0);
607 610
608 /* Turn on the clocks to SATA and de-assert resets */ 611 /* Turn on the clocks to SATA and de-assert resets */
609 bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_SATACOLD); 612 bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_SATACOLD);
610 bus_space_write_4(bst, bsh, CAR_CLK_ENB_V_SET_REG, CAR_DEV_V_SATA); 613 bus_space_write_4(bst, bsh, CAR_CLK_ENB_V_SET_REG, CAR_DEV_V_SATA);
611 bus_space_write_4(bst, bsh, CAR_CLK_ENB_V_SET_REG, CAR_DEV_V_SATA_OOB); 614 bus_space_write_4(bst, bsh, CAR_CLK_ENB_V_SET_REG, CAR_DEV_V_SATA_OOB);
612 615
613 bus_space_write_4(bst, bsh, CAR_RST_DEV_W_CLR_REG, CAR_DEV_W_SATACOLD); 616 bus_space_write_4(bst, bsh, CAR_RST_DEV_W_CLR_REG, CAR_DEV_W_SATACOLD);
614 bus_space_write_4(bst, bsh, CAR_RST_DEV_V_CLR_REG, CAR_DEV_V_SATA); 617 bus_space_write_4(bst, bsh, CAR_RST_DEV_V_CLR_REG, CAR_DEV_V_SATA);
615} 618}
616 619
617int 620int
618tegra_car_periph_i2c_enable(u_int port, u_int rate) 621tegra_car_periph_i2c_enable(u_int port, u_int rate)
619{ 622{
620 bus_space_tag_t bst; 623 bus_space_tag_t bst;
621 bus_space_handle_t bsh; 624 bus_space_handle_t bsh;
622 bus_size_t rst_reg, enb_reg, clksrc_reg; 625 bus_size_t rst_reg, enb_reg, clksrc_reg;
623 uint32_t dev_bit; 626 uint32_t dev_bit;
624 627
625 tegra_car_get_bs(&bst, &bsh); 628 tegra_car_get_bs(&bst, &bsh);
626 629
627 switch (port) { 630 switch (port) {
628 case 0: 631 case 0:
629 rst_reg = CAR_RST_DEV_L_SET_REG; 632 rst_reg = CAR_RST_DEV_L_SET_REG;
630 enb_reg = CAR_CLK_ENB_L_SET_REG; 633 enb_reg = CAR_CLK_ENB_L_SET_REG;
631 dev_bit = CAR_DEV_L_I2C1; 634 dev_bit = CAR_DEV_L_I2C1;
632 clksrc_reg = CAR_CLKSRC_I2C1_REG; 635 clksrc_reg = CAR_CLKSRC_I2C1_REG;
633 break; 636 break;
634 case 1: 637 case 1:
635 rst_reg = CAR_RST_DEV_H_SET_REG; 638 rst_reg = CAR_RST_DEV_H_SET_REG;
636 enb_reg = CAR_CLK_ENB_H_SET_REG; 639 enb_reg = CAR_CLK_ENB_H_SET_REG;
637 dev_bit = CAR_DEV_H_I2C2; 640 dev_bit = CAR_DEV_H_I2C2;
638 clksrc_reg = CAR_CLKSRC_I2C2_REG; 641 clksrc_reg = CAR_CLKSRC_I2C2_REG;
639 break; 642 break;
640 case 2: 643 case 2:
641 rst_reg = CAR_RST_DEV_U_SET_REG; 644 rst_reg = CAR_RST_DEV_U_SET_REG;
642 enb_reg = CAR_CLK_ENB_U_SET_REG; 645 enb_reg = CAR_CLK_ENB_U_SET_REG;
643 dev_bit = CAR_DEV_U_I2C3; 646 dev_bit = CAR_DEV_U_I2C3;
644 clksrc_reg = CAR_CLKSRC_I2C3_REG; 647 clksrc_reg = CAR_CLKSRC_I2C3_REG;
645 break; 648 break;
646 case 3: 649 case 3:
647 rst_reg = CAR_RST_DEV_V_SET_REG; 650 rst_reg = CAR_RST_DEV_V_SET_REG;
648 enb_reg = CAR_CLK_ENB_V_SET_REG; 651 enb_reg = CAR_CLK_ENB_V_SET_REG;
649 dev_bit = CAR_DEV_V_I2C4; 652 dev_bit = CAR_DEV_V_I2C4;
650 clksrc_reg = CAR_CLKSRC_I2C4_REG; 653 clksrc_reg = CAR_CLKSRC_I2C4_REG;
651 break; 654 break;
652 case 4: 655 case 4:
653 rst_reg = CAR_RST_DEV_H_SET_REG; 656 rst_reg = CAR_RST_DEV_H_SET_REG;
654 enb_reg = CAR_CLK_ENB_H_SET_REG; 657 enb_reg = CAR_CLK_ENB_H_SET_REG;
655 dev_bit = CAR_DEV_H_I2C5; 658 dev_bit = CAR_DEV_H_I2C5;
656 clksrc_reg = CAR_CLKSRC_I2C5_REG; 659 clksrc_reg = CAR_CLKSRC_I2C5_REG;
657 break; 660 break;
658 case 5: 661 case 5:
659 rst_reg = CAR_RST_DEV_X_SET_REG; 662 rst_reg = CAR_RST_DEV_X_SET_REG;
660 enb_reg = CAR_CLK_ENB_X_SET_REG; 663 enb_reg = CAR_CLK_ENB_X_SET_REG;
661 dev_bit = CAR_DEV_X_I2C6; 664 dev_bit = CAR_DEV_X_I2C6;
662 clksrc_reg = CAR_CLKSRC_I2C6_REG; 665 clksrc_reg = CAR_CLKSRC_I2C6_REG;
663 break; 666 break;
664 default: 667 default:
665 return EINVAL; 668 return EINVAL;
666 } 669 }
667 670
668 /* Enter reset, enable clock */ 671 /* Enter reset, enable clock */
669 bus_space_write_4(bst, bsh, rst_reg, dev_bit); 672 bus_space_write_4(bst, bsh, rst_reg, dev_bit);
670 bus_space_write_4(bst, bsh, enb_reg, dev_bit); 673 bus_space_write_4(bst, bsh, enb_reg, dev_bit);
671 674
672 /* Set clock source to PLLP */ 675 /* Set clock source to PLLP */
673 const u_int div = howmany(tegra_car_pllp0_rate() / 1000, rate / 1000); 676 const u_int div = howmany(tegra_car_pllp0_rate() / 1000, rate / 1000);
674 bus_space_write_4(bst, bsh, clksrc_reg, 677 bus_space_write_4(bst, bsh, clksrc_reg,
675 __SHIFTIN(CAR_CLKSRC_I2C_SRC_PLLP_OUT0, CAR_CLKSRC_I2C_SRC) | 678 __SHIFTIN(CAR_CLKSRC_I2C_SRC_PLLP_OUT0, CAR_CLKSRC_I2C_SRC) |
676 __SHIFTIN(div - 1, CAR_CLKSRC_I2C_DIV)); 679 __SHIFTIN(div - 1, CAR_CLKSRC_I2C_DIV));
677 680
678 /* Leave reset */ 681 /* Leave reset */
679 bus_space_write_4(bst, bsh, rst_reg+4, dev_bit); 682 bus_space_write_4(bst, bsh, rst_reg+4, dev_bit);
680 683
681 return 0; 684 return 0;
682} 685}
683 686
684void 687void
685tegra_car_hdmi_enable(u_int rate) 688tegra_car_hdmi_enable(u_int rate)
686{ 689{
687 bus_space_tag_t bst; 690 bus_space_tag_t bst;
688 bus_space_handle_t bsh; 691 bus_space_handle_t bsh;
689 uint32_t base; 692 uint32_t base;
690 int retry = 10000; 693 int retry = 10000;
691 694
692 tegra_car_get_bs(&bst, &bsh); 695 tegra_car_get_bs(&bst, &bsh);
693 696
694 /* Enter reset, enable clock */ 697 /* Enter reset, enable clock */
695 bus_space_write_4(bst, bsh, CAR_RST_DEV_H_SET_REG, CAR_DEV_H_HDMI); 698 bus_space_write_4(bst, bsh, CAR_RST_DEV_H_SET_REG, CAR_DEV_H_HDMI);
696 bus_space_write_4(bst, bsh, CAR_CLK_ENB_H_SET_REG, CAR_DEV_H_HDMI); 699 bus_space_write_4(bst, bsh, CAR_CLK_ENB_H_SET_REG, CAR_DEV_H_HDMI);
697 700
698 /* Change IDDQ from 1 to 0 */ 701 /* Change IDDQ from 1 to 0 */
699 tegra_reg_set_clear(bst, bsh, CAR_PLLD2_BASE_REG, 702 tegra_reg_set_clear(bst, bsh, CAR_PLLD2_BASE_REG,
700 0, CAR_PLLD2_BASE_IDDQ); 703 0, CAR_PLLD2_BASE_IDDQ);
701 delay(2); 704 delay(2);
702 /* Enable lock */ 705 /* Enable lock */
703 tegra_reg_set_clear(bst, bsh, CAR_PLLD2_MISC_REG, 706 tegra_reg_set_clear(bst, bsh, CAR_PLLD2_MISC_REG,
704 CAR_PLLD2_MISC_LOCK_ENABLE, 0); 707 CAR_PLLD2_MISC_LOCK_ENABLE, 0);
705 /* Enable PLLD2 */ 708 /* Enable PLLD2 */
706 tegra_reg_set_clear(bst, bsh, CAR_PLLD2_BASE_REG, 709 tegra_reg_set_clear(bst, bsh, CAR_PLLD2_BASE_REG,
707 CAR_PLLD2_BASE_ENABLE, 0); 710 CAR_PLLD2_BASE_ENABLE, 0);
708 711
709 /* Wait for lock */ 712 /* Wait for lock */
710 do { 713 do {
711 delay(2); 714 delay(2);
712 base = bus_space_read_4(bst, bsh, CAR_PLLD2_BASE_REG); 715 base = bus_space_read_4(bst, bsh, CAR_PLLD2_BASE_REG);
713 } while ((base & CAR_PLLD2_BASE_LOCK) == 0 && --retry > 0); 716 } while ((base & CAR_PLLD2_BASE_LOCK) == 0 && --retry > 0);
714 delay(100); 717 delay(100);
715 if (retry == 0) { 718 if (retry == 0) {
716 printf("WARNING: timeout waiting for PLLD2 lock\n"); 719 printf("WARNING: timeout waiting for PLLD2 lock\n");
717 } 720 }
718 721
719 /* Set clock source to PLLD2 */ 722 /* Set clock source to PLLD2 */
720 const u_int div = (tegra_car_plld2_rate() * 2) / rate - 2; 723 const u_int div = (tegra_car_plld2_rate() * 2) / rate - 2;
721 bus_space_write_4(bst, bsh, CAR_CLKSRC_HDMI_REG, 724 bus_space_write_4(bst, bsh, CAR_CLKSRC_HDMI_REG,
722 __SHIFTIN(CAR_CLKSRC_HDMI_SRC_PLLD2_OUT0, CAR_CLKSRC_HDMI_SRC) | 725 __SHIFTIN(CAR_CLKSRC_HDMI_SRC_PLLD2_OUT0, CAR_CLKSRC_HDMI_SRC) |
723 __SHIFTIN(div, CAR_CLKSRC_HDMI_DIV)); 726 __SHIFTIN(div, CAR_CLKSRC_HDMI_DIV));
724 727
725 /* Leave reset */ 728 /* Leave reset */
726 bus_space_write_4(bst, bsh, CAR_RST_DEV_H_CLR_REG, CAR_DEV_H_HDMI); 729 bus_space_write_4(bst, bsh, CAR_RST_DEV_H_CLR_REG, CAR_DEV_H_HDMI);
727} 730}
728 731
729int 732int
730tegra_car_dc_enable(u_int port) 733tegra_car_dc_enable(u_int port)
731{ 734{
732 bus_space_tag_t bst; 735 bus_space_tag_t bst;
733 bus_space_handle_t bsh; 736 bus_space_handle_t bsh;
734 bus_size_t src_reg; 737 bus_size_t src_reg;
735 uint32_t dev_bit; 738 uint32_t dev_bit;
736 u_int partid; 739 u_int partid;
737 740
738 tegra_car_get_bs(&bst, &bsh); 741 tegra_car_get_bs(&bst, &bsh);
739 742
740 switch (port) { 743 switch (port) {
741 case 0: 744 case 0:
742 dev_bit = CAR_DEV_L_DISP1; 745 dev_bit = CAR_DEV_L_DISP1;
743 src_reg = CAR_CLKSRC_DISP1_REG; 746 src_reg = CAR_CLKSRC_DISP1_REG;
744 partid = PMC_PARTID_DIS; 747 partid = PMC_PARTID_DIS;
745 break; 748 break;
746 case 1: 749 case 1:
747 dev_bit = CAR_DEV_L_DISP2; 750 dev_bit = CAR_DEV_L_DISP2;
748 src_reg = CAR_CLKSRC_DISP2_REG; 751 src_reg = CAR_CLKSRC_DISP2_REG;
749 partid = PMC_PARTID_DISB; 752 partid = PMC_PARTID_DISB;
750 break; 753 break;
751 default: 754 default:
752 return EINVAL; 755 return EINVAL;
753 } 756 }
754 757
755 /* Enter reset, enable clock */ 758 /* Enter reset, enable clock */
756 bus_space_write_4(bst, bsh, CAR_RST_DEV_L_SET_REG, dev_bit); 759 bus_space_write_4(bst, bsh, CAR_RST_DEV_L_SET_REG, dev_bit);
757 bus_space_write_4(bst, bsh, CAR_CLK_ENB_L_SET_REG, dev_bit); 760 bus_space_write_4(bst, bsh, CAR_CLK_ENB_L_SET_REG, dev_bit);
758 761
759 /* Turn on power to display partition */ 762 /* Turn on power to display partition */
760 tegra_pmc_power(partid, true); 763 tegra_pmc_power(partid, true);
761 tegra_pmc_remove_clamping(partid); 764 tegra_pmc_remove_clamping(partid);
762 765
763 /* Select PLLD2 for clock source */ 766 /* Select PLLD2 for clock source */
764 bus_space_write_4(bst, bsh, src_reg, 767 bus_space_write_4(bst, bsh, src_reg,
765 __SHIFTIN(CAR_CLKSRC_DISP_SRC_PLLD2_OUT0, 768 __SHIFTIN(CAR_CLKSRC_DISP_SRC_PLLD2_OUT0,
766 CAR_CLKSRC_DISP_SRC)); 769 CAR_CLKSRC_DISP_SRC));
767 770
768 /* Leave reset */ 771 /* Leave reset */
769 bus_space_write_4(bst, bsh, CAR_RST_DEV_L_CLR_REG, dev_bit); 772 bus_space_write_4(bst, bsh, CAR_RST_DEV_L_CLR_REG, dev_bit);
770 773
771 return 0; 774 return 0;
772} 775}
773 776
774void 777void
775tegra_car_host1x_enable(void) 778tegra_car_host1x_enable(void)
776{ 779{
777 bus_space_tag_t bst; 780 bus_space_tag_t bst;
778 bus_space_handle_t bsh; 781 bus_space_handle_t bsh;
779 782
780 tegra_car_get_bs(&bst, &bsh); 783 tegra_car_get_bs(&bst, &bsh);
781 784
782 /* Enter reset, enable clock */ 785 /* Enter reset, enable clock */
783 bus_space_write_4(bst, bsh, CAR_RST_DEV_L_SET_REG, CAR_DEV_L_HOST1X); 786 bus_space_write_4(bst, bsh, CAR_RST_DEV_L_SET_REG, CAR_DEV_L_HOST1X);
784 bus_space_write_4(bst, bsh, CAR_CLK_ENB_L_SET_REG, CAR_DEV_L_HOST1X); 787 bus_space_write_4(bst, bsh, CAR_CLK_ENB_L_SET_REG, CAR_DEV_L_HOST1X);
785 788
786 /* Select PLLP for clock source, 408 MHz */ 789 /* Select PLLP for clock source, 408 MHz */
787 bus_space_write_4(bst, bsh, CAR_CLKSRC_HOST1X_REG, 790 bus_space_write_4(bst, bsh, CAR_CLKSRC_HOST1X_REG,
788 __SHIFTIN(CAR_CLKSRC_HOST1X_SRC_PLLP_OUT0, 791 __SHIFTIN(CAR_CLKSRC_HOST1X_SRC_PLLP_OUT0,
789 CAR_CLKSRC_HOST1X_SRC) | 792 CAR_CLKSRC_HOST1X_SRC) |
790 __SHIFTIN(0, CAR_CLKSRC_HOST1X_CLK_DIVISOR)); 793 __SHIFTIN(0, CAR_CLKSRC_HOST1X_CLK_DIVISOR));
791 794
792 delay(2); 795 delay(2);
793 796
794 /* Leave reset */ 797 /* Leave reset */
795 bus_space_write_4(bst, bsh, CAR_RST_DEV_L_CLR_REG, CAR_DEV_L_HOST1X); 798 bus_space_write_4(bst, bsh, CAR_RST_DEV_L_CLR_REG, CAR_DEV_L_HOST1X);
796} 799}
797 800
798void 801void
799tegra_car_wdt_enable(u_int timer, bool enable) 802tegra_car_wdt_enable(u_int timer, bool enable)
800{ 803{
801 bus_space_tag_t bst; 804 bus_space_tag_t bst;
802 bus_space_handle_t bsh; 805 bus_space_handle_t bsh;
803 uint32_t enable_bits; 806 uint32_t enable_bits;
804 807
805 KASSERT(timer == 1 || timer == 2); 808 KASSERT(timer == 1 || timer == 2);
806 809
807 tegra_car_get_bs(&bst, &bsh); 810 tegra_car_get_bs(&bst, &bsh);
808 811
809 enable_bits = enable ? 812 enable_bits = enable ?
810 (CAR_RST_SOURCE_WDT_EN|CAR_RST_SOURCE_WDT_SYS_RST_EN) : 0; 813 (CAR_RST_SOURCE_WDT_EN|CAR_RST_SOURCE_WDT_SYS_RST_EN) : 0;
811 814
812 tegra_reg_set_clear(bst, bsh, CAR_RST_SOURCE_REG, 815 tegra_reg_set_clear(bst, bsh, CAR_RST_SOURCE_REG,
813 __SHIFTIN(timer - 1, CAR_RST_SOURCE_WDT_SEL) | 816 __SHIFTIN(timer - 1, CAR_RST_SOURCE_WDT_SEL) |
814 enable_bits, 817 enable_bits,
815 CAR_RST_SOURCE_WDT_SYS_RST_EN | 818 CAR_RST_SOURCE_WDT_SYS_RST_EN |
816 CAR_RST_SOURCE_WDT_SEL | 819 CAR_RST_SOURCE_WDT_SEL |
817 CAR_RST_SOURCE_WDT_EN); 820 CAR_RST_SOURCE_WDT_EN);
818} 821}
cvs diff -r1.19 -r1.20 src/sys/arch/arm/nvidia/Attic/tegra_carreg.h (switch to unified diff)

--- src/sys/arch/arm/nvidia/Attic/tegra_carreg.h 2015/07/23 15:07:31 1.19
+++ src/sys/arch/arm/nvidia/Attic/tegra_carreg.h 2015/07/25 15:50:42 1.20
@@ -1,465 +1,483 @@ @@ -1,465 +1,483 @@
1/* $NetBSD: tegra_carreg.h,v 1.19 2015/07/23 15:07:31 skrll Exp $ */ 1/* $NetBSD: tegra_carreg.h,v 1.20 2015/07/25 15:50:42 jmcneill Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
15 * 15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE. 26 * SUCH DAMAGE.
27 */ 27 */
28 28
29#ifndef _ARM_TEGRA_CARREG_H 29#ifndef _ARM_TEGRA_CARREG_H
30#define _ARM_TEGRA_CARREG_H 30#define _ARM_TEGRA_CARREG_H
31 31
32#define CAR_RST_SOURCE_REG 0x00 32#define CAR_RST_SOURCE_REG 0x00
33#define CAR_RST_SOURCE_WDT_EN __BIT(5) 33#define CAR_RST_SOURCE_WDT_EN __BIT(5)
34#define CAR_RST_SOURCE_WDT_SEL __BIT(4) 34#define CAR_RST_SOURCE_WDT_SEL __BIT(4)
35#define CAR_RST_SOURCE_WDT_SYS_RST_EN __BIT(2) 35#define CAR_RST_SOURCE_WDT_SYS_RST_EN __BIT(2)
36#define CAR_RST_SOURCE_WDT_COP_RST_EN __BIT(1) 36#define CAR_RST_SOURCE_WDT_COP_RST_EN __BIT(1)
37#define CAR_RST_SOURCE_WDT_CPU_RST_EN __BIT(0) 37#define CAR_RST_SOURCE_WDT_CPU_RST_EN __BIT(0)
38 38
39#define CAR_CLK_OUT_ENB_L_REG 0x10 39#define CAR_CLK_OUT_ENB_L_REG 0x10
40#define CAR_CLK_OUT_ENB_H_REG 0x14 40#define CAR_CLK_OUT_ENB_H_REG 0x14
41#define CAR_CLK_OUT_ENB_U_REG 0x18 41#define CAR_CLK_OUT_ENB_U_REG 0x18
42 42
43#define CAR_PLL_LFSR_REG 0x54 43#define CAR_PLL_LFSR_REG 0x54
44#define CAR_PLL_LFSR_RND __BITS(15,0) 44#define CAR_PLL_LFSR_RND __BITS(15,0)
45 45
46#define CAR_PLLP_BASE_REG 0xa0 46#define CAR_PLLP_BASE_REG 0xa0
47#define CAR_PLLP_BASE_BYPASS __BIT(31) 47#define CAR_PLLP_BASE_BYPASS __BIT(31)
48#define CAR_PLLP_BASE_ENABLE __BIT(30) 48#define CAR_PLLP_BASE_ENABLE __BIT(30)
49#define CAR_PLLP_BASE_REF_DIS __BIT(29) 49#define CAR_PLLP_BASE_REF_DIS __BIT(29)
50#define CAR_PLLP_BASE_OVERRIDE __BIT(28) 50#define CAR_PLLP_BASE_OVERRIDE __BIT(28)
51#define CAR_PLLP_BASE_LOCK __BIT(27) 51#define CAR_PLLP_BASE_LOCK __BIT(27)
52#define CAR_PLLP_BASE_DIVP __BITS(22,20) 52#define CAR_PLLP_BASE_DIVP __BITS(22,20)
53#define CAR_PLLP_BASE_DIVN __BITS(17,8) 53#define CAR_PLLP_BASE_DIVN __BITS(17,8)
54#define CAR_PLLP_BASE_DIVM __BITS(4,0) 54#define CAR_PLLP_BASE_DIVM __BITS(4,0)
55 55
56#define CAR_PLLP_OUTA_REG 0xa4 56#define CAR_PLLP_OUTA_REG 0xa4
57#define CAR_PLLP_OUTB_REG 0xa8 57#define CAR_PLLP_OUTB_REG 0xa8
58#define CAR_PLLP_OUTB_OUT4_RATIO __BITS(31,24) 58#define CAR_PLLP_OUTB_OUT4_RATIO __BITS(31,24)
59#define CAR_PLLP_OUTB_OUT4_OVRRIDE __BIT(18) 59#define CAR_PLLP_OUTB_OUT4_OVRRIDE __BIT(18)
60#define CAR_PLLP_OUTB_OUT4_CLKEN __BIT(17) 60#define CAR_PLLP_OUTB_OUT4_CLKEN __BIT(17)
61#define CAR_PLLP_OUTB_OUT4_RSTN __BIT(16) 61#define CAR_PLLP_OUTB_OUT4_RSTN __BIT(16)
62#define CAR_PLLP_OUTB_OUT3_RATIO __BITS(15,8) 62#define CAR_PLLP_OUTB_OUT3_RATIO __BITS(15,8)
63#define CAR_PLLP_OUTB_OUT3_OVRRIDE __BIT(2) 63#define CAR_PLLP_OUTB_OUT3_OVRRIDE __BIT(2)
64#define CAR_PLLP_OUTB_OUT3_CLKEN __BIT(1) 64#define CAR_PLLP_OUTB_OUT3_CLKEN __BIT(1)
65#define CAR_PLLP_OUTB_OUT3_RSTN __BIT(0) 65#define CAR_PLLP_OUTB_OUT3_RSTN __BIT(0)
66#define CAR_PLLP_MISC_REG 0xac 66#define CAR_PLLP_MISC_REG 0xac
67 67
68#define CAR_PLLC_BASE_REG 0x80 68#define CAR_PLLC_BASE_REG 0x80
69#define CAR_PLLC_BASE_ENABLE __BIT(30) 69#define CAR_PLLC_BASE_ENABLE __BIT(30)
70#define CAR_PLLC_BASE_REF_DIS __BIT(29) 70#define CAR_PLLC_BASE_REF_DIS __BIT(29)
71#define CAR_PLLC_BASE_LOCK_OVERRIDE __BIT(28) 71#define CAR_PLLC_BASE_LOCK_OVERRIDE __BIT(28)
72#define CAR_PLLC_BASE_LOCK __BIT(27) 72#define CAR_PLLC_BASE_LOCK __BIT(27)
73#define CAR_PLLC_BASE_DIVP __BITS(23,20) 73#define CAR_PLLC_BASE_DIVP __BITS(23,20)
74#define CAR_PLLC_BASE_DIVN __BITS(15,8) 74#define CAR_PLLC_BASE_DIVN __BITS(15,8)
75#define CAR_PLLC_BASE_DIVM __BITS(7,0) 75#define CAR_PLLC_BASE_DIVM __BITS(7,0)
76 76
77#define CAR_PLLU_BASE_REG 0xc0 77#define CAR_PLLU_BASE_REG 0xc0
78#define CAR_PLLU_BASE_BYPASS __BIT(31) 78#define CAR_PLLU_BASE_BYPASS __BIT(31)
79#define CAR_PLLU_BASE_ENABLE __BIT(30) 79#define CAR_PLLU_BASE_ENABLE __BIT(30)
80#define CAR_PLLU_BASE_REF_DIS __BIT(29) 80#define CAR_PLLU_BASE_REF_DIS __BIT(29)
81#define CAR_PLLU_BASE_LOCK __BIT(27) 81#define CAR_PLLU_BASE_LOCK __BIT(27)
82#define CAR_PLLU_BASE_CLKENABLE_48M __BIT(25) 82#define CAR_PLLU_BASE_CLKENABLE_48M __BIT(25)
83#define CAR_PLLU_BASE_OVERRIDE __BIT(24) 83#define CAR_PLLU_BASE_OVERRIDE __BIT(24)
84#define CAR_PLLU_BASE_CLKENABLE_ICUSB __BIT(23) 84#define CAR_PLLU_BASE_CLKENABLE_ICUSB __BIT(23)
85#define CAR_PLLU_BASE_CLKENABLE_HSIC __BIT(22) 85#define CAR_PLLU_BASE_CLKENABLE_HSIC __BIT(22)
86#define CAR_PLLU_BASE_CLKENABLE_USB __BIT(21) 86#define CAR_PLLU_BASE_CLKENABLE_USB __BIT(21)
87#define CAR_PLLU_BASE_VCO_FREQ __BIT(20) 87#define CAR_PLLU_BASE_VCO_FREQ __BIT(20)
88#define CAR_PLLU_BASE_DIVN __BITS(17,8) 88#define CAR_PLLU_BASE_DIVN __BITS(17,8)
89#define CAR_PLLU_BASE_DIVM __BITS(4,0) 89#define CAR_PLLU_BASE_DIVM __BITS(4,0)
90 90
91#define CAR_PLLD_BASE_REG 0xd0 91#define CAR_PLLD_BASE_REG 0xd0
92#define CAR_PLLD_BASE_BYPASS __BIT(31) 92#define CAR_PLLD_BASE_BYPASS __BIT(31)
93#define CAR_PLLD_BASE_ENABLE __BIT(30) 93#define CAR_PLLD_BASE_ENABLE __BIT(30)
94#define CAR_PLLD_BASE_REF_DIS __BIT(29) 94#define CAR_PLLD_BASE_REF_DIS __BIT(29)
95#define CAR_PLLD_BASE_LOCK __BIT(27) 95#define CAR_PLLD_BASE_LOCK __BIT(27)
96#define CAR_PLLD_BASE_CLKENABLE_CSI __BIT(26) 96#define CAR_PLLD_BASE_CLKENABLE_CSI __BIT(26)
97#define CAR_PLLD_BASE_DSIA_CLK_SRC __BIT(25) 97#define CAR_PLLD_BASE_DSIA_CLK_SRC __BIT(25)
98#define CAR_PLLD_BASE_CSI_CLK_SRC __BIT(23) 98#define CAR_PLLD_BASE_CSI_CLK_SRC __BIT(23)
99#define CAR_PLLD_BASE_DIVP __BITS(22,20) 99#define CAR_PLLD_BASE_DIVP __BITS(22,20)
100#define CAR_PLLD_BASE_DIVN __BITS(18,8) 100#define CAR_PLLD_BASE_DIVN __BITS(18,8)
101#define CAR_PLLD_BASE_DIVM __BITS(4,0) 101#define CAR_PLLD_BASE_DIVM __BITS(4,0)
102 102
103#define CAR_PLLD_MISC_REG 0xdc 103#define CAR_PLLD_MISC_REG 0xdc
104 104
105#define CAR_PLLX_BASE_REG 0xe0 105#define CAR_PLLX_BASE_REG 0xe0
106#define CAR_PLLX_BASE_BYPASS __BIT(31) 106#define CAR_PLLX_BASE_BYPASS __BIT(31)
107#define CAR_PLLX_BASE_ENABLE __BIT(30) 107#define CAR_PLLX_BASE_ENABLE __BIT(30)
108#define CAR_PLLX_BASE_REF_DIS __BIT(29) 108#define CAR_PLLX_BASE_REF_DIS __BIT(29)
109#define CAR_PLLX_BASE_LOCK __BIT(27) 109#define CAR_PLLX_BASE_LOCK __BIT(27)
110#define CAR_PLLX_BASE_DIVP __BITS(23,20) 110#define CAR_PLLX_BASE_DIVP __BITS(23,20)
111#define CAR_PLLX_BASE_DIVN __BITS(15,8) 111#define CAR_PLLX_BASE_DIVN __BITS(15,8)
112#define CAR_PLLX_BASE_DIVM __BITS(7,0) 112#define CAR_PLLX_BASE_DIVM __BITS(7,0)
113 113
114#define CAR_PLLX_MISC_REG 0xe4 114#define CAR_PLLX_MISC_REG 0xe4
115#define CAR_PLLX_MISC_FO_LP_DISABLE __BIT(29) 115#define CAR_PLLX_MISC_FO_LP_DISABLE __BIT(29)
116#define CAR_PLLX_MISC_FO_G_DISABLE __BIT(28) 116#define CAR_PLLX_MISC_FO_G_DISABLE __BIT(28)
117#define CAR_PLLX_MISC_PTS __BITS(23,22) 117#define CAR_PLLX_MISC_PTS __BITS(23,22)
118#define CAR_PLLX_MISC_LOCK_ENABLE __BIT(18) 118#define CAR_PLLX_MISC_LOCK_ENABLE __BIT(18)
119 119
120#define CAR_PLLE_BASE_REG 0xe8 120#define CAR_PLLE_BASE_REG 0xe8
121#define CAR_PLLE_BASE_ENABLE __BIT(30) 121#define CAR_PLLE_BASE_ENABLE __BIT(30)
122#define CAR_PLLE_BASE_LOCK_OVERRIDE __BIT(29) 122#define CAR_PLLE_BASE_LOCK_OVERRIDE __BIT(29)
123#define CAR_PLLE_BASE_FDIV48 __BIT(28) 123#define CAR_PLLE_BASE_FDIV48 __BIT(28)
124#define CAR_PLLE_BASE_DIVP_CML __BITS(27,24) 124#define CAR_PLLE_BASE_DIVP_CML __BITS(27,24)
125#define CAR_PLLE_BASE_EXT_SETUP_23_16 __BITS(23,16) 125#define CAR_PLLE_BASE_EXT_SETUP_23_16 __BITS(23,16)
126#define CAR_PLLE_BASE_DIVN __BITS(15,8) 126#define CAR_PLLE_BASE_DIVN __BITS(15,8)
127#define CAR_PLLE_BASE_DIVM __BITS(7,0) 127#define CAR_PLLE_BASE_DIVM __BITS(7,0)
128 128
129#define CAR_PLLE_MISC_REG 0xec 129#define CAR_PLLE_MISC_REG 0xec
130 130
131#define CAR_PLLD2_BASE_REG 0x4b8 131#define CAR_PLLD2_BASE_REG 0x4b8
132#define CAR_PLLD2_BASE_BYPASS __BIT(31) 132#define CAR_PLLD2_BASE_BYPASS __BIT(31)
133#define CAR_PLLD2_BASE_ENABLE __BIT(30) 133#define CAR_PLLD2_BASE_ENABLE __BIT(30)
134#define CAR_PLLD2_BASE_REF_DIS __BIT(29) 134#define CAR_PLLD2_BASE_REF_DIS __BIT(29)
135#define CAR_PLLD2_BASE_FREQLOCK __BIT(28) 135#define CAR_PLLD2_BASE_FREQLOCK __BIT(28)
136#define CAR_PLLD2_BASE_LOCK __BIT(27) 136#define CAR_PLLD2_BASE_LOCK __BIT(27)
137#define CAR_PLLD2_BASE_REF_SRC_SEL __BITS(26,25) 137#define CAR_PLLD2_BASE_REF_SRC_SEL __BITS(26,25)
138#define CAR_PLLD2_BASE_REF_SRC_SEL_PLL_D 0 138#define CAR_PLLD2_BASE_REF_SRC_SEL_PLL_D 0
139#define CAR_PLLD2_BASE_REF_SRC_SEL_PLL_D2 1 139#define CAR_PLLD2_BASE_REF_SRC_SEL_PLL_D2 1
140#define CAR_PLLD2_BASE_LOCK_OVERRIDE __BIT(24) 140#define CAR_PLLD2_BASE_LOCK_OVERRIDE __BIT(24)
141#define CAR_PLLD2_BASE_PLDIV __BITS(23,20) 141#define CAR_PLLD2_BASE_PLDIV __BITS(23,20)
142#define CAR_PLLD2_BASE_IDDQ __BIT(19) 142#define CAR_PLLD2_BASE_IDDQ __BIT(19)
143#define CAR_PLLD2_BASE_PTS __BIT(16) 143#define CAR_PLLD2_BASE_PTS __BIT(16)
144#define CAR_PLLD2_BASE_NDIV __BITS(15,8) 144#define CAR_PLLD2_BASE_NDIV __BITS(15,8)
145#define CAR_PLLD2_BASE_MDIV __BITS(7,0) 145#define CAR_PLLD2_BASE_MDIV __BITS(7,0)
146 146
147#define CAR_PLLD2_MISC_REG 0x4bc 147#define CAR_PLLD2_MISC_REG 0x4bc
148#define CAR_PLLD2_MISC_EN_FSTLCK __BIT(31) 148#define CAR_PLLD2_MISC_EN_FSTLCK __BIT(31)
149#define CAR_PLLD2_MISC_LOCK_ENABLE __BIT(30) 149#define CAR_PLLD2_MISC_LOCK_ENABLE __BIT(30)
150#define CAR_PLLD2_MISC_MON_TEST_OUT __BITS(29,27) 150#define CAR_PLLD2_MISC_MON_TEST_OUT __BITS(29,27)
151#define CAR_PLLD2_MISC_KCP __BITS(26,25) 151#define CAR_PLLD2_MISC_KCP __BITS(26,25)
152#define CAR_PLLD2_MISC_KVCO __BIT(24) 152#define CAR_PLLD2_MISC_KVCO __BIT(24)
153#define CAR_PLLD2_MISC_SETUP __BITS(23,0) 153#define CAR_PLLD2_MISC_SETUP __BITS(23,0)
154 154
155#define CAR_CLKSRC_I2C1_REG 0x124 155#define CAR_CLKSRC_I2C1_REG 0x124
156#define CAR_CLKSRC_I2C2_REG 0x198 156#define CAR_CLKSRC_I2C2_REG 0x198
157#define CAR_CLKSRC_I2C3_REG 0x1b8 157#define CAR_CLKSRC_I2C3_REG 0x1b8
158#define CAR_CLKSRC_I2C4_REG 0x3c4 158#define CAR_CLKSRC_I2C4_REG 0x3c4
159#define CAR_CLKSRC_I2C5_REG 0x128 159#define CAR_CLKSRC_I2C5_REG 0x128
160#define CAR_CLKSRC_I2C6_REG 0x65c 160#define CAR_CLKSRC_I2C6_REG 0x65c
161 161
162#define CAR_CLKSRC_I2C_SRC __BITS(31,29) 162#define CAR_CLKSRC_I2C_SRC __BITS(31,29)
163#define CAR_CLKSRC_I2C_SRC_PLLP_OUT0 0 163#define CAR_CLKSRC_I2C_SRC_PLLP_OUT0 0
164#define CAR_CLKSRC_I2C_SRC_PLLC2_OUT0 1 164#define CAR_CLKSRC_I2C_SRC_PLLC2_OUT0 1
165#define CAR_CLKSRC_I2C_SRC_PLLC_OUT0 2 165#define CAR_CLKSRC_I2C_SRC_PLLC_OUT0 2
166#define CAR_CLKSRC_I2C_SRC_PLLC3_OUT0 3 166#define CAR_CLKSRC_I2C_SRC_PLLC3_OUT0 3
167#define CAR_CLKSRC_I2C_SRC_PLLM_OUT0 4 167#define CAR_CLKSRC_I2C_SRC_PLLM_OUT0 4
168#define CAR_CLKSRC_I2C_SRC_CLK_M 6 168#define CAR_CLKSRC_I2C_SRC_CLK_M 6
169#define CAR_CLKSRC_I2C_DIV __BITS(15,0) 169#define CAR_CLKSRC_I2C_DIV __BITS(15,0)
170 170
171#define CAR_CLKSRC_UARTA_REG 0x178 171#define CAR_CLKSRC_UARTA_REG 0x178
172#define CAR_CLKSRC_UARTB_REG 0x17c 172#define CAR_CLKSRC_UARTB_REG 0x17c
173#define CAR_CLKSRC_UARTC_REG 0x1a0 173#define CAR_CLKSRC_UARTC_REG 0x1a0
174#define CAR_CLKSRC_UARTD_REG 0x1c0 174#define CAR_CLKSRC_UARTD_REG 0x1c0
175 175
176#define CAR_CLKSRC_UART_SRC __BITS(31,29) 176#define CAR_CLKSRC_UART_SRC __BITS(31,29)
177#define CAR_CLKSRC_UART_SRC_PLLP_OUT0 0 177#define CAR_CLKSRC_UART_SRC_PLLP_OUT0 0
178#define CAR_CLKSRC_UART_SRC_PLLC2_OUT0 1 178#define CAR_CLKSRC_UART_SRC_PLLC2_OUT0 1
179#define CAR_CLKSRC_UART_SRC_PLLC_OUT0 2 179#define CAR_CLKSRC_UART_SRC_PLLC_OUT0 2
180#define CAR_CLKSRC_UART_SRC_PLLC3_OUT0 3 180#define CAR_CLKSRC_UART_SRC_PLLC3_OUT0 3
181#define CAR_CLKSRC_UART_SRC_PLLM_OUT0 4 181#define CAR_CLKSRC_UART_SRC_PLLM_OUT0 4
182#define CAR_CLKSRC_UART_SRC_CLK_M 6 182#define CAR_CLKSRC_UART_SRC_CLK_M 6
183#define CAR_CLKSRC_UART_DIV_ENB __BIT(24) 183#define CAR_CLKSRC_UART_DIV_ENB __BIT(24)
184#define CAR_CLKSRC_UART_DIV __BITS(15,0) 184#define CAR_CLKSRC_UART_DIV __BITS(15,0)
185 185
186#define CAR_CLKSRC_SDMMC1_REG 0x150 186#define CAR_CLKSRC_SDMMC1_REG 0x150
187#define CAR_CLKSRC_SDMMC2_REG 0x154 187#define CAR_CLKSRC_SDMMC2_REG 0x154
188#define CAR_CLKSRC_SDMMC4_REG 0x164 188#define CAR_CLKSRC_SDMMC4_REG 0x164
189#define CAR_CLKSRC_SDMMC3_REG 0x1bc 189#define CAR_CLKSRC_SDMMC3_REG 0x1bc
190 190
191#define CAR_CLKSRC_SDMMC_SRC __BITS(31,29) 191#define CAR_CLKSRC_SDMMC_SRC __BITS(31,29)
192#define CAR_CLKSRC_SDMMC_SRC_PLLP_OUT0 0 192#define CAR_CLKSRC_SDMMC_SRC_PLLP_OUT0 0
193#define CAR_CLKSRC_SDMMC_SRC_PLLC2_OUT0 1 193#define CAR_CLKSRC_SDMMC_SRC_PLLC2_OUT0 1
194#define CAR_CLKSRC_SDMMC_SRC_PLLC_OUT0 2 194#define CAR_CLKSRC_SDMMC_SRC_PLLC_OUT0 2
195#define CAR_CLKSRC_SDMMC_SRC_PLLC3_OUT0 3 195#define CAR_CLKSRC_SDMMC_SRC_PLLC3_OUT0 3
196#define CAR_CLKSRC_SDMMC_SRC_PLLM_OUT0 4 196#define CAR_CLKSRC_SDMMC_SRC_PLLM_OUT0 4
197#define CAR_CLKSRC_SDMMC_SRC_PLLE_OUT0 5 197#define CAR_CLKSRC_SDMMC_SRC_PLLE_OUT0 5
198#define CAR_CLKSRC_SDMMC_SRC_CLK_M 6 198#define CAR_CLKSRC_SDMMC_SRC_CLK_M 6
199#define CAR_CLKSRC_SDMMC_DIV __BITS(7,0) 199#define CAR_CLKSRC_SDMMC_DIV __BITS(7,0)
200 200
201#define CAR_CLKSRC_HDMI_REG 0x18c 201#define CAR_CLKSRC_HDMI_REG 0x18c
202#define CAR_CLKSRC_HDMI_SRC __BITS(31,29) 202#define CAR_CLKSRC_HDMI_SRC __BITS(31,29)
203#define CAR_CLKSRC_HDMI_SRC_PLLP_OUT0 0 203#define CAR_CLKSRC_HDMI_SRC_PLLP_OUT0 0
204#define CAR_CLKSRC_HDMI_SRC_PLLM_OUT0 1 204#define CAR_CLKSRC_HDMI_SRC_PLLM_OUT0 1
205#define CAR_CLKSRC_HDMI_SRC_PLLD_OUT0 2 205#define CAR_CLKSRC_HDMI_SRC_PLLD_OUT0 2
206#define CAR_CLKSRC_HDMI_SRC_PLLA_OUT0 3 206#define CAR_CLKSRC_HDMI_SRC_PLLA_OUT0 3
207#define CAR_CLKSRC_HDMI_SRC_PLLC_OUT0 4 207#define CAR_CLKSRC_HDMI_SRC_PLLC_OUT0 4
208#define CAR_CLKSRC_HDMI_SRC_PLLD2_OUT0 5 208#define CAR_CLKSRC_HDMI_SRC_PLLD2_OUT0 5
209#define CAR_CLKSRC_HDMI_SRC_CLK_M 6 209#define CAR_CLKSRC_HDMI_SRC_CLK_M 6
210#define CAR_CLKSRC_HDMI_DIV __BITS(7,0) 210#define CAR_CLKSRC_HDMI_DIV __BITS(7,0)
211 211
212#define CAR_CLKSRC_DISP1_REG 0x138 212#define CAR_CLKSRC_DISP1_REG 0x138
213#define CAR_CLKSRC_DISP2_REG 0x13c 213#define CAR_CLKSRC_DISP2_REG 0x13c
214#define CAR_CLKSRC_DISP_SRC __BITS(31,29) 214#define CAR_CLKSRC_DISP_SRC __BITS(31,29)
215#define CAR_CLKSRC_DISP_SRC_PLLP_OUT0 0 215#define CAR_CLKSRC_DISP_SRC_PLLP_OUT0 0
216#define CAR_CLKSRC_DISP_SRC_PLLM_OUT0 1 216#define CAR_CLKSRC_DISP_SRC_PLLM_OUT0 1
217#define CAR_CLKSRC_DISP_SRC_PLLD_OUT0 2 217#define CAR_CLKSRC_DISP_SRC_PLLD_OUT0 2
218#define CAR_CLKSRC_DISP_SRC_PLLA_OUT0 3 218#define CAR_CLKSRC_DISP_SRC_PLLA_OUT0 3
219#define CAR_CLKSRC_DISP_SRC_PLLC_OUT0 4 219#define CAR_CLKSRC_DISP_SRC_PLLC_OUT0 4
220#define CAR_CLKSRC_DISP_SRC_PLLD2_OUT0 5 220#define CAR_CLKSRC_DISP_SRC_PLLD2_OUT0 5
221#define CAR_CLKSRC_DISP_SRC_CLK_M 6 221#define CAR_CLKSRC_DISP_SRC_CLK_M 6
222 222
223#define CAR_CLKSRC_HOST1X_REG 0x180 223#define CAR_CLKSRC_HOST1X_REG 0x180
224#define CAR_CLKSRC_HOST1X_SRC __BITS(31,29) 224#define CAR_CLKSRC_HOST1X_SRC __BITS(31,29)
225#define CAR_CLKSRC_HOST1X_SRC_PLLM_OUT0 0 225#define CAR_CLKSRC_HOST1X_SRC_PLLM_OUT0 0
226#define CAR_CLKSRC_HOST1X_SRC_PLLC2_OUT0 1 226#define CAR_CLKSRC_HOST1X_SRC_PLLC2_OUT0 1
227#define CAR_CLKSRC_HOST1X_SRC_PLLC_OUT0 2 227#define CAR_CLKSRC_HOST1X_SRC_PLLC_OUT0 2
228#define CAR_CLKSRC_HOST1X_SRC_PLLC3_OUT0 3 228#define CAR_CLKSRC_HOST1X_SRC_PLLC3_OUT0 3
229#define CAR_CLKSRC_HOST1X_SRC_PLLP_OUT0 4 229#define CAR_CLKSRC_HOST1X_SRC_PLLP_OUT0 4
230#define CAR_CLKSRC_HOST1X_SRC_PLLA_OUT0 6 230#define CAR_CLKSRC_HOST1X_SRC_PLLA_OUT0 6
231#define CAR_CLKSRC_HOST1X_IDLE_DIVISOR __BITS(15,8) 231#define CAR_CLKSRC_HOST1X_IDLE_DIVISOR __BITS(15,8)
232#define CAR_CLKSRC_HOST1X_CLK_DIVISOR __BITS(7,0) 232#define CAR_CLKSRC_HOST1X_CLK_DIVISOR __BITS(7,0)
233 233
234#define CAR_RST_DEV_L_SET_REG 0x300 234#define CAR_RST_DEV_L_SET_REG 0x300
235#define CAR_RST_DEV_L_CLR_REG 0x304 235#define CAR_RST_DEV_L_CLR_REG 0x304
236#define CAR_RST_DEV_H_SET_REG 0x308 236#define CAR_RST_DEV_H_SET_REG 0x308
237#define CAR_RST_DEV_H_CLR_REG 0x30c 237#define CAR_RST_DEV_H_CLR_REG 0x30c
238#define CAR_RST_DEV_U_SET_REG 0x310 238#define CAR_RST_DEV_U_SET_REG 0x310
239#define CAR_RST_DEV_U_CLR_REG 0x314 239#define CAR_RST_DEV_U_CLR_REG 0x314
240#define CAR_RST_DEV_V_SET_REG 0x430 240#define CAR_RST_DEV_V_SET_REG 0x430
241#define CAR_RST_DEV_V_CLR_REG 0x434 241#define CAR_RST_DEV_V_CLR_REG 0x434
242#define CAR_RST_DEV_W_SET_REG 0x438 242#define CAR_RST_DEV_W_SET_REG 0x438
243#define CAR_RST_DEV_W_CLR_REG 0x43c 243#define CAR_RST_DEV_W_CLR_REG 0x43c
244#define CAR_RST_DEV_X_SET_REG 0x290 244#define CAR_RST_DEV_X_SET_REG 0x290
245#define CAR_RST_DEV_X_CLR_REG 0x294 245#define CAR_RST_DEV_X_CLR_REG 0x294
246 246
247#define CAR_CLK_ENB_L_SET_REG 0x320 247#define CAR_CLK_ENB_L_SET_REG 0x320
248#define CAR_CLK_ENB_L_CLR_REG 0x324 248#define CAR_CLK_ENB_L_CLR_REG 0x324
249#define CAR_CLK_ENB_H_SET_REG 0x328 249#define CAR_CLK_ENB_H_SET_REG 0x328
250#define CAR_CLK_ENB_H_CLR_REG 0x32c 250#define CAR_CLK_ENB_H_CLR_REG 0x32c
251#define CAR_CLK_ENB_U_SET_REG 0x330 251#define CAR_CLK_ENB_U_SET_REG 0x330
252#define CAR_CLK_ENB_U_CLR_REG 0x334 252#define CAR_CLK_ENB_U_CLR_REG 0x334
253#define CAR_CLK_ENB_V_SET_REG 0x440 253#define CAR_CLK_ENB_V_SET_REG 0x440
254#define CAR_CLK_ENB_V_CLR_REG 0x444 254#define CAR_CLK_ENB_V_CLR_REG 0x444
255#define CAR_CLK_ENB_W_SET_REG 0x448 255#define CAR_CLK_ENB_W_SET_REG 0x448
256#define CAR_CLK_ENB_W_CLR_REG 0x44c 256#define CAR_CLK_ENB_W_CLR_REG 0x44c
257#define CAR_CLK_ENB_X_SET_REG 0x284 257#define CAR_CLK_ENB_X_SET_REG 0x284
258#define CAR_CLK_ENB_X_CLR_REG 0x288 258#define CAR_CLK_ENB_X_CLR_REG 0x288
259 259
260#define CAR_DEV_L_CACHE2 __BIT(31) 260#define CAR_DEV_L_CACHE2 __BIT(31)
261#define CAR_DEV_L_I2S0 __BIT(30) 261#define CAR_DEV_L_I2S0 __BIT(30)
262#define CAR_DEV_L_VCP __BIT(29) 262#define CAR_DEV_L_VCP __BIT(29)
263#define CAR_DEV_L_HOST1X __BIT(28) 263#define CAR_DEV_L_HOST1X __BIT(28)
264#define CAR_DEV_L_DISP1 __BIT(27) 264#define CAR_DEV_L_DISP1 __BIT(27)
265#define CAR_DEV_L_DISP2 __BIT(26) 265#define CAR_DEV_L_DISP2 __BIT(26)
266#define CAR_DEV_L_ISP __BIT(23) 266#define CAR_DEV_L_ISP __BIT(23)
267#define CAR_DEV_L_USBD __BIT(22) 267#define CAR_DEV_L_USBD __BIT(22)
268#define CAR_DEV_L_VI __BIT(20) 268#define CAR_DEV_L_VI __BIT(20)
269#define CAR_DEV_L_I2S2 __BIT(18) 269#define CAR_DEV_L_I2S2 __BIT(18)
270#define CAR_DEV_L_PWM __BIT(17) 270#define CAR_DEV_L_PWM __BIT(17)
271#define CAR_DEV_L_SDMMC4 __BIT(15) 271#define CAR_DEV_L_SDMMC4 __BIT(15)
272#define CAR_DEV_L_SDMMC1 __BIT(14) 272#define CAR_DEV_L_SDMMC1 __BIT(14)
273#define CAR_DEV_L_I2C1 __BIT(12) 273#define CAR_DEV_L_I2C1 __BIT(12)
274#define CAR_DEV_L_I2S1 __BIT(11) 274#define CAR_DEV_L_I2S1 __BIT(11)
275#define CAR_DEV_L_SPDIF __BIT(10) 275#define CAR_DEV_L_SPDIF __BIT(10)
276#define CAR_DEV_L_SDMMC2 __BIT(9) 276#define CAR_DEV_L_SDMMC2 __BIT(9)
277#define CAR_DEV_L_GPIO __BIT(8) 277#define CAR_DEV_L_GPIO __BIT(8)
278#define CAR_DEV_L_UARTB __BIT(7) 278#define CAR_DEV_L_UARTB __BIT(7)
279#define CAR_DEV_L_UARTA __BIT(6) 279#define CAR_DEV_L_UARTA __BIT(6)
280#define CAR_DEV_L_TMR __BIT(5 280#define CAR_DEV_L_TMR __BIT(5
281#define CAR_DEV_L_RTC __BIT(4) 281#define CAR_DEV_L_RTC __BIT(4)
282#define CAR_DEV_L_ISPB __BIT(3) 282#define CAR_DEV_L_ISPB __BIT(3)
283#define CAR_DEV_L_CPU __BIT(0) 283#define CAR_DEV_L_CPU __BIT(0)
284 284
285#define CAR_DEV_U_XUSB_DEV __BIT(31) 285#define CAR_DEV_U_XUSB_DEV __BIT(31)
286#define CAR_DEV_U_DEV1_OUT __BIT(30) 286#define CAR_DEV_U_DEV1_OUT __BIT(30)
287#define CAR_DEV_U_DEV2_OUT __BIT(29) 287#define CAR_DEV_U_DEV2_OUT __BIT(29)
288#define CAR_DEV_U_SUS_OUT __BIT(28) 288#define CAR_DEV_U_SUS_OUT __BIT(28)
289#define CAR_DEV_U_MSENC __BIT(27) 289#define CAR_DEV_U_MSENC __BIT(27)
290#define CAR_DEV_U_XUSB_HOST __BIT(25) 290#define CAR_DEV_U_XUSB_HOST __BIT(25)
291#define CAR_DEV_U_CRAM2 __BIT(24) 291#define CAR_DEV_U_CRAM2 __BIT(24)
292#define CAR_DEV_U_IRAMD __BIT(23) 292#define CAR_DEV_U_IRAMD __BIT(23)
293#define CAR_DEV_U_IRAMC __BIT(22) 293#define CAR_DEV_U_IRAMC __BIT(22)
294#define CAR_DEV_U_IRAMB __BIT(21) 294#define CAR_DEV_U_IRAMB __BIT(21)
295#define CAR_DEV_U_IRAMA __BIT(20) 295#define CAR_DEV_U_IRAMA __BIT(20)
296#define CAR_DEV_U_TSEC __BIT(19) 296#define CAR_DEV_U_TSEC __BIT(19)
297#define CAR_DEV_U_DSIB __BIT(18) 297#define CAR_DEV_U_DSIB __BIT(18)
298#define CAR_DEV_U_I2C_SLOW __BIT(17) 298#define CAR_DEV_U_I2C_SLOW __BIT(17)
299#define CAR_DEV_U_DTV __BIT(15) 299#define CAR_DEV_U_DTV __BIT(15)
300#define CAR_DEV_U_SOC_THERM __BIT(14) 300#define CAR_DEV_U_SOC_THERM __BIT(14)
301#define CAR_DEV_U_TRACECLKIN __BIT(13) 301#define CAR_DEV_U_TRACECLKIN __BIT(13)
302#define CAR_DEV_U_AVPUCQ __BIT(11) 302#define CAR_DEV_U_AVPUCQ __BIT(11)
303#define CAR_DEV_U_CSITE __BIT(9) 303#define CAR_DEV_U_CSITE __BIT(9)
304#define CAR_DEV_U_AFI __BIT(8) 304#define CAR_DEV_U_AFI __BIT(8)
305#define CAR_DEV_U_OWR __BIT(7) 305#define CAR_DEV_U_OWR __BIT(7)
306#define CAR_DEV_U_PCIE __BIT(6) 306#define CAR_DEV_U_PCIE __BIT(6)
307#define CAR_DEV_U_SDMMC3 __BIT(5) 307#define CAR_DEV_U_SDMMC3 __BIT(5)
308#define CAR_DEV_U_SPI4 __BIT(4) 308#define CAR_DEV_U_SPI4 __BIT(4)
309#define CAR_DEV_U_I2C3 __BIT(3) 309#define CAR_DEV_U_I2C3 __BIT(3)
310#define CAR_DEV_U_UARTD __BIT(1) 310#define CAR_DEV_U_UARTD __BIT(1)
311 311
312#define CAR_DEV_H_BSEV __BIT(31) 312#define CAR_DEV_H_BSEV __BIT(31)
313#define CAR_DEV_H_BSEA __BIT(30) 313#define CAR_DEV_H_BSEA __BIT(30)
314#define CAR_DEV_H_VDE __BIT(29) 314#define CAR_DEV_H_VDE __BIT(29)
315#define CAR_DEV_H_USB3 __BIT(27) 315#define CAR_DEV_H_USB3 __BIT(27)
316#define CAR_DEV_H_USB2 __BIT(26) 316#define CAR_DEV_H_USB2 __BIT(26)
317#define CAR_DEV_H_EMC __BIT(25) 317#define CAR_DEV_H_EMC __BIT(25)
318#define CAR_DEV_H_MIPI_CAL __BIT(24) 318#define CAR_DEV_H_MIPI_CAL __BIT(24)
319#define CAR_DEV_H_UARTC __BIT(23) 319#define CAR_DEV_H_UARTC __BIT(23)
320#define CAR_DEV_H_I2C2 __BIT(22) 320#define CAR_DEV_H_I2C2 __BIT(22)
321#define CAR_DEV_H_CSI __BIT(20) 321#define CAR_DEV_H_CSI __BIT(20)
322#define CAR_DEV_H_HDMI __BIT(19) 322#define CAR_DEV_H_HDMI __BIT(19)
323#define CAR_DEV_H_HSI __BIT(18) 323#define CAR_DEV_H_HSI __BIT(18)
324#define CAR_DEV_H_DSI __BIT(16) 324#define CAR_DEV_H_DSI __BIT(16)
325#define CAR_DEV_H_I2C5 __BIT(15) 325#define CAR_DEV_H_I2C5 __BIT(15)
326#define CAR_DEV_H_SPI3 __BIT(14) 326#define CAR_DEV_H_SPI3 __BIT(14)
327#define CAR_DEV_H_SPI2 __BIT(12) 327#define CAR_DEV_H_SPI2 __BIT(12)
328#define CAR_DEV_H_JTAG2TBC __BIT(11) 328#define CAR_DEV_H_JTAG2TBC __BIT(11)
329#define CAR_DEV_H_SNOR __BIT(10) 329#define CAR_DEV_H_SNOR __BIT(10)
330#define CAR_DEV_H_SPI1 __BIT(9) 330#define CAR_DEV_H_SPI1 __BIT(9)
331#define CAR_DEV_H_KFUSE __BIT(8) 331#define CAR_DEV_H_KFUSE __BIT(8)
332#define CAR_DEV_H_FUSE __BIT(7) 332#define CAR_DEV_H_FUSE __BIT(7)
333#define CAR_DEV_H_PMC __BIT(6) 333#define CAR_DEV_H_PMC __BIT(6)
334#define CAR_DEV_H_STAT_MON __BIT(5) 334#define CAR_DEV_H_STAT_MON __BIT(5)
335#define CAR_DEV_H_KBC __BIT(4) 335#define CAR_DEV_H_KBC __BIT(4)
336#define CAR_DEV_H_APBDMA __BIT(2) 336#define CAR_DEV_H_APBDMA __BIT(2)
337#define CAR_DEV_H_AHBDMA __BIT(1) 337#define CAR_DEV_H_AHBDMA __BIT(1)
338#define CAR_DEV_H_MEM __BIT(0) 338#define CAR_DEV_H_MEM __BIT(0)
339 339
340#define CAR_DEV_V_HDA __BIT(29) 340#define CAR_DEV_V_HDA __BIT(29)
341#define CAR_DEV_V_SATA __BIT(28) 341#define CAR_DEV_V_SATA __BIT(28)
342#define CAR_DEV_V_SATA_OOB __BIT(27) 342#define CAR_DEV_V_SATA_OOB __BIT(27)
343#define CAR_DEV_V_ACTMON __BIT(23) 343#define CAR_DEV_V_ACTMON __BIT(23)
344#define CAR_DEV_V_ATOMICS __BIT(16) 344#define CAR_DEV_V_ATOMICS __BIT(16)
345#define CAR_DEV_V_HDA2CODEC_2X __BIT(15) 345#define CAR_DEV_V_HDA2CODEC_2X __BIT(15)
346#define CAR_DEV_V_DAM2 __BIT(14) 346#define CAR_DEV_V_DAM2 __BIT(14)
347#define CAR_DEV_V_DAM1 __BIT(13) 347#define CAR_DEV_V_DAM1 __BIT(13)
348#define CAR_DEV_V_DAM0 __BIT(12) 348#define CAR_DEV_V_DAM0 __BIT(12)
349#define CAR_DEV_V_APBIF __BIT(11) 349#define CAR_DEV_V_APBIF __BIT(11)
350#define CAR_DEV_V_AUDIO __BIT(10) 350#define CAR_DEV_V_AUDIO __BIT(10)
351#define CAR_DEV_V_SPI6 __BIT(9) 351#define CAR_DEV_V_SPI6 __BIT(9)
352#define CAR_DEV_V_SPI5 __BIT(8) 352#define CAR_DEV_V_SPI5 __BIT(8)
353#define CAR_DEV_V_I2C4 __BIT(7) 353#define CAR_DEV_V_I2C4 __BIT(7)
354#define CAR_DEV_V_I2S4 __BIT(6) 354#define CAR_DEV_V_I2S4 __BIT(6)
355#define CAR_DEV_V_I2S3 __BIT(5) 355#define CAR_DEV_V_I2S3 __BIT(5)
356#define CAR_DEV_V_MSELECT __BIT(3) 356#define CAR_DEV_V_MSELECT __BIT(3)
357#define CAR_DEV_V_CPULP __BIT(1) 357#define CAR_DEV_V_CPULP __BIT(1)
358#define CAR_DEV_V_CPUG __BIT(0) 358#define CAR_DEV_V_CPUG __BIT(0)
359 359
360#define CAR_DEV_W_XUSB_SS __BIT(28) 360#define CAR_DEV_W_XUSB_SS __BIT(28)
361#define CAR_DEV_W_DVFS __BIT(27) 361#define CAR_DEV_W_DVFS __BIT(27)
362#define CAR_DEV_W_ADX0 __BIT(26) 362#define CAR_DEV_W_ADX0 __BIT(26)
363#define CAR_DEV_W_AMX0 __BIT(25) 363#define CAR_DEV_W_AMX0 __BIT(25)
364#define CAR_DEV_W_ENTROPY __BIT(21) 364#define CAR_DEV_W_ENTROPY __BIT(21)
365#define CAR_DEV_W_XUSB_PADCTL __BIT(14) 365#define CAR_DEV_W_XUSB_PADCTL __BIT(14)
366#define CAR_DEV_W_CEC __BIT(8) 366#define CAR_DEV_W_CEC __BIT(8)
367#define CAR_DEV_W_SATACOLD __BIT(1) 367#define CAR_DEV_W_SATACOLD __BIT(1)
368#define CAR_DEV_W_HDA2HDMICODEC __BIT(0) 368#define CAR_DEV_W_HDA2HDMICODEC __BIT(0)
369 369
370#define CAR_DEV_X_AMX1 __BIT(25) 370#define CAR_DEV_X_AMX1 __BIT(25)
371#define CAR_DEV_X_GPU __BIT(24) 371#define CAR_DEV_X_GPU __BIT(24)
372#define CAR_DEV_X_SOR0 __BIT(22) 372#define CAR_DEV_X_SOR0 __BIT(22)
373#define CAR_DEV_X_DPAUX __BIT(21) 373#define CAR_DEV_X_DPAUX __BIT(21)
374#define CAR_DEV_X_ADX1 __BIT(20) 374#define CAR_DEV_X_ADX1 __BIT(20)
375#define CAR_DEV_X_VIC __BIT(18) 375#define CAR_DEV_X_VIC __BIT(18)
376#define CAR_DEV_X_CLK72MHZ __BIT(17) 376#define CAR_DEV_X_CLK72MHZ __BIT(17)
377#define CAR_DEV_X_HDMI_AUDIO __BIT(16) 377#define CAR_DEV_X_HDMI_AUDIO __BIT(16)
378#define CAR_DEV_X_EMC_DLL __BIT(14) 378#define CAR_DEV_X_EMC_DLL __BIT(14)
379#define CAR_DEV_X_VIM2_CLK __BIT(11) 379#define CAR_DEV_X_VIM2_CLK __BIT(11)
380#define CAR_DEV_X_I2C6 __BIT(6) 380#define CAR_DEV_X_I2C6 __BIT(6)
381#define CAR_DEV_X_CAM_MCLK2 __BIT(5) 381#define CAR_DEV_X_CAM_MCLK2 __BIT(5)
382#define CAR_DEV_X_CAM_MCLK __BIT(4) 382#define CAR_DEV_X_CAM_MCLK __BIT(4)
383#define CAR_DEV_X_SPARE __BIT(0) 383#define CAR_DEV_X_SPARE __BIT(0)
384 384
385#define CAR_CCLKG_BURST_POLICY_REG 0x368 385#define CAR_CCLKG_BURST_POLICY_REG 0x368
386#define CAR_CCLKG_BURST_POLICY_CPU_STATE __BITS(31,28) 386#define CAR_CCLKG_BURST_POLICY_CPU_STATE __BITS(31,28)
387#define CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE 1 387#define CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE 1
388#define CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN 2 388#define CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN 2
389#define CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE __BITS(3,0) 389#define CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE __BITS(3,0)
390#define CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM 0 390#define CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM 0
391#define CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ 8 391#define CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ 8
392 392
 393#define CAR_CLKSRC_HDA2CODEC_2X_REG 0x3e4
 394#define CAR_CLKSRC_HDA2CODEC_2X_SRC __BITS(31,29)
 395#define CAR_CLKSRC_HDA2CODEC_2X_SRC_PLLP_OUT0 0
 396#define CAR_CLKSRC_HDA2CODEC_2X_SRC_PLLC2_OUT0 1
 397#define CAR_CLKSRC_HDA2CODEC_2X_SRC_PLLC_OUT0 2
 398#define CAR_CLKSRC_HDA2CODEC_2X_SRC_PLLC3_OUT0 3
 399#define CAR_CLKSRC_HDA2CODEC_2X_SRC_PLLM_OUT0 4
 400#define CAR_CLKSRC_HDA2CODEC_2X_SRC_CLKM 6
 401#define CAR_CLKSRC_HDA2CODEC_2X_DIV __BITS(7,0)
 402
393#define CAR_CLKSRC_SATA_OOB_REG 0x420 403#define CAR_CLKSRC_SATA_OOB_REG 0x420
394#define CAR_CLKSRC_SATA_OOB_SRC __BITS(31,29) 404#define CAR_CLKSRC_SATA_OOB_SRC __BITS(31,29)
395#define CAR_CLKSRC_SATA_OOB_SRC_PLLP_OUT0 0 405#define CAR_CLKSRC_SATA_OOB_SRC_PLLP_OUT0 0
396#define CAR_CLKSRC_SATA_OOB_SRC_PLLC_OUT0 2 406#define CAR_CLKSRC_SATA_OOB_SRC_PLLC_OUT0 2
397#define CAR_CLKSRC_SATA_OOB_SRC_PLLM_OUT0 4 407#define CAR_CLKSRC_SATA_OOB_SRC_PLLM_OUT0 4
398#define CAR_CLKSRC_SATA_OOB_SRC_CLKM 6 408#define CAR_CLKSRC_SATA_OOB_SRC_CLKM 6
399#define CAR_CLKSRC_SATA_OOB_DIV __BITS(7,0) 409#define CAR_CLKSRC_SATA_OOB_DIV __BITS(7,0)
400 410
401#define CAR_CLKSRC_SATA_REG 0x424 411#define CAR_CLKSRC_SATA_REG 0x424
402#define CAR_CLKSRC_SATA_SRC __BITS(31,29) 412#define CAR_CLKSRC_SATA_SRC __BITS(31,29)
403#define CAR_CLKSRC_SATA_SRC_PLLP_OUT0 0 413#define CAR_CLKSRC_SATA_SRC_PLLP_OUT0 0
404#define CAR_CLKSRC_SATA_SRC_PLLC_OUT0 2 414#define CAR_CLKSRC_SATA_SRC_PLLC_OUT0 2
405#define CAR_CLKSRC_SATA_SRC_PLLM_OUT0 4 415#define CAR_CLKSRC_SATA_SRC_PLLM_OUT0 4
406#define CAR_CLKSRC_SATA_SRC_CLKM 6 416#define CAR_CLKSRC_SATA_SRC_CLKM 6
407#define CAR_CLKSRC_SATA_AUX_CLK_ENB __BIT(24) 417#define CAR_CLKSRC_SATA_AUX_CLK_ENB __BIT(24)
408#define CAR_CLKSRC_SATA_DIV __BITS(7,0) 418#define CAR_CLKSRC_SATA_DIV __BITS(7,0)
409 419
410#define CAR_UTMIP_PLL_CFG0_REG 0x480 420#define CAR_UTMIP_PLL_CFG0_REG 0x480
411 421
412#define CAR_UTMIP_PLL_CFG1_REG 0x484 422#define CAR_UTMIP_PLL_CFG1_REG 0x484
413#define CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT __BITS(31,27) 423#define CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT __BITS(31,27)
414#define CAR_UTMIP_PLL_CFG1_PLLU_POWERUP __BIT(17) 424#define CAR_UTMIP_PLL_CFG1_PLLU_POWERUP __BIT(17)
415#define CAR_UTMIP_PLL_CFG1_PLLU_POWERDOWN __BIT(16) 425#define CAR_UTMIP_PLL_CFG1_PLLU_POWERDOWN __BIT(16)
416#define CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERUP __BIT(15) 426#define CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERUP __BIT(15)
417#define CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN __BIT(14) 427#define CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN __BIT(14)
418#define CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT __BITS(11,0) 428#define CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT __BITS(11,0)
419 429
420#define CAR_UTMIP_PLL_CFG2_REG 0x488 430#define CAR_UTMIP_PLL_CFG2_REG 0x488
421#define CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT __BITS(23,18) 431#define CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT __BITS(23,18)
422#define CAR_UTMIP_PLL_CFG2_STABLE_COUNT __BITS(17,6) 432#define CAR_UTMIP_PLL_CFG2_STABLE_COUNT __BITS(17,6)
423#define CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERUP __BIT(5) 433#define CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERUP __BIT(5)
424#define CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN __BIT(4) 434#define CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN __BIT(4)
425#define CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERUP __BIT(3) 435#define CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERUP __BIT(3)
426#define CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN __BIT(2) 436#define CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN __BIT(2)
427#define CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERUP __BIT(1) 437#define CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERUP __BIT(1)
428#define CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN __BIT(0) 438#define CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN __BIT(0)
429 439
430#define CAR_PLLE_AUX_REG 0x48c 440#define CAR_PLLE_AUX_REG 0x48c
431#define CAR_PLLE_AUX_SS_SEQ_INCLUDE __BIT(31) 441#define CAR_PLLE_AUX_SS_SEQ_INCLUDE __BIT(31)
432#define CAR_PLLE_AUX_REF_SEL_PLLREFE __BIT(28) 442#define CAR_PLLE_AUX_REF_SEL_PLLREFE __BIT(28)
433#define CAR_PLLE_AUX_SEQ_STATE __BITS(27,26) 443#define CAR_PLLE_AUX_SEQ_STATE __BITS(27,26)
434#define CAR_PLLE_AUX_SEQ_START_STATE __BIT(25) 444#define CAR_PLLE_AUX_SEQ_START_STATE __BIT(25)
435#define CAR_PLLE_AUX_SEQ_ENABLE __BIT(24) 445#define CAR_PLLE_AUX_SEQ_ENABLE __BIT(24)
436#define CAR_PLLE_AUX_SS_DLY __BITS(23,16) 446#define CAR_PLLE_AUX_SS_DLY __BITS(23,16)
437#define CAR_PLLE_AUX_LOCK_DLY __BITS(15,8) 447#define CAR_PLLE_AUX_LOCK_DLY __BITS(15,8)
438#define CAR_PLLE_AUX_FAST_PT __BIT(7) 448#define CAR_PLLE_AUX_FAST_PT __BIT(7)
439#define CAR_PLLE_AUX_SS_SWCTL __BIT(6) 449#define CAR_PLLE_AUX_SS_SWCTL __BIT(6)
440#define CAR_PLLE_AUX_CONFIG_SWCTL __BIT(5) 450#define CAR_PLLE_AUX_CONFIG_SWCTL __BIT(5)
441#define CAR_PLLE_AUX_ENABLE_SWCTL __BIT(4) 451#define CAR_PLLE_AUX_ENABLE_SWCTL __BIT(4)
442#define CAR_PLLE_AUX_USE_LOCKDET __BIT(3) 452#define CAR_PLLE_AUX_USE_LOCKDET __BIT(3)
443#define CAR_PLLE_AUX_REF_SRC __BIT(2) 453#define CAR_PLLE_AUX_REF_SRC __BIT(2)
444#define CAR_PLLE_AUX_CML1_OEN __BIT(1) 454#define CAR_PLLE_AUX_CML1_OEN __BIT(1)
445#define CAR_PLLE_AUX_CML0_OEN __BIT(0) 455#define CAR_PLLE_AUX_CML0_OEN __BIT(0)
446 456
447#define CAR_SATA_PLL_CFG0_REG 0x490 457#define CAR_SATA_PLL_CFG0_REG 0x490
448#define CAR_SATA_PLL_CFG0_SEQ_STATE __BITS(27,26) 458#define CAR_SATA_PLL_CFG0_SEQ_STATE __BITS(27,26)
449#define CAR_SATA_PLL_CFG0_SEQ_START_STATE __BIT(25) 459#define CAR_SATA_PLL_CFG0_SEQ_START_STATE __BIT(25)
450#define CAR_SATA_PLL_CFG0_SEQ_ENABLE __BIT(24) 460#define CAR_SATA_PLL_CFG0_SEQ_ENABLE __BIT(24)
451#define CAR_SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE __BIT(7) 461#define CAR_SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE __BIT(7)
452#define CAR_SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE __BIT(6) 462#define CAR_SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE __BIT(6)
453#define CAR_SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE __BIT(5) 463#define CAR_SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE __BIT(5)
454#define CAR_SATA_PLL_CFG0_SEQ_IN_SWCTL __BIT(4) 464#define CAR_SATA_PLL_CFG0_SEQ_IN_SWCTL __BIT(4)
455#define CAR_SATA_PLL_CFG0_PADPLL_USE_LOCKDET __BIT(2) 465#define CAR_SATA_PLL_CFG0_PADPLL_USE_LOCKDET __BIT(2)
456#define CAR_SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE __BIT(1) 466#define CAR_SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE __BIT(1)
457#define CAR_SATA_PLL_CFG0_PADPLL_RESET_SWCTL __BIT(0) 467#define CAR_SATA_PLL_CFG0_PADPLL_RESET_SWCTL __BIT(0)
458 468
459#define CAR_SATA_PLL_CFG1_REG 0x494 469#define CAR_SATA_PLL_CFG1_REG 0x494
460#define CAR_SATA_PLL_CFG1_LANE_IDDQ2_PADPLL_RESET_DLY __BITS(31,24) 470#define CAR_SATA_PLL_CFG1_LANE_IDDQ2_PADPLL_RESET_DLY __BITS(31,24)
461#define CAR_SATA_PLL_CFG1_PADPLL_IDDQ2LANE_SLUMBER_DLY __BITS(23,16) 471#define CAR_SATA_PLL_CFG1_PADPLL_IDDQ2LANE_SLUMBER_DLY __BITS(23,16)
462#define CAR_SATA_PLL_CFG1_PADPLL_PU_POST_DLY __BITS(15,8) 472#define CAR_SATA_PLL_CFG1_PADPLL_PU_POST_DLY __BITS(15,8)
463#define CAR_SATA_PLL_CFG1_LANE_IDDQ2_PADPLL_IDDQ_DLY __BITS(7,0) 473#define CAR_SATA_PLL_CFG1_LANE_IDDQ2_PADPLL_IDDQ_DLY __BITS(7,0)
464 474
 475#define CAR_CLKSRC_HDMI_AUDIO_REG 0x668
 476#define CAR_CLKSRC_HDMI_AUDIO_SRC __BITS(31,29)
 477#define CAR_CLKSRC_HDMI_AUDIO_SRC_PLLP_OUT0 0
 478#define CAR_CLKSRC_HDMI_AUDIO_SRC_PLLC_OUT0 1
 479#define CAR_CLKSRC_HDMI_AUDIO_SRC_PLLC2_OUT0 2
 480#define CAR_CLKSRC_HDMI_AUDIO_SRC_CLKM 3
 481#define CAR_CLKSRC_HDMI_AUDIO_DIV __BITS(7,0)
 482
465#endif /* _ARM_TEGRA_CARREG_H */ 483#endif /* _ARM_TEGRA_CARREG_H */
cvs diff -r1.5 -r1.6 src/sys/arch/arm/nvidia/Attic/tegra_hdmi.c (switch to unified diff)

--- src/sys/arch/arm/nvidia/Attic/tegra_hdmi.c 2015/07/23 15:43:06 1.5
+++ src/sys/arch/arm/nvidia/Attic/tegra_hdmi.c 2015/07/25 15:50:42 1.6
@@ -1,393 +1,540 @@ @@ -1,393 +1,540 @@
1/* $NetBSD: tegra_hdmi.c,v 1.5 2015/07/23 15:43:06 jmcneill Exp $ */ 1/* $NetBSD: tegra_hdmi.c,v 1.6 2015/07/25 15:50:42 jmcneill Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
15 * 15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE. 26 * SUCH DAMAGE.
27 */ 27 */
28 28
29#include "locators.h" 29#include "locators.h"
30 30
31#include <sys/cdefs.h> 31#include <sys/cdefs.h>
32__KERNEL_RCSID(0, "$NetBSD: tegra_hdmi.c,v 1.5 2015/07/23 15:43:06 jmcneill Exp $"); 32__KERNEL_RCSID(0, "$NetBSD: tegra_hdmi.c,v 1.6 2015/07/25 15:50:42 jmcneill Exp $");
33 33
34#include <sys/param.h> 34#include <sys/param.h>
35#include <sys/bus.h> 35#include <sys/bus.h>
36#include <sys/device.h> 36#include <sys/device.h>
37#include <sys/intr.h> 37#include <sys/intr.h>
38#include <sys/systm.h> 38#include <sys/systm.h>
39#include <sys/kernel.h> 39#include <sys/kernel.h>
40 40
41#include <dev/i2c/i2cvar.h> 41#include <dev/i2c/i2cvar.h>
42#include <dev/i2c/ddcvar.h> 42#include <dev/i2c/ddcvar.h>
43#include <dev/videomode/videomode.h> 43#include <dev/videomode/videomode.h>
44#include <dev/videomode/edidvar.h> 44#include <dev/videomode/edidvar.h>
45 45
46#include <arm/nvidia/tegra_reg.h> 46#include <arm/nvidia/tegra_reg.h>
47#include <arm/nvidia/tegra_hdmireg.h> 47#include <arm/nvidia/tegra_hdmireg.h>
48#include <arm/nvidia/tegra_var.h> 48#include <arm/nvidia/tegra_var.h>
49 49
50static int tegra_hdmi_match(device_t, cfdata_t, void *); 50static int tegra_hdmi_match(device_t, cfdata_t, void *);
51static void tegra_hdmi_attach(device_t, device_t, void *); 51static void tegra_hdmi_attach(device_t, device_t, void *);
52 52
53static const struct tegra_hdmi_tmds_config { 53static const struct tegra_hdmi_tmds_config {
54 u_int dot_clock; 54 u_int dot_clock;
55 uint32_t sor_pll0; 55 uint32_t sor_pll0;
56 uint32_t sor_pll1; 56 uint32_t sor_pll1;
57 uint32_t sor_lane_drive_current; 57 uint32_t sor_lane_drive_current;
58 uint32_t pe_current; 58 uint32_t pe_current;
59 uint32_t sor_io_peak_current; 59 uint32_t sor_io_peak_current;
60 uint32_t sor_pad_ctls0; 60 uint32_t sor_pad_ctls0;
61 uint32_t car_plld_misc; /* XXX unused? */ 61 uint32_t car_plld_misc; /* XXX unused? */
62} tegra_hdmi_tmds_config[] = { 62} tegra_hdmi_tmds_config[] = {
63 /* 480p */ 63 /* 480p */
64 { 27000, 0x01003010, 0x00301b00, 0x1f1f1f1f, 64 { 27000, 0x01003010, 0x00301b00, 0x1f1f1f1f,
65 0x00000000, 0x03030303, 0x800034bb, 0x40400820 }, 65 0x00000000, 0x03030303, 0x800034bb, 0x40400820 },
66 /* 720p / 1080i */ 66 /* 720p / 1080i */
67 { 74250, 0x01003110, 0x00301500, 0x2c2c2c2c, 67 { 74250, 0x01003110, 0x00301500, 0x2c2c2c2c,
68 0x00000000, 0x07070707, 0x800034bb, 0x40400820 }, 68 0x00000000, 0x07070707, 0x800034bb, 0x40400820 },
69 /* 1080p */ 69 /* 1080p */
70 { 148500, 0x01003310, 0x00301500, 0x2d2d2d2d, 70 { 148500, 0x01003310, 0x00301500, 0x2d2d2d2d,
71 0x00000000, 0x05050505, 0x800034bb, 0x40400820 }, 71 0x00000000, 0x05050505, 0x800034bb, 0x40400820 },
72 /* 2160p */ 72 /* 2160p */
73 { 297000, 0x01003f10, 0x00300f00, 0x37373737, 73 { 297000, 0x01003f10, 0x00300f00, 0x37373737,
74 0x00000000, 0x17171717, 0x800036bb, 0x40400f20 }, 74 0x00000000, 0x17171717, 0x800036bb, 0x40400f20 },
75}; 75};
76 76
77struct tegra_hdmi_softc { 77struct tegra_hdmi_softc {
78 device_t sc_dev; 78 device_t sc_dev;
79 bus_space_tag_t sc_bst; 79 bus_space_tag_t sc_bst;
80 bus_space_handle_t sc_bsh; 80 bus_space_handle_t sc_bsh;
81 81
82 device_t sc_displaydev; 82 device_t sc_displaydev;
83 device_t sc_ddcdev; 83 device_t sc_ddcdev;
84 struct tegra_gpio_pin *sc_pin_hpd; 84 struct tegra_gpio_pin *sc_pin_hpd;
85 struct tegra_gpio_pin *sc_pin_pll; 85 struct tegra_gpio_pin *sc_pin_pll;
86 struct tegra_gpio_pin *sc_pin_power; 86 struct tegra_gpio_pin *sc_pin_power;
87 87
88 bool sc_connected; 88 bool sc_connected;
89 const struct videomode *sc_curmode; 89 const struct videomode *sc_curmode;
 90 bool sc_hdmimode;
90}; 91};
91 92
92static void tegra_hdmi_hpd(struct tegra_hdmi_softc *); 93static void tegra_hdmi_hpd(struct tegra_hdmi_softc *);
93static void tegra_hdmi_connect(struct tegra_hdmi_softc *); 94static void tegra_hdmi_connect(struct tegra_hdmi_softc *);
94static void tegra_hdmi_disconnect(struct tegra_hdmi_softc *); 95static void tegra_hdmi_disconnect(struct tegra_hdmi_softc *);
95static void tegra_hdmi_enable(struct tegra_hdmi_softc *, const uint8_t *); 96static void tegra_hdmi_enable(struct tegra_hdmi_softc *, const uint8_t *);
96static int tegra_hdmi_sor_start(struct tegra_hdmi_softc *); 97static int tegra_hdmi_sor_start(struct tegra_hdmi_softc *);
 98static bool tegra_hdmi_is_hdmi(struct tegra_hdmi_softc *,
 99 const struct edid_info *);
 100static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi_softc *);
 101static uint8_t tegra_hdmi_infoframe_csum(const uint8_t *, size_t);
97 102
98CFATTACH_DECL_NEW(tegra_hdmi, sizeof(struct tegra_hdmi_softc), 103CFATTACH_DECL_NEW(tegra_hdmi, sizeof(struct tegra_hdmi_softc),
99 tegra_hdmi_match, tegra_hdmi_attach, NULL, NULL); 104 tegra_hdmi_match, tegra_hdmi_attach, NULL, NULL);
100 105
101#define HDMI_READ(sc, reg) \ 106#define HDMI_READ(sc, reg) \
102 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 107 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
103#define HDMI_WRITE(sc, reg, val) \ 108#define HDMI_WRITE(sc, reg, val) \
104 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 109 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
105#define HDMI_SET_CLEAR(sc, reg, set, clr) \ 110#define HDMI_SET_CLEAR(sc, reg, set, clr) \
106 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (set), (clr)) 111 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (set), (clr))
107 112
108static int 113static int
109tegra_hdmi_match(device_t parent, cfdata_t cf, void *aux) 114tegra_hdmi_match(device_t parent, cfdata_t cf, void *aux)
110{ 115{
111 return 1; 116 return 1;
112} 117}
113 118
114static void 119static void
115tegra_hdmi_attach(device_t parent, device_t self, void *aux) 120tegra_hdmi_attach(device_t parent, device_t self, void *aux)
116{ 121{
117 struct tegra_hdmi_softc * const sc = device_private(self); 122 struct tegra_hdmi_softc * const sc = device_private(self);
118 struct tegraio_attach_args * const tio = aux; 123 struct tegraio_attach_args * const tio = aux;
119 const struct tegra_locators * const loc = &tio->tio_loc; 124 const struct tegra_locators * const loc = &tio->tio_loc;
120 prop_dictionary_t prop = device_properties(self); 125 prop_dictionary_t prop = device_properties(self);
121 const char *pin, *dev; 126 const char *pin, *dev;
122 127
123 sc->sc_dev = self; 128 sc->sc_dev = self;
124 sc->sc_bst = tio->tio_bst; 129 sc->sc_bst = tio->tio_bst;
125 if (bus_space_map(sc->sc_bst, TEGRA_GHOST_BASE + loc->loc_offset, 130 if (bus_space_map(sc->sc_bst, TEGRA_GHOST_BASE + loc->loc_offset,
126 loc->loc_size, 0, &sc->sc_bsh) != 0) { 131 loc->loc_size, 0, &sc->sc_bsh) != 0) {
127 aprint_error(": couldn't map HDMI\n"); 132 aprint_error(": couldn't map HDMI\n");
128 return; 133 return;
129 } 134 }
130 135
131 if (prop_dictionary_get_cstring_nocopy(prop, "hpd-gpio", &pin)) { 136 if (prop_dictionary_get_cstring_nocopy(prop, "hpd-gpio", &pin)) {
132 sc->sc_pin_hpd = tegra_gpio_acquire(pin, GPIO_PIN_INPUT); 137 sc->sc_pin_hpd = tegra_gpio_acquire(pin, GPIO_PIN_INPUT);
133 } 138 }
134 if (prop_dictionary_get_cstring_nocopy(prop, "pll-gpio", &pin)) { 139 if (prop_dictionary_get_cstring_nocopy(prop, "pll-gpio", &pin)) {
135 sc->sc_pin_pll = tegra_gpio_acquire(pin, GPIO_PIN_OUTPUT); 140 sc->sc_pin_pll = tegra_gpio_acquire(pin, GPIO_PIN_OUTPUT);
136 if (sc->sc_pin_pll) { 141 if (sc->sc_pin_pll) {
137 tegra_gpio_write(sc->sc_pin_pll, 0); 142 tegra_gpio_write(sc->sc_pin_pll, 0);
138 } else { 143 } else {
139 panic("couldn't get pll-gpio pin"); 144 panic("couldn't get pll-gpio pin");
140 } 145 }
141 } 146 }
142 if (prop_dictionary_get_cstring_nocopy(prop, "power-gpio", &pin)) { 147 if (prop_dictionary_get_cstring_nocopy(prop, "power-gpio", &pin)) {
143 sc->sc_pin_power = tegra_gpio_acquire(pin, GPIO_PIN_OUTPUT); 148 sc->sc_pin_power = tegra_gpio_acquire(pin, GPIO_PIN_OUTPUT);
144 if (sc->sc_pin_power) { 149 if (sc->sc_pin_power) {
145 tegra_gpio_write(sc->sc_pin_power, 1); 150 tegra_gpio_write(sc->sc_pin_power, 1);
146 } 151 }
147 } 152 }
148 if (prop_dictionary_get_cstring_nocopy(prop, "ddc-device", &dev)) { 153 if (prop_dictionary_get_cstring_nocopy(prop, "ddc-device", &dev)) {
149 sc->sc_ddcdev = device_find_by_xname(dev); 154 sc->sc_ddcdev = device_find_by_xname(dev);
150 } 155 }
151 if (prop_dictionary_get_cstring_nocopy(prop, "display-device", &dev)) { 156 if (prop_dictionary_get_cstring_nocopy(prop, "display-device", &dev)) {
152 sc->sc_displaydev = device_find_by_xname(dev); 157 sc->sc_displaydev = device_find_by_xname(dev);
153 } 158 }
154 159
155 if (sc->sc_displaydev == NULL) { 160 if (sc->sc_displaydev == NULL) {
156 aprint_error(": no display-device property\n"); 161 aprint_error(": no display-device property\n");
157 return; 162 return;
158 } 163 }
159 164
160 aprint_naive("\n"); 165 aprint_naive("\n");
161 aprint_normal(": HDMI\n"); 166 aprint_normal(": HDMI\n");
162 167
163 tegra_hdmi_hpd(sc); 168 tegra_hdmi_hpd(sc);
164} 169}
165 170
166static void 171static void
167tegra_hdmi_hpd(struct tegra_hdmi_softc *sc) 172tegra_hdmi_hpd(struct tegra_hdmi_softc *sc)
168{ 173{
169 bool con; 174 bool con;
170 175
171 if (sc->sc_pin_hpd) { 176 if (sc->sc_pin_hpd) {
172 con = tegra_gpio_read(sc->sc_pin_hpd); 177 con = tegra_gpio_read(sc->sc_pin_hpd);
173 } else { 178 } else {
174 con = true; 179 con = true;
175 } 180 }
176 181
177 if (sc->sc_connected == con) 182 if (sc->sc_connected == con)
178 return; 183 return;
179 184
180 if (con) { 185 if (con) {
181 device_printf(sc->sc_dev, "display connected\n"); 186 device_printf(sc->sc_dev, "display connected\n");
182 tegra_hdmi_connect(sc); 187 tegra_hdmi_connect(sc);
183 } else { 188 } else {
184 device_printf(sc->sc_dev, "display disconnected\n"); 189 device_printf(sc->sc_dev, "display disconnected\n");
185 tegra_hdmi_disconnect(sc); 190 tegra_hdmi_disconnect(sc);
186 } 191 }
187 192
188 sc->sc_connected = con; 193 sc->sc_connected = con;
189} 194}
190 195
191static void 196static void
192tegra_hdmi_connect(struct tegra_hdmi_softc *sc) 197tegra_hdmi_connect(struct tegra_hdmi_softc *sc)
193{ 198{
194 const struct videomode *mode; 199 const struct videomode *mode;
195 char edid[128], *pedid = NULL; 200 char edid[128], *pedid = NULL;
196 struct edid_info ei; 201 struct edid_info ei;
197 int retry = 4, error; 202 int retry = 4, error;
198 203
199 memset(&ei, 0, sizeof(ei)); 204 memset(&ei, 0, sizeof(ei));
200 205
201 if (sc->sc_ddcdev) { 206 if (sc->sc_ddcdev) {
202 memset(edid, 0, sizeof(edid)); 207 memset(edid, 0, sizeof(edid));
203 208
204 while (--retry > 0) { 209 while (--retry > 0) {
205 error = ddc_dev_read_edid(sc->sc_ddcdev, edid, 210 error = ddc_dev_read_edid(sc->sc_ddcdev, edid,
206 sizeof(edid)); 211 sizeof(edid));
207 if (error == 0) { 212 if (error == 0) {
208 break; 213 break;
209 } 214 }
210 } 215 }
211 if (retry == 0) { 216 if (retry == 0) {
212 device_printf(sc->sc_dev, "failed to read EDID (%d)\n", 217 device_printf(sc->sc_dev, "failed to read EDID (%d)\n",
213 error); 218 error);
214 } else { 219 } else {
215 if (edid_parse(edid, &ei) != 0) { 220 if (edid_parse(edid, &ei) != 0) {
216 device_printf(sc->sc_dev, 221 device_printf(sc->sc_dev,
217 "failed to parse EDID\n"); 222 "failed to parse EDID\n");
218 } else { 223 } else {
219#ifdef TEGRA_HDMI_DEBUG 224#ifdef TEGRA_HDMI_DEBUG
220 edid_print(&ei); 225 edid_print(&ei);
221#endif 226#endif
222 pedid = edid; 227 pedid = edid;
223 } 228 }
224 } 229 }
225 } 230 }
226 231
227 mode = ei.edid_preferred_mode; 232 mode = ei.edid_preferred_mode;
228 if (mode == NULL) { 233 if (mode == NULL) {
229 mode = pick_mode_by_ref(640, 480, 60); 234 mode = pick_mode_by_ref(640, 480, 60);
230 } 235 }
231 236
232 sc->sc_curmode = mode; 237 sc->sc_curmode = mode;
 238 sc->sc_hdmimode = tegra_hdmi_is_hdmi(sc, &ei);
 239device_printf(sc->sc_dev, "connected to %s display\n", sc->sc_hdmimode ? "HDMI" : "DVI");
 240 if (sc->sc_hdmimode == false) {
 241 device_printf(sc->sc_dev, "forcing HDMI mode\n");
 242 sc->sc_hdmimode = true;
 243 }
 244
233 tegra_hdmi_enable(sc, pedid); 245 tegra_hdmi_enable(sc, pedid);
234} 246}
235 247
236static void 248static void
237tegra_hdmi_disconnect(struct tegra_hdmi_softc *sc) 249tegra_hdmi_disconnect(struct tegra_hdmi_softc *sc)
238{ 250{
239} 251}
240 252
241static void 253static void
242tegra_hdmi_enable(struct tegra_hdmi_softc *sc, const uint8_t *edid) 254tegra_hdmi_enable(struct tegra_hdmi_softc *sc, const uint8_t *edid)
243{ 255{
244 const struct tegra_hdmi_tmds_config *tmds = NULL; 256 const struct tegra_hdmi_tmds_config *tmds = NULL;
245 const struct videomode *mode = sc->sc_curmode; 257 const struct videomode *mode = sc->sc_curmode;
246 uint32_t input_ctrl; 258 uint32_t input_ctrl;
247 u_int n; 259 u_int i;
248 260
249 KASSERT(sc->sc_curmode != NULL); 261 KASSERT(sc->sc_curmode != NULL);
250 tegra_pmc_hdmi_enable(); 262 tegra_pmc_hdmi_enable();
251 263
252 tegra_car_hdmi_enable(mode->dot_clock * 1000); 264 tegra_car_hdmi_enable(mode->dot_clock * 1000);
253 265
254 for (n = 0; n < __arraycount(tegra_hdmi_tmds_config); n++) { 266 for (i = 0; i < __arraycount(tegra_hdmi_tmds_config); i++) {
255 if (tegra_hdmi_tmds_config[n].dot_clock >= mode->dot_clock) { 267 if (tegra_hdmi_tmds_config[i].dot_clock >= mode->dot_clock) {
256 break; 268 break;
257 } 269 }
258 } 270 }
259 if (n < __arraycount(tegra_hdmi_tmds_config)) { 271 if (i < __arraycount(tegra_hdmi_tmds_config)) {
260 tmds = &tegra_hdmi_tmds_config[n]; 272 tmds = &tegra_hdmi_tmds_config[i];
261 } else { 273 } else {
262 tmds = &tegra_hdmi_tmds_config[__arraycount(tegra_hdmi_tmds_config) - 1]; 274 tmds = &tegra_hdmi_tmds_config[__arraycount(tegra_hdmi_tmds_config) - 1];
263 } 275 }
264 if (tmds != NULL) { 276
265 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_PLL0_REG, tmds->sor_pll0); 277 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_PLL0_REG, tmds->sor_pll0);
266 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_PLL1_REG, tmds->sor_pll1); 278 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_PLL1_REG, tmds->sor_pll1);
267 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT_REG, 279 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT_REG,
268 tmds->sor_lane_drive_current); 280 tmds->sor_lane_drive_current);
269 HDMI_WRITE(sc, HDMI_NV_PDISP_PE_CURRENT_REG, tmds->pe_current); 281 HDMI_WRITE(sc, HDMI_NV_PDISP_PE_CURRENT_REG, tmds->pe_current);
270 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT_REG, 282 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT_REG,
271 tmds->sor_io_peak_current); 283 tmds->sor_io_peak_current);
272 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_PAD_CTLS0_REG, 284 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_PAD_CTLS0_REG,
273 tmds->sor_pad_ctls0); 285 tmds->sor_pad_ctls0);
274 } 
275 286
276 tegra_dc_enable(sc->sc_displaydev, sc->sc_dev, mode, edid); 287 tegra_dc_enable(sc->sc_displaydev, sc->sc_dev, mode, edid);
277 288
278 const u_int div = (mode->dot_clock / 1000) * 4; 289 const u_int div = (mode->dot_clock / 1000) * 4;
279 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_REFCLK_REG, 290 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_REFCLK_REG,
280 __SHIFTIN(div >> 2, HDMI_NV_PDISP_SOR_REFCLK_DIV_INT) | 291 __SHIFTIN(div >> 2, HDMI_NV_PDISP_SOR_REFCLK_DIV_INT) |
281 __SHIFTIN(div & 3, HDMI_NV_PDISP_SOR_REFCLK_DIV_FRAC)); 292 __SHIFTIN(div & 3, HDMI_NV_PDISP_SOR_REFCLK_DIV_FRAC));
282 293
283 HDMI_SET_CLEAR(sc, HDMI_NV_PDISP_SOR_CSTM_REG, 294 HDMI_SET_CLEAR(sc, HDMI_NV_PDISP_SOR_CSTM_REG,
284 __SHIFTIN(HDMI_NV_PDISP_SOR_CSTM_MODE_TMDS, 295 __SHIFTIN(HDMI_NV_PDISP_SOR_CSTM_MODE_TMDS,
285 HDMI_NV_PDISP_SOR_CSTM_MODE) | 296 HDMI_NV_PDISP_SOR_CSTM_MODE) |
286 __SHIFTIN(2, HDMI_NV_PDISP_SOR_CSTM_ROTCLK) | 297 __SHIFTIN(2, HDMI_NV_PDISP_SOR_CSTM_ROTCLK) |
287 HDMI_NV_PDISP_SOR_CSTM_PLLDIV, 298 HDMI_NV_PDISP_SOR_CSTM_PLLDIV,
288 HDMI_NV_PDISP_SOR_CSTM_MODE | 299 HDMI_NV_PDISP_SOR_CSTM_MODE |
289 HDMI_NV_PDISP_SOR_CSTM_ROTCLK | 300 HDMI_NV_PDISP_SOR_CSTM_ROTCLK |
290 HDMI_NV_PDISP_SOR_CSTM_LVDS_EN); 301 HDMI_NV_PDISP_SOR_CSTM_LVDS_EN);
291 302
292 const uint32_t inst = 303 const uint32_t inst =
293 HDMI_NV_PDISP_SOR_SEQ_INST_DRIVE_PWM_OUT_LO | 304 HDMI_NV_PDISP_SOR_SEQ_INST_DRIVE_PWM_OUT_LO |
294 HDMI_NV_PDISP_SOR_SEQ_INST_HALT | 305 HDMI_NV_PDISP_SOR_SEQ_INST_HALT |
295 __SHIFTIN(2, HDMI_NV_PDISP_SOR_SEQ_INST_WAIT_UNITS) | 306 __SHIFTIN(2, HDMI_NV_PDISP_SOR_SEQ_INST_WAIT_UNITS) |
296 __SHIFTIN(1, HDMI_NV_PDISP_SOR_SEQ_INST_WAIT_TIME); 307 __SHIFTIN(1, HDMI_NV_PDISP_SOR_SEQ_INST_WAIT_TIME);
297 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_SEQ_INST0_REG, inst); 308 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_SEQ_INST0_REG, inst);
298 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_SEQ_INST8_REG, inst); 309 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_SEQ_INST8_REG, inst);
299 310
300 input_ctrl = __SHIFTIN(tegra_dc_port(sc->sc_displaydev), 311 input_ctrl = __SHIFTIN(tegra_dc_port(sc->sc_displaydev),
301 HDMI_NV_PDISP_INPUT_CONTROL_HDMI_SRC_SELECT); 312 HDMI_NV_PDISP_INPUT_CONTROL_HDMI_SRC_SELECT);
302 if (mode->hdisplay != 640 || mode->vdisplay != 480) 313 if (mode->hdisplay != 640 || mode->vdisplay != 480)
303 input_ctrl |= HDMI_NV_PDISP_INPUT_CONTROL_ARM_VIDEO_RANGE; 314 input_ctrl |= HDMI_NV_PDISP_INPUT_CONTROL_ARM_VIDEO_RANGE;
304 HDMI_WRITE(sc, HDMI_NV_PDISP_INPUT_CONTROL_REG, input_ctrl); 315 HDMI_WRITE(sc, HDMI_NV_PDISP_INPUT_CONTROL_REG, input_ctrl);
305 316
306 if (tegra_hdmi_sor_start(sc) != 0) 317 if (tegra_hdmi_sor_start(sc) != 0)
307 return; 318 return;
308 319
309 const u_int rekey = 56; 320 const u_int rekey = 56;
310 const u_int hspw = mode->hsync_end - mode->hsync_start; 321 const u_int hspw = mode->hsync_end - mode->hsync_start;
311 const u_int hbp = mode->htotal - mode->hsync_end; 322 const u_int hbp = mode->htotal - mode->hsync_end;
312 const u_int hfp = mode->hsync_start - mode->hdisplay; 323 const u_int hfp = mode->hsync_start - mode->hdisplay;
313 const u_int max_ac_packet = (hspw + hbp + hfp - rekey - 18) / 32; 324 const u_int max_ac_packet = (hspw + hbp + hfp - rekey - 18) / 32;
314 uint32_t ctrl = 325 uint32_t ctrl =
315 __SHIFTIN(rekey, HDMI_NV_PDISP_HDMI_CTRL_REKEY) | 326 __SHIFTIN(rekey, HDMI_NV_PDISP_HDMI_CTRL_REKEY) |
316 __SHIFTIN(max_ac_packet, HDMI_NV_PDISP_HDMI_CTRL_MAX_AC_PACKET); 327 __SHIFTIN(max_ac_packet, HDMI_NV_PDISP_HDMI_CTRL_MAX_AC_PACKET);
317#if notyet 328 if (sc->sc_hdmimode) {
318 if (HDMI mode) { 
319 ctrl |= HDMI_NV_PDISP_HDMI_CTRL_ENABLE; /* HDMI ENABLE */ 329 ctrl |= HDMI_NV_PDISP_HDMI_CTRL_ENABLE; /* HDMI ENABLE */
320 } 330 }
321#endif 
322 HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_CTRL_REG, ctrl); 331 HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_CTRL_REG, ctrl);
323 332
324 /* XXX DVI */ 333 if (sc->sc_hdmimode) {
325 HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_GENERIC_CTRL_REG, 0); 334 const u_int n = 6144; /* 48 kHz */
326 HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_REG, 0); 335 const u_int cts = ((mode->dot_clock * 10) * (n / 128)) / 480;
327 HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_REG, 0); 336
 337 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_REG,
 338 __SHIFTIN(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO,
 339 HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SOURCE_SELECT) |
 340 HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_INJECT_NULLSMPL);
 341 HDMI_WRITE(sc, HDMI_NV_PDISP_AUDIO_N_REG,
 342 HDMI_NV_PDISP_AUDIO_N_RESETF |
 343 HDMI_NV_PDISP_AUDIO_N_GENERATE |
 344 __SHIFTIN(n - 1, HDMI_NV_PDISP_AUDIO_N_VALUE));
 345
 346 HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_SPARE_REG,
 347 HDMI_NV_PDISP_HDMI_SPARE_HW_CTS |
 348 HDMI_NV_PDISP_HDMI_SPARE_FORCE_SW_CTS |
 349 __SHIFTIN(1, HDMI_NV_PDISP_HDMI_SPARE_CTS_RESET_VAL));
 350
 351 /*
 352 * When HW_CTS=1 and FORCE_SW_CTS=1, the CTS is programmed by
 353 * software in the 44.1 kHz register regardless of chosen rate.
 354 */
 355 HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW_REG,
 356 cts << 8);
 357 HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH_REG,
 358 0x80000000 | n);
 359
 360 HDMI_SET_CLEAR(sc, HDMI_NV_PDISP_AUDIO_N_REG, 0,
 361 HDMI_NV_PDISP_AUDIO_N_RESETF);
 362
 363 HDMI_WRITE(sc, 24000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480_REG);
 364
 365 tegra_hdmi_setup_audio_infoframe(sc);
 366
 367 HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_GENERIC_CTRL_REG,
 368 HDMI_NV_PDISP_HDMI_GENERIC_CTRL_AUDIO);
 369 HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_REG, 0);
 370 HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_REG,
 371 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_ENABLE);
 372 HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_ACR_CTRL_REG, 0);
 373 } else {
 374 HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_GENERIC_CTRL_REG, 0);
 375 HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_REG, 0);
 376 HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_REG, 0);
 377 HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_ACR_CTRL_REG, 0);
 378 }
328 379
329 /* Start HDMI output */ 380 /* Start HDMI output */
330 tegra_dc_hdmi_start(sc->sc_displaydev); 381 tegra_dc_hdmi_start(sc->sc_displaydev);
331} 382}
332 383
333static int 384static int
334tegra_hdmi_sor_start(struct tegra_hdmi_softc *sc) 385tegra_hdmi_sor_start(struct tegra_hdmi_softc *sc)
335{ 386{
336 int retry; 387 int retry;
337 388
338 HDMI_SET_CLEAR(sc, HDMI_NV_PDISP_SOR_PLL0_REG, 389 HDMI_SET_CLEAR(sc, HDMI_NV_PDISP_SOR_PLL0_REG,
339 0, 390 0,
340 HDMI_NV_PDISP_SOR_PLL0_PWR | 391 HDMI_NV_PDISP_SOR_PLL0_PWR |
341 HDMI_NV_PDISP_SOR_PLL0_VCOPD | 392 HDMI_NV_PDISP_SOR_PLL0_VCOPD |
342 HDMI_NV_PDISP_SOR_PLL0_PULLDOWN); 393 HDMI_NV_PDISP_SOR_PLL0_PULLDOWN);
343 delay(10); 394 delay(10);
344 HDMI_SET_CLEAR(sc, HDMI_NV_PDISP_SOR_PLL0_REG, 395 HDMI_SET_CLEAR(sc, HDMI_NV_PDISP_SOR_PLL0_REG,
345 0, 396 0,
346 HDMI_NV_PDISP_SOR_PLL0_PDBG); 397 HDMI_NV_PDISP_SOR_PLL0_PDBG);
347 398
348 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_PWR_REG, 399 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_PWR_REG,
349 HDMI_NV_PDISP_SOR_PWR_NORMAL_STATE | 400 HDMI_NV_PDISP_SOR_PWR_NORMAL_STATE |
350 HDMI_NV_PDISP_SOR_PWR_SETTING_NEW); 401 HDMI_NV_PDISP_SOR_PWR_SETTING_NEW);
351 402
352 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_PWR_REG, 403 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_PWR_REG,
353 HDMI_NV_PDISP_SOR_PWR_NORMAL_STATE); 404 HDMI_NV_PDISP_SOR_PWR_NORMAL_STATE);
354 405
355 for (retry = 10000; retry > 0; retry--) { 406 for (retry = 10000; retry > 0; retry--) {
356 const uint32_t pwr = HDMI_READ(sc, HDMI_NV_PDISP_SOR_PWR_REG); 407 const uint32_t pwr = HDMI_READ(sc, HDMI_NV_PDISP_SOR_PWR_REG);
357 if ((pwr & HDMI_NV_PDISP_SOR_PWR_SETTING_NEW) == 0) 408 if ((pwr & HDMI_NV_PDISP_SOR_PWR_SETTING_NEW) == 0)
358 break; 409 break;
359 delay(10); 410 delay(10);
360 } 411 }
361 if (retry == 0) { 412 if (retry == 0) {
362 device_printf(sc->sc_dev, "timeout enabling SOR power\n"); 413 device_printf(sc->sc_dev, "timeout enabling SOR power\n");
363 return ETIMEDOUT; 414 return ETIMEDOUT;
364 } 415 }
365 416
366 uint32_t state2 = 417 uint32_t state2 =
367 __SHIFTIN(1, HDMI_NV_PDISP_SOR_STATE2_ASY_OWNER) | 418 __SHIFTIN(1, HDMI_NV_PDISP_SOR_STATE2_ASY_OWNER) |
368 __SHIFTIN(3, HDMI_NV_PDISP_SOR_STATE2_ASY_SUBOWNER) | 419 __SHIFTIN(3, HDMI_NV_PDISP_SOR_STATE2_ASY_SUBOWNER) |
369 __SHIFTIN(1, HDMI_NV_PDISP_SOR_STATE2_ASY_CRCMODE) | 420 __SHIFTIN(1, HDMI_NV_PDISP_SOR_STATE2_ASY_CRCMODE) |
370 __SHIFTIN(1, HDMI_NV_PDISP_SOR_STATE2_ASY_PROTOCOL); 421 __SHIFTIN(1, HDMI_NV_PDISP_SOR_STATE2_ASY_PROTOCOL);
371 if (sc->sc_curmode->flags & VID_NHSYNC) 422 if (sc->sc_curmode->flags & VID_NHSYNC)
372 state2 |= HDMI_NV_PDISP_SOR_STATE2_ASY_HSYNCPOL; 423 state2 |= HDMI_NV_PDISP_SOR_STATE2_ASY_HSYNCPOL;
373 if (sc->sc_curmode->flags & VID_NVSYNC) 424 if (sc->sc_curmode->flags & VID_NVSYNC)
374 state2 |= HDMI_NV_PDISP_SOR_STATE2_ASY_VSYNCPOL; 425 state2 |= HDMI_NV_PDISP_SOR_STATE2_ASY_VSYNCPOL;
375 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_STATE2_REG, state2); 426 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_STATE2_REG, state2);
376 427
377 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_STATE1_REG, 428 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_STATE1_REG,
378 __SHIFTIN(HDMI_NV_PDISP_SOR_STATE1_ASY_HEAD_OPMODE_AWAKE, 429 __SHIFTIN(HDMI_NV_PDISP_SOR_STATE1_ASY_HEAD_OPMODE_AWAKE,
379 HDMI_NV_PDISP_SOR_STATE1_ASY_HEAD_OPMODE) | 430 HDMI_NV_PDISP_SOR_STATE1_ASY_HEAD_OPMODE) |
380 HDMI_NV_PDISP_SOR_STATE1_ASY_ORMODE); 431 HDMI_NV_PDISP_SOR_STATE1_ASY_ORMODE);
381 432
382 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_STATE0_REG, 0); 433 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_STATE0_REG, 0);
383 434
384 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_STATE0_REG, 435 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_STATE0_REG,
385 HDMI_NV_PDISP_SOR_STATE0_UPDATE); 436 HDMI_NV_PDISP_SOR_STATE0_UPDATE);
386 437
387 HDMI_SET_CLEAR(sc, HDMI_NV_PDISP_SOR_STATE1_REG, 438 HDMI_SET_CLEAR(sc, HDMI_NV_PDISP_SOR_STATE1_REG,
388 HDMI_NV_PDISP_SOR_STATE1_ATTACHED, 0); 439 HDMI_NV_PDISP_SOR_STATE1_ATTACHED, 0);
389 440
390 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_STATE0_REG, 0); 441 HDMI_WRITE(sc, HDMI_NV_PDISP_SOR_STATE0_REG, 0);
391 442
392 return 0; 443 return 0;
393} 444}
 445
 446static bool
 447tegra_hdmi_is_hdmi(struct tegra_hdmi_softc *sc, const struct edid_info *ei)
 448{
 449 char edid[128];
 450 bool found_hdmi = false;
 451 unsigned int n, p;
 452
 453 /*
 454 * Scan through extension blocks, looking for a CEA-861-D v3
 455 * block. If an HDMI Vendor-Specific Data Block (HDMI VSDB) is
 456 * found in that, assume HDMI mode.
 457 */
 458 for (n = 1; n <= MIN(ei->edid_ext_block_count, 4); n++) {
 459 if (ddc_dev_read_edid_block(sc->sc_ddcdev, edid,
 460 sizeof(edid), n)) {
 461 break;
 462 }
 463
 464 const uint8_t tag = edid[0];
 465 const uint8_t rev = edid[1];
 466 const uint8_t off = edid[2];
 467
 468 /* We are looking for a CEA-861-D tag (02h) with revision 3 */
 469 if (tag != 0x02 || rev != 3)
 470 continue;
 471 /*
 472 * CEA data block collection starts at byte 4, so the
 473 * DTD blocks must start after it.
 474 */
 475 if (off <= 4)
 476 continue;
 477
 478 /* Parse the CEA data blocks */
 479 for (p = 4; p < off;) {
 480 const uint8_t btag = (edid[p] >> 5) & 0x7;
 481 const uint8_t blen = edid[p] & 0x1f;
 482
 483 /* Make sure the length is sane */
 484 if (p + blen + 1 > off)
 485 break;
 486 /* Looking for a VSDB tag */
 487 if (btag != 3)
 488 goto next_block;
 489 /* HDMI VSDB is at least 5 bytes long */
 490 if (blen < 5)
 491 goto next_block;
 492
 493 /* HDMI 24-bit IEEE registration ID is 0x000C03 */
 494 if (memcmp(&edid[p + 1], "\x03\x0c\x00", 3) == 0)
 495 found_hdmi = true;
 496
 497next_block:
 498 p += (1 + blen);
 499 }
 500 }
 501
 502 return found_hdmi;
 503}
 504
 505static void
 506tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi_softc *sc)
 507{
 508 uint8_t data[10] = {
 509 0x84, 0x01, 0x10,
 510 0x00, /* PB0 (checksum) */
 511 0x01, /* CT=0, CC=2ch */
 512 0xc0, /* SS=0, SF=48kHz */
 513 0x00, /* CA=FR/FL */
 514 0x00, /* LSV=0dB, DM_INH=permitted */
 515 0x00, 0x00
 516 };
 517
 518 data[3] = tegra_hdmi_infoframe_csum(data, sizeof(data));
 519
 520 HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER_REG,
 521 data[0] | (data[1] << 8) | (data[2] << 16));
 522 HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_REG,
 523 data[3] | (data[4] << 8) | (data[5] << 16) | (data[6] << 24));
 524 HDMI_WRITE(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_REG,
 525 data[7] | (data[8] << 8) | (data[9] << 16));
 526}
 527
 528static uint8_t
 529tegra_hdmi_infoframe_csum(const uint8_t *data, size_t len)
 530{
 531 uint8_t csum = 0;
 532 u_int n;
 533
 534 for (n = 0; n < len; n++)
 535 csum += data[n];
 536 if (csum)
 537 csum = 0x100 - csum;
 538
 539 return csum;
 540}
cvs diff -r1.3 -r1.4 src/sys/arch/arm/nvidia/tegra_hdmireg.h (switch to unified diff)

--- src/sys/arch/arm/nvidia/tegra_hdmireg.h 2015/07/23 15:08:19 1.3
+++ src/sys/arch/arm/nvidia/tegra_hdmireg.h 2015/07/25 15:50:42 1.4
@@ -1,304 +1,351 @@ @@ -1,304 +1,351 @@
1/* $NetBSD: tegra_hdmireg.h,v 1.3 2015/07/23 15:08:19 skrll Exp $ */ 1/* $NetBSD: tegra_hdmireg.h,v 1.4 2015/07/25 15:50:42 jmcneill Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
15 * 15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE. 26 * SUCH DAMAGE.
27 */ 27 */
28 28
29#ifndef _ARM_TEGRA_HDMIREG_H 29#ifndef _ARM_TEGRA_HDMIREG_H
30#define _ARM_TEGRA_HDMIREG_H 30#define _ARM_TEGRA_HDMIREG_H
31 31
32/* 32/*
33 * HDMI Registers 33 * HDMI Registers
34 */ 34 */
35#define HDMI_CTXSW_REG 0x000 35#define HDMI_CTXSW_REG 0x000
36 36
37#define HDMI_NV_PDISP_SOR_STATE0_REG 0x004 37#define HDMI_NV_PDISP_SOR_STATE0_REG 0x004
38#define HDMI_NV_PDISP_SOR_STATE0_UPDATE __BIT(0) 38#define HDMI_NV_PDISP_SOR_STATE0_UPDATE __BIT(0)
39 39
40#define HDMI_NV_PDISP_SOR_STATE1_REG 0x008 40#define HDMI_NV_PDISP_SOR_STATE1_REG 0x008
41#define HDMI_NV_PDISP_SOR_STATE1_ARM_SHOW_VGA __BIT(4) 41#define HDMI_NV_PDISP_SOR_STATE1_ARM_SHOW_VGA __BIT(4)
42#define HDMI_NV_PDISP_SOR_STATE1_ATTACHED __BIT(3) 42#define HDMI_NV_PDISP_SOR_STATE1_ATTACHED __BIT(3)
43#define HDMI_NV_PDISP_SOR_STATE1_ASY_ORMODE __BIT(2) 43#define HDMI_NV_PDISP_SOR_STATE1_ASY_ORMODE __BIT(2)
44#define HDMI_NV_PDISP_SOR_STATE1_ASY_HEAD_OPMODE __BITS(1,0) 44#define HDMI_NV_PDISP_SOR_STATE1_ASY_HEAD_OPMODE __BITS(1,0)
45#define HDMI_NV_PDISP_SOR_STATE1_ASY_HEAD_OPMODE_SLEEP 0 45#define HDMI_NV_PDISP_SOR_STATE1_ASY_HEAD_OPMODE_SLEEP 0
46#define HDMI_NV_PDISP_SOR_STATE1_ASY_HEAD_OPMODE_SNOOZE 1 46#define HDMI_NV_PDISP_SOR_STATE1_ASY_HEAD_OPMODE_SNOOZE 1
47#define HDMI_NV_PDISP_SOR_STATE1_ASY_HEAD_OPMODE_AWAKE 2 47#define HDMI_NV_PDISP_SOR_STATE1_ASY_HEAD_OPMODE_AWAKE 2
48 48
49#define HDMI_NV_PDISP_SOR_STATE2_REG 0x00c 49#define HDMI_NV_PDISP_SOR_STATE2_REG 0x00c
50#define HDMI_NV_PDISP_SOR_STATE2_ASY_DEPOL __BIT(14) 50#define HDMI_NV_PDISP_SOR_STATE2_ASY_DEPOL __BIT(14)
51#define HDMI_NV_PDISP_SOR_STATE2_ASY_VSYNCPOL __BIT(13) 51#define HDMI_NV_PDISP_SOR_STATE2_ASY_VSYNCPOL __BIT(13)
52#define HDMI_NV_PDISP_SOR_STATE2_ASY_HSYNCPOL __BIT(12) 52#define HDMI_NV_PDISP_SOR_STATE2_ASY_HSYNCPOL __BIT(12)
53#define HDMI_NV_PDISP_SOR_STATE2_ASY_PROTOCOL __BITS(11,8) 53#define HDMI_NV_PDISP_SOR_STATE2_ASY_PROTOCOL __BITS(11,8)
54#define HDMI_NV_PDISP_SOR_STATE2_ASY_CRCMODE __BITS(7,6) 54#define HDMI_NV_PDISP_SOR_STATE2_ASY_CRCMODE __BITS(7,6)
55#define HDMI_NV_PDISP_SOR_STATE2_ASY_SUBOWNER __BITS(5,4) 55#define HDMI_NV_PDISP_SOR_STATE2_ASY_SUBOWNER __BITS(5,4)
56#define HDMI_NV_PDISP_SOR_STATE2_ASY_OWNER __BITS(3,0) 56#define HDMI_NV_PDISP_SOR_STATE2_ASY_OWNER __BITS(3,0)
57 57
58#define HDMI_NV_PDISP_HDMI_AUDIO_EMU0_REG 0x068 58#define HDMI_NV_PDISP_HDMI_AUDIO_EMU0_REG 0x068
59#define HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0_REG 0x06c 59#define HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0_REG 0x06c
60#define HDMI_NV_PDISP_HDMI_AUDIO_EMU1_REG 0x070 60#define HDMI_NV_PDISP_HDMI_AUDIO_EMU1_REG 0x070
61#define HDMI_NV_PDISP_HDMI_AUDIO_EMU2_REG 0x074 61#define HDMI_NV_PDISP_HDMI_AUDIO_EMU2_REG 0x074
 62
62#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_REG 0x078 63#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_REG 0x078
 64#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_CHKSUM_HW __BIT(9)
 65#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_SINGLE __BIT(8)
 66#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_OTHER __BIT(4)
 67#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_ENABLE __BIT(0)
 68
63#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS_REG 0x07c 69#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS_REG 0x07c
64#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER_REG 0x080 70#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER_REG 0x080
65#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_REG 0x084 71#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_REG 0x084
66#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_REG 0x088 72#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_REG 0x088
 73
67#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_REG 0x08c 74#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_REG 0x08c
 75#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW __BIT(9)
 76#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_SINGLE __BIT(8)
 77#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_OTHER __BIT(4)
 78#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_ENABLE __BIT(0)
 79
68#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS_REG 0x090 80#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS_REG 0x090
69#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER_REG 0x094 81#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER_REG 0x094
70#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_REG 0x098 82#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_REG 0x098
71#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_REG 0x09c 83#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_REG 0x09c
72#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_REG 0x0a0 84#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_REG 0x0a0
73#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_REG 0x0a4 85#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_REG 0x0a4
 86
74#define HDMI_NV_PDISP_HDMI_GENERIC_CTRL_REG 0x0a8 87#define HDMI_NV_PDISP_HDMI_GENERIC_CTRL_REG 0x0a8
 88#define HDMI_NV_PDISP_HDMI_GENERIC_CTRL_AUDIO __BIT(16)
 89#define HDMI_NV_PDISP_HDMI_GENERIC_CTRL_HBLANK __BIT(12)
 90#define HDMI_NV_PDISP_HDMI_GENERIC_CTRL_SINGLE __BIT(8)
 91#define HDMI_NV_PDISP_HDMI_GENERIC_CTRL_OTHER __BIT(4)
 92#define HDMI_NV_PDISP_HDMI_GENERIC_CTRL_ENABLE __BIT(0)
 93
75#define HDMI_NV_PDISP_HDMI_GENERIC_STATUS_REG 0x0ac 94#define HDMI_NV_PDISP_HDMI_GENERIC_STATUS_REG 0x0ac
76#define HDMI_NV_PDISP_HDMI_GENERIC_HEADER_REG 0x0b0 95#define HDMI_NV_PDISP_HDMI_GENERIC_HEADER_REG 0x0b0
77#define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK0_LOW_REG 0x0b4 96#define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK0_LOW_REG 0x0b4
78#define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK0_HIGH_REG 0x0b8 97#define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK0_HIGH_REG 0x0b8
79#define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK1_LOW_REG 0x0bc 98#define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK1_LOW_REG 0x0bc
80#define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK1_HIGH_REG 0x0c0 99#define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK1_HIGH_REG 0x0c0
81#define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK2_LOW_REG 0x0c4 100#define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK2_LOW_REG 0x0c4
82#define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK2_HIGH_REG 0x0c8 101#define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK2_HIGH_REG 0x0c8
83#define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK3_LOW_REG 0x0cc 102#define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK3_LOW_REG 0x0cc
84#define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK3_HIGH_REG 0x0d0 103#define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK3_HIGH_REG 0x0d0
85#define HDMI_NV_PDISP_HDMI_ACR_CTRL_REG 0x0d4 104#define HDMI_NV_PDISP_HDMI_ACR_CTRL_REG 0x0d4
86#define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW_REG 0x0d8 105#define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW_REG 0x0d8
87#define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH_REG 0x0dc 106#define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH_REG 0x0dc
88#define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW_REG 0x0e0 107#define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW_REG 0x0e0
89#define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH_REG 0x0e4 108#define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH_REG 0x0e4
90#define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW_REG 0x0e8 109#define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW_REG 0x0e8
91#define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH_REG 0x0ec 110#define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH_REG 0x0ec
92#define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW_REG 0x0f0 111#define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW_REG 0x0f0
93#define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH_REG 0x0f4 112#define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH_REG 0x0f4
94#define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW_REG 0x0f8 113#define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW_REG 0x0f8
95#define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH_REG 0x0fc 114#define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH_REG 0x0fc
96#define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW_REG 0x100 115#define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW_REG 0x100
97#define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH_REG 0x104 116#define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH_REG 0x104
98#define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW_REG 0x108 117#define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW_REG 0x108
99#define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH_REG 0x10c 118#define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH_REG 0x10c
100 119
101#define HDMI_NV_PDISP_HDMI_CTRL_REG 0x110 120#define HDMI_NV_PDISP_HDMI_CTRL_REG 0x110
102#define HDMI_NV_PDISP_HDMI_CTRL_ENABLE __BIT(30) 121#define HDMI_NV_PDISP_HDMI_CTRL_ENABLE __BIT(30)
103#define HDMI_NV_PDISP_HDMI_CTRL_CA_SELECT __BIT(28) 122#define HDMI_NV_PDISP_HDMI_CTRL_CA_SELECT __BIT(28)
104#define HDMI_NV_PDISP_HDMI_CTRL_SS_SELECT __BIT(27) 123#define HDMI_NV_PDISP_HDMI_CTRL_SS_SELECT __BIT(27)
105#define HDMI_NV_PDISP_HDMI_CTRL_SF_SELECT __BIT(26) 124#define HDMI_NV_PDISP_HDMI_CTRL_SF_SELECT __BIT(26)
106#define HDMI_NV_PDISP_HDMI_CTRL_CC_SELECT __BIT(25) 125#define HDMI_NV_PDISP_HDMI_CTRL_CC_SELECT __BIT(25)
107#define HDMI_NV_PDISP_HDMI_CTRL_CT_SELECT __BIT(24) 126#define HDMI_NV_PDISP_HDMI_CTRL_CT_SELECT __BIT(24)
108#define HDMI_NV_PDISP_HDMI_CTRL_MAX_AC_PACKET __BITS(20,16) 127#define HDMI_NV_PDISP_HDMI_CTRL_MAX_AC_PACKET __BITS(20,16)
109#define HDMI_NV_PDISP_HDMI_CTRL_SAMPLE_FLAT __BIT(12) 128#define HDMI_NV_PDISP_HDMI_CTRL_SAMPLE_FLAT __BIT(12)
110#define HDMI_NV_PDISP_HDMI_CTRL_AUDIO_LAYOUT_SELECT __BIT(10) 129#define HDMI_NV_PDISP_HDMI_CTRL_AUDIO_LAYOUT_SELECT __BIT(10)
111#define HDMI_NV_PDISP_HDMI_CTRL_AUDIO_LAYOUT __BIT(8) 130#define HDMI_NV_PDISP_HDMI_CTRL_AUDIO_LAYOUT __BIT(8)
112#define HDMI_NV_PDISP_HDMI_CTRL_REKEY __BITS(6,0) 131#define HDMI_NV_PDISP_HDMI_CTRL_REKEY __BITS(6,0)
113 132
114#define HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT_REG 0x114 133#define HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT_REG 0x114
115#define HDMI_NV_PDISP_HDMI_VSYNC_WINDOW_REG 0x118 134#define HDMI_NV_PDISP_HDMI_VSYNC_WINDOW_REG 0x118
116#define HDMI_NV_PDISP_HDMI_GCP_CTRL_REG 0x11c 135#define HDMI_NV_PDISP_HDMI_GCP_CTRL_REG 0x11c
117#define HDMI_NV_PDISP_HDMI_GCP_STATUS_REG 0x120 136#define HDMI_NV_PDISP_HDMI_GCP_STATUS_REG 0x120
118#define HDMI_NV_PDISP_HDMI_GCP_SUBPACK_REG 0x124 137#define HDMI_NV_PDISP_HDMI_GCP_SUBPACK_REG 0x124
119#define HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1_REG 0x128 138#define HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1_REG 0x128
120#define HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2_REG 0x12c 139#define HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2_REG 0x12c
121#define HDMI_NV_PDISP_HDMI_EMU0_REG 0x130 140#define HDMI_NV_PDISP_HDMI_EMU0_REG 0x130
122#define HDMI_NV_PDISP_HDMI_EMU1_REG 0x134 141#define HDMI_NV_PDISP_HDMI_EMU1_REG 0x134
123#define HDMI_NV_PDISP_HDMI_EMU1_RDATA_REG 0x138 142#define HDMI_NV_PDISP_HDMI_EMU1_RDATA_REG 0x138
 143
124#define HDMI_NV_PDISP_HDMI_SPARE_REG 0x13c 144#define HDMI_NV_PDISP_HDMI_SPARE_REG 0x13c
 145#define HDMI_NV_PDISP_HDMI_SPARE_HW_CTS __BIT(0)
 146#define HDMI_NV_PDISP_HDMI_SPARE_FORCE_SW_CTS __BIT(1)
 147#define HDMI_NV_PDISP_HDMI_SPARE_CTS_RESET_VAL __BITS(18,16)
 148
125#define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1_REG 0x140 149#define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1_REG 0x140
126#define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STAUTS2_REG 0x144 150#define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STAUTS2_REG 0x144
127#define HDMI_NV_PDISP_CRC_CONTROL_REG 0x258 151#define HDMI_NV_PDISP_CRC_CONTROL_REG 0x258
128 152
129#define HDMI_NV_PDISP_INPUT_CONTROL_REG 0x25c 153#define HDMI_NV_PDISP_INPUT_CONTROL_REG 0x25c
130#define HDMI_NV_PDISP_INPUT_CONTROL_ARM_VIDEO_RANGE __BIT(1) 154#define HDMI_NV_PDISP_INPUT_CONTROL_ARM_VIDEO_RANGE __BIT(1)
131#define HDMI_NV_PDISP_INPUT_CONTROL_HDMI_SRC_SELECT __BIT(0) 155#define HDMI_NV_PDISP_INPUT_CONTROL_HDMI_SRC_SELECT __BIT(0)
132 156
133#define HDMI_NV_PDISP_SCRATCH_REG 0x260 157#define HDMI_NV_PDISP_SCRATCH_REG 0x260
134#define HDMI_NV_PDISP_PE_CURRENT_REG 0x264 158#define HDMI_NV_PDISP_PE_CURRENT_REG 0x264
135#define HDMI_NV_PDISP_KEY_CTRL_REG 0x268 159#define HDMI_NV_PDISP_KEY_CTRL_REG 0x268
136#define HDMI_NV_PDISP_KEY_DEBUG0_REG 0x26c 160#define HDMI_NV_PDISP_KEY_DEBUG0_REG 0x26c
137#define HDMI_NV_PDISP_KEY_DEBUG1_REG 0x270 161#define HDMI_NV_PDISP_KEY_DEBUG1_REG 0x270
138#define HDMI_NV_PDISP_KEY_DEBUG2_REG 0x274 162#define HDMI_NV_PDISP_KEY_DEBUG2_REG 0x274
139#define HDMI_NV_PDISP_KEY_HDCP_KEY_0_REG 0x278 163#define HDMI_NV_PDISP_KEY_HDCP_KEY_0_REG 0x278
140#define HDMI_NV_PDISP_KEY_HDCP_KEY_1_REG 0x27c 164#define HDMI_NV_PDISP_KEY_HDCP_KEY_1_REG 0x27c
141#define HDMI_NV_PDISP_KEY_HDCP_KEY_2_REG 0x280 165#define HDMI_NV_PDISP_KEY_HDCP_KEY_2_REG 0x280
142#define HDMI_NV_PDISP_KEY_HDCP_KEY_3_REG 0x284 166#define HDMI_NV_PDISP_KEY_HDCP_KEY_3_REG 0x284
143#define HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG_REG 0x288 167#define HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG_REG 0x288
144#define HDMI_NV_PDISP_KEY_SKEY_INDEX_REG 0x28c 168#define HDMI_NV_PDISP_KEY_SKEY_INDEX_REG 0x28c
145#define HDMI_NV_PDISP_INT_STATUS_REG 0x330 169#define HDMI_NV_PDISP_INT_STATUS_REG 0x330
146#define HDMI_NV_PDISP_INT_MASK_REG 0x334 170#define HDMI_NV_PDISP_INT_MASK_REG 0x334
147#define HDMI_NV_PDISP_INT_ENABLE_REG 0x338 171#define HDMI_NV_PDISP_INT_ENABLE_REG 0x338
148#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_CTRL_REG 0x358 172#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_CTRL_REG 0x358
149#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_STATUS_REG 0x35c 173#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_STATUS_REG 0x35c
150#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_HEADER_REG 0x360 174#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_HEADER_REG 0x360
151#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_REG 0x364 175#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_REG 0x364
152#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_REG 0x368 176#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_REG 0x368
153#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_REG 0x36c 177#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_REG 0x36c
154#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_REG 0x370 178#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_REG 0x370
155#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_REG 0x374 179#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_REG 0x374
156#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_REG 0x378 180#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_REG 0x378
157#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_REG 0x37c 181#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_REG 0x37c
158#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_REG 0x380 182#define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_REG 0x380
159 183
160/* 184/*
161 * Serial Output Resource Registers 185 * Serial Output Resource Registers
162 */ 186 */
163#define HDMI_NV_PDISP_SOR_PWR_REG 0x154 187#define HDMI_NV_PDISP_SOR_PWR_REG 0x154
164#define HDMI_NV_PDISP_SOR_PWR_SETTING_NEW __BIT(31) 188#define HDMI_NV_PDISP_SOR_PWR_SETTING_NEW __BIT(31)
165#define HDMI_NV_PDISP_SOR_PWR_MODE __BIT(28) 189#define HDMI_NV_PDISP_SOR_PWR_MODE __BIT(28)
166#define HDMI_NV_PDISP_SOR_PWR_HALT_DELAY __BIT(24) 190#define HDMI_NV_PDISP_SOR_PWR_HALT_DELAY __BIT(24)
167#define HDMI_NV_PDISP_SOR_PWR_SAFE_START __BIT(17) 191#define HDMI_NV_PDISP_SOR_PWR_SAFE_START __BIT(17)
168#define HDMI_NV_PDISP_SOR_PWR_SAFE_STATE __BIT(16) 192#define HDMI_NV_PDISP_SOR_PWR_SAFE_STATE __BIT(16)
169#define HDMI_NV_PDISP_SOR_PWR_NORMAL_START __BIT(1) 193#define HDMI_NV_PDISP_SOR_PWR_NORMAL_START __BIT(1)
170#define HDMI_NV_PDISP_SOR_PWR_NORMAL_STATE __BIT(0) 194#define HDMI_NV_PDISP_SOR_PWR_NORMAL_STATE __BIT(0)
171 195
172#define HDMI_NV_PDISP_SOR_TEST_REG 0x158 196#define HDMI_NV_PDISP_SOR_TEST_REG 0x158
173 197
174#define HDMI_NV_PDISP_SOR_PLL0_REG 0x15c 198#define HDMI_NV_PDISP_SOR_PLL0_REG 0x15c
175#define HDMI_NV_PDISP_SOR_PLL0_TX_REG_LOAD __BITS(29,28) 199#define HDMI_NV_PDISP_SOR_PLL0_TX_REG_LOAD __BITS(29,28)
176#define HDMI_NV_PDISP_SOR_PLL0_ICHPMP __BITS(27,24) 200#define HDMI_NV_PDISP_SOR_PLL0_ICHPMP __BITS(27,24)
177#define HDMI_NV_PDISP_SOR_PLL0_FILTER __BITS(19,16) 201#define HDMI_NV_PDISP_SOR_PLL0_FILTER __BITS(19,16)
178#define HDMI_NV_PDISP_SOR_PLL0_BG_V17_S __BITS(15,12) 202#define HDMI_NV_PDISP_SOR_PLL0_BG_V17_S __BITS(15,12)
179#define HDMI_NV_PDISP_SOR_PLL0_VCOCAP __BITS(11,8) 203#define HDMI_NV_PDISP_SOR_PLL0_VCOCAP __BITS(11,8)
180#define HDMI_NV_PDISP_SOR_PLL0_PULLDOWN __BIT(5) 204#define HDMI_NV_PDISP_SOR_PLL0_PULLDOWN __BIT(5)
181#define HDMI_NV_PDISP_SOR_PLL0_RESISTORSEL __BIT(4) 205#define HDMI_NV_PDISP_SOR_PLL0_RESISTORSEL __BIT(4)
182#define HDMI_NV_PDISP_SOR_PLL0_PDPORT __BIT(3) 206#define HDMI_NV_PDISP_SOR_PLL0_PDPORT __BIT(3)
183#define HDMI_NV_PDISP_SOR_PLL0_VCOPD __BIT(2) 207#define HDMI_NV_PDISP_SOR_PLL0_VCOPD __BIT(2)
184#define HDMI_NV_PDISP_SOR_PLL0_PDBG __BIT(1) 208#define HDMI_NV_PDISP_SOR_PLL0_PDBG __BIT(1)
185#define HDMI_NV_PDISP_SOR_PLL0_PWR __BIT(0) 209#define HDMI_NV_PDISP_SOR_PLL0_PWR __BIT(0)
186 210
187#define HDMI_NV_PDISP_SOR_PLL1_REG 0x160 211#define HDMI_NV_PDISP_SOR_PLL1_REG 0x160
188#define HDMI_NV_PDISP_SOR_PLL2_REG 0x164 212#define HDMI_NV_PDISP_SOR_PLL2_REG 0x164
189 213
190#define HDMI_NV_PDISP_SOR_CSTM_REG 0x168 214#define HDMI_NV_PDISP_SOR_CSTM_REG 0x168
191#define HDMI_NV_PDISP_SOR_CSTM_ROTDAT __BITS(30,28) 215#define HDMI_NV_PDISP_SOR_CSTM_ROTDAT __BITS(30,28)
192#define HDMI_NV_PDISP_SOR_CSTM_ROTCLK __BITS(27,24) 216#define HDMI_NV_PDISP_SOR_CSTM_ROTCLK __BITS(27,24)
193#define HDMI_NV_PDISP_SOR_CSTM_PLLDIV __BIT(21) 217#define HDMI_NV_PDISP_SOR_CSTM_PLLDIV __BIT(21)
194#define HDMI_NV_PDISP_SOR_CSTM_BALANCED __BIT(19) 218#define HDMI_NV_PDISP_SOR_CSTM_BALANCED __BIT(19)
195#define HDMI_NV_PDISP_SOR_CSTM_NEW_MODE __BIT(18) 219#define HDMI_NV_PDISP_SOR_CSTM_NEW_MODE __BIT(18)
196#define HDMI_NV_PDISP_SOR_CSTM_DUP_SYNC __BIT(17) 220#define HDMI_NV_PDISP_SOR_CSTM_DUP_SYNC __BIT(17)
197#define HDMI_NV_PDISP_SOR_CSTM_LVDS_EN __BIT(16) 221#define HDMI_NV_PDISP_SOR_CSTM_LVDS_EN __BIT(16)
198#define HDMI_NV_PDISP_SOR_CSTM_LINKACTB __BIT(15) 222#define HDMI_NV_PDISP_SOR_CSTM_LINKACTB __BIT(15)
199#define HDMI_NV_PDISP_SOR_CSTM_LINKACTA __BIT(14) 223#define HDMI_NV_PDISP_SOR_CSTM_LINKACTA __BIT(14)
200#define HDMI_NV_PDISP_SOR_CSTM_MODE __BITS(13,12) 224#define HDMI_NV_PDISP_SOR_CSTM_MODE __BITS(13,12)
201#define HDMI_NV_PDISP_SOR_CSTM_MODE_LVDS 0 225#define HDMI_NV_PDISP_SOR_CSTM_MODE_LVDS 0
202#define HDMI_NV_PDISP_SOR_CSTM_MODE_TMDS 1 226#define HDMI_NV_PDISP_SOR_CSTM_MODE_TMDS 1
203#define HDMI_NV_PDISP_SOR_CSTM_UPPER __BIT(11) 227#define HDMI_NV_PDISP_SOR_CSTM_UPPER __BIT(11)
204#define HDMI_NV_PDISP_SOR_CSTM_PD_TXCB __BIT(9) 228#define HDMI_NV_PDISP_SOR_CSTM_PD_TXCB __BIT(9)
205#define HDMI_NV_PDISP_SOR_CSTM_PD_TXCA __BIT(8) 229#define HDMI_NV_PDISP_SOR_CSTM_PD_TXCA __BIT(8)
206#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDB_3 __BIT(7) 230#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDB_3 __BIT(7)
207#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDB_2 __BIT(6) 231#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDB_2 __BIT(6)
208#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDB_1 __BIT(5) 232#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDB_1 __BIT(5)
209#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDB_0 __BIT(4) 233#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDB_0 __BIT(4)
210#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDA_3 __BIT(3) 234#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDA_3 __BIT(3)
211#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDA_2 __BIT(2) 235#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDA_2 __BIT(2)
212#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDA_1 __BIT(1) 236#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDA_1 __BIT(1)
213#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDA_0 __BIT(0) 237#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDA_0 __BIT(0)
214 238
215#define HDMI_NV_PDISP_SOR_LVDS_REG 0x16c 239#define HDMI_NV_PDISP_SOR_LVDS_REG 0x16c
216#define HDMI_NV_PDISP_SOR_CRCA_REG 0x170 240#define HDMI_NV_PDISP_SOR_CRCA_REG 0x170
217#define HDMI_NV_PDISP_SOR_CRCB_REG 0x174 241#define HDMI_NV_PDISP_SOR_CRCB_REG 0x174
218#define HDMI_NV_PDISP_SOR_BLANK_REG 0x178 242#define HDMI_NV_PDISP_SOR_BLANK_REG 0x178
219 243
220#define HDMI_NV_PDISP_SOR_SEQ_CTL_REG 0x17c 244#define HDMI_NV_PDISP_SOR_SEQ_CTL_REG 0x17c
221#define HDMI_NV_PDISP_SOR_SEQ_CTL_SWITCH __BIT(30) 245#define HDMI_NV_PDISP_SOR_SEQ_CTL_SWITCH __BIT(30)
222#define HDMI_NV_PDISP_SOR_SEQ_CTL_STATUS __BIT(28) 246#define HDMI_NV_PDISP_SOR_SEQ_CTL_STATUS __BIT(28)
223#define HDMI_NV_PDISP_SOR_SEQ_CTL_PC __BITS(19,16) 247#define HDMI_NV_PDISP_SOR_SEQ_CTL_PC __BITS(19,16)
224#define HDMI_NV_PDISP_SOR_SEQ_CTL_PD_PC_ALT __BITS(15,12) 248#define HDMI_NV_PDISP_SOR_SEQ_CTL_PD_PC_ALT __BITS(15,12)
225#define HDMI_NV_PDISP_SOR_SEQ_CTL_PD_PC __BITS(11,8) 249#define HDMI_NV_PDISP_SOR_SEQ_CTL_PD_PC __BITS(11,8)
226#define HDMI_NV_PDISP_SOR_SEQ_CTL_PU_PC_ALT __BITS(7,4) 250#define HDMI_NV_PDISP_SOR_SEQ_CTL_PU_PC_ALT __BITS(7,4)
227#define HDMI_NV_PDISP_SOR_SEQ_CTL_PU_PC __BITS(3,0) 251#define HDMI_NV_PDISP_SOR_SEQ_CTL_PU_PC __BITS(3,0)
228 252
229#define HDMI_NV_PDISP_SOR_SEQ_INST0_REG 0x180 253#define HDMI_NV_PDISP_SOR_SEQ_INST0_REG 0x180
230#define HDMI_NV_PDISP_SOR_SEQ_INST1_REG 0x184 254#define HDMI_NV_PDISP_SOR_SEQ_INST1_REG 0x184
231#define HDMI_NV_PDISP_SOR_SEQ_INST2_REG 0x188 255#define HDMI_NV_PDISP_SOR_SEQ_INST2_REG 0x188
232#define HDMI_NV_PDISP_SOR_SEQ_INST3_REG 0x18c 256#define HDMI_NV_PDISP_SOR_SEQ_INST3_REG 0x18c
233#define HDMI_NV_PDISP_SOR_SEQ_INST4_REG 0x190 257#define HDMI_NV_PDISP_SOR_SEQ_INST4_REG 0x190
234#define HDMI_NV_PDISP_SOR_SEQ_INST5_REG 0x194 258#define HDMI_NV_PDISP_SOR_SEQ_INST5_REG 0x194
235#define HDMI_NV_PDISP_SOR_SEQ_INST6_REG 0x198 259#define HDMI_NV_PDISP_SOR_SEQ_INST6_REG 0x198
236#define HDMI_NV_PDISP_SOR_SEQ_INST7_REG 0x19c 260#define HDMI_NV_PDISP_SOR_SEQ_INST7_REG 0x19c
237#define HDMI_NV_PDISP_SOR_SEQ_INST8_REG 0x1a0 261#define HDMI_NV_PDISP_SOR_SEQ_INST8_REG 0x1a0
238#define HDMI_NV_PDISP_SOR_SEQ_INST9_REG 0x1a4 262#define HDMI_NV_PDISP_SOR_SEQ_INST9_REG 0x1a4
239#define HDMI_NV_PDISP_SOR_SEQ_INSTA_REG 0x1a8 263#define HDMI_NV_PDISP_SOR_SEQ_INSTA_REG 0x1a8
240#define HDMI_NV_PDISP_SOR_SEQ_INSTB_REG 0x1ac 264#define HDMI_NV_PDISP_SOR_SEQ_INSTB_REG 0x1ac
241#define HDMI_NV_PDISP_SOR_SEQ_INSTC_REG 0x1b0 265#define HDMI_NV_PDISP_SOR_SEQ_INSTC_REG 0x1b0
242#define HDMI_NV_PDISP_SOR_SEQ_INSTD_REG 0x1b4 266#define HDMI_NV_PDISP_SOR_SEQ_INSTD_REG 0x1b4
243#define HDMI_NV_PDISP_SOR_SEQ_INSTE_REG 0x1b8 267#define HDMI_NV_PDISP_SOR_SEQ_INSTE_REG 0x1b8
244#define HDMI_NV_PDISP_SOR_SEQ_INSTF_REG 0x1bc 268#define HDMI_NV_PDISP_SOR_SEQ_INSTF_REG 0x1bc
245#define HDMI_NV_PDISP_SOR_SEQ_INST_PLL_PULLDOWN __BIT(31) 269#define HDMI_NV_PDISP_SOR_SEQ_INST_PLL_PULLDOWN __BIT(31)
246#define HDMI_NV_PDISP_SOR_SEQ_INST_POWERDOWN_MACRO __BIT(30) 270#define HDMI_NV_PDISP_SOR_SEQ_INST_POWERDOWN_MACRO __BIT(30)
247#define HDMI_NV_PDISP_SOR_SEQ_INST_ASSERT_PLL_RESETV __BIT(29) 271#define HDMI_NV_PDISP_SOR_SEQ_INST_ASSERT_PLL_RESETV __BIT(29)
248#define HDMI_NV_PDISP_SOR_SEQ_INST_BLANK_V __BIT(28) 272#define HDMI_NV_PDISP_SOR_SEQ_INST_BLANK_V __BIT(28)
249#define HDMI_NV_PDISP_SOR_SEQ_INST_BLANK_H __BIT(27) 273#define HDMI_NV_PDISP_SOR_SEQ_INST_BLANK_H __BIT(27)
250#define HDMI_NV_PDISP_SOR_SEQ_INST_BLANK_DE __BIT(26) 274#define HDMI_NV_PDISP_SOR_SEQ_INST_BLANK_DE __BIT(26)
251#define HDMI_NV_PDISP_SOR_SEQ_INST_BLACK_DATA __BIT(25) 275#define HDMI_NV_PDISP_SOR_SEQ_INST_BLACK_DATA __BIT(25)
252#define HDMI_NV_PDISP_SOR_SEQ_INST_TRISTATE_IOS __BIT(24) 276#define HDMI_NV_PDISP_SOR_SEQ_INST_TRISTATE_IOS __BIT(24)
253#define HDMI_NV_PDISP_SOR_SEQ_INST_DRIVE_PWM_OUT_LO __BIT(23) 277#define HDMI_NV_PDISP_SOR_SEQ_INST_DRIVE_PWM_OUT_LO __BIT(23)
254#define HDMI_NV_PDISP_SOR_SEQ_INST_PIN_B __BIT(22) 278#define HDMI_NV_PDISP_SOR_SEQ_INST_PIN_B __BIT(22)
255#define HDMI_NV_PDISP_SOR_SEQ_INST_PIN_A __BIT(21) 279#define HDMI_NV_PDISP_SOR_SEQ_INST_PIN_A __BIT(21)
256#define HDMI_NV_PDISP_SOR_SEQ_INST_HALT __BIT(15) 280#define HDMI_NV_PDISP_SOR_SEQ_INST_HALT __BIT(15)
257#define HDMI_NV_PDISP_SOR_SEQ_INST_WAIT_UNITS __BITS(13,12) 281#define HDMI_NV_PDISP_SOR_SEQ_INST_WAIT_UNITS __BITS(13,12)
258#define HDMI_NV_PDISP_SOR_SEQ_INST_WAIT_TIME __BITS(9,0) 282#define HDMI_NV_PDISP_SOR_SEQ_INST_WAIT_TIME __BITS(9,0)
259 283
260#define HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT_REG 0x1f8 284#define HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT_REG 0x1f8
261 285
262#define HDMI_NV_PDISP_SOR_REFCLK_REG 0x254 286#define HDMI_NV_PDISP_SOR_REFCLK_REG 0x254
263#define HDMI_NV_PDISP_SOR_REFCLK_DIV_INT __BITS(15,8) 287#define HDMI_NV_PDISP_SOR_REFCLK_DIV_INT __BITS(15,8)
264#define HDMI_NV_PDISP_SOR_REFCLK_DIV_FRAC __BITS(7,6) 288#define HDMI_NV_PDISP_SOR_REFCLK_DIV_FRAC __BITS(7,6)
265 289
266#define HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT_REG 0x344 290#define HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT_REG 0x344
267#define HDMI_NV_PDISP_SOR_PAD_CTLS0_REG 0x348 291#define HDMI_NV_PDISP_SOR_PAD_CTLS0_REG 0x348
268#define HDMI_NV_PDISP_SOR_PAD_CTLS1_REG 0x34c 292#define HDMI_NV_PDISP_SOR_PAD_CTLS1_REG 0x34c
269 293
270/* 294/*
271 * Audio Registers 295 * Audio Registers
272 */ 296 */
273#define HDMI_NV_PDISP_AUDIO_N_REG 0x230 297#define HDMI_NV_PDISP_AUDIO_N_REG 0x230
 298#define HDMI_NV_PDISP_AUDIO_N_LOOKUP __BIT(28)
 299#define HDMI_NV_PDISP_AUDIO_N_GENERATE __BIT(24)
 300#define HDMI_NV_PDISP_AUDIO_N_RESETF __BIT(20)
 301#define HDMI_NV_PDISP_AUDIO_N_VALUE __BITS(19,0)
 302
274#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_REG 0x2b0 303#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_REG 0x2b0
 304#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_INPUT_MODE __BIT(31)
 305#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_INJECT_NULLSMPL __BIT(29)
 306#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SOURCE_SELECT __BITS(21,20)
 307#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO 0
 308#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF 1
 309#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL 2
 310#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SAMPLING_FREQ __BITS(19,16)
 311#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SAMPLING_FREQ_32_0KHZ 3
 312#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SAMPLING_FREQ_44_1KHZ 0
 313#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SAMPLING_FREQ_88_2KHZ 8
 314#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SAMPLING_FREQ_176_4KHZ 12
 315#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SAMPLING_FREQ_48_0KHZ 2
 316#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SAMPLING_FREQ_96_0KHZ 10
 317#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SAMPLING_FREQ_192_0KHZ 14
 318#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SAMPLING_FREQ_UNKNOWN 1
 319#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_AFIFO_FLUSH __BIT(12)
 320#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_PORT_CONNECTIVITY __BIT(0)
 321
275#define HDMI_NV_PDISP_SOR_AUDIO_DEBUG_REG 0x2b4 322#define HDMI_NV_PDISP_SOR_AUDIO_DEBUG_REG 0x2b4
276#define HDMI_NV_PDISP_SOR_AUDIO_SPARE0_REG 0x2b8 323#define HDMI_NV_PDISP_SOR_AUDIO_SPARE0_REG 0x2b8
277#define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0320_REG 0x2bc 324#define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0320_REG 0x2bc
278#define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0441_REG 0x2c0 325#define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0441_REG 0x2c0
279#define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0882_REG 0x2c4 326#define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0882_REG 0x2c4
280#define HDMI_NV_PDISP_SOR_AUDIO_NVAL_1764_REG 0x2c8 327#define HDMI_NV_PDISP_SOR_AUDIO_NVAL_1764_REG 0x2c8
281#define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0480_REG 0x2cc 328#define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0480_REG 0x2cc
282#define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0960_REG 0x2d0 329#define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0960_REG 0x2d0
283#define HDMI_NV_PDISP_SOR_AUDIO_NVAL_1920_REG 0x2d4 330#define HDMI_NV_PDISP_SOR_AUDIO_NVAL_1920_REG 0x2d4
284#define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0_REG 0x2d8 331#define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0_REG 0x2d8
285#define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1_REG 0x2dc 332#define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1_REG 0x2dc
286#define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2_REG 0x2e0 333#define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2_REG 0x2e0
287#define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3_REG 0x2e4 334#define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3_REG 0x2e4
288#define HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0_REG 0x2e8 335#define HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0_REG 0x2e8
289#define HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1_REG 0x2ec 336#define HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1_REG 0x2ec
290#define HDMI_NV_PDISP_SOR_AUDIO_HDA_ELF_BUFWR_REG 0x2f0 337#define HDMI_NV_PDISP_SOR_AUDIO_HDA_ELF_BUFWR_REG 0x2f0
291#define HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_REG 0x2f4 338#define HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_REG 0x2f4
292#define HDMI_NV_PDISP_SOR_AUDIO_HDA_CP_REG 0x2f8 339#define HDMI_NV_PDISP_SOR_AUDIO_HDA_CP_REG 0x2f8
293#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320_REG 0x2fc 340#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320_REG 0x2fc
294#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441_REG 0x300 341#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441_REG 0x300
295#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882_REG 0x304 342#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882_REG 0x304
296#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764_REG 0x308 343#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764_REG 0x308
297#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480_REG 0x30c 344#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480_REG 0x30c
298#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960_REG 0x310 345#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960_REG 0x310
299#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920_REG 0x314 346#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920_REG 0x314
300#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT_REG 0x318 347#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT_REG 0x318
301#define HDMI_NV_PDISP_SOR_AUDIO_GEN_CTRL_REG 0x31c 348#define HDMI_NV_PDISP_SOR_AUDIO_GEN_CTRL_REG 0x31c
302#define HDMI_NV_HDACODEC_AUDIO_GEN_CTL_REG 0x354 349#define HDMI_NV_HDACODEC_AUDIO_GEN_CTL_REG 0x354
303 350
304#endif /* _ARM_TEGRA_HDMIREG_H */ 351#endif /* _ARM_TEGRA_HDMIREG_H */