 @@ -2629,1998 +2629,2000 @@ static void ilk_update_wm(struct drm_crt
 	    config.num_pipes_active == 1 && config.sprites_enabled) {
 		ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
 		ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
 		best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
 	} else {
 		best_lp_wm = &lp_wm_1_2;
+	}
 	partitioning = (best_lp_wm == &lp_wm_1_2) ?
 		       INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
 	ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
 	ilk_write_wm_values(dev_priv, &results);
+}
 static void ilk_update_sprite_wm(struct drm_plane *plane,
 				     struct drm_crtc *crtc,
 				     uint32_t sprite_width, int pixel_size,
 				     bool enabled, bool scaled)
+{
 	struct drm_device *dev = plane->dev;
 	struct intel_plane *intel_plane = to_intel_plane(plane);
 	intel_plane->wm.enabled = enabled;
 	intel_plane->wm.scaled = scaled;
 	intel_plane->wm.horiz_pixels = sprite_width;
 	intel_plane->wm.bytes_per_pixel = pixel_size;
 	/*
 	 * IVB workaround: must disable low power watermarks for at least
 	 * one frame before enabling scaling.  LP watermarks can be re-enabled
 	 * when scaling is disabled.
+	 *
 	 * WaCxSRDisabledForSpriteScaling:ivb
 	 */
 	if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
 		intel_wait_for_vblank(dev, intel_plane->pipe);
 	ilk_update_wm(crtc);
+}
 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
+{
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct ilk_wm_values *hw = &dev_priv->wm.hw;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_pipe_wm *active = &intel_crtc->wm.active;
 	enum i915_pipe pipe = intel_crtc->pipe;
 	static const unsigned int wm0_pipe_reg[] = {
 		[PIPE_A] = WM0_PIPEA_ILK,
 		[PIPE_B] = WM0_PIPEB_ILK,
 		[PIPE_C] = WM0_PIPEC_IVB,
 	};
 	hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
 	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
 	if (intel_crtc_active(crtc)) {
 		u32 tmp = hw->wm_pipe[pipe];
 		/*
 		 * For active pipes LP0 watermark is marked as
 		 * enabled, and LP1+ watermaks as disabled since
 		 * we can't really reverse compute them in case
 		 * multiple pipes are active.
 		 */
 		active->wm[0].enable = true;
 		active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
 		active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
 		active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
 		active->linetime = hw->wm_linetime[pipe];
 	} else {
 		int level, max_level = ilk_wm_max_level(dev);
 		/*
 		 * For inactive pipes, all watermark levels
 		 * should be marked as enabled but zeroed,
 		 * which is what we'd compute them to.
 		 */
 		for (level = 0; level <= max_level; level++)
 			active->wm[level].enable = true;
+	}
+}
 void ilk_wm_get_hw_state(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct ilk_wm_values *hw = &dev_priv->wm.hw;
 	struct drm_crtc *crtc;
 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 		ilk_pipe_wm_get_hw_state(crtc);
 	hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
 	hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
 	hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
 	hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
 	hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
 	hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
 	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
 			INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
 	else if (IS_IVYBRIDGE(dev))
 		hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
 			INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
 	hw->enable_fbc_wm =
 		!(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
+}
 /**
  * intel_update_watermarks - update FIFO watermark values based on current modes
+ *
  * Calculate watermark values for the various WM regs based on current mode
  * and plane configuration.
+ *
  * There are several cases to deal with here:
  *   - normal (i.e. non-self-refresh)
  *   - self-refresh (SR) mode
  *   - lines are large relative to FIFO size (buffer can hold up to 2)
  *   - lines are small relative to FIFO size (buffer can hold more than 2
  *     lines), so need to account for TLB latency
+ *
  *   The normal calculation is:
  *     watermark = dotclock * bytes per pixel * latency
  *   where latency is platform & configuration dependent (we assume pessimal
  *   values here).
+ *
  *   The SR calculation is:
  *     watermark = (trunc(latency/line time)+1) * surface width *
  *       bytes per pixel
  *   where
  *     line time = htotal / dotclock
  *     surface width = hdisplay for normal plane and 64 for cursor
  *   and latency is assumed to be high, as above.
+ *
  * The final value programmed to the register should always be rounded up,
  * and include an extra 2 entries to account for clock crossings.
+ *
  * We don't use the sprite, so we can ignore that.  And on Crestline we have
  * to set the non-SR watermarks to 8.
  */
 void intel_update_watermarks(struct drm_crtc *crtc)
+{
 	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 	if (dev_priv->display.update_wm)
 		dev_priv->display.update_wm(crtc);
+}
 void intel_update_sprite_watermarks(struct drm_plane *plane,
 				    struct drm_crtc *crtc,
 				    uint32_t sprite_width, int pixel_size,
 				    bool enabled, bool scaled)
+{
 	struct drm_i915_private *dev_priv = plane->dev->dev_private;
 	if (dev_priv->display.update_sprite_wm)
 		dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
 						   pixel_size, enabled, scaled);
+}
 static struct drm_i915_gem_object *
 intel_alloc_context_page(struct drm_device *dev)
+{
 	struct drm_i915_gem_object *ctx;
 	int ret;
 	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
 	ctx = i915_gem_alloc_object(dev, 4096);
 	if (!ctx) {
 		DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
 		return NULL;
+	}
 	ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
 	if (ret) {
 		DRM_ERROR("failed to pin power context: %d\n", ret);
 		goto err_unref;
+	}
 	ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
 	if (ret) {
 		DRM_ERROR("failed to set-domain on power context: %d\n", ret);
 		goto err_unpin;
+	}
 	return ctx;
 err_unpin:
 	i915_gem_object_ggtt_unpin(ctx);
 err_unref:
 	drm_gem_object_unreference(&ctx->base);
 	return NULL;
+}
 /**
  * Lock protecting IPS related data structures
  */
 #ifdef __NetBSD__
 spinlock_t mchdev_lock;
 #else
 DEFINE_SPINLOCK(mchdev_lock);
 #endif
 /* Global for IPS driver to get at the current i915 device. Protected by
  * mchdev_lock. */
 static struct drm_i915_private *i915_mch_dev;
 bool ironlake_set_drps(struct drm_device *dev, u8 val)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u16 rgvswctl;
 	assert_spin_locked(&mchdev_lock);
 	rgvswctl = I915_READ16(MEMSWCTL);
 	if (rgvswctl & MEMCTL_CMD_STS) {
 		DRM_DEBUG("gpu busy, RCS change rejected\n");
 		return false; /* still busy with another command */
+	}
 	rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
 		(val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
 	I915_WRITE16(MEMSWCTL, rgvswctl);
 	POSTING_READ16(MEMSWCTL);
 	rgvswctl |= MEMCTL_CMD_STS;
 	I915_WRITE16(MEMSWCTL, rgvswctl);
 	return true;
+}
 static void ironlake_enable_drps(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 rgvmodectl = I915_READ(MEMMODECTL);
 	u8 fmax, fmin, fstart, vstart;
 	spin_lock_irq(&mchdev_lock);
 	/* Enable temp reporting */
 	I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
 	I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
 	/* 100ms RC evaluation intervals */
 	I915_WRITE(RCUPEI, 100000);
 	I915_WRITE(RCDNEI, 100000);
 	/* Set max/min thresholds to 90ms and 80ms respectively */
 	I915_WRITE(RCBMAXAVG, 90000);
 	I915_WRITE(RCBMINAVG, 80000);
 	I915_WRITE(MEMIHYST, 1);
 	/* Set up min, max, and cur for interrupt handling */
 	fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
 	fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
 	fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
 		MEMMODE_FSTART_SHIFT;
 	vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
 		PXVFREQ_PX_SHIFT;
 	dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
 	dev_priv->ips.fstart = fstart;
 	dev_priv->ips.max_delay = fstart;
 	dev_priv->ips.min_delay = fmin;
 	dev_priv->ips.cur_delay = fstart;
 	DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
 			 fmax, fmin, fstart);
 	I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
 	/*
 	 * Interrupts will be enabled in ironlake_irq_postinstall
 	 */
 	I915_WRITE(VIDSTART, vstart);
 	POSTING_READ(VIDSTART);
 	rgvmodectl |= MEMMODE_SWMODE_EN;
 	I915_WRITE(MEMMODECTL, rgvmodectl);
 	if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
 		DRM_ERROR("stuck trying to change perf mode\n");
 	mdelay(1);
 	ironlake_set_drps(dev, fstart);
 	dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
 		I915_READ(0x112e0);
 	dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
 	dev_priv->ips.last_count2 = I915_READ(0x112f4);
 	getrawmonotonic(&dev_priv->ips.last_time2);
 	spin_unlock_irq(&mchdev_lock);
+}
 static void ironlake_disable_drps(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u16 rgvswctl;
 	spin_lock_irq(&mchdev_lock);
 	rgvswctl = I915_READ16(MEMSWCTL);
 	/* Ack interrupts, disable EFC interrupt */
 	I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
 	I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
 	I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
 	I915_WRITE(DEIIR, DE_PCU_EVENT);
 	I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
 	/* Go back to the starting frequency */
 	ironlake_set_drps(dev, dev_priv->ips.fstart);
 	mdelay(1);
 	rgvswctl |= MEMCTL_CMD_STS;
 	I915_WRITE(MEMSWCTL, rgvswctl);
 	mdelay(1);
 	spin_unlock_irq(&mchdev_lock);
+}
 /* There's a funny hw issue where the hw returns all 0 when reading from
  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
  * ourselves, instead of doing a rmw cycle (which might result in us clearing
  * all limits and the gpu stuck at whatever frequency it is at atm).
  */
 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
+{
 	u32 limits;
 	/* Only set the down limit when we've reached the lowest level to avoid
 	 * getting more interrupts, otherwise leave this clear. This prevents a
 	 * race in the hw when coming out of rc6: There's a tiny window where
 	 * the hw runs at the minimal clock before selecting the desired
 	 * frequency, if the down threshold expires in that window we will not
 	 * receive a down interrupt. */
 	limits = dev_priv->rps.max_freq_softlimit << 24;
 	if (val <= dev_priv->rps.min_freq_softlimit)
 		limits |= dev_priv->rps.min_freq_softlimit << 16;
 	return limits;
+}
 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
+{
 	int new_power;
 	new_power = dev_priv->rps.power;
 	switch (dev_priv->rps.power) {
 	case LOW_POWER:
 		if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
 			new_power = BETWEEN;
 		break;
 	case BETWEEN:
 		if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
 			new_power = LOW_POWER;
 		else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
 			new_power = HIGH_POWER;
 		break;
 	case HIGH_POWER:
 		if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
 			new_power = BETWEEN;
 		break;
+	}
 	/* Max/min bins are special */
 	if (val == dev_priv->rps.min_freq_softlimit)
 		new_power = LOW_POWER;
 	if (val == dev_priv->rps.max_freq_softlimit)
 		new_power = HIGH_POWER;
 	if (new_power == dev_priv->rps.power)
 		return;
 	/* Note the units here are not exactly 1us, but 1280ns. */
 	switch (new_power) {
 	case LOW_POWER:
 		/* Upclock if more than 95% busy over 16ms */
 		I915_WRITE(GEN6_RP_UP_EI, 12500);
 		I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
 		/* Downclock if less than 85% busy over 32ms */
 		I915_WRITE(GEN6_RP_DOWN_EI, 25000);
 		I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
 		I915_WRITE(GEN6_RP_CONTROL,
 			   GEN6_RP_MEDIA_TURBO |
 			   GEN6_RP_MEDIA_HW_NORMAL_MODE |
 			   GEN6_RP_MEDIA_IS_GFX |
 			   GEN6_RP_ENABLE |
 			   GEN6_RP_UP_BUSY_AVG |
 			   GEN6_RP_DOWN_IDLE_AVG);
 		break;
 	case BETWEEN:
 		/* Upclock if more than 90% busy over 13ms */
 		I915_WRITE(GEN6_RP_UP_EI, 10250);
 		I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
 		/* Downclock if less than 75% busy over 32ms */
 		I915_WRITE(GEN6_RP_DOWN_EI, 25000);
 		I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
 		I915_WRITE(GEN6_RP_CONTROL,
 			   GEN6_RP_MEDIA_TURBO |
 			   GEN6_RP_MEDIA_HW_NORMAL_MODE |
 			   GEN6_RP_MEDIA_IS_GFX |
 			   GEN6_RP_ENABLE |
 			   GEN6_RP_UP_BUSY_AVG |
 			   GEN6_RP_DOWN_IDLE_AVG);
 		break;
 	case HIGH_POWER:
 		/* Upclock if more than 85% busy over 10ms */
 		I915_WRITE(GEN6_RP_UP_EI, 8000);
 		I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
 		/* Downclock if less than 60% busy over 32ms */
 		I915_WRITE(GEN6_RP_DOWN_EI, 25000);
 		I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
 		I915_WRITE(GEN6_RP_CONTROL,
 			   GEN6_RP_MEDIA_TURBO |
 			   GEN6_RP_MEDIA_HW_NORMAL_MODE |
 			   GEN6_RP_MEDIA_IS_GFX |
 			   GEN6_RP_ENABLE |
 			   GEN6_RP_UP_BUSY_AVG |
 			   GEN6_RP_DOWN_IDLE_AVG);
 		break;
+	}
 	dev_priv->rps.power = new_power;
 	dev_priv->rps.last_adj = 0;
+}
 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
+{
 	u32 mask = 0;
 	if (val > dev_priv->rps.min_freq_softlimit)
 		mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
 	if (val < dev_priv->rps.max_freq_softlimit)
 		mask |= GEN6_PM_RP_UP_THRESHOLD;
 	/* IVB and SNB hard hangs on looping batchbuffer
 	 * if GEN6_PM_UP_EI_EXPIRED is masked.
 	 */
 	if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
 		mask |= GEN6_PM_RP_UP_EI_EXPIRED;
 	return ~mask;
+}
 /* gen6_set_rps is called to update the frequency request, but should also be
  * called when the range (min_delay and max_delay) is modified so that we can
  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
 void gen6_set_rps(struct drm_device *dev, u8 val)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
 	WARN_ON(val > dev_priv->rps.max_freq_softlimit);
 	WARN_ON(val < dev_priv->rps.min_freq_softlimit);
 	/* min/max delay may still have been modified so be sure to
 	 * write the limits value.
 	 */
 	if (val != dev_priv->rps.cur_freq) {
 		gen6_set_rps_thresholds(dev_priv, val);
 		if (IS_HASWELL(dev))
 			I915_WRITE(GEN6_RPNSWREQ,
 				   HSW_FREQUENCY(val));
 		else
 			I915_WRITE(GEN6_RPNSWREQ,
 				   GEN6_FREQUENCY(val) |
 				   GEN6_OFFSET(0) |
 				   GEN6_AGGRESSIVE_TURBO);
+	}
 	/* Make sure we continue to get interrupts
 	 * until we hit the minimum or maximum frequencies.
 	 */
 	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
 	I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
 	POSTING_READ(GEN6_RPNSWREQ);
 	dev_priv->rps.cur_freq = val;
 	trace_intel_gpu_freq_change(val * 50);
+}
 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
+ *
  * * If Gfx is Idle, then
  * 1. Mask Turbo interrupts
  * 2. Bring up Gfx clock
  * 3. Change the freq to Rpn and wait till P-Unit updates freq
  * 4. Clear the Force GFX CLK ON bit so that Gfx can down
  * 5. Unmask Turbo interrupts
 */
 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
+{
 	/*
 	 * When we are idle.  Drop to min voltage state.
 	 */
 	if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
 		return;
 	/* Mask turbo interrupt so that they will not come in between */
 	I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
 	/* Bring up the Gfx clock */
 	I915_WRITE(VLV_GTLC_SURVIVABILITY_REG,
 		I915_READ(VLV_GTLC_SURVIVABILITY_REG) |
 				VLV_GFX_CLK_FORCE_ON_BIT);
 	if (wait_for(((VLV_GFX_CLK_STATUS_BIT &
 		I915_READ(VLV_GTLC_SURVIVABILITY_REG)) != 0), 5)) {
 			DRM_ERROR("GFX_CLK_ON request timed out\n");
 		return;
+	}
 	dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
 	vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
 					dev_priv->rps.min_freq_softlimit);
 	if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
 				& GENFREQSTATUS) == 0, 5))
 		DRM_ERROR("timed out waiting for Punit\n");
 	/* Release the Gfx clock */
 	I915_WRITE(VLV_GTLC_SURVIVABILITY_REG,
 		I915_READ(VLV_GTLC_SURVIVABILITY_REG) &
 				~VLV_GFX_CLK_FORCE_ON_BIT);
 	I915_WRITE(GEN6_PMINTRMSK,
 		   gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
+}
 void gen6_rps_idle(struct drm_i915_private *dev_priv)
+{
 	struct drm_device *dev = dev_priv->dev;
 	mutex_lock(&dev_priv->rps.hw_lock);
 	if (dev_priv->rps.enabled) {
 		if (IS_VALLEYVIEW(dev))
 			vlv_set_rps_idle(dev_priv);
 		else
 			gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
 		dev_priv->rps.last_adj = 0;
+	}
 	mutex_unlock(&dev_priv->rps.hw_lock);
+}
 void gen6_rps_boost(struct drm_i915_private *dev_priv)
+{
 	struct drm_device *dev = dev_priv->dev;
 	mutex_lock(&dev_priv->rps.hw_lock);
 	if (dev_priv->rps.enabled) {
 		if (IS_VALLEYVIEW(dev))
 			valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
 		else
 			gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
 		dev_priv->rps.last_adj = 0;
+	}
 	mutex_unlock(&dev_priv->rps.hw_lock);
+}
 void valleyview_set_rps(struct drm_device *dev, u8 val)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
 	WARN_ON(val > dev_priv->rps.max_freq_softlimit);
 	WARN_ON(val < dev_priv->rps.min_freq_softlimit);
 	DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
 			 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
 			 dev_priv->rps.cur_freq,
 			 vlv_gpu_freq(dev_priv, val), val);
 	if (val != dev_priv->rps.cur_freq)
 		vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
 	I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
 	dev_priv->rps.cur_freq = val;
 	trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
+}
 static void gen6_disable_rps_interrupts(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
 	I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
 				~dev_priv->pm_rps_events);
 	/* Complete PM interrupt masking here doesn't race with the rps work
 	 * item again unmasking PM interrupts because that is using a different
 	 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
 	 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
 	spin_lock_irq(&dev_priv->irq_lock);
 	dev_priv->rps.pm_iir = 0;
 	spin_unlock_irq(&dev_priv->irq_lock);
 	I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
+}
 static void gen6_disable_rps(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 	I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
 	gen6_disable_rps_interrupts(dev);
+}
 static void valleyview_disable_rps(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 	gen6_disable_rps_interrupts(dev);
+}
 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
+{
 	DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
 		 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
 		 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
 		 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
+}
 int intel_enable_rc6(const struct drm_device *dev)
+{
 	/* No RC6 before Ironlake */
 	if (INTEL_INFO(dev)->gen < 5)
 		return 0;
 	/* Respect the kernel parameter if it is set */
 	if (i915.enable_rc6 >= 0)
 		return i915.enable_rc6;
 	/* Disable RC6 on Ironlake */
 	if (INTEL_INFO(dev)->gen == 5)
 		return 0;
 	if (IS_IVYBRIDGE(dev))
 		return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
 	return INTEL_RC6_ENABLE;
+}
 static void gen6_enable_rps_interrupts(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	spin_lock_irq(&dev_priv->irq_lock);
 	WARN_ON(dev_priv->rps.pm_iir);
 	snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 	I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
 	spin_unlock_irq(&dev_priv->irq_lock);
+}
 static void gen8_enable_rps(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_ring_buffer *ring;
 	uint32_t rc6_mask = 0;
 	int unused;
 	/* 1a: Software RC state - RC0 */
 	I915_WRITE(GEN6_RC_STATE, 0);
 	/* 1c & 1d: Get forcewake during program sequence. Although the driver
 	 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
 	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
 	/* 2a: Disable RC states. */
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 	(void)I915_READ(GEN6_RP_STATE_CAP);
 	/* 2b: Program RC6 thresholds.*/
 	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
 	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
 	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
 	for_each_ring(ring, dev_priv, unused)
 		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
 	I915_WRITE(GEN6_RC_SLEEP, 0);
 	I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
 	/* 3: Enable RC6 */
 	if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
 		rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
 	intel_print_rc6_info(dev, rc6_mask);
 	I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
 				    GEN6_RC_CTL_EI_MODE(1) |
 				    rc6_mask);
 	/* 4 Program defaults and thresholds for RPS*/
 	I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */
 	I915_WRITE(GEN6_RC_VIDEO_FREQ, HSW_FREQUENCY(12)); /* Request 600 MHz */
 	/* NB: Docs say 1s, and 1000000 - which aren't equivalent */
 	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
 	/* Docs recommend 900MHz, and 300 MHz respectively */
 	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
 		   dev_priv->rps.max_freq_softlimit << 24 |
 		   dev_priv->rps.min_freq_softlimit << 16);
 	I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
 	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
 	I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
 	I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
 	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
 	/* 5: Enable RPS */
 	I915_WRITE(GEN6_RP_CONTROL,
 		   GEN6_RP_MEDIA_TURBO |
 		   GEN6_RP_MEDIA_HW_NORMAL_MODE |
 		   GEN6_RP_MEDIA_IS_GFX |
 		   GEN6_RP_ENABLE |
 		   GEN6_RP_UP_BUSY_AVG |
 		   GEN6_RP_DOWN_IDLE_AVG);
 	/* 6: Ring frequency + overclocking (our driver does this later */
 	gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
 	gen6_enable_rps_interrupts(dev);
 	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
+}
 static void gen6_enable_rps(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_ring_buffer *ring;
 	u32 rp_state_cap;
 	u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
 	u32 gtfifodbg;
 	int rc6_mode;
 	int i, ret;
 	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
 	/* Here begins a magic sequence of register writes to enable
 	 * auto-downclocking.
+	 *
 	 * Perhaps there might be some value in exposing these to
 	 * userspace...
 	 */
 	I915_WRITE(GEN6_RC_STATE, 0);
 	/* Clear the DBG now so we don't confuse earlier errors */
 	if ((gtfifodbg = I915_READ(GTFIFODBG))) {
 		DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
 		I915_WRITE(GTFIFODBG, gtfifodbg);
+	}
 	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
 	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
 	(void)I915_READ(GEN6_GT_PERF_STATUS);
 	/* All of these values are in units of 50MHz */
 	dev_priv->rps.cur_freq		= 0;
 	/* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
 	dev_priv->rps.rp1_freq		= (rp_state_cap >>  8) & 0xff;
 	dev_priv->rps.rp0_freq		= (rp_state_cap >>  0) & 0xff;
 	dev_priv->rps.min_freq		= (rp_state_cap >> 16) & 0xff;
 	/* XXX: only BYT has a special efficient freq */
 	dev_priv->rps.efficient_freq	= dev_priv->rps.rp1_freq;
 	/* hw_max = RP0 until we check for overclocking */
 	dev_priv->rps.max_freq		= dev_priv->rps.rp0_freq;
 	/* Preserve min/max settings in case of re-init */
 	if (dev_priv->rps.max_freq_softlimit == 0)
 		dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
 	if (dev_priv->rps.min_freq_softlimit == 0)
 		dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
 	/* disable the counters and set deterministic thresholds */
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 	I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
 	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
 	I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
 	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
 	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
 	for_each_ring(ring, dev_priv, i)
 		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
 	I915_WRITE(GEN6_RC_SLEEP, 0);
 	I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
 	if (IS_IVYBRIDGE(dev))
 		I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
 	else
 		I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
 	I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
 	I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
 	/* Check if we are enabling RC6 */
 	rc6_mode = intel_enable_rc6(dev_priv->dev);
 	if (rc6_mode & INTEL_RC6_ENABLE)
 		rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
 	/* We don't use those on Haswell */
 	if (!IS_HASWELL(dev)) {
 		if (rc6_mode & INTEL_RC6p_ENABLE)
 			rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
 		if (rc6_mode & INTEL_RC6pp_ENABLE)
 			rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
+	}
 	intel_print_rc6_info(dev, rc6_mask);
 	I915_WRITE(GEN6_RC_CONTROL,
 		   rc6_mask |
 		   GEN6_RC_CTL_EI_MODE(1) |
 		   GEN6_RC_CTL_HW_ENABLE);
 	/* Power down if completely idle for over 50ms */
 	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
 	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
 	ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
 	if (ret)
 		DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
 	ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
 	if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
 		DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
 				 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
 				 (pcu_mbox & 0xff) * 50);
 		dev_priv->rps.max_freq = pcu_mbox & 0xff;
+	}
 	dev_priv->rps.power = HIGH_POWER; /* force a reset */
 	gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
 	gen6_enable_rps_interrupts(dev);
 	rc6vids = 0;
 	ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
 	if (IS_GEN6(dev) && ret) {
 		DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
 	} else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
 		DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
 			  GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
 		rc6vids &= 0xffff00;
 		rc6vids |= GEN6_ENCODE_RC6_VID(450);
 		ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
 		if (ret)
 			DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
+	}
 	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
+}
 void gen6_update_ring_freq(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int min_freq = 15;
 	unsigned int gpu_freq;
 	unsigned int max_ia_freq, min_ring_freq;
 	int scaling_factor = 180;
 #ifndef __NetBSD__
 	struct cpufreq_policy *policy;
 #endif
 	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
 #ifdef __NetBSD__
+	{
 		extern uint64_t tsc_freq; /* x86 TSC frequency in Hz */
 		max_ia_freq = (tsc_freq / 1000);
+	}
 #else
 	policy = cpufreq_cpu_get(0);
 	if (policy) {
 		max_ia_freq = policy->cpuinfo.max_freq;
 		cpufreq_cpu_put(policy);
 	} else {
 		/*
 		 * Default to measured freq if none found, PCU will ensure we
 		 * don't go over
 		 */
 		max_ia_freq = tsc_khz;
+	}
 #endif
 	/* Convert from kHz to MHz */
 	max_ia_freq /= 1000;
 	min_ring_freq = I915_READ(DCLK) & 0xf;
 	/* convert DDR frequency from units of 266.6MHz to bandwidth */
 	min_ring_freq = mult_frac(min_ring_freq, 8, 3);
 	/*
 	 * For each potential GPU frequency, load a ring frequency we'd like
 	 * to use for memory access.  We do this by specifying the IA frequency
 	 * the PCU should use as a reference to determine the ring frequency.
 	 */
 	for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
 	     gpu_freq--) {
 		int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
 		unsigned int ia_freq = 0, ring_freq = 0;
 		if (INTEL_INFO(dev)->gen >= 8) {
 			/* max(2 * GT, DDR). NB: GT is 50MHz units */
 			ring_freq = max(min_ring_freq, gpu_freq);
 		} else if (IS_HASWELL(dev)) {
 			ring_freq = mult_frac(gpu_freq, 5, 4);
 			ring_freq = max(min_ring_freq, ring_freq);
 			/* leave ia_freq as the default, chosen by cpufreq */
 		} else {
 			/* On older processors, there is no separate ring
 			 * clock domain, so in order to boost the bandwidth
 			 * of the ring, we need to upclock the CPU (ia_freq).
+			 *
 			 * For GPU frequencies less than 750MHz,
 			 * just use the lowest ring freq.
 			 */
 			if (gpu_freq < min_freq)
 				ia_freq = 800;
 			else
 				ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
 			ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
+		}
 		sandybridge_pcode_write(dev_priv,
 					GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
 					ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
 					ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
 					gpu_freq);
+	}
+}
 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
+{
 	u32 val, rp0;
 	val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
 	rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
 	/* Clamp to max */
 	rp0 = min_t(u32, rp0, 0xea);
 	return rp0;
+}
 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
+{
 	u32 val, rpe;
 	val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
 	rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
 	val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
 	rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
 	return rpe;
+}
 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
+{
 	return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
+}
 /* Check that the pctx buffer wasn't move under us. */
 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
+{
 	unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
 	if (WARN_ON(!dev_priv->vlv_pctx))
 		return;
 	WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
 			     dev_priv->vlv_pctx->stolen->start);
+}
 static void valleyview_setup_pctx(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_i915_gem_object *pctx;
 	unsigned long pctx_paddr;
 	u32 pcbr;
 	int pctx_size = 24*1024;
 	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
 	pcbr = I915_READ(VLV_PCBR);
 	if (pcbr) {
 		/* BIOS set it up already, grab the pre-alloc'd space */
 		int pcbr_offset;
 		pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
 		pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
 								      pcbr_offset,
 								      I915_GTT_OFFSET_NONE,
 								      pctx_size);
 		goto out;
+	}
 	/*
 	 * From the Gunit register HAS:
 	 * The Gfx driver is expected to program this register and ensure
 	 * proper allocation within Gfx stolen memory.  For example, this
 	 * register should be programmed such than the PCBR range does not
 	 * overlap with other ranges, such as the frame buffer, protected
 	 * memory, or any other relevant ranges.
 	 */
 	pctx = i915_gem_object_create_stolen(dev, pctx_size);
 	if (!pctx) {
 		DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
 		return;
+	}
 	pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
 	I915_WRITE(VLV_PCBR, pctx_paddr);
 out:
 	dev_priv->vlv_pctx = pctx;
+}
 static void valleyview_cleanup_pctx(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	if (WARN_ON(!dev_priv->vlv_pctx))
 		return;
 	drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
 	dev_priv->vlv_pctx = NULL;
+}
 static void valleyview_enable_rps(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_ring_buffer *ring;
 	u32 gtfifodbg, val, rc6_mode = 0;
 	int i;
 	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
 	valleyview_check_pctx(dev_priv);
 	if ((gtfifodbg = I915_READ(GTFIFODBG))) {
 		DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
 				 gtfifodbg);
 		I915_WRITE(GTFIFODBG, gtfifodbg);
+	}
 	/* If VLV, Forcewake all wells, else re-direct to regular path */
 	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
 	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
 	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
 	I915_WRITE(GEN6_RP_UP_EI, 66000);
 	I915_WRITE(GEN6_RP_DOWN_EI, 350000);
 	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
 	I915_WRITE(GEN6_RP_CONTROL,
 		   GEN6_RP_MEDIA_TURBO |
 		   GEN6_RP_MEDIA_HW_NORMAL_MODE |
 		   GEN6_RP_MEDIA_IS_GFX |
 		   GEN6_RP_ENABLE |
 		   GEN6_RP_UP_BUSY_AVG |
 		   GEN6_RP_DOWN_IDLE_CONT);
 	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
 	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
 	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
 	for_each_ring(ring, dev_priv, i)
 		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
 	I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
 	/* allows RC6 residency counter to work */
 	I915_WRITE(VLV_COUNTER_CONTROL,
 		   _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
 				      VLV_MEDIA_RC6_COUNT_EN |
 				      VLV_RENDER_RC6_COUNT_EN));
 	if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
 		rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
 	intel_print_rc6_info(dev, rc6_mode);
 	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
 	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
 	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
 	DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
 	dev_priv->rps.cur_freq = (val >> 8) & 0xff;
 	DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
 			 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
 			 dev_priv->rps.cur_freq);
 	dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
 	dev_priv->rps.rp0_freq  = dev_priv->rps.max_freq;
 	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
 			 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
 			 dev_priv->rps.max_freq);
 	dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
 	DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
 			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
 			 dev_priv->rps.efficient_freq);
 	dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
 	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
 			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
 			 dev_priv->rps.min_freq);
 	/* Preserve min/max settings in case of re-init */
 	if (dev_priv->rps.max_freq_softlimit == 0)
 		dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
 	if (dev_priv->rps.min_freq_softlimit == 0)
 		dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
 	DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
 			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
 			 dev_priv->rps.efficient_freq);
 	valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
 	gen6_enable_rps_interrupts(dev);
 	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
+}
 void ironlake_teardown_rc6(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	if (dev_priv->ips.renderctx) {
 		i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
 		drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
 		dev_priv->ips.renderctx = NULL;
+	}
 	if (dev_priv->ips.pwrctx) {
 		i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
 		drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
 		dev_priv->ips.pwrctx = NULL;
+	}
+}
 static void ironlake_disable_rc6(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	if (I915_READ(PWRCTXA)) {
 		/* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
 		I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
 		wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
 );
 		I915_WRITE(PWRCTXA, 0);
 		POSTING_READ(PWRCTXA);
 		I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
 		POSTING_READ(RSTDBYCTL);
+	}
+}
 static int ironlake_setup_rc6(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	if (dev_priv->ips.renderctx == NULL)
 		dev_priv->ips.renderctx = intel_alloc_context_page(dev);
 	if (!dev_priv->ips.renderctx)
 		return -ENOMEM;
 	if (dev_priv->ips.pwrctx == NULL)
 		dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
 	if (!dev_priv->ips.pwrctx) {
 		ironlake_teardown_rc6(dev);
 		return -ENOMEM;
+	}
 	return 0;
+}
 static void ironlake_enable_rc6(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
 	bool was_interruptible;
 	int ret;
 	/* rc6 disabled by default due to repeated reports of hanging during
 	 * boot and resume.
 	 */
 	if (!intel_enable_rc6(dev))
 		return;
 	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
 	ret = ironlake_setup_rc6(dev);
 	if (ret)
 		return;
 	was_interruptible = dev_priv->mm.interruptible;
 	dev_priv->mm.interruptible = false;
 	/*
 	 * GPU can automatically power down the render unit if given a page
 	 * to save state.
 	 */
 	ret = intel_ring_begin(ring, 6);
 	if (ret) {
 		ironlake_teardown_rc6(dev);
 		dev_priv->mm.interruptible = was_interruptible;
 		return;
+	}
 	intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
 	intel_ring_emit(ring, MI_SET_CONTEXT);
 	intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
 			MI_MM_SPACE_GTT |
 			MI_SAVE_EXT_STATE_EN |
 			MI_RESTORE_EXT_STATE_EN |
 			MI_RESTORE_INHIBIT);
 	intel_ring_emit(ring, MI_SUSPEND_FLUSH);
 	intel_ring_emit(ring, MI_NOOP);
 	intel_ring_emit(ring, MI_FLUSH);
 	intel_ring_advance(ring);
 	/*
 	 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
 	 * does an implicit flush, combined with MI_FLUSH above, it should be
 	 * safe to assume that renderctx is valid
 	 */
 	ret = intel_ring_idle(ring);
 	dev_priv->mm.interruptible = was_interruptible;
 	if (ret) {
 		DRM_ERROR("failed to enable ironlake power savings\n");
 		ironlake_teardown_rc6(dev);
 		return;
+	}
 	I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
 	I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
 	intel_print_rc6_info(dev, INTEL_RC6_ENABLE);
+}
 static unsigned long intel_pxfreq(u32 vidfreq)
+{
 	unsigned long freq;
 	int div = (vidfreq & 0x3f0000) >> 16;
 	int post = (vidfreq & 0x3000) >> 12;
 	int pre = (vidfreq & 0x7);
 	if (!pre)
 		return 0;
 	freq = ((div * 133333) / ((1<<post) * pre));
 	return freq;
+}
 static const struct cparams {
 	u16 i;
 	u16 t;
 	u16 m;
 	u16 c;
 } cparams[] = {
 	{ 1, 1333, 301, 28664 },
 	{ 1, 1066, 294, 24460 },
 	{ 1, 800, 294, 25192 },
 	{ 0, 1333, 276, 27605 },
 	{ 0, 1066, 276, 27605 },
 	{ 0, 800, 231, 23784 },
 };
 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
+{
 	u64 total_count, diff, ret;
 	u32 count1, count2, count3, m = 0, c = 0;
 	unsigned long now = jiffies_to_msecs(jiffies), diff1;
 	int i;
 	assert_spin_locked(&mchdev_lock);
 	diff1 = now - dev_priv->ips.last_time1;
 	/* Prevent division-by-zero if we are asking too fast.
 	 * Also, we don't get interesting results if we are polling
 	 * faster than once in 10ms, so just return the saved value
 	 * in such cases.
 	 */
 	if (diff1 <= 10)
 		return dev_priv->ips.chipset_power;
 	count1 = I915_READ(DMIEC);
 	count2 = I915_READ(DDREC);
 	count3 = I915_READ(CSIEC);
 	total_count = count1 + count2 + count3;
 	/* FIXME: handle per-counter overflow */
 	if (total_count < dev_priv->ips.last_count1) {
 		diff = ~0UL - dev_priv->ips.last_count1;
 		diff += total_count;
 	} else {
 		diff = total_count - dev_priv->ips.last_count1;
+	}
 	for (i = 0; i < ARRAY_SIZE(cparams); i++) {
 		if (cparams[i].i == dev_priv->ips.c_m &&
 		    cparams[i].t == dev_priv->ips.r_t) {
 			m = cparams[i].m;
 			c = cparams[i].c;
 			break;
+		}
+	}
 	diff = div_u64(diff, diff1);
 	ret = ((m * diff) + c);
 	ret = div_u64(ret, 10);
 	dev_priv->ips.last_count1 = total_count;
 	dev_priv->ips.last_time1 = now;
 	dev_priv->ips.chipset_power = ret;
 	return ret;
+}
 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
+{
 	struct drm_device *dev = dev_priv->dev;
 	unsigned long val;
 	if (INTEL_INFO(dev)->gen != 5)
 		return 0;
 	spin_lock_irq(&mchdev_lock);
 	val = __i915_chipset_val(dev_priv);
 	spin_unlock_irq(&mchdev_lock);
 	return val;
+}
 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
+{
 	unsigned long m, x, b;
 	u32 tsfs;
 	tsfs = I915_READ(TSFS);
 	m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
 	x = I915_READ8(TR1);
 	b = tsfs & TSFS_INTR_MASK;
 	return ((m * x) / 127) - b;
+}
 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
+{
 	struct drm_device *dev = dev_priv->dev;
 	static const struct v_table {
 		u16 vd; /* in .1 mil */
 		u16 vm; /* in .1 mil */
 	} v_table[] = {
 		{ 0, 0, },
 		{ 375, 0, },
 		{ 500, 0, },
 		{ 625, 0, },
 		{ 750, 0, },
 		{ 875, 0, },
 		{ 1000, 0, },
 		{ 1125, 0, },
 		{ 4125, 3000, },
 		{ 4125, 3000, },
 		{ 4125, 3000, },
 		{ 4125, 3000, },
 		{ 4125, 3000, },
 		{ 4125, 3000, },
 		{ 4125, 3000, },
 		{ 4125, 3000, },
 		{ 4125, 3000, },
 		{ 4125, 3000, },
 		{ 4125, 3000, },
 		{ 4125, 3000, },
 		{ 4125, 3000, },
 		{ 4125, 3000, },
 		{ 4125, 3000, },
 		{ 4125, 3000, },
 		{ 4125, 3000, },
 		{ 4125, 3000, },
 		{ 4125, 3000, },
 		{ 4125, 3000, },
 		{ 4125, 3000, },
 		{ 4125, 3000, },
 		{ 4125, 3000, },
 		{ 4125, 3000, },
 		{ 4250, 3125, },
 		{ 4375, 3250, },
 		{ 4500, 3375, },
 		{ 4625, 3500, },
 		{ 4750, 3625, },
 		{ 4875, 3750, },
 		{ 5000, 3875, },
 		{ 5125, 4000, },
 		{ 5250, 4125, },
 		{ 5375, 4250, },
 		{ 5500, 4375, },
 		{ 5625, 4500, },
 		{ 5750, 4625, },
 		{ 5875, 4750, },
 		{ 6000, 4875, },
 		{ 6125, 5000, },
 		{ 6250, 5125, },
 		{ 6375, 5250, },
 		{ 6500, 5375, },
 		{ 6625, 5500, },
 		{ 6750, 5625, },
 		{ 6875, 5750, },
 		{ 7000, 5875, },
 		{ 7125, 6000, },
 		{ 7250, 6125, },
 		{ 7375, 6250, },
 		{ 7500, 6375, },
 		{ 7625, 6500, },
 		{ 7750, 6625, },
 		{ 7875, 6750, },
 		{ 8000, 6875, },
 		{ 8125, 7000, },
 		{ 8250, 7125, },
 		{ 8375, 7250, },
 		{ 8500, 7375, },
 		{ 8625, 7500, },
 		{ 8750, 7625, },
 		{ 8875, 7750, },
 		{ 9000, 7875, },
 		{ 9125, 8000, },
 		{ 9250, 8125, },
 		{ 9375, 8250, },
 		{ 9500, 8375, },
 		{ 9625, 8500, },
 		{ 9750, 8625, },
 		{ 9875, 8750, },
 		{ 10000, 8875, },
 		{ 10125, 9000, },
 		{ 10250, 9125, },
 		{ 10375, 9250, },
 		{ 10500, 9375, },
 		{ 10625, 9500, },
 		{ 10750, 9625, },
 		{ 10875, 9750, },
 		{ 11000, 9875, },
 		{ 11125, 10000, },
 		{ 11250, 10125, },
 		{ 11375, 10250, },
 		{ 11500, 10375, },
 		{ 11625, 10500, },
 		{ 11750, 10625, },
 		{ 11875, 10750, },
 		{ 12000, 10875, },
 		{ 12125, 11000, },
 		{ 12250, 11125, },
 		{ 12375, 11250, },
 		{ 12500, 11375, },
 		{ 12625, 11500, },
 		{ 12750, 11625, },
 		{ 12875, 11750, },
 		{ 13000, 11875, },
 		{ 13125, 12000, },
 		{ 13250, 12125, },
 		{ 13375, 12250, },
 		{ 13500, 12375, },
 		{ 13625, 12500, },
 		{ 13750, 12625, },
 		{ 13875, 12750, },
 		{ 14000, 12875, },
 		{ 14125, 13000, },
 		{ 14250, 13125, },
 		{ 14375, 13250, },
 		{ 14500, 13375, },
 		{ 14625, 13500, },
 		{ 14750, 13625, },
 		{ 14875, 13750, },
 		{ 15000, 13875, },
 		{ 15125, 14000, },
 		{ 15250, 14125, },
 		{ 15375, 14250, },
 		{ 15500, 14375, },
 		{ 15625, 14500, },
 		{ 15750, 14625, },
 		{ 15875, 14750, },
 		{ 16000, 14875, },
 		{ 16125, 15000, },
 	};
 	if (INTEL_INFO(dev)->is_mobile)
 		return v_table[pxvid].vm;
 	else
 		return v_table[pxvid].vd;
+}
 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
+{
 	struct timespec now, diff1;
 	u64 diff;
 	unsigned long diffms;
 	u32 count;
 	assert_spin_locked(&mchdev_lock);
 	getrawmonotonic(&now);
 	diff1 = timespec_sub(now, dev_priv->ips.last_time2);
 	/* Don't divide by 0 */
 	diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
 	if (!diffms)
 		return;
 	count = I915_READ(GFXEC);
 	if (count < dev_priv->ips.last_count2) {
 		diff = ~0UL - dev_priv->ips.last_count2;
 		diff += count;
 	} else {
 		diff = count - dev_priv->ips.last_count2;
+	}
 	dev_priv->ips.last_count2 = count;
 	dev_priv->ips.last_time2 = now;
 	/* More magic constants... */
 	diff = diff * 1181;
 	diff = div_u64(diff, diffms * 10);
 	dev_priv->ips.gfx_power = diff;
+}
 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
+{
 	struct drm_device *dev = dev_priv->dev;
 	if (INTEL_INFO(dev)->gen != 5)
 		return;
 	spin_lock_irq(&mchdev_lock);
 	__i915_update_gfx_val(dev_priv);
 	spin_unlock_irq(&mchdev_lock);
+}
 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
+{
 	unsigned long t, corr, state1, corr2, state2;
 	u32 pxvid, ext_v;
 	assert_spin_locked(&mchdev_lock);
 	pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
 	pxvid = (pxvid >> 24) & 0x7f;
 	ext_v = pvid_to_extvid(dev_priv, pxvid);
 	state1 = ext_v;
 	t = i915_mch_val(dev_priv);
 	/* Revel in the empirically derived constants */
 	/* Correction factor in 1/100000 units */
 	if (t > 80)
 		corr = ((t * 2349) + 135940);
 	else if (t >= 50)
 		corr = ((t * 964) + 29317);
 	else /* < 50 */
 		corr = ((t * 301) + 1004);
 	corr = corr * ((150142 * state1) / 10000 - 78642);
 	corr /= 100000;
 	corr2 = (corr * dev_priv->ips.corr);
 	state2 = (corr2 * state1) / 10000;
 	state2 /= 100; /* convert to mW */
 	__i915_update_gfx_val(dev_priv);
 	return dev_priv->ips.gfx_power + state2;
+}
 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
+{
 	struct drm_device *dev = dev_priv->dev;
 	unsigned long val;
 	if (INTEL_INFO(dev)->gen != 5)
 		return 0;
 	spin_lock_irq(&mchdev_lock);
 	val = __i915_gfx_val(dev_priv);
 	spin_unlock_irq(&mchdev_lock);
 	return val;
+}
 /**
  * i915_read_mch_val - return value for IPS use
+ *
  * Calculate and return a value for the IPS driver to use when deciding whether
  * we have thermal and power headroom to increase CPU or GPU power budget.
  */
 unsigned long i915_read_mch_val(void)
+{
 	struct drm_i915_private *dev_priv;
 	unsigned long chipset_val, graphics_val, ret = 0;
 	spin_lock_irq(&mchdev_lock);
 	if (!i915_mch_dev)
 		goto out_unlock;
 	dev_priv = i915_mch_dev;
 	chipset_val = __i915_chipset_val(dev_priv);
 	graphics_val = __i915_gfx_val(dev_priv);
 	ret = chipset_val + graphics_val;
 out_unlock:
 	spin_unlock_irq(&mchdev_lock);
 	return ret;
+}
 EXPORT_SYMBOL_GPL(i915_read_mch_val);
 /**
  * i915_gpu_raise - raise GPU frequency limit
+ *
  * Raise the limit; IPS indicates we have thermal headroom.
  */
 bool i915_gpu_raise(void)
+{
 	struct drm_i915_private *dev_priv;
 	bool ret = true;
 	spin_lock_irq(&mchdev_lock);
 	if (!i915_mch_dev) {
 		ret = false;
 		goto out_unlock;
+	}
 	dev_priv = i915_mch_dev;
 	if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
 		dev_priv->ips.max_delay--;
 out_unlock:
 	spin_unlock_irq(&mchdev_lock);
 	return ret;
+}
 EXPORT_SYMBOL_GPL(i915_gpu_raise);
 /**
  * i915_gpu_lower - lower GPU frequency limit
+ *
  * IPS indicates we're close to a thermal limit, so throttle back the GPU
  * frequency maximum.
  */
 bool i915_gpu_lower(void)
+{
 	struct drm_i915_private *dev_priv;
 	bool ret = true;
 	spin_lock_irq(&mchdev_lock);
 	if (!i915_mch_dev) {
 		ret = false;
 		goto out_unlock;
+	}
 	dev_priv = i915_mch_dev;
 	if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
 		dev_priv->ips.max_delay++;
 out_unlock:
 	spin_unlock_irq(&mchdev_lock);
 	return ret;
+}
 EXPORT_SYMBOL_GPL(i915_gpu_lower);
 /**
  * i915_gpu_busy - indicate GPU business to IPS
+ *
  * Tell the IPS driver whether or not the GPU is busy.
  */
 bool i915_gpu_busy(void)
+{
 	struct drm_i915_private *dev_priv;
 	struct intel_ring_buffer *ring;
 	bool ret = false;
 	int i;
 	spin_lock_irq(&mchdev_lock);
 	if (!i915_mch_dev)
 		goto out_unlock;
 	dev_priv = i915_mch_dev;
 	for_each_ring(ring, dev_priv, i)
 		ret |= !list_empty(&ring->request_list);
 out_unlock:
 	spin_unlock_irq(&mchdev_lock);
 	return ret;
+}
 EXPORT_SYMBOL_GPL(i915_gpu_busy);
 /**
  * i915_gpu_turbo_disable - disable graphics turbo
+ *
  * Disable graphics turbo by resetting the max frequency and setting the
  * current frequency to the default.
  */
 bool i915_gpu_turbo_disable(void)
+{
 	struct drm_i915_private *dev_priv;
 	bool ret = true;
 	spin_lock_irq(&mchdev_lock);
 	if (!i915_mch_dev) {
 		ret = false;
 		goto out_unlock;
+	}
 	dev_priv = i915_mch_dev;
 	dev_priv->ips.max_delay = dev_priv->ips.fstart;
 	if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
 		ret = false;
 out_unlock:
 	spin_unlock_irq(&mchdev_lock);
 	return ret;
+}
 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
 /**
  * Tells the intel_ips driver that the i915 driver is now loaded, if
  * IPS got loaded first.
+ *
  * This awkward dance is so that neither module has to depend on the
  * other in order for IPS to do the appropriate communication of
  * GPU turbo limits to i915.
  */
 static void
 ips_ping_for_i915_load(void)
+{
 #ifndef __NetBSD__		/* XXX IPS GPU turbo limits what?  */
 	void (*link)(void);
 	link = symbol_get(ips_link_to_i915_driver);
 	if (link) {
 		link();
 		symbol_put(ips_link_to_i915_driver);
+	}
 #endif
+}
 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
+{
 	/* We only register the i915 ips part with intel-ips once everything is
 	 * set up, to avoid intel-ips sneaking in and reading bogus values. */
 	spin_lock_irq(&mchdev_lock);
 	i915_mch_dev = dev_priv;
 	spin_unlock_irq(&mchdev_lock);
 	ips_ping_for_i915_load();
+}
 void intel_gpu_ips_teardown(void)
+{
 	spin_lock_irq(&mchdev_lock);
 	i915_mch_dev = NULL;
 	spin_unlock_irq(&mchdev_lock);
+}
 static void intel_init_emon(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 lcfuse;
 	u8 pxw[16];
 	int i;
 	/* Disable to program */
 	I915_WRITE(ECR, 0);
 	POSTING_READ(ECR);
 	/* Program energy weights for various events */
 	I915_WRITE(SDEW, 0x15040d00);
 	I915_WRITE(CSIEW0, 0x007f0000);
 	I915_WRITE(CSIEW1, 0x1e220004);
 	I915_WRITE(CSIEW2, 0x04000004);
 	for (i = 0; i < 5; i++)
 		I915_WRITE(PEW + (i * 4), 0);
 	for (i = 0; i < 3; i++)
 		I915_WRITE(DEW + (i * 4), 0);
 	/* Program P-state weights to account for frequency power adjustment */
 	for (i = 0; i < 16; i++) {
 		u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
 		unsigned long freq = intel_pxfreq(pxvidfreq);
 		unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
 			PXVFREQ_PX_SHIFT;
 		unsigned long val;
 		val = vid * vid;
 		val *= (freq / 1000);
 		val *= 255;
 		val /= (127*127*900);
 		if (val > 0xff)
 			DRM_ERROR("bad pxval: %ld\n", val);
 		pxw[i] = val;
+	}
 	/* Render standby states get 0 weight */
 	pxw[14] = 0;
 	pxw[15] = 0;
 	for (i = 0; i < 4; i++) {
 		u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
 			(pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
 		I915_WRITE(PXW + (i * 4), val);
+	}
 	/* Adjust magic regs to magic values (more experimental results) */
 	I915_WRITE(OGW0, 0);
 	I915_WRITE(OGW1, 0);
 	I915_WRITE(EG0, 0x00007f00);
 	I915_WRITE(EG1, 0x0000000e);
 	I915_WRITE(EG2, 0x000e0000);
 	I915_WRITE(EG3, 0x68000300);
 	I915_WRITE(EG4, 0x42000000);
 	I915_WRITE(EG5, 0x00140031);
 	I915_WRITE(EG6, 0);
 	I915_WRITE(EG7, 0);
 	for (i = 0; i < 8; i++)
 		I915_WRITE(PXWL + (i * 4), 0);
 	/* Enable PMON + select events */
 	I915_WRITE(ECR, 0x80000019);
 	lcfuse = I915_READ(LCFUSE02);
 	dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
+}
 void intel_init_gt_powersave(struct drm_device *dev)
+{
 	if (IS_VALLEYVIEW(dev))
 		valleyview_setup_pctx(dev);
+}
 void intel_cleanup_gt_powersave(struct drm_device *dev)
+{
 	if (IS_VALLEYVIEW(dev))
 		valleyview_cleanup_pctx(dev);
+}
 void intel_disable_gt_powersave(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	/* Interrupts should be disabled already to avoid re-arming. */
 	WARN_ON(dev->irq_enabled);
 	if (IS_IRONLAKE_M(dev)) {
 		ironlake_disable_drps(dev);
 		ironlake_disable_rc6(dev);
 	} else if (INTEL_INFO(dev)->gen >= 6) {
 		cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
 		cancel_work_sync(&dev_priv->rps.work);
 		mutex_lock(&dev_priv->rps.hw_lock);
 		if (IS_VALLEYVIEW(dev))
 			valleyview_disable_rps(dev);
 		else
 			gen6_disable_rps(dev);
 		dev_priv->rps.enabled = false;
 		mutex_unlock(&dev_priv->rps.hw_lock);
+	}
+}
 static void intel_gen6_powersave_work(struct work_struct *work)
+{
 	struct drm_i915_private *dev_priv =
 		container_of(work, struct drm_i915_private,
 			     rps.delayed_resume_work.work);
 	struct drm_device *dev = dev_priv->dev;
 	mutex_lock(&dev_priv->rps.hw_lock);
 	if (IS_VALLEYVIEW(dev)) {
 		valleyview_enable_rps(dev);
 	} else if (IS_BROADWELL(dev)) {
 		gen8_enable_rps(dev);
 		gen6_update_ring_freq(dev);
 	} else {
 		gen6_enable_rps(dev);
 		gen6_update_ring_freq(dev);
+	}
 	dev_priv->rps.enabled = true;
 	mutex_unlock(&dev_priv->rps.hw_lock);
+}
 void intel_enable_gt_powersave(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	if (IS_IRONLAKE_M(dev)) {
 		ironlake_enable_drps(dev);
 		ironlake_enable_rc6(dev);
 		intel_init_emon(dev);
 	} else if (IS_GEN6(dev) || IS_GEN7(dev)) {
 		/*
 		 * PCU communication is slow and this doesn't need to be
 		 * done at any specific time, so do this out of our fast path
 		 * to make resume and init faster.
 		 */
 		schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
 				      round_jiffies_up_relative(HZ));
+	}
+}
 static void ibx_init_clock_gating(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	/*
 	 * On Ibex Peak and Cougar Point, we need to disable clock
 	 * gating for the panel power sequencer or it will fail to
 	 * start up when no ports are active.
 	 */
 	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
+}
 static void g4x_disable_trickle_feed(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int pipe;
 	for_each_pipe(pipe) {
 		I915_WRITE(DSPCNTR(pipe),
 			   I915_READ(DSPCNTR(pipe)) |
 			   DISPPLANE_TRICKLE_FEED_DISABLE);
 		intel_flush_primary_plane(dev_priv, pipe);
+	}
+}
 static void ilk_init_lp_watermarks(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
 	I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
 	I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
 	/*
 	 * Don't touch WM1S_LP_EN here.