 @@ -1,39 +1,39 @@
-/*	$NetBSD: sdhc.c,v 1.75 2015/08/03 05:24:37 mlelstv Exp $	*/
+/*	$NetBSD: sdhc.c,v 1.76 2015/08/03 10:08:51 jmcneill Exp $	*/
 /*	$OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $	*/
 /*
  * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
+ *
  * Permission to use, copy, modify, and distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
  * copyright notice and this permission notice appear in all copies.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 /*
  * SD Host Controller driver based on the SD Host Controller Standard
  * Simplified Specification Version 1.00 (www.sdcard.com).
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.75 2015/08/03 05:24:37 mlelstv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.76 2015/08/03 10:08:51 jmcneill Exp $");
 #ifdef _KERNEL_OPT
 #include "opt_sdmmc.h"
 #endif
 #include <sys/param.h>
 #include <sys/device.h>
 #include <sys/kernel.h>
 #include <sys/malloc.h>
 #include <sys/systm.h>
 #include <sys/mutex.h>
 #include <sys/condvar.h>
 @@ -164,27 +164,27 @@ hwrite2(struct sdhc_host *hp, bus_size_t
 	do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)); while (0)
 #define HSET2(hp, reg, bits)						\
 	do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)); while (0)
 #define HSET4(hp, reg, bits)						\
 	do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) | (bits)); while (0)
 static int	sdhc_host_reset(sdmmc_chipset_handle_t);
 static int	sdhc_host_reset1(sdmmc_chipset_handle_t);
 static uint32_t	sdhc_host_ocr(sdmmc_chipset_handle_t);
 static int	sdhc_host_maxblklen(sdmmc_chipset_handle_t);
 static int	sdhc_card_detect(sdmmc_chipset_handle_t);
 static int	sdhc_write_protect(sdmmc_chipset_handle_t);
 static int	sdhc_bus_power(sdmmc_chipset_handle_t, uint32_t);
-static int	sdhc_bus_clock(sdmmc_chipset_handle_t, int);
+static int	sdhc_bus_clock_ddr(sdmmc_chipset_handle_t, int, bool);
 static int	sdhc_bus_width(sdmmc_chipset_handle_t, int);
 static int	sdhc_bus_rod(sdmmc_chipset_handle_t, int);
 static void	sdhc_card_enable_intr(sdmmc_chipset_handle_t, int);
 static void	sdhc_card_intr_ack(sdmmc_chipset_handle_t);
 static void	sdhc_exec_command(sdmmc_chipset_handle_t,
 		    struct sdmmc_command *);
 static int	sdhc_signal_voltage(sdmmc_chipset_handle_t, int);
 static int	sdhc_start_command(struct sdhc_host *, struct sdmmc_command *);
 static int	sdhc_wait_state(struct sdhc_host *, uint32_t, uint32_t);
 static int	sdhc_soft_reset(struct sdhc_host *, int);
 static int	sdhc_wait_intr(struct sdhc_host *, int, int);
 static void	sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *);
 static int	sdhc_transfer_data_dma(struct sdhc_host *, struct sdmmc_command *);
 @@ -200,39 +200,40 @@ static struct sdmmc_chip_functions sdhc_
 	/* host controller capabilities */
 	.host_ocr = sdhc_host_ocr,
 	.host_maxblklen = sdhc_host_maxblklen,
 	/* card detection */
 	.card_detect = sdhc_card_detect,
 	/* write protect */
 	.write_protect = sdhc_write_protect,
 	/* bus power, clock frequency, width and ROD(OpenDrain/PushPull) */
 	.bus_power = sdhc_bus_power,
-	.bus_clock = sdhc_bus_clock,
+	.bus_clock = NULL,	/* see sdhc_bus_clock_ddr */
 	.bus_width = sdhc_bus_width,
 	.bus_rod = sdhc_bus_rod,
 	/* command execution */
 	.exec_command = sdhc_exec_command,
 	/* card interrupt */
 	.card_enable_intr = sdhc_card_enable_intr,
 	.card_intr_ack = sdhc_card_intr_ack,
 	/* UHS functions */
 	.signal_voltage = sdhc_signal_voltage,
 	.bus_clock_ddr = sdhc_bus_clock_ddr,
 };
 static int
 sdhc_cfprint(void *aux, const char *pnp)
+{
 	const struct sdmmcbus_attach_args * const saa = aux;
 	const struct sdhc_host * const hp = saa->saa_sch;
 	if (pnp) {
 		aprint_normal("sdmmc at %s", pnp);
+	}
 	for (size_t host = 0; host < hp->sc->sc_nhosts; host++) {
 		if (hp->sc->sc_host[host] == hp) {
 @@ -408,34 +409,34 @@ sdhc_host_found(struct sdhc_softc *sc, b
 	/*
 	 * Determine SD bus voltage levels supported by the controller.
 	 */
 	aprint_normal(",");
 	if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) {
 		SET(hp->ocr, MMC_OCR_HCS);
 		aprint_normal(" HS");
+	}
 	if (ISSET(caps2, SDHC_SDR50_SUPP)) {
 		SET(hp->ocr, MMC_OCR_S18A);
 		aprint_normal(" SDR50");
+	}
 	if (ISSET(caps2, SDHC_SDR104_SUPP)) {
 		SET(hp->ocr, MMC_OCR_S18A);
 		aprint_normal(" SDR104");
 	if (ISSET(caps2, SDHC_DDR50_SUPP)) {
 		SET(hp->ocr, MMC_OCR_S18A);
 		aprint_normal(" DDR50");
+	}
 	if (ISSET(caps2, SDHC_SDR104_SUPP)) {
 		SET(hp->ocr, MMC_OCR_S18A);
 		aprint_normal(" SDR104 HS200");
+	}
 	if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V)) {
 		SET(hp->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V);
 		aprint_normal(" 1.8V");
+	}
 	if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) {
 		SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V);
 		aprint_normal(" 3.0V");
+	}
 	if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) {
 		SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V);
 		aprint_normal(" 3.3V");
+	}
 @@ -524,26 +525,34 @@ adma_done:
 		saa.saa_clkmin = hp->clkbase / 256 / 16;
 	else if (hp->sc->sc_clkmsk != 0)
 		saa.saa_clkmin = hp->clkbase / (hp->sc->sc_clkmsk >>
 		    (ffs(hp->sc->sc_clkmsk) - 1));
 	else if (hp->specver >= SDHC_SPEC_VERS_300)
 		saa.saa_clkmin = hp->clkbase / 0x3ff;
 	else
 		saa.saa_clkmin = hp->clkbase / 256;
 	saa.saa_caps = SMC_CAPS_4BIT_MODE|SMC_CAPS_AUTO_STOP;
 	if (ISSET(sc->sc_flags, SDHC_FLAG_8BIT_MODE))
 		saa.saa_caps |= SMC_CAPS_8BIT_MODE;
 	if (ISSET(caps, SDHC_HIGH_SPEED_SUPP))
 		saa.saa_caps |= SMC_CAPS_SD_HIGHSPEED;
 	if (ISSET(caps2, SDHC_SDR104_SUPP))
 		saa.saa_caps |= SMC_CAPS_UHS_SDR104 |
 				SMC_CAPS_UHS_SDR50 |
 				SMC_CAPS_MMC_HS200;
 	if (ISSET(caps2, SDHC_SDR50_SUPP))
 		saa.saa_caps |= SMC_CAPS_UHS_SDR50;
 	if (ISSET(caps2, SDHC_DDR50_SUPP))
 		saa.saa_caps |= SMC_CAPS_UHS_DDR50;
 	if (ISSET(hp->flags, SHF_USE_DMA)) {
 		saa.saa_caps |= SMC_CAPS_DMA;
 		if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED))
 			saa.saa_caps |= SMC_CAPS_MULTI_SEG_DMA;
+	}
 	if (ISSET(sc->sc_flags, SDHC_FLAG_SINGLE_ONLY))
 		saa.saa_caps |= SMC_CAPS_SINGLE_ONLY;
 	hp->sdmmc = config_found(sc->sc_dev, &saa, sdhc_cfprint);
 	return 0;
 err:
 	cv_destroy(&hp->intr_cv);
 @@ -954,27 +963,27 @@ sdhc_clock_divisor(struct sdhc_host *hp,
+		}
 		/* No divisor found. */
 		return false;
+	}
 	/* No divisor found. */
 	return false;
+}
 /*
  * Set or change SDCLK frequency or disable the SD clock.
  * Return zero on success.
  */
 static int
-sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq)
+sdhc_bus_clock_ddr(sdmmc_chipset_handle_t sch, int freq, bool ddr)
+{
 	struct sdhc_host *hp = (struct sdhc_host *)sch;
 	u_int div;
 	u_int timo;
 	int16_t reg;
 	int error = 0;
 	bool present __diagused;
 	mutex_enter(&hp->intr_lock);
 #ifdef DIAGNOSTIC
 	present = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK);
 @@ -997,34 +1006,39 @@ sdhc_bus_clock(sdmmc_chipset_handle_t sc
 	if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) {
 		HCLR4(hp, SDHC_CLOCK_CTL, 0xfff8);
 		if (freq == SDMMC_SDCLK_OFF) {
 			HSET4(hp, SDHC_CLOCK_CTL, 0x80f0);
 			goto out;
+		}
 	} else {
 		HCLR2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE);
 		if (freq == SDMMC_SDCLK_OFF)
 			goto out;
+	}
 	if (hp->specver >= SDHC_SPEC_VERS_300) {
 		/* XXX DDR */
 		HCLR2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_MASK);
 		if (freq > 100000) {
 			HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_SDR104);
 		} else if (freq > 50000) {
 			HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_SDR50);
 		} else if (freq > 25000) {
-			HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_SDR25);
+			if (ddr) {
 				HSET2(hp, SDHC_HOST_CTL2,
 				    SDHC_UHS_MODE_SELECT_DDR50);
 			} else {
 				HSET2(hp, SDHC_HOST_CTL2,
 				    SDHC_UHS_MODE_SELECT_SDR25);
+			}
 		} else if (freq > 400) {
 			HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_SDR12);
+		}
+	}
 	/*
 	 * Set the minimum base clock frequency divisor.
 	 */
 	if (!sdhc_clock_divisor(hp, freq, &div)) {
 		/* Invalid base clock frequency or `freq' value. */
 		aprint_error_dev(hp->sc->sc_dev,
 			"Invalid bus clock %d kHz\n", freq);
 		error = EINVAL;

 @@ -1,14 +1,14 @@
-/*	$NetBSD: sdmmc.c,v 1.28 2015/08/03 05:32:50 mlelstv Exp $	*/
+/*	$NetBSD: sdmmc.c,v 1.29 2015/08/03 10:08:51 jmcneill Exp $	*/
 /*	$OpenBSD: sdmmc.c,v 1.18 2009/01/09 10:58:38 jsg Exp $	*/
 /*
  * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
+ *
  * Permission to use, copy, modify, and distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
  * copyright notice and this permission notice appear in all copies.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 @@ -39,27 +39,27 @@
  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Host controller independent SD/MMC bus driver based on information
  * from SanDisk SD Card Product Manual Revision 2.2 (SanDisk), SDIO
  * Simple Specification Version 1.0 (SDIO) and the Linux "mmc" driver.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sdmmc.c,v 1.28 2015/08/03 05:32:50 mlelstv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sdmmc.c,v 1.29 2015/08/03 10:08:51 jmcneill Exp $");
 #ifdef _KERNEL_OPT
 #include "opt_sdmmc.h"
 #endif
 #include <sys/param.h>
 #include <sys/device.h>
 #include <sys/kernel.h>
 #include <sys/kthread.h>
 #include <sys/malloc.h>
 #include <sys/proc.h>
 #include <sys/systm.h>
 #include <sys/callout.h>
 @@ -513,27 +513,28 @@ sdmmc_enable(struct sdmmc_softc *sc)
 	 * Calculate the equivalent of the card OCR from the host
 	 * capabilities and select the maximum supported bus voltage.
 	 */
 	error = sdmmc_chip_bus_power(sc->sc_sct, sc->sc_sch,
 	    sdmmc_chip_host_ocr(sc->sc_sct, sc->sc_sch));
 	if (error) {
 		aprint_error_dev(sc->sc_dev, "couldn't supply bus power\n");
 		goto out;
+	}
 	/*
 	 * Select the minimum clock frequency.
 	 */
-	error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, SDMMC_SDCLK_400K);
+	error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, SDMMC_SDCLK_400K,
 	    false);
 	if (error) {
 		aprint_error_dev(sc->sc_dev, "couldn't supply clock\n");
 		goto out;
+	}
 	/* XXX wait for card to power up */
 	sdmmc_delay(100000);
 	if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
 		/* Initialize SD I/O card function(s). */
 		error = sdmmc_io_enable(sc);
 		if (error) {
 			DPRINTF(1, ("%s: sdmmc_io_enable failed %d\n", DEVNAME(sc), error));
 @@ -559,27 +560,28 @@ out:
 static void
 sdmmc_disable(struct sdmmc_softc *sc)
+{
 	/* XXX complete commands if card is still present. */
 	if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) {
 		/* Make sure no card is still selected. */
 		(void)sdmmc_select_card(sc, NULL);
+	}
 	/* Turn off bus power and clock. */
 	(void)sdmmc_chip_bus_width(sc->sc_sct, sc->sc_sch, 1);
-	(void)sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, SDMMC_SDCLK_OFF);
+	(void)sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, SDMMC_SDCLK_OFF,
 	    false);
 	(void)sdmmc_chip_bus_power(sc->sc_sct, sc->sc_sch, 0);
 	sc->sc_busclk = sc->sc_clkmax;
+}
 /*
  * Set the lowest bus voltage supported by the card and the host.
  */
 int
 sdmmc_set_bus_power(struct sdmmc_softc *sc, uint32_t host_ocr,
     uint32_t card_ocr)
+{
 	uint32_t bit;

 @@ -1,14 +1,14 @@
-/*	$NetBSD: sdmmc_mem.c,v 1.38 2015/08/03 05:32:50 mlelstv Exp $	*/
+/*	$NetBSD: sdmmc_mem.c,v 1.39 2015/08/03 10:08:51 jmcneill Exp $	*/
 /*	$OpenBSD: sdmmc_mem.c,v 1.10 2009/01/09 10:55:22 jsg Exp $	*/
 /*
  * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
+ *
  * Permission to use, copy, modify, and distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
  * copyright notice and this permission notice appear in all copies.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 @@ -35,27 +35,27 @@
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 /* Routines for SD/MMC memory cards. */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sdmmc_mem.c,v 1.38 2015/08/03 05:32:50 mlelstv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sdmmc_mem.c,v 1.39 2015/08/03 10:08:51 jmcneill Exp $");
 #ifdef _KERNEL_OPT
 #include "opt_sdmmc.h"
 #endif
 #include <sys/param.h>
 #include <sys/kernel.h>
 #include <sys/malloc.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <dev/sdmmc/sdmmcchip.h>
 #include <dev/sdmmc/sdmmcreg.h>
 @@ -86,26 +86,47 @@ static int sdmmc_mem_spi_read_ocr(struct
 static int sdmmc_mem_single_read_block(struct sdmmc_function *, uint32_t,
     u_char *, size_t);
 static int sdmmc_mem_single_write_block(struct sdmmc_function *, uint32_t,
     u_char *, size_t);
 static int sdmmc_mem_single_segment_dma_read_block(struct sdmmc_function *,
     uint32_t, u_char *, size_t);
 static int sdmmc_mem_single_segment_dma_write_block(struct sdmmc_function *,
     uint32_t, u_char *, size_t);
 static int sdmmc_mem_read_block_subr(struct sdmmc_function *, bus_dmamap_t,
     uint32_t, u_char *, size_t);
 static int sdmmc_mem_write_block_subr(struct sdmmc_function *, bus_dmamap_t,
     uint32_t, u_char *, size_t);
 static const struct {
 	const char *name;
 	int v;
 	int freq;
 } switch_group0_functions[] = {
 	/* Default/SDR12 */
 	{ "Default/SDR12",	 0,			 25000 },
 	/* High-Speed/SDR25 */
 	{ "High-Speed/SDR25",	SMC_CAPS_SD_HIGHSPEED,	 50000 },
 	/* SDR50 */
 	{ "SDR50",		SMC_CAPS_UHS_SDR50,	100000 },
 	/* SDR104 */
 	{ "SDR104",		SMC_CAPS_UHS_SDR104,	208000 },
 	/* DDR50 */
 	{ "DDR50",		SMC_CAPS_UHS_DDR50,	 50000 },
 };
 /*
  * Initialize SD/MMC memory cards and memory in SDIO "combo" cards.
  */
 int
 sdmmc_mem_enable(struct sdmmc_softc *sc)
+{
 	uint32_t host_ocr;
 	uint32_t card_ocr;
 	uint32_t new_ocr;
 	uint32_t ocr = 0;
 	int error;
 	SDMMC_LOCK(sc);
 @@ -211,47 +232,48 @@ mmc_mode:
 		error = sdmmc_mmc_command(sc, &cmd);
 		if (error) {
 			DPRINTF(("%s: voltage switch command failed\n",
 			    SDMMCDEVNAME(sc)));
 			goto out;
+		}
 		delay(1000);
 		/*
 		 * Stop the clock
 		 */
 		error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch,
-		    SDMMC_SDCLK_OFF);
+		    SDMMC_SDCLK_OFF, false);
 		if (error)
 			goto out;
 		delay(1000);
 		/*
 		 * Card switch command was successful, update host controller
 		 * signal voltage setting.
 		 */
 		error = sdmmc_chip_signal_voltage(sc->sc_sct,
 		    sc->sc_sch, SDMMC_SIGNAL_VOLTAGE_180);
 		if (error)
 			goto out;
 		delay(5000);
 		/*
 		 * Switch to SDR12 timing
 		 */
-		error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, 25000);
+		error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, 25000,
 		    false);
 		if (error)
 			goto out;
 		delay(1000);
 		SET(sc->sc_flags, SMF_UHS_MODE);
+	}
 out:
 	SDMMC_UNLOCK(sc);
 	if (error)
 		printf("%s: %s failed with error %d\n", SDMMCDEVNAME(sc),
 @@ -662,214 +684,258 @@ static void
 sdmmc_be512_to_bitfield512(sdmmc_bitfield512_t *buf) {
 	size_t i;
 	uint32_t tmp0, tmp1;
 	const size_t bitswords = __arraycount(buf->_bits);
 	for (i = 0; i < bitswords/2; i++) {
 		tmp0 = buf->_bits[i];
 		tmp1 = buf->_bits[bitswords - 1 - i];
 		buf->_bits[i] = be32toh(tmp1);
 		buf->_bits[bitswords - 1 - i] = be32toh(tmp0);
+	}
+}
 static int
 sdmmc_mem_select_transfer_mode(struct sdmmc_softc *sc, int support_func)
+{
 	if (ISSET(sc->sc_flags, SMF_UHS_MODE)) {
 		if (ISSET(sc->sc_caps, SMC_CAPS_UHS_SDR104) &&
 		    ISSET(support_func, SD_ACCESS_MODE_SDR104)) {
 			return SD_ACCESS_MODE_SDR104;
+		}
 		if (ISSET(sc->sc_caps, SMC_CAPS_UHS_DDR50) &&
 		    ISSET(support_func, SD_ACCESS_MODE_DDR50)) {
 			return SD_ACCESS_MODE_DDR50;
+		}
 		if (ISSET(sc->sc_caps, SMC_CAPS_UHS_SDR50) &&
 		    ISSET(support_func, SD_ACCESS_MODE_SDR50)) {
 			return SD_ACCESS_MODE_SDR50;
+		}
+	}
 	if (ISSET(sc->sc_caps, SMC_CAPS_SD_HIGHSPEED) &&
 	    ISSET(support_func, SD_ACCESS_MODE_SDR25)) {
 		return SD_ACCESS_MODE_SDR25;
+	}
 	return SD_ACCESS_MODE_SDR12;
+}
 static int
 sdmmc_mem_sd_init(struct sdmmc_softc *sc, struct sdmmc_function *sf)
+{
-	static const struct {
+	int support_func, best_func, bus_clock, error, i;
 		int v;
 		int freq;
 		int uhs;
 	} switch_group0_functions[] = {
 		/* Default/SDR12 */
 		{ MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V |
 		  MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V,	 25000, 0 },
 		/* High-Speed/SDR25 */
 		{ MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V |
 		  MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V,	 50000, 0 },
 		/* SDR50 */
 		{ MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V,	100000, 1 },
 		/* SDR104 */
 		{ MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V,	208000, 1 },
 #if notyet
 		/* DDR50 */
 		{ MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V,	 50000, 1 },
 #endif
 	};
 	int host_ocr, support_func, best_func, bus_clock, error, g, i;
 	sdmmc_bitfield512_t status; /* Switch Function Status */
 	bool ddr = false;
 	/* change bus clock */
 	bus_clock = min(sc->sc_busclk, sf->csd.tran_speed);
-	error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, bus_clock);
+	error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, bus_clock, false);
 	if (error) {
 		aprint_error_dev(sc->sc_dev, "can't change bus clock\n");
 		return error;
+	}
 	error = sdmmc_mem_send_scr(sc, sf, sf->raw_scr);
 	if (error) {
 		aprint_error_dev(sc->sc_dev, "SD_SEND_SCR send failed.\n");
 		return error;
+	}
 	error = sdmmc_mem_decode_scr(sc, sf);
 	if (error)
 		return error;
 	if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE) &&
 	    ISSET(sf->scr.bus_width, SCR_SD_BUS_WIDTHS_4BIT)) {
 		DPRINTF(("%s: change bus width\n", SDMMCDEVNAME(sc)));
 		error = sdmmc_set_bus_width(sf, 4);
 		if (error) {
 			aprint_error_dev(sc->sc_dev,
 			    "can't change bus width (%d bit)\n", 4);
 			return error;
+		}
 		sf->width = 4;
+	}
 	best_func = 0;
 	if (sf->scr.sd_spec >= SCR_SD_SPEC_VER_1_10 &&
 	    ISSET(sf->csd.ccc, SD_CSD_CCC_SWITCH)) {
 		DPRINTF(("%s: switch func mode 0\n", SDMMCDEVNAME(sc)));
 		error = sdmmc_mem_sd_switch(sf, 0, 1, 0, &status);
 		if (error) {
 			aprint_error_dev(sc->sc_dev,
 			    "switch func mode 0 failed\n");
 			return error;
+		}
 		host_ocr = sdmmc_chip_host_ocr(sc->sc_sct, sc->sc_sch);
 		support_func = SFUNC_STATUS_GROUP(&status, 1);
 		DPRINTF(("%s: support_func %#x\n", SDMMCDEVNAME(sc), support_func));
-		best_func = 0;
+		for (i = 0; i < __arraycount(switch_group0_functions); i++) {
-		for (i = 0, g = 1;
+			if (!(support_func & (1 << i)))
 		    i < __arraycount(switch_group0_functions); i++, g <<= 1) {
 			if (!(switch_group0_functions[i].v & host_ocr))
 				continue;
-			if (switch_group0_functions[i].uhs &&
+			DPRINTF(("%s: card supports mode %s\n",
-			    !ISSET(sc->sc_flags, SMF_UHS_MODE))
+			    SDMMCDEVNAME(sc),
-				break;
+			    switch_group0_functions[i].name));
 			if (g & support_func)
 				best_func = i;
+		}
 		if (ISSET(sc->sc_caps, SMC_CAPS_SD_HIGHSPEED) &&
-		    best_func != 0) {
+		best_func = sdmmc_mem_select_transfer_mode(sc, support_func);
 		DPRINTF(("%s: using mode %s\n", SDMMCDEVNAME(sc),
 		    switch_group0_functions[best_func].name));
 		if (best_func != 0) {
 			DPRINTF(("%s: switch func mode 1(func=%d)\n",
 			    SDMMCDEVNAME(sc), best_func));
 			error =
 			    sdmmc_mem_sd_switch(sf, 1, 1, best_func, &status);
 			if (error) {
 				aprint_error_dev(sc->sc_dev,
 				    "switch func mode 1 failed:"
 				    " group 1 function %d(0x%2x)\n",
 				    best_func, support_func);
 				return error;
+			}
 			sf->csd.tran_speed =
 			    switch_group0_functions[best_func].freq;
 			if (best_func == SD_ACCESS_MODE_DDR50)
 				ddr = true;
 			/* Wait 400KHz x 8 clock (2.5us * 8 + slop) */
 			delay(25);
+		}
+	}
 	/* update bus clock */
 	if (sc->sc_busclk > sf->csd.tran_speed)
 		sc->sc_busclk = sf->csd.tran_speed;
-	if (sc->sc_busclk == bus_clock)
+	if (sc->sc_busclk == bus_clock && sc->sc_busddr == ddr)
 		return 0;
 	/* change bus clock */
-	error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, sc->sc_busclk);
+	error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, sc->sc_busclk,
 	    ddr);
 	if (error) {
 		aprint_error_dev(sc->sc_dev, "can't change bus clock\n");
 		return error;
+	}
 	sc->sc_transfer_mode = switch_group0_functions[best_func].name;
 	sc->sc_busddr = ddr;
 	return 0;
+}
 static int
 sdmmc_mem_mmc_init(struct sdmmc_softc *sc, struct sdmmc_function *sf)
+{
 	int width, value, hs_timing, bus_clock, error;
 	char ext_csd[512];
 	uint32_t sectors = 0;
 	int host_ocr;
 	sc->sc_transfer_mode = NULL;
 	/* change bus clock */
 	bus_clock = min(sc->sc_busclk, sf->csd.tran_speed);
-	error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, bus_clock);
+	error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, bus_clock, false);
 	if (error) {
 		aprint_error_dev(sc->sc_dev, "can't change bus clock\n");
 		return error;
+	}
 	host_ocr = sdmmc_chip_host_ocr(sc->sc_sct, sc->sc_sch);
 	if (sf->csd.mmcver >= MMC_CSD_MMCVER_4_0) {
 		error = sdmmc_mem_send_cxd_data(sc,
 		    MMC_SEND_EXT_CSD, ext_csd, sizeof(ext_csd));
 		if (error) {
 			aprint_error_dev(sc->sc_dev,
 			    "can't read EXT_CSD (error=%d)\n", error);
 			return error;
+		}
 		if ((sf->csd.csdver == MMC_CSD_CSDVER_EXT_CSD) &&
 		    (ext_csd[EXT_CSD_STRUCTURE] > EXT_CSD_STRUCTURE_VER_1_2)) {
 			aprint_error_dev(sc->sc_dev,
 			    "unrecognised future version (%d)\n",
 				ext_csd[EXT_CSD_STRUCTURE]);
 			return ENOTSUP;
+		}
-		if (ISSET(host_ocr, MMC_OCR_1_7V_1_8V|MMC_OCR_1_8V_1_9V) &&
+		sc->sc_transfer_mode = NULL;
 		if (ISSET(sc->sc_caps, SMC_CAPS_MMC_HS200) &&
 		    ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_F_HS200_1_8V) {
 			sf->csd.tran_speed = 200000;	/* 200MHz SDR */
 			hs_timing = 2;
 		} else if (ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_F_52M) {
 			sf->csd.tran_speed = 52000;	/* 52MHz */
 			hs_timing = 1;
 		} else if (ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_F_26M) {
 			sf->csd.tran_speed = 26000;	/* 26MHz */
 			hs_timing = 0;
 		} else {
 			aprint_error_dev(sc->sc_dev,
 			    "unknown CARD_TYPE: 0x%x\n",
 			    ext_csd[EXT_CSD_CARD_TYPE]);
 			return ENOTSUP;
+		}
-		if (!ISSET(sc->sc_caps, SMC_CAPS_MMC_HIGHSPEED)) {
+		if (hs_timing == 2) {
 			error = sdmmc_chip_signal_voltage(sc->sc_sct,
 			    sc->sc_sch, SDMMC_SIGNAL_VOLTAGE_180);
 			if (error)
 				hs_timing = 1;
+		}
 		if (ISSET(sc->sc_caps, SMC_CAPS_8BIT_MODE)) {
 			width = 8;
 			value = EXT_CSD_BUS_WIDTH_8;
 		} else if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE)) {
 			width = 4;
 			value = EXT_CSD_BUS_WIDTH_4;
 		} else {
 			width = 1;
 			value = EXT_CSD_BUS_WIDTH_1;
+		}
 		if (width != 1) {
 			error = sdmmc_mem_mmc_switch(sf, EXT_CSD_CMD_SET_NORMAL,
 			    EXT_CSD_BUS_WIDTH, value);
 			if (error == 0)
 				error = sdmmc_chip_bus_width(sc->sc_sct,
 				    sc->sc_sch, width);
 			else {
 				DPRINTF(("%s: can't change bus width"
 				    " (%d bit)\n", SDMMCDEVNAME(sc), width));
 				return error;
+			}
 			/* XXXX: need bus test? (using by CMD14 & CMD19) */
+		}
 		sf->width = width;
 		if (hs_timing == 1 &&
 		    !ISSET(sc->sc_caps, SMC_CAPS_MMC_HIGHSPEED)) {
 			hs_timing = 0;
+		}
 		if (hs_timing) {
 			error = sdmmc_mem_mmc_switch(sf, EXT_CSD_CMD_SET_NORMAL,
 			    EXT_CSD_HS_TIMING, hs_timing);
 			if (error) {
 				aprint_error_dev(sc->sc_dev,
 				    "can't change high speed\n");
 				return error;
+			}
+		}
 		if (sc->sc_busclk > sf->csd.tran_speed)
 			sc->sc_busclk = sf->csd.tran_speed;
 		if (sc->sc_busclk != bus_clock) {
 			error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch,
-			    sc->sc_busclk);
+			    sc->sc_busclk, false);
 			if (error) {
 				aprint_error_dev(sc->sc_dev,
 				    "can't change bus clock\n");
 				return error;
+			}
+		}
 		if (hs_timing) {
 			error = sdmmc_mem_send_cxd_data(sc,
 			    MMC_SEND_EXT_CSD, ext_csd, sizeof(ext_csd));
 			if (error) {
 				aprint_error_dev(sc->sc_dev,
 				    "can't re-read EXT_CSD\n");
 @@ -881,58 +947,37 @@ sdmmc_mem_mmc_init(struct sdmmc_softc *s
 				return EINVAL;
+			}
+		}
 		sectors = ext_csd[EXT_CSD_SEC_COUNT + 0] << 0 |
 		    ext_csd[EXT_CSD_SEC_COUNT + 1] << 8  |
 		    ext_csd[EXT_CSD_SEC_COUNT + 2] << 16 |
 		    ext_csd[EXT_CSD_SEC_COUNT + 3] << 24;
 		if (sectors > (2u * 1024 * 1024 * 1024) / 512) {
 			SET(sf->flags, SFF_SDHC);
 			sf->csd.capacity = sectors;
+		}
-		if (ISSET(sc->sc_caps, SMC_CAPS_8BIT_MODE)) {
+		if (hs_timing == 2) {
-			width = 8;
+			sc->sc_transfer_mode = "HS200";
 			value = EXT_CSD_BUS_WIDTH_8;
 		} else if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE)) {
 			width = 4;
 			value = EXT_CSD_BUS_WIDTH_4;
 		} else {
-			width = 1;
+			sc->sc_transfer_mode = NULL;
 			value = EXT_CSD_BUS_WIDTH_1;
+		}
 		if (width != 1) {
 			error = sdmmc_mem_mmc_switch(sf, EXT_CSD_CMD_SET_NORMAL,
 			    EXT_CSD_BUS_WIDTH, value);
 			if (error == 0)
 				error = sdmmc_chip_bus_width(sc->sc_sct,
 				    sc->sc_sch, width);
 			else {
 				DPRINTF(("%s: can't change bus width"
 				    " (%d bit)\n", SDMMCDEVNAME(sc), width));
 				return error;
 			/* XXXX: need bus test? (using by CMD14 & CMD19) */
 		sf->width = width;
 	} else {
 		if (sc->sc_busclk > sf->csd.tran_speed)
 			sc->sc_busclk = sf->csd.tran_speed;
 		if (sc->sc_busclk != bus_clock) {
 			error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch,
-			    sc->sc_busclk);
+			    sc->sc_busclk, false);
 			if (error) {
 				aprint_error_dev(sc->sc_dev,
 				    "can't change bus clock\n");
 				return error;
+			}
+		}
+	}
 	return 0;
+}
 static int
 sdmmc_mem_send_cid(struct sdmmc_softc *sc, sdmmc_response *resp)
 @@ -1073,31 +1118,31 @@ sdmmc_mem_decode_scr(struct sdmmc_softc
 	memset(resp, 0, sizeof(resp));
 	/*
 	 * Change the raw-scr received from the DMA stream to resp.
 	 */
 	resp[0] = be32toh(sf->raw_scr[1]) >> 8;		// LSW
 	resp[1] = be32toh(sf->raw_scr[0]);		// MSW
 	resp[0] |= (resp[1] & 0xff) << 24;
 	resp[1] >>= 8;
 	ver = SCR_STRUCTURE(resp);
 	sf->scr.sd_spec = SCR_SD_SPEC(resp);
 	sf->scr.bus_width = SCR_SD_BUS_WIDTHS(resp);
-	DPRINTF(("%s: sdmmc_mem_decode_scr: %08x%08x spec=%d, bus width=%d\n",
+	DPRINTF(("%s: sdmmc_mem_decode_scr: %08x%08x ver=%d, spec=%d, bus width=%d, spec3=%d\n",
 	    SDMMCDEVNAME(sc), resp[1], resp[0],
-	    sf->scr.sd_spec, sf->scr.bus_width));
+	    ver, sf->scr.sd_spec, sf->scr.bus_width, sf->scr.sd_spec3));
-	if (ver != 0) {
+	if (ver != 0 && ver != 1) {
 		DPRINTF(("%s: unknown structure version: %d\n",
 		    SDMMCDEVNAME(sc), ver));
 		return EINVAL;
+	}
 	return 0;
+}
 static int
 sdmmc_mem_send_cxd_data(struct sdmmc_softc *sc, int opcode, void *data,
     size_t datalen)
+{
 	struct sdmmc_command cmd;
 	bus_dma_segment_t ds[1];

 @@ -1,14 +1,14 @@
-/*	$NetBSD: sdmmcvar.h,v 1.17 2015/08/02 21:44:36 jmcneill Exp $	*/
+/*	$NetBSD: sdmmcvar.h,v 1.18 2015/08/03 10:08:51 jmcneill Exp $	*/
 /*	$OpenBSD: sdmmcvar.h,v 1.13 2009/01/09 10:55:22 jsg Exp $	*/
 /*
  * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
+ *
  * Permission to use, copy, modify, and distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
  * copyright notice and this permission notice appear in all copies.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 @@ -219,52 +219,59 @@ struct sdmmc_softc {
 #define SMF_UHS_MODE		0x10000	/* host in UHS mode */
 	uint32_t sc_caps;		/* host capability */
 #define SMC_CAPS_AUTO_STOP	0x0001	/* send CMD12 automagically by host */
 #define SMC_CAPS_4BIT_MODE	0x0002	/* 4-bits data bus width */
 #define SMC_CAPS_DMA		0x0004	/* DMA transfer */
 #define SMC_CAPS_SPI_MODE	0x0008	/* SPI mode */
 #define SMC_CAPS_POLL_CARD_DET	0x0010	/* Polling card detect */
 #define SMC_CAPS_SINGLE_ONLY	0x0020	/* only single read/write */
 #define SMC_CAPS_8BIT_MODE	0x0040	/* 8-bits data bus width */
 #define SMC_CAPS_MULTI_SEG_DMA	0x0080	/* multiple segment DMA transfer */
 #define SMC_CAPS_SD_HIGHSPEED	0x0100	/* SD high-speed timing */
 #define SMC_CAPS_MMC_HIGHSPEED	0x0200	/* MMC high-speed timing */
 #define SMC_CAPS_UHS_SDR50	0x1000	/* UHS SDR50 timing */
 #define SMC_CAPS_UHS_SDR104	0x2000	/* UHS SDR104 timing */
 #define SMC_CAPS_UHS_DDR50	0x4000	/* UHS DDR50 timing */
 #define SMC_CAPS_UHS_MASK	0x7000
 #define SMC_CAPS_MMC_HS200	0x8000	/* eMMC HS200 timing */
 	/* function */
 	int sc_function_count;		/* number of I/O functions (SDIO) */
 	struct sdmmc_function *sc_card;	/* selected card */
 	struct sdmmc_function *sc_fn0;	/* function 0, the card itself */
 	SIMPLEQ_HEAD(, sdmmc_function) sf_head; /* list of card functions */
 	/* task queue */
 	struct lwp *sc_tskq_lwp;	/* asynchronous tasks */
 	TAILQ_HEAD(, sdmmc_task) sc_tskq;   /* task thread work queue */
 	struct kmutex sc_tskq_mtx;
 	struct kcondvar sc_tskq_cv;
 	/* discover task */
 	struct sdmmc_task sc_discover_task; /* card attach/detach task */
 	struct kmutex sc_discover_task_mtx;
 	/* interrupt task */
 	struct sdmmc_task sc_intr_task;	/* card interrupt task */
 	struct kmutex sc_intr_task_mtx;
 	TAILQ_HEAD(, sdmmc_intr_handler) sc_intrq; /* interrupt handlers */
 	u_int sc_clkmin;		/* host min bus clock */
 	u_int sc_clkmax;		/* host max bus clock */
 	u_int sc_busclk;		/* host bus clock */
 	bool sc_busddr;			/* host bus clock is in DDR mode */
 	int sc_buswidth;		/* host bus width */
 	const char *sc_transfer_mode;	/* current transfer mode */
 	callout_t sc_card_detect_ch;	/* polling card insert/remove */
 };
 /*
  * Attach devices at the sdmmc bus.
  */
 struct sdmmc_attach_args {
 	uint16_t manufacturer;
 	uint16_t product;
 	int interface;
 	struct sdmmc_function *sf;
 };

 @@ -1,14 +1,14 @@
-/*	$NetBSD: sdmmcchip.h,v 1.5 2015/08/02 21:44:36 jmcneill Exp $	*/
+/*	$NetBSD: sdmmcchip.h,v 1.6 2015/08/03 10:08:51 jmcneill Exp $	*/
 /*	$OpenBSD: sdmmcchip.h,v 1.3 2007/05/31 10:09:01 uwe Exp $	*/
 /*
  * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
+ *
  * Permission to use, copy, modify, and distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
  * copyright notice and this permission notice appear in all copies.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 @@ -50,47 +50,48 @@ struct sdmmc_chip_functions {
 	int		(*bus_width)(sdmmc_chipset_handle_t, int);
 	int		(*bus_rod)(sdmmc_chipset_handle_t, int);
 	/* command execution */
 	void		(*exec_command)(sdmmc_chipset_handle_t,
 			    struct sdmmc_command *);
 	/* card interrupt */
 	void		(*card_enable_intr)(sdmmc_chipset_handle_t, int);
 	void		(*card_intr_ack)(sdmmc_chipset_handle_t);
 	/* UHS functions */
 	int		(*signal_voltage)(sdmmc_chipset_handle_t, int);
 	int		(*bus_clock_ddr)(sdmmc_chipset_handle_t, int, bool);
 };
 /* host controller reset */
 #define sdmmc_chip_host_reset(tag, handle)				\
 	((tag)->host_reset((handle)))
 /* host capabilities */
 #define sdmmc_chip_host_ocr(tag, handle)				\
 	((tag)->host_ocr((handle)))
 #define sdmmc_chip_host_maxblklen(tag, handle)				\
 	((tag)->host_maxblklen((handle)))
 /* card detection */
 #define sdmmc_chip_card_detect(tag, handle)				\
 	((tag)->card_detect((handle)))
 /* write protect */
 #define sdmmc_chip_write_protect(tag, handle)				\
 	((tag)->write_protect((handle)))
 /* bus power, clock frequency, width and rod */
 #define sdmmc_chip_bus_power(tag, handle, ocr)				\
 	((tag)->bus_power((handle), (ocr)))
-#define sdmmc_chip_bus_clock(tag, handle, freq)				\
+#define sdmmc_chip_bus_clock(tag, handle, freq, ddr)			\
-	((tag)->bus_clock((handle), (freq)))
+	((tag)->bus_clock_ddr ? (tag)->bus_clock_ddr((handle), (freq), (ddr)) : ((ddr) ? EINVAL : ((tag)->bus_clock((handle), (freq)))))
 #define sdmmc_chip_bus_width(tag, handle, width)			\
 	((tag)->bus_width((handle), (width)))
 #define sdmmc_chip_bus_rod(tag, handle, width)				\
 	((tag)->bus_rod((handle), (width)))
 /* command execution */
 #define sdmmc_chip_exec_command(tag, handle, cmdp)			\
 	((tag)->exec_command((handle), (cmdp)))
 /* card interrupt */
 #define sdmmc_chip_card_enable_intr(tag, handle, enable)		\
 	((tag)->card_enable_intr((handle), (enable)))
 #define sdmmc_chip_card_intr_ack(tag, handle)				\
 	((tag)->card_intr_ack((handle)))
 /* UHS functions */

 @@ -1,14 +1,14 @@
-/*	$NetBSD: sdmmcreg.h,v 1.17 2015/08/02 22:47:05 jmcneill Exp $	*/
+/*	$NetBSD: sdmmcreg.h,v 1.18 2015/08/03 10:08:51 jmcneill Exp $	*/
 /*	$OpenBSD: sdmmcreg.h,v 1.4 2009/01/09 10:55:22 jsg Exp $	*/
 /*
  * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
+ *
  * Permission to use, copy, modify, and distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
  * copyright notice and this permission notice appear in all copies.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 @@ -324,26 +324,32 @@
 #define  SCR_SD_BUS_WIDTHS_1BIT		(1 << 0) /* 1bit (DAT0) */
 #define  SCR_SD_BUS_WIDTHS_4BIT		(1 << 2) /* 4bit (DAT0-3) */
 #define SCR_SD_SPEC3(scr)		MMC_RSP_BITS((scr), 47, 1)
 #define SCR_EX_SECURITY(scr)		MMC_RSP_BITS((scr), 43, 4)
 #define SCR_RESERVED(scr)		MMC_RSP_BITS((scr), 34, 9)
 #define SCR_CMD_SUPPORT_CMD23(scr)	MMC_RSP_BITS((scr), 33, 1)
 #define SCR_CMD_SUPPORT_CMD20(scr)	MMC_RSP_BITS((scr), 32, 1)
 #define SCR_RESERVED2(scr)		MMC_RSP_BITS((scr), 0, 32)
 /* Status of Switch Function */
 #define SFUNC_STATUS_GROUP(status, group) \
 	(__bitfield((uint32_t *)(status), 400 + (group - 1) * 16, 16))
 #define SD_ACCESS_MODE_SDR12	0
 #define SD_ACCESS_MODE_SDR25	1
 #define SD_ACCESS_MODE_SDR50	2
 #define SD_ACCESS_MODE_SDR104	3
 #define SD_ACCESS_MODE_DDR50	4
 /* This assumes the response fields are in host byte order in 32-bit units.  */
 #define MMC_RSP_BITS(resp, start, len)	__bitfield((resp), (start)-8, (len))
 static inline uint32_t
 __bitfield(const uint32_t *src, size_t start, size_t len)
+{
 	if (start + len > 512 || len == 0 || len > 32)
 		return 0;
 	src += start / 32;
 	start %= 32;
 	uint32_t dst = src[0] >> start;