 @@ -1,14 +1,14 @@
-/*	$NetBSD: if_wm.c,v 1.353 2015/10/13 07:53:02 knakahara Exp $	*/
+/*	$NetBSD: if_wm.c,v 1.354 2015/10/13 08:00:15 knakahara Exp $	*/
 /*
  * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
 @@ -73,27 +73,27 @@
  * TODO (in order of importance):
+ *
  *	- Check XXX'ed comments
  *	- EEE (Energy Efficiency Ethernet)
  *	- Multi queue
  *	- Image Unique ID
  *	- LPLU other than PCH*
  *	- Virtual Function
  *	- Set LED correctly (based on contents in EEPROM)
  *	- Rework how parameters are loaded from the EEPROM.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.353 2015/10/13 07:53:02 knakahara Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.354 2015/10/13 08:00:15 knakahara Exp $");
 #ifdef _KERNEL_OPT
 #include "opt_net_mpsafe.h"
 #endif
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/callout.h>
 #include <sys/mbuf.h>
 #include <sys/malloc.h>
 #include <sys/kernel.h>
 #include <sys/socket.h>
 #include <sys/ioctl.h>
 @@ -209,55 +209,33 @@ int	wm_debug = WM_DEBUG_TX | WM_DEBUG_RX
 #define	WM_MAXTXDMA		 (2 * round_page(IP_MAXPACKET)) /* for TSO */
 /*
  * Receive descriptor list size.  We have one Rx buffer for normal
  * sized packets.  Jumbo packets consume 5 Rx buffers for a full-sized
  * packet.  We allocate 256 receive descriptors, each with a 2k
  * buffer (MCLBYTES), which gives us room for 50 jumbo packets.
  */
 #define	WM_NRXDESC		256
 #define	WM_NRXDESC_MASK		(WM_NRXDESC - 1)
 #define	WM_NEXTRX(x)		(((x) + 1) & WM_NRXDESC_MASK)
 #define	WM_PREVRX(x)		(((x) - 1) & WM_NRXDESC_MASK)
-/*
+typedef union txdescs {
- * Control structures are DMA'd to the i82542 chip.  We allocate them in
+	wiseman_txdesc_t sctxu_txdescs[WM_NTXDESC_82544];
- * a single clump that maps to a single DMA segment to make several things
+	nq_txdesc_t      sctxu_nq_txdescs[WM_NTXDESC_82544];
- * easier.
+} txdescs_t;
  */
 struct wm_control_data_82544 {
 	/*
 	 * The receive descriptors.
 	 */
 	wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC];
-	/*
+#define	WM_CDTXOFF(x)	(sizeof(wiseman_txdesc_t) * x)
-	 * The transmit descriptors.  Put these at the end, because
+#define	WM_CDRXOFF(x)	(sizeof(wiseman_rxdesc_t) * x)
 	 * we might use a smaller number of them.
 	 */
 	union {
 		wiseman_txdesc_t wcdu_txdescs[WM_NTXDESC_82544];
 		nq_txdesc_t      wcdu_nq_txdescs[WM_NTXDESC_82544];
 	} wdc_u;
 };
 struct wm_control_data_82542 {
 	wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC];
 	wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82542];
 };
 #define	WM_CDOFF(x)	offsetof(struct wm_control_data_82544, x)
 #define	WM_CDTXOFF(x)	WM_CDOFF(wdc_u.wcdu_txdescs[(x)])
 #define	WM_CDRXOFF(x)	WM_CDOFF(wcd_rxdescs[(x)])
 /*
  * Software state for transmit jobs.
  */
 struct wm_txsoft {
 	struct mbuf *txs_mbuf;		/* head of our mbuf chain */
 	bus_dmamap_t txs_dmamap;	/* our DMA map */
 	int txs_firstdesc;		/* first descriptor in packet */
 	int txs_lastdesc;		/* last descriptor in packet */
 	int txs_ndesc;			/* # of descriptors used */
 };
 /*
 @@ -336,37 +314,44 @@ struct wm_softc {
 	int sc_nvm_ver_minor;
 	int sc_nvm_ver_build;
 	int sc_nvm_addrbits;		/* NVM address bits */
 	unsigned int sc_nvm_wordsize;	/* NVM word size */
 	int sc_ich8_flash_base;
 	int sc_ich8_flash_bank_size;
 	int sc_nvm_k1_enabled;
 	/* Software state for the transmit and receive descriptors. */
 	int sc_txnum;			/* must be a power of two */
 	struct wm_txsoft sc_txsoft[WM_TXQUEUELEN_MAX];
 	struct wm_rxsoft sc_rxsoft[WM_NRXDESC];
-	/* Control data structures. */
+	/* TX control data structures. */
 	int sc_ntxdesc;			/* must be a power of two */
-	struct wm_control_data_82544 *sc_control_data;
+	txdescs_t *sc_txdescs_u;
-	bus_dmamap_t sc_cddmamap;	/* control data DMA map */
+	bus_dmamap_t sc_txdesc_dmamap;	/* control data DMA map */
-	bus_dma_segment_t sc_cd_seg;	/* control data segment */
+	bus_dma_segment_t sc_txdesc_seg;/* control data segment */
-	int sc_cd_rseg;			/* real number of control segment */
+	int sc_txdesc_rseg;		/* real number of control segment */
-	size_t sc_cd_size;		/* control data size */
+	size_t sc_txdesc_size;		/* control data size */
-#define	sc_cddma	sc_cddmamap->dm_segs[0].ds_addr
+#define	sc_txdesc_dma	sc_txdesc_dmamap->dm_segs[0].ds_addr
-#define	sc_txdescs	sc_control_data->wdc_u.wcdu_txdescs
+#define	sc_txdescs	sc_txdescs_u->sctxu_txdescs
-#define	sc_nq_txdescs	sc_control_data->wdc_u.wcdu_nq_txdescs
+#define	sc_nq_txdescs	sc_txdescs_u->sctxu_nq_txdescs
 #define	sc_rxdescs	sc_control_data->wcd_rxdescs
 	/* RX control data structures. */
 	wiseman_rxdesc_t *sc_rxdescs;
 	bus_dmamap_t sc_rxdesc_dmamap;	/* control data DMA map */
 	bus_dma_segment_t sc_rxdesc_seg;/* control data segment */
 	int sc_rxdesc_rseg;		/* real number of control segment */
 	size_t sc_rxdesc_size;		/* control data size */
 #define	sc_rxdesc_dma	sc_rxdesc_dmamap->dm_segs[0].ds_addr
 #ifdef WM_EVENT_COUNTERS
 	/* Event counters. */
 	struct evcnt sc_ev_txsstall;	/* Tx stalled due to no txs */
 	struct evcnt sc_ev_txdstall;	/* Tx stalled due to no txd */
 	struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */
 	struct evcnt sc_ev_txdw;	/* Tx descriptor interrupts */
 	struct evcnt sc_ev_txqe;	/* Tx queue empty interrupts */
 	struct evcnt sc_ev_rxintr;	/* Rx interrupts */
 	struct evcnt sc_ev_linkintr;	/* Link interrupts */
 	struct evcnt sc_ev_rxipsum;	/* IP checksums checked in-bound */
 	struct evcnt sc_ev_rxtusum;	/* TCP/UDP cksums checked in-bound */
 @@ -483,28 +468,28 @@ do {									\
 #define	CSR_WRITE_FLUSH(sc)						\
 	(void) CSR_READ((sc), WMREG_STATUS)
 #define ICH8_FLASH_READ32(sc, reg) \
 	bus_space_read_4((sc)->sc_flasht, (sc)->sc_flashh, (reg))
 #define ICH8_FLASH_WRITE32(sc, reg, data) \
 	bus_space_write_4((sc)->sc_flasht, (sc)->sc_flashh, (reg), (data))
 #define ICH8_FLASH_READ16(sc, reg) \
 	bus_space_read_2((sc)->sc_flasht, (sc)->sc_flashh, (reg))
 #define ICH8_FLASH_WRITE16(sc, reg, data) \
 	bus_space_write_2((sc)->sc_flasht, (sc)->sc_flashh, (reg), (data))
-#define	WM_CDTXADDR(sc, x)	((sc)->sc_cddma + WM_CDTXOFF((x)))
+#define	WM_CDTXADDR(sc, x)	((sc)->sc_txdesc_dma + WM_CDTXOFF((x)))
-#define	WM_CDRXADDR(sc, x)	((sc)->sc_cddma + WM_CDRXOFF((x)))
+#define	WM_CDRXADDR(sc, x)	((sc)->sc_rxdesc_dma + WM_CDRXOFF((x)))
 #define	WM_CDTXADDR_LO(sc, x)	(WM_CDTXADDR((sc), (x)) & 0xffffffffU)
 #define	WM_CDTXADDR_HI(sc, x)						\
 	(sizeof(bus_addr_t) == 8 ?					\
 	 (uint64_t)WM_CDTXADDR((sc), (x)) >> 32 : 0)
 #define	WM_CDRXADDR_LO(sc, x)	(WM_CDRXADDR((sc), (x)) & 0xffffffffU)
 #define	WM_CDRXADDR_HI(sc, x)						\
 	(sizeof(bus_addr_t) == 8 ?					\
 	 (uint64_t)WM_CDRXADDR((sc), (x)) >> 32 : 0)
 /*
  * Register read/write functions.
 @@ -556,28 +541,30 @@ static uint32_t	wm_rxpbs_adjust_82580(ui
 static void	wm_reset(struct wm_softc *);
 static int	wm_add_rxbuf(struct wm_softc *, int);
 static void	wm_rxdrain(struct wm_softc *);
 static int	wm_init(struct ifnet *);
 static int	wm_init_locked(struct ifnet *);
 static void	wm_stop(struct ifnet *, int);
 static void	wm_stop_locked(struct ifnet *, int);
 static int	wm_tx_offload(struct wm_softc *, struct wm_txsoft *,
     uint32_t *, uint8_t *);
 static void	wm_dump_mbuf_chain(struct wm_softc *, struct mbuf *);
 static void	wm_82547_txfifo_stall(void *);
 static int	wm_82547_txfifo_bugchk(struct wm_softc *, struct mbuf *);
 /* DMA related */
-static int	wm_alloc_descs(struct wm_softc *);
+static int	wm_alloc_tx_descs(struct wm_softc *);
-static void	wm_free_descs(struct wm_softc *);
+static void	wm_free_tx_descs(struct wm_softc *);
 static int	wm_alloc_rx_descs(struct wm_softc *);
 static void	wm_free_rx_descs(struct wm_softc *);
 static int	wm_alloc_tx_buffer(struct wm_softc *);
 static void	wm_free_tx_buffer(struct wm_softc *);
 static int	wm_alloc_rx_buffer(struct wm_softc *);
 static void	wm_free_rx_buffer(struct wm_softc *);
 static int	wm_alloc_txrx_queues(struct wm_softc *);
 static void	wm_free_txrx_queues(struct wm_softc *);
 /* Start */
 static void	wm_start(struct ifnet *);
 static void	wm_start_locked(struct ifnet *);
 static int	wm_nq_tx_offload(struct wm_softc *, struct wm_txsoft *,
     uint32_t *, uint32_t *, bool *);
 static void	wm_nq_start(struct ifnet *);
 static void	wm_nq_start_locked(struct ifnet *);
 @@ -1336,43 +1323,43 @@ wm_set_dma_addr(volatile wiseman_addr_t
 	else
 		wa->wa_high = 0;
+}
 /*
  * Descriptor sync/init functions.
  */
 static inline void
 wm_cdtxsync(struct wm_softc *sc, int start, int num, int ops)
+{
 	/* If it will wrap around, sync to the end of the ring. */
 	if ((start + num) > WM_NTXDESC(sc)) {
-		bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap,
+		bus_dmamap_sync(sc->sc_dmat, sc->sc_txdesc_dmamap,
 		    WM_CDTXOFF(start), sizeof(wiseman_txdesc_t) *
 		    (WM_NTXDESC(sc) - start), ops);
 		num -= (WM_NTXDESC(sc) - start);
 		start = 0;
+	}
 	/* Now sync whatever is left. */
-	bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap,
+	bus_dmamap_sync(sc->sc_dmat, sc->sc_txdesc_dmamap,
 	    WM_CDTXOFF(start), sizeof(wiseman_txdesc_t) * num, ops);
+}
 static inline void
 wm_cdrxsync(struct wm_softc *sc, int start, int ops)
+{
-	bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap,
+	bus_dmamap_sync(sc->sc_dmat, sc->sc_rxdesc_dmamap,
 	    WM_CDRXOFF(start), sizeof(wiseman_rxdesc_t), ops);
+}
 static inline void
 wm_init_rxdesc(struct wm_softc *sc, int start)
+{
 	struct wm_rxsoft *rxs = &sc->sc_rxsoft[start];
 	wiseman_rxdesc_t *rxd = &sc->sc_rxdescs[start];
 	struct mbuf *m = rxs->rxs_mbuf;
 	/*
 	 * Note: We scoot the packet forward 2 bytes in the buffer
 	 * so that the payload after the Ethernet header is aligned
 @@ -5086,100 +5073,175 @@ wm_82547_txfifo_bugchk(struct wm_softc *
 		callout_schedule(&sc->sc_txfifo_ch, 1);
 		return 1;
+	}
  send_packet:
 	sc->sc_txfifo_head += len;
 	if (sc->sc_txfifo_head >= sc->sc_txfifo_size)
 		sc->sc_txfifo_head -= sc->sc_txfifo_size;
 	return 0;
+}
 static int
-wm_alloc_descs(struct wm_softc *sc)
+wm_alloc_tx_descs(struct wm_softc *sc)
+{
 	int error;
 	/*
 	 * Allocate the control data structures, and create and load the
 	 * DMA map for it.
+	 *
 	 * NOTE: All Tx descriptors must be in the same 4G segment of
 	 * memory.  So must Rx descriptors.  We simplify by allocating
 	 * both sets within the same 4G segment.
 	 */
 	if (sc->sc_type < WM_T_82544) {
 		WM_NTXDESC(sc) = WM_NTXDESC_82542;
 		sc->sc_txdesc_size = sizeof(wiseman_txdesc_t) * WM_NTXDESC(sc);
 	} else {
 		WM_NTXDESC(sc) = WM_NTXDESC_82544;
 		sc->sc_txdesc_size = sizeof(txdescs_t);
+	}
 	if ((error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_txdesc_size, PAGE_SIZE,
 		    (bus_size_t) 0x100000000ULL, &sc->sc_txdesc_seg, 1,
 		    &sc->sc_txdesc_rseg, 0)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to allocate TX control data, error = %d\n",
 		    error);
 		goto fail_0;
+	}
 	if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_txdesc_seg,
 		    sc->sc_txdesc_rseg, sc->sc_txdesc_size,
 		    (void **)&sc->sc_txdescs_u, BUS_DMA_COHERENT)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to map TX control data, error = %d\n", error);
 		goto fail_1;
+	}
 	if ((error = bus_dmamap_create(sc->sc_dmat, sc->sc_txdesc_size, 1,
 		    sc->sc_txdesc_size, 0, 0, &sc->sc_txdesc_dmamap)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to create TX control data DMA map, error = %d\n",
 		    error);
 		goto fail_2;
+	}
 	if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_txdesc_dmamap,
 		    sc->sc_txdescs_u, sc->sc_txdesc_size, NULL, 0)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to load TX control data DMA map, error = %d\n",
 		    error);
 		goto fail_3;
+	}
 	return 0;
  fail_3:
 	bus_dmamap_destroy(sc->sc_dmat, sc->sc_txdesc_dmamap);
  fail_2:
 	bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_txdescs_u,
 	    sc->sc_txdesc_size);
  fail_1:
 	bus_dmamem_free(sc->sc_dmat, &sc->sc_txdesc_seg, sc->sc_txdesc_rseg);
  fail_0:
 	return error;
+}
 static void
 wm_free_tx_descs(struct wm_softc *sc)
+{
 	bus_dmamap_unload(sc->sc_dmat, sc->sc_txdesc_dmamap);
 	bus_dmamap_destroy(sc->sc_dmat, sc->sc_txdesc_dmamap);
 	bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_txdescs_u,
 	    sc->sc_txdesc_size);
 	bus_dmamem_free(sc->sc_dmat, &sc->sc_txdesc_seg, sc->sc_txdesc_rseg);
+}
 static int
 wm_alloc_rx_descs(struct wm_softc *sc)
+{
 	int error;
 	/*
 	 * Allocate the control data structures, and create and load the
 	 * DMA map for it.
+	 *
 	 * NOTE: All Tx descriptors must be in the same 4G segment of
 	 * memory.  So must Rx descriptors.  We simplify by allocating
 	 * both sets within the same 4G segment.
 	 */
-	WM_NTXDESC(sc) = sc->sc_type < WM_T_82544 ?
+	sc->sc_rxdesc_size = sizeof(wiseman_rxdesc_t) * WM_NRXDESC;
-	    WM_NTXDESC_82542 : WM_NTXDESC_82544;
+	if ((error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_rxdesc_size, PAGE_SIZE,
-	sc->sc_cd_size = sc->sc_type < WM_T_82544 ?
+		    (bus_size_t) 0x100000000ULL, &sc->sc_rxdesc_seg, 1,
-	    sizeof(struct wm_control_data_82542) :
+		    &sc->sc_rxdesc_rseg, 0)) != 0) {
 	    sizeof(struct wm_control_data_82544);
 	if ((error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_cd_size, PAGE_SIZE,
 		    (bus_size_t) 0x100000000ULL, &sc->sc_cd_seg, 1,
 		    &sc->sc_cd_rseg, 0)) != 0) {
 		aprint_error_dev(sc->sc_dev,
-		    "unable to allocate control data, error = %d\n",
+		    "unable to allocate RX control data, error = %d\n",
 		    error);
 		goto fail_0;
+	}
-	if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cd_seg,
+	if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_rxdesc_seg,
-		    sc->sc_cd_rseg, sc->sc_cd_size,
+		    sc->sc_rxdesc_rseg, sc->sc_rxdesc_size,
-		    (void **)&sc->sc_control_data, BUS_DMA_COHERENT)) != 0) {
+		    (void **)&sc->sc_rxdescs, BUS_DMA_COHERENT)) != 0) {
 		aprint_error_dev(sc->sc_dev,
-		    "unable to map control data, error = %d\n", error);
+		    "unable to map RX control data, error = %d\n", error);
 		goto fail_1;
+	}
-	if ((error = bus_dmamap_create(sc->sc_dmat, sc->sc_cd_size, 1,
+	if ((error = bus_dmamap_create(sc->sc_dmat, sc->sc_rxdesc_size, 1,
-		    sc->sc_cd_size, 0, 0, &sc->sc_cddmamap)) != 0) {
+		    sc->sc_rxdesc_size, 0, 0, &sc->sc_rxdesc_dmamap)) != 0) {
 		aprint_error_dev(sc->sc_dev,
-		    "unable to create control data DMA map, error = %d\n",
+		    "unable to create RX control data DMA map, error = %d\n",
 		    error);
 		goto fail_2;
+	}
-	if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
+	if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_rxdesc_dmamap,
-		    sc->sc_control_data, sc->sc_cd_size, NULL, 0)) != 0) {
+		    sc->sc_rxdescs, sc->sc_rxdesc_size, NULL, 0)) != 0) {
 		aprint_error_dev(sc->sc_dev,
-		    "unable to load control data DMA map, error = %d\n",
+		    "unable to load RX control data DMA map, error = %d\n",
 		    error);
 		goto fail_3;
+	}
 	return 0;
  fail_3:
-	bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
+	bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxdesc_dmamap);
  fail_2:
-	bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data,
+	bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_rxdescs,
-	    sc->sc_cd_size);
+	    sc->sc_rxdesc_size);
  fail_1:
-	bus_dmamem_free(sc->sc_dmat, &sc->sc_cd_seg, sc->sc_cd_rseg);
+	bus_dmamem_free(sc->sc_dmat, &sc->sc_rxdesc_seg, sc->sc_rxdesc_rseg);
  fail_0:
 	return error;
+}
 static void
-wm_free_descs(struct wm_softc *sc)
+wm_free_rx_descs(struct wm_softc *sc)
+{
-	bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
+	bus_dmamap_unload(sc->sc_dmat, sc->sc_rxdesc_dmamap);
-	bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
+	bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxdesc_dmamap);
-	bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data,
+	bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_rxdescs,
-	    sc->sc_cd_size);
+	    sc->sc_rxdesc_size);
-	bus_dmamem_free(sc->sc_dmat, &sc->sc_cd_seg, sc->sc_cd_rseg);
+	bus_dmamem_free(sc->sc_dmat, &sc->sc_rxdesc_seg, sc->sc_rxdesc_rseg);
+}
 static int
 wm_alloc_tx_buffer(struct wm_softc *sc)
+{
 	int i, error;
 	/* Create the transmit buffer DMA maps. */
 	WM_TXQUEUELEN(sc) =
 	    (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ?
 	    WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX;
 	for (i = 0; i < WM_TXQUEUELEN(sc); i++) {
 		if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA,
 			    WM_NTXSEGS, WTX_MAX_LEN, 0, 0,
 			    &sc->sc_txsoft[i].txs_dmamap)) != 0) {
 @@ -5253,59 +5315,72 @@ wm_free_rx_buffer(struct wm_softc *sc)
 			    sc->sc_rxsoft[i].rxs_dmamap);
+	}
+}
 /*
  * wm_alloc_quques:
  *	Allocate {tx,rx}descs and {tx,rx} buffers
  */
 static int
 wm_alloc_txrx_queues(struct wm_softc *sc)
+{
 	int error;
-	error = wm_alloc_descs(sc);
+	/*
 	 * For transmission
 	 */
 	error = wm_alloc_tx_descs(sc);
 	if (error)
 		goto fail_0;
 	error = wm_alloc_tx_buffer(sc);
 	if (error)
 		goto fail_1;
-	error = wm_alloc_rx_buffer(sc);
+	/*
 	 * For recieve
 	 */
 	error = wm_alloc_rx_descs(sc);
 	if (error)
 		goto fail_2;
 	error = wm_alloc_rx_buffer(sc);
 	if (error)
 		goto fail_3;
 	return 0;
 fail_3:
 	wm_free_rx_descs(sc);
 fail_2:
 	wm_free_tx_buffer(sc);
 fail_1:
-	wm_free_descs(sc);
+	wm_free_tx_descs(sc);
 fail_0:
 	return error;
+}
 /*
  * wm_free_quques:
  *	Free {tx,rx}descs and {tx,rx} buffers
  */
 static void
 wm_free_txrx_queues(struct wm_softc *sc)
+{
 	wm_free_rx_buffer(sc);
 	wm_free_rx_descs(sc);
 	wm_free_tx_buffer(sc);
-	wm_free_descs(sc);
+	wm_free_tx_descs(sc);
+}
 /*
  * wm_start:		[ifnet interface function]
+ *
  *	Start packet transmission on the interface.
  */
 static void
 wm_start(struct ifnet *ifp)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	WM_TX_LOCK(sc);