| @@ -1,2901 +1,2901 @@ | | | @@ -1,2901 +1,2901 @@ |
1 | /* $NetBSD: if_wm.c,v 1.358 2015/10/13 08:14:27 knakahara Exp $ */ | | 1 | /* $NetBSD: if_wm.c,v 1.359 2015/10/13 08:17:15 knakahara Exp $ */ |
2 | | | 2 | |
3 | /* | | 3 | /* |
4 | * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc. | | 4 | * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc. |
5 | * All rights reserved. | | 5 | * All rights reserved. |
6 | * | | 6 | * |
7 | * Written by Jason R. Thorpe for Wasabi Systems, Inc. | | 7 | * Written by Jason R. Thorpe for Wasabi Systems, Inc. |
8 | * | | 8 | * |
9 | * Redistribution and use in source and binary forms, with or without | | 9 | * Redistribution and use in source and binary forms, with or without |
10 | * modification, are permitted provided that the following conditions | | 10 | * modification, are permitted provided that the following conditions |
11 | * are met: | | 11 | * are met: |
12 | * 1. Redistributions of source code must retain the above copyright | | 12 | * 1. Redistributions of source code must retain the above copyright |
13 | * notice, this list of conditions and the following disclaimer. | | 13 | * notice, this list of conditions and the following disclaimer. |
14 | * 2. Redistributions in binary form must reproduce the above copyright | | 14 | * 2. Redistributions in binary form must reproduce the above copyright |
15 | * notice, this list of conditions and the following disclaimer in the | | 15 | * notice, this list of conditions and the following disclaimer in the |
16 | * documentation and/or other materials provided with the distribution. | | 16 | * documentation and/or other materials provided with the distribution. |
17 | * 3. All advertising materials mentioning features or use of this software | | 17 | * 3. All advertising materials mentioning features or use of this software |
18 | * must display the following acknowledgement: | | 18 | * must display the following acknowledgement: |
19 | * This product includes software developed for the NetBSD Project by | | 19 | * This product includes software developed for the NetBSD Project by |
20 | * Wasabi Systems, Inc. | | 20 | * Wasabi Systems, Inc. |
21 | * 4. The name of Wasabi Systems, Inc. may not be used to endorse | | 21 | * 4. The name of Wasabi Systems, Inc. may not be used to endorse |
22 | * or promote products derived from this software without specific prior | | 22 | * or promote products derived from this software without specific prior |
23 | * written permission. | | 23 | * written permission. |
24 | * | | 24 | * |
25 | * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND | | 25 | * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND |
26 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED | | 26 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
27 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | | 27 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
28 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC | | 28 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC |
29 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | | 29 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
30 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | | 30 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
31 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | | 31 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
32 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | | 32 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
33 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | | 33 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
34 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | | 34 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
35 | * POSSIBILITY OF SUCH DAMAGE. | | 35 | * POSSIBILITY OF SUCH DAMAGE. |
36 | */ | | 36 | */ |
37 | | | 37 | |
38 | /******************************************************************************* | | 38 | /******************************************************************************* |
39 | | | 39 | |
40 | Copyright (c) 2001-2005, Intel Corporation | | 40 | Copyright (c) 2001-2005, Intel Corporation |
41 | All rights reserved. | | 41 | All rights reserved. |
42 | | | 42 | |
43 | Redistribution and use in source and binary forms, with or without | | 43 | Redistribution and use in source and binary forms, with or without |
44 | modification, are permitted provided that the following conditions are met: | | 44 | modification, are permitted provided that the following conditions are met: |
45 | | | 45 | |
46 | 1. Redistributions of source code must retain the above copyright notice, | | 46 | 1. Redistributions of source code must retain the above copyright notice, |
47 | this list of conditions and the following disclaimer. | | 47 | this list of conditions and the following disclaimer. |
48 | | | 48 | |
49 | 2. Redistributions in binary form must reproduce the above copyright | | 49 | 2. Redistributions in binary form must reproduce the above copyright |
50 | notice, this list of conditions and the following disclaimer in the | | 50 | notice, this list of conditions and the following disclaimer in the |
51 | documentation and/or other materials provided with the distribution. | | 51 | documentation and/or other materials provided with the distribution. |
52 | | | 52 | |
53 | 3. Neither the name of the Intel Corporation nor the names of its | | 53 | 3. Neither the name of the Intel Corporation nor the names of its |
54 | contributors may be used to endorse or promote products derived from | | 54 | contributors may be used to endorse or promote products derived from |
55 | this software without specific prior written permission. | | 55 | this software without specific prior written permission. |
56 | | | 56 | |
57 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | | 57 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
58 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | | 58 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
59 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | | 59 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
60 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | | 60 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
61 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | | 61 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
62 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | | 62 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
63 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | | 63 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
64 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | | 64 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
65 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | | 65 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
66 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | | 66 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
67 | POSSIBILITY OF SUCH DAMAGE. | | 67 | POSSIBILITY OF SUCH DAMAGE. |
68 | | | 68 | |
69 | *******************************************************************************/ | | 69 | *******************************************************************************/ |
70 | /* | | 70 | /* |
71 | * Device driver for the Intel i8254x family of Gigabit Ethernet chips. | | 71 | * Device driver for the Intel i8254x family of Gigabit Ethernet chips. |
72 | * | | 72 | * |
73 | * TODO (in order of importance): | | 73 | * TODO (in order of importance): |
74 | * | | 74 | * |
75 | * - Check XXX'ed comments | | 75 | * - Check XXX'ed comments |
76 | * - EEE (Energy Efficiency Ethernet) | | 76 | * - EEE (Energy Efficiency Ethernet) |
77 | * - Multi queue | | 77 | * - Multi queue |
78 | * - Image Unique ID | | 78 | * - Image Unique ID |
79 | * - LPLU other than PCH* | | 79 | * - LPLU other than PCH* |
80 | * - Virtual Function | | 80 | * - Virtual Function |
81 | * - Set LED correctly (based on contents in EEPROM) | | 81 | * - Set LED correctly (based on contents in EEPROM) |
82 | * - Rework how parameters are loaded from the EEPROM. | | 82 | * - Rework how parameters are loaded from the EEPROM. |
83 | */ | | 83 | */ |
84 | | | 84 | |
85 | #include <sys/cdefs.h> | | 85 | #include <sys/cdefs.h> |
86 | __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.358 2015/10/13 08:14:27 knakahara Exp $"); | | 86 | __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.359 2015/10/13 08:17:15 knakahara Exp $"); |
87 | | | 87 | |
88 | #ifdef _KERNEL_OPT | | 88 | #ifdef _KERNEL_OPT |
89 | #include "opt_net_mpsafe.h" | | 89 | #include "opt_net_mpsafe.h" |
90 | #endif | | 90 | #endif |
91 | | | 91 | |
92 | #include <sys/param.h> | | 92 | #include <sys/param.h> |
93 | #include <sys/systm.h> | | 93 | #include <sys/systm.h> |
94 | #include <sys/callout.h> | | 94 | #include <sys/callout.h> |
95 | #include <sys/mbuf.h> | | 95 | #include <sys/mbuf.h> |
96 | #include <sys/malloc.h> | | 96 | #include <sys/malloc.h> |
97 | #include <sys/kmem.h> | | 97 | #include <sys/kmem.h> |
98 | #include <sys/kernel.h> | | 98 | #include <sys/kernel.h> |
99 | #include <sys/socket.h> | | 99 | #include <sys/socket.h> |
100 | #include <sys/ioctl.h> | | 100 | #include <sys/ioctl.h> |
101 | #include <sys/errno.h> | | 101 | #include <sys/errno.h> |
102 | #include <sys/device.h> | | 102 | #include <sys/device.h> |
103 | #include <sys/queue.h> | | 103 | #include <sys/queue.h> |
104 | #include <sys/syslog.h> | | 104 | #include <sys/syslog.h> |
105 | #include <sys/interrupt.h> | | 105 | #include <sys/interrupt.h> |
106 | | | 106 | |
107 | #include <sys/rndsource.h> | | 107 | #include <sys/rndsource.h> |
108 | | | 108 | |
109 | #include <net/if.h> | | 109 | #include <net/if.h> |
110 | #include <net/if_dl.h> | | 110 | #include <net/if_dl.h> |
111 | #include <net/if_media.h> | | 111 | #include <net/if_media.h> |
112 | #include <net/if_ether.h> | | 112 | #include <net/if_ether.h> |
113 | | | 113 | |
114 | #include <net/bpf.h> | | 114 | #include <net/bpf.h> |
115 | | | 115 | |
116 | #include <netinet/in.h> /* XXX for struct ip */ | | 116 | #include <netinet/in.h> /* XXX for struct ip */ |
117 | #include <netinet/in_systm.h> /* XXX for struct ip */ | | 117 | #include <netinet/in_systm.h> /* XXX for struct ip */ |
118 | #include <netinet/ip.h> /* XXX for struct ip */ | | 118 | #include <netinet/ip.h> /* XXX for struct ip */ |
119 | #include <netinet/ip6.h> /* XXX for struct ip6_hdr */ | | 119 | #include <netinet/ip6.h> /* XXX for struct ip6_hdr */ |
120 | #include <netinet/tcp.h> /* XXX for struct tcphdr */ | | 120 | #include <netinet/tcp.h> /* XXX for struct tcphdr */ |
121 | | | 121 | |
122 | #include <sys/bus.h> | | 122 | #include <sys/bus.h> |
123 | #include <sys/intr.h> | | 123 | #include <sys/intr.h> |
124 | #include <machine/endian.h> | | 124 | #include <machine/endian.h> |
125 | | | 125 | |
126 | #include <dev/mii/mii.h> | | 126 | #include <dev/mii/mii.h> |
127 | #include <dev/mii/miivar.h> | | 127 | #include <dev/mii/miivar.h> |
128 | #include <dev/mii/miidevs.h> | | 128 | #include <dev/mii/miidevs.h> |
129 | #include <dev/mii/mii_bitbang.h> | | 129 | #include <dev/mii/mii_bitbang.h> |
130 | #include <dev/mii/ikphyreg.h> | | 130 | #include <dev/mii/ikphyreg.h> |
131 | #include <dev/mii/igphyreg.h> | | 131 | #include <dev/mii/igphyreg.h> |
132 | #include <dev/mii/igphyvar.h> | | 132 | #include <dev/mii/igphyvar.h> |
133 | #include <dev/mii/inbmphyreg.h> | | 133 | #include <dev/mii/inbmphyreg.h> |
134 | | | 134 | |
135 | #include <dev/pci/pcireg.h> | | 135 | #include <dev/pci/pcireg.h> |
136 | #include <dev/pci/pcivar.h> | | 136 | #include <dev/pci/pcivar.h> |
137 | #include <dev/pci/pcidevs.h> | | 137 | #include <dev/pci/pcidevs.h> |
138 | | | 138 | |
139 | #include <dev/pci/if_wmreg.h> | | 139 | #include <dev/pci/if_wmreg.h> |
140 | #include <dev/pci/if_wmvar.h> | | 140 | #include <dev/pci/if_wmvar.h> |
141 | | | 141 | |
142 | #ifdef WM_DEBUG | | 142 | #ifdef WM_DEBUG |
143 | #define WM_DEBUG_LINK 0x01 | | 143 | #define WM_DEBUG_LINK 0x01 |
144 | #define WM_DEBUG_TX 0x02 | | 144 | #define WM_DEBUG_TX 0x02 |
145 | #define WM_DEBUG_RX 0x04 | | 145 | #define WM_DEBUG_RX 0x04 |
146 | #define WM_DEBUG_GMII 0x08 | | 146 | #define WM_DEBUG_GMII 0x08 |
147 | #define WM_DEBUG_MANAGE 0x10 | | 147 | #define WM_DEBUG_MANAGE 0x10 |
148 | #define WM_DEBUG_NVM 0x20 | | 148 | #define WM_DEBUG_NVM 0x20 |
149 | int wm_debug = WM_DEBUG_TX | WM_DEBUG_RX | WM_DEBUG_LINK | WM_DEBUG_GMII | | 149 | int wm_debug = WM_DEBUG_TX | WM_DEBUG_RX | WM_DEBUG_LINK | WM_DEBUG_GMII |
150 | | WM_DEBUG_MANAGE | WM_DEBUG_NVM; | | 150 | | WM_DEBUG_MANAGE | WM_DEBUG_NVM; |
151 | | | 151 | |
152 | #define DPRINTF(x, y) if (wm_debug & (x)) printf y | | 152 | #define DPRINTF(x, y) if (wm_debug & (x)) printf y |
153 | #else | | 153 | #else |
154 | #define DPRINTF(x, y) /* nothing */ | | 154 | #define DPRINTF(x, y) /* nothing */ |
155 | #endif /* WM_DEBUG */ | | 155 | #endif /* WM_DEBUG */ |
156 | | | 156 | |
157 | #ifdef NET_MPSAFE | | 157 | #ifdef NET_MPSAFE |
158 | #define WM_MPSAFE 1 | | 158 | #define WM_MPSAFE 1 |
159 | #endif | | 159 | #endif |
160 | | | 160 | |
161 | #ifdef __HAVE_PCI_MSI_MSIX | | 161 | #ifdef __HAVE_PCI_MSI_MSIX |
162 | #define WM_MSI_MSIX 1 /* Enable by default */ | | 162 | #define WM_MSI_MSIX 1 /* Enable by default */ |
163 | #endif | | 163 | #endif |
164 | | | 164 | |
165 | /* | | 165 | /* |
166 | * This device driver divides interrupt to TX, RX and link state. | | 166 | * This device driver divides interrupt to TX, RX and link state. |
167 | * Each MSI-X vector indexes are below. | | 167 | * Each MSI-X vector indexes are below. |
168 | */ | | 168 | */ |
169 | #define WM_MSIX_NINTR 3 | | 169 | #define WM_MSIX_NINTR 3 |
170 | #define WM_MSIX_TXINTR_IDX 0 | | 170 | #define WM_MSIX_TXINTR_IDX 0 |
171 | #define WM_MSIX_RXINTR_IDX 1 | | 171 | #define WM_MSIX_RXINTR_IDX 1 |
172 | #define WM_MSIX_LINKINTR_IDX 2 | | 172 | #define WM_MSIX_LINKINTR_IDX 2 |
173 | #define WM_MAX_NINTR WM_MSIX_NINTR | | 173 | #define WM_MAX_NINTR WM_MSIX_NINTR |
174 | | | 174 | |
175 | /* | | 175 | /* |
176 | * This device driver set affinity to each interrupts like below (round-robin). | | 176 | * This device driver set affinity to each interrupts like below (round-robin). |
177 | * If the number CPUs is less than the number of interrupts, this driver usase | | 177 | * If the number CPUs is less than the number of interrupts, this driver usase |
178 | * the same CPU for multiple interrupts. | | 178 | * the same CPU for multiple interrupts. |
179 | */ | | 179 | */ |
180 | #define WM_MSIX_TXINTR_CPUID 0 | | 180 | #define WM_MSIX_TXINTR_CPUID 0 |
181 | #define WM_MSIX_RXINTR_CPUID 1 | | 181 | #define WM_MSIX_RXINTR_CPUID 1 |
182 | #define WM_MSIX_LINKINTR_CPUID 2 | | 182 | #define WM_MSIX_LINKINTR_CPUID 2 |
183 | | | 183 | |
184 | /* | | 184 | /* |
185 | * Transmit descriptor list size. Due to errata, we can only have | | 185 | * Transmit descriptor list size. Due to errata, we can only have |
186 | * 256 hardware descriptors in the ring on < 82544, but we use 4096 | | 186 | * 256 hardware descriptors in the ring on < 82544, but we use 4096 |
187 | * on >= 82544. We tell the upper layers that they can queue a lot | | 187 | * on >= 82544. We tell the upper layers that they can queue a lot |
188 | * of packets, and we go ahead and manage up to 64 (16 for the i82547) | | 188 | * of packets, and we go ahead and manage up to 64 (16 for the i82547) |
189 | * of them at a time. | | 189 | * of them at a time. |
190 | * | | 190 | * |
191 | * We allow up to 256 (!) DMA segments per packet. Pathological packet | | 191 | * We allow up to 256 (!) DMA segments per packet. Pathological packet |
192 | * chains containing many small mbufs have been observed in zero-copy | | 192 | * chains containing many small mbufs have been observed in zero-copy |
193 | * situations with jumbo frames. | | 193 | * situations with jumbo frames. |
194 | */ | | 194 | */ |
195 | #define WM_NTXSEGS 256 | | 195 | #define WM_NTXSEGS 256 |
196 | #define WM_IFQUEUELEN 256 | | 196 | #define WM_IFQUEUELEN 256 |
197 | #define WM_TXQUEUELEN_MAX 64 | | 197 | #define WM_TXQUEUELEN_MAX 64 |
198 | #define WM_TXQUEUELEN_MAX_82547 16 | | 198 | #define WM_TXQUEUELEN_MAX_82547 16 |
199 | #define WM_TXQUEUELEN(txq) ((txq)->txq_num) | | 199 | #define WM_TXQUEUELEN(txq) ((txq)->txq_num) |
200 | #define WM_TXQUEUELEN_MASK(txq) (WM_TXQUEUELEN(txq) - 1) | | 200 | #define WM_TXQUEUELEN_MASK(txq) (WM_TXQUEUELEN(txq) - 1) |
201 | #define WM_TXQUEUE_GC(txq) (WM_TXQUEUELEN(txq) / 8) | | 201 | #define WM_TXQUEUE_GC(txq) (WM_TXQUEUELEN(txq) / 8) |
202 | #define WM_NTXDESC_82542 256 | | 202 | #define WM_NTXDESC_82542 256 |
203 | #define WM_NTXDESC_82544 4096 | | 203 | #define WM_NTXDESC_82544 4096 |
204 | #define WM_NTXDESC(txq) ((txq)->txq_ndesc) | | 204 | #define WM_NTXDESC(txq) ((txq)->txq_ndesc) |
205 | #define WM_NTXDESC_MASK(txq) (WM_NTXDESC(txq) - 1) | | 205 | #define WM_NTXDESC_MASK(txq) (WM_NTXDESC(txq) - 1) |
206 | #define WM_TXDESCSIZE(txq) (WM_NTXDESC(txq) * sizeof(wiseman_txdesc_t)) | | 206 | #define WM_TXDESCSIZE(txq) (WM_NTXDESC(txq) * sizeof(wiseman_txdesc_t)) |
207 | #define WM_NEXTTX(txq, x) (((x) + 1) & WM_NTXDESC_MASK(txq)) | | 207 | #define WM_NEXTTX(txq, x) (((x) + 1) & WM_NTXDESC_MASK(txq)) |
208 | #define WM_NEXTTXS(txq, x) (((x) + 1) & WM_TXQUEUELEN_MASK(txq)) | | 208 | #define WM_NEXTTXS(txq, x) (((x) + 1) & WM_TXQUEUELEN_MASK(txq)) |
209 | | | 209 | |
210 | #define WM_MAXTXDMA (2 * round_page(IP_MAXPACKET)) /* for TSO */ | | 210 | #define WM_MAXTXDMA (2 * round_page(IP_MAXPACKET)) /* for TSO */ |
211 | | | 211 | |
212 | /* | | 212 | /* |
213 | * Receive descriptor list size. We have one Rx buffer for normal | | 213 | * Receive descriptor list size. We have one Rx buffer for normal |
214 | * sized packets. Jumbo packets consume 5 Rx buffers for a full-sized | | 214 | * sized packets. Jumbo packets consume 5 Rx buffers for a full-sized |
215 | * packet. We allocate 256 receive descriptors, each with a 2k | | 215 | * packet. We allocate 256 receive descriptors, each with a 2k |
216 | * buffer (MCLBYTES), which gives us room for 50 jumbo packets. | | 216 | * buffer (MCLBYTES), which gives us room for 50 jumbo packets. |
217 | */ | | 217 | */ |
218 | #define WM_NRXDESC 256 | | 218 | #define WM_NRXDESC 256 |
219 | #define WM_NRXDESC_MASK (WM_NRXDESC - 1) | | 219 | #define WM_NRXDESC_MASK (WM_NRXDESC - 1) |
220 | #define WM_NEXTRX(x) (((x) + 1) & WM_NRXDESC_MASK) | | 220 | #define WM_NEXTRX(x) (((x) + 1) & WM_NRXDESC_MASK) |
221 | #define WM_PREVRX(x) (((x) - 1) & WM_NRXDESC_MASK) | | 221 | #define WM_PREVRX(x) (((x) - 1) & WM_NRXDESC_MASK) |
222 | | | 222 | |
223 | typedef union txdescs { | | 223 | typedef union txdescs { |
224 | wiseman_txdesc_t sctxu_txdescs[WM_NTXDESC_82544]; | | 224 | wiseman_txdesc_t sctxu_txdescs[WM_NTXDESC_82544]; |
225 | nq_txdesc_t sctxu_nq_txdescs[WM_NTXDESC_82544]; | | 225 | nq_txdesc_t sctxu_nq_txdescs[WM_NTXDESC_82544]; |
226 | } txdescs_t; | | 226 | } txdescs_t; |
227 | | | 227 | |
228 | #define WM_CDTXOFF(x) (sizeof(wiseman_txdesc_t) * x) | | 228 | #define WM_CDTXOFF(x) (sizeof(wiseman_txdesc_t) * x) |
229 | #define WM_CDRXOFF(x) (sizeof(wiseman_rxdesc_t) * x) | | 229 | #define WM_CDRXOFF(x) (sizeof(wiseman_rxdesc_t) * x) |
230 | | | 230 | |
231 | /* | | 231 | /* |
232 | * Software state for transmit jobs. | | 232 | * Software state for transmit jobs. |
233 | */ | | 233 | */ |
234 | struct wm_txsoft { | | 234 | struct wm_txsoft { |
235 | struct mbuf *txs_mbuf; /* head of our mbuf chain */ | | 235 | struct mbuf *txs_mbuf; /* head of our mbuf chain */ |
236 | bus_dmamap_t txs_dmamap; /* our DMA map */ | | 236 | bus_dmamap_t txs_dmamap; /* our DMA map */ |
237 | int txs_firstdesc; /* first descriptor in packet */ | | 237 | int txs_firstdesc; /* first descriptor in packet */ |
238 | int txs_lastdesc; /* last descriptor in packet */ | | 238 | int txs_lastdesc; /* last descriptor in packet */ |
239 | int txs_ndesc; /* # of descriptors used */ | | 239 | int txs_ndesc; /* # of descriptors used */ |
240 | }; | | 240 | }; |
241 | | | 241 | |
242 | /* | | 242 | /* |
243 | * Software state for receive buffers. Each descriptor gets a | | 243 | * Software state for receive buffers. Each descriptor gets a |
244 | * 2k (MCLBYTES) buffer and a DMA map. For packets which fill | | 244 | * 2k (MCLBYTES) buffer and a DMA map. For packets which fill |
245 | * more than one buffer, we chain them together. | | 245 | * more than one buffer, we chain them together. |
246 | */ | | 246 | */ |
247 | struct wm_rxsoft { | | 247 | struct wm_rxsoft { |
248 | struct mbuf *rxs_mbuf; /* head of our mbuf chain */ | | 248 | struct mbuf *rxs_mbuf; /* head of our mbuf chain */ |
249 | bus_dmamap_t rxs_dmamap; /* our DMA map */ | | 249 | bus_dmamap_t rxs_dmamap; /* our DMA map */ |
250 | }; | | 250 | }; |
251 | | | 251 | |
252 | #define WM_LINKUP_TIMEOUT 50 | | 252 | #define WM_LINKUP_TIMEOUT 50 |
253 | | | 253 | |
254 | static uint16_t swfwphysem[] = { | | 254 | static uint16_t swfwphysem[] = { |
255 | SWFW_PHY0_SM, | | 255 | SWFW_PHY0_SM, |
256 | SWFW_PHY1_SM, | | 256 | SWFW_PHY1_SM, |
257 | SWFW_PHY2_SM, | | 257 | SWFW_PHY2_SM, |
258 | SWFW_PHY3_SM | | 258 | SWFW_PHY3_SM |
259 | }; | | 259 | }; |
260 | | | 260 | |
261 | static const uint32_t wm_82580_rxpbs_table[] = { | | 261 | static const uint32_t wm_82580_rxpbs_table[] = { |
262 | 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 | | 262 | 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 |
263 | }; | | 263 | }; |
264 | | | 264 | |
265 | struct wm_softc; | | 265 | struct wm_softc; |
266 | | | 266 | |
267 | struct wm_txqueue { | | 267 | struct wm_txqueue { |
268 | kmutex_t *txq_lock; /* lock for tx operations */ | | 268 | kmutex_t *txq_lock; /* lock for tx operations */ |
269 | | | 269 | |
270 | struct wm_softc *txq_sc; | | 270 | struct wm_softc *txq_sc; |
271 | | | 271 | |
272 | /* Software state for the transmit descriptors. */ | | 272 | /* Software state for the transmit descriptors. */ |
273 | int txq_num; /* must be a power of two */ | | 273 | int txq_num; /* must be a power of two */ |
274 | struct wm_txsoft txq_soft[WM_TXQUEUELEN_MAX]; | | 274 | struct wm_txsoft txq_soft[WM_TXQUEUELEN_MAX]; |
275 | | | 275 | |
276 | /* TX control data structures. */ | | 276 | /* TX control data structures. */ |
277 | int txq_ndesc; /* must be a power of two */ | | 277 | int txq_ndesc; /* must be a power of two */ |
278 | txdescs_t *txq_descs_u; | | 278 | txdescs_t *txq_descs_u; |
279 | bus_dmamap_t txq_desc_dmamap; /* control data DMA map */ | | 279 | bus_dmamap_t txq_desc_dmamap; /* control data DMA map */ |
280 | bus_dma_segment_t txq_desc_seg; /* control data segment */ | | 280 | bus_dma_segment_t txq_desc_seg; /* control data segment */ |
281 | int txq_desc_rseg; /* real number of control segment */ | | 281 | int txq_desc_rseg; /* real number of control segment */ |
282 | size_t txq_desc_size; /* control data size */ | | 282 | size_t txq_desc_size; /* control data size */ |
283 | #define txq_desc_dma txq_desc_dmamap->dm_segs[0].ds_addr | | 283 | #define txq_desc_dma txq_desc_dmamap->dm_segs[0].ds_addr |
284 | #define txq_descs txq_descs_u->sctxu_txdescs | | 284 | #define txq_descs txq_descs_u->sctxu_txdescs |
285 | #define txq_nq_descs txq_descs_u->sctxu_nq_txdescs | | 285 | #define txq_nq_descs txq_descs_u->sctxu_nq_txdescs |
286 | | | 286 | |
287 | bus_addr_t txq_tdt_reg; /* offset of TDT register */ | | 287 | bus_addr_t txq_tdt_reg; /* offset of TDT register */ |
288 | | | 288 | |
289 | int txq_free; /* number of free Tx descriptors */ | | 289 | int txq_free; /* number of free Tx descriptors */ |
290 | int txq_next; /* next ready Tx descriptor */ | | 290 | int txq_next; /* next ready Tx descriptor */ |
291 | | | 291 | |
292 | int txq_sfree; /* number of free Tx jobs */ | | 292 | int txq_sfree; /* number of free Tx jobs */ |
293 | int txq_snext; /* next free Tx job */ | | 293 | int txq_snext; /* next free Tx job */ |
294 | int txq_sdirty; /* dirty Tx jobs */ | | 294 | int txq_sdirty; /* dirty Tx jobs */ |
295 | | | 295 | |
296 | /* These 4 variables are used only on the 82547. */ | | 296 | /* These 4 variables are used only on the 82547. */ |
297 | int txq_fifo_size; /* Tx FIFO size */ | | 297 | int txq_fifo_size; /* Tx FIFO size */ |
298 | int txq_fifo_head; /* current head of FIFO */ | | 298 | int txq_fifo_head; /* current head of FIFO */ |
299 | uint32_t txq_fifo_addr; /* internal address of start of FIFO */ | | 299 | uint32_t txq_fifo_addr; /* internal address of start of FIFO */ |
300 | int txq_fifo_stall; /* Tx FIFO is stalled */ | | 300 | int txq_fifo_stall; /* Tx FIFO is stalled */ |
301 | | | 301 | |
302 | /* XXX which event counter is required? */ | | 302 | /* XXX which event counter is required? */ |
303 | }; | | 303 | }; |
304 | | | 304 | |
305 | struct wm_rxqueue { | | 305 | struct wm_rxqueue { |
306 | kmutex_t *rxq_lock; /* lock for rx operations */ | | 306 | kmutex_t *rxq_lock; /* lock for rx operations */ |
307 | | | 307 | |
308 | struct wm_softc *rxq_sc; | | 308 | struct wm_softc *rxq_sc; |
309 | | | 309 | |
310 | /* Software state for the receive descriptors. */ | | 310 | /* Software state for the receive descriptors. */ |
311 | wiseman_rxdesc_t *rxq_descs; | | 311 | wiseman_rxdesc_t *rxq_descs; |
312 | | | 312 | |
313 | /* RX control data structures. */ | | 313 | /* RX control data structures. */ |
314 | struct wm_rxsoft rxq_soft[WM_NRXDESC]; | | 314 | struct wm_rxsoft rxq_soft[WM_NRXDESC]; |
315 | bus_dmamap_t rxq_desc_dmamap; /* control data DMA map */ | | 315 | bus_dmamap_t rxq_desc_dmamap; /* control data DMA map */ |
316 | bus_dma_segment_t rxq_desc_seg; /* control data segment */ | | 316 | bus_dma_segment_t rxq_desc_seg; /* control data segment */ |
317 | int rxq_desc_rseg; /* real number of control segment */ | | 317 | int rxq_desc_rseg; /* real number of control segment */ |
318 | size_t rxq_desc_size; /* control data size */ | | 318 | size_t rxq_desc_size; /* control data size */ |
319 | #define rxq_desc_dma rxq_desc_dmamap->dm_segs[0].ds_addr | | 319 | #define rxq_desc_dma rxq_desc_dmamap->dm_segs[0].ds_addr |
320 | | | 320 | |
321 | bus_addr_t rxq_rdt_reg; /* offset of RDT register */ | | 321 | bus_addr_t rxq_rdt_reg; /* offset of RDT register */ |
322 | | | 322 | |
323 | int rxq_ptr; /* next ready Rx descriptor/queue ent */ | | 323 | int rxq_ptr; /* next ready Rx descriptor/queue ent */ |
324 | int rxq_discard; | | 324 | int rxq_discard; |
325 | int rxq_len; | | 325 | int rxq_len; |
326 | struct mbuf *rxq_head; | | 326 | struct mbuf *rxq_head; |
327 | struct mbuf *rxq_tail; | | 327 | struct mbuf *rxq_tail; |
328 | struct mbuf **rxq_tailp; | | 328 | struct mbuf **rxq_tailp; |
329 | | | 329 | |
330 | /* XXX which event counter is required? */ | | 330 | /* XXX which event counter is required? */ |
331 | }; | | 331 | }; |
332 | | | 332 | |
333 | /* | | 333 | /* |
334 | * Software state per device. | | 334 | * Software state per device. |
335 | */ | | 335 | */ |
336 | struct wm_softc { | | 336 | struct wm_softc { |
337 | device_t sc_dev; /* generic device information */ | | 337 | device_t sc_dev; /* generic device information */ |
338 | bus_space_tag_t sc_st; /* bus space tag */ | | 338 | bus_space_tag_t sc_st; /* bus space tag */ |
339 | bus_space_handle_t sc_sh; /* bus space handle */ | | 339 | bus_space_handle_t sc_sh; /* bus space handle */ |
340 | bus_size_t sc_ss; /* bus space size */ | | 340 | bus_size_t sc_ss; /* bus space size */ |
341 | bus_space_tag_t sc_iot; /* I/O space tag */ | | 341 | bus_space_tag_t sc_iot; /* I/O space tag */ |
342 | bus_space_handle_t sc_ioh; /* I/O space handle */ | | 342 | bus_space_handle_t sc_ioh; /* I/O space handle */ |
343 | bus_size_t sc_ios; /* I/O space size */ | | 343 | bus_size_t sc_ios; /* I/O space size */ |
344 | bus_space_tag_t sc_flasht; /* flash registers space tag */ | | 344 | bus_space_tag_t sc_flasht; /* flash registers space tag */ |
345 | bus_space_handle_t sc_flashh; /* flash registers space handle */ | | 345 | bus_space_handle_t sc_flashh; /* flash registers space handle */ |
346 | bus_size_t sc_flashs; /* flash registers space size */ | | 346 | bus_size_t sc_flashs; /* flash registers space size */ |
347 | bus_dma_tag_t sc_dmat; /* bus DMA tag */ | | 347 | bus_dma_tag_t sc_dmat; /* bus DMA tag */ |
348 | | | 348 | |
349 | struct ethercom sc_ethercom; /* ethernet common data */ | | 349 | struct ethercom sc_ethercom; /* ethernet common data */ |
350 | struct mii_data sc_mii; /* MII/media information */ | | 350 | struct mii_data sc_mii; /* MII/media information */ |
351 | | | 351 | |
352 | pci_chipset_tag_t sc_pc; | | 352 | pci_chipset_tag_t sc_pc; |
353 | pcitag_t sc_pcitag; | | 353 | pcitag_t sc_pcitag; |
354 | int sc_bus_speed; /* PCI/PCIX bus speed */ | | 354 | int sc_bus_speed; /* PCI/PCIX bus speed */ |
355 | int sc_pcixe_capoff; /* PCI[Xe] capability reg offset */ | | 355 | int sc_pcixe_capoff; /* PCI[Xe] capability reg offset */ |
356 | | | 356 | |
357 | uint16_t sc_pcidevid; /* PCI device ID */ | | 357 | uint16_t sc_pcidevid; /* PCI device ID */ |
358 | wm_chip_type sc_type; /* MAC type */ | | 358 | wm_chip_type sc_type; /* MAC type */ |
359 | int sc_rev; /* MAC revision */ | | 359 | int sc_rev; /* MAC revision */ |
360 | wm_phy_type sc_phytype; /* PHY type */ | | 360 | wm_phy_type sc_phytype; /* PHY type */ |
361 | uint32_t sc_mediatype; /* Media type (Copper, Fiber, SERDES)*/ | | 361 | uint32_t sc_mediatype; /* Media type (Copper, Fiber, SERDES)*/ |
362 | #define WM_MEDIATYPE_UNKNOWN 0x00 | | 362 | #define WM_MEDIATYPE_UNKNOWN 0x00 |
363 | #define WM_MEDIATYPE_FIBER 0x01 | | 363 | #define WM_MEDIATYPE_FIBER 0x01 |
364 | #define WM_MEDIATYPE_COPPER 0x02 | | 364 | #define WM_MEDIATYPE_COPPER 0x02 |
365 | #define WM_MEDIATYPE_SERDES 0x03 /* Internal SERDES */ | | 365 | #define WM_MEDIATYPE_SERDES 0x03 /* Internal SERDES */ |
366 | int sc_funcid; /* unit number of the chip (0 to 3) */ | | 366 | int sc_funcid; /* unit number of the chip (0 to 3) */ |
367 | int sc_flags; /* flags; see below */ | | 367 | int sc_flags; /* flags; see below */ |
368 | int sc_if_flags; /* last if_flags */ | | 368 | int sc_if_flags; /* last if_flags */ |
369 | int sc_flowflags; /* 802.3x flow control flags */ | | 369 | int sc_flowflags; /* 802.3x flow control flags */ |
370 | int sc_align_tweak; | | 370 | int sc_align_tweak; |
371 | | | 371 | |
372 | void *sc_ihs[WM_MAX_NINTR]; /* | | 372 | void *sc_ihs[WM_MAX_NINTR]; /* |
373 | * interrupt cookie. | | 373 | * interrupt cookie. |
374 | * legacy and msi use sc_ihs[0]. | | 374 | * legacy and msi use sc_ihs[0]. |
375 | */ | | 375 | */ |
376 | pci_intr_handle_t *sc_intrs; /* legacy and msi use sc_intrs[0] */ | | 376 | pci_intr_handle_t *sc_intrs; /* legacy and msi use sc_intrs[0] */ |
377 | int sc_nintrs; /* number of interrupts */ | | 377 | int sc_nintrs; /* number of interrupts */ |
378 | | | 378 | |
379 | callout_t sc_tick_ch; /* tick callout */ | | 379 | callout_t sc_tick_ch; /* tick callout */ |
380 | bool sc_stopping; | | 380 | bool sc_stopping; |
381 | | | 381 | |
382 | int sc_nvm_ver_major; | | 382 | int sc_nvm_ver_major; |
383 | int sc_nvm_ver_minor; | | 383 | int sc_nvm_ver_minor; |
384 | int sc_nvm_ver_build; | | 384 | int sc_nvm_ver_build; |
385 | int sc_nvm_addrbits; /* NVM address bits */ | | 385 | int sc_nvm_addrbits; /* NVM address bits */ |
386 | unsigned int sc_nvm_wordsize; /* NVM word size */ | | 386 | unsigned int sc_nvm_wordsize; /* NVM word size */ |
387 | int sc_ich8_flash_base; | | 387 | int sc_ich8_flash_base; |
388 | int sc_ich8_flash_bank_size; | | 388 | int sc_ich8_flash_bank_size; |
389 | int sc_nvm_k1_enabled; | | 389 | int sc_nvm_k1_enabled; |
390 | | | 390 | |
391 | int sc_ntxqueues; | | 391 | int sc_ntxqueues; |
392 | struct wm_txqueue *sc_txq; | | 392 | struct wm_txqueue *sc_txq; |
393 | | | 393 | |
394 | int sc_nrxqueues; | | 394 | int sc_nrxqueues; |
395 | struct wm_rxqueue *sc_rxq; | | 395 | struct wm_rxqueue *sc_rxq; |
396 | | | 396 | |
397 | #ifdef WM_EVENT_COUNTERS | | 397 | #ifdef WM_EVENT_COUNTERS |
398 | /* Event counters. */ | | 398 | /* Event counters. */ |
399 | struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ | | 399 | struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ |
400 | struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ | | 400 | struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ |
401 | struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */ | | 401 | struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */ |
402 | struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ | | 402 | struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ |
403 | struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ | | 403 | struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ |
404 | struct evcnt sc_ev_rxintr; /* Rx interrupts */ | | 404 | struct evcnt sc_ev_rxintr; /* Rx interrupts */ |
405 | struct evcnt sc_ev_linkintr; /* Link interrupts */ | | 405 | struct evcnt sc_ev_linkintr; /* Link interrupts */ |
406 | | | 406 | |
407 | struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ | | 407 | struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ |
408 | struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ | | 408 | struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ |
409 | struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ | | 409 | struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ |
410 | struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ | | 410 | struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ |
411 | struct evcnt sc_ev_txtusum6; /* TCP/UDP v6 cksums comp. out-bound */ | | 411 | struct evcnt sc_ev_txtusum6; /* TCP/UDP v6 cksums comp. out-bound */ |
412 | struct evcnt sc_ev_txtso; /* TCP seg offload out-bound (IPv4) */ | | 412 | struct evcnt sc_ev_txtso; /* TCP seg offload out-bound (IPv4) */ |
413 | struct evcnt sc_ev_txtso6; /* TCP seg offload out-bound (IPv6) */ | | 413 | struct evcnt sc_ev_txtso6; /* TCP seg offload out-bound (IPv6) */ |
414 | struct evcnt sc_ev_txtsopain; /* painful header manip. for TSO */ | | 414 | struct evcnt sc_ev_txtsopain; /* painful header manip. for TSO */ |
415 | | | 415 | |
416 | struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */ | | 416 | struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */ |
417 | struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ | | 417 | struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ |
418 | | | 418 | |
419 | struct evcnt sc_ev_tu; /* Tx underrun */ | | 419 | struct evcnt sc_ev_tu; /* Tx underrun */ |
420 | | | 420 | |
421 | struct evcnt sc_ev_tx_xoff; /* Tx PAUSE(!0) frames */ | | 421 | struct evcnt sc_ev_tx_xoff; /* Tx PAUSE(!0) frames */ |
422 | struct evcnt sc_ev_tx_xon; /* Tx PAUSE(0) frames */ | | 422 | struct evcnt sc_ev_tx_xon; /* Tx PAUSE(0) frames */ |
423 | struct evcnt sc_ev_rx_xoff; /* Rx PAUSE(!0) frames */ | | 423 | struct evcnt sc_ev_rx_xoff; /* Rx PAUSE(!0) frames */ |
424 | struct evcnt sc_ev_rx_xon; /* Rx PAUSE(0) frames */ | | 424 | struct evcnt sc_ev_rx_xon; /* Rx PAUSE(0) frames */ |
425 | struct evcnt sc_ev_rx_macctl; /* Rx Unsupported */ | | 425 | struct evcnt sc_ev_rx_macctl; /* Rx Unsupported */ |
426 | #endif /* WM_EVENT_COUNTERS */ | | 426 | #endif /* WM_EVENT_COUNTERS */ |
427 | | | 427 | |
428 | /* This variable are used only on the 82547. */ | | 428 | /* This variable are used only on the 82547. */ |
429 | callout_t sc_txfifo_ch; /* Tx FIFO stall work-around timer */ | | 429 | callout_t sc_txfifo_ch; /* Tx FIFO stall work-around timer */ |
430 | | | 430 | |
431 | uint32_t sc_ctrl; /* prototype CTRL register */ | | 431 | uint32_t sc_ctrl; /* prototype CTRL register */ |
432 | #if 0 | | 432 | #if 0 |
433 | uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */ | | 433 | uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */ |
434 | #endif | | 434 | #endif |
435 | uint32_t sc_icr; /* prototype interrupt bits */ | | 435 | uint32_t sc_icr; /* prototype interrupt bits */ |
436 | uint32_t sc_itr; /* prototype intr throttling reg */ | | 436 | uint32_t sc_itr; /* prototype intr throttling reg */ |
437 | uint32_t sc_tctl; /* prototype TCTL register */ | | 437 | uint32_t sc_tctl; /* prototype TCTL register */ |
438 | uint32_t sc_rctl; /* prototype RCTL register */ | | 438 | uint32_t sc_rctl; /* prototype RCTL register */ |
439 | uint32_t sc_txcw; /* prototype TXCW register */ | | 439 | uint32_t sc_txcw; /* prototype TXCW register */ |
440 | uint32_t sc_tipg; /* prototype TIPG register */ | | 440 | uint32_t sc_tipg; /* prototype TIPG register */ |
441 | uint32_t sc_fcrtl; /* prototype FCRTL register */ | | 441 | uint32_t sc_fcrtl; /* prototype FCRTL register */ |
442 | uint32_t sc_pba; /* prototype PBA register */ | | 442 | uint32_t sc_pba; /* prototype PBA register */ |
443 | | | 443 | |
444 | int sc_tbi_linkup; /* TBI link status */ | | 444 | int sc_tbi_linkup; /* TBI link status */ |
445 | int sc_tbi_serdes_anegticks; /* autonegotiation ticks */ | | 445 | int sc_tbi_serdes_anegticks; /* autonegotiation ticks */ |
446 | int sc_tbi_serdes_ticks; /* tbi ticks */ | | 446 | int sc_tbi_serdes_ticks; /* tbi ticks */ |
447 | | | 447 | |
448 | int sc_mchash_type; /* multicast filter offset */ | | 448 | int sc_mchash_type; /* multicast filter offset */ |
449 | | | 449 | |
450 | krndsource_t rnd_source; /* random source */ | | 450 | krndsource_t rnd_source; /* random source */ |
451 | | | 451 | |
452 | kmutex_t *sc_core_lock; /* lock for softc operations */ | | 452 | kmutex_t *sc_core_lock; /* lock for softc operations */ |
453 | }; | | 453 | }; |
454 | | | 454 | |
455 | #define WM_TX_LOCK(_txq) if ((_txq)->txq_lock) mutex_enter((_txq)->txq_lock) | | 455 | #define WM_TX_LOCK(_txq) if ((_txq)->txq_lock) mutex_enter((_txq)->txq_lock) |
456 | #define WM_TX_UNLOCK(_txq) if ((_txq)->txq_lock) mutex_exit((_txq)->txq_lock) | | 456 | #define WM_TX_UNLOCK(_txq) if ((_txq)->txq_lock) mutex_exit((_txq)->txq_lock) |
457 | #define WM_TX_LOCKED(_txq) (!(_txq)->txq_lock || mutex_owned((_txq)->txq_lock)) | | 457 | #define WM_TX_LOCKED(_txq) (!(_txq)->txq_lock || mutex_owned((_txq)->txq_lock)) |
458 | #define WM_RX_LOCK(_rxq) if ((_rxq)->rxq_lock) mutex_enter((_rxq)->rxq_lock) | | 458 | #define WM_RX_LOCK(_rxq) if ((_rxq)->rxq_lock) mutex_enter((_rxq)->rxq_lock) |
459 | #define WM_RX_UNLOCK(_rxq) if ((_rxq)->rxq_lock) mutex_exit((_rxq)->rxq_lock) | | 459 | #define WM_RX_UNLOCK(_rxq) if ((_rxq)->rxq_lock) mutex_exit((_rxq)->rxq_lock) |
460 | #define WM_RX_LOCKED(_rxq) (!(_rxq)->rxq_lock || mutex_owned((_rxq)->rxq_lock)) | | 460 | #define WM_RX_LOCKED(_rxq) (!(_rxq)->rxq_lock || mutex_owned((_rxq)->rxq_lock)) |
461 | #define WM_CORE_LOCK(_sc) if ((_sc)->sc_core_lock) mutex_enter((_sc)->sc_core_lock) | | 461 | #define WM_CORE_LOCK(_sc) if ((_sc)->sc_core_lock) mutex_enter((_sc)->sc_core_lock) |
462 | #define WM_CORE_UNLOCK(_sc) if ((_sc)->sc_core_lock) mutex_exit((_sc)->sc_core_lock) | | 462 | #define WM_CORE_UNLOCK(_sc) if ((_sc)->sc_core_lock) mutex_exit((_sc)->sc_core_lock) |
463 | #define WM_CORE_LOCKED(_sc) (!(_sc)->sc_core_lock || mutex_owned((_sc)->sc_core_lock)) | | 463 | #define WM_CORE_LOCKED(_sc) (!(_sc)->sc_core_lock || mutex_owned((_sc)->sc_core_lock)) |
464 | | | 464 | |
465 | #ifdef WM_MPSAFE | | 465 | #ifdef WM_MPSAFE |
466 | #define CALLOUT_FLAGS CALLOUT_MPSAFE | | 466 | #define CALLOUT_FLAGS CALLOUT_MPSAFE |
467 | #else | | 467 | #else |
468 | #define CALLOUT_FLAGS 0 | | 468 | #define CALLOUT_FLAGS 0 |
469 | #endif | | 469 | #endif |
470 | | | 470 | |
471 | #define WM_RXCHAIN_RESET(rxq) \ | | 471 | #define WM_RXCHAIN_RESET(rxq) \ |
472 | do { \ | | 472 | do { \ |
473 | (rxq)->rxq_tailp = &(rxq)->rxq_head; \ | | 473 | (rxq)->rxq_tailp = &(rxq)->rxq_head; \ |
474 | *(rxq)->rxq_tailp = NULL; \ | | 474 | *(rxq)->rxq_tailp = NULL; \ |
475 | (rxq)->rxq_len = 0; \ | | 475 | (rxq)->rxq_len = 0; \ |
476 | } while (/*CONSTCOND*/0) | | 476 | } while (/*CONSTCOND*/0) |
477 | | | 477 | |
478 | #define WM_RXCHAIN_LINK(rxq, m) \ | | 478 | #define WM_RXCHAIN_LINK(rxq, m) \ |
479 | do { \ | | 479 | do { \ |
480 | *(rxq)->rxq_tailp = (rxq)->rxq_tail = (m); \ | | 480 | *(rxq)->rxq_tailp = (rxq)->rxq_tail = (m); \ |
481 | (rxq)->rxq_tailp = &(m)->m_next; \ | | 481 | (rxq)->rxq_tailp = &(m)->m_next; \ |
482 | } while (/*CONSTCOND*/0) | | 482 | } while (/*CONSTCOND*/0) |
483 | | | 483 | |
484 | #ifdef WM_EVENT_COUNTERS | | 484 | #ifdef WM_EVENT_COUNTERS |
485 | #define WM_EVCNT_INCR(ev) (ev)->ev_count++ | | 485 | #define WM_EVCNT_INCR(ev) (ev)->ev_count++ |
486 | #define WM_EVCNT_ADD(ev, val) (ev)->ev_count += (val) | | 486 | #define WM_EVCNT_ADD(ev, val) (ev)->ev_count += (val) |
487 | #else | | 487 | #else |
488 | #define WM_EVCNT_INCR(ev) /* nothing */ | | 488 | #define WM_EVCNT_INCR(ev) /* nothing */ |
489 | #define WM_EVCNT_ADD(ev, val) /* nothing */ | | 489 | #define WM_EVCNT_ADD(ev, val) /* nothing */ |
490 | #endif | | 490 | #endif |
491 | | | 491 | |
492 | #define CSR_READ(sc, reg) \ | | 492 | #define CSR_READ(sc, reg) \ |
493 | bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) | | 493 | bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) |
494 | #define CSR_WRITE(sc, reg, val) \ | | 494 | #define CSR_WRITE(sc, reg, val) \ |
495 | bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) | | 495 | bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) |
496 | #define CSR_WRITE_FLUSH(sc) \ | | 496 | #define CSR_WRITE_FLUSH(sc) \ |
497 | (void) CSR_READ((sc), WMREG_STATUS) | | 497 | (void) CSR_READ((sc), WMREG_STATUS) |
498 | | | 498 | |
499 | #define ICH8_FLASH_READ32(sc, reg) \ | | 499 | #define ICH8_FLASH_READ32(sc, reg) \ |
500 | bus_space_read_4((sc)->sc_flasht, (sc)->sc_flashh, (reg)) | | 500 | bus_space_read_4((sc)->sc_flasht, (sc)->sc_flashh, (reg)) |
501 | #define ICH8_FLASH_WRITE32(sc, reg, data) \ | | 501 | #define ICH8_FLASH_WRITE32(sc, reg, data) \ |
502 | bus_space_write_4((sc)->sc_flasht, (sc)->sc_flashh, (reg), (data)) | | 502 | bus_space_write_4((sc)->sc_flasht, (sc)->sc_flashh, (reg), (data)) |
503 | | | 503 | |
504 | #define ICH8_FLASH_READ16(sc, reg) \ | | 504 | #define ICH8_FLASH_READ16(sc, reg) \ |
505 | bus_space_read_2((sc)->sc_flasht, (sc)->sc_flashh, (reg)) | | 505 | bus_space_read_2((sc)->sc_flasht, (sc)->sc_flashh, (reg)) |
506 | #define ICH8_FLASH_WRITE16(sc, reg, data) \ | | 506 | #define ICH8_FLASH_WRITE16(sc, reg, data) \ |
507 | bus_space_write_2((sc)->sc_flasht, (sc)->sc_flashh, (reg), (data)) | | 507 | bus_space_write_2((sc)->sc_flasht, (sc)->sc_flashh, (reg), (data)) |
508 | | | 508 | |
509 | #define WM_CDTXADDR(txq, x) ((txq)->txq_desc_dma + WM_CDTXOFF((x))) | | 509 | #define WM_CDTXADDR(txq, x) ((txq)->txq_desc_dma + WM_CDTXOFF((x))) |
510 | #define WM_CDRXADDR(rxq, x) ((rxq)->rxq_desc_dma + WM_CDRXOFF((x))) | | 510 | #define WM_CDRXADDR(rxq, x) ((rxq)->rxq_desc_dma + WM_CDRXOFF((x))) |
511 | | | 511 | |
512 | #define WM_CDTXADDR_LO(txq, x) (WM_CDTXADDR((txq), (x)) & 0xffffffffU) | | 512 | #define WM_CDTXADDR_LO(txq, x) (WM_CDTXADDR((txq), (x)) & 0xffffffffU) |
513 | #define WM_CDTXADDR_HI(txq, x) \ | | 513 | #define WM_CDTXADDR_HI(txq, x) \ |
514 | (sizeof(bus_addr_t) == 8 ? \ | | 514 | (sizeof(bus_addr_t) == 8 ? \ |
515 | (uint64_t)WM_CDTXADDR((txq), (x)) >> 32 : 0) | | 515 | (uint64_t)WM_CDTXADDR((txq), (x)) >> 32 : 0) |
516 | | | 516 | |
517 | #define WM_CDRXADDR_LO(rxq, x) (WM_CDRXADDR((rxq), (x)) & 0xffffffffU) | | 517 | #define WM_CDRXADDR_LO(rxq, x) (WM_CDRXADDR((rxq), (x)) & 0xffffffffU) |
518 | #define WM_CDRXADDR_HI(rxq, x) \ | | 518 | #define WM_CDRXADDR_HI(rxq, x) \ |
519 | (sizeof(bus_addr_t) == 8 ? \ | | 519 | (sizeof(bus_addr_t) == 8 ? \ |
520 | (uint64_t)WM_CDRXADDR((rxq), (x)) >> 32 : 0) | | 520 | (uint64_t)WM_CDRXADDR((rxq), (x)) >> 32 : 0) |
521 | | | 521 | |
522 | /* | | 522 | /* |
523 | * Register read/write functions. | | 523 | * Register read/write functions. |
524 | * Other than CSR_{READ|WRITE}(). | | 524 | * Other than CSR_{READ|WRITE}(). |
525 | */ | | 525 | */ |
526 | #if 0 | | 526 | #if 0 |
527 | static inline uint32_t wm_io_read(struct wm_softc *, int); | | 527 | static inline uint32_t wm_io_read(struct wm_softc *, int); |
528 | #endif | | 528 | #endif |
529 | static inline void wm_io_write(struct wm_softc *, int, uint32_t); | | 529 | static inline void wm_io_write(struct wm_softc *, int, uint32_t); |
530 | static inline void wm_82575_write_8bit_ctlr_reg(struct wm_softc *, uint32_t, | | 530 | static inline void wm_82575_write_8bit_ctlr_reg(struct wm_softc *, uint32_t, |
531 | uint32_t, uint32_t); | | 531 | uint32_t, uint32_t); |
532 | static inline void wm_set_dma_addr(volatile wiseman_addr_t *, bus_addr_t); | | 532 | static inline void wm_set_dma_addr(volatile wiseman_addr_t *, bus_addr_t); |
533 | | | 533 | |
534 | /* | | 534 | /* |
535 | * Descriptor sync/init functions. | | 535 | * Descriptor sync/init functions. |
536 | */ | | 536 | */ |
537 | static inline void wm_cdtxsync(struct wm_softc *, int, int, int); | | 537 | static inline void wm_cdtxsync(struct wm_softc *, int, int, int); |
538 | static inline void wm_cdrxsync(struct wm_softc *, int, int); | | 538 | static inline void wm_cdrxsync(struct wm_softc *, int, int); |
539 | static inline void wm_init_rxdesc(struct wm_softc *, int); | | 539 | static inline void wm_init_rxdesc(struct wm_softc *, int); |
540 | | | 540 | |
541 | /* | | 541 | /* |
542 | * Device driver interface functions and commonly used functions. | | 542 | * Device driver interface functions and commonly used functions. |
543 | * match, attach, detach, init, start, stop, ioctl, watchdog and so on. | | 543 | * match, attach, detach, init, start, stop, ioctl, watchdog and so on. |
544 | */ | | 544 | */ |
545 | static const struct wm_product *wm_lookup(const struct pci_attach_args *); | | 545 | static const struct wm_product *wm_lookup(const struct pci_attach_args *); |
546 | static int wm_match(device_t, cfdata_t, void *); | | 546 | static int wm_match(device_t, cfdata_t, void *); |
547 | static void wm_attach(device_t, device_t, void *); | | 547 | static void wm_attach(device_t, device_t, void *); |
548 | static int wm_detach(device_t, int); | | 548 | static int wm_detach(device_t, int); |
549 | static bool wm_suspend(device_t, const pmf_qual_t *); | | 549 | static bool wm_suspend(device_t, const pmf_qual_t *); |
550 | static bool wm_resume(device_t, const pmf_qual_t *); | | 550 | static bool wm_resume(device_t, const pmf_qual_t *); |
551 | static void wm_watchdog(struct ifnet *); | | 551 | static void wm_watchdog(struct ifnet *); |
552 | static void wm_tick(void *); | | 552 | static void wm_tick(void *); |
553 | static int wm_ifflags_cb(struct ethercom *); | | 553 | static int wm_ifflags_cb(struct ethercom *); |
554 | static int wm_ioctl(struct ifnet *, u_long, void *); | | 554 | static int wm_ioctl(struct ifnet *, u_long, void *); |
555 | /* MAC address related */ | | 555 | /* MAC address related */ |
556 | static uint16_t wm_check_alt_mac_addr(struct wm_softc *); | | 556 | static uint16_t wm_check_alt_mac_addr(struct wm_softc *); |
557 | static int wm_read_mac_addr(struct wm_softc *, uint8_t *); | | 557 | static int wm_read_mac_addr(struct wm_softc *, uint8_t *); |
558 | static void wm_set_ral(struct wm_softc *, const uint8_t *, int); | | 558 | static void wm_set_ral(struct wm_softc *, const uint8_t *, int); |
559 | static uint32_t wm_mchash(struct wm_softc *, const uint8_t *); | | 559 | static uint32_t wm_mchash(struct wm_softc *, const uint8_t *); |
560 | static void wm_set_filter(struct wm_softc *); | | 560 | static void wm_set_filter(struct wm_softc *); |
561 | /* Reset and init related */ | | 561 | /* Reset and init related */ |
562 | static void wm_set_vlan(struct wm_softc *); | | 562 | static void wm_set_vlan(struct wm_softc *); |
563 | static void wm_set_pcie_completion_timeout(struct wm_softc *); | | 563 | static void wm_set_pcie_completion_timeout(struct wm_softc *); |
564 | static void wm_get_auto_rd_done(struct wm_softc *); | | 564 | static void wm_get_auto_rd_done(struct wm_softc *); |
565 | static void wm_lan_init_done(struct wm_softc *); | | 565 | static void wm_lan_init_done(struct wm_softc *); |
566 | static void wm_get_cfg_done(struct wm_softc *); | | 566 | static void wm_get_cfg_done(struct wm_softc *); |
567 | static void wm_initialize_hardware_bits(struct wm_softc *); | | 567 | static void wm_initialize_hardware_bits(struct wm_softc *); |
568 | static uint32_t wm_rxpbs_adjust_82580(uint32_t); | | 568 | static uint32_t wm_rxpbs_adjust_82580(uint32_t); |
569 | static void wm_reset(struct wm_softc *); | | 569 | static void wm_reset(struct wm_softc *); |
570 | static int wm_add_rxbuf(struct wm_softc *, int); | | 570 | static int wm_add_rxbuf(struct wm_softc *, int); |
571 | static void wm_rxdrain(struct wm_softc *); | | 571 | static void wm_rxdrain(struct wm_softc *); |
572 | static int wm_init(struct ifnet *); | | 572 | static int wm_init(struct ifnet *); |
573 | static int wm_init_locked(struct ifnet *); | | 573 | static int wm_init_locked(struct ifnet *); |
574 | static void wm_stop(struct ifnet *, int); | | 574 | static void wm_stop(struct ifnet *, int); |
575 | static void wm_stop_locked(struct ifnet *, int); | | 575 | static void wm_stop_locked(struct ifnet *, int); |
576 | static int wm_tx_offload(struct wm_softc *, struct wm_txsoft *, | | 576 | static int wm_tx_offload(struct wm_softc *, struct wm_txsoft *, |
577 | uint32_t *, uint8_t *); | | 577 | uint32_t *, uint8_t *); |
578 | static void wm_dump_mbuf_chain(struct wm_softc *, struct mbuf *); | | 578 | static void wm_dump_mbuf_chain(struct wm_softc *, struct mbuf *); |
579 | static void wm_82547_txfifo_stall(void *); | | 579 | static void wm_82547_txfifo_stall(void *); |
580 | static int wm_82547_txfifo_bugchk(struct wm_softc *, struct mbuf *); | | 580 | static int wm_82547_txfifo_bugchk(struct wm_softc *, struct mbuf *); |
581 | /* DMA related */ | | 581 | /* DMA related */ |
582 | static int wm_alloc_tx_descs(struct wm_softc *); | | 582 | static int wm_alloc_tx_descs(struct wm_softc *); |
583 | static void wm_free_tx_descs(struct wm_softc *); | | 583 | static void wm_free_tx_descs(struct wm_softc *); |
584 | static void wm_init_tx_descs(struct wm_softc *); | | 584 | static void wm_init_tx_descs(struct wm_softc *); |
585 | static void wm_init_tx_regs(struct wm_softc *); | | 585 | static void wm_init_tx_regs(struct wm_softc *); |
586 | static int wm_alloc_rx_descs(struct wm_softc *); | | 586 | static int wm_alloc_rx_descs(struct wm_softc *); |
587 | static void wm_free_rx_descs(struct wm_softc *); | | 587 | static void wm_free_rx_descs(struct wm_softc *); |
588 | static void wm_init_rx_regs(struct wm_softc *); | | 588 | static void wm_init_rx_regs(struct wm_softc *); |
589 | static int wm_alloc_tx_buffer(struct wm_softc *); | | 589 | static int wm_alloc_tx_buffer(struct wm_softc *); |
590 | static void wm_free_tx_buffer(struct wm_softc *); | | 590 | static void wm_free_tx_buffer(struct wm_softc *); |
591 | static void wm_init_tx_buffer(struct wm_softc *); | | 591 | static void wm_init_tx_buffer(struct wm_softc *); |
592 | static int wm_alloc_rx_buffer(struct wm_softc *); | | 592 | static int wm_alloc_rx_buffer(struct wm_softc *); |
593 | static void wm_free_rx_buffer(struct wm_softc *); | | 593 | static void wm_free_rx_buffer(struct wm_softc *); |
594 | static int wm_init_rx_buffer(struct wm_softc *); | | 594 | static int wm_init_rx_buffer(struct wm_softc *); |
595 | static void wm_init_tx_queue(struct wm_softc *); | | 595 | static void wm_init_tx_queue(struct wm_softc *); |
596 | static int wm_init_rx_queue(struct wm_softc *); | | 596 | static int wm_init_rx_queue(struct wm_softc *); |
597 | static int wm_alloc_txrx_queues(struct wm_softc *); | | 597 | static int wm_alloc_txrx_queues(struct wm_softc *); |
598 | static void wm_free_txrx_queues(struct wm_softc *); | | 598 | static void wm_free_txrx_queues(struct wm_softc *); |
599 | static int wm_init_txrx_queues(struct wm_softc *); | | 599 | static int wm_init_txrx_queues(struct wm_softc *); |
600 | /* Start */ | | 600 | /* Start */ |
601 | static void wm_start(struct ifnet *); | | 601 | static void wm_start(struct ifnet *); |
602 | static void wm_start_locked(struct ifnet *); | | 602 | static void wm_start_locked(struct ifnet *); |
603 | static int wm_nq_tx_offload(struct wm_softc *, struct wm_txsoft *, | | 603 | static int wm_nq_tx_offload(struct wm_softc *, struct wm_txsoft *, |
604 | uint32_t *, uint32_t *, bool *); | | 604 | uint32_t *, uint32_t *, bool *); |
605 | static void wm_nq_start(struct ifnet *); | | 605 | static void wm_nq_start(struct ifnet *); |
606 | static void wm_nq_start_locked(struct ifnet *); | | 606 | static void wm_nq_start_locked(struct ifnet *); |
607 | /* Interrupt */ | | 607 | /* Interrupt */ |
608 | static int wm_txeof(struct wm_softc *); | | 608 | static int wm_txeof(struct wm_softc *); |
609 | static void wm_rxeof(struct wm_softc *); | | 609 | static void wm_rxeof(struct wm_softc *); |
610 | static void wm_linkintr_gmii(struct wm_softc *, uint32_t); | | 610 | static void wm_linkintr_gmii(struct wm_softc *, uint32_t); |
611 | static void wm_linkintr_tbi(struct wm_softc *, uint32_t); | | 611 | static void wm_linkintr_tbi(struct wm_softc *, uint32_t); |
612 | static void wm_linkintr_serdes(struct wm_softc *, uint32_t); | | 612 | static void wm_linkintr_serdes(struct wm_softc *, uint32_t); |
613 | static void wm_linkintr(struct wm_softc *, uint32_t); | | 613 | static void wm_linkintr(struct wm_softc *, uint32_t); |
614 | static int wm_intr_legacy(void *); | | 614 | static int wm_intr_legacy(void *); |
615 | #ifdef WM_MSI_MSIX | | 615 | #ifdef WM_MSI_MSIX |
616 | static int wm_txintr_msix(void *); | | 616 | static int wm_txintr_msix(void *); |
617 | static int wm_rxintr_msix(void *); | | 617 | static int wm_rxintr_msix(void *); |
618 | static int wm_linkintr_msix(void *); | | 618 | static int wm_linkintr_msix(void *); |
619 | #endif | | 619 | #endif |
620 | | | 620 | |
621 | /* | | 621 | /* |
622 | * Media related. | | 622 | * Media related. |
623 | * GMII, SGMII, TBI, SERDES and SFP. | | 623 | * GMII, SGMII, TBI, SERDES and SFP. |
624 | */ | | 624 | */ |
625 | /* Common */ | | 625 | /* Common */ |
626 | static void wm_tbi_serdes_set_linkled(struct wm_softc *); | | 626 | static void wm_tbi_serdes_set_linkled(struct wm_softc *); |
627 | /* GMII related */ | | 627 | /* GMII related */ |
628 | static void wm_gmii_reset(struct wm_softc *); | | 628 | static void wm_gmii_reset(struct wm_softc *); |
629 | static int wm_get_phy_id_82575(struct wm_softc *); | | 629 | static int wm_get_phy_id_82575(struct wm_softc *); |
630 | static void wm_gmii_mediainit(struct wm_softc *, pci_product_id_t); | | 630 | static void wm_gmii_mediainit(struct wm_softc *, pci_product_id_t); |
631 | static int wm_gmii_mediachange(struct ifnet *); | | 631 | static int wm_gmii_mediachange(struct ifnet *); |
632 | static void wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *); | | 632 | static void wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *); |
633 | static void wm_i82543_mii_sendbits(struct wm_softc *, uint32_t, int); | | 633 | static void wm_i82543_mii_sendbits(struct wm_softc *, uint32_t, int); |
634 | static uint32_t wm_i82543_mii_recvbits(struct wm_softc *); | | 634 | static uint32_t wm_i82543_mii_recvbits(struct wm_softc *); |
635 | static int wm_gmii_i82543_readreg(device_t, int, int); | | 635 | static int wm_gmii_i82543_readreg(device_t, int, int); |
636 | static void wm_gmii_i82543_writereg(device_t, int, int, int); | | 636 | static void wm_gmii_i82543_writereg(device_t, int, int, int); |
637 | static int wm_gmii_i82544_readreg(device_t, int, int); | | 637 | static int wm_gmii_i82544_readreg(device_t, int, int); |
638 | static void wm_gmii_i82544_writereg(device_t, int, int, int); | | 638 | static void wm_gmii_i82544_writereg(device_t, int, int, int); |
639 | static int wm_gmii_i80003_readreg(device_t, int, int); | | 639 | static int wm_gmii_i80003_readreg(device_t, int, int); |
640 | static void wm_gmii_i80003_writereg(device_t, int, int, int); | | 640 | static void wm_gmii_i80003_writereg(device_t, int, int, int); |
641 | static int wm_gmii_bm_readreg(device_t, int, int); | | 641 | static int wm_gmii_bm_readreg(device_t, int, int); |
642 | static void wm_gmii_bm_writereg(device_t, int, int, int); | | 642 | static void wm_gmii_bm_writereg(device_t, int, int, int); |
643 | static void wm_access_phy_wakeup_reg_bm(device_t, int, int16_t *, int); | | 643 | static void wm_access_phy_wakeup_reg_bm(device_t, int, int16_t *, int); |
644 | static int wm_gmii_hv_readreg(device_t, int, int); | | 644 | static int wm_gmii_hv_readreg(device_t, int, int); |
645 | static void wm_gmii_hv_writereg(device_t, int, int, int); | | 645 | static void wm_gmii_hv_writereg(device_t, int, int, int); |
646 | static int wm_gmii_82580_readreg(device_t, int, int); | | 646 | static int wm_gmii_82580_readreg(device_t, int, int); |
647 | static void wm_gmii_82580_writereg(device_t, int, int, int); | | 647 | static void wm_gmii_82580_writereg(device_t, int, int, int); |
648 | static int wm_gmii_gs40g_readreg(device_t, int, int); | | 648 | static int wm_gmii_gs40g_readreg(device_t, int, int); |
649 | static void wm_gmii_gs40g_writereg(device_t, int, int, int); | | 649 | static void wm_gmii_gs40g_writereg(device_t, int, int, int); |
650 | static void wm_gmii_statchg(struct ifnet *); | | 650 | static void wm_gmii_statchg(struct ifnet *); |
651 | static int wm_kmrn_readreg(struct wm_softc *, int); | | 651 | static int wm_kmrn_readreg(struct wm_softc *, int); |
652 | static void wm_kmrn_writereg(struct wm_softc *, int, int); | | 652 | static void wm_kmrn_writereg(struct wm_softc *, int, int); |
653 | /* SGMII */ | | 653 | /* SGMII */ |
654 | static bool wm_sgmii_uses_mdio(struct wm_softc *); | | 654 | static bool wm_sgmii_uses_mdio(struct wm_softc *); |
655 | static int wm_sgmii_readreg(device_t, int, int); | | 655 | static int wm_sgmii_readreg(device_t, int, int); |
656 | static void wm_sgmii_writereg(device_t, int, int, int); | | 656 | static void wm_sgmii_writereg(device_t, int, int, int); |
657 | /* TBI related */ | | 657 | /* TBI related */ |
658 | static void wm_tbi_mediainit(struct wm_softc *); | | 658 | static void wm_tbi_mediainit(struct wm_softc *); |
659 | static int wm_tbi_mediachange(struct ifnet *); | | 659 | static int wm_tbi_mediachange(struct ifnet *); |
660 | static void wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *); | | 660 | static void wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *); |
661 | static int wm_check_for_link(struct wm_softc *); | | 661 | static int wm_check_for_link(struct wm_softc *); |
662 | static void wm_tbi_tick(struct wm_softc *); | | 662 | static void wm_tbi_tick(struct wm_softc *); |
663 | /* SERDES related */ | | 663 | /* SERDES related */ |
664 | static void wm_serdes_power_up_link_82575(struct wm_softc *); | | 664 | static void wm_serdes_power_up_link_82575(struct wm_softc *); |
665 | static int wm_serdes_mediachange(struct ifnet *); | | 665 | static int wm_serdes_mediachange(struct ifnet *); |
666 | static void wm_serdes_mediastatus(struct ifnet *, struct ifmediareq *); | | 666 | static void wm_serdes_mediastatus(struct ifnet *, struct ifmediareq *); |
667 | static void wm_serdes_tick(struct wm_softc *); | | 667 | static void wm_serdes_tick(struct wm_softc *); |
668 | /* SFP related */ | | 668 | /* SFP related */ |
669 | static int wm_sfp_read_data_byte(struct wm_softc *, uint16_t, uint8_t *); | | 669 | static int wm_sfp_read_data_byte(struct wm_softc *, uint16_t, uint8_t *); |
670 | static uint32_t wm_sfp_get_media_type(struct wm_softc *); | | 670 | static uint32_t wm_sfp_get_media_type(struct wm_softc *); |
671 | | | 671 | |
672 | /* | | 672 | /* |
673 | * NVM related. | | 673 | * NVM related. |
674 | * Microwire, SPI (w/wo EERD) and Flash. | | 674 | * Microwire, SPI (w/wo EERD) and Flash. |
675 | */ | | 675 | */ |
676 | /* Misc functions */ | | 676 | /* Misc functions */ |
677 | static void wm_eeprom_sendbits(struct wm_softc *, uint32_t, int); | | 677 | static void wm_eeprom_sendbits(struct wm_softc *, uint32_t, int); |
678 | static void wm_eeprom_recvbits(struct wm_softc *, uint32_t *, int); | | 678 | static void wm_eeprom_recvbits(struct wm_softc *, uint32_t *, int); |
679 | static int wm_nvm_set_addrbits_size_eecd(struct wm_softc *); | | 679 | static int wm_nvm_set_addrbits_size_eecd(struct wm_softc *); |
680 | /* Microwire */ | | 680 | /* Microwire */ |
681 | static int wm_nvm_read_uwire(struct wm_softc *, int, int, uint16_t *); | | 681 | static int wm_nvm_read_uwire(struct wm_softc *, int, int, uint16_t *); |
682 | /* SPI */ | | 682 | /* SPI */ |
683 | static int wm_nvm_ready_spi(struct wm_softc *); | | 683 | static int wm_nvm_ready_spi(struct wm_softc *); |
684 | static int wm_nvm_read_spi(struct wm_softc *, int, int, uint16_t *); | | 684 | static int wm_nvm_read_spi(struct wm_softc *, int, int, uint16_t *); |
685 | /* Using with EERD */ | | 685 | /* Using with EERD */ |
686 | static int wm_poll_eerd_eewr_done(struct wm_softc *, int); | | 686 | static int wm_poll_eerd_eewr_done(struct wm_softc *, int); |
687 | static int wm_nvm_read_eerd(struct wm_softc *, int, int, uint16_t *); | | 687 | static int wm_nvm_read_eerd(struct wm_softc *, int, int, uint16_t *); |
688 | /* Flash */ | | 688 | /* Flash */ |
689 | static int wm_nvm_valid_bank_detect_ich8lan(struct wm_softc *, | | 689 | static int wm_nvm_valid_bank_detect_ich8lan(struct wm_softc *, |
690 | unsigned int *); | | 690 | unsigned int *); |
691 | static int32_t wm_ich8_cycle_init(struct wm_softc *); | | 691 | static int32_t wm_ich8_cycle_init(struct wm_softc *); |
692 | static int32_t wm_ich8_flash_cycle(struct wm_softc *, uint32_t); | | 692 | static int32_t wm_ich8_flash_cycle(struct wm_softc *, uint32_t); |
693 | static int32_t wm_read_ich8_data(struct wm_softc *, uint32_t, uint32_t, | | 693 | static int32_t wm_read_ich8_data(struct wm_softc *, uint32_t, uint32_t, |
694 | uint16_t *); | | 694 | uint16_t *); |
695 | static int32_t wm_read_ich8_byte(struct wm_softc *, uint32_t, uint8_t *); | | 695 | static int32_t wm_read_ich8_byte(struct wm_softc *, uint32_t, uint8_t *); |
696 | static int32_t wm_read_ich8_word(struct wm_softc *, uint32_t, uint16_t *); | | 696 | static int32_t wm_read_ich8_word(struct wm_softc *, uint32_t, uint16_t *); |
697 | static int wm_nvm_read_ich8(struct wm_softc *, int, int, uint16_t *); | | 697 | static int wm_nvm_read_ich8(struct wm_softc *, int, int, uint16_t *); |
698 | /* iNVM */ | | 698 | /* iNVM */ |
699 | static int wm_nvm_read_word_invm(struct wm_softc *, uint16_t, uint16_t *); | | 699 | static int wm_nvm_read_word_invm(struct wm_softc *, uint16_t, uint16_t *); |
700 | static int wm_nvm_read_invm(struct wm_softc *, int, int, uint16_t *); | | 700 | static int wm_nvm_read_invm(struct wm_softc *, int, int, uint16_t *); |
701 | /* Lock, detecting NVM type, validate checksum and read */ | | 701 | /* Lock, detecting NVM type, validate checksum and read */ |
702 | static int wm_nvm_acquire(struct wm_softc *); | | 702 | static int wm_nvm_acquire(struct wm_softc *); |
703 | static void wm_nvm_release(struct wm_softc *); | | 703 | static void wm_nvm_release(struct wm_softc *); |
704 | static int wm_nvm_is_onboard_eeprom(struct wm_softc *); | | 704 | static int wm_nvm_is_onboard_eeprom(struct wm_softc *); |
705 | static int wm_nvm_get_flash_presence_i210(struct wm_softc *); | | 705 | static int wm_nvm_get_flash_presence_i210(struct wm_softc *); |
706 | static int wm_nvm_validate_checksum(struct wm_softc *); | | 706 | static int wm_nvm_validate_checksum(struct wm_softc *); |
707 | static void wm_nvm_version_invm(struct wm_softc *); | | 707 | static void wm_nvm_version_invm(struct wm_softc *); |
708 | static void wm_nvm_version(struct wm_softc *); | | 708 | static void wm_nvm_version(struct wm_softc *); |
709 | static int wm_nvm_read(struct wm_softc *, int, int, uint16_t *); | | 709 | static int wm_nvm_read(struct wm_softc *, int, int, uint16_t *); |
710 | | | 710 | |
711 | /* | | 711 | /* |
712 | * Hardware semaphores. | | 712 | * Hardware semaphores. |
713 | * Very complexed... | | 713 | * Very complexed... |
714 | */ | | 714 | */ |
715 | static int wm_get_swsm_semaphore(struct wm_softc *); | | 715 | static int wm_get_swsm_semaphore(struct wm_softc *); |
716 | static void wm_put_swsm_semaphore(struct wm_softc *); | | 716 | static void wm_put_swsm_semaphore(struct wm_softc *); |
717 | static int wm_get_swfw_semaphore(struct wm_softc *, uint16_t); | | 717 | static int wm_get_swfw_semaphore(struct wm_softc *, uint16_t); |
718 | static void wm_put_swfw_semaphore(struct wm_softc *, uint16_t); | | 718 | static void wm_put_swfw_semaphore(struct wm_softc *, uint16_t); |
719 | static int wm_get_swfwhw_semaphore(struct wm_softc *); | | 719 | static int wm_get_swfwhw_semaphore(struct wm_softc *); |
720 | static void wm_put_swfwhw_semaphore(struct wm_softc *); | | 720 | static void wm_put_swfwhw_semaphore(struct wm_softc *); |
721 | static int wm_get_hw_semaphore_82573(struct wm_softc *); | | 721 | static int wm_get_hw_semaphore_82573(struct wm_softc *); |
722 | static void wm_put_hw_semaphore_82573(struct wm_softc *); | | 722 | static void wm_put_hw_semaphore_82573(struct wm_softc *); |
723 | | | 723 | |
724 | /* | | 724 | /* |
725 | * Management mode and power management related subroutines. | | 725 | * Management mode and power management related subroutines. |
726 | * BMC, AMT, suspend/resume and EEE. | | 726 | * BMC, AMT, suspend/resume and EEE. |
727 | */ | | 727 | */ |
728 | static int wm_check_mng_mode(struct wm_softc *); | | 728 | static int wm_check_mng_mode(struct wm_softc *); |
729 | static int wm_check_mng_mode_ich8lan(struct wm_softc *); | | 729 | static int wm_check_mng_mode_ich8lan(struct wm_softc *); |
730 | static int wm_check_mng_mode_82574(struct wm_softc *); | | 730 | static int wm_check_mng_mode_82574(struct wm_softc *); |
731 | static int wm_check_mng_mode_generic(struct wm_softc *); | | 731 | static int wm_check_mng_mode_generic(struct wm_softc *); |
732 | static int wm_enable_mng_pass_thru(struct wm_softc *); | | 732 | static int wm_enable_mng_pass_thru(struct wm_softc *); |
733 | static int wm_check_reset_block(struct wm_softc *); | | 733 | static int wm_check_reset_block(struct wm_softc *); |
734 | static void wm_get_hw_control(struct wm_softc *); | | 734 | static void wm_get_hw_control(struct wm_softc *); |
735 | static void wm_release_hw_control(struct wm_softc *); | | 735 | static void wm_release_hw_control(struct wm_softc *); |
736 | static void wm_gate_hw_phy_config_ich8lan(struct wm_softc *, int); | | 736 | static void wm_gate_hw_phy_config_ich8lan(struct wm_softc *, int); |
737 | static void wm_smbustopci(struct wm_softc *); | | 737 | static void wm_smbustopci(struct wm_softc *); |
738 | static void wm_init_manageability(struct wm_softc *); | | 738 | static void wm_init_manageability(struct wm_softc *); |
739 | static void wm_release_manageability(struct wm_softc *); | | 739 | static void wm_release_manageability(struct wm_softc *); |
740 | static void wm_get_wakeup(struct wm_softc *); | | 740 | static void wm_get_wakeup(struct wm_softc *); |
741 | #ifdef WM_WOL | | 741 | #ifdef WM_WOL |
742 | static void wm_enable_phy_wakeup(struct wm_softc *); | | 742 | static void wm_enable_phy_wakeup(struct wm_softc *); |
743 | static void wm_igp3_phy_powerdown_workaround_ich8lan(struct wm_softc *); | | 743 | static void wm_igp3_phy_powerdown_workaround_ich8lan(struct wm_softc *); |
744 | static void wm_enable_wakeup(struct wm_softc *); | | 744 | static void wm_enable_wakeup(struct wm_softc *); |
745 | #endif | | 745 | #endif |
746 | /* EEE */ | | 746 | /* EEE */ |
747 | static void wm_set_eee_i350(struct wm_softc *); | | 747 | static void wm_set_eee_i350(struct wm_softc *); |
748 | | | 748 | |
749 | /* | | 749 | /* |
750 | * Workarounds (mainly PHY related). | | 750 | * Workarounds (mainly PHY related). |
751 | * Basically, PHY's workarounds are in the PHY drivers. | | 751 | * Basically, PHY's workarounds are in the PHY drivers. |
752 | */ | | 752 | */ |
753 | static void wm_kmrn_lock_loss_workaround_ich8lan(struct wm_softc *); | | 753 | static void wm_kmrn_lock_loss_workaround_ich8lan(struct wm_softc *); |
754 | static void wm_gig_downshift_workaround_ich8lan(struct wm_softc *); | | 754 | static void wm_gig_downshift_workaround_ich8lan(struct wm_softc *); |
755 | static void wm_hv_phy_workaround_ich8lan(struct wm_softc *); | | 755 | static void wm_hv_phy_workaround_ich8lan(struct wm_softc *); |
756 | static void wm_lv_phy_workaround_ich8lan(struct wm_softc *); | | 756 | static void wm_lv_phy_workaround_ich8lan(struct wm_softc *); |
757 | static void wm_k1_gig_workaround_hv(struct wm_softc *, int); | | 757 | static void wm_k1_gig_workaround_hv(struct wm_softc *, int); |
758 | static void wm_set_mdio_slow_mode_hv(struct wm_softc *); | | 758 | static void wm_set_mdio_slow_mode_hv(struct wm_softc *); |
759 | static void wm_configure_k1_ich8lan(struct wm_softc *, int); | | 759 | static void wm_configure_k1_ich8lan(struct wm_softc *, int); |
760 | static void wm_reset_init_script_82575(struct wm_softc *); | | 760 | static void wm_reset_init_script_82575(struct wm_softc *); |
761 | static void wm_reset_mdicnfg_82580(struct wm_softc *); | | 761 | static void wm_reset_mdicnfg_82580(struct wm_softc *); |
762 | static void wm_pll_workaround_i210(struct wm_softc *); | | 762 | static void wm_pll_workaround_i210(struct wm_softc *); |
763 | | | 763 | |
764 | #ifdef WM_MSI_MSIX | | 764 | #ifdef WM_MSI_MSIX |
765 | struct _msix_matrix { | | 765 | struct _msix_matrix { |
766 | const char *intrname; | | 766 | const char *intrname; |
767 | int(*func)(void *); | | 767 | int(*func)(void *); |
768 | int intridx; | | 768 | int intridx; |
769 | int cpuid; | | 769 | int cpuid; |
770 | } msix_matrix[WM_MSIX_NINTR] = { | | 770 | } msix_matrix[WM_MSIX_NINTR] = { |
771 | { "TX", wm_txintr_msix, WM_MSIX_TXINTR_IDX, WM_MSIX_TXINTR_CPUID }, | | 771 | { "TX", wm_txintr_msix, WM_MSIX_TXINTR_IDX, WM_MSIX_TXINTR_CPUID }, |
772 | { "RX", wm_rxintr_msix, WM_MSIX_RXINTR_IDX, WM_MSIX_RXINTR_CPUID }, | | 772 | { "RX", wm_rxintr_msix, WM_MSIX_RXINTR_IDX, WM_MSIX_RXINTR_CPUID }, |
773 | { "LINK", wm_linkintr_msix, WM_MSIX_LINKINTR_IDX, | | 773 | { "LINK", wm_linkintr_msix, WM_MSIX_LINKINTR_IDX, |
774 | WM_MSIX_LINKINTR_CPUID }, | | 774 | WM_MSIX_LINKINTR_CPUID }, |
775 | }; | | 775 | }; |
776 | #endif | | 776 | #endif |
777 | | | 777 | |
778 | CFATTACH_DECL3_NEW(wm, sizeof(struct wm_softc), | | 778 | CFATTACH_DECL3_NEW(wm, sizeof(struct wm_softc), |
779 | wm_match, wm_attach, wm_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); | | 779 | wm_match, wm_attach, wm_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); |
780 | | | 780 | |
781 | /* | | 781 | /* |
782 | * Devices supported by this driver. | | 782 | * Devices supported by this driver. |
783 | */ | | 783 | */ |
784 | static const struct wm_product { | | 784 | static const struct wm_product { |
785 | pci_vendor_id_t wmp_vendor; | | 785 | pci_vendor_id_t wmp_vendor; |
786 | pci_product_id_t wmp_product; | | 786 | pci_product_id_t wmp_product; |
787 | const char *wmp_name; | | 787 | const char *wmp_name; |
788 | wm_chip_type wmp_type; | | 788 | wm_chip_type wmp_type; |
789 | uint32_t wmp_flags; | | 789 | uint32_t wmp_flags; |
790 | #define WMP_F_UNKNOWN WM_MEDIATYPE_UNKNOWN | | 790 | #define WMP_F_UNKNOWN WM_MEDIATYPE_UNKNOWN |
791 | #define WMP_F_FIBER WM_MEDIATYPE_FIBER | | 791 | #define WMP_F_FIBER WM_MEDIATYPE_FIBER |
792 | #define WMP_F_COPPER WM_MEDIATYPE_COPPER | | 792 | #define WMP_F_COPPER WM_MEDIATYPE_COPPER |
793 | #define WMP_F_SERDES WM_MEDIATYPE_SERDES | | 793 | #define WMP_F_SERDES WM_MEDIATYPE_SERDES |
794 | #define WMP_MEDIATYPE(x) ((x) & 0x03) | | 794 | #define WMP_MEDIATYPE(x) ((x) & 0x03) |
795 | } wm_products[] = { | | 795 | } wm_products[] = { |
796 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542, | | 796 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542, |
797 | "Intel i82542 1000BASE-X Ethernet", | | 797 | "Intel i82542 1000BASE-X Ethernet", |
798 | WM_T_82542_2_1, WMP_F_FIBER }, | | 798 | WM_T_82542_2_1, WMP_F_FIBER }, |
799 | | | 799 | |
800 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER, | | 800 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER, |
801 | "Intel i82543GC 1000BASE-X Ethernet", | | 801 | "Intel i82543GC 1000BASE-X Ethernet", |
802 | WM_T_82543, WMP_F_FIBER }, | | 802 | WM_T_82543, WMP_F_FIBER }, |
803 | | | 803 | |
804 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER, | | 804 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER, |
805 | "Intel i82543GC 1000BASE-T Ethernet", | | 805 | "Intel i82543GC 1000BASE-T Ethernet", |
806 | WM_T_82543, WMP_F_COPPER }, | | 806 | WM_T_82543, WMP_F_COPPER }, |
807 | | | 807 | |
808 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER, | | 808 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER, |
809 | "Intel i82544EI 1000BASE-T Ethernet", | | 809 | "Intel i82544EI 1000BASE-T Ethernet", |
810 | WM_T_82544, WMP_F_COPPER }, | | 810 | WM_T_82544, WMP_F_COPPER }, |
811 | | | 811 | |
812 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER, | | 812 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER, |
813 | "Intel i82544EI 1000BASE-X Ethernet", | | 813 | "Intel i82544EI 1000BASE-X Ethernet", |
814 | WM_T_82544, WMP_F_FIBER }, | | 814 | WM_T_82544, WMP_F_FIBER }, |
815 | | | 815 | |
816 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER, | | 816 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER, |
817 | "Intel i82544GC 1000BASE-T Ethernet", | | 817 | "Intel i82544GC 1000BASE-T Ethernet", |
818 | WM_T_82544, WMP_F_COPPER }, | | 818 | WM_T_82544, WMP_F_COPPER }, |
819 | | | 819 | |
820 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM, | | 820 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM, |
821 | "Intel i82544GC (LOM) 1000BASE-T Ethernet", | | 821 | "Intel i82544GC (LOM) 1000BASE-T Ethernet", |
822 | WM_T_82544, WMP_F_COPPER }, | | 822 | WM_T_82544, WMP_F_COPPER }, |
823 | | | 823 | |
824 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM, | | 824 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM, |
825 | "Intel i82540EM 1000BASE-T Ethernet", | | 825 | "Intel i82540EM 1000BASE-T Ethernet", |
826 | WM_T_82540, WMP_F_COPPER }, | | 826 | WM_T_82540, WMP_F_COPPER }, |
827 | | | 827 | |
828 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM, | | 828 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM, |
829 | "Intel i82540EM (LOM) 1000BASE-T Ethernet", | | 829 | "Intel i82540EM (LOM) 1000BASE-T Ethernet", |
830 | WM_T_82540, WMP_F_COPPER }, | | 830 | WM_T_82540, WMP_F_COPPER }, |
831 | | | 831 | |
832 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM, | | 832 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM, |
833 | "Intel i82540EP 1000BASE-T Ethernet", | | 833 | "Intel i82540EP 1000BASE-T Ethernet", |
834 | WM_T_82540, WMP_F_COPPER }, | | 834 | WM_T_82540, WMP_F_COPPER }, |
835 | | | 835 | |
836 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP, | | 836 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP, |
837 | "Intel i82540EP 1000BASE-T Ethernet", | | 837 | "Intel i82540EP 1000BASE-T Ethernet", |
838 | WM_T_82540, WMP_F_COPPER }, | | 838 | WM_T_82540, WMP_F_COPPER }, |
839 | | | 839 | |
840 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP, | | 840 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP, |
841 | "Intel i82540EP 1000BASE-T Ethernet", | | 841 | "Intel i82540EP 1000BASE-T Ethernet", |
842 | WM_T_82540, WMP_F_COPPER }, | | 842 | WM_T_82540, WMP_F_COPPER }, |
843 | | | 843 | |
844 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER, | | 844 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER, |
845 | "Intel i82545EM 1000BASE-T Ethernet", | | 845 | "Intel i82545EM 1000BASE-T Ethernet", |
846 | WM_T_82545, WMP_F_COPPER }, | | 846 | WM_T_82545, WMP_F_COPPER }, |
847 | | | 847 | |
848 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER, | | 848 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER, |
849 | "Intel i82545GM 1000BASE-T Ethernet", | | 849 | "Intel i82545GM 1000BASE-T Ethernet", |
850 | WM_T_82545_3, WMP_F_COPPER }, | | 850 | WM_T_82545_3, WMP_F_COPPER }, |
851 | | | 851 | |
852 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER, | | 852 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER, |
853 | "Intel i82545GM 1000BASE-X Ethernet", | | 853 | "Intel i82545GM 1000BASE-X Ethernet", |
854 | WM_T_82545_3, WMP_F_FIBER }, | | 854 | WM_T_82545_3, WMP_F_FIBER }, |
855 | | | 855 | |
856 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES, | | 856 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES, |
857 | "Intel i82545GM Gigabit Ethernet (SERDES)", | | 857 | "Intel i82545GM Gigabit Ethernet (SERDES)", |
858 | WM_T_82545_3, WMP_F_SERDES }, | | 858 | WM_T_82545_3, WMP_F_SERDES }, |
859 | | | 859 | |
860 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER, | | 860 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER, |
861 | "Intel i82546EB 1000BASE-T Ethernet", | | 861 | "Intel i82546EB 1000BASE-T Ethernet", |
862 | WM_T_82546, WMP_F_COPPER }, | | 862 | WM_T_82546, WMP_F_COPPER }, |
863 | | | 863 | |
864 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD, | | 864 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD, |
865 | "Intel i82546EB 1000BASE-T Ethernet", | | 865 | "Intel i82546EB 1000BASE-T Ethernet", |
866 | WM_T_82546, WMP_F_COPPER }, | | 866 | WM_T_82546, WMP_F_COPPER }, |
867 | | | 867 | |
868 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER, | | 868 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER, |
869 | "Intel i82545EM 1000BASE-X Ethernet", | | 869 | "Intel i82545EM 1000BASE-X Ethernet", |
870 | WM_T_82545, WMP_F_FIBER }, | | 870 | WM_T_82545, WMP_F_FIBER }, |
871 | | | 871 | |
872 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER, | | 872 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER, |
873 | "Intel i82546EB 1000BASE-X Ethernet", | | 873 | "Intel i82546EB 1000BASE-X Ethernet", |
874 | WM_T_82546, WMP_F_FIBER }, | | 874 | WM_T_82546, WMP_F_FIBER }, |
875 | | | 875 | |
876 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER, | | 876 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER, |
877 | "Intel i82546GB 1000BASE-T Ethernet", | | 877 | "Intel i82546GB 1000BASE-T Ethernet", |
878 | WM_T_82546_3, WMP_F_COPPER }, | | 878 | WM_T_82546_3, WMP_F_COPPER }, |
879 | | | 879 | |
880 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER, | | 880 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER, |
881 | "Intel i82546GB 1000BASE-X Ethernet", | | 881 | "Intel i82546GB 1000BASE-X Ethernet", |
882 | WM_T_82546_3, WMP_F_FIBER }, | | 882 | WM_T_82546_3, WMP_F_FIBER }, |
883 | | | 883 | |
884 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES, | | 884 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES, |
885 | "Intel i82546GB Gigabit Ethernet (SERDES)", | | 885 | "Intel i82546GB Gigabit Ethernet (SERDES)", |
886 | WM_T_82546_3, WMP_F_SERDES }, | | 886 | WM_T_82546_3, WMP_F_SERDES }, |
887 | | | 887 | |
888 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER, | | 888 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER, |
889 | "i82546GB quad-port Gigabit Ethernet", | | 889 | "i82546GB quad-port Gigabit Ethernet", |
890 | WM_T_82546_3, WMP_F_COPPER }, | | 890 | WM_T_82546_3, WMP_F_COPPER }, |
891 | | | 891 | |
892 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER_KSP3, | | 892 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER_KSP3, |
893 | "i82546GB quad-port Gigabit Ethernet (KSP3)", | | 893 | "i82546GB quad-port Gigabit Ethernet (KSP3)", |
894 | WM_T_82546_3, WMP_F_COPPER }, | | 894 | WM_T_82546_3, WMP_F_COPPER }, |
895 | | | 895 | |
896 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_PCIE, | | 896 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_PCIE, |
897 | "Intel PRO/1000MT (82546GB)", | | 897 | "Intel PRO/1000MT (82546GB)", |
898 | WM_T_82546_3, WMP_F_COPPER }, | | 898 | WM_T_82546_3, WMP_F_COPPER }, |
899 | | | 899 | |
900 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI, | | 900 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI, |
901 | "Intel i82541EI 1000BASE-T Ethernet", | | 901 | "Intel i82541EI 1000BASE-T Ethernet", |
902 | WM_T_82541, WMP_F_COPPER }, | | 902 | WM_T_82541, WMP_F_COPPER }, |
903 | | | 903 | |
904 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER_LOM, | | 904 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER_LOM, |
905 | "Intel i82541ER (LOM) 1000BASE-T Ethernet", | | 905 | "Intel i82541ER (LOM) 1000BASE-T Ethernet", |
906 | WM_T_82541, WMP_F_COPPER }, | | 906 | WM_T_82541, WMP_F_COPPER }, |
907 | | | 907 | |
908 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE, | | 908 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE, |
909 | "Intel i82541EI Mobile 1000BASE-T Ethernet", | | 909 | "Intel i82541EI Mobile 1000BASE-T Ethernet", |
910 | WM_T_82541, WMP_F_COPPER }, | | 910 | WM_T_82541, WMP_F_COPPER }, |
911 | | | 911 | |
912 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER, | | 912 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER, |
913 | "Intel i82541ER 1000BASE-T Ethernet", | | 913 | "Intel i82541ER 1000BASE-T Ethernet", |
914 | WM_T_82541_2, WMP_F_COPPER }, | | 914 | WM_T_82541_2, WMP_F_COPPER }, |
915 | | | 915 | |
916 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI, | | 916 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI, |
917 | "Intel i82541GI 1000BASE-T Ethernet", | | 917 | "Intel i82541GI 1000BASE-T Ethernet", |
918 | WM_T_82541_2, WMP_F_COPPER }, | | 918 | WM_T_82541_2, WMP_F_COPPER }, |
919 | | | 919 | |
920 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE, | | 920 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE, |
921 | "Intel i82541GI Mobile 1000BASE-T Ethernet", | | 921 | "Intel i82541GI Mobile 1000BASE-T Ethernet", |
922 | WM_T_82541_2, WMP_F_COPPER }, | | 922 | WM_T_82541_2, WMP_F_COPPER }, |
923 | | | 923 | |
924 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541PI, | | 924 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541PI, |
925 | "Intel i82541PI 1000BASE-T Ethernet", | | 925 | "Intel i82541PI 1000BASE-T Ethernet", |
926 | WM_T_82541_2, WMP_F_COPPER }, | | 926 | WM_T_82541_2, WMP_F_COPPER }, |
927 | | | 927 | |
928 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI, | | 928 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI, |
929 | "Intel i82547EI 1000BASE-T Ethernet", | | 929 | "Intel i82547EI 1000BASE-T Ethernet", |
930 | WM_T_82547, WMP_F_COPPER }, | | 930 | WM_T_82547, WMP_F_COPPER }, |
931 | | | 931 | |
932 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI_MOBILE, | | 932 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI_MOBILE, |
933 | "Intel i82547EI Mobile 1000BASE-T Ethernet", | | 933 | "Intel i82547EI Mobile 1000BASE-T Ethernet", |
934 | WM_T_82547, WMP_F_COPPER }, | | 934 | WM_T_82547, WMP_F_COPPER }, |
935 | | | 935 | |
936 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI, | | 936 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI, |
937 | "Intel i82547GI 1000BASE-T Ethernet", | | 937 | "Intel i82547GI 1000BASE-T Ethernet", |
938 | WM_T_82547_2, WMP_F_COPPER }, | | 938 | WM_T_82547_2, WMP_F_COPPER }, |
939 | | | 939 | |
940 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_COPPER, | | 940 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_COPPER, |
941 | "Intel PRO/1000 PT (82571EB)", | | 941 | "Intel PRO/1000 PT (82571EB)", |
942 | WM_T_82571, WMP_F_COPPER }, | | 942 | WM_T_82571, WMP_F_COPPER }, |
943 | | | 943 | |
944 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_FIBER, | | 944 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_FIBER, |
945 | "Intel PRO/1000 PF (82571EB)", | | 945 | "Intel PRO/1000 PF (82571EB)", |
946 | WM_T_82571, WMP_F_FIBER }, | | 946 | WM_T_82571, WMP_F_FIBER }, |
947 | | | 947 | |
948 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SERDES, | | 948 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SERDES, |
949 | "Intel PRO/1000 PB (82571EB)", | | 949 | "Intel PRO/1000 PB (82571EB)", |
950 | WM_T_82571, WMP_F_SERDES }, | | 950 | WM_T_82571, WMP_F_SERDES }, |
951 | | | 951 | |
952 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_COPPER, | | 952 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_COPPER, |
953 | "Intel PRO/1000 QT (82571EB)", | | 953 | "Intel PRO/1000 QT (82571EB)", |
954 | WM_T_82571, WMP_F_COPPER }, | | 954 | WM_T_82571, WMP_F_COPPER }, |
955 | | | 955 | |
956 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571GB_QUAD_COPPER, | | 956 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571GB_QUAD_COPPER, |
957 | "Intel PRO/1000 PT Quad Port Server Adapter", | | 957 | "Intel PRO/1000 PT Quad Port Server Adapter", |
958 | WM_T_82571, WMP_F_COPPER, }, | | 958 | WM_T_82571, WMP_F_COPPER, }, |
959 | | | 959 | |
960 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571PT_QUAD_COPPER, | | 960 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571PT_QUAD_COPPER, |
961 | "Intel Gigabit PT Quad Port Server ExpressModule", | | 961 | "Intel Gigabit PT Quad Port Server ExpressModule", |
962 | WM_T_82571, WMP_F_COPPER, }, | | 962 | WM_T_82571, WMP_F_COPPER, }, |
963 | | | 963 | |
964 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_DUAL_SERDES, | | 964 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_DUAL_SERDES, |
965 | "Intel 82571EB Dual Gigabit Ethernet (SERDES)", | | 965 | "Intel 82571EB Dual Gigabit Ethernet (SERDES)", |
966 | WM_T_82571, WMP_F_SERDES, }, | | 966 | WM_T_82571, WMP_F_SERDES, }, |
967 | | | 967 | |
968 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_SERDES, | | 968 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_SERDES, |
969 | "Intel 82571EB Quad Gigabit Ethernet (SERDES)", | | 969 | "Intel 82571EB Quad Gigabit Ethernet (SERDES)", |
970 | WM_T_82571, WMP_F_SERDES, }, | | 970 | WM_T_82571, WMP_F_SERDES, }, |
971 | | | 971 | |
972 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_FIBER, | | 972 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_FIBER, |
973 | "Intel 82571EB Quad 1000baseX Ethernet", | | 973 | "Intel 82571EB Quad 1000baseX Ethernet", |
974 | WM_T_82571, WMP_F_FIBER, }, | | 974 | WM_T_82571, WMP_F_FIBER, }, |
975 | | | 975 | |
976 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_COPPER, | | 976 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_COPPER, |
977 | "Intel i82572EI 1000baseT Ethernet", | | 977 | "Intel i82572EI 1000baseT Ethernet", |
978 | WM_T_82572, WMP_F_COPPER }, | | 978 | WM_T_82572, WMP_F_COPPER }, |
979 | | | 979 | |
980 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_FIBER, | | 980 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_FIBER, |
981 | "Intel i82572EI 1000baseX Ethernet", | | 981 | "Intel i82572EI 1000baseX Ethernet", |
982 | WM_T_82572, WMP_F_FIBER }, | | 982 | WM_T_82572, WMP_F_FIBER }, |
983 | | | 983 | |
984 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_SERDES, | | 984 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_SERDES, |
985 | "Intel i82572EI Gigabit Ethernet (SERDES)", | | 985 | "Intel i82572EI Gigabit Ethernet (SERDES)", |
986 | WM_T_82572, WMP_F_SERDES }, | | 986 | WM_T_82572, WMP_F_SERDES }, |
987 | | | 987 | |
988 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI, | | 988 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI, |
989 | "Intel i82572EI 1000baseT Ethernet", | | 989 | "Intel i82572EI 1000baseT Ethernet", |
990 | WM_T_82572, WMP_F_COPPER }, | | 990 | WM_T_82572, WMP_F_COPPER }, |
991 | | | 991 | |
992 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E, | | 992 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E, |
993 | "Intel i82573E", | | 993 | "Intel i82573E", |
994 | WM_T_82573, WMP_F_COPPER }, | | 994 | WM_T_82573, WMP_F_COPPER }, |
995 | | | 995 | |
996 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_IAMT, | | 996 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_IAMT, |
997 | "Intel i82573E IAMT", | | 997 | "Intel i82573E IAMT", |
998 | WM_T_82573, WMP_F_COPPER }, | | 998 | WM_T_82573, WMP_F_COPPER }, |
999 | | | 999 | |
1000 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L, | | 1000 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L, |
1001 | "Intel i82573L Gigabit Ethernet", | | 1001 | "Intel i82573L Gigabit Ethernet", |
1002 | WM_T_82573, WMP_F_COPPER }, | | 1002 | WM_T_82573, WMP_F_COPPER }, |
1003 | | | 1003 | |
1004 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574L, | | 1004 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574L, |
1005 | "Intel i82574L", | | 1005 | "Intel i82574L", |
1006 | WM_T_82574, WMP_F_COPPER }, | | 1006 | WM_T_82574, WMP_F_COPPER }, |
1007 | | | 1007 | |
1008 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574LA, | | 1008 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574LA, |
1009 | "Intel i82574L", | | 1009 | "Intel i82574L", |
1010 | WM_T_82574, WMP_F_COPPER }, | | 1010 | WM_T_82574, WMP_F_COPPER }, |
1011 | | | 1011 | |
1012 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82583V, | | 1012 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82583V, |
1013 | "Intel i82583V", | | 1013 | "Intel i82583V", |
1014 | WM_T_82583, WMP_F_COPPER }, | | 1014 | WM_T_82583, WMP_F_COPPER }, |
1015 | | | 1015 | |
1016 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_CPR_DPT, | | 1016 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_CPR_DPT, |
1017 | "i80003 dual 1000baseT Ethernet", | | 1017 | "i80003 dual 1000baseT Ethernet", |
1018 | WM_T_80003, WMP_F_COPPER }, | | 1018 | WM_T_80003, WMP_F_COPPER }, |
1019 | | | 1019 | |
1020 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_FIB_DPT, | | 1020 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_FIB_DPT, |
1021 | "i80003 dual 1000baseX Ethernet", | | 1021 | "i80003 dual 1000baseX Ethernet", |
1022 | WM_T_80003, WMP_F_COPPER }, | | 1022 | WM_T_80003, WMP_F_COPPER }, |
1023 | | | 1023 | |
1024 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_SDS_DPT, | | 1024 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_SDS_DPT, |
1025 | "Intel i80003ES2 dual Gigabit Ethernet (SERDES)", | | 1025 | "Intel i80003ES2 dual Gigabit Ethernet (SERDES)", |
1026 | WM_T_80003, WMP_F_SERDES }, | | 1026 | WM_T_80003, WMP_F_SERDES }, |
1027 | | | 1027 | |
1028 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_CPR_SPT, | | 1028 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_CPR_SPT, |
1029 | "Intel i80003 1000baseT Ethernet", | | 1029 | "Intel i80003 1000baseT Ethernet", |
1030 | WM_T_80003, WMP_F_COPPER }, | | 1030 | WM_T_80003, WMP_F_COPPER }, |
1031 | | | 1031 | |
1032 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_SDS_SPT, | | 1032 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_SDS_SPT, |
1033 | "Intel i80003 Gigabit Ethernet (SERDES)", | | 1033 | "Intel i80003 Gigabit Ethernet (SERDES)", |
1034 | WM_T_80003, WMP_F_SERDES }, | | 1034 | WM_T_80003, WMP_F_SERDES }, |
1035 | | | 1035 | |
1036 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_M_AMT, | | 1036 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_M_AMT, |
1037 | "Intel i82801H (M_AMT) LAN Controller", | | 1037 | "Intel i82801H (M_AMT) LAN Controller", |
1038 | WM_T_ICH8, WMP_F_COPPER }, | | 1038 | WM_T_ICH8, WMP_F_COPPER }, |
1039 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_AMT, | | 1039 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_AMT, |
1040 | "Intel i82801H (AMT) LAN Controller", | | 1040 | "Intel i82801H (AMT) LAN Controller", |
1041 | WM_T_ICH8, WMP_F_COPPER }, | | 1041 | WM_T_ICH8, WMP_F_COPPER }, |
1042 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LAN, | | 1042 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LAN, |
1043 | "Intel i82801H LAN Controller", | | 1043 | "Intel i82801H LAN Controller", |
1044 | WM_T_ICH8, WMP_F_COPPER }, | | 1044 | WM_T_ICH8, WMP_F_COPPER }, |
1045 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IFE_LAN, | | 1045 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IFE_LAN, |
1046 | "Intel i82801H (IFE) LAN Controller", | | 1046 | "Intel i82801H (IFE) LAN Controller", |
1047 | WM_T_ICH8, WMP_F_COPPER }, | | 1047 | WM_T_ICH8, WMP_F_COPPER }, |
1048 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_M_LAN, | | 1048 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_M_LAN, |
1049 | "Intel i82801H (M) LAN Controller", | | 1049 | "Intel i82801H (M) LAN Controller", |
1050 | WM_T_ICH8, WMP_F_COPPER }, | | 1050 | WM_T_ICH8, WMP_F_COPPER }, |
1051 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IFE_GT, | | 1051 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IFE_GT, |
1052 | "Intel i82801H IFE (GT) LAN Controller", | | 1052 | "Intel i82801H IFE (GT) LAN Controller", |
1053 | WM_T_ICH8, WMP_F_COPPER }, | | 1053 | WM_T_ICH8, WMP_F_COPPER }, |
1054 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IFE_G, | | 1054 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IFE_G, |
1055 | "Intel i82801H IFE (G) LAN Controller", | | 1055 | "Intel i82801H IFE (G) LAN Controller", |
1056 | WM_T_ICH8, WMP_F_COPPER }, | | 1056 | WM_T_ICH8, WMP_F_COPPER }, |
1057 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_AMT, | | 1057 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_AMT, |
1058 | "82801I (AMT) LAN Controller", | | 1058 | "82801I (AMT) LAN Controller", |
1059 | WM_T_ICH9, WMP_F_COPPER }, | | 1059 | WM_T_ICH9, WMP_F_COPPER }, |
1060 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IFE, | | 1060 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IFE, |
1061 | "82801I LAN Controller", | | 1061 | "82801I LAN Controller", |
1062 | WM_T_ICH9, WMP_F_COPPER }, | | 1062 | WM_T_ICH9, WMP_F_COPPER }, |
1063 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IFE_G, | | 1063 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IFE_G, |
1064 | "82801I (G) LAN Controller", | | 1064 | "82801I (G) LAN Controller", |
1065 | WM_T_ICH9, WMP_F_COPPER }, | | 1065 | WM_T_ICH9, WMP_F_COPPER }, |
1066 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IFE_GT, | | 1066 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IFE_GT, |
1067 | "82801I (GT) LAN Controller", | | 1067 | "82801I (GT) LAN Controller", |
1068 | WM_T_ICH9, WMP_F_COPPER }, | | 1068 | WM_T_ICH9, WMP_F_COPPER }, |
1069 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_C, | | 1069 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_C, |
1070 | "82801I (C) LAN Controller", | | 1070 | "82801I (C) LAN Controller", |
1071 | WM_T_ICH9, WMP_F_COPPER }, | | 1071 | WM_T_ICH9, WMP_F_COPPER }, |
1072 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_M, | | 1072 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_M, |
1073 | "82801I mobile LAN Controller", | | 1073 | "82801I mobile LAN Controller", |
1074 | WM_T_ICH9, WMP_F_COPPER }, | | 1074 | WM_T_ICH9, WMP_F_COPPER }, |
1075 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IGP_M_V, | | 1075 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IGP_M_V, |
1076 | "82801I mobile (V) LAN Controller", | | 1076 | "82801I mobile (V) LAN Controller", |
1077 | WM_T_ICH9, WMP_F_COPPER }, | | 1077 | WM_T_ICH9, WMP_F_COPPER }, |
1078 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_M_AMT, | | 1078 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_M_AMT, |
1079 | "82801I mobile (AMT) LAN Controller", | | 1079 | "82801I mobile (AMT) LAN Controller", |
1080 | WM_T_ICH9, WMP_F_COPPER }, | | 1080 | WM_T_ICH9, WMP_F_COPPER }, |
1081 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_BM, | | 1081 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_BM, |
1082 | "82567LM-4 LAN Controller", | | 1082 | "82567LM-4 LAN Controller", |
1083 | WM_T_ICH9, WMP_F_COPPER }, | | 1083 | WM_T_ICH9, WMP_F_COPPER }, |
1084 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_82567V_3, | | 1084 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_82567V_3, |
1085 | "82567V-3 LAN Controller", | | 1085 | "82567V-3 LAN Controller", |
1086 | WM_T_ICH9, WMP_F_COPPER }, | | 1086 | WM_T_ICH9, WMP_F_COPPER }, |
1087 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_R_BM_LM, | | 1087 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_R_BM_LM, |
1088 | "82567LM-2 LAN Controller", | | 1088 | "82567LM-2 LAN Controller", |
1089 | WM_T_ICH10, WMP_F_COPPER }, | | 1089 | WM_T_ICH10, WMP_F_COPPER }, |
1090 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_R_BM_LF, | | 1090 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_R_BM_LF, |
1091 | "82567LF-2 LAN Controller", | | 1091 | "82567LF-2 LAN Controller", |
1092 | WM_T_ICH10, WMP_F_COPPER }, | | 1092 | WM_T_ICH10, WMP_F_COPPER }, |
1093 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_D_BM_LM, | | 1093 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_D_BM_LM, |
1094 | "82567LM-3 LAN Controller", | | 1094 | "82567LM-3 LAN Controller", |
1095 | WM_T_ICH10, WMP_F_COPPER }, | | 1095 | WM_T_ICH10, WMP_F_COPPER }, |
1096 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_D_BM_LF, | | 1096 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_D_BM_LF, |
1097 | "82567LF-3 LAN Controller", | | 1097 | "82567LF-3 LAN Controller", |
1098 | WM_T_ICH10, WMP_F_COPPER }, | | 1098 | WM_T_ICH10, WMP_F_COPPER }, |
1099 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_R_BM_V, | | 1099 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_R_BM_V, |
1100 | "82567V-2 LAN Controller", | | 1100 | "82567V-2 LAN Controller", |
1101 | WM_T_ICH10, WMP_F_COPPER }, | | 1101 | WM_T_ICH10, WMP_F_COPPER }, |
1102 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_D_BM_V, | | 1102 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_D_BM_V, |
1103 | "82567V-3? LAN Controller", | | 1103 | "82567V-3? LAN Controller", |
1104 | WM_T_ICH10, WMP_F_COPPER }, | | 1104 | WM_T_ICH10, WMP_F_COPPER }, |
1105 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HANKSVILLE, | | 1105 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HANKSVILLE, |
1106 | "HANKSVILLE LAN Controller", | | 1106 | "HANKSVILLE LAN Controller", |
1107 | WM_T_ICH10, WMP_F_COPPER }, | | 1107 | WM_T_ICH10, WMP_F_COPPER }, |
1108 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_M_LM, | | 1108 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_M_LM, |
1109 | "PCH LAN (82577LM) Controller", | | 1109 | "PCH LAN (82577LM) Controller", |
1110 | WM_T_PCH, WMP_F_COPPER }, | | 1110 | WM_T_PCH, WMP_F_COPPER }, |
1111 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_M_LC, | | 1111 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_M_LC, |
1112 | "PCH LAN (82577LC) Controller", | | 1112 | "PCH LAN (82577LC) Controller", |
1113 | WM_T_PCH, WMP_F_COPPER }, | | 1113 | WM_T_PCH, WMP_F_COPPER }, |
1114 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_D_DM, | | 1114 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_D_DM, |
1115 | "PCH LAN (82578DM) Controller", | | 1115 | "PCH LAN (82578DM) Controller", |
1116 | WM_T_PCH, WMP_F_COPPER }, | | 1116 | WM_T_PCH, WMP_F_COPPER }, |
1117 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_D_DC, | | 1117 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_D_DC, |
1118 | "PCH LAN (82578DC) Controller", | | 1118 | "PCH LAN (82578DC) Controller", |
1119 | WM_T_PCH, WMP_F_COPPER }, | | 1119 | WM_T_PCH, WMP_F_COPPER }, |
1120 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH2_LV_LM, | | 1120 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH2_LV_LM, |
1121 | "PCH2 LAN (82579LM) Controller", | | 1121 | "PCH2 LAN (82579LM) Controller", |
1122 | WM_T_PCH2, WMP_F_COPPER }, | | 1122 | WM_T_PCH2, WMP_F_COPPER }, |
1123 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH2_LV_V, | | 1123 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH2_LV_V, |
1124 | "PCH2 LAN (82579V) Controller", | | 1124 | "PCH2 LAN (82579V) Controller", |
1125 | WM_T_PCH2, WMP_F_COPPER }, | | 1125 | WM_T_PCH2, WMP_F_COPPER }, |
1126 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_COPPER, | | 1126 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_COPPER, |
1127 | "82575EB dual-1000baseT Ethernet", | | 1127 | "82575EB dual-1000baseT Ethernet", |
1128 | WM_T_82575, WMP_F_COPPER }, | | 1128 | WM_T_82575, WMP_F_COPPER }, |
1129 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_FIBER_SERDES, | | 1129 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_FIBER_SERDES, |
1130 | "82575EB dual-1000baseX Ethernet (SERDES)", | | 1130 | "82575EB dual-1000baseX Ethernet (SERDES)", |
1131 | WM_T_82575, WMP_F_SERDES }, | | 1131 | WM_T_82575, WMP_F_SERDES }, |
1132 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QUAD_COPPER, | | 1132 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QUAD_COPPER, |
1133 | "82575GB quad-1000baseT Ethernet", | | 1133 | "82575GB quad-1000baseT Ethernet", |
1134 | WM_T_82575, WMP_F_COPPER }, | | 1134 | WM_T_82575, WMP_F_COPPER }, |
1135 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QUAD_COPPER_PM, | | 1135 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QUAD_COPPER_PM, |
1136 | "82575GB quad-1000baseT Ethernet (PM)", | | 1136 | "82575GB quad-1000baseT Ethernet (PM)", |
1137 | WM_T_82575, WMP_F_COPPER }, | | 1137 | WM_T_82575, WMP_F_COPPER }, |
1138 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_COPPER, | | 1138 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_COPPER, |
1139 | "82576 1000BaseT Ethernet", | | 1139 | "82576 1000BaseT Ethernet", |
1140 | WM_T_82576, WMP_F_COPPER }, | | 1140 | WM_T_82576, WMP_F_COPPER }, |
1141 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_FIBER, | | 1141 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_FIBER, |
1142 | "82576 1000BaseX Ethernet", | | 1142 | "82576 1000BaseX Ethernet", |
1143 | WM_T_82576, WMP_F_FIBER }, | | 1143 | WM_T_82576, WMP_F_FIBER }, |
1144 | | | 1144 | |
1145 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES, | | 1145 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES, |
1146 | "82576 gigabit Ethernet (SERDES)", | | 1146 | "82576 gigabit Ethernet (SERDES)", |
1147 | WM_T_82576, WMP_F_SERDES }, | | 1147 | WM_T_82576, WMP_F_SERDES }, |
1148 | | | 1148 | |
1149 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_COPPER, | | 1149 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_COPPER, |
1150 | "82576 quad-1000BaseT Ethernet", | | 1150 | "82576 quad-1000BaseT Ethernet", |
1151 | WM_T_82576, WMP_F_COPPER }, | | 1151 | WM_T_82576, WMP_F_COPPER }, |
1152 | | | 1152 | |
1153 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_COPPER_ET2, | | 1153 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_COPPER_ET2, |
1154 | "82576 Gigabit ET2 Quad Port Server Adapter", | | 1154 | "82576 Gigabit ET2 Quad Port Server Adapter", |
1155 | WM_T_82576, WMP_F_COPPER }, | | 1155 | WM_T_82576, WMP_F_COPPER }, |
1156 | | | 1156 | |
1157 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS, | | 1157 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS, |
1158 | "82576 gigabit Ethernet", | | 1158 | "82576 gigabit Ethernet", |
1159 | WM_T_82576, WMP_F_COPPER }, | | 1159 | WM_T_82576, WMP_F_COPPER }, |
1160 | | | 1160 | |
1161 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS_SERDES, | | 1161 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS_SERDES, |
1162 | "82576 gigabit Ethernet (SERDES)", | | 1162 | "82576 gigabit Ethernet (SERDES)", |
1163 | WM_T_82576, WMP_F_SERDES }, | | 1163 | WM_T_82576, WMP_F_SERDES }, |
1164 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES_QUAD, | | 1164 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES_QUAD, |
1165 | "82576 quad-gigabit Ethernet (SERDES)", | | 1165 | "82576 quad-gigabit Ethernet (SERDES)", |
1166 | WM_T_82576, WMP_F_SERDES }, | | 1166 | WM_T_82576, WMP_F_SERDES }, |
1167 | | | 1167 | |
1168 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER, | | 1168 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER, |
1169 | "82580 1000BaseT Ethernet", | | 1169 | "82580 1000BaseT Ethernet", |
1170 | WM_T_82580, WMP_F_COPPER }, | | 1170 | WM_T_82580, WMP_F_COPPER }, |
1171 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_FIBER, | | 1171 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_FIBER, |
1172 | "82580 1000BaseX Ethernet", | | 1172 | "82580 1000BaseX Ethernet", |
1173 | WM_T_82580, WMP_F_FIBER }, | | 1173 | WM_T_82580, WMP_F_FIBER }, |
1174 | | | 1174 | |
1175 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SERDES, | | 1175 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SERDES, |
1176 | "82580 1000BaseT Ethernet (SERDES)", | | 1176 | "82580 1000BaseT Ethernet (SERDES)", |
1177 | WM_T_82580, WMP_F_SERDES }, | | 1177 | WM_T_82580, WMP_F_SERDES }, |
1178 | | | 1178 | |
1179 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SGMII, | | 1179 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SGMII, |
1180 | "82580 gigabit Ethernet (SGMII)", | | 1180 | "82580 gigabit Ethernet (SGMII)", |
1181 | WM_T_82580, WMP_F_COPPER }, | | 1181 | WM_T_82580, WMP_F_COPPER }, |
1182 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER_DUAL, | | 1182 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER_DUAL, |
1183 | "82580 dual-1000BaseT Ethernet", | | 1183 | "82580 dual-1000BaseT Ethernet", |
1184 | WM_T_82580, WMP_F_COPPER }, | | 1184 | WM_T_82580, WMP_F_COPPER }, |
1185 | | | 1185 | |
1186 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_QUAD_FIBER, | | 1186 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_QUAD_FIBER, |
1187 | "82580 quad-1000BaseX Ethernet", | | 1187 | "82580 quad-1000BaseX Ethernet", |
1188 | WM_T_82580, WMP_F_FIBER }, | | 1188 | WM_T_82580, WMP_F_FIBER }, |
1189 | | | 1189 | |
1190 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SGMII, | | 1190 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SGMII, |
1191 | "DH89XXCC Gigabit Ethernet (SGMII)", | | 1191 | "DH89XXCC Gigabit Ethernet (SGMII)", |
1192 | WM_T_82580, WMP_F_COPPER }, | | 1192 | WM_T_82580, WMP_F_COPPER }, |
1193 | | | 1193 | |
1194 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SERDES, | | 1194 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SERDES, |
1195 | "DH89XXCC Gigabit Ethernet (SERDES)", | | 1195 | "DH89XXCC Gigabit Ethernet (SERDES)", |
1196 | WM_T_82580, WMP_F_SERDES }, | | 1196 | WM_T_82580, WMP_F_SERDES }, |
1197 | | | 1197 | |
1198 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_BPLANE, | | 1198 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_BPLANE, |
1199 | "DH89XXCC 1000BASE-KX Ethernet", | | 1199 | "DH89XXCC 1000BASE-KX Ethernet", |
1200 | WM_T_82580, WMP_F_SERDES }, | | 1200 | WM_T_82580, WMP_F_SERDES }, |
1201 | | | 1201 | |
1202 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SFP, | | 1202 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SFP, |
1203 | "DH89XXCC Gigabit Ethernet (SFP)", | | 1203 | "DH89XXCC Gigabit Ethernet (SFP)", |
1204 | WM_T_82580, WMP_F_SERDES }, | | 1204 | WM_T_82580, WMP_F_SERDES }, |
1205 | | | 1205 | |
1206 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_COPPER, | | 1206 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_COPPER, |
1207 | "I350 Gigabit Network Connection", | | 1207 | "I350 Gigabit Network Connection", |
1208 | WM_T_I350, WMP_F_COPPER }, | | 1208 | WM_T_I350, WMP_F_COPPER }, |
1209 | | | 1209 | |
1210 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_FIBER, | | 1210 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_FIBER, |
1211 | "I350 Gigabit Fiber Network Connection", | | 1211 | "I350 Gigabit Fiber Network Connection", |
1212 | WM_T_I350, WMP_F_FIBER }, | | 1212 | WM_T_I350, WMP_F_FIBER }, |
1213 | | | 1213 | |
1214 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_SERDES, | | 1214 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_SERDES, |
1215 | "I350 Gigabit Backplane Connection", | | 1215 | "I350 Gigabit Backplane Connection", |
1216 | WM_T_I350, WMP_F_SERDES }, | | 1216 | WM_T_I350, WMP_F_SERDES }, |
1217 | | | 1217 | |
1218 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_DA4, | | 1218 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_DA4, |
1219 | "I350 Quad Port Gigabit Ethernet", | | 1219 | "I350 Quad Port Gigabit Ethernet", |
1220 | WM_T_I350, WMP_F_SERDES }, | | 1220 | WM_T_I350, WMP_F_SERDES }, |
1221 | | | 1221 | |
1222 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_SGMII, | | 1222 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_SGMII, |
1223 | "I350 Gigabit Connection", | | 1223 | "I350 Gigabit Connection", |
1224 | WM_T_I350, WMP_F_COPPER }, | | 1224 | WM_T_I350, WMP_F_COPPER }, |
1225 | | | 1225 | |
1226 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_1000KX, | | 1226 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_1000KX, |
1227 | "I354 Gigabit Ethernet (KX)", | | 1227 | "I354 Gigabit Ethernet (KX)", |
1228 | WM_T_I354, WMP_F_SERDES }, | | 1228 | WM_T_I354, WMP_F_SERDES }, |
1229 | | | 1229 | |
1230 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_SGMII, | | 1230 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_SGMII, |
1231 | "I354 Gigabit Ethernet (SGMII)", | | 1231 | "I354 Gigabit Ethernet (SGMII)", |
1232 | WM_T_I354, WMP_F_COPPER }, | | 1232 | WM_T_I354, WMP_F_COPPER }, |
1233 | | | 1233 | |
1234 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_25GBE, | | 1234 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_25GBE, |
1235 | "I354 Gigabit Ethernet (2.5G)", | | 1235 | "I354 Gigabit Ethernet (2.5G)", |
1236 | WM_T_I354, WMP_F_COPPER }, | | 1236 | WM_T_I354, WMP_F_COPPER }, |
1237 | | | 1237 | |
1238 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_T1, | | 1238 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_T1, |
1239 | "I210-T1 Ethernet Server Adapter", | | 1239 | "I210-T1 Ethernet Server Adapter", |
1240 | WM_T_I210, WMP_F_COPPER }, | | 1240 | WM_T_I210, WMP_F_COPPER }, |
1241 | | | 1241 | |
1242 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_OEM1, | | 1242 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_OEM1, |
1243 | "I210 Ethernet (Copper OEM)", | | 1243 | "I210 Ethernet (Copper OEM)", |
1244 | WM_T_I210, WMP_F_COPPER }, | | 1244 | WM_T_I210, WMP_F_COPPER }, |
1245 | | | 1245 | |
1246 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_IT, | | 1246 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_IT, |
1247 | "I210 Ethernet (Copper IT)", | | 1247 | "I210 Ethernet (Copper IT)", |
1248 | WM_T_I210, WMP_F_COPPER }, | | 1248 | WM_T_I210, WMP_F_COPPER }, |
1249 | | | 1249 | |
1250 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_WOF, | | 1250 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_WOF, |
1251 | "I210 Ethernet (FLASH less)", | | 1251 | "I210 Ethernet (FLASH less)", |
1252 | WM_T_I210, WMP_F_COPPER }, | | 1252 | WM_T_I210, WMP_F_COPPER }, |
1253 | | | 1253 | |
1254 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_FIBER, | | 1254 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_FIBER, |
1255 | "I210 Gigabit Ethernet (Fiber)", | | 1255 | "I210 Gigabit Ethernet (Fiber)", |
1256 | WM_T_I210, WMP_F_FIBER }, | | 1256 | WM_T_I210, WMP_F_FIBER }, |
1257 | | | 1257 | |
1258 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SERDES, | | 1258 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SERDES, |
1259 | "I210 Gigabit Ethernet (SERDES)", | | 1259 | "I210 Gigabit Ethernet (SERDES)", |
1260 | WM_T_I210, WMP_F_SERDES }, | | 1260 | WM_T_I210, WMP_F_SERDES }, |
1261 | | | 1261 | |
1262 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SERDES_WOF, | | 1262 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SERDES_WOF, |
1263 | "I210 Gigabit Ethernet (FLASH less)", | | 1263 | "I210 Gigabit Ethernet (FLASH less)", |
1264 | WM_T_I210, WMP_F_SERDES }, | | 1264 | WM_T_I210, WMP_F_SERDES }, |
1265 | | | 1265 | |
1266 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SGMII, | | 1266 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SGMII, |
1267 | "I210 Gigabit Ethernet (SGMII)", | | 1267 | "I210 Gigabit Ethernet (SGMII)", |
1268 | WM_T_I210, WMP_F_COPPER }, | | 1268 | WM_T_I210, WMP_F_COPPER }, |
1269 | | | 1269 | |
1270 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I211_COPPER, | | 1270 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I211_COPPER, |
1271 | "I211 Ethernet (COPPER)", | | 1271 | "I211 Ethernet (COPPER)", |
1272 | WM_T_I211, WMP_F_COPPER }, | | 1272 | WM_T_I211, WMP_F_COPPER }, |
1273 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_V, | | 1273 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_V, |
1274 | "I217 V Ethernet Connection", | | 1274 | "I217 V Ethernet Connection", |
1275 | WM_T_PCH_LPT, WMP_F_COPPER }, | | 1275 | WM_T_PCH_LPT, WMP_F_COPPER }, |
1276 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_LM, | | 1276 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_LM, |
1277 | "I217 LM Ethernet Connection", | | 1277 | "I217 LM Ethernet Connection", |
1278 | WM_T_PCH_LPT, WMP_F_COPPER }, | | 1278 | WM_T_PCH_LPT, WMP_F_COPPER }, |
1279 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V, | | 1279 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V, |
1280 | "I218 V Ethernet Connection", | | 1280 | "I218 V Ethernet Connection", |
1281 | WM_T_PCH_LPT, WMP_F_COPPER }, | | 1281 | WM_T_PCH_LPT, WMP_F_COPPER }, |
1282 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V2, | | 1282 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V2, |
1283 | "I218 V Ethernet Connection", | | 1283 | "I218 V Ethernet Connection", |
1284 | WM_T_PCH_LPT, WMP_F_COPPER }, | | 1284 | WM_T_PCH_LPT, WMP_F_COPPER }, |
1285 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V3, | | 1285 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V3, |
1286 | "I218 V Ethernet Connection", | | 1286 | "I218 V Ethernet Connection", |
1287 | WM_T_PCH_LPT, WMP_F_COPPER }, | | 1287 | WM_T_PCH_LPT, WMP_F_COPPER }, |
1288 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM, | | 1288 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM, |
1289 | "I218 LM Ethernet Connection", | | 1289 | "I218 LM Ethernet Connection", |
1290 | WM_T_PCH_LPT, WMP_F_COPPER }, | | 1290 | WM_T_PCH_LPT, WMP_F_COPPER }, |
1291 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM2, | | 1291 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM2, |
1292 | "I218 LM Ethernet Connection", | | 1292 | "I218 LM Ethernet Connection", |
1293 | WM_T_PCH_LPT, WMP_F_COPPER }, | | 1293 | WM_T_PCH_LPT, WMP_F_COPPER }, |
1294 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM3, | | 1294 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM3, |
1295 | "I218 LM Ethernet Connection", | | 1295 | "I218 LM Ethernet Connection", |
1296 | WM_T_PCH_LPT, WMP_F_COPPER }, | | 1296 | WM_T_PCH_LPT, WMP_F_COPPER }, |
1297 | { 0, 0, | | 1297 | { 0, 0, |
1298 | NULL, | | 1298 | NULL, |
1299 | 0, 0 }, | | 1299 | 0, 0 }, |
1300 | }; | | 1300 | }; |
1301 | | | 1301 | |
1302 | #ifdef WM_EVENT_COUNTERS | | 1302 | #ifdef WM_EVENT_COUNTERS |
1303 | static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")]; | | 1303 | static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")]; |
1304 | #endif /* WM_EVENT_COUNTERS */ | | 1304 | #endif /* WM_EVENT_COUNTERS */ |
1305 | | | 1305 | |
1306 | | | 1306 | |
1307 | /* | | 1307 | /* |
1308 | * Register read/write functions. | | 1308 | * Register read/write functions. |
1309 | * Other than CSR_{READ|WRITE}(). | | 1309 | * Other than CSR_{READ|WRITE}(). |
1310 | */ | | 1310 | */ |
1311 | | | 1311 | |
1312 | #if 0 /* Not currently used */ | | 1312 | #if 0 /* Not currently used */ |
1313 | static inline uint32_t | | 1313 | static inline uint32_t |
1314 | wm_io_read(struct wm_softc *sc, int reg) | | 1314 | wm_io_read(struct wm_softc *sc, int reg) |
1315 | { | | 1315 | { |
1316 | | | 1316 | |
1317 | bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); | | 1317 | bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); |
1318 | return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4)); | | 1318 | return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4)); |
1319 | } | | 1319 | } |
1320 | #endif | | 1320 | #endif |
1321 | | | 1321 | |
1322 | static inline void | | 1322 | static inline void |
1323 | wm_io_write(struct wm_softc *sc, int reg, uint32_t val) | | 1323 | wm_io_write(struct wm_softc *sc, int reg, uint32_t val) |
1324 | { | | 1324 | { |
1325 | | | 1325 | |
1326 | bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); | | 1326 | bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); |
1327 | bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val); | | 1327 | bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val); |
1328 | } | | 1328 | } |
1329 | | | 1329 | |
1330 | static inline void | | 1330 | static inline void |
1331 | wm_82575_write_8bit_ctlr_reg(struct wm_softc *sc, uint32_t reg, uint32_t off, | | 1331 | wm_82575_write_8bit_ctlr_reg(struct wm_softc *sc, uint32_t reg, uint32_t off, |
1332 | uint32_t data) | | 1332 | uint32_t data) |
1333 | { | | 1333 | { |
1334 | uint32_t regval; | | 1334 | uint32_t regval; |
1335 | int i; | | 1335 | int i; |
1336 | | | 1336 | |
1337 | regval = (data & SCTL_CTL_DATA_MASK) | (off << SCTL_CTL_ADDR_SHIFT); | | 1337 | regval = (data & SCTL_CTL_DATA_MASK) | (off << SCTL_CTL_ADDR_SHIFT); |
1338 | | | 1338 | |
1339 | CSR_WRITE(sc, reg, regval); | | 1339 | CSR_WRITE(sc, reg, regval); |
1340 | | | 1340 | |
1341 | for (i = 0; i < SCTL_CTL_POLL_TIMEOUT; i++) { | | 1341 | for (i = 0; i < SCTL_CTL_POLL_TIMEOUT; i++) { |
1342 | delay(5); | | 1342 | delay(5); |
1343 | if (CSR_READ(sc, reg) & SCTL_CTL_READY) | | 1343 | if (CSR_READ(sc, reg) & SCTL_CTL_READY) |
1344 | break; | | 1344 | break; |
1345 | } | | 1345 | } |
1346 | if (i == SCTL_CTL_POLL_TIMEOUT) { | | 1346 | if (i == SCTL_CTL_POLL_TIMEOUT) { |
1347 | aprint_error("%s: WARNING:" | | 1347 | aprint_error("%s: WARNING:" |
1348 | " i82575 reg 0x%08x setup did not indicate ready\n", | | 1348 | " i82575 reg 0x%08x setup did not indicate ready\n", |
1349 | device_xname(sc->sc_dev), reg); | | 1349 | device_xname(sc->sc_dev), reg); |
1350 | } | | 1350 | } |
1351 | } | | 1351 | } |
1352 | | | 1352 | |
1353 | static inline void | | 1353 | static inline void |
1354 | wm_set_dma_addr(volatile wiseman_addr_t *wa, bus_addr_t v) | | 1354 | wm_set_dma_addr(volatile wiseman_addr_t *wa, bus_addr_t v) |
1355 | { | | 1355 | { |
1356 | wa->wa_low = htole32(v & 0xffffffffU); | | 1356 | wa->wa_low = htole32(v & 0xffffffffU); |
1357 | if (sizeof(bus_addr_t) == 8) | | 1357 | if (sizeof(bus_addr_t) == 8) |
1358 | wa->wa_high = htole32((uint64_t) v >> 32); | | 1358 | wa->wa_high = htole32((uint64_t) v >> 32); |
1359 | else | | 1359 | else |
1360 | wa->wa_high = 0; | | 1360 | wa->wa_high = 0; |
1361 | } | | 1361 | } |
1362 | | | 1362 | |
1363 | /* | | 1363 | /* |
1364 | * Descriptor sync/init functions. | | 1364 | * Descriptor sync/init functions. |
1365 | */ | | 1365 | */ |
1366 | static inline void | | 1366 | static inline void |
1367 | wm_cdtxsync(struct wm_softc *sc, int start, int num, int ops) | | 1367 | wm_cdtxsync(struct wm_softc *sc, int start, int num, int ops) |
1368 | { | | 1368 | { |
1369 | struct wm_txqueue *txq = sc->sc_txq; | | 1369 | struct wm_txqueue *txq = sc->sc_txq; |
1370 | | | 1370 | |
1371 | /* If it will wrap around, sync to the end of the ring. */ | | 1371 | /* If it will wrap around, sync to the end of the ring. */ |
1372 | if ((start + num) > WM_NTXDESC(txq)) { | | 1372 | if ((start + num) > WM_NTXDESC(txq)) { |
1373 | bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_dmamap, | | 1373 | bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_dmamap, |
1374 | WM_CDTXOFF(start), sizeof(wiseman_txdesc_t) * | | 1374 | WM_CDTXOFF(start), sizeof(wiseman_txdesc_t) * |
1375 | (WM_NTXDESC(txq) - start), ops); | | 1375 | (WM_NTXDESC(txq) - start), ops); |
1376 | num -= (WM_NTXDESC(txq) - start); | | 1376 | num -= (WM_NTXDESC(txq) - start); |
1377 | start = 0; | | 1377 | start = 0; |
1378 | } | | 1378 | } |
1379 | | | 1379 | |
1380 | /* Now sync whatever is left. */ | | 1380 | /* Now sync whatever is left. */ |
1381 | bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_dmamap, | | 1381 | bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_dmamap, |
1382 | WM_CDTXOFF(start), sizeof(wiseman_txdesc_t) * num, ops); | | 1382 | WM_CDTXOFF(start), sizeof(wiseman_txdesc_t) * num, ops); |
1383 | } | | 1383 | } |
1384 | | | 1384 | |
1385 | static inline void | | 1385 | static inline void |
1386 | wm_cdrxsync(struct wm_softc *sc, int start, int ops) | | 1386 | wm_cdrxsync(struct wm_softc *sc, int start, int ops) |
1387 | { | | 1387 | { |
1388 | struct wm_rxqueue *rxq = sc->sc_rxq; | | 1388 | struct wm_rxqueue *rxq = sc->sc_rxq; |
1389 | | | 1389 | |
1390 | bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_dmamap, | | 1390 | bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_dmamap, |
1391 | WM_CDRXOFF(start), sizeof(wiseman_rxdesc_t), ops); | | 1391 | WM_CDRXOFF(start), sizeof(wiseman_rxdesc_t), ops); |
1392 | } | | 1392 | } |
1393 | | | 1393 | |
1394 | static inline void | | 1394 | static inline void |
1395 | wm_init_rxdesc(struct wm_softc *sc, int start) | | 1395 | wm_init_rxdesc(struct wm_softc *sc, int start) |
1396 | { | | 1396 | { |
1397 | struct wm_rxqueue *rxq = sc->sc_rxq; | | 1397 | struct wm_rxqueue *rxq = sc->sc_rxq; |
1398 | struct wm_rxsoft *rxs = &rxq->rxq_soft[start]; | | 1398 | struct wm_rxsoft *rxs = &rxq->rxq_soft[start]; |
1399 | wiseman_rxdesc_t *rxd = &rxq->rxq_descs[start]; | | 1399 | wiseman_rxdesc_t *rxd = &rxq->rxq_descs[start]; |
1400 | struct mbuf *m = rxs->rxs_mbuf; | | 1400 | struct mbuf *m = rxs->rxs_mbuf; |
1401 | | | 1401 | |
1402 | /* | | 1402 | /* |
1403 | * Note: We scoot the packet forward 2 bytes in the buffer | | 1403 | * Note: We scoot the packet forward 2 bytes in the buffer |
1404 | * so that the payload after the Ethernet header is aligned | | 1404 | * so that the payload after the Ethernet header is aligned |
1405 | * to a 4-byte boundary. | | 1405 | * to a 4-byte boundary. |
1406 | | | 1406 | |
1407 | * XXX BRAINDAMAGE ALERT! | | 1407 | * XXX BRAINDAMAGE ALERT! |
1408 | * The stupid chip uses the same size for every buffer, which | | 1408 | * The stupid chip uses the same size for every buffer, which |
1409 | * is set in the Receive Control register. We are using the 2K | | 1409 | * is set in the Receive Control register. We are using the 2K |
1410 | * size option, but what we REALLY want is (2K - 2)! For this | | 1410 | * size option, but what we REALLY want is (2K - 2)! For this |
1411 | * reason, we can't "scoot" packets longer than the standard | | 1411 | * reason, we can't "scoot" packets longer than the standard |
1412 | * Ethernet MTU. On strict-alignment platforms, if the total | | 1412 | * Ethernet MTU. On strict-alignment platforms, if the total |
1413 | * size exceeds (2K - 2) we set align_tweak to 0 and let | | 1413 | * size exceeds (2K - 2) we set align_tweak to 0 and let |
1414 | * the upper layer copy the headers. | | 1414 | * the upper layer copy the headers. |
1415 | */ | | 1415 | */ |
1416 | m->m_data = m->m_ext.ext_buf + sc->sc_align_tweak; | | 1416 | m->m_data = m->m_ext.ext_buf + sc->sc_align_tweak; |
1417 | | | 1417 | |
1418 | wm_set_dma_addr(&rxd->wrx_addr, | | 1418 | wm_set_dma_addr(&rxd->wrx_addr, |
1419 | rxs->rxs_dmamap->dm_segs[0].ds_addr + sc->sc_align_tweak); | | 1419 | rxs->rxs_dmamap->dm_segs[0].ds_addr + sc->sc_align_tweak); |
1420 | rxd->wrx_len = 0; | | 1420 | rxd->wrx_len = 0; |
1421 | rxd->wrx_cksum = 0; | | 1421 | rxd->wrx_cksum = 0; |
1422 | rxd->wrx_status = 0; | | 1422 | rxd->wrx_status = 0; |
1423 | rxd->wrx_errors = 0; | | 1423 | rxd->wrx_errors = 0; |
1424 | rxd->wrx_special = 0; | | 1424 | rxd->wrx_special = 0; |
1425 | wm_cdrxsync(sc, start, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); | | 1425 | wm_cdrxsync(sc, start, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); |
1426 | | | 1426 | |
1427 | CSR_WRITE(sc, rxq->rxq_rdt_reg, start); | | 1427 | CSR_WRITE(sc, rxq->rxq_rdt_reg, start); |
1428 | } | | 1428 | } |
1429 | | | 1429 | |
1430 | /* | | 1430 | /* |
1431 | * Device driver interface functions and commonly used functions. | | 1431 | * Device driver interface functions and commonly used functions. |
1432 | * match, attach, detach, init, start, stop, ioctl, watchdog and so on. | | 1432 | * match, attach, detach, init, start, stop, ioctl, watchdog and so on. |
1433 | */ | | 1433 | */ |
1434 | | | 1434 | |
1435 | /* Lookup supported device table */ | | 1435 | /* Lookup supported device table */ |
1436 | static const struct wm_product * | | 1436 | static const struct wm_product * |
1437 | wm_lookup(const struct pci_attach_args *pa) | | 1437 | wm_lookup(const struct pci_attach_args *pa) |
1438 | { | | 1438 | { |
1439 | const struct wm_product *wmp; | | 1439 | const struct wm_product *wmp; |
1440 | | | 1440 | |
1441 | for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) { | | 1441 | for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) { |
1442 | if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor && | | 1442 | if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor && |
1443 | PCI_PRODUCT(pa->pa_id) == wmp->wmp_product) | | 1443 | PCI_PRODUCT(pa->pa_id) == wmp->wmp_product) |
1444 | return wmp; | | 1444 | return wmp; |
1445 | } | | 1445 | } |
1446 | return NULL; | | 1446 | return NULL; |
1447 | } | | 1447 | } |
1448 | | | 1448 | |
1449 | /* The match function (ca_match) */ | | 1449 | /* The match function (ca_match) */ |
1450 | static int | | 1450 | static int |
1451 | wm_match(device_t parent, cfdata_t cf, void *aux) | | 1451 | wm_match(device_t parent, cfdata_t cf, void *aux) |
1452 | { | | 1452 | { |
1453 | struct pci_attach_args *pa = aux; | | 1453 | struct pci_attach_args *pa = aux; |
1454 | | | 1454 | |
1455 | if (wm_lookup(pa) != NULL) | | 1455 | if (wm_lookup(pa) != NULL) |
1456 | return 1; | | 1456 | return 1; |
1457 | | | 1457 | |
1458 | return 0; | | 1458 | return 0; |
1459 | } | | 1459 | } |
1460 | | | 1460 | |
1461 | /* The attach function (ca_attach) */ | | 1461 | /* The attach function (ca_attach) */ |
1462 | static void | | 1462 | static void |
1463 | wm_attach(device_t parent, device_t self, void *aux) | | 1463 | wm_attach(device_t parent, device_t self, void *aux) |
1464 | { | | 1464 | { |
1465 | struct wm_softc *sc = device_private(self); | | 1465 | struct wm_softc *sc = device_private(self); |
1466 | struct pci_attach_args *pa = aux; | | 1466 | struct pci_attach_args *pa = aux; |
1467 | prop_dictionary_t dict; | | 1467 | prop_dictionary_t dict; |
1468 | struct ifnet *ifp = &sc->sc_ethercom.ec_if; | | 1468 | struct ifnet *ifp = &sc->sc_ethercom.ec_if; |
1469 | pci_chipset_tag_t pc = pa->pa_pc; | | 1469 | pci_chipset_tag_t pc = pa->pa_pc; |
1470 | #ifndef WM_MSI_MSIX | | 1470 | #ifndef WM_MSI_MSIX |
1471 | pci_intr_handle_t ih; | | 1471 | pci_intr_handle_t ih; |
1472 | #else | | 1472 | #else |
1473 | int counts[PCI_INTR_TYPE_SIZE]; | | 1473 | int counts[PCI_INTR_TYPE_SIZE]; |
1474 | pci_intr_type_t max_type; | | 1474 | pci_intr_type_t max_type; |
1475 | #endif | | 1475 | #endif |
1476 | const char *intrstr = NULL; | | 1476 | const char *intrstr = NULL; |
1477 | const char *eetype, *xname; | | 1477 | const char *eetype, *xname; |
1478 | bus_space_tag_t memt; | | 1478 | bus_space_tag_t memt; |
1479 | bus_space_handle_t memh; | | 1479 | bus_space_handle_t memh; |
1480 | bus_size_t memsize; | | 1480 | bus_size_t memsize; |
1481 | int memh_valid; | | 1481 | int memh_valid; |
1482 | int i, error; | | 1482 | int i, error; |
1483 | const struct wm_product *wmp; | | 1483 | const struct wm_product *wmp; |
1484 | prop_data_t ea; | | 1484 | prop_data_t ea; |
1485 | prop_number_t pn; | | 1485 | prop_number_t pn; |
1486 | uint8_t enaddr[ETHER_ADDR_LEN]; | | 1486 | uint8_t enaddr[ETHER_ADDR_LEN]; |
1487 | uint16_t cfg1, cfg2, swdpin, nvmword; | | 1487 | uint16_t cfg1, cfg2, swdpin, nvmword; |
1488 | pcireg_t preg, memtype; | | 1488 | pcireg_t preg, memtype; |
1489 | uint16_t eeprom_data, apme_mask; | | 1489 | uint16_t eeprom_data, apme_mask; |
1490 | bool force_clear_smbi; | | 1490 | bool force_clear_smbi; |
1491 | uint32_t link_mode; | | 1491 | uint32_t link_mode; |
1492 | uint32_t reg; | | 1492 | uint32_t reg; |
1493 | char intrbuf[PCI_INTRSTR_LEN]; | | 1493 | char intrbuf[PCI_INTRSTR_LEN]; |
1494 | | | 1494 | |
1495 | sc->sc_dev = self; | | 1495 | sc->sc_dev = self; |
1496 | callout_init(&sc->sc_tick_ch, CALLOUT_FLAGS); | | 1496 | callout_init(&sc->sc_tick_ch, CALLOUT_FLAGS); |
1497 | sc->sc_stopping = false; | | 1497 | sc->sc_stopping = false; |
1498 | | | 1498 | |
1499 | wmp = wm_lookup(pa); | | 1499 | wmp = wm_lookup(pa); |
1500 | #ifdef DIAGNOSTIC | | 1500 | #ifdef DIAGNOSTIC |
1501 | if (wmp == NULL) { | | 1501 | if (wmp == NULL) { |
1502 | printf("\n"); | | 1502 | printf("\n"); |
1503 | panic("wm_attach: impossible"); | | 1503 | panic("wm_attach: impossible"); |
1504 | } | | 1504 | } |
1505 | #endif | | 1505 | #endif |
1506 | sc->sc_mediatype = WMP_MEDIATYPE(wmp->wmp_flags); | | 1506 | sc->sc_mediatype = WMP_MEDIATYPE(wmp->wmp_flags); |
1507 | | | 1507 | |
1508 | sc->sc_pc = pa->pa_pc; | | 1508 | sc->sc_pc = pa->pa_pc; |
1509 | sc->sc_pcitag = pa->pa_tag; | | 1509 | sc->sc_pcitag = pa->pa_tag; |
1510 | | | 1510 | |
1511 | if (pci_dma64_available(pa)) | | 1511 | if (pci_dma64_available(pa)) |
1512 | sc->sc_dmat = pa->pa_dmat64; | | 1512 | sc->sc_dmat = pa->pa_dmat64; |
1513 | else | | 1513 | else |
1514 | sc->sc_dmat = pa->pa_dmat; | | 1514 | sc->sc_dmat = pa->pa_dmat; |
1515 | | | 1515 | |
1516 | sc->sc_pcidevid = PCI_PRODUCT(pa->pa_id); | | 1516 | sc->sc_pcidevid = PCI_PRODUCT(pa->pa_id); |
1517 | sc->sc_rev = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); | | 1517 | sc->sc_rev = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); |
1518 | pci_aprint_devinfo_fancy(pa, "Ethernet controller", wmp->wmp_name, 1); | | 1518 | pci_aprint_devinfo_fancy(pa, "Ethernet controller", wmp->wmp_name, 1); |
1519 | | | 1519 | |
1520 | sc->sc_type = wmp->wmp_type; | | 1520 | sc->sc_type = wmp->wmp_type; |
1521 | if (sc->sc_type < WM_T_82543) { | | 1521 | if (sc->sc_type < WM_T_82543) { |
1522 | if (sc->sc_rev < 2) { | | 1522 | if (sc->sc_rev < 2) { |
1523 | aprint_error_dev(sc->sc_dev, | | 1523 | aprint_error_dev(sc->sc_dev, |
1524 | "i82542 must be at least rev. 2\n"); | | 1524 | "i82542 must be at least rev. 2\n"); |
1525 | return; | | 1525 | return; |
1526 | } | | 1526 | } |
1527 | if (sc->sc_rev < 3) | | 1527 | if (sc->sc_rev < 3) |
1528 | sc->sc_type = WM_T_82542_2_0; | | 1528 | sc->sc_type = WM_T_82542_2_0; |
1529 | } | | 1529 | } |
1530 | | | 1530 | |
1531 | /* | | 1531 | /* |
1532 | * Disable MSI for Errata: | | 1532 | * Disable MSI for Errata: |
1533 | * "Message Signaled Interrupt Feature May Corrupt Write Transactions" | | 1533 | * "Message Signaled Interrupt Feature May Corrupt Write Transactions" |
1534 | * | | 1534 | * |
1535 | * 82544: Errata 25 | | 1535 | * 82544: Errata 25 |
1536 | * 82540: Errata 6 (easy to reproduce device timeout) | | 1536 | * 82540: Errata 6 (easy to reproduce device timeout) |
1537 | * 82545: Errata 4 (easy to reproduce device timeout) | | 1537 | * 82545: Errata 4 (easy to reproduce device timeout) |
1538 | * 82546: Errata 26 (easy to reproduce device timeout) | | 1538 | * 82546: Errata 26 (easy to reproduce device timeout) |
1539 | * 82541: Errata 7 (easy to reproduce device timeout) | | 1539 | * 82541: Errata 7 (easy to reproduce device timeout) |
1540 | * | | 1540 | * |
1541 | * "Byte Enables 2 and 3 are not set on MSI writes" | | 1541 | * "Byte Enables 2 and 3 are not set on MSI writes" |
1542 | * | | 1542 | * |
1543 | * 82571 & 82572: Errata 63 | | 1543 | * 82571 & 82572: Errata 63 |
1544 | */ | | 1544 | */ |
1545 | if ((sc->sc_type <= WM_T_82541_2) || (sc->sc_type == WM_T_82571) | | 1545 | if ((sc->sc_type <= WM_T_82541_2) || (sc->sc_type == WM_T_82571) |
1546 | || (sc->sc_type == WM_T_82572)) | | 1546 | || (sc->sc_type == WM_T_82572)) |
1547 | pa->pa_flags &= ~PCI_FLAGS_MSI_OKAY; | | 1547 | pa->pa_flags &= ~PCI_FLAGS_MSI_OKAY; |
1548 | | | 1548 | |
1549 | if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576) | | 1549 | if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576) |
1550 | || (sc->sc_type == WM_T_82580) | | 1550 | || (sc->sc_type == WM_T_82580) |
1551 | || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354) | | 1551 | || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354) |
1552 | || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211)) | | 1552 | || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211)) |
1553 | sc->sc_flags |= WM_F_NEWQUEUE; | | 1553 | sc->sc_flags |= WM_F_NEWQUEUE; |
1554 | | | 1554 | |
1555 | /* Set device properties (mactype) */ | | 1555 | /* Set device properties (mactype) */ |
1556 | dict = device_properties(sc->sc_dev); | | 1556 | dict = device_properties(sc->sc_dev); |
1557 | prop_dictionary_set_uint32(dict, "mactype", sc->sc_type); | | 1557 | prop_dictionary_set_uint32(dict, "mactype", sc->sc_type); |
1558 | | | 1558 | |
1559 | /* | | 1559 | /* |
1560 | * Map the device. All devices support memory-mapped acccess, | | 1560 | * Map the device. All devices support memory-mapped acccess, |
1561 | * and it is really required for normal operation. | | 1561 | * and it is really required for normal operation. |
1562 | */ | | 1562 | */ |
1563 | memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA); | | 1563 | memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA); |
1564 | switch (memtype) { | | 1564 | switch (memtype) { |
1565 | case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: | | 1565 | case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: |
1566 | case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: | | 1566 | case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: |
1567 | memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA, | | 1567 | memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA, |
1568 | memtype, 0, &memt, &memh, NULL, &memsize) == 0); | | 1568 | memtype, 0, &memt, &memh, NULL, &memsize) == 0); |
1569 | break; | | 1569 | break; |
1570 | default: | | 1570 | default: |
1571 | memh_valid = 0; | | 1571 | memh_valid = 0; |
1572 | break; | | 1572 | break; |
1573 | } | | 1573 | } |
1574 | | | 1574 | |
1575 | if (memh_valid) { | | 1575 | if (memh_valid) { |
1576 | sc->sc_st = memt; | | 1576 | sc->sc_st = memt; |
1577 | sc->sc_sh = memh; | | 1577 | sc->sc_sh = memh; |
1578 | sc->sc_ss = memsize; | | 1578 | sc->sc_ss = memsize; |
1579 | } else { | | 1579 | } else { |
1580 | aprint_error_dev(sc->sc_dev, | | 1580 | aprint_error_dev(sc->sc_dev, |
1581 | "unable to map device registers\n"); | | 1581 | "unable to map device registers\n"); |
1582 | return; | | 1582 | return; |
1583 | } | | 1583 | } |
1584 | | | 1584 | |
1585 | /* | | 1585 | /* |
1586 | * In addition, i82544 and later support I/O mapped indirect | | 1586 | * In addition, i82544 and later support I/O mapped indirect |
1587 | * register access. It is not desirable (nor supported in | | 1587 | * register access. It is not desirable (nor supported in |
1588 | * this driver) to use it for normal operation, though it is | | 1588 | * this driver) to use it for normal operation, though it is |
1589 | * required to work around bugs in some chip versions. | | 1589 | * required to work around bugs in some chip versions. |
1590 | */ | | 1590 | */ |
1591 | if (sc->sc_type >= WM_T_82544) { | | 1591 | if (sc->sc_type >= WM_T_82544) { |
1592 | /* First we have to find the I/O BAR. */ | | 1592 | /* First we have to find the I/O BAR. */ |
1593 | for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { | | 1593 | for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { |
1594 | memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, i); | | 1594 | memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, i); |
1595 | if (memtype == PCI_MAPREG_TYPE_IO) | | 1595 | if (memtype == PCI_MAPREG_TYPE_IO) |
1596 | break; | | 1596 | break; |
1597 | if (PCI_MAPREG_MEM_TYPE(memtype) == | | 1597 | if (PCI_MAPREG_MEM_TYPE(memtype) == |
1598 | PCI_MAPREG_MEM_TYPE_64BIT) | | 1598 | PCI_MAPREG_MEM_TYPE_64BIT) |
1599 | i += 4; /* skip high bits, too */ | | 1599 | i += 4; /* skip high bits, too */ |
1600 | } | | 1600 | } |
1601 | if (i < PCI_MAPREG_END) { | | 1601 | if (i < PCI_MAPREG_END) { |
1602 | /* | | 1602 | /* |
1603 | * We found PCI_MAPREG_TYPE_IO. Note that 82580 | | 1603 | * We found PCI_MAPREG_TYPE_IO. Note that 82580 |
1604 | * (and newer?) chip has no PCI_MAPREG_TYPE_IO. | | 1604 | * (and newer?) chip has no PCI_MAPREG_TYPE_IO. |
1605 | * It's no problem because newer chips has no this | | 1605 | * It's no problem because newer chips has no this |
1606 | * bug. | | 1606 | * bug. |
1607 | * | | 1607 | * |
1608 | * The i8254x doesn't apparently respond when the | | 1608 | * The i8254x doesn't apparently respond when the |
1609 | * I/O BAR is 0, which looks somewhat like it's not | | 1609 | * I/O BAR is 0, which looks somewhat like it's not |
1610 | * been configured. | | 1610 | * been configured. |
1611 | */ | | 1611 | */ |
1612 | preg = pci_conf_read(pc, pa->pa_tag, i); | | 1612 | preg = pci_conf_read(pc, pa->pa_tag, i); |
1613 | if (PCI_MAPREG_MEM_ADDR(preg) == 0) { | | 1613 | if (PCI_MAPREG_MEM_ADDR(preg) == 0) { |
1614 | aprint_error_dev(sc->sc_dev, | | 1614 | aprint_error_dev(sc->sc_dev, |
1615 | "WARNING: I/O BAR at zero.\n"); | | 1615 | "WARNING: I/O BAR at zero.\n"); |
1616 | } else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO, | | 1616 | } else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO, |
1617 | 0, &sc->sc_iot, &sc->sc_ioh, | | 1617 | 0, &sc->sc_iot, &sc->sc_ioh, |
1618 | NULL, &sc->sc_ios) == 0) { | | 1618 | NULL, &sc->sc_ios) == 0) { |
1619 | sc->sc_flags |= WM_F_IOH_VALID; | | 1619 | sc->sc_flags |= WM_F_IOH_VALID; |
1620 | } else { | | 1620 | } else { |
1621 | aprint_error_dev(sc->sc_dev, | | 1621 | aprint_error_dev(sc->sc_dev, |
1622 | "WARNING: unable to map I/O space\n"); | | 1622 | "WARNING: unable to map I/O space\n"); |
1623 | } | | 1623 | } |
1624 | } | | 1624 | } |
1625 | | | 1625 | |
1626 | } | | 1626 | } |
1627 | | | 1627 | |
1628 | /* Enable bus mastering. Disable MWI on the i82542 2.0. */ | | 1628 | /* Enable bus mastering. Disable MWI on the i82542 2.0. */ |
1629 | preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); | | 1629 | preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); |
1630 | preg |= PCI_COMMAND_MASTER_ENABLE; | | 1630 | preg |= PCI_COMMAND_MASTER_ENABLE; |
1631 | if (sc->sc_type < WM_T_82542_2_1) | | 1631 | if (sc->sc_type < WM_T_82542_2_1) |
1632 | preg &= ~PCI_COMMAND_INVALIDATE_ENABLE; | | 1632 | preg &= ~PCI_COMMAND_INVALIDATE_ENABLE; |
1633 | pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); | | 1633 | pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); |
1634 | | | 1634 | |
1635 | /* power up chip */ | | 1635 | /* power up chip */ |
1636 | if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, | | 1636 | if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, |
1637 | NULL)) && error != EOPNOTSUPP) { | | 1637 | NULL)) && error != EOPNOTSUPP) { |
1638 | aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); | | 1638 | aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); |
1639 | return; | | 1639 | return; |
1640 | } | | 1640 | } |
1641 | | | 1641 | |
| | | 1642 | /* XXX Currently, Tx, Rx queue are always one. */ |
| | | 1643 | sc->sc_nrxqueues = 1; |
| | | 1644 | sc->sc_ntxqueues = 1; |
| | | 1645 | error = wm_alloc_txrx_queues(sc); |
| | | 1646 | if (error) |
| | | 1647 | return; |
| | | 1648 | |
1642 | #ifndef WM_MSI_MSIX | | 1649 | #ifndef WM_MSI_MSIX |
1643 | /* | | 1650 | /* |
1644 | * Map and establish our interrupt. | | 1651 | * Map and establish our interrupt. |
1645 | */ | | 1652 | */ |
1646 | if (pci_intr_map(pa, &ih)) { | | 1653 | if (pci_intr_map(pa, &ih)) { |
1647 | aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); | | 1654 | aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); |
1648 | return; | | 1655 | return; |
1649 | } | | 1656 | } |
1650 | intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); | | 1657 | intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); |
1651 | #ifdef WM_MPSAFE | | 1658 | #ifdef WM_MPSAFE |
1652 | pci_intr_setattr(pc, &ih, PCI_INTR_MPSAFE, true); | | 1659 | pci_intr_setattr(pc, &ih, PCI_INTR_MPSAFE, true); |
1653 | #endif | | 1660 | #endif |
1654 | sc->sc_ihs[0] = pci_intr_establish_xname(pc, ih, IPL_NET, | | 1661 | sc->sc_ihs[0] = pci_intr_establish_xname(pc, ih, IPL_NET, |
1655 | wm_intr_legacy, sc, device_xname(sc->sc_dev)); | | 1662 | wm_intr_legacy, sc, device_xname(sc->sc_dev)); |
1656 | if (sc->sc_ihs[0] == NULL) { | | 1663 | if (sc->sc_ihs[0] == NULL) { |
1657 | aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); | | 1664 | aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); |
1658 | if (intrstr != NULL) | | 1665 | if (intrstr != NULL) |
1659 | aprint_error(" at %s", intrstr); | | 1666 | aprint_error(" at %s", intrstr); |
1660 | aprint_error("\n"); | | 1667 | aprint_error("\n"); |
1661 | return; | | 1668 | return; |
1662 | } | | 1669 | } |
1663 | aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); | | 1670 | aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); |
1664 | sc->sc_nintrs = 1; | | 1671 | sc->sc_nintrs = 1; |
1665 | #else /* WM_MSI_MSIX */ | | 1672 | #else /* WM_MSI_MSIX */ |
1666 | /* Allocation settings */ | | 1673 | /* Allocation settings */ |
1667 | max_type = PCI_INTR_TYPE_MSIX; | | 1674 | max_type = PCI_INTR_TYPE_MSIX; |
1668 | counts[PCI_INTR_TYPE_MSIX] = WM_MAX_NINTR; | | 1675 | counts[PCI_INTR_TYPE_MSIX] = WM_MAX_NINTR; |
1669 | counts[PCI_INTR_TYPE_MSI] = 1; | | 1676 | counts[PCI_INTR_TYPE_MSI] = 1; |
1670 | counts[PCI_INTR_TYPE_INTX] = 1; | | 1677 | counts[PCI_INTR_TYPE_INTX] = 1; |
1671 | | | 1678 | |
1672 | alloc_retry: | | 1679 | alloc_retry: |
1673 | if (pci_intr_alloc(pa, &sc->sc_intrs, counts, max_type) != 0) { | | 1680 | if (pci_intr_alloc(pa, &sc->sc_intrs, counts, max_type) != 0) { |
1674 | aprint_error_dev(sc->sc_dev, "failed to allocate interrupt\n"); | | 1681 | aprint_error_dev(sc->sc_dev, "failed to allocate interrupt\n"); |
1675 | return; | | 1682 | return; |
1676 | } | | 1683 | } |
1677 | | | 1684 | |
1678 | if (pci_intr_type(sc->sc_intrs[0]) == PCI_INTR_TYPE_MSIX) { | | 1685 | if (pci_intr_type(sc->sc_intrs[0]) == PCI_INTR_TYPE_MSIX) { |
1679 | void *vih; | | 1686 | void *vih; |
1680 | kcpuset_t *affinity; | | 1687 | kcpuset_t *affinity; |
1681 | char intr_xname[INTRDEVNAMEBUF]; | | 1688 | char intr_xname[INTRDEVNAMEBUF]; |
1682 | | | 1689 | |
1683 | kcpuset_create(&affinity, false); | | 1690 | kcpuset_create(&affinity, false); |
1684 | | | 1691 | |
1685 | for (i = 0; i < WM_MSIX_NINTR; i++) { | | 1692 | for (i = 0; i < WM_MSIX_NINTR; i++) { |
1686 | intrstr = pci_intr_string(pc, | | 1693 | intrstr = pci_intr_string(pc, |
1687 | sc->sc_intrs[msix_matrix[i].intridx], intrbuf, | | 1694 | sc->sc_intrs[msix_matrix[i].intridx], intrbuf, |
1688 | sizeof(intrbuf)); | | 1695 | sizeof(intrbuf)); |
1689 | #ifdef WM_MPSAFE | | 1696 | #ifdef WM_MPSAFE |
1690 | pci_intr_setattr(pc, | | 1697 | pci_intr_setattr(pc, |
1691 | &sc->sc_intrs[msix_matrix[i].intridx], | | 1698 | &sc->sc_intrs[msix_matrix[i].intridx], |
1692 | PCI_INTR_MPSAFE, true); | | 1699 | PCI_INTR_MPSAFE, true); |
1693 | #endif | | 1700 | #endif |
1694 | memset(intr_xname, 0, sizeof(intr_xname)); | | 1701 | memset(intr_xname, 0, sizeof(intr_xname)); |
1695 | strlcat(intr_xname, device_xname(sc->sc_dev), | | 1702 | strlcat(intr_xname, device_xname(sc->sc_dev), |
1696 | sizeof(intr_xname)); | | 1703 | sizeof(intr_xname)); |
1697 | strlcat(intr_xname, msix_matrix[i].intrname, | | 1704 | strlcat(intr_xname, msix_matrix[i].intrname, |
1698 | sizeof(intr_xname)); | | 1705 | sizeof(intr_xname)); |
1699 | vih = pci_intr_establish_xname(pc, | | 1706 | vih = pci_intr_establish_xname(pc, |
1700 | sc->sc_intrs[msix_matrix[i].intridx], IPL_NET, | | 1707 | sc->sc_intrs[msix_matrix[i].intridx], IPL_NET, |
1701 | msix_matrix[i].func, sc, intr_xname); | | 1708 | msix_matrix[i].func, sc, intr_xname); |
1702 | if (vih == NULL) { | | 1709 | if (vih == NULL) { |
1703 | aprint_error_dev(sc->sc_dev, | | 1710 | aprint_error_dev(sc->sc_dev, |
1704 | "unable to establish MSI-X(for %s)%s%s\n", | | 1711 | "unable to establish MSI-X(for %s)%s%s\n", |
1705 | msix_matrix[i].intrname, | | 1712 | msix_matrix[i].intrname, |
1706 | intrstr ? " at " : "", | | 1713 | intrstr ? " at " : "", |
1707 | intrstr ? intrstr : ""); | | 1714 | intrstr ? intrstr : ""); |
1708 | pci_intr_release(sc->sc_pc, sc->sc_intrs, | | 1715 | pci_intr_release(sc->sc_pc, sc->sc_intrs, |
1709 | WM_MSIX_NINTR); | | 1716 | WM_MSIX_NINTR); |
1710 | kcpuset_destroy(affinity); | | 1717 | kcpuset_destroy(affinity); |
1711 | | | 1718 | |
1712 | /* Setup for MSI: Disable MSI-X */ | | 1719 | /* Setup for MSI: Disable MSI-X */ |
1713 | max_type = PCI_INTR_TYPE_MSI; | | 1720 | max_type = PCI_INTR_TYPE_MSI; |
1714 | counts[PCI_INTR_TYPE_MSI] = 1; | | 1721 | counts[PCI_INTR_TYPE_MSI] = 1; |
1715 | counts[PCI_INTR_TYPE_INTX] = 1; | | 1722 | counts[PCI_INTR_TYPE_INTX] = 1; |
1716 | goto alloc_retry; | | 1723 | goto alloc_retry; |
1717 | } | | 1724 | } |
1718 | kcpuset_zero(affinity); | | 1725 | kcpuset_zero(affinity); |
1719 | /* Round-robin affinity */ | | 1726 | /* Round-robin affinity */ |
1720 | kcpuset_set(affinity, msix_matrix[i].cpuid % ncpu); | | 1727 | kcpuset_set(affinity, msix_matrix[i].cpuid % ncpu); |
1721 | error = interrupt_distribute(vih, affinity, NULL); | | 1728 | error = interrupt_distribute(vih, affinity, NULL); |
1722 | if (error == 0) { | | 1729 | if (error == 0) { |
1723 | aprint_normal_dev(sc->sc_dev, | | 1730 | aprint_normal_dev(sc->sc_dev, |
1724 | "for %s interrupting at %s affinity to %u\n", | | 1731 | "for %s interrupting at %s affinity to %u\n", |
1725 | msix_matrix[i].intrname, intrstr, | | 1732 | msix_matrix[i].intrname, intrstr, |
1726 | msix_matrix[i].cpuid % ncpu); | | 1733 | msix_matrix[i].cpuid % ncpu); |
1727 | } else { | | 1734 | } else { |
1728 | aprint_normal_dev(sc->sc_dev, | | 1735 | aprint_normal_dev(sc->sc_dev, |
1729 | "for %s interrupting at %s\n", | | 1736 | "for %s interrupting at %s\n", |
1730 | msix_matrix[i].intrname, intrstr); | | 1737 | msix_matrix[i].intrname, intrstr); |
1731 | } | | 1738 | } |
1732 | sc->sc_ihs[msix_matrix[i].intridx] = vih; | | 1739 | sc->sc_ihs[msix_matrix[i].intridx] = vih; |
1733 | } | | 1740 | } |
1734 | | | 1741 | |
1735 | sc->sc_nintrs = WM_MSIX_NINTR; | | 1742 | sc->sc_nintrs = WM_MSIX_NINTR; |
1736 | kcpuset_destroy(affinity); | | 1743 | kcpuset_destroy(affinity); |
1737 | } else { | | 1744 | } else { |
1738 | /* MSI or INTx */ | | 1745 | /* MSI or INTx */ |
1739 | intrstr = pci_intr_string(pc, sc->sc_intrs[0], intrbuf, | | 1746 | intrstr = pci_intr_string(pc, sc->sc_intrs[0], intrbuf, |
1740 | sizeof(intrbuf)); | | 1747 | sizeof(intrbuf)); |
1741 | #ifdef WM_MPSAFE | | 1748 | #ifdef WM_MPSAFE |
1742 | pci_intr_setattr(pc, &sc->sc_intrs[0], PCI_INTR_MPSAFE, true); | | 1749 | pci_intr_setattr(pc, &sc->sc_intrs[0], PCI_INTR_MPSAFE, true); |
1743 | #endif | | 1750 | #endif |
1744 | sc->sc_ihs[0] = pci_intr_establish_xname(pc, sc->sc_intrs[0], | | 1751 | sc->sc_ihs[0] = pci_intr_establish_xname(pc, sc->sc_intrs[0], |
1745 | IPL_NET, wm_intr_legacy, sc, device_xname(sc->sc_dev)); | | 1752 | IPL_NET, wm_intr_legacy, sc, device_xname(sc->sc_dev)); |
1746 | if (sc->sc_ihs[0] == NULL) { | | 1753 | if (sc->sc_ihs[0] == NULL) { |
1747 | aprint_error_dev(sc->sc_dev,"unable to establish %s\n", | | 1754 | aprint_error_dev(sc->sc_dev,"unable to establish %s\n", |
1748 | (pci_intr_type(sc->sc_intrs[0]) | | 1755 | (pci_intr_type(sc->sc_intrs[0]) |
1749 | == PCI_INTR_TYPE_MSI) ? "MSI" : "INTx"); | | 1756 | == PCI_INTR_TYPE_MSI) ? "MSI" : "INTx"); |
1750 | pci_intr_release(sc->sc_pc, sc->sc_intrs, 1); | | 1757 | pci_intr_release(sc->sc_pc, sc->sc_intrs, 1); |
1751 | switch (pci_intr_type(sc->sc_intrs[0])) { | | 1758 | switch (pci_intr_type(sc->sc_intrs[0])) { |
1752 | case PCI_INTR_TYPE_MSI: | | 1759 | case PCI_INTR_TYPE_MSI: |
1753 | /* The next try is for INTx: Disable MSI */ | | 1760 | /* The next try is for INTx: Disable MSI */ |
1754 | max_type = PCI_INTR_TYPE_INTX; | | 1761 | max_type = PCI_INTR_TYPE_INTX; |
1755 | counts[PCI_INTR_TYPE_INTX] = 1; | | 1762 | counts[PCI_INTR_TYPE_INTX] = 1; |
1756 | goto alloc_retry; | | 1763 | goto alloc_retry; |
1757 | case PCI_INTR_TYPE_INTX: | | 1764 | case PCI_INTR_TYPE_INTX: |
1758 | default: | | 1765 | default: |
1759 | return; | | 1766 | return; |
1760 | } | | 1767 | } |
1761 | } | | 1768 | } |
1762 | aprint_normal_dev(sc->sc_dev, "%s at %s\n", | | 1769 | aprint_normal_dev(sc->sc_dev, "%s at %s\n", |
1763 | (pci_intr_type(sc->sc_intrs[0]) == PCI_INTR_TYPE_MSI) | | 1770 | (pci_intr_type(sc->sc_intrs[0]) == PCI_INTR_TYPE_MSI) |
1764 | ? "MSI" : "interrupting", intrstr); | | 1771 | ? "MSI" : "interrupting", intrstr); |
1765 | | | 1772 | |
1766 | sc->sc_nintrs = 1; | | 1773 | sc->sc_nintrs = 1; |
1767 | } | | 1774 | } |
1768 | #endif /* WM_MSI_MSIX */ | | 1775 | #endif /* WM_MSI_MSIX */ |
1769 | | | 1776 | |
1770 | /* | | 1777 | /* |
1771 | * Check the function ID (unit number of the chip). | | 1778 | * Check the function ID (unit number of the chip). |
1772 | */ | | 1779 | */ |
1773 | if ((sc->sc_type == WM_T_82546) || (sc->sc_type == WM_T_82546_3) | | 1780 | if ((sc->sc_type == WM_T_82546) || (sc->sc_type == WM_T_82546_3) |
1774 | || (sc->sc_type == WM_T_82571) || (sc->sc_type == WM_T_80003) | | 1781 | || (sc->sc_type == WM_T_82571) || (sc->sc_type == WM_T_80003) |
1775 | || (sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576) | | 1782 | || (sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576) |
1776 | || (sc->sc_type == WM_T_82580) | | 1783 | || (sc->sc_type == WM_T_82580) |
1777 | || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)) | | 1784 | || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)) |
1778 | sc->sc_funcid = (CSR_READ(sc, WMREG_STATUS) | | 1785 | sc->sc_funcid = (CSR_READ(sc, WMREG_STATUS) |
1779 | >> STATUS_FUNCID_SHIFT) & STATUS_FUNCID_MASK; | | 1786 | >> STATUS_FUNCID_SHIFT) & STATUS_FUNCID_MASK; |
1780 | else | | 1787 | else |
1781 | sc->sc_funcid = 0; | | 1788 | sc->sc_funcid = 0; |
1782 | | | 1789 | |
1783 | /* | | 1790 | /* |
1784 | * Determine a few things about the bus we're connected to. | | 1791 | * Determine a few things about the bus we're connected to. |
1785 | */ | | 1792 | */ |
1786 | if (sc->sc_type < WM_T_82543) { | | 1793 | if (sc->sc_type < WM_T_82543) { |
1787 | /* We don't really know the bus characteristics here. */ | | 1794 | /* We don't really know the bus characteristics here. */ |
1788 | sc->sc_bus_speed = 33; | | 1795 | sc->sc_bus_speed = 33; |
1789 | } else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) { | | 1796 | } else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) { |
1790 | /* | | 1797 | /* |
1791 | * CSA (Communication Streaming Architecture) is about as fast | | 1798 | * CSA (Communication Streaming Architecture) is about as fast |
1792 | * a 32-bit 66MHz PCI Bus. | | 1799 | * a 32-bit 66MHz PCI Bus. |
1793 | */ | | 1800 | */ |
1794 | sc->sc_flags |= WM_F_CSA; | | 1801 | sc->sc_flags |= WM_F_CSA; |
1795 | sc->sc_bus_speed = 66; | | 1802 | sc->sc_bus_speed = 66; |
1796 | aprint_verbose_dev(sc->sc_dev, | | 1803 | aprint_verbose_dev(sc->sc_dev, |
1797 | "Communication Streaming Architecture\n"); | | 1804 | "Communication Streaming Architecture\n"); |
1798 | if (sc->sc_type == WM_T_82547) { | | 1805 | if (sc->sc_type == WM_T_82547) { |
1799 | callout_init(&sc->sc_txfifo_ch, CALLOUT_FLAGS); | | 1806 | callout_init(&sc->sc_txfifo_ch, CALLOUT_FLAGS); |
1800 | callout_setfunc(&sc->sc_txfifo_ch, | | 1807 | callout_setfunc(&sc->sc_txfifo_ch, |
1801 | wm_82547_txfifo_stall, sc); | | 1808 | wm_82547_txfifo_stall, sc); |
1802 | aprint_verbose_dev(sc->sc_dev, | | 1809 | aprint_verbose_dev(sc->sc_dev, |
1803 | "using 82547 Tx FIFO stall work-around\n"); | | 1810 | "using 82547 Tx FIFO stall work-around\n"); |
1804 | } | | 1811 | } |
1805 | } else if (sc->sc_type >= WM_T_82571) { | | 1812 | } else if (sc->sc_type >= WM_T_82571) { |
1806 | sc->sc_flags |= WM_F_PCIE; | | 1813 | sc->sc_flags |= WM_F_PCIE; |
1807 | if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9) | | 1814 | if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9) |
1808 | && (sc->sc_type != WM_T_ICH10) | | 1815 | && (sc->sc_type != WM_T_ICH10) |
1809 | && (sc->sc_type != WM_T_PCH) | | 1816 | && (sc->sc_type != WM_T_PCH) |
1810 | && (sc->sc_type != WM_T_PCH2) | | 1817 | && (sc->sc_type != WM_T_PCH2) |
1811 | && (sc->sc_type != WM_T_PCH_LPT)) { | | 1818 | && (sc->sc_type != WM_T_PCH_LPT)) { |
1812 | /* ICH* and PCH* have no PCIe capability registers */ | | 1819 | /* ICH* and PCH* have no PCIe capability registers */ |
1813 | if (pci_get_capability(pa->pa_pc, pa->pa_tag, | | 1820 | if (pci_get_capability(pa->pa_pc, pa->pa_tag, |
1814 | PCI_CAP_PCIEXPRESS, &sc->sc_pcixe_capoff, | | 1821 | PCI_CAP_PCIEXPRESS, &sc->sc_pcixe_capoff, |
1815 | NULL) == 0) | | 1822 | NULL) == 0) |
1816 | aprint_error_dev(sc->sc_dev, | | 1823 | aprint_error_dev(sc->sc_dev, |
1817 | "unable to find PCIe capability\n"); | | 1824 | "unable to find PCIe capability\n"); |
1818 | } | | 1825 | } |
1819 | aprint_verbose_dev(sc->sc_dev, "PCI-Express bus\n"); | | 1826 | aprint_verbose_dev(sc->sc_dev, "PCI-Express bus\n"); |
1820 | } else { | | 1827 | } else { |
1821 | reg = CSR_READ(sc, WMREG_STATUS); | | 1828 | reg = CSR_READ(sc, WMREG_STATUS); |
1822 | if (reg & STATUS_BUS64) | | 1829 | if (reg & STATUS_BUS64) |
1823 | sc->sc_flags |= WM_F_BUS64; | | 1830 | sc->sc_flags |= WM_F_BUS64; |
1824 | if ((reg & STATUS_PCIX_MODE) != 0) { | | 1831 | if ((reg & STATUS_PCIX_MODE) != 0) { |
1825 | pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb; | | 1832 | pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb; |
1826 | | | 1833 | |
1827 | sc->sc_flags |= WM_F_PCIX; | | 1834 | sc->sc_flags |= WM_F_PCIX; |
1828 | if (pci_get_capability(pa->pa_pc, pa->pa_tag, | | 1835 | if (pci_get_capability(pa->pa_pc, pa->pa_tag, |
1829 | PCI_CAP_PCIX, &sc->sc_pcixe_capoff, NULL) == 0) | | 1836 | PCI_CAP_PCIX, &sc->sc_pcixe_capoff, NULL) == 0) |
1830 | aprint_error_dev(sc->sc_dev, | | 1837 | aprint_error_dev(sc->sc_dev, |
1831 | "unable to find PCIX capability\n"); | | 1838 | "unable to find PCIX capability\n"); |
1832 | else if (sc->sc_type != WM_T_82545_3 && | | 1839 | else if (sc->sc_type != WM_T_82545_3 && |
1833 | sc->sc_type != WM_T_82546_3) { | | 1840 | sc->sc_type != WM_T_82546_3) { |
1834 | /* | | 1841 | /* |
1835 | * Work around a problem caused by the BIOS | | 1842 | * Work around a problem caused by the BIOS |
1836 | * setting the max memory read byte count | | 1843 | * setting the max memory read byte count |
1837 | * incorrectly. | | 1844 | * incorrectly. |
1838 | */ | | 1845 | */ |
1839 | pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, | | 1846 | pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, |
1840 | sc->sc_pcixe_capoff + PCIX_CMD); | | 1847 | sc->sc_pcixe_capoff + PCIX_CMD); |
1841 | pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag, | | 1848 | pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag, |
1842 | sc->sc_pcixe_capoff + PCIX_STATUS); | | 1849 | sc->sc_pcixe_capoff + PCIX_STATUS); |
1843 | | | 1850 | |
1844 | bytecnt = | | 1851 | bytecnt = |
1845 | (pcix_cmd & PCIX_CMD_BYTECNT_MASK) >> | | 1852 | (pcix_cmd & PCIX_CMD_BYTECNT_MASK) >> |
1846 | PCIX_CMD_BYTECNT_SHIFT; | | 1853 | PCIX_CMD_BYTECNT_SHIFT; |
1847 | maxb = | | 1854 | maxb = |
1848 | (pcix_sts & PCIX_STATUS_MAXB_MASK) >> | | 1855 | (pcix_sts & PCIX_STATUS_MAXB_MASK) >> |
1849 | PCIX_STATUS_MAXB_SHIFT; | | 1856 | PCIX_STATUS_MAXB_SHIFT; |
1850 | if (bytecnt > maxb) { | | 1857 | if (bytecnt > maxb) { |
1851 | aprint_verbose_dev(sc->sc_dev, | | 1858 | aprint_verbose_dev(sc->sc_dev, |
1852 | "resetting PCI-X MMRBC: %d -> %d\n", | | 1859 | "resetting PCI-X MMRBC: %d -> %d\n", |
1853 | 512 << bytecnt, 512 << maxb); | | 1860 | 512 << bytecnt, 512 << maxb); |
1854 | pcix_cmd = (pcix_cmd & | | 1861 | pcix_cmd = (pcix_cmd & |
1855 | ~PCIX_CMD_BYTECNT_MASK) | | | 1862 | ~PCIX_CMD_BYTECNT_MASK) | |
1856 | (maxb << PCIX_CMD_BYTECNT_SHIFT); | | 1863 | (maxb << PCIX_CMD_BYTECNT_SHIFT); |
1857 | pci_conf_write(pa->pa_pc, pa->pa_tag, | | 1864 | pci_conf_write(pa->pa_pc, pa->pa_tag, |
1858 | sc->sc_pcixe_capoff + PCIX_CMD, | | 1865 | sc->sc_pcixe_capoff + PCIX_CMD, |
1859 | pcix_cmd); | | 1866 | pcix_cmd); |
1860 | } | | 1867 | } |
1861 | } | | 1868 | } |
1862 | } | | 1869 | } |
1863 | /* | | 1870 | /* |
1864 | * The quad port adapter is special; it has a PCIX-PCIX | | 1871 | * The quad port adapter is special; it has a PCIX-PCIX |
1865 | * bridge on the board, and can run the secondary bus at | | 1872 | * bridge on the board, and can run the secondary bus at |
1866 | * a higher speed. | | 1873 | * a higher speed. |
1867 | */ | | 1874 | */ |
1868 | if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) { | | 1875 | if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) { |
1869 | sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120 | | 1876 | sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120 |
1870 | : 66; | | 1877 | : 66; |
1871 | } else if (sc->sc_flags & WM_F_PCIX) { | | 1878 | } else if (sc->sc_flags & WM_F_PCIX) { |
1872 | switch (reg & STATUS_PCIXSPD_MASK) { | | 1879 | switch (reg & STATUS_PCIXSPD_MASK) { |
1873 | case STATUS_PCIXSPD_50_66: | | 1880 | case STATUS_PCIXSPD_50_66: |
1874 | sc->sc_bus_speed = 66; | | 1881 | sc->sc_bus_speed = 66; |
1875 | break; | | 1882 | break; |
1876 | case STATUS_PCIXSPD_66_100: | | 1883 | case STATUS_PCIXSPD_66_100: |
1877 | sc->sc_bus_speed = 100; | | 1884 | sc->sc_bus_speed = 100; |
1878 | break; | | 1885 | break; |
1879 | case STATUS_PCIXSPD_100_133: | | 1886 | case STATUS_PCIXSPD_100_133: |
1880 | sc->sc_bus_speed = 133; | | 1887 | sc->sc_bus_speed = 133; |
1881 | break; | | 1888 | break; |
1882 | default: | | 1889 | default: |
1883 | aprint_error_dev(sc->sc_dev, | | 1890 | aprint_error_dev(sc->sc_dev, |
1884 | "unknown PCIXSPD %d; assuming 66MHz\n", | | 1891 | "unknown PCIXSPD %d; assuming 66MHz\n", |
1885 | reg & STATUS_PCIXSPD_MASK); | | 1892 | reg & STATUS_PCIXSPD_MASK); |
1886 | sc->sc_bus_speed = 66; | | 1893 | sc->sc_bus_speed = 66; |
1887 | break; | | 1894 | break; |
1888 | } | | 1895 | } |
1889 | } else | | 1896 | } else |
1890 | sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33; | | 1897 | sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33; |
1891 | aprint_verbose_dev(sc->sc_dev, "%d-bit %dMHz %s bus\n", | | 1898 | aprint_verbose_dev(sc->sc_dev, "%d-bit %dMHz %s bus\n", |
1892 | (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed, | | 1899 | (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed, |
1893 | (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI"); | | 1900 | (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI"); |
1894 | } | | 1901 | } |
1895 | | | 1902 | |
1896 | /* XXX Currently, Tx, Rx queue are always one. */ | | | |
1897 | sc->sc_nrxqueues = 1; | | | |
1898 | sc->sc_ntxqueues = 1; | | | |
1899 | error = wm_alloc_txrx_queues(sc); | | | |
1900 | if (error) | | | |
1901 | return; | | | |
1902 | | | | |
1903 | /* clear interesting stat counters */ | | 1903 | /* clear interesting stat counters */ |
1904 | CSR_READ(sc, WMREG_COLC); | | 1904 | CSR_READ(sc, WMREG_COLC); |
1905 | CSR_READ(sc, WMREG_RXERRC); | | 1905 | CSR_READ(sc, WMREG_RXERRC); |
1906 | | | 1906 | |
1907 | /* get PHY control from SMBus to PCIe */ | | 1907 | /* get PHY control from SMBus to PCIe */ |
1908 | if ((sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2) | | 1908 | if ((sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2) |
1909 | || (sc->sc_type == WM_T_PCH_LPT)) | | 1909 | || (sc->sc_type == WM_T_PCH_LPT)) |
1910 | wm_smbustopci(sc); | | 1910 | wm_smbustopci(sc); |
1911 | | | 1911 | |
1912 | /* Reset the chip to a known state. */ | | 1912 | /* Reset the chip to a known state. */ |
1913 | wm_reset(sc); | | 1913 | wm_reset(sc); |
1914 | | | 1914 | |
1915 | /* Get some information about the EEPROM. */ | | 1915 | /* Get some information about the EEPROM. */ |
1916 | switch (sc->sc_type) { | | 1916 | switch (sc->sc_type) { |
1917 | case WM_T_82542_2_0: | | 1917 | case WM_T_82542_2_0: |
1918 | case WM_T_82542_2_1: | | 1918 | case WM_T_82542_2_1: |
1919 | case WM_T_82543: | | 1919 | case WM_T_82543: |
1920 | case WM_T_82544: | | 1920 | case WM_T_82544: |
1921 | /* Microwire */ | | 1921 | /* Microwire */ |
1922 | sc->sc_nvm_wordsize = 64; | | 1922 | sc->sc_nvm_wordsize = 64; |
1923 | sc->sc_nvm_addrbits = 6; | | 1923 | sc->sc_nvm_addrbits = 6; |
1924 | break; | | 1924 | break; |
1925 | case WM_T_82540: | | 1925 | case WM_T_82540: |
1926 | case WM_T_82545: | | 1926 | case WM_T_82545: |
1927 | case WM_T_82545_3: | | 1927 | case WM_T_82545_3: |
1928 | case WM_T_82546: | | 1928 | case WM_T_82546: |
1929 | case WM_T_82546_3: | | 1929 | case WM_T_82546_3: |
1930 | /* Microwire */ | | 1930 | /* Microwire */ |
1931 | reg = CSR_READ(sc, WMREG_EECD); | | 1931 | reg = CSR_READ(sc, WMREG_EECD); |
1932 | if (reg & EECD_EE_SIZE) { | | 1932 | if (reg & EECD_EE_SIZE) { |
1933 | sc->sc_nvm_wordsize = 256; | | 1933 | sc->sc_nvm_wordsize = 256; |
1934 | sc->sc_nvm_addrbits = 8; | | 1934 | sc->sc_nvm_addrbits = 8; |
1935 | } else { | | 1935 | } else { |
1936 | sc->sc_nvm_wordsize = 64; | | 1936 | sc->sc_nvm_wordsize = 64; |
1937 | sc->sc_nvm_addrbits = 6; | | 1937 | sc->sc_nvm_addrbits = 6; |
1938 | } | | 1938 | } |
1939 | sc->sc_flags |= WM_F_LOCK_EECD; | | 1939 | sc->sc_flags |= WM_F_LOCK_EECD; |
1940 | break; | | 1940 | break; |
1941 | case WM_T_82541: | | 1941 | case WM_T_82541: |
1942 | case WM_T_82541_2: | | 1942 | case WM_T_82541_2: |
1943 | case WM_T_82547: | | 1943 | case WM_T_82547: |
1944 | case WM_T_82547_2: | | 1944 | case WM_T_82547_2: |
1945 | sc->sc_flags |= WM_F_LOCK_EECD; | | 1945 | sc->sc_flags |= WM_F_LOCK_EECD; |
1946 | reg = CSR_READ(sc, WMREG_EECD); | | 1946 | reg = CSR_READ(sc, WMREG_EECD); |
1947 | if (reg & EECD_EE_TYPE) { | | 1947 | if (reg & EECD_EE_TYPE) { |
1948 | /* SPI */ | | 1948 | /* SPI */ |
1949 | sc->sc_flags |= WM_F_EEPROM_SPI; | | 1949 | sc->sc_flags |= WM_F_EEPROM_SPI; |
1950 | wm_nvm_set_addrbits_size_eecd(sc); | | 1950 | wm_nvm_set_addrbits_size_eecd(sc); |
1951 | } else { | | 1951 | } else { |
1952 | /* Microwire */ | | 1952 | /* Microwire */ |
1953 | if ((reg & EECD_EE_ABITS) != 0) { | | 1953 | if ((reg & EECD_EE_ABITS) != 0) { |
1954 | sc->sc_nvm_wordsize = 256; | | 1954 | sc->sc_nvm_wordsize = 256; |
1955 | sc->sc_nvm_addrbits = 8; | | 1955 | sc->sc_nvm_addrbits = 8; |
1956 | } else { | | 1956 | } else { |
1957 | sc->sc_nvm_wordsize = 64; | | 1957 | sc->sc_nvm_wordsize = 64; |
1958 | sc->sc_nvm_addrbits = 6; | | 1958 | sc->sc_nvm_addrbits = 6; |
1959 | } | | 1959 | } |
1960 | } | | 1960 | } |
1961 | break; | | 1961 | break; |
1962 | case WM_T_82571: | | 1962 | case WM_T_82571: |
1963 | case WM_T_82572: | | 1963 | case WM_T_82572: |
1964 | /* SPI */ | | 1964 | /* SPI */ |
1965 | sc->sc_flags |= WM_F_EEPROM_SPI; | | 1965 | sc->sc_flags |= WM_F_EEPROM_SPI; |
1966 | wm_nvm_set_addrbits_size_eecd(sc); | | 1966 | wm_nvm_set_addrbits_size_eecd(sc); |
1967 | sc->sc_flags |= WM_F_LOCK_EECD | WM_F_LOCK_SWSM; | | 1967 | sc->sc_flags |= WM_F_LOCK_EECD | WM_F_LOCK_SWSM; |
1968 | break; | | 1968 | break; |
1969 | case WM_T_82573: | | 1969 | case WM_T_82573: |
1970 | sc->sc_flags |= WM_F_LOCK_SWSM; | | 1970 | sc->sc_flags |= WM_F_LOCK_SWSM; |
1971 | /* FALLTHROUGH */ | | 1971 | /* FALLTHROUGH */ |
1972 | case WM_T_82574: | | 1972 | case WM_T_82574: |
1973 | case WM_T_82583: | | 1973 | case WM_T_82583: |
1974 | if (wm_nvm_is_onboard_eeprom(sc) == 0) { | | 1974 | if (wm_nvm_is_onboard_eeprom(sc) == 0) { |
1975 | sc->sc_flags |= WM_F_EEPROM_FLASH; | | 1975 | sc->sc_flags |= WM_F_EEPROM_FLASH; |
1976 | sc->sc_nvm_wordsize = 2048; | | 1976 | sc->sc_nvm_wordsize = 2048; |
1977 | } else { | | 1977 | } else { |
1978 | /* SPI */ | | 1978 | /* SPI */ |
1979 | sc->sc_flags |= WM_F_EEPROM_SPI; | | 1979 | sc->sc_flags |= WM_F_EEPROM_SPI; |
1980 | wm_nvm_set_addrbits_size_eecd(sc); | | 1980 | wm_nvm_set_addrbits_size_eecd(sc); |
1981 | } | | 1981 | } |
1982 | sc->sc_flags |= WM_F_EEPROM_EERDEEWR; | | 1982 | sc->sc_flags |= WM_F_EEPROM_EERDEEWR; |
1983 | break; | | 1983 | break; |
1984 | case WM_T_82575: | | 1984 | case WM_T_82575: |
1985 | case WM_T_82576: | | 1985 | case WM_T_82576: |
1986 | case WM_T_82580: | | 1986 | case WM_T_82580: |
1987 | case WM_T_I350: | | 1987 | case WM_T_I350: |
1988 | case WM_T_I354: | | 1988 | case WM_T_I354: |
1989 | case WM_T_80003: | | 1989 | case WM_T_80003: |
1990 | /* SPI */ | | 1990 | /* SPI */ |
1991 | sc->sc_flags |= WM_F_EEPROM_SPI; | | 1991 | sc->sc_flags |= WM_F_EEPROM_SPI; |
1992 | wm_nvm_set_addrbits_size_eecd(sc); | | 1992 | wm_nvm_set_addrbits_size_eecd(sc); |
1993 | sc->sc_flags |= WM_F_EEPROM_EERDEEWR | WM_F_LOCK_SWFW | | 1993 | sc->sc_flags |= WM_F_EEPROM_EERDEEWR | WM_F_LOCK_SWFW |
1994 | | WM_F_LOCK_SWSM; | | 1994 | | WM_F_LOCK_SWSM; |
1995 | break; | | 1995 | break; |
1996 | case WM_T_ICH8: | | 1996 | case WM_T_ICH8: |
1997 | case WM_T_ICH9: | | 1997 | case WM_T_ICH9: |
1998 | case WM_T_ICH10: | | 1998 | case WM_T_ICH10: |
1999 | case WM_T_PCH: | | 1999 | case WM_T_PCH: |
2000 | case WM_T_PCH2: | | 2000 | case WM_T_PCH2: |
2001 | case WM_T_PCH_LPT: | | 2001 | case WM_T_PCH_LPT: |
2002 | /* FLASH */ | | 2002 | /* FLASH */ |
2003 | sc->sc_flags |= WM_F_EEPROM_FLASH | WM_F_LOCK_EXTCNF; | | 2003 | sc->sc_flags |= WM_F_EEPROM_FLASH | WM_F_LOCK_EXTCNF; |
2004 | sc->sc_nvm_wordsize = 2048; | | 2004 | sc->sc_nvm_wordsize = 2048; |
2005 | memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_ICH8_FLASH); | | 2005 | memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_ICH8_FLASH); |
2006 | if (pci_mapreg_map(pa, WM_ICH8_FLASH, memtype, 0, | | 2006 | if (pci_mapreg_map(pa, WM_ICH8_FLASH, memtype, 0, |
2007 | &sc->sc_flasht, &sc->sc_flashh, NULL, &sc->sc_flashs)) { | | 2007 | &sc->sc_flasht, &sc->sc_flashh, NULL, &sc->sc_flashs)) { |
2008 | aprint_error_dev(sc->sc_dev, | | 2008 | aprint_error_dev(sc->sc_dev, |
2009 | "can't map FLASH registers\n"); | | 2009 | "can't map FLASH registers\n"); |
2010 | goto out; | | 2010 | goto out; |
2011 | } | | 2011 | } |
2012 | reg = ICH8_FLASH_READ32(sc, ICH_FLASH_GFPREG); | | 2012 | reg = ICH8_FLASH_READ32(sc, ICH_FLASH_GFPREG); |
2013 | sc->sc_ich8_flash_base = (reg & ICH_GFPREG_BASE_MASK) * | | 2013 | sc->sc_ich8_flash_base = (reg & ICH_GFPREG_BASE_MASK) * |
2014 | ICH_FLASH_SECTOR_SIZE; | | 2014 | ICH_FLASH_SECTOR_SIZE; |
2015 | sc->sc_ich8_flash_bank_size = | | 2015 | sc->sc_ich8_flash_bank_size = |
2016 | ((reg >> 16) & ICH_GFPREG_BASE_MASK) + 1; | | 2016 | ((reg >> 16) & ICH_GFPREG_BASE_MASK) + 1; |
2017 | sc->sc_ich8_flash_bank_size -= | | 2017 | sc->sc_ich8_flash_bank_size -= |
2018 | (reg & ICH_GFPREG_BASE_MASK); | | 2018 | (reg & ICH_GFPREG_BASE_MASK); |
2019 | sc->sc_ich8_flash_bank_size *= ICH_FLASH_SECTOR_SIZE; | | 2019 | sc->sc_ich8_flash_bank_size *= ICH_FLASH_SECTOR_SIZE; |
2020 | sc->sc_ich8_flash_bank_size /= 2 * sizeof(uint16_t); | | 2020 | sc->sc_ich8_flash_bank_size /= 2 * sizeof(uint16_t); |
2021 | break; | | 2021 | break; |
2022 | case WM_T_I210: | | 2022 | case WM_T_I210: |
2023 | case WM_T_I211: | | 2023 | case WM_T_I211: |
2024 | if (wm_nvm_get_flash_presence_i210(sc)) { | | 2024 | if (wm_nvm_get_flash_presence_i210(sc)) { |
2025 | wm_nvm_set_addrbits_size_eecd(sc); | | 2025 | wm_nvm_set_addrbits_size_eecd(sc); |
2026 | sc->sc_flags |= WM_F_EEPROM_FLASH_HW; | | 2026 | sc->sc_flags |= WM_F_EEPROM_FLASH_HW; |
2027 | sc->sc_flags |= WM_F_EEPROM_EERDEEWR | WM_F_LOCK_SWFW; | | 2027 | sc->sc_flags |= WM_F_EEPROM_EERDEEWR | WM_F_LOCK_SWFW; |
2028 | } else { | | 2028 | } else { |
2029 | sc->sc_nvm_wordsize = INVM_SIZE; | | 2029 | sc->sc_nvm_wordsize = INVM_SIZE; |
2030 | sc->sc_flags |= WM_F_EEPROM_INVM; | | 2030 | sc->sc_flags |= WM_F_EEPROM_INVM; |
2031 | sc->sc_flags |= WM_F_LOCK_SWFW; | | 2031 | sc->sc_flags |= WM_F_LOCK_SWFW; |
2032 | } | | 2032 | } |
2033 | break; | | 2033 | break; |
2034 | default: | | 2034 | default: |
2035 | break; | | 2035 | break; |
2036 | } | | 2036 | } |
2037 | | | 2037 | |
2038 | /* Ensure the SMBI bit is clear before first NVM or PHY access */ | | 2038 | /* Ensure the SMBI bit is clear before first NVM or PHY access */ |
2039 | switch (sc->sc_type) { | | 2039 | switch (sc->sc_type) { |
2040 | case WM_T_82571: | | 2040 | case WM_T_82571: |
2041 | case WM_T_82572: | | 2041 | case WM_T_82572: |
2042 | reg = CSR_READ(sc, WMREG_SWSM2); | | 2042 | reg = CSR_READ(sc, WMREG_SWSM2); |
2043 | if ((reg & SWSM2_LOCK) == 0) { | | 2043 | if ((reg & SWSM2_LOCK) == 0) { |
2044 | CSR_WRITE(sc, WMREG_SWSM2, reg | SWSM2_LOCK); | | 2044 | CSR_WRITE(sc, WMREG_SWSM2, reg | SWSM2_LOCK); |
2045 | force_clear_smbi = true; | | 2045 | force_clear_smbi = true; |
2046 | } else | | 2046 | } else |
2047 | force_clear_smbi = false; | | 2047 | force_clear_smbi = false; |
2048 | break; | | 2048 | break; |
2049 | case WM_T_82573: | | 2049 | case WM_T_82573: |
2050 | case WM_T_82574: | | 2050 | case WM_T_82574: |
2051 | case WM_T_82583: | | 2051 | case WM_T_82583: |
2052 | force_clear_smbi = true; | | 2052 | force_clear_smbi = true; |
2053 | break; | | 2053 | break; |
2054 | default: | | 2054 | default: |
2055 | force_clear_smbi = false; | | 2055 | force_clear_smbi = false; |
2056 | break; | | 2056 | break; |
2057 | } | | 2057 | } |
2058 | if (force_clear_smbi) { | | 2058 | if (force_clear_smbi) { |
2059 | reg = CSR_READ(sc, WMREG_SWSM); | | 2059 | reg = CSR_READ(sc, WMREG_SWSM); |
2060 | if ((reg & SWSM_SMBI) != 0) | | 2060 | if ((reg & SWSM_SMBI) != 0) |
2061 | aprint_error_dev(sc->sc_dev, | | 2061 | aprint_error_dev(sc->sc_dev, |
2062 | "Please update the Bootagent\n"); | | 2062 | "Please update the Bootagent\n"); |
2063 | CSR_WRITE(sc, WMREG_SWSM, reg & ~SWSM_SMBI); | | 2063 | CSR_WRITE(sc, WMREG_SWSM, reg & ~SWSM_SMBI); |
2064 | } | | 2064 | } |
2065 | | | 2065 | |
2066 | /* | | 2066 | /* |
2067 | * Defer printing the EEPROM type until after verifying the checksum | | 2067 | * Defer printing the EEPROM type until after verifying the checksum |
2068 | * This allows the EEPROM type to be printed correctly in the case | | 2068 | * This allows the EEPROM type to be printed correctly in the case |
2069 | * that no EEPROM is attached. | | 2069 | * that no EEPROM is attached. |
2070 | */ | | 2070 | */ |
2071 | /* | | 2071 | /* |
2072 | * Validate the EEPROM checksum. If the checksum fails, flag | | 2072 | * Validate the EEPROM checksum. If the checksum fails, flag |
2073 | * this for later, so we can fail future reads from the EEPROM. | | 2073 | * this for later, so we can fail future reads from the EEPROM. |
2074 | */ | | 2074 | */ |
2075 | if (wm_nvm_validate_checksum(sc)) { | | 2075 | if (wm_nvm_validate_checksum(sc)) { |
2076 | /* | | 2076 | /* |
2077 | * Read twice again because some PCI-e parts fail the | | 2077 | * Read twice again because some PCI-e parts fail the |
2078 | * first check due to the link being in sleep state. | | 2078 | * first check due to the link being in sleep state. |
2079 | */ | | 2079 | */ |
2080 | if (wm_nvm_validate_checksum(sc)) | | 2080 | if (wm_nvm_validate_checksum(sc)) |
2081 | sc->sc_flags |= WM_F_EEPROM_INVALID; | | 2081 | sc->sc_flags |= WM_F_EEPROM_INVALID; |
2082 | } | | 2082 | } |
2083 | | | 2083 | |
2084 | /* Set device properties (macflags) */ | | 2084 | /* Set device properties (macflags) */ |
2085 | prop_dictionary_set_uint32(dict, "macflags", sc->sc_flags); | | 2085 | prop_dictionary_set_uint32(dict, "macflags", sc->sc_flags); |
2086 | | | 2086 | |
2087 | if (sc->sc_flags & WM_F_EEPROM_INVALID) | | 2087 | if (sc->sc_flags & WM_F_EEPROM_INVALID) |
2088 | aprint_verbose_dev(sc->sc_dev, "No EEPROM"); | | 2088 | aprint_verbose_dev(sc->sc_dev, "No EEPROM"); |
2089 | else { | | 2089 | else { |
2090 | aprint_verbose_dev(sc->sc_dev, "%u words ", | | 2090 | aprint_verbose_dev(sc->sc_dev, "%u words ", |
2091 | sc->sc_nvm_wordsize); | | 2091 | sc->sc_nvm_wordsize); |
2092 | if (sc->sc_flags & WM_F_EEPROM_INVM) | | 2092 | if (sc->sc_flags & WM_F_EEPROM_INVM) |
2093 | aprint_verbose("iNVM"); | | 2093 | aprint_verbose("iNVM"); |
2094 | else if (sc->sc_flags & WM_F_EEPROM_FLASH_HW) | | 2094 | else if (sc->sc_flags & WM_F_EEPROM_FLASH_HW) |
2095 | aprint_verbose("FLASH(HW)"); | | 2095 | aprint_verbose("FLASH(HW)"); |
2096 | else if (sc->sc_flags & WM_F_EEPROM_FLASH) | | 2096 | else if (sc->sc_flags & WM_F_EEPROM_FLASH) |
2097 | aprint_verbose("FLASH"); | | 2097 | aprint_verbose("FLASH"); |
2098 | else { | | 2098 | else { |
2099 | if (sc->sc_flags & WM_F_EEPROM_SPI) | | 2099 | if (sc->sc_flags & WM_F_EEPROM_SPI) |
2100 | eetype = "SPI"; | | 2100 | eetype = "SPI"; |
2101 | else | | 2101 | else |
2102 | eetype = "MicroWire"; | | 2102 | eetype = "MicroWire"; |
2103 | aprint_verbose("(%d address bits) %s EEPROM", | | 2103 | aprint_verbose("(%d address bits) %s EEPROM", |
2104 | sc->sc_nvm_addrbits, eetype); | | 2104 | sc->sc_nvm_addrbits, eetype); |
2105 | } | | 2105 | } |
2106 | } | | 2106 | } |
2107 | wm_nvm_version(sc); | | 2107 | wm_nvm_version(sc); |
2108 | aprint_verbose("\n"); | | 2108 | aprint_verbose("\n"); |
2109 | | | 2109 | |
2110 | /* Check for I21[01] PLL workaround */ | | 2110 | /* Check for I21[01] PLL workaround */ |
2111 | if (sc->sc_type == WM_T_I210) | | 2111 | if (sc->sc_type == WM_T_I210) |
2112 | sc->sc_flags |= WM_F_PLL_WA_I210; | | 2112 | sc->sc_flags |= WM_F_PLL_WA_I210; |
2113 | if ((sc->sc_type == WM_T_I210) && wm_nvm_get_flash_presence_i210(sc)) { | | 2113 | if ((sc->sc_type == WM_T_I210) && wm_nvm_get_flash_presence_i210(sc)) { |
2114 | /* NVM image release 3.25 has a workaround */ | | 2114 | /* NVM image release 3.25 has a workaround */ |
2115 | if ((sc->sc_nvm_ver_major < 3) | | 2115 | if ((sc->sc_nvm_ver_major < 3) |
2116 | || ((sc->sc_nvm_ver_major == 3) | | 2116 | || ((sc->sc_nvm_ver_major == 3) |
2117 | && (sc->sc_nvm_ver_minor < 25))) { | | 2117 | && (sc->sc_nvm_ver_minor < 25))) { |
2118 | aprint_verbose_dev(sc->sc_dev, | | 2118 | aprint_verbose_dev(sc->sc_dev, |
2119 | "ROM image version %d.%d is older than 3.25\n", | | 2119 | "ROM image version %d.%d is older than 3.25\n", |
2120 | sc->sc_nvm_ver_major, sc->sc_nvm_ver_minor); | | 2120 | sc->sc_nvm_ver_major, sc->sc_nvm_ver_minor); |
2121 | sc->sc_flags |= WM_F_PLL_WA_I210; | | 2121 | sc->sc_flags |= WM_F_PLL_WA_I210; |
2122 | } | | 2122 | } |
2123 | } | | 2123 | } |
2124 | if ((sc->sc_flags & WM_F_PLL_WA_I210) != 0) | | 2124 | if ((sc->sc_flags & WM_F_PLL_WA_I210) != 0) |
2125 | wm_pll_workaround_i210(sc); | | 2125 | wm_pll_workaround_i210(sc); |
2126 | | | 2126 | |
2127 | switch (sc->sc_type) { | | 2127 | switch (sc->sc_type) { |
2128 | case WM_T_82571: | | 2128 | case WM_T_82571: |
2129 | case WM_T_82572: | | 2129 | case WM_T_82572: |
2130 | case WM_T_82573: | | 2130 | case WM_T_82573: |
2131 | case WM_T_82574: | | 2131 | case WM_T_82574: |
2132 | case WM_T_82583: | | 2132 | case WM_T_82583: |
2133 | case WM_T_80003: | | 2133 | case WM_T_80003: |
2134 | case WM_T_ICH8: | | 2134 | case WM_T_ICH8: |
2135 | case WM_T_ICH9: | | 2135 | case WM_T_ICH9: |
2136 | case WM_T_ICH10: | | 2136 | case WM_T_ICH10: |
2137 | case WM_T_PCH: | | 2137 | case WM_T_PCH: |
2138 | case WM_T_PCH2: | | 2138 | case WM_T_PCH2: |
2139 | case WM_T_PCH_LPT: | | 2139 | case WM_T_PCH_LPT: |
2140 | if (wm_check_mng_mode(sc) != 0) | | 2140 | if (wm_check_mng_mode(sc) != 0) |
2141 | wm_get_hw_control(sc); | | 2141 | wm_get_hw_control(sc); |
2142 | break; | | 2142 | break; |
2143 | default: | | 2143 | default: |
2144 | break; | | 2144 | break; |
2145 | } | | 2145 | } |
2146 | wm_get_wakeup(sc); | | 2146 | wm_get_wakeup(sc); |
2147 | /* | | 2147 | /* |
2148 | * Read the Ethernet address from the EEPROM, if not first found | | 2148 | * Read the Ethernet address from the EEPROM, if not first found |
2149 | * in device properties. | | 2149 | * in device properties. |
2150 | */ | | 2150 | */ |
2151 | ea = prop_dictionary_get(dict, "mac-address"); | | 2151 | ea = prop_dictionary_get(dict, "mac-address"); |
2152 | if (ea != NULL) { | | 2152 | if (ea != NULL) { |
2153 | KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); | | 2153 | KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); |
2154 | KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); | | 2154 | KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); |
2155 | memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); | | 2155 | memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); |
2156 | } else { | | 2156 | } else { |
2157 | if (wm_read_mac_addr(sc, enaddr) != 0) { | | 2157 | if (wm_read_mac_addr(sc, enaddr) != 0) { |
2158 | aprint_error_dev(sc->sc_dev, | | 2158 | aprint_error_dev(sc->sc_dev, |
2159 | "unable to read Ethernet address\n"); | | 2159 | "unable to read Ethernet address\n"); |
2160 | goto out; | | 2160 | goto out; |
2161 | } | | 2161 | } |
2162 | } | | 2162 | } |
2163 | | | 2163 | |
2164 | aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", | | 2164 | aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", |
2165 | ether_sprintf(enaddr)); | | 2165 | ether_sprintf(enaddr)); |
2166 | | | 2166 | |
2167 | /* | | 2167 | /* |
2168 | * Read the config info from the EEPROM, and set up various | | 2168 | * Read the config info from the EEPROM, and set up various |
2169 | * bits in the control registers based on their contents. | | 2169 | * bits in the control registers based on their contents. |
2170 | */ | | 2170 | */ |
2171 | pn = prop_dictionary_get(dict, "i82543-cfg1"); | | 2171 | pn = prop_dictionary_get(dict, "i82543-cfg1"); |
2172 | if (pn != NULL) { | | 2172 | if (pn != NULL) { |
2173 | KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); | | 2173 | KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); |
2174 | cfg1 = (uint16_t) prop_number_integer_value(pn); | | 2174 | cfg1 = (uint16_t) prop_number_integer_value(pn); |
2175 | } else { | | 2175 | } else { |
2176 | if (wm_nvm_read(sc, NVM_OFF_CFG1, 1, &cfg1)) { | | 2176 | if (wm_nvm_read(sc, NVM_OFF_CFG1, 1, &cfg1)) { |
2177 | aprint_error_dev(sc->sc_dev, "unable to read CFG1\n"); | | 2177 | aprint_error_dev(sc->sc_dev, "unable to read CFG1\n"); |
2178 | goto out; | | 2178 | goto out; |
2179 | } | | 2179 | } |
2180 | } | | 2180 | } |
2181 | | | 2181 | |
2182 | pn = prop_dictionary_get(dict, "i82543-cfg2"); | | 2182 | pn = prop_dictionary_get(dict, "i82543-cfg2"); |
2183 | if (pn != NULL) { | | 2183 | if (pn != NULL) { |
2184 | KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); | | 2184 | KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); |
2185 | cfg2 = (uint16_t) prop_number_integer_value(pn); | | 2185 | cfg2 = (uint16_t) prop_number_integer_value(pn); |
2186 | } else { | | 2186 | } else { |
2187 | if (wm_nvm_read(sc, NVM_OFF_CFG2, 1, &cfg2)) { | | 2187 | if (wm_nvm_read(sc, NVM_OFF_CFG2, 1, &cfg2)) { |
2188 | aprint_error_dev(sc->sc_dev, "unable to read CFG2\n"); | | 2188 | aprint_error_dev(sc->sc_dev, "unable to read CFG2\n"); |
2189 | goto out; | | 2189 | goto out; |
2190 | } | | 2190 | } |
2191 | } | | 2191 | } |
2192 | | | 2192 | |
2193 | /* check for WM_F_WOL */ | | 2193 | /* check for WM_F_WOL */ |
2194 | switch (sc->sc_type) { | | 2194 | switch (sc->sc_type) { |
2195 | case WM_T_82542_2_0: | | 2195 | case WM_T_82542_2_0: |
2196 | case WM_T_82542_2_1: | | 2196 | case WM_T_82542_2_1: |
2197 | case WM_T_82543: | | 2197 | case WM_T_82543: |
2198 | /* dummy? */ | | 2198 | /* dummy? */ |
2199 | eeprom_data = 0; | | 2199 | eeprom_data = 0; |
2200 | apme_mask = NVM_CFG3_APME; | | 2200 | apme_mask = NVM_CFG3_APME; |
2201 | break; | | 2201 | break; |
2202 | case WM_T_82544: | | 2202 | case WM_T_82544: |
2203 | apme_mask = NVM_CFG2_82544_APM_EN; | | 2203 | apme_mask = NVM_CFG2_82544_APM_EN; |
2204 | eeprom_data = cfg2; | | 2204 | eeprom_data = cfg2; |
2205 | break; | | 2205 | break; |
2206 | case WM_T_82546: | | 2206 | case WM_T_82546: |
2207 | case WM_T_82546_3: | | 2207 | case WM_T_82546_3: |
2208 | case WM_T_82571: | | 2208 | case WM_T_82571: |
2209 | case WM_T_82572: | | 2209 | case WM_T_82572: |
2210 | case WM_T_82573: | | 2210 | case WM_T_82573: |
2211 | case WM_T_82574: | | 2211 | case WM_T_82574: |
2212 | case WM_T_82583: | | 2212 | case WM_T_82583: |
2213 | case WM_T_80003: | | 2213 | case WM_T_80003: |
2214 | default: | | 2214 | default: |
2215 | apme_mask = NVM_CFG3_APME; | | 2215 | apme_mask = NVM_CFG3_APME; |
2216 | wm_nvm_read(sc, (sc->sc_funcid == 1) ? NVM_OFF_CFG3_PORTB | | 2216 | wm_nvm_read(sc, (sc->sc_funcid == 1) ? NVM_OFF_CFG3_PORTB |
2217 | : NVM_OFF_CFG3_PORTA, 1, &eeprom_data); | | 2217 | : NVM_OFF_CFG3_PORTA, 1, &eeprom_data); |
2218 | break; | | 2218 | break; |
2219 | case WM_T_82575: | | 2219 | case WM_T_82575: |
2220 | case WM_T_82576: | | 2220 | case WM_T_82576: |
2221 | case WM_T_82580: | | 2221 | case WM_T_82580: |
2222 | case WM_T_I350: | | 2222 | case WM_T_I350: |
2223 | case WM_T_I354: /* XXX ok? */ | | 2223 | case WM_T_I354: /* XXX ok? */ |
2224 | case WM_T_ICH8: | | 2224 | case WM_T_ICH8: |
2225 | case WM_T_ICH9: | | 2225 | case WM_T_ICH9: |
2226 | case WM_T_ICH10: | | 2226 | case WM_T_ICH10: |
2227 | case WM_T_PCH: | | 2227 | case WM_T_PCH: |
2228 | case WM_T_PCH2: | | 2228 | case WM_T_PCH2: |
2229 | case WM_T_PCH_LPT: | | 2229 | case WM_T_PCH_LPT: |
2230 | /* XXX The funcid should be checked on some devices */ | | 2230 | /* XXX The funcid should be checked on some devices */ |
2231 | apme_mask = WUC_APME; | | 2231 | apme_mask = WUC_APME; |
2232 | eeprom_data = CSR_READ(sc, WMREG_WUC); | | 2232 | eeprom_data = CSR_READ(sc, WMREG_WUC); |
2233 | break; | | 2233 | break; |
2234 | } | | 2234 | } |
2235 | | | 2235 | |
2236 | /* Check for WM_F_WOL flag after the setting of the EEPROM stuff */ | | 2236 | /* Check for WM_F_WOL flag after the setting of the EEPROM stuff */ |
2237 | if ((eeprom_data & apme_mask) != 0) | | 2237 | if ((eeprom_data & apme_mask) != 0) |
2238 | sc->sc_flags |= WM_F_WOL; | | 2238 | sc->sc_flags |= WM_F_WOL; |
2239 | #ifdef WM_DEBUG | | 2239 | #ifdef WM_DEBUG |
2240 | if ((sc->sc_flags & WM_F_WOL) != 0) | | 2240 | if ((sc->sc_flags & WM_F_WOL) != 0) |
2241 | printf("WOL\n"); | | 2241 | printf("WOL\n"); |
2242 | #endif | | 2242 | #endif |
2243 | | | 2243 | |
2244 | if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)) { | | 2244 | if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)) { |
2245 | /* Check NVM for autonegotiation */ | | 2245 | /* Check NVM for autonegotiation */ |
2246 | if (wm_nvm_read(sc, NVM_OFF_COMPAT, 1, &nvmword) == 0) { | | 2246 | if (wm_nvm_read(sc, NVM_OFF_COMPAT, 1, &nvmword) == 0) { |
2247 | if ((nvmword & NVM_COMPAT_SERDES_FORCE_MODE) != 0) | | 2247 | if ((nvmword & NVM_COMPAT_SERDES_FORCE_MODE) != 0) |
2248 | sc->sc_flags |= WM_F_PCS_DIS_AUTONEGO; | | 2248 | sc->sc_flags |= WM_F_PCS_DIS_AUTONEGO; |
2249 | } | | 2249 | } |
2250 | } | | 2250 | } |
2251 | | | 2251 | |
2252 | /* | | 2252 | /* |
2253 | * XXX need special handling for some multiple port cards | | 2253 | * XXX need special handling for some multiple port cards |
2254 | * to disable a paticular port. | | 2254 | * to disable a paticular port. |
2255 | */ | | 2255 | */ |
2256 | | | 2256 | |
2257 | if (sc->sc_type >= WM_T_82544) { | | 2257 | if (sc->sc_type >= WM_T_82544) { |
2258 | pn = prop_dictionary_get(dict, "i82543-swdpin"); | | 2258 | pn = prop_dictionary_get(dict, "i82543-swdpin"); |
2259 | if (pn != NULL) { | | 2259 | if (pn != NULL) { |
2260 | KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); | | 2260 | KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); |
2261 | swdpin = (uint16_t) prop_number_integer_value(pn); | | 2261 | swdpin = (uint16_t) prop_number_integer_value(pn); |
2262 | } else { | | 2262 | } else { |
2263 | if (wm_nvm_read(sc, NVM_OFF_SWDPIN, 1, &swdpin)) { | | 2263 | if (wm_nvm_read(sc, NVM_OFF_SWDPIN, 1, &swdpin)) { |
2264 | aprint_error_dev(sc->sc_dev, | | 2264 | aprint_error_dev(sc->sc_dev, |
2265 | "unable to read SWDPIN\n"); | | 2265 | "unable to read SWDPIN\n"); |
2266 | goto out; | | 2266 | goto out; |
2267 | } | | 2267 | } |
2268 | } | | 2268 | } |
2269 | } | | 2269 | } |
2270 | | | 2270 | |
2271 | if (cfg1 & NVM_CFG1_ILOS) | | 2271 | if (cfg1 & NVM_CFG1_ILOS) |
2272 | sc->sc_ctrl |= CTRL_ILOS; | | 2272 | sc->sc_ctrl |= CTRL_ILOS; |
2273 | | | 2273 | |
2274 | /* | | 2274 | /* |
2275 | * XXX | | 2275 | * XXX |
2276 | * This code isn't correct because pin 2 and 3 are located | | 2276 | * This code isn't correct because pin 2 and 3 are located |
2277 | * in different position on newer chips. Check all datasheet. | | 2277 | * in different position on newer chips. Check all datasheet. |
2278 | * | | 2278 | * |
2279 | * Until resolve this problem, check if a chip < 82580 | | 2279 | * Until resolve this problem, check if a chip < 82580 |
2280 | */ | | 2280 | */ |
2281 | if (sc->sc_type <= WM_T_82580) { | | 2281 | if (sc->sc_type <= WM_T_82580) { |
2282 | if (sc->sc_type >= WM_T_82544) { | | 2282 | if (sc->sc_type >= WM_T_82544) { |
2283 | sc->sc_ctrl |= | | 2283 | sc->sc_ctrl |= |
2284 | ((swdpin >> NVM_SWDPIN_SWDPIO_SHIFT) & 0xf) << | | 2284 | ((swdpin >> NVM_SWDPIN_SWDPIO_SHIFT) & 0xf) << |
2285 | CTRL_SWDPIO_SHIFT; | | 2285 | CTRL_SWDPIO_SHIFT; |
2286 | sc->sc_ctrl |= | | 2286 | sc->sc_ctrl |= |
2287 | ((swdpin >> NVM_SWDPIN_SWDPIN_SHIFT) & 0xf) << | | 2287 | ((swdpin >> NVM_SWDPIN_SWDPIN_SHIFT) & 0xf) << |
2288 | CTRL_SWDPINS_SHIFT; | | 2288 | CTRL_SWDPINS_SHIFT; |
2289 | } else { | | 2289 | } else { |
2290 | sc->sc_ctrl |= | | 2290 | sc->sc_ctrl |= |
2291 | ((cfg1 >> NVM_CFG1_SWDPIO_SHIFT) & 0xf) << | | 2291 | ((cfg1 >> NVM_CFG1_SWDPIO_SHIFT) & 0xf) << |
2292 | CTRL_SWDPIO_SHIFT; | | 2292 | CTRL_SWDPIO_SHIFT; |
2293 | } | | 2293 | } |
2294 | } | | 2294 | } |
2295 | | | 2295 | |
2296 | /* XXX For other than 82580? */ | | 2296 | /* XXX For other than 82580? */ |
2297 | if (sc->sc_type == WM_T_82580) { | | 2297 | if (sc->sc_type == WM_T_82580) { |
2298 | wm_nvm_read(sc, NVM_OFF_CFG3_PORTA, 1, &nvmword); | | 2298 | wm_nvm_read(sc, NVM_OFF_CFG3_PORTA, 1, &nvmword); |
2299 | printf("CFG3 = %08x\n", (uint32_t)nvmword); | | 2299 | printf("CFG3 = %08x\n", (uint32_t)nvmword); |
2300 | if (nvmword & __BIT(13)) { | | 2300 | if (nvmword & __BIT(13)) { |
2301 | printf("SET ILOS\n"); | | 2301 | printf("SET ILOS\n"); |
2302 | sc->sc_ctrl |= CTRL_ILOS; | | 2302 | sc->sc_ctrl |= CTRL_ILOS; |
2303 | } | | 2303 | } |
2304 | } | | 2304 | } |
2305 | | | 2305 | |
2306 | #if 0 | | 2306 | #if 0 |
2307 | if (sc->sc_type >= WM_T_82544) { | | 2307 | if (sc->sc_type >= WM_T_82544) { |
2308 | if (cfg1 & NVM_CFG1_IPS0) | | 2308 | if (cfg1 & NVM_CFG1_IPS0) |
2309 | sc->sc_ctrl_ext |= CTRL_EXT_IPS; | | 2309 | sc->sc_ctrl_ext |= CTRL_EXT_IPS; |
2310 | if (cfg1 & NVM_CFG1_IPS1) | | 2310 | if (cfg1 & NVM_CFG1_IPS1) |
2311 | sc->sc_ctrl_ext |= CTRL_EXT_IPS1; | | 2311 | sc->sc_ctrl_ext |= CTRL_EXT_IPS1; |
2312 | sc->sc_ctrl_ext |= | | 2312 | sc->sc_ctrl_ext |= |
2313 | ((swdpin >> (NVM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) << | | 2313 | ((swdpin >> (NVM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) << |
2314 | CTRL_EXT_SWDPIO_SHIFT; | | 2314 | CTRL_EXT_SWDPIO_SHIFT; |
2315 | sc->sc_ctrl_ext |= | | 2315 | sc->sc_ctrl_ext |= |
2316 | ((swdpin >> (NVM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) << | | 2316 | ((swdpin >> (NVM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) << |
2317 | CTRL_EXT_SWDPINS_SHIFT; | | 2317 | CTRL_EXT_SWDPINS_SHIFT; |
2318 | } else { | | 2318 | } else { |
2319 | sc->sc_ctrl_ext |= | | 2319 | sc->sc_ctrl_ext |= |
2320 | ((cfg2 >> NVM_CFG2_SWDPIO_SHIFT) & 0xf) << | | 2320 | ((cfg2 >> NVM_CFG2_SWDPIO_SHIFT) & 0xf) << |
2321 | CTRL_EXT_SWDPIO_SHIFT; | | 2321 | CTRL_EXT_SWDPIO_SHIFT; |
2322 | } | | 2322 | } |
2323 | #endif | | 2323 | #endif |
2324 | | | 2324 | |
2325 | CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); | | 2325 | CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); |
2326 | #if 0 | | 2326 | #if 0 |
2327 | CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); | | 2327 | CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); |
2328 | #endif | | 2328 | #endif |
2329 | | | 2329 | |
2330 | if (sc->sc_type == WM_T_PCH) { | | 2330 | if (sc->sc_type == WM_T_PCH) { |
2331 | uint16_t val; | | 2331 | uint16_t val; |
2332 | | | 2332 | |
2333 | /* Save the NVM K1 bit setting */ | | 2333 | /* Save the NVM K1 bit setting */ |
2334 | wm_nvm_read(sc, NVM_OFF_K1_CONFIG, 1, &val); | | 2334 | wm_nvm_read(sc, NVM_OFF_K1_CONFIG, 1, &val); |
2335 | | | 2335 | |
2336 | if ((val & NVM_K1_CONFIG_ENABLE) != 0) | | 2336 | if ((val & NVM_K1_CONFIG_ENABLE) != 0) |
2337 | sc->sc_nvm_k1_enabled = 1; | | 2337 | sc->sc_nvm_k1_enabled = 1; |
2338 | else | | 2338 | else |
2339 | sc->sc_nvm_k1_enabled = 0; | | 2339 | sc->sc_nvm_k1_enabled = 0; |
2340 | } | | 2340 | } |
2341 | | | 2341 | |
2342 | /* | | 2342 | /* |
2343 | * Determine if we're TBI,GMII or SGMII mode, and initialize the | | 2343 | * Determine if we're TBI,GMII or SGMII mode, and initialize the |
2344 | * media structures accordingly. | | 2344 | * media structures accordingly. |
2345 | */ | | 2345 | */ |
2346 | if (sc->sc_type == WM_T_ICH8 || sc->sc_type == WM_T_ICH9 | | 2346 | if (sc->sc_type == WM_T_ICH8 || sc->sc_type == WM_T_ICH9 |
2347 | || sc->sc_type == WM_T_ICH10 || sc->sc_type == WM_T_PCH | | 2347 | || sc->sc_type == WM_T_ICH10 || sc->sc_type == WM_T_PCH |
2348 | || sc->sc_type == WM_T_PCH2 || sc->sc_type == WM_T_PCH_LPT | | 2348 | || sc->sc_type == WM_T_PCH2 || sc->sc_type == WM_T_PCH_LPT |
2349 | || sc->sc_type == WM_T_82573 | | 2349 | || sc->sc_type == WM_T_82573 |
2350 | || sc->sc_type == WM_T_82574 || sc->sc_type == WM_T_82583) { | | 2350 | || sc->sc_type == WM_T_82574 || sc->sc_type == WM_T_82583) { |
2351 | /* STATUS_TBIMODE reserved/reused, can't rely on it */ | | 2351 | /* STATUS_TBIMODE reserved/reused, can't rely on it */ |
2352 | wm_gmii_mediainit(sc, wmp->wmp_product); | | 2352 | wm_gmii_mediainit(sc, wmp->wmp_product); |
2353 | } else if (sc->sc_type < WM_T_82543 || | | 2353 | } else if (sc->sc_type < WM_T_82543 || |
2354 | (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) { | | 2354 | (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) { |
2355 | if (sc->sc_mediatype == WM_MEDIATYPE_COPPER) { | | 2355 | if (sc->sc_mediatype == WM_MEDIATYPE_COPPER) { |
2356 | aprint_error_dev(sc->sc_dev, | | 2356 | aprint_error_dev(sc->sc_dev, |
2357 | "WARNING: TBIMODE set on 1000BASE-T product!\n"); | | 2357 | "WARNING: TBIMODE set on 1000BASE-T product!\n"); |
2358 | sc->sc_mediatype = WM_MEDIATYPE_FIBER; | | 2358 | sc->sc_mediatype = WM_MEDIATYPE_FIBER; |
2359 | } | | 2359 | } |
2360 | wm_tbi_mediainit(sc); | | 2360 | wm_tbi_mediainit(sc); |
2361 | } else { | | 2361 | } else { |
2362 | switch (sc->sc_type) { | | 2362 | switch (sc->sc_type) { |
2363 | case WM_T_82575: | | 2363 | case WM_T_82575: |
2364 | case WM_T_82576: | | 2364 | case WM_T_82576: |
2365 | case WM_T_82580: | | 2365 | case WM_T_82580: |
2366 | case WM_T_I350: | | 2366 | case WM_T_I350: |
2367 | case WM_T_I354: | | 2367 | case WM_T_I354: |
2368 | case WM_T_I210: | | 2368 | case WM_T_I210: |
2369 | case WM_T_I211: | | 2369 | case WM_T_I211: |
2370 | reg = CSR_READ(sc, WMREG_CTRL_EXT); | | 2370 | reg = CSR_READ(sc, WMREG_CTRL_EXT); |
2371 | link_mode = reg & CTRL_EXT_LINK_MODE_MASK; | | 2371 | link_mode = reg & CTRL_EXT_LINK_MODE_MASK; |
2372 | switch (link_mode) { | | 2372 | switch (link_mode) { |
2373 | case CTRL_EXT_LINK_MODE_1000KX: | | 2373 | case CTRL_EXT_LINK_MODE_1000KX: |
2374 | aprint_verbose_dev(sc->sc_dev, "1000KX\n"); | | 2374 | aprint_verbose_dev(sc->sc_dev, "1000KX\n"); |
2375 | sc->sc_mediatype = WM_MEDIATYPE_SERDES; | | 2375 | sc->sc_mediatype = WM_MEDIATYPE_SERDES; |
2376 | break; | | 2376 | break; |
2377 | case CTRL_EXT_LINK_MODE_SGMII: | | 2377 | case CTRL_EXT_LINK_MODE_SGMII: |
2378 | if (wm_sgmii_uses_mdio(sc)) { | | 2378 | if (wm_sgmii_uses_mdio(sc)) { |
2379 | aprint_verbose_dev(sc->sc_dev, | | 2379 | aprint_verbose_dev(sc->sc_dev, |
2380 | "SGMII(MDIO)\n"); | | 2380 | "SGMII(MDIO)\n"); |
2381 | sc->sc_flags |= WM_F_SGMII; | | 2381 | sc->sc_flags |= WM_F_SGMII; |
2382 | sc->sc_mediatype = WM_MEDIATYPE_COPPER; | | 2382 | sc->sc_mediatype = WM_MEDIATYPE_COPPER; |
2383 | break; | | 2383 | break; |
2384 | } | | 2384 | } |
2385 | aprint_verbose_dev(sc->sc_dev, "SGMII(I2C)\n"); | | 2385 | aprint_verbose_dev(sc->sc_dev, "SGMII(I2C)\n"); |
2386 | /*FALLTHROUGH*/ | | 2386 | /*FALLTHROUGH*/ |
2387 | case CTRL_EXT_LINK_MODE_PCIE_SERDES: | | 2387 | case CTRL_EXT_LINK_MODE_PCIE_SERDES: |
2388 | sc->sc_mediatype = wm_sfp_get_media_type(sc); | | 2388 | sc->sc_mediatype = wm_sfp_get_media_type(sc); |
2389 | if (sc->sc_mediatype == WM_MEDIATYPE_UNKNOWN) { | | 2389 | if (sc->sc_mediatype == WM_MEDIATYPE_UNKNOWN) { |
2390 | if (link_mode | | 2390 | if (link_mode |
2391 | == CTRL_EXT_LINK_MODE_SGMII) { | | 2391 | == CTRL_EXT_LINK_MODE_SGMII) { |
2392 | sc->sc_mediatype | | 2392 | sc->sc_mediatype |
2393 | = WM_MEDIATYPE_COPPER; | | 2393 | = WM_MEDIATYPE_COPPER; |
2394 | sc->sc_flags |= WM_F_SGMII; | | 2394 | sc->sc_flags |= WM_F_SGMII; |
2395 | } else { | | 2395 | } else { |
2396 | sc->sc_mediatype | | 2396 | sc->sc_mediatype |
2397 | = WM_MEDIATYPE_SERDES; | | 2397 | = WM_MEDIATYPE_SERDES; |
2398 | aprint_verbose_dev(sc->sc_dev, | | 2398 | aprint_verbose_dev(sc->sc_dev, |
2399 | "SERDES\n"); | | 2399 | "SERDES\n"); |
2400 | } | | 2400 | } |
2401 | break; | | 2401 | break; |
2402 | } | | 2402 | } |
2403 | if (sc->sc_mediatype == WM_MEDIATYPE_SERDES) | | 2403 | if (sc->sc_mediatype == WM_MEDIATYPE_SERDES) |
2404 | aprint_verbose_dev(sc->sc_dev, | | 2404 | aprint_verbose_dev(sc->sc_dev, |
2405 | "SERDES\n"); | | 2405 | "SERDES\n"); |
2406 | | | 2406 | |
2407 | /* Change current link mode setting */ | | 2407 | /* Change current link mode setting */ |
2408 | reg &= ~CTRL_EXT_LINK_MODE_MASK; | | 2408 | reg &= ~CTRL_EXT_LINK_MODE_MASK; |
2409 | switch (sc->sc_mediatype) { | | 2409 | switch (sc->sc_mediatype) { |
2410 | case WM_MEDIATYPE_COPPER: | | 2410 | case WM_MEDIATYPE_COPPER: |
2411 | reg |= CTRL_EXT_LINK_MODE_SGMII; | | 2411 | reg |= CTRL_EXT_LINK_MODE_SGMII; |
2412 | break; | | 2412 | break; |
2413 | case WM_MEDIATYPE_SERDES: | | 2413 | case WM_MEDIATYPE_SERDES: |
2414 | reg |= CTRL_EXT_LINK_MODE_PCIE_SERDES; | | 2414 | reg |= CTRL_EXT_LINK_MODE_PCIE_SERDES; |
2415 | break; | | 2415 | break; |
2416 | default: | | 2416 | default: |
2417 | break; | | 2417 | break; |
2418 | } | | 2418 | } |
2419 | CSR_WRITE(sc, WMREG_CTRL_EXT, reg); | | 2419 | CSR_WRITE(sc, WMREG_CTRL_EXT, reg); |
2420 | break; | | 2420 | break; |
2421 | case CTRL_EXT_LINK_MODE_GMII: | | 2421 | case CTRL_EXT_LINK_MODE_GMII: |
2422 | default: | | 2422 | default: |
2423 | aprint_verbose_dev(sc->sc_dev, "Copper\n"); | | 2423 | aprint_verbose_dev(sc->sc_dev, "Copper\n"); |
2424 | sc->sc_mediatype = WM_MEDIATYPE_COPPER; | | 2424 | sc->sc_mediatype = WM_MEDIATYPE_COPPER; |
2425 | break; | | 2425 | break; |
2426 | } | | 2426 | } |
2427 | | | 2427 | |
2428 | reg &= ~CTRL_EXT_I2C_ENA; | | 2428 | reg &= ~CTRL_EXT_I2C_ENA; |
2429 | if ((sc->sc_flags & WM_F_SGMII) != 0) | | 2429 | if ((sc->sc_flags & WM_F_SGMII) != 0) |
2430 | reg |= CTRL_EXT_I2C_ENA; | | 2430 | reg |= CTRL_EXT_I2C_ENA; |
2431 | else | | 2431 | else |
2432 | reg &= ~CTRL_EXT_I2C_ENA; | | 2432 | reg &= ~CTRL_EXT_I2C_ENA; |
2433 | CSR_WRITE(sc, WMREG_CTRL_EXT, reg); | | 2433 | CSR_WRITE(sc, WMREG_CTRL_EXT, reg); |
2434 | | | 2434 | |
2435 | if (sc->sc_mediatype == WM_MEDIATYPE_COPPER) | | 2435 | if (sc->sc_mediatype == WM_MEDIATYPE_COPPER) |
2436 | wm_gmii_mediainit(sc, wmp->wmp_product); | | 2436 | wm_gmii_mediainit(sc, wmp->wmp_product); |
2437 | else | | 2437 | else |
2438 | wm_tbi_mediainit(sc); | | 2438 | wm_tbi_mediainit(sc); |
2439 | break; | | 2439 | break; |
2440 | default: | | 2440 | default: |
2441 | if (sc->sc_mediatype == WM_MEDIATYPE_FIBER) | | 2441 | if (sc->sc_mediatype == WM_MEDIATYPE_FIBER) |
2442 | aprint_error_dev(sc->sc_dev, | | 2442 | aprint_error_dev(sc->sc_dev, |
2443 | "WARNING: TBIMODE clear on 1000BASE-X product!\n"); | | 2443 | "WARNING: TBIMODE clear on 1000BASE-X product!\n"); |
2444 | sc->sc_mediatype = WM_MEDIATYPE_COPPER; | | 2444 | sc->sc_mediatype = WM_MEDIATYPE_COPPER; |
2445 | wm_gmii_mediainit(sc, wmp->wmp_product); | | 2445 | wm_gmii_mediainit(sc, wmp->wmp_product); |
2446 | } | | 2446 | } |
2447 | } | | 2447 | } |
2448 | | | 2448 | |
2449 | ifp = &sc->sc_ethercom.ec_if; | | 2449 | ifp = &sc->sc_ethercom.ec_if; |
2450 | xname = device_xname(sc->sc_dev); | | 2450 | xname = device_xname(sc->sc_dev); |
2451 | strlcpy(ifp->if_xname, xname, IFNAMSIZ); | | 2451 | strlcpy(ifp->if_xname, xname, IFNAMSIZ); |
2452 | ifp->if_softc = sc; | | 2452 | ifp->if_softc = sc; |
2453 | ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; | | 2453 | ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; |
2454 | ifp->if_ioctl = wm_ioctl; | | 2454 | ifp->if_ioctl = wm_ioctl; |
2455 | if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) | | 2455 | if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) |
2456 | ifp->if_start = wm_nq_start; | | 2456 | ifp->if_start = wm_nq_start; |
2457 | else | | 2457 | else |
2458 | ifp->if_start = wm_start; | | 2458 | ifp->if_start = wm_start; |
2459 | ifp->if_watchdog = wm_watchdog; | | 2459 | ifp->if_watchdog = wm_watchdog; |
2460 | ifp->if_init = wm_init; | | 2460 | ifp->if_init = wm_init; |
2461 | ifp->if_stop = wm_stop; | | 2461 | ifp->if_stop = wm_stop; |
2462 | IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN)); | | 2462 | IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN)); |
2463 | IFQ_SET_READY(&ifp->if_snd); | | 2463 | IFQ_SET_READY(&ifp->if_snd); |
2464 | | | 2464 | |
2465 | /* Check for jumbo frame */ | | 2465 | /* Check for jumbo frame */ |
2466 | switch (sc->sc_type) { | | 2466 | switch (sc->sc_type) { |
2467 | case WM_T_82573: | | 2467 | case WM_T_82573: |
2468 | /* XXX limited to 9234 if ASPM is disabled */ | | 2468 | /* XXX limited to 9234 if ASPM is disabled */ |
2469 | wm_nvm_read(sc, NVM_OFF_INIT_3GIO_3, 1, &nvmword); | | 2469 | wm_nvm_read(sc, NVM_OFF_INIT_3GIO_3, 1, &nvmword); |
2470 | if ((nvmword & NVM_3GIO_3_ASPM_MASK) != 0) | | 2470 | if ((nvmword & NVM_3GIO_3_ASPM_MASK) != 0) |
2471 | sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; | | 2471 | sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; |
2472 | break; | | 2472 | break; |
2473 | case WM_T_82571: | | 2473 | case WM_T_82571: |
2474 | case WM_T_82572: | | 2474 | case WM_T_82572: |
2475 | case WM_T_82574: | | 2475 | case WM_T_82574: |
2476 | case WM_T_82575: | | 2476 | case WM_T_82575: |
2477 | case WM_T_82576: | | 2477 | case WM_T_82576: |
2478 | case WM_T_82580: | | 2478 | case WM_T_82580: |
2479 | case WM_T_I350: | | 2479 | case WM_T_I350: |
2480 | case WM_T_I354: /* XXXX ok? */ | | 2480 | case WM_T_I354: /* XXXX ok? */ |
2481 | case WM_T_I210: | | 2481 | case WM_T_I210: |
2482 | case WM_T_I211: | | 2482 | case WM_T_I211: |
2483 | case WM_T_80003: | | 2483 | case WM_T_80003: |
2484 | case WM_T_ICH9: | | 2484 | case WM_T_ICH9: |
2485 | case WM_T_ICH10: | | 2485 | case WM_T_ICH10: |
2486 | case WM_T_PCH2: /* PCH2 supports 9K frame size */ | | 2486 | case WM_T_PCH2: /* PCH2 supports 9K frame size */ |
2487 | case WM_T_PCH_LPT: | | 2487 | case WM_T_PCH_LPT: |
2488 | /* XXX limited to 9234 */ | | 2488 | /* XXX limited to 9234 */ |
2489 | sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; | | 2489 | sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; |
2490 | break; | | 2490 | break; |
2491 | case WM_T_PCH: | | 2491 | case WM_T_PCH: |
2492 | /* XXX limited to 4096 */ | | 2492 | /* XXX limited to 4096 */ |
2493 | sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; | | 2493 | sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; |
2494 | break; | | 2494 | break; |
2495 | case WM_T_82542_2_0: | | 2495 | case WM_T_82542_2_0: |
2496 | case WM_T_82542_2_1: | | 2496 | case WM_T_82542_2_1: |
2497 | case WM_T_82583: | | 2497 | case WM_T_82583: |
2498 | case WM_T_ICH8: | | 2498 | case WM_T_ICH8: |
2499 | /* No support for jumbo frame */ | | 2499 | /* No support for jumbo frame */ |
2500 | break; | | 2500 | break; |
2501 | default: | | 2501 | default: |
2502 | /* ETHER_MAX_LEN_JUMBO */ | | 2502 | /* ETHER_MAX_LEN_JUMBO */ |
2503 | sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; | | 2503 | sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; |
2504 | break; | | 2504 | break; |
2505 | } | | 2505 | } |
2506 | | | 2506 | |
2507 | /* If we're a i82543 or greater, we can support VLANs. */ | | 2507 | /* If we're a i82543 or greater, we can support VLANs. */ |
2508 | if (sc->sc_type >= WM_T_82543) | | 2508 | if (sc->sc_type >= WM_T_82543) |
2509 | sc->sc_ethercom.ec_capabilities |= | | 2509 | sc->sc_ethercom.ec_capabilities |= |
2510 | ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; | | 2510 | ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; |
2511 | | | 2511 | |
2512 | /* | | 2512 | /* |
2513 | * We can perform TCPv4 and UDPv4 checkums in-bound. Only | | 2513 | * We can perform TCPv4 and UDPv4 checkums in-bound. Only |
2514 | * on i82543 and later. | | 2514 | * on i82543 and later. |
2515 | */ | | 2515 | */ |
2516 | if (sc->sc_type >= WM_T_82543) { | | 2516 | if (sc->sc_type >= WM_T_82543) { |
2517 | ifp->if_capabilities |= | | 2517 | ifp->if_capabilities |= |
2518 | IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | | | 2518 | IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | |
2519 | IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | | | 2519 | IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | |
2520 | IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | | | 2520 | IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | |
2521 | IFCAP_CSUM_TCPv6_Tx | | | 2521 | IFCAP_CSUM_TCPv6_Tx | |
2522 | IFCAP_CSUM_UDPv6_Tx; | | 2522 | IFCAP_CSUM_UDPv6_Tx; |
2523 | } | | 2523 | } |
2524 | | | 2524 | |
2525 | /* | | 2525 | /* |
2526 | * XXXyamt: i'm not sure which chips support RXCSUM_IPV6OFL. | | 2526 | * XXXyamt: i'm not sure which chips support RXCSUM_IPV6OFL. |
2527 | * | | 2527 | * |
2528 | * 82541GI (8086:1076) ... no | | 2528 | * 82541GI (8086:1076) ... no |
2529 | * 82572EI (8086:10b9) ... yes | | 2529 | * 82572EI (8086:10b9) ... yes |
2530 | */ | | 2530 | */ |
2531 | if (sc->sc_type >= WM_T_82571) { | | 2531 | if (sc->sc_type >= WM_T_82571) { |
2532 | ifp->if_capabilities |= | | 2532 | ifp->if_capabilities |= |
2533 | IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; | | 2533 | IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; |
2534 | } | | 2534 | } |
2535 | | | 2535 | |
2536 | /* | | 2536 | /* |
2537 | * If we're a i82544 or greater (except i82547), we can do | | 2537 | * If we're a i82544 or greater (except i82547), we can do |
2538 | * TCP segmentation offload. | | 2538 | * TCP segmentation offload. |
2539 | */ | | 2539 | */ |
2540 | if (sc->sc_type >= WM_T_82544 && sc->sc_type != WM_T_82547) { | | 2540 | if (sc->sc_type >= WM_T_82544 && sc->sc_type != WM_T_82547) { |
2541 | ifp->if_capabilities |= IFCAP_TSOv4; | | 2541 | ifp->if_capabilities |= IFCAP_TSOv4; |
2542 | } | | 2542 | } |
2543 | | | 2543 | |
2544 | if (sc->sc_type >= WM_T_82571) { | | 2544 | if (sc->sc_type >= WM_T_82571) { |
2545 | ifp->if_capabilities |= IFCAP_TSOv6; | | 2545 | ifp->if_capabilities |= IFCAP_TSOv6; |
2546 | } | | 2546 | } |
2547 | | | 2547 | |
2548 | #ifdef WM_MPSAFE | | 2548 | #ifdef WM_MPSAFE |
2549 | sc->sc_core_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET); | | 2549 | sc->sc_core_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET); |
2550 | #else | | 2550 | #else |
2551 | sc->sc_core_lock = NULL; | | 2551 | sc->sc_core_lock = NULL; |
2552 | #endif | | 2552 | #endif |
2553 | | | 2553 | |
2554 | /* Attach the interface. */ | | 2554 | /* Attach the interface. */ |
2555 | if_attach(ifp); | | 2555 | if_attach(ifp); |
2556 | ether_ifattach(ifp, enaddr); | | 2556 | ether_ifattach(ifp, enaddr); |
2557 | ether_set_ifflags_cb(&sc->sc_ethercom, wm_ifflags_cb); | | 2557 | ether_set_ifflags_cb(&sc->sc_ethercom, wm_ifflags_cb); |
2558 | rnd_attach_source(&sc->rnd_source, xname, RND_TYPE_NET, | | 2558 | rnd_attach_source(&sc->rnd_source, xname, RND_TYPE_NET, |
2559 | RND_FLAG_DEFAULT); | | 2559 | RND_FLAG_DEFAULT); |
2560 | | | 2560 | |
2561 | #ifdef WM_EVENT_COUNTERS | | 2561 | #ifdef WM_EVENT_COUNTERS |
2562 | /* Attach event counters. */ | | 2562 | /* Attach event counters. */ |
2563 | evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, | | 2563 | evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, |
2564 | NULL, xname, "txsstall"); | | 2564 | NULL, xname, "txsstall"); |
2565 | evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, | | 2565 | evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, |
2566 | NULL, xname, "txdstall"); | | 2566 | NULL, xname, "txdstall"); |
2567 | evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC, | | 2567 | evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC, |
2568 | NULL, xname, "txfifo_stall"); | | 2568 | NULL, xname, "txfifo_stall"); |
2569 | evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, | | 2569 | evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, |
2570 | NULL, xname, "txdw"); | | 2570 | NULL, xname, "txdw"); |
2571 | evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, | | 2571 | evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, |
2572 | NULL, xname, "txqe"); | | 2572 | NULL, xname, "txqe"); |
2573 | evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, | | 2573 | evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, |
2574 | NULL, xname, "rxintr"); | | 2574 | NULL, xname, "rxintr"); |
2575 | evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, | | 2575 | evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, |
2576 | NULL, xname, "linkintr"); | | 2576 | NULL, xname, "linkintr"); |
2577 | | | 2577 | |
2578 | evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, | | 2578 | evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, |
2579 | NULL, xname, "rxipsum"); | | 2579 | NULL, xname, "rxipsum"); |
2580 | evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, | | 2580 | evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, |
2581 | NULL, xname, "rxtusum"); | | 2581 | NULL, xname, "rxtusum"); |
2582 | evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, | | 2582 | evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, |
2583 | NULL, xname, "txipsum"); | | 2583 | NULL, xname, "txipsum"); |
2584 | evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, | | 2584 | evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, |
2585 | NULL, xname, "txtusum"); | | 2585 | NULL, xname, "txtusum"); |
2586 | evcnt_attach_dynamic(&sc->sc_ev_txtusum6, EVCNT_TYPE_MISC, | | 2586 | evcnt_attach_dynamic(&sc->sc_ev_txtusum6, EVCNT_TYPE_MISC, |
2587 | NULL, xname, "txtusum6"); | | 2587 | NULL, xname, "txtusum6"); |
2588 | | | 2588 | |
2589 | evcnt_attach_dynamic(&sc->sc_ev_txtso, EVCNT_TYPE_MISC, | | 2589 | evcnt_attach_dynamic(&sc->sc_ev_txtso, EVCNT_TYPE_MISC, |
2590 | NULL, xname, "txtso"); | | 2590 | NULL, xname, "txtso"); |
2591 | evcnt_attach_dynamic(&sc->sc_ev_txtso6, EVCNT_TYPE_MISC, | | 2591 | evcnt_attach_dynamic(&sc->sc_ev_txtso6, EVCNT_TYPE_MISC, |
2592 | NULL, xname, "txtso6"); | | 2592 | NULL, xname, "txtso6"); |
2593 | evcnt_attach_dynamic(&sc->sc_ev_txtsopain, EVCNT_TYPE_MISC, | | 2593 | evcnt_attach_dynamic(&sc->sc_ev_txtsopain, EVCNT_TYPE_MISC, |
2594 | NULL, xname, "txtsopain"); | | 2594 | NULL, xname, "txtsopain"); |
2595 | | | 2595 | |
2596 | for (i = 0; i < WM_NTXSEGS; i++) { | | 2596 | for (i = 0; i < WM_NTXSEGS; i++) { |
2597 | snprintf(wm_txseg_evcnt_names[i], | | 2597 | snprintf(wm_txseg_evcnt_names[i], |
2598 | sizeof(wm_txseg_evcnt_names[i]), "txseg%d", i); | | 2598 | sizeof(wm_txseg_evcnt_names[i]), "txseg%d", i); |
2599 | evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, | | 2599 | evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, |
2600 | NULL, xname, wm_txseg_evcnt_names[i]); | | 2600 | NULL, xname, wm_txseg_evcnt_names[i]); |
2601 | } | | 2601 | } |
2602 | | | 2602 | |
2603 | evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, | | 2603 | evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, |
2604 | NULL, xname, "txdrop"); | | 2604 | NULL, xname, "txdrop"); |
2605 | | | 2605 | |
2606 | evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, | | 2606 | evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, |
2607 | NULL, xname, "tu"); | | 2607 | NULL, xname, "tu"); |
2608 | | | 2608 | |
2609 | evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC, | | 2609 | evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC, |
2610 | NULL, xname, "tx_xoff"); | | 2610 | NULL, xname, "tx_xoff"); |
2611 | evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC, | | 2611 | evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC, |
2612 | NULL, xname, "tx_xon"); | | 2612 | NULL, xname, "tx_xon"); |
2613 | evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC, | | 2613 | evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC, |
2614 | NULL, xname, "rx_xoff"); | | 2614 | NULL, xname, "rx_xoff"); |
2615 | evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC, | | 2615 | evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC, |
2616 | NULL, xname, "rx_xon"); | | 2616 | NULL, xname, "rx_xon"); |
2617 | evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC, | | 2617 | evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC, |
2618 | NULL, xname, "rx_macctl"); | | 2618 | NULL, xname, "rx_macctl"); |
2619 | #endif /* WM_EVENT_COUNTERS */ | | 2619 | #endif /* WM_EVENT_COUNTERS */ |
2620 | | | 2620 | |
2621 | if (pmf_device_register(self, wm_suspend, wm_resume)) | | 2621 | if (pmf_device_register(self, wm_suspend, wm_resume)) |
2622 | pmf_class_network_register(self, ifp); | | 2622 | pmf_class_network_register(self, ifp); |
2623 | else | | 2623 | else |
2624 | aprint_error_dev(self, "couldn't establish power handler\n"); | | 2624 | aprint_error_dev(self, "couldn't establish power handler\n"); |
2625 | | | 2625 | |
2626 | sc->sc_flags |= WM_F_ATTACHED; | | 2626 | sc->sc_flags |= WM_F_ATTACHED; |
2627 | out: | | 2627 | out: |
2628 | return; | | 2628 | return; |
2629 | } | | 2629 | } |
2630 | | | 2630 | |
2631 | /* The detach function (ca_detach) */ | | 2631 | /* The detach function (ca_detach) */ |
2632 | static int | | 2632 | static int |
2633 | wm_detach(device_t self, int flags __unused) | | 2633 | wm_detach(device_t self, int flags __unused) |
2634 | { | | 2634 | { |
2635 | struct wm_softc *sc = device_private(self); | | 2635 | struct wm_softc *sc = device_private(self); |
2636 | struct wm_rxqueue *rxq = sc->sc_rxq; | | 2636 | struct wm_rxqueue *rxq = sc->sc_rxq; |
2637 | struct ifnet *ifp = &sc->sc_ethercom.ec_if; | | 2637 | struct ifnet *ifp = &sc->sc_ethercom.ec_if; |
2638 | int i; | | 2638 | int i; |
2639 | #ifndef WM_MPSAFE | | 2639 | #ifndef WM_MPSAFE |
2640 | int s; | | 2640 | int s; |
2641 | #endif | | 2641 | #endif |
2642 | | | 2642 | |
2643 | if ((sc->sc_flags & WM_F_ATTACHED) == 0) | | 2643 | if ((sc->sc_flags & WM_F_ATTACHED) == 0) |
2644 | return 0; | | 2644 | return 0; |
2645 | | | 2645 | |
2646 | #ifndef WM_MPSAFE | | 2646 | #ifndef WM_MPSAFE |
2647 | s = splnet(); | | 2647 | s = splnet(); |
2648 | #endif | | 2648 | #endif |
2649 | /* Stop the interface. Callouts are stopped in it. */ | | 2649 | /* Stop the interface. Callouts are stopped in it. */ |
2650 | wm_stop(ifp, 1); | | 2650 | wm_stop(ifp, 1); |
2651 | | | 2651 | |
2652 | #ifndef WM_MPSAFE | | 2652 | #ifndef WM_MPSAFE |
2653 | splx(s); | | 2653 | splx(s); |
2654 | #endif | | 2654 | #endif |
2655 | | | 2655 | |
2656 | pmf_device_deregister(self); | | 2656 | pmf_device_deregister(self); |
2657 | | | 2657 | |
2658 | /* Tell the firmware about the release */ | | 2658 | /* Tell the firmware about the release */ |
2659 | WM_CORE_LOCK(sc); | | 2659 | WM_CORE_LOCK(sc); |
2660 | wm_release_manageability(sc); | | 2660 | wm_release_manageability(sc); |
2661 | wm_release_hw_control(sc); | | 2661 | wm_release_hw_control(sc); |
2662 | WM_CORE_UNLOCK(sc); | | 2662 | WM_CORE_UNLOCK(sc); |
2663 | | | 2663 | |
2664 | mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); | | 2664 | mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); |
2665 | | | 2665 | |
2666 | /* Delete all remaining media. */ | | 2666 | /* Delete all remaining media. */ |
2667 | ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); | | 2667 | ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); |
2668 | | | 2668 | |
2669 | ether_ifdetach(ifp); | | 2669 | ether_ifdetach(ifp); |
2670 | if_detach(ifp); | | 2670 | if_detach(ifp); |
2671 | | | 2671 | |
2672 | | | 2672 | |
2673 | /* Unload RX dmamaps and free mbufs */ | | 2673 | /* Unload RX dmamaps and free mbufs */ |
2674 | WM_RX_LOCK(rxq); | | 2674 | WM_RX_LOCK(rxq); |
2675 | wm_rxdrain(sc); | | 2675 | wm_rxdrain(sc); |
2676 | WM_RX_UNLOCK(rxq); | | 2676 | WM_RX_UNLOCK(rxq); |
2677 | /* Must unlock here */ | | 2677 | /* Must unlock here */ |
2678 | | | 2678 | |
2679 | wm_free_txrx_queues(sc); | | 2679 | wm_free_txrx_queues(sc); |
2680 | | | 2680 | |
2681 | /* Disestablish the interrupt handler */ | | 2681 | /* Disestablish the interrupt handler */ |
2682 | for (i = 0; i < sc->sc_nintrs; i++) { | | 2682 | for (i = 0; i < sc->sc_nintrs; i++) { |
2683 | if (sc->sc_ihs[i] != NULL) { | | 2683 | if (sc->sc_ihs[i] != NULL) { |
2684 | pci_intr_disestablish(sc->sc_pc, sc->sc_ihs[i]); | | 2684 | pci_intr_disestablish(sc->sc_pc, sc->sc_ihs[i]); |
2685 | sc->sc_ihs[i] = NULL; | | 2685 | sc->sc_ihs[i] = NULL; |
2686 | } | | 2686 | } |
2687 | } | | 2687 | } |
2688 | #ifdef WM_MSI_MSIX | | 2688 | #ifdef WM_MSI_MSIX |
2689 | pci_intr_release(sc->sc_pc, sc->sc_intrs, sc->sc_nintrs); | | 2689 | pci_intr_release(sc->sc_pc, sc->sc_intrs, sc->sc_nintrs); |
2690 | #endif /* WM_MSI_MSIX */ | | 2690 | #endif /* WM_MSI_MSIX */ |
2691 | | | 2691 | |
2692 | /* Unmap the registers */ | | 2692 | /* Unmap the registers */ |
2693 | if (sc->sc_ss) { | | 2693 | if (sc->sc_ss) { |
2694 | bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_ss); | | 2694 | bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_ss); |
2695 | sc->sc_ss = 0; | | 2695 | sc->sc_ss = 0; |
2696 | } | | 2696 | } |
2697 | if (sc->sc_ios) { | | 2697 | if (sc->sc_ios) { |
2698 | bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); | | 2698 | bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); |
2699 | sc->sc_ios = 0; | | 2699 | sc->sc_ios = 0; |
2700 | } | | 2700 | } |
2701 | if (sc->sc_flashs) { | | 2701 | if (sc->sc_flashs) { |
2702 | bus_space_unmap(sc->sc_flasht, sc->sc_flashh, sc->sc_flashs); | | 2702 | bus_space_unmap(sc->sc_flasht, sc->sc_flashh, sc->sc_flashs); |
2703 | sc->sc_flashs = 0; | | 2703 | sc->sc_flashs = 0; |
2704 | } | | 2704 | } |
2705 | | | 2705 | |
2706 | if (sc->sc_core_lock) | | 2706 | if (sc->sc_core_lock) |
2707 | mutex_obj_free(sc->sc_core_lock); | | 2707 | mutex_obj_free(sc->sc_core_lock); |
2708 | | | 2708 | |
2709 | return 0; | | 2709 | return 0; |
2710 | } | | 2710 | } |
2711 | | | 2711 | |
2712 | static bool | | 2712 | static bool |
2713 | wm_suspend(device_t self, const pmf_qual_t *qual) | | 2713 | wm_suspend(device_t self, const pmf_qual_t *qual) |
2714 | { | | 2714 | { |
2715 | struct wm_softc *sc = device_private(self); | | 2715 | struct wm_softc *sc = device_private(self); |
2716 | | | 2716 | |
2717 | wm_release_manageability(sc); | | 2717 | wm_release_manageability(sc); |
2718 | wm_release_hw_control(sc); | | 2718 | wm_release_hw_control(sc); |
2719 | #ifdef WM_WOL | | 2719 | #ifdef WM_WOL |
2720 | wm_enable_wakeup(sc); | | 2720 | wm_enable_wakeup(sc); |
2721 | #endif | | 2721 | #endif |
2722 | | | 2722 | |
2723 | return true; | | 2723 | return true; |
2724 | } | | 2724 | } |
2725 | | | 2725 | |
2726 | static bool | | 2726 | static bool |
2727 | wm_resume(device_t self, const pmf_qual_t *qual) | | 2727 | wm_resume(device_t self, const pmf_qual_t *qual) |
2728 | { | | 2728 | { |
2729 | struct wm_softc *sc = device_private(self); | | 2729 | struct wm_softc *sc = device_private(self); |
2730 | | | 2730 | |
2731 | wm_init_manageability(sc); | | 2731 | wm_init_manageability(sc); |
2732 | | | 2732 | |
2733 | return true; | | 2733 | return true; |
2734 | } | | 2734 | } |
2735 | | | 2735 | |
2736 | /* | | 2736 | /* |
2737 | * wm_watchdog: [ifnet interface function] | | 2737 | * wm_watchdog: [ifnet interface function] |
2738 | * | | 2738 | * |
2739 | * Watchdog timer handler. | | 2739 | * Watchdog timer handler. |
2740 | */ | | 2740 | */ |
2741 | static void | | 2741 | static void |
2742 | wm_watchdog(struct ifnet *ifp) | | 2742 | wm_watchdog(struct ifnet *ifp) |
2743 | { | | 2743 | { |
2744 | struct wm_softc *sc = ifp->if_softc; | | 2744 | struct wm_softc *sc = ifp->if_softc; |
2745 | struct wm_txqueue *txq = sc->sc_txq; | | 2745 | struct wm_txqueue *txq = sc->sc_txq; |
2746 | | | 2746 | |
2747 | /* | | 2747 | /* |
2748 | * Since we're using delayed interrupts, sweep up | | 2748 | * Since we're using delayed interrupts, sweep up |
2749 | * before we report an error. | | 2749 | * before we report an error. |
2750 | */ | | 2750 | */ |
2751 | WM_TX_LOCK(txq); | | 2751 | WM_TX_LOCK(txq); |
2752 | wm_txeof(sc); | | 2752 | wm_txeof(sc); |
2753 | WM_TX_UNLOCK(txq); | | 2753 | WM_TX_UNLOCK(txq); |
2754 | | | 2754 | |
2755 | if (txq->txq_free != WM_NTXDESC(txq)) { | | 2755 | if (txq->txq_free != WM_NTXDESC(txq)) { |
2756 | #ifdef WM_DEBUG | | 2756 | #ifdef WM_DEBUG |
2757 | int i, j; | | 2757 | int i, j; |
2758 | struct wm_txsoft *txs; | | 2758 | struct wm_txsoft *txs; |
2759 | #endif | | 2759 | #endif |
2760 | log(LOG_ERR, | | 2760 | log(LOG_ERR, |
2761 | "%s: device timeout (txfree %d txsfree %d txnext %d)\n", | | 2761 | "%s: device timeout (txfree %d txsfree %d txnext %d)\n", |
2762 | device_xname(sc->sc_dev), txq->txq_free, txq->txq_sfree, | | 2762 | device_xname(sc->sc_dev), txq->txq_free, txq->txq_sfree, |
2763 | txq->txq_next); | | 2763 | txq->txq_next); |
2764 | ifp->if_oerrors++; | | 2764 | ifp->if_oerrors++; |
2765 | #ifdef WM_DEBUG | | 2765 | #ifdef WM_DEBUG |
2766 | for (i = txq->txq_txsdirty; i != txq->txq_txsnext ; | | 2766 | for (i = txq->txq_txsdirty; i != txq->txq_txsnext ; |
2767 | i = WM_NEXTTXS(txq, i)) { | | 2767 | i = WM_NEXTTXS(txq, i)) { |
2768 | txs = &txq->txq_txsoft[i]; | | 2768 | txs = &txq->txq_txsoft[i]; |
2769 | printf("txs %d tx %d -> %d\n", | | 2769 | printf("txs %d tx %d -> %d\n", |
2770 | i, txs->txs_firstdesc, txs->txs_lastdesc); | | 2770 | i, txs->txs_firstdesc, txs->txs_lastdesc); |
2771 | for (j = txs->txs_firstdesc; ; | | 2771 | for (j = txs->txs_firstdesc; ; |
2772 | j = WM_NEXTTX(txq, j)) { | | 2772 | j = WM_NEXTTX(txq, j)) { |
2773 | printf("\tdesc %d: 0x%" PRIx64 "\n", j, | | 2773 | printf("\tdesc %d: 0x%" PRIx64 "\n", j, |
2774 | txq->txq_nq_txdescs[j].nqtx_data.nqtxd_addr); | | 2774 | txq->txq_nq_txdescs[j].nqtx_data.nqtxd_addr); |
2775 | printf("\t %#08x%08x\n", | | 2775 | printf("\t %#08x%08x\n", |
2776 | txq->txq_nq_txdescs[j].nqtx_data.nqtxd_fields, | | 2776 | txq->txq_nq_txdescs[j].nqtx_data.nqtxd_fields, |
2777 | txq->txq_nq_txdescs[j].nqtx_data.nqtxd_cmdlen); | | 2777 | txq->txq_nq_txdescs[j].nqtx_data.nqtxd_cmdlen); |
2778 | if (j == txs->txs_lastdesc) | | 2778 | if (j == txs->txs_lastdesc) |
2779 | break; | | 2779 | break; |
2780 | } | | 2780 | } |
2781 | } | | 2781 | } |
2782 | #endif | | 2782 | #endif |
2783 | /* Reset the interface. */ | | 2783 | /* Reset the interface. */ |
2784 | (void) wm_init(ifp); | | 2784 | (void) wm_init(ifp); |
2785 | } | | 2785 | } |
2786 | | | 2786 | |
2787 | /* Try to get more packets going. */ | | 2787 | /* Try to get more packets going. */ |
2788 | ifp->if_start(ifp); | | 2788 | ifp->if_start(ifp); |
2789 | } | | 2789 | } |
2790 | | | 2790 | |
2791 | /* | | 2791 | /* |
2792 | * wm_tick: | | 2792 | * wm_tick: |
2793 | * | | 2793 | * |
2794 | * One second timer, used to check link status, sweep up | | 2794 | * One second timer, used to check link status, sweep up |
2795 | * completed transmit jobs, etc. | | 2795 | * completed transmit jobs, etc. |
2796 | */ | | 2796 | */ |
2797 | static void | | 2797 | static void |
2798 | wm_tick(void *arg) | | 2798 | wm_tick(void *arg) |
2799 | { | | 2799 | { |
2800 | struct wm_softc *sc = arg; | | 2800 | struct wm_softc *sc = arg; |
2801 | struct ifnet *ifp = &sc->sc_ethercom.ec_if; | | 2801 | struct ifnet *ifp = &sc->sc_ethercom.ec_if; |
2802 | #ifndef WM_MPSAFE | | 2802 | #ifndef WM_MPSAFE |
2803 | int s; | | 2803 | int s; |
2804 | | | 2804 | |
2805 | s = splnet(); | | 2805 | s = splnet(); |
2806 | #endif | | 2806 | #endif |
2807 | | | 2807 | |
2808 | WM_CORE_LOCK(sc); | | 2808 | WM_CORE_LOCK(sc); |
2809 | | | 2809 | |
2810 | if (sc->sc_stopping) | | 2810 | if (sc->sc_stopping) |
2811 | goto out; | | 2811 | goto out; |
2812 | | | 2812 | |
2813 | if (sc->sc_type >= WM_T_82542_2_1) { | | 2813 | if (sc->sc_type >= WM_T_82542_2_1) { |
2814 | WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC)); | | 2814 | WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC)); |
2815 | WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC)); | | 2815 | WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC)); |
2816 | WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC)); | | 2816 | WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC)); |
2817 | WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC)); | | 2817 | WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC)); |
2818 | WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC)); | | 2818 | WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC)); |
2819 | } | | 2819 | } |
2820 | | | 2820 | |
2821 | ifp->if_collisions += CSR_READ(sc, WMREG_COLC); | | 2821 | ifp->if_collisions += CSR_READ(sc, WMREG_COLC); |
2822 | ifp->if_ierrors += 0ULL + /* ensure quad_t */ | | 2822 | ifp->if_ierrors += 0ULL + /* ensure quad_t */ |
2823 | + CSR_READ(sc, WMREG_CRCERRS) | | 2823 | + CSR_READ(sc, WMREG_CRCERRS) |
2824 | + CSR_READ(sc, WMREG_ALGNERRC) | | 2824 | + CSR_READ(sc, WMREG_ALGNERRC) |
2825 | + CSR_READ(sc, WMREG_SYMERRC) | | 2825 | + CSR_READ(sc, WMREG_SYMERRC) |
2826 | + CSR_READ(sc, WMREG_RXERRC) | | 2826 | + CSR_READ(sc, WMREG_RXERRC) |
2827 | + CSR_READ(sc, WMREG_SEC) | | 2827 | + CSR_READ(sc, WMREG_SEC) |
2828 | + CSR_READ(sc, WMREG_CEXTERR) | | 2828 | + CSR_READ(sc, WMREG_CEXTERR) |
2829 | + CSR_READ(sc, WMREG_RLEC); | | 2829 | + CSR_READ(sc, WMREG_RLEC); |
2830 | ifp->if_iqdrops += CSR_READ(sc, WMREG_MPC) + CSR_READ(sc, WMREG_RNBC); | | 2830 | ifp->if_iqdrops += CSR_READ(sc, WMREG_MPC) + CSR_READ(sc, WMREG_RNBC); |
2831 | | | 2831 | |
2832 | if (sc->sc_flags & WM_F_HAS_MII) | | 2832 | if (sc->sc_flags & WM_F_HAS_MII) |
2833 | mii_tick(&sc->sc_mii); | | 2833 | mii_tick(&sc->sc_mii); |
2834 | else if ((sc->sc_type >= WM_T_82575) | | 2834 | else if ((sc->sc_type >= WM_T_82575) |
2835 | && (sc->sc_mediatype == WM_MEDIATYPE_SERDES)) | | 2835 | && (sc->sc_mediatype == WM_MEDIATYPE_SERDES)) |
2836 | wm_serdes_tick(sc); | | 2836 | wm_serdes_tick(sc); |
2837 | else | | 2837 | else |
2838 | wm_tbi_tick(sc); | | 2838 | wm_tbi_tick(sc); |
2839 | | | 2839 | |
2840 | out: | | 2840 | out: |
2841 | WM_CORE_UNLOCK(sc); | | 2841 | WM_CORE_UNLOCK(sc); |
2842 | #ifndef WM_MPSAFE | | 2842 | #ifndef WM_MPSAFE |
2843 | splx(s); | | 2843 | splx(s); |
2844 | #endif | | 2844 | #endif |
2845 | | | 2845 | |
2846 | if (!sc->sc_stopping) | | 2846 | if (!sc->sc_stopping) |
2847 | callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); | | 2847 | callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); |
2848 | } | | 2848 | } |
2849 | | | 2849 | |
2850 | static int | | 2850 | static int |
2851 | wm_ifflags_cb(struct ethercom *ec) | | 2851 | wm_ifflags_cb(struct ethercom *ec) |
2852 | { | | 2852 | { |
2853 | struct ifnet *ifp = &ec->ec_if; | | 2853 | struct ifnet *ifp = &ec->ec_if; |
2854 | struct wm_softc *sc = ifp->if_softc; | | 2854 | struct wm_softc *sc = ifp->if_softc; |
2855 | int change = ifp->if_flags ^ sc->sc_if_flags; | | 2855 | int change = ifp->if_flags ^ sc->sc_if_flags; |
2856 | int rc = 0; | | 2856 | int rc = 0; |
2857 | | | 2857 | |
2858 | WM_CORE_LOCK(sc); | | 2858 | WM_CORE_LOCK(sc); |
2859 | | | 2859 | |
2860 | if (change != 0) | | 2860 | if (change != 0) |
2861 | sc->sc_if_flags = ifp->if_flags; | | 2861 | sc->sc_if_flags = ifp->if_flags; |
2862 | | | 2862 | |
2863 | if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) { | | 2863 | if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) { |
2864 | rc = ENETRESET; | | 2864 | rc = ENETRESET; |
2865 | goto out; | | 2865 | goto out; |
2866 | } | | 2866 | } |
2867 | | | 2867 | |
2868 | if ((change & (IFF_PROMISC | IFF_ALLMULTI)) != 0) | | 2868 | if ((change & (IFF_PROMISC | IFF_ALLMULTI)) != 0) |
2869 | wm_set_filter(sc); | | 2869 | wm_set_filter(sc); |
2870 | | | 2870 | |
2871 | wm_set_vlan(sc); | | 2871 | wm_set_vlan(sc); |
2872 | | | 2872 | |
2873 | out: | | 2873 | out: |
2874 | WM_CORE_UNLOCK(sc); | | 2874 | WM_CORE_UNLOCK(sc); |
2875 | | | 2875 | |
2876 | return rc; | | 2876 | return rc; |
2877 | } | | 2877 | } |
2878 | | | 2878 | |
2879 | /* | | 2879 | /* |
2880 | * wm_ioctl: [ifnet interface function] | | 2880 | * wm_ioctl: [ifnet interface function] |
2881 | * | | 2881 | * |
2882 | * Handle control requests from the operator. | | 2882 | * Handle control requests from the operator. |
2883 | */ | | 2883 | */ |
2884 | static int | | 2884 | static int |
2885 | wm_ioctl(struct ifnet *ifp, u_long cmd, void *data) | | 2885 | wm_ioctl(struct ifnet *ifp, u_long cmd, void *data) |
2886 | { | | 2886 | { |
2887 | struct wm_softc *sc = ifp->if_softc; | | 2887 | struct wm_softc *sc = ifp->if_softc; |
2888 | struct ifreq *ifr = (struct ifreq *) data; | | 2888 | struct ifreq *ifr = (struct ifreq *) data; |
2889 | struct ifaddr *ifa = (struct ifaddr *)data; | | 2889 | struct ifaddr *ifa = (struct ifaddr *)data; |
2890 | struct sockaddr_dl *sdl; | | 2890 | struct sockaddr_dl *sdl; |
2891 | int s, error; | | 2891 | int s, error; |
2892 | | | 2892 | |
2893 | #ifndef WM_MPSAFE | | 2893 | #ifndef WM_MPSAFE |
2894 | s = splnet(); | | 2894 | s = splnet(); |
2895 | #endif | | 2895 | #endif |
2896 | switch (cmd) { | | 2896 | switch (cmd) { |
2897 | case SIOCSIFMEDIA: | | 2897 | case SIOCSIFMEDIA: |
2898 | case SIOCGIFMEDIA: | | 2898 | case SIOCGIFMEDIA: |
2899 | WM_CORE_LOCK(sc); | | 2899 | WM_CORE_LOCK(sc); |
2900 | /* Flow control requires full-duplex mode. */ | | 2900 | /* Flow control requires full-duplex mode. */ |
2901 | if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || | | 2901 | if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || |