| @@ -1,2772 +1,2701 @@ | | | @@ -1,2772 +1,2701 @@ |
1 | /* $NetBSD: if_wm.c,v 1.359 2015/10/13 08:17:15 knakahara Exp $ */ | | 1 | /* $NetBSD: if_wm.c,v 1.360 2015/10/13 08:20:02 knakahara Exp $ */ |
2 | | | 2 | |
3 | /* | | 3 | /* |
4 | * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc. | | 4 | * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc. |
5 | * All rights reserved. | | 5 | * All rights reserved. |
6 | * | | 6 | * |
7 | * Written by Jason R. Thorpe for Wasabi Systems, Inc. | | 7 | * Written by Jason R. Thorpe for Wasabi Systems, Inc. |
8 | * | | 8 | * |
9 | * Redistribution and use in source and binary forms, with or without | | 9 | * Redistribution and use in source and binary forms, with or without |
10 | * modification, are permitted provided that the following conditions | | 10 | * modification, are permitted provided that the following conditions |
11 | * are met: | | 11 | * are met: |
12 | * 1. Redistributions of source code must retain the above copyright | | 12 | * 1. Redistributions of source code must retain the above copyright |
13 | * notice, this list of conditions and the following disclaimer. | | 13 | * notice, this list of conditions and the following disclaimer. |
14 | * 2. Redistributions in binary form must reproduce the above copyright | | 14 | * 2. Redistributions in binary form must reproduce the above copyright |
15 | * notice, this list of conditions and the following disclaimer in the | | 15 | * notice, this list of conditions and the following disclaimer in the |
16 | * documentation and/or other materials provided with the distribution. | | 16 | * documentation and/or other materials provided with the distribution. |
17 | * 3. All advertising materials mentioning features or use of this software | | 17 | * 3. All advertising materials mentioning features or use of this software |
18 | * must display the following acknowledgement: | | 18 | * must display the following acknowledgement: |
19 | * This product includes software developed for the NetBSD Project by | | 19 | * This product includes software developed for the NetBSD Project by |
20 | * Wasabi Systems, Inc. | | 20 | * Wasabi Systems, Inc. |
21 | * 4. The name of Wasabi Systems, Inc. may not be used to endorse | | 21 | * 4. The name of Wasabi Systems, Inc. may not be used to endorse |
22 | * or promote products derived from this software without specific prior | | 22 | * or promote products derived from this software without specific prior |
23 | * written permission. | | 23 | * written permission. |
24 | * | | 24 | * |
25 | * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND | | 25 | * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND |
26 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED | | 26 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
27 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | | 27 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
28 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC | | 28 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC |
29 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | | 29 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
30 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | | 30 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
31 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | | 31 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
32 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | | 32 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
33 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | | 33 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
34 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | | 34 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
35 | * POSSIBILITY OF SUCH DAMAGE. | | 35 | * POSSIBILITY OF SUCH DAMAGE. |
36 | */ | | 36 | */ |
37 | | | 37 | |
38 | /******************************************************************************* | | 38 | /******************************************************************************* |
39 | | | 39 | |
40 | Copyright (c) 2001-2005, Intel Corporation | | 40 | Copyright (c) 2001-2005, Intel Corporation |
41 | All rights reserved. | | 41 | All rights reserved. |
42 | | | 42 | |
43 | Redistribution and use in source and binary forms, with or without | | 43 | Redistribution and use in source and binary forms, with or without |
44 | modification, are permitted provided that the following conditions are met: | | 44 | modification, are permitted provided that the following conditions are met: |
45 | | | 45 | |
46 | 1. Redistributions of source code must retain the above copyright notice, | | 46 | 1. Redistributions of source code must retain the above copyright notice, |
47 | this list of conditions and the following disclaimer. | | 47 | this list of conditions and the following disclaimer. |
48 | | | 48 | |
49 | 2. Redistributions in binary form must reproduce the above copyright | | 49 | 2. Redistributions in binary form must reproduce the above copyright |
50 | notice, this list of conditions and the following disclaimer in the | | 50 | notice, this list of conditions and the following disclaimer in the |
51 | documentation and/or other materials provided with the distribution. | | 51 | documentation and/or other materials provided with the distribution. |
52 | | | 52 | |
53 | 3. Neither the name of the Intel Corporation nor the names of its | | 53 | 3. Neither the name of the Intel Corporation nor the names of its |
54 | contributors may be used to endorse or promote products derived from | | 54 | contributors may be used to endorse or promote products derived from |
55 | this software without specific prior written permission. | | 55 | this software without specific prior written permission. |
56 | | | 56 | |
57 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | | 57 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
58 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | | 58 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
59 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | | 59 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
60 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | | 60 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
61 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | | 61 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
62 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | | 62 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
63 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | | 63 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
64 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | | 64 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
65 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | | 65 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
66 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | | 66 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
67 | POSSIBILITY OF SUCH DAMAGE. | | 67 | POSSIBILITY OF SUCH DAMAGE. |
68 | | | 68 | |
69 | *******************************************************************************/ | | 69 | *******************************************************************************/ |
70 | /* | | 70 | /* |
71 | * Device driver for the Intel i8254x family of Gigabit Ethernet chips. | | 71 | * Device driver for the Intel i8254x family of Gigabit Ethernet chips. |
72 | * | | 72 | * |
73 | * TODO (in order of importance): | | 73 | * TODO (in order of importance): |
74 | * | | 74 | * |
75 | * - Check XXX'ed comments | | 75 | * - Check XXX'ed comments |
76 | * - EEE (Energy Efficiency Ethernet) | | 76 | * - EEE (Energy Efficiency Ethernet) |
77 | * - Multi queue | | 77 | * - Multi queue |
78 | * - Image Unique ID | | 78 | * - Image Unique ID |
79 | * - LPLU other than PCH* | | 79 | * - LPLU other than PCH* |
80 | * - Virtual Function | | 80 | * - Virtual Function |
81 | * - Set LED correctly (based on contents in EEPROM) | | 81 | * - Set LED correctly (based on contents in EEPROM) |
82 | * - Rework how parameters are loaded from the EEPROM. | | 82 | * - Rework how parameters are loaded from the EEPROM. |
83 | */ | | 83 | */ |
84 | | | 84 | |
85 | #include <sys/cdefs.h> | | 85 | #include <sys/cdefs.h> |
86 | __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.359 2015/10/13 08:17:15 knakahara Exp $"); | | 86 | __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.360 2015/10/13 08:20:02 knakahara Exp $"); |
87 | | | 87 | |
88 | #ifdef _KERNEL_OPT | | 88 | #ifdef _KERNEL_OPT |
89 | #include "opt_net_mpsafe.h" | | 89 | #include "opt_net_mpsafe.h" |
90 | #endif | | 90 | #endif |
91 | | | 91 | |
92 | #include <sys/param.h> | | 92 | #include <sys/param.h> |
93 | #include <sys/systm.h> | | 93 | #include <sys/systm.h> |
94 | #include <sys/callout.h> | | 94 | #include <sys/callout.h> |
95 | #include <sys/mbuf.h> | | 95 | #include <sys/mbuf.h> |
96 | #include <sys/malloc.h> | | 96 | #include <sys/malloc.h> |
97 | #include <sys/kmem.h> | | 97 | #include <sys/kmem.h> |
98 | #include <sys/kernel.h> | | 98 | #include <sys/kernel.h> |
99 | #include <sys/socket.h> | | 99 | #include <sys/socket.h> |
100 | #include <sys/ioctl.h> | | 100 | #include <sys/ioctl.h> |
101 | #include <sys/errno.h> | | 101 | #include <sys/errno.h> |
102 | #include <sys/device.h> | | 102 | #include <sys/device.h> |
103 | #include <sys/queue.h> | | 103 | #include <sys/queue.h> |
104 | #include <sys/syslog.h> | | 104 | #include <sys/syslog.h> |
105 | #include <sys/interrupt.h> | | 105 | #include <sys/interrupt.h> |
106 | | | 106 | |
107 | #include <sys/rndsource.h> | | 107 | #include <sys/rndsource.h> |
108 | | | 108 | |
109 | #include <net/if.h> | | 109 | #include <net/if.h> |
110 | #include <net/if_dl.h> | | 110 | #include <net/if_dl.h> |
111 | #include <net/if_media.h> | | 111 | #include <net/if_media.h> |
112 | #include <net/if_ether.h> | | 112 | #include <net/if_ether.h> |
113 | | | 113 | |
114 | #include <net/bpf.h> | | 114 | #include <net/bpf.h> |
115 | | | 115 | |
116 | #include <netinet/in.h> /* XXX for struct ip */ | | 116 | #include <netinet/in.h> /* XXX for struct ip */ |
117 | #include <netinet/in_systm.h> /* XXX for struct ip */ | | 117 | #include <netinet/in_systm.h> /* XXX for struct ip */ |
118 | #include <netinet/ip.h> /* XXX for struct ip */ | | 118 | #include <netinet/ip.h> /* XXX for struct ip */ |
119 | #include <netinet/ip6.h> /* XXX for struct ip6_hdr */ | | 119 | #include <netinet/ip6.h> /* XXX for struct ip6_hdr */ |
120 | #include <netinet/tcp.h> /* XXX for struct tcphdr */ | | 120 | #include <netinet/tcp.h> /* XXX for struct tcphdr */ |
121 | | | 121 | |
122 | #include <sys/bus.h> | | 122 | #include <sys/bus.h> |
123 | #include <sys/intr.h> | | 123 | #include <sys/intr.h> |
124 | #include <machine/endian.h> | | 124 | #include <machine/endian.h> |
125 | | | 125 | |
126 | #include <dev/mii/mii.h> | | 126 | #include <dev/mii/mii.h> |
127 | #include <dev/mii/miivar.h> | | 127 | #include <dev/mii/miivar.h> |
128 | #include <dev/mii/miidevs.h> | | 128 | #include <dev/mii/miidevs.h> |
129 | #include <dev/mii/mii_bitbang.h> | | 129 | #include <dev/mii/mii_bitbang.h> |
130 | #include <dev/mii/ikphyreg.h> | | 130 | #include <dev/mii/ikphyreg.h> |
131 | #include <dev/mii/igphyreg.h> | | 131 | #include <dev/mii/igphyreg.h> |
132 | #include <dev/mii/igphyvar.h> | | 132 | #include <dev/mii/igphyvar.h> |
133 | #include <dev/mii/inbmphyreg.h> | | 133 | #include <dev/mii/inbmphyreg.h> |
134 | | | 134 | |
135 | #include <dev/pci/pcireg.h> | | 135 | #include <dev/pci/pcireg.h> |
136 | #include <dev/pci/pcivar.h> | | 136 | #include <dev/pci/pcivar.h> |
137 | #include <dev/pci/pcidevs.h> | | 137 | #include <dev/pci/pcidevs.h> |
138 | | | 138 | |
139 | #include <dev/pci/if_wmreg.h> | | 139 | #include <dev/pci/if_wmreg.h> |
140 | #include <dev/pci/if_wmvar.h> | | 140 | #include <dev/pci/if_wmvar.h> |
141 | | | 141 | |
142 | #ifdef WM_DEBUG | | 142 | #ifdef WM_DEBUG |
143 | #define WM_DEBUG_LINK 0x01 | | 143 | #define WM_DEBUG_LINK 0x01 |
144 | #define WM_DEBUG_TX 0x02 | | 144 | #define WM_DEBUG_TX 0x02 |
145 | #define WM_DEBUG_RX 0x04 | | 145 | #define WM_DEBUG_RX 0x04 |
146 | #define WM_DEBUG_GMII 0x08 | | 146 | #define WM_DEBUG_GMII 0x08 |
147 | #define WM_DEBUG_MANAGE 0x10 | | 147 | #define WM_DEBUG_MANAGE 0x10 |
148 | #define WM_DEBUG_NVM 0x20 | | 148 | #define WM_DEBUG_NVM 0x20 |
149 | int wm_debug = WM_DEBUG_TX | WM_DEBUG_RX | WM_DEBUG_LINK | WM_DEBUG_GMII | | 149 | int wm_debug = WM_DEBUG_TX | WM_DEBUG_RX | WM_DEBUG_LINK | WM_DEBUG_GMII |
150 | | WM_DEBUG_MANAGE | WM_DEBUG_NVM; | | 150 | | WM_DEBUG_MANAGE | WM_DEBUG_NVM; |
151 | | | 151 | |
152 | #define DPRINTF(x, y) if (wm_debug & (x)) printf y | | 152 | #define DPRINTF(x, y) if (wm_debug & (x)) printf y |
153 | #else | | 153 | #else |
154 | #define DPRINTF(x, y) /* nothing */ | | 154 | #define DPRINTF(x, y) /* nothing */ |
155 | #endif /* WM_DEBUG */ | | 155 | #endif /* WM_DEBUG */ |
156 | | | 156 | |
157 | #ifdef NET_MPSAFE | | 157 | #ifdef NET_MPSAFE |
158 | #define WM_MPSAFE 1 | | 158 | #define WM_MPSAFE 1 |
159 | #endif | | 159 | #endif |
160 | | | 160 | |
161 | #ifdef __HAVE_PCI_MSI_MSIX | | 161 | #ifdef __HAVE_PCI_MSI_MSIX |
162 | #define WM_MSI_MSIX 1 /* Enable by default */ | | 162 | #define WM_MSI_MSIX 1 /* Enable by default */ |
163 | #endif | | 163 | #endif |
164 | | | 164 | |
165 | /* | | 165 | /* |
166 | * This device driver divides interrupt to TX, RX and link state. | | 166 | * This device driver divides interrupt to TX, RX and link state. |
167 | * Each MSI-X vector indexes are below. | | 167 | * Each MSI-X vector indexes are below. |
168 | */ | | 168 | */ |
169 | #define WM_MSIX_NINTR 3 | | 169 | #define WM_MSIX_NINTR 3 |
170 | #define WM_MSIX_TXINTR_IDX 0 | | 170 | #define WM_MSIX_TXINTR_IDX 0 |
171 | #define WM_MSIX_RXINTR_IDX 1 | | 171 | #define WM_MSIX_RXINTR_IDX 1 |
172 | #define WM_MSIX_LINKINTR_IDX 2 | | 172 | #define WM_MSIX_LINKINTR_IDX 2 |
173 | #define WM_MAX_NINTR WM_MSIX_NINTR | | 173 | #define WM_MAX_NINTR WM_MSIX_NINTR |
174 | | | 174 | |
175 | /* | | 175 | /* |
176 | * This device driver set affinity to each interrupts like below (round-robin). | | 176 | * This device driver set affinity to each interrupts like below (round-robin). |
177 | * If the number CPUs is less than the number of interrupts, this driver usase | | 177 | * If the number CPUs is less than the number of interrupts, this driver usase |
178 | * the same CPU for multiple interrupts. | | 178 | * the same CPU for multiple interrupts. |
179 | */ | | 179 | */ |
180 | #define WM_MSIX_TXINTR_CPUID 0 | | 180 | #define WM_MSIX_TXINTR_CPUID 0 |
181 | #define WM_MSIX_RXINTR_CPUID 1 | | 181 | #define WM_MSIX_RXINTR_CPUID 1 |
182 | #define WM_MSIX_LINKINTR_CPUID 2 | | 182 | #define WM_MSIX_LINKINTR_CPUID 2 |
183 | | | 183 | |
184 | /* | | 184 | /* |
185 | * Transmit descriptor list size. Due to errata, we can only have | | 185 | * Transmit descriptor list size. Due to errata, we can only have |
186 | * 256 hardware descriptors in the ring on < 82544, but we use 4096 | | 186 | * 256 hardware descriptors in the ring on < 82544, but we use 4096 |
187 | * on >= 82544. We tell the upper layers that they can queue a lot | | 187 | * on >= 82544. We tell the upper layers that they can queue a lot |
188 | * of packets, and we go ahead and manage up to 64 (16 for the i82547) | | 188 | * of packets, and we go ahead and manage up to 64 (16 for the i82547) |
189 | * of them at a time. | | 189 | * of them at a time. |
190 | * | | 190 | * |
191 | * We allow up to 256 (!) DMA segments per packet. Pathological packet | | 191 | * We allow up to 256 (!) DMA segments per packet. Pathological packet |
192 | * chains containing many small mbufs have been observed in zero-copy | | 192 | * chains containing many small mbufs have been observed in zero-copy |
193 | * situations with jumbo frames. | | 193 | * situations with jumbo frames. |
194 | */ | | 194 | */ |
195 | #define WM_NTXSEGS 256 | | 195 | #define WM_NTXSEGS 256 |
196 | #define WM_IFQUEUELEN 256 | | 196 | #define WM_IFQUEUELEN 256 |
197 | #define WM_TXQUEUELEN_MAX 64 | | 197 | #define WM_TXQUEUELEN_MAX 64 |
198 | #define WM_TXQUEUELEN_MAX_82547 16 | | 198 | #define WM_TXQUEUELEN_MAX_82547 16 |
199 | #define WM_TXQUEUELEN(txq) ((txq)->txq_num) | | 199 | #define WM_TXQUEUELEN(txq) ((txq)->txq_num) |
200 | #define WM_TXQUEUELEN_MASK(txq) (WM_TXQUEUELEN(txq) - 1) | | 200 | #define WM_TXQUEUELEN_MASK(txq) (WM_TXQUEUELEN(txq) - 1) |
201 | #define WM_TXQUEUE_GC(txq) (WM_TXQUEUELEN(txq) / 8) | | 201 | #define WM_TXQUEUE_GC(txq) (WM_TXQUEUELEN(txq) / 8) |
202 | #define WM_NTXDESC_82542 256 | | 202 | #define WM_NTXDESC_82542 256 |
203 | #define WM_NTXDESC_82544 4096 | | 203 | #define WM_NTXDESC_82544 4096 |
204 | #define WM_NTXDESC(txq) ((txq)->txq_ndesc) | | 204 | #define WM_NTXDESC(txq) ((txq)->txq_ndesc) |
205 | #define WM_NTXDESC_MASK(txq) (WM_NTXDESC(txq) - 1) | | 205 | #define WM_NTXDESC_MASK(txq) (WM_NTXDESC(txq) - 1) |
206 | #define WM_TXDESCSIZE(txq) (WM_NTXDESC(txq) * sizeof(wiseman_txdesc_t)) | | 206 | #define WM_TXDESCSIZE(txq) (WM_NTXDESC(txq) * sizeof(wiseman_txdesc_t)) |
207 | #define WM_NEXTTX(txq, x) (((x) + 1) & WM_NTXDESC_MASK(txq)) | | 207 | #define WM_NEXTTX(txq, x) (((x) + 1) & WM_NTXDESC_MASK(txq)) |
208 | #define WM_NEXTTXS(txq, x) (((x) + 1) & WM_TXQUEUELEN_MASK(txq)) | | 208 | #define WM_NEXTTXS(txq, x) (((x) + 1) & WM_TXQUEUELEN_MASK(txq)) |
209 | | | 209 | |
210 | #define WM_MAXTXDMA (2 * round_page(IP_MAXPACKET)) /* for TSO */ | | 210 | #define WM_MAXTXDMA (2 * round_page(IP_MAXPACKET)) /* for TSO */ |
211 | | | 211 | |
212 | /* | | 212 | /* |
213 | * Receive descriptor list size. We have one Rx buffer for normal | | 213 | * Receive descriptor list size. We have one Rx buffer for normal |
214 | * sized packets. Jumbo packets consume 5 Rx buffers for a full-sized | | 214 | * sized packets. Jumbo packets consume 5 Rx buffers for a full-sized |
215 | * packet. We allocate 256 receive descriptors, each with a 2k | | 215 | * packet. We allocate 256 receive descriptors, each with a 2k |
216 | * buffer (MCLBYTES), which gives us room for 50 jumbo packets. | | 216 | * buffer (MCLBYTES), which gives us room for 50 jumbo packets. |
217 | */ | | 217 | */ |
218 | #define WM_NRXDESC 256 | | 218 | #define WM_NRXDESC 256 |
219 | #define WM_NRXDESC_MASK (WM_NRXDESC - 1) | | 219 | #define WM_NRXDESC_MASK (WM_NRXDESC - 1) |
220 | #define WM_NEXTRX(x) (((x) + 1) & WM_NRXDESC_MASK) | | 220 | #define WM_NEXTRX(x) (((x) + 1) & WM_NRXDESC_MASK) |
221 | #define WM_PREVRX(x) (((x) - 1) & WM_NRXDESC_MASK) | | 221 | #define WM_PREVRX(x) (((x) - 1) & WM_NRXDESC_MASK) |
222 | | | 222 | |
223 | typedef union txdescs { | | 223 | typedef union txdescs { |
224 | wiseman_txdesc_t sctxu_txdescs[WM_NTXDESC_82544]; | | 224 | wiseman_txdesc_t sctxu_txdescs[WM_NTXDESC_82544]; |
225 | nq_txdesc_t sctxu_nq_txdescs[WM_NTXDESC_82544]; | | 225 | nq_txdesc_t sctxu_nq_txdescs[WM_NTXDESC_82544]; |
226 | } txdescs_t; | | 226 | } txdescs_t; |
227 | | | 227 | |
228 | #define WM_CDTXOFF(x) (sizeof(wiseman_txdesc_t) * x) | | 228 | #define WM_CDTXOFF(x) (sizeof(wiseman_txdesc_t) * x) |
229 | #define WM_CDRXOFF(x) (sizeof(wiseman_rxdesc_t) * x) | | 229 | #define WM_CDRXOFF(x) (sizeof(wiseman_rxdesc_t) * x) |
230 | | | 230 | |
231 | /* | | 231 | /* |
232 | * Software state for transmit jobs. | | 232 | * Software state for transmit jobs. |
233 | */ | | 233 | */ |
234 | struct wm_txsoft { | | 234 | struct wm_txsoft { |
235 | struct mbuf *txs_mbuf; /* head of our mbuf chain */ | | 235 | struct mbuf *txs_mbuf; /* head of our mbuf chain */ |
236 | bus_dmamap_t txs_dmamap; /* our DMA map */ | | 236 | bus_dmamap_t txs_dmamap; /* our DMA map */ |
237 | int txs_firstdesc; /* first descriptor in packet */ | | 237 | int txs_firstdesc; /* first descriptor in packet */ |
238 | int txs_lastdesc; /* last descriptor in packet */ | | 238 | int txs_lastdesc; /* last descriptor in packet */ |
239 | int txs_ndesc; /* # of descriptors used */ | | 239 | int txs_ndesc; /* # of descriptors used */ |
240 | }; | | 240 | }; |
241 | | | 241 | |
242 | /* | | 242 | /* |
243 | * Software state for receive buffers. Each descriptor gets a | | 243 | * Software state for receive buffers. Each descriptor gets a |
244 | * 2k (MCLBYTES) buffer and a DMA map. For packets which fill | | 244 | * 2k (MCLBYTES) buffer and a DMA map. For packets which fill |
245 | * more than one buffer, we chain them together. | | 245 | * more than one buffer, we chain them together. |
246 | */ | | 246 | */ |
247 | struct wm_rxsoft { | | 247 | struct wm_rxsoft { |
248 | struct mbuf *rxs_mbuf; /* head of our mbuf chain */ | | 248 | struct mbuf *rxs_mbuf; /* head of our mbuf chain */ |
249 | bus_dmamap_t rxs_dmamap; /* our DMA map */ | | 249 | bus_dmamap_t rxs_dmamap; /* our DMA map */ |
250 | }; | | 250 | }; |
251 | | | 251 | |
252 | #define WM_LINKUP_TIMEOUT 50 | | 252 | #define WM_LINKUP_TIMEOUT 50 |
253 | | | 253 | |
254 | static uint16_t swfwphysem[] = { | | 254 | static uint16_t swfwphysem[] = { |
255 | SWFW_PHY0_SM, | | 255 | SWFW_PHY0_SM, |
256 | SWFW_PHY1_SM, | | 256 | SWFW_PHY1_SM, |
257 | SWFW_PHY2_SM, | | 257 | SWFW_PHY2_SM, |
258 | SWFW_PHY3_SM | | 258 | SWFW_PHY3_SM |
259 | }; | | 259 | }; |
260 | | | 260 | |
261 | static const uint32_t wm_82580_rxpbs_table[] = { | | 261 | static const uint32_t wm_82580_rxpbs_table[] = { |
262 | 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 | | 262 | 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 |
263 | }; | | 263 | }; |
264 | | | 264 | |
265 | struct wm_softc; | | 265 | struct wm_softc; |
266 | | | 266 | |
267 | struct wm_txqueue { | | 267 | struct wm_txqueue { |
268 | kmutex_t *txq_lock; /* lock for tx operations */ | | 268 | kmutex_t *txq_lock; /* lock for tx operations */ |
269 | | | 269 | |
270 | struct wm_softc *txq_sc; | | 270 | struct wm_softc *txq_sc; |
271 | | | 271 | |
272 | /* Software state for the transmit descriptors. */ | | 272 | /* Software state for the transmit descriptors. */ |
273 | int txq_num; /* must be a power of two */ | | 273 | int txq_num; /* must be a power of two */ |
274 | struct wm_txsoft txq_soft[WM_TXQUEUELEN_MAX]; | | 274 | struct wm_txsoft txq_soft[WM_TXQUEUELEN_MAX]; |
275 | | | 275 | |
276 | /* TX control data structures. */ | | 276 | /* TX control data structures. */ |
277 | int txq_ndesc; /* must be a power of two */ | | 277 | int txq_ndesc; /* must be a power of two */ |
278 | txdescs_t *txq_descs_u; | | 278 | txdescs_t *txq_descs_u; |
279 | bus_dmamap_t txq_desc_dmamap; /* control data DMA map */ | | 279 | bus_dmamap_t txq_desc_dmamap; /* control data DMA map */ |
280 | bus_dma_segment_t txq_desc_seg; /* control data segment */ | | 280 | bus_dma_segment_t txq_desc_seg; /* control data segment */ |
281 | int txq_desc_rseg; /* real number of control segment */ | | 281 | int txq_desc_rseg; /* real number of control segment */ |
282 | size_t txq_desc_size; /* control data size */ | | 282 | size_t txq_desc_size; /* control data size */ |
283 | #define txq_desc_dma txq_desc_dmamap->dm_segs[0].ds_addr | | 283 | #define txq_desc_dma txq_desc_dmamap->dm_segs[0].ds_addr |
284 | #define txq_descs txq_descs_u->sctxu_txdescs | | 284 | #define txq_descs txq_descs_u->sctxu_txdescs |
285 | #define txq_nq_descs txq_descs_u->sctxu_nq_txdescs | | 285 | #define txq_nq_descs txq_descs_u->sctxu_nq_txdescs |
286 | | | 286 | |
287 | bus_addr_t txq_tdt_reg; /* offset of TDT register */ | | 287 | bus_addr_t txq_tdt_reg; /* offset of TDT register */ |
288 | | | 288 | |
289 | int txq_free; /* number of free Tx descriptors */ | | 289 | int txq_free; /* number of free Tx descriptors */ |
290 | int txq_next; /* next ready Tx descriptor */ | | 290 | int txq_next; /* next ready Tx descriptor */ |
291 | | | 291 | |
292 | int txq_sfree; /* number of free Tx jobs */ | | 292 | int txq_sfree; /* number of free Tx jobs */ |
293 | int txq_snext; /* next free Tx job */ | | 293 | int txq_snext; /* next free Tx job */ |
294 | int txq_sdirty; /* dirty Tx jobs */ | | 294 | int txq_sdirty; /* dirty Tx jobs */ |
295 | | | 295 | |
296 | /* These 4 variables are used only on the 82547. */ | | 296 | /* These 4 variables are used only on the 82547. */ |
297 | int txq_fifo_size; /* Tx FIFO size */ | | 297 | int txq_fifo_size; /* Tx FIFO size */ |
298 | int txq_fifo_head; /* current head of FIFO */ | | 298 | int txq_fifo_head; /* current head of FIFO */ |
299 | uint32_t txq_fifo_addr; /* internal address of start of FIFO */ | | 299 | uint32_t txq_fifo_addr; /* internal address of start of FIFO */ |
300 | int txq_fifo_stall; /* Tx FIFO is stalled */ | | 300 | int txq_fifo_stall; /* Tx FIFO is stalled */ |
301 | | | 301 | |
302 | /* XXX which event counter is required? */ | | 302 | /* XXX which event counter is required? */ |
303 | }; | | 303 | }; |
304 | | | 304 | |
305 | struct wm_rxqueue { | | 305 | struct wm_rxqueue { |
306 | kmutex_t *rxq_lock; /* lock for rx operations */ | | 306 | kmutex_t *rxq_lock; /* lock for rx operations */ |
307 | | | 307 | |
308 | struct wm_softc *rxq_sc; | | 308 | struct wm_softc *rxq_sc; |
309 | | | 309 | |
310 | /* Software state for the receive descriptors. */ | | 310 | /* Software state for the receive descriptors. */ |
311 | wiseman_rxdesc_t *rxq_descs; | | 311 | wiseman_rxdesc_t *rxq_descs; |
312 | | | 312 | |
313 | /* RX control data structures. */ | | 313 | /* RX control data structures. */ |
314 | struct wm_rxsoft rxq_soft[WM_NRXDESC]; | | 314 | struct wm_rxsoft rxq_soft[WM_NRXDESC]; |
315 | bus_dmamap_t rxq_desc_dmamap; /* control data DMA map */ | | 315 | bus_dmamap_t rxq_desc_dmamap; /* control data DMA map */ |
316 | bus_dma_segment_t rxq_desc_seg; /* control data segment */ | | 316 | bus_dma_segment_t rxq_desc_seg; /* control data segment */ |
317 | int rxq_desc_rseg; /* real number of control segment */ | | 317 | int rxq_desc_rseg; /* real number of control segment */ |
318 | size_t rxq_desc_size; /* control data size */ | | 318 | size_t rxq_desc_size; /* control data size */ |
319 | #define rxq_desc_dma rxq_desc_dmamap->dm_segs[0].ds_addr | | 319 | #define rxq_desc_dma rxq_desc_dmamap->dm_segs[0].ds_addr |
320 | | | 320 | |
321 | bus_addr_t rxq_rdt_reg; /* offset of RDT register */ | | 321 | bus_addr_t rxq_rdt_reg; /* offset of RDT register */ |
322 | | | 322 | |
323 | int rxq_ptr; /* next ready Rx descriptor/queue ent */ | | 323 | int rxq_ptr; /* next ready Rx descriptor/queue ent */ |
324 | int rxq_discard; | | 324 | int rxq_discard; |
325 | int rxq_len; | | 325 | int rxq_len; |
326 | struct mbuf *rxq_head; | | 326 | struct mbuf *rxq_head; |
327 | struct mbuf *rxq_tail; | | 327 | struct mbuf *rxq_tail; |
328 | struct mbuf **rxq_tailp; | | 328 | struct mbuf **rxq_tailp; |
329 | | | 329 | |
330 | /* XXX which event counter is required? */ | | 330 | /* XXX which event counter is required? */ |
331 | }; | | 331 | }; |
332 | | | 332 | |
333 | /* | | 333 | /* |
334 | * Software state per device. | | 334 | * Software state per device. |
335 | */ | | 335 | */ |
336 | struct wm_softc { | | 336 | struct wm_softc { |
337 | device_t sc_dev; /* generic device information */ | | 337 | device_t sc_dev; /* generic device information */ |
338 | bus_space_tag_t sc_st; /* bus space tag */ | | 338 | bus_space_tag_t sc_st; /* bus space tag */ |
339 | bus_space_handle_t sc_sh; /* bus space handle */ | | 339 | bus_space_handle_t sc_sh; /* bus space handle */ |
340 | bus_size_t sc_ss; /* bus space size */ | | 340 | bus_size_t sc_ss; /* bus space size */ |
341 | bus_space_tag_t sc_iot; /* I/O space tag */ | | 341 | bus_space_tag_t sc_iot; /* I/O space tag */ |
342 | bus_space_handle_t sc_ioh; /* I/O space handle */ | | 342 | bus_space_handle_t sc_ioh; /* I/O space handle */ |
343 | bus_size_t sc_ios; /* I/O space size */ | | 343 | bus_size_t sc_ios; /* I/O space size */ |
344 | bus_space_tag_t sc_flasht; /* flash registers space tag */ | | 344 | bus_space_tag_t sc_flasht; /* flash registers space tag */ |
345 | bus_space_handle_t sc_flashh; /* flash registers space handle */ | | 345 | bus_space_handle_t sc_flashh; /* flash registers space handle */ |
346 | bus_size_t sc_flashs; /* flash registers space size */ | | 346 | bus_size_t sc_flashs; /* flash registers space size */ |
347 | bus_dma_tag_t sc_dmat; /* bus DMA tag */ | | 347 | bus_dma_tag_t sc_dmat; /* bus DMA tag */ |
348 | | | 348 | |
349 | struct ethercom sc_ethercom; /* ethernet common data */ | | 349 | struct ethercom sc_ethercom; /* ethernet common data */ |
350 | struct mii_data sc_mii; /* MII/media information */ | | 350 | struct mii_data sc_mii; /* MII/media information */ |
351 | | | 351 | |
352 | pci_chipset_tag_t sc_pc; | | 352 | pci_chipset_tag_t sc_pc; |
353 | pcitag_t sc_pcitag; | | 353 | pcitag_t sc_pcitag; |
354 | int sc_bus_speed; /* PCI/PCIX bus speed */ | | 354 | int sc_bus_speed; /* PCI/PCIX bus speed */ |
355 | int sc_pcixe_capoff; /* PCI[Xe] capability reg offset */ | | 355 | int sc_pcixe_capoff; /* PCI[Xe] capability reg offset */ |
356 | | | 356 | |
357 | uint16_t sc_pcidevid; /* PCI device ID */ | | 357 | uint16_t sc_pcidevid; /* PCI device ID */ |
358 | wm_chip_type sc_type; /* MAC type */ | | 358 | wm_chip_type sc_type; /* MAC type */ |
359 | int sc_rev; /* MAC revision */ | | 359 | int sc_rev; /* MAC revision */ |
360 | wm_phy_type sc_phytype; /* PHY type */ | | 360 | wm_phy_type sc_phytype; /* PHY type */ |
361 | uint32_t sc_mediatype; /* Media type (Copper, Fiber, SERDES)*/ | | 361 | uint32_t sc_mediatype; /* Media type (Copper, Fiber, SERDES)*/ |
362 | #define WM_MEDIATYPE_UNKNOWN 0x00 | | 362 | #define WM_MEDIATYPE_UNKNOWN 0x00 |
363 | #define WM_MEDIATYPE_FIBER 0x01 | | 363 | #define WM_MEDIATYPE_FIBER 0x01 |
364 | #define WM_MEDIATYPE_COPPER 0x02 | | 364 | #define WM_MEDIATYPE_COPPER 0x02 |
365 | #define WM_MEDIATYPE_SERDES 0x03 /* Internal SERDES */ | | 365 | #define WM_MEDIATYPE_SERDES 0x03 /* Internal SERDES */ |
366 | int sc_funcid; /* unit number of the chip (0 to 3) */ | | 366 | int sc_funcid; /* unit number of the chip (0 to 3) */ |
367 | int sc_flags; /* flags; see below */ | | 367 | int sc_flags; /* flags; see below */ |
368 | int sc_if_flags; /* last if_flags */ | | 368 | int sc_if_flags; /* last if_flags */ |
369 | int sc_flowflags; /* 802.3x flow control flags */ | | 369 | int sc_flowflags; /* 802.3x flow control flags */ |
370 | int sc_align_tweak; | | 370 | int sc_align_tweak; |
371 | | | 371 | |
372 | void *sc_ihs[WM_MAX_NINTR]; /* | | 372 | void *sc_ihs[WM_MAX_NINTR]; /* |
373 | * interrupt cookie. | | 373 | * interrupt cookie. |
374 | * legacy and msi use sc_ihs[0]. | | 374 | * legacy and msi use sc_ihs[0]. |
375 | */ | | 375 | */ |
376 | pci_intr_handle_t *sc_intrs; /* legacy and msi use sc_intrs[0] */ | | 376 | pci_intr_handle_t *sc_intrs; /* legacy and msi use sc_intrs[0] */ |
377 | int sc_nintrs; /* number of interrupts */ | | 377 | int sc_nintrs; /* number of interrupts */ |
378 | | | 378 | |
379 | callout_t sc_tick_ch; /* tick callout */ | | 379 | callout_t sc_tick_ch; /* tick callout */ |
380 | bool sc_stopping; | | 380 | bool sc_stopping; |
381 | | | 381 | |
382 | int sc_nvm_ver_major; | | 382 | int sc_nvm_ver_major; |
383 | int sc_nvm_ver_minor; | | 383 | int sc_nvm_ver_minor; |
384 | int sc_nvm_ver_build; | | 384 | int sc_nvm_ver_build; |
385 | int sc_nvm_addrbits; /* NVM address bits */ | | 385 | int sc_nvm_addrbits; /* NVM address bits */ |
386 | unsigned int sc_nvm_wordsize; /* NVM word size */ | | 386 | unsigned int sc_nvm_wordsize; /* NVM word size */ |
387 | int sc_ich8_flash_base; | | 387 | int sc_ich8_flash_base; |
388 | int sc_ich8_flash_bank_size; | | 388 | int sc_ich8_flash_bank_size; |
389 | int sc_nvm_k1_enabled; | | 389 | int sc_nvm_k1_enabled; |
390 | | | 390 | |
391 | int sc_ntxqueues; | | 391 | int sc_ntxqueues; |
392 | struct wm_txqueue *sc_txq; | | 392 | struct wm_txqueue *sc_txq; |
393 | | | 393 | |
394 | int sc_nrxqueues; | | 394 | int sc_nrxqueues; |
395 | struct wm_rxqueue *sc_rxq; | | 395 | struct wm_rxqueue *sc_rxq; |
396 | | | 396 | |
397 | #ifdef WM_EVENT_COUNTERS | | 397 | #ifdef WM_EVENT_COUNTERS |
398 | /* Event counters. */ | | 398 | /* Event counters. */ |
399 | struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ | | 399 | struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ |
400 | struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ | | 400 | struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ |
401 | struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */ | | 401 | struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */ |
402 | struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ | | 402 | struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ |
403 | struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ | | 403 | struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ |
404 | struct evcnt sc_ev_rxintr; /* Rx interrupts */ | | 404 | struct evcnt sc_ev_rxintr; /* Rx interrupts */ |
405 | struct evcnt sc_ev_linkintr; /* Link interrupts */ | | 405 | struct evcnt sc_ev_linkintr; /* Link interrupts */ |
406 | | | 406 | |
407 | struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ | | 407 | struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ |
408 | struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ | | 408 | struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ |
409 | struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ | | 409 | struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ |
410 | struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ | | 410 | struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ |
411 | struct evcnt sc_ev_txtusum6; /* TCP/UDP v6 cksums comp. out-bound */ | | 411 | struct evcnt sc_ev_txtusum6; /* TCP/UDP v6 cksums comp. out-bound */ |
412 | struct evcnt sc_ev_txtso; /* TCP seg offload out-bound (IPv4) */ | | 412 | struct evcnt sc_ev_txtso; /* TCP seg offload out-bound (IPv4) */ |
413 | struct evcnt sc_ev_txtso6; /* TCP seg offload out-bound (IPv6) */ | | 413 | struct evcnt sc_ev_txtso6; /* TCP seg offload out-bound (IPv6) */ |
414 | struct evcnt sc_ev_txtsopain; /* painful header manip. for TSO */ | | 414 | struct evcnt sc_ev_txtsopain; /* painful header manip. for TSO */ |
415 | | | 415 | |
416 | struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */ | | 416 | struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */ |
417 | struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ | | 417 | struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ |
418 | | | 418 | |
419 | struct evcnt sc_ev_tu; /* Tx underrun */ | | 419 | struct evcnt sc_ev_tu; /* Tx underrun */ |
420 | | | 420 | |
421 | struct evcnt sc_ev_tx_xoff; /* Tx PAUSE(!0) frames */ | | 421 | struct evcnt sc_ev_tx_xoff; /* Tx PAUSE(!0) frames */ |
422 | struct evcnt sc_ev_tx_xon; /* Tx PAUSE(0) frames */ | | 422 | struct evcnt sc_ev_tx_xon; /* Tx PAUSE(0) frames */ |
423 | struct evcnt sc_ev_rx_xoff; /* Rx PAUSE(!0) frames */ | | 423 | struct evcnt sc_ev_rx_xoff; /* Rx PAUSE(!0) frames */ |
424 | struct evcnt sc_ev_rx_xon; /* Rx PAUSE(0) frames */ | | 424 | struct evcnt sc_ev_rx_xon; /* Rx PAUSE(0) frames */ |
425 | struct evcnt sc_ev_rx_macctl; /* Rx Unsupported */ | | 425 | struct evcnt sc_ev_rx_macctl; /* Rx Unsupported */ |
426 | #endif /* WM_EVENT_COUNTERS */ | | 426 | #endif /* WM_EVENT_COUNTERS */ |
427 | | | 427 | |
428 | /* This variable are used only on the 82547. */ | | 428 | /* This variable are used only on the 82547. */ |
429 | callout_t sc_txfifo_ch; /* Tx FIFO stall work-around timer */ | | 429 | callout_t sc_txfifo_ch; /* Tx FIFO stall work-around timer */ |
430 | | | 430 | |
431 | uint32_t sc_ctrl; /* prototype CTRL register */ | | 431 | uint32_t sc_ctrl; /* prototype CTRL register */ |
432 | #if 0 | | 432 | #if 0 |
433 | uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */ | | 433 | uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */ |
434 | #endif | | 434 | #endif |
435 | uint32_t sc_icr; /* prototype interrupt bits */ | | 435 | uint32_t sc_icr; /* prototype interrupt bits */ |
436 | uint32_t sc_itr; /* prototype intr throttling reg */ | | 436 | uint32_t sc_itr; /* prototype intr throttling reg */ |
437 | uint32_t sc_tctl; /* prototype TCTL register */ | | 437 | uint32_t sc_tctl; /* prototype TCTL register */ |
438 | uint32_t sc_rctl; /* prototype RCTL register */ | | 438 | uint32_t sc_rctl; /* prototype RCTL register */ |
439 | uint32_t sc_txcw; /* prototype TXCW register */ | | 439 | uint32_t sc_txcw; /* prototype TXCW register */ |
440 | uint32_t sc_tipg; /* prototype TIPG register */ | | 440 | uint32_t sc_tipg; /* prototype TIPG register */ |
441 | uint32_t sc_fcrtl; /* prototype FCRTL register */ | | 441 | uint32_t sc_fcrtl; /* prototype FCRTL register */ |
442 | uint32_t sc_pba; /* prototype PBA register */ | | 442 | uint32_t sc_pba; /* prototype PBA register */ |
443 | | | 443 | |
444 | int sc_tbi_linkup; /* TBI link status */ | | 444 | int sc_tbi_linkup; /* TBI link status */ |
445 | int sc_tbi_serdes_anegticks; /* autonegotiation ticks */ | | 445 | int sc_tbi_serdes_anegticks; /* autonegotiation ticks */ |
446 | int sc_tbi_serdes_ticks; /* tbi ticks */ | | 446 | int sc_tbi_serdes_ticks; /* tbi ticks */ |
447 | | | 447 | |
448 | int sc_mchash_type; /* multicast filter offset */ | | 448 | int sc_mchash_type; /* multicast filter offset */ |
449 | | | 449 | |
450 | krndsource_t rnd_source; /* random source */ | | 450 | krndsource_t rnd_source; /* random source */ |
451 | | | 451 | |
452 | kmutex_t *sc_core_lock; /* lock for softc operations */ | | 452 | kmutex_t *sc_core_lock; /* lock for softc operations */ |
453 | }; | | 453 | }; |
454 | | | 454 | |
455 | #define WM_TX_LOCK(_txq) if ((_txq)->txq_lock) mutex_enter((_txq)->txq_lock) | | 455 | #define WM_TX_LOCK(_txq) if ((_txq)->txq_lock) mutex_enter((_txq)->txq_lock) |
456 | #define WM_TX_UNLOCK(_txq) if ((_txq)->txq_lock) mutex_exit((_txq)->txq_lock) | | 456 | #define WM_TX_UNLOCK(_txq) if ((_txq)->txq_lock) mutex_exit((_txq)->txq_lock) |
457 | #define WM_TX_LOCKED(_txq) (!(_txq)->txq_lock || mutex_owned((_txq)->txq_lock)) | | 457 | #define WM_TX_LOCKED(_txq) (!(_txq)->txq_lock || mutex_owned((_txq)->txq_lock)) |
458 | #define WM_RX_LOCK(_rxq) if ((_rxq)->rxq_lock) mutex_enter((_rxq)->rxq_lock) | | 458 | #define WM_RX_LOCK(_rxq) if ((_rxq)->rxq_lock) mutex_enter((_rxq)->rxq_lock) |
459 | #define WM_RX_UNLOCK(_rxq) if ((_rxq)->rxq_lock) mutex_exit((_rxq)->rxq_lock) | | 459 | #define WM_RX_UNLOCK(_rxq) if ((_rxq)->rxq_lock) mutex_exit((_rxq)->rxq_lock) |
460 | #define WM_RX_LOCKED(_rxq) (!(_rxq)->rxq_lock || mutex_owned((_rxq)->rxq_lock)) | | 460 | #define WM_RX_LOCKED(_rxq) (!(_rxq)->rxq_lock || mutex_owned((_rxq)->rxq_lock)) |
461 | #define WM_CORE_LOCK(_sc) if ((_sc)->sc_core_lock) mutex_enter((_sc)->sc_core_lock) | | 461 | #define WM_CORE_LOCK(_sc) if ((_sc)->sc_core_lock) mutex_enter((_sc)->sc_core_lock) |
462 | #define WM_CORE_UNLOCK(_sc) if ((_sc)->sc_core_lock) mutex_exit((_sc)->sc_core_lock) | | 462 | #define WM_CORE_UNLOCK(_sc) if ((_sc)->sc_core_lock) mutex_exit((_sc)->sc_core_lock) |
463 | #define WM_CORE_LOCKED(_sc) (!(_sc)->sc_core_lock || mutex_owned((_sc)->sc_core_lock)) | | 463 | #define WM_CORE_LOCKED(_sc) (!(_sc)->sc_core_lock || mutex_owned((_sc)->sc_core_lock)) |
464 | | | 464 | |
465 | #ifdef WM_MPSAFE | | 465 | #ifdef WM_MPSAFE |
466 | #define CALLOUT_FLAGS CALLOUT_MPSAFE | | 466 | #define CALLOUT_FLAGS CALLOUT_MPSAFE |
467 | #else | | 467 | #else |
468 | #define CALLOUT_FLAGS 0 | | 468 | #define CALLOUT_FLAGS 0 |
469 | #endif | | 469 | #endif |
470 | | | 470 | |
471 | #define WM_RXCHAIN_RESET(rxq) \ | | 471 | #define WM_RXCHAIN_RESET(rxq) \ |
472 | do { \ | | 472 | do { \ |
473 | (rxq)->rxq_tailp = &(rxq)->rxq_head; \ | | 473 | (rxq)->rxq_tailp = &(rxq)->rxq_head; \ |
474 | *(rxq)->rxq_tailp = NULL; \ | | 474 | *(rxq)->rxq_tailp = NULL; \ |
475 | (rxq)->rxq_len = 0; \ | | 475 | (rxq)->rxq_len = 0; \ |
476 | } while (/*CONSTCOND*/0) | | 476 | } while (/*CONSTCOND*/0) |
477 | | | 477 | |
478 | #define WM_RXCHAIN_LINK(rxq, m) \ | | 478 | #define WM_RXCHAIN_LINK(rxq, m) \ |
479 | do { \ | | 479 | do { \ |
480 | *(rxq)->rxq_tailp = (rxq)->rxq_tail = (m); \ | | 480 | *(rxq)->rxq_tailp = (rxq)->rxq_tail = (m); \ |
481 | (rxq)->rxq_tailp = &(m)->m_next; \ | | 481 | (rxq)->rxq_tailp = &(m)->m_next; \ |
482 | } while (/*CONSTCOND*/0) | | 482 | } while (/*CONSTCOND*/0) |
483 | | | 483 | |
484 | #ifdef WM_EVENT_COUNTERS | | 484 | #ifdef WM_EVENT_COUNTERS |
485 | #define WM_EVCNT_INCR(ev) (ev)->ev_count++ | | 485 | #define WM_EVCNT_INCR(ev) (ev)->ev_count++ |
486 | #define WM_EVCNT_ADD(ev, val) (ev)->ev_count += (val) | | 486 | #define WM_EVCNT_ADD(ev, val) (ev)->ev_count += (val) |
487 | #else | | 487 | #else |
488 | #define WM_EVCNT_INCR(ev) /* nothing */ | | 488 | #define WM_EVCNT_INCR(ev) /* nothing */ |
489 | #define WM_EVCNT_ADD(ev, val) /* nothing */ | | 489 | #define WM_EVCNT_ADD(ev, val) /* nothing */ |
490 | #endif | | 490 | #endif |
491 | | | 491 | |
492 | #define CSR_READ(sc, reg) \ | | 492 | #define CSR_READ(sc, reg) \ |
493 | bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) | | 493 | bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) |
494 | #define CSR_WRITE(sc, reg, val) \ | | 494 | #define CSR_WRITE(sc, reg, val) \ |
495 | bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) | | 495 | bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) |
496 | #define CSR_WRITE_FLUSH(sc) \ | | 496 | #define CSR_WRITE_FLUSH(sc) \ |
497 | (void) CSR_READ((sc), WMREG_STATUS) | | 497 | (void) CSR_READ((sc), WMREG_STATUS) |
498 | | | 498 | |
499 | #define ICH8_FLASH_READ32(sc, reg) \ | | 499 | #define ICH8_FLASH_READ32(sc, reg) \ |
500 | bus_space_read_4((sc)->sc_flasht, (sc)->sc_flashh, (reg)) | | 500 | bus_space_read_4((sc)->sc_flasht, (sc)->sc_flashh, (reg)) |
501 | #define ICH8_FLASH_WRITE32(sc, reg, data) \ | | 501 | #define ICH8_FLASH_WRITE32(sc, reg, data) \ |
502 | bus_space_write_4((sc)->sc_flasht, (sc)->sc_flashh, (reg), (data)) | | 502 | bus_space_write_4((sc)->sc_flasht, (sc)->sc_flashh, (reg), (data)) |
503 | | | 503 | |
504 | #define ICH8_FLASH_READ16(sc, reg) \ | | 504 | #define ICH8_FLASH_READ16(sc, reg) \ |
505 | bus_space_read_2((sc)->sc_flasht, (sc)->sc_flashh, (reg)) | | 505 | bus_space_read_2((sc)->sc_flasht, (sc)->sc_flashh, (reg)) |
506 | #define ICH8_FLASH_WRITE16(sc, reg, data) \ | | 506 | #define ICH8_FLASH_WRITE16(sc, reg, data) \ |
507 | bus_space_write_2((sc)->sc_flasht, (sc)->sc_flashh, (reg), (data)) | | 507 | bus_space_write_2((sc)->sc_flasht, (sc)->sc_flashh, (reg), (data)) |
508 | | | 508 | |
509 | #define WM_CDTXADDR(txq, x) ((txq)->txq_desc_dma + WM_CDTXOFF((x))) | | 509 | #define WM_CDTXADDR(txq, x) ((txq)->txq_desc_dma + WM_CDTXOFF((x))) |
510 | #define WM_CDRXADDR(rxq, x) ((rxq)->rxq_desc_dma + WM_CDRXOFF((x))) | | 510 | #define WM_CDRXADDR(rxq, x) ((rxq)->rxq_desc_dma + WM_CDRXOFF((x))) |
511 | | | 511 | |
512 | #define WM_CDTXADDR_LO(txq, x) (WM_CDTXADDR((txq), (x)) & 0xffffffffU) | | 512 | #define WM_CDTXADDR_LO(txq, x) (WM_CDTXADDR((txq), (x)) & 0xffffffffU) |
513 | #define WM_CDTXADDR_HI(txq, x) \ | | 513 | #define WM_CDTXADDR_HI(txq, x) \ |
514 | (sizeof(bus_addr_t) == 8 ? \ | | 514 | (sizeof(bus_addr_t) == 8 ? \ |
515 | (uint64_t)WM_CDTXADDR((txq), (x)) >> 32 : 0) | | 515 | (uint64_t)WM_CDTXADDR((txq), (x)) >> 32 : 0) |
516 | | | 516 | |
517 | #define WM_CDRXADDR_LO(rxq, x) (WM_CDRXADDR((rxq), (x)) & 0xffffffffU) | | 517 | #define WM_CDRXADDR_LO(rxq, x) (WM_CDRXADDR((rxq), (x)) & 0xffffffffU) |
518 | #define WM_CDRXADDR_HI(rxq, x) \ | | 518 | #define WM_CDRXADDR_HI(rxq, x) \ |
519 | (sizeof(bus_addr_t) == 8 ? \ | | 519 | (sizeof(bus_addr_t) == 8 ? \ |
520 | (uint64_t)WM_CDRXADDR((rxq), (x)) >> 32 : 0) | | 520 | (uint64_t)WM_CDRXADDR((rxq), (x)) >> 32 : 0) |
521 | | | 521 | |
522 | /* | | 522 | /* |
523 | * Register read/write functions. | | 523 | * Register read/write functions. |
524 | * Other than CSR_{READ|WRITE}(). | | 524 | * Other than CSR_{READ|WRITE}(). |
525 | */ | | 525 | */ |
526 | #if 0 | | 526 | #if 0 |
527 | static inline uint32_t wm_io_read(struct wm_softc *, int); | | 527 | static inline uint32_t wm_io_read(struct wm_softc *, int); |
528 | #endif | | 528 | #endif |
529 | static inline void wm_io_write(struct wm_softc *, int, uint32_t); | | 529 | static inline void wm_io_write(struct wm_softc *, int, uint32_t); |
530 | static inline void wm_82575_write_8bit_ctlr_reg(struct wm_softc *, uint32_t, | | 530 | static inline void wm_82575_write_8bit_ctlr_reg(struct wm_softc *, uint32_t, |
531 | uint32_t, uint32_t); | | 531 | uint32_t, uint32_t); |
532 | static inline void wm_set_dma_addr(volatile wiseman_addr_t *, bus_addr_t); | | 532 | static inline void wm_set_dma_addr(volatile wiseman_addr_t *, bus_addr_t); |
533 | | | 533 | |
534 | /* | | 534 | /* |
535 | * Descriptor sync/init functions. | | 535 | * Descriptor sync/init functions. |
536 | */ | | 536 | */ |
537 | static inline void wm_cdtxsync(struct wm_softc *, int, int, int); | | 537 | static inline void wm_cdtxsync(struct wm_softc *, int, int, int); |
538 | static inline void wm_cdrxsync(struct wm_softc *, int, int); | | 538 | static inline void wm_cdrxsync(struct wm_softc *, int, int); |
539 | static inline void wm_init_rxdesc(struct wm_softc *, int); | | 539 | static inline void wm_init_rxdesc(struct wm_softc *, int); |
540 | | | 540 | |
541 | /* | | 541 | /* |
542 | * Device driver interface functions and commonly used functions. | | 542 | * Device driver interface functions and commonly used functions. |
543 | * match, attach, detach, init, start, stop, ioctl, watchdog and so on. | | 543 | * match, attach, detach, init, start, stop, ioctl, watchdog and so on. |
544 | */ | | 544 | */ |
545 | static const struct wm_product *wm_lookup(const struct pci_attach_args *); | | 545 | static const struct wm_product *wm_lookup(const struct pci_attach_args *); |
546 | static int wm_match(device_t, cfdata_t, void *); | | 546 | static int wm_match(device_t, cfdata_t, void *); |
547 | static void wm_attach(device_t, device_t, void *); | | 547 | static void wm_attach(device_t, device_t, void *); |
548 | static int wm_detach(device_t, int); | | 548 | static int wm_detach(device_t, int); |
549 | static bool wm_suspend(device_t, const pmf_qual_t *); | | 549 | static bool wm_suspend(device_t, const pmf_qual_t *); |
550 | static bool wm_resume(device_t, const pmf_qual_t *); | | 550 | static bool wm_resume(device_t, const pmf_qual_t *); |
551 | static void wm_watchdog(struct ifnet *); | | 551 | static void wm_watchdog(struct ifnet *); |
552 | static void wm_tick(void *); | | 552 | static void wm_tick(void *); |
553 | static int wm_ifflags_cb(struct ethercom *); | | 553 | static int wm_ifflags_cb(struct ethercom *); |
554 | static int wm_ioctl(struct ifnet *, u_long, void *); | | 554 | static int wm_ioctl(struct ifnet *, u_long, void *); |
555 | /* MAC address related */ | | 555 | /* MAC address related */ |
556 | static uint16_t wm_check_alt_mac_addr(struct wm_softc *); | | 556 | static uint16_t wm_check_alt_mac_addr(struct wm_softc *); |
557 | static int wm_read_mac_addr(struct wm_softc *, uint8_t *); | | 557 | static int wm_read_mac_addr(struct wm_softc *, uint8_t *); |
558 | static void wm_set_ral(struct wm_softc *, const uint8_t *, int); | | 558 | static void wm_set_ral(struct wm_softc *, const uint8_t *, int); |
559 | static uint32_t wm_mchash(struct wm_softc *, const uint8_t *); | | 559 | static uint32_t wm_mchash(struct wm_softc *, const uint8_t *); |
560 | static void wm_set_filter(struct wm_softc *); | | 560 | static void wm_set_filter(struct wm_softc *); |
561 | /* Reset and init related */ | | 561 | /* Reset and init related */ |
562 | static void wm_set_vlan(struct wm_softc *); | | 562 | static void wm_set_vlan(struct wm_softc *); |
563 | static void wm_set_pcie_completion_timeout(struct wm_softc *); | | 563 | static void wm_set_pcie_completion_timeout(struct wm_softc *); |
564 | static void wm_get_auto_rd_done(struct wm_softc *); | | 564 | static void wm_get_auto_rd_done(struct wm_softc *); |
565 | static void wm_lan_init_done(struct wm_softc *); | | 565 | static void wm_lan_init_done(struct wm_softc *); |
566 | static void wm_get_cfg_done(struct wm_softc *); | | 566 | static void wm_get_cfg_done(struct wm_softc *); |
567 | static void wm_initialize_hardware_bits(struct wm_softc *); | | 567 | static void wm_initialize_hardware_bits(struct wm_softc *); |
568 | static uint32_t wm_rxpbs_adjust_82580(uint32_t); | | 568 | static uint32_t wm_rxpbs_adjust_82580(uint32_t); |
569 | static void wm_reset(struct wm_softc *); | | 569 | static void wm_reset(struct wm_softc *); |
570 | static int wm_add_rxbuf(struct wm_softc *, int); | | 570 | static int wm_add_rxbuf(struct wm_softc *, int); |
571 | static void wm_rxdrain(struct wm_softc *); | | 571 | static void wm_rxdrain(struct wm_softc *); |
572 | static int wm_init(struct ifnet *); | | 572 | static int wm_init(struct ifnet *); |
573 | static int wm_init_locked(struct ifnet *); | | 573 | static int wm_init_locked(struct ifnet *); |
574 | static void wm_stop(struct ifnet *, int); | | 574 | static void wm_stop(struct ifnet *, int); |
575 | static void wm_stop_locked(struct ifnet *, int); | | 575 | static void wm_stop_locked(struct ifnet *, int); |
576 | static int wm_tx_offload(struct wm_softc *, struct wm_txsoft *, | | 576 | static int wm_tx_offload(struct wm_softc *, struct wm_txsoft *, |
577 | uint32_t *, uint8_t *); | | 577 | uint32_t *, uint8_t *); |
578 | static void wm_dump_mbuf_chain(struct wm_softc *, struct mbuf *); | | 578 | static void wm_dump_mbuf_chain(struct wm_softc *, struct mbuf *); |
579 | static void wm_82547_txfifo_stall(void *); | | 579 | static void wm_82547_txfifo_stall(void *); |
580 | static int wm_82547_txfifo_bugchk(struct wm_softc *, struct mbuf *); | | 580 | static int wm_82547_txfifo_bugchk(struct wm_softc *, struct mbuf *); |
581 | /* DMA related */ | | 581 | /* DMA related */ |
582 | static int wm_alloc_tx_descs(struct wm_softc *); | | 582 | static int wm_alloc_tx_descs(struct wm_softc *); |
583 | static void wm_free_tx_descs(struct wm_softc *); | | 583 | static void wm_free_tx_descs(struct wm_softc *); |
584 | static void wm_init_tx_descs(struct wm_softc *); | | 584 | static void wm_init_tx_descs(struct wm_softc *); |
585 | static void wm_init_tx_regs(struct wm_softc *); | | 585 | static void wm_init_tx_regs(struct wm_softc *); |
586 | static int wm_alloc_rx_descs(struct wm_softc *); | | 586 | static int wm_alloc_rx_descs(struct wm_softc *); |
587 | static void wm_free_rx_descs(struct wm_softc *); | | 587 | static void wm_free_rx_descs(struct wm_softc *); |
588 | static void wm_init_rx_regs(struct wm_softc *); | | 588 | static void wm_init_rx_regs(struct wm_softc *); |
589 | static int wm_alloc_tx_buffer(struct wm_softc *); | | 589 | static int wm_alloc_tx_buffer(struct wm_softc *); |
590 | static void wm_free_tx_buffer(struct wm_softc *); | | 590 | static void wm_free_tx_buffer(struct wm_softc *); |
591 | static void wm_init_tx_buffer(struct wm_softc *); | | 591 | static void wm_init_tx_buffer(struct wm_softc *); |
592 | static int wm_alloc_rx_buffer(struct wm_softc *); | | 592 | static int wm_alloc_rx_buffer(struct wm_softc *); |
593 | static void wm_free_rx_buffer(struct wm_softc *); | | 593 | static void wm_free_rx_buffer(struct wm_softc *); |
594 | static int wm_init_rx_buffer(struct wm_softc *); | | 594 | static int wm_init_rx_buffer(struct wm_softc *); |
595 | static void wm_init_tx_queue(struct wm_softc *); | | 595 | static void wm_init_tx_queue(struct wm_softc *); |
596 | static int wm_init_rx_queue(struct wm_softc *); | | 596 | static int wm_init_rx_queue(struct wm_softc *); |
597 | static int wm_alloc_txrx_queues(struct wm_softc *); | | 597 | static int wm_alloc_txrx_queues(struct wm_softc *); |
598 | static void wm_free_txrx_queues(struct wm_softc *); | | 598 | static void wm_free_txrx_queues(struct wm_softc *); |
599 | static int wm_init_txrx_queues(struct wm_softc *); | | 599 | static int wm_init_txrx_queues(struct wm_softc *); |
600 | /* Start */ | | 600 | /* Start */ |
601 | static void wm_start(struct ifnet *); | | 601 | static void wm_start(struct ifnet *); |
602 | static void wm_start_locked(struct ifnet *); | | 602 | static void wm_start_locked(struct ifnet *); |
603 | static int wm_nq_tx_offload(struct wm_softc *, struct wm_txsoft *, | | 603 | static int wm_nq_tx_offload(struct wm_softc *, struct wm_txsoft *, |
604 | uint32_t *, uint32_t *, bool *); | | 604 | uint32_t *, uint32_t *, bool *); |
605 | static void wm_nq_start(struct ifnet *); | | 605 | static void wm_nq_start(struct ifnet *); |
606 | static void wm_nq_start_locked(struct ifnet *); | | 606 | static void wm_nq_start_locked(struct ifnet *); |
607 | /* Interrupt */ | | 607 | /* Interrupt */ |
608 | static int wm_txeof(struct wm_softc *); | | 608 | static int wm_txeof(struct wm_softc *); |
609 | static void wm_rxeof(struct wm_softc *); | | 609 | static void wm_rxeof(struct wm_softc *); |
610 | static void wm_linkintr_gmii(struct wm_softc *, uint32_t); | | 610 | static void wm_linkintr_gmii(struct wm_softc *, uint32_t); |
611 | static void wm_linkintr_tbi(struct wm_softc *, uint32_t); | | 611 | static void wm_linkintr_tbi(struct wm_softc *, uint32_t); |
612 | static void wm_linkintr_serdes(struct wm_softc *, uint32_t); | | 612 | static void wm_linkintr_serdes(struct wm_softc *, uint32_t); |
613 | static void wm_linkintr(struct wm_softc *, uint32_t); | | 613 | static void wm_linkintr(struct wm_softc *, uint32_t); |
614 | static int wm_intr_legacy(void *); | | 614 | static int wm_intr_legacy(void *); |
615 | #ifdef WM_MSI_MSIX | | 615 | #ifdef WM_MSI_MSIX |
| | | 616 | static int wm_setup_legacy(struct wm_softc *); |
| | | 617 | static int wm_setup_msix(struct wm_softc *); |
616 | static int wm_txintr_msix(void *); | | 618 | static int wm_txintr_msix(void *); |
617 | static int wm_rxintr_msix(void *); | | 619 | static int wm_rxintr_msix(void *); |
618 | static int wm_linkintr_msix(void *); | | 620 | static int wm_linkintr_msix(void *); |
619 | #endif | | 621 | #endif |
620 | | | 622 | |
621 | /* | | 623 | /* |
622 | * Media related. | | 624 | * Media related. |
623 | * GMII, SGMII, TBI, SERDES and SFP. | | 625 | * GMII, SGMII, TBI, SERDES and SFP. |
624 | */ | | 626 | */ |
625 | /* Common */ | | 627 | /* Common */ |
626 | static void wm_tbi_serdes_set_linkled(struct wm_softc *); | | 628 | static void wm_tbi_serdes_set_linkled(struct wm_softc *); |
627 | /* GMII related */ | | 629 | /* GMII related */ |
628 | static void wm_gmii_reset(struct wm_softc *); | | 630 | static void wm_gmii_reset(struct wm_softc *); |
629 | static int wm_get_phy_id_82575(struct wm_softc *); | | 631 | static int wm_get_phy_id_82575(struct wm_softc *); |
630 | static void wm_gmii_mediainit(struct wm_softc *, pci_product_id_t); | | 632 | static void wm_gmii_mediainit(struct wm_softc *, pci_product_id_t); |
631 | static int wm_gmii_mediachange(struct ifnet *); | | 633 | static int wm_gmii_mediachange(struct ifnet *); |
632 | static void wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *); | | 634 | static void wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *); |
633 | static void wm_i82543_mii_sendbits(struct wm_softc *, uint32_t, int); | | 635 | static void wm_i82543_mii_sendbits(struct wm_softc *, uint32_t, int); |
634 | static uint32_t wm_i82543_mii_recvbits(struct wm_softc *); | | 636 | static uint32_t wm_i82543_mii_recvbits(struct wm_softc *); |
635 | static int wm_gmii_i82543_readreg(device_t, int, int); | | 637 | static int wm_gmii_i82543_readreg(device_t, int, int); |
636 | static void wm_gmii_i82543_writereg(device_t, int, int, int); | | 638 | static void wm_gmii_i82543_writereg(device_t, int, int, int); |
637 | static int wm_gmii_i82544_readreg(device_t, int, int); | | 639 | static int wm_gmii_i82544_readreg(device_t, int, int); |
638 | static void wm_gmii_i82544_writereg(device_t, int, int, int); | | 640 | static void wm_gmii_i82544_writereg(device_t, int, int, int); |
639 | static int wm_gmii_i80003_readreg(device_t, int, int); | | 641 | static int wm_gmii_i80003_readreg(device_t, int, int); |
640 | static void wm_gmii_i80003_writereg(device_t, int, int, int); | | 642 | static void wm_gmii_i80003_writereg(device_t, int, int, int); |
641 | static int wm_gmii_bm_readreg(device_t, int, int); | | 643 | static int wm_gmii_bm_readreg(device_t, int, int); |
642 | static void wm_gmii_bm_writereg(device_t, int, int, int); | | 644 | static void wm_gmii_bm_writereg(device_t, int, int, int); |
643 | static void wm_access_phy_wakeup_reg_bm(device_t, int, int16_t *, int); | | 645 | static void wm_access_phy_wakeup_reg_bm(device_t, int, int16_t *, int); |
644 | static int wm_gmii_hv_readreg(device_t, int, int); | | 646 | static int wm_gmii_hv_readreg(device_t, int, int); |
645 | static void wm_gmii_hv_writereg(device_t, int, int, int); | | 647 | static void wm_gmii_hv_writereg(device_t, int, int, int); |
646 | static int wm_gmii_82580_readreg(device_t, int, int); | | 648 | static int wm_gmii_82580_readreg(device_t, int, int); |
647 | static void wm_gmii_82580_writereg(device_t, int, int, int); | | 649 | static void wm_gmii_82580_writereg(device_t, int, int, int); |
648 | static int wm_gmii_gs40g_readreg(device_t, int, int); | | 650 | static int wm_gmii_gs40g_readreg(device_t, int, int); |
649 | static void wm_gmii_gs40g_writereg(device_t, int, int, int); | | 651 | static void wm_gmii_gs40g_writereg(device_t, int, int, int); |
650 | static void wm_gmii_statchg(struct ifnet *); | | 652 | static void wm_gmii_statchg(struct ifnet *); |
651 | static int wm_kmrn_readreg(struct wm_softc *, int); | | 653 | static int wm_kmrn_readreg(struct wm_softc *, int); |
652 | static void wm_kmrn_writereg(struct wm_softc *, int, int); | | 654 | static void wm_kmrn_writereg(struct wm_softc *, int, int); |
653 | /* SGMII */ | | 655 | /* SGMII */ |
654 | static bool wm_sgmii_uses_mdio(struct wm_softc *); | | 656 | static bool wm_sgmii_uses_mdio(struct wm_softc *); |
655 | static int wm_sgmii_readreg(device_t, int, int); | | 657 | static int wm_sgmii_readreg(device_t, int, int); |
656 | static void wm_sgmii_writereg(device_t, int, int, int); | | 658 | static void wm_sgmii_writereg(device_t, int, int, int); |
657 | /* TBI related */ | | 659 | /* TBI related */ |
658 | static void wm_tbi_mediainit(struct wm_softc *); | | 660 | static void wm_tbi_mediainit(struct wm_softc *); |
659 | static int wm_tbi_mediachange(struct ifnet *); | | 661 | static int wm_tbi_mediachange(struct ifnet *); |
660 | static void wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *); | | 662 | static void wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *); |
661 | static int wm_check_for_link(struct wm_softc *); | | 663 | static int wm_check_for_link(struct wm_softc *); |
662 | static void wm_tbi_tick(struct wm_softc *); | | 664 | static void wm_tbi_tick(struct wm_softc *); |
663 | /* SERDES related */ | | 665 | /* SERDES related */ |
664 | static void wm_serdes_power_up_link_82575(struct wm_softc *); | | 666 | static void wm_serdes_power_up_link_82575(struct wm_softc *); |
665 | static int wm_serdes_mediachange(struct ifnet *); | | 667 | static int wm_serdes_mediachange(struct ifnet *); |
666 | static void wm_serdes_mediastatus(struct ifnet *, struct ifmediareq *); | | 668 | static void wm_serdes_mediastatus(struct ifnet *, struct ifmediareq *); |
667 | static void wm_serdes_tick(struct wm_softc *); | | 669 | static void wm_serdes_tick(struct wm_softc *); |
668 | /* SFP related */ | | 670 | /* SFP related */ |
669 | static int wm_sfp_read_data_byte(struct wm_softc *, uint16_t, uint8_t *); | | 671 | static int wm_sfp_read_data_byte(struct wm_softc *, uint16_t, uint8_t *); |
670 | static uint32_t wm_sfp_get_media_type(struct wm_softc *); | | 672 | static uint32_t wm_sfp_get_media_type(struct wm_softc *); |
671 | | | 673 | |
672 | /* | | 674 | /* |
673 | * NVM related. | | 675 | * NVM related. |
674 | * Microwire, SPI (w/wo EERD) and Flash. | | 676 | * Microwire, SPI (w/wo EERD) and Flash. |
675 | */ | | 677 | */ |
676 | /* Misc functions */ | | 678 | /* Misc functions */ |
677 | static void wm_eeprom_sendbits(struct wm_softc *, uint32_t, int); | | 679 | static void wm_eeprom_sendbits(struct wm_softc *, uint32_t, int); |
678 | static void wm_eeprom_recvbits(struct wm_softc *, uint32_t *, int); | | 680 | static void wm_eeprom_recvbits(struct wm_softc *, uint32_t *, int); |
679 | static int wm_nvm_set_addrbits_size_eecd(struct wm_softc *); | | 681 | static int wm_nvm_set_addrbits_size_eecd(struct wm_softc *); |
680 | /* Microwire */ | | 682 | /* Microwire */ |
681 | static int wm_nvm_read_uwire(struct wm_softc *, int, int, uint16_t *); | | 683 | static int wm_nvm_read_uwire(struct wm_softc *, int, int, uint16_t *); |
682 | /* SPI */ | | 684 | /* SPI */ |
683 | static int wm_nvm_ready_spi(struct wm_softc *); | | 685 | static int wm_nvm_ready_spi(struct wm_softc *); |
684 | static int wm_nvm_read_spi(struct wm_softc *, int, int, uint16_t *); | | 686 | static int wm_nvm_read_spi(struct wm_softc *, int, int, uint16_t *); |
685 | /* Using with EERD */ | | 687 | /* Using with EERD */ |
686 | static int wm_poll_eerd_eewr_done(struct wm_softc *, int); | | 688 | static int wm_poll_eerd_eewr_done(struct wm_softc *, int); |
687 | static int wm_nvm_read_eerd(struct wm_softc *, int, int, uint16_t *); | | 689 | static int wm_nvm_read_eerd(struct wm_softc *, int, int, uint16_t *); |
688 | /* Flash */ | | 690 | /* Flash */ |
689 | static int wm_nvm_valid_bank_detect_ich8lan(struct wm_softc *, | | 691 | static int wm_nvm_valid_bank_detect_ich8lan(struct wm_softc *, |
690 | unsigned int *); | | 692 | unsigned int *); |
691 | static int32_t wm_ich8_cycle_init(struct wm_softc *); | | 693 | static int32_t wm_ich8_cycle_init(struct wm_softc *); |
692 | static int32_t wm_ich8_flash_cycle(struct wm_softc *, uint32_t); | | 694 | static int32_t wm_ich8_flash_cycle(struct wm_softc *, uint32_t); |
693 | static int32_t wm_read_ich8_data(struct wm_softc *, uint32_t, uint32_t, | | 695 | static int32_t wm_read_ich8_data(struct wm_softc *, uint32_t, uint32_t, |
694 | uint16_t *); | | 696 | uint16_t *); |
695 | static int32_t wm_read_ich8_byte(struct wm_softc *, uint32_t, uint8_t *); | | 697 | static int32_t wm_read_ich8_byte(struct wm_softc *, uint32_t, uint8_t *); |
696 | static int32_t wm_read_ich8_word(struct wm_softc *, uint32_t, uint16_t *); | | 698 | static int32_t wm_read_ich8_word(struct wm_softc *, uint32_t, uint16_t *); |
697 | static int wm_nvm_read_ich8(struct wm_softc *, int, int, uint16_t *); | | 699 | static int wm_nvm_read_ich8(struct wm_softc *, int, int, uint16_t *); |
698 | /* iNVM */ | | 700 | /* iNVM */ |
699 | static int wm_nvm_read_word_invm(struct wm_softc *, uint16_t, uint16_t *); | | 701 | static int wm_nvm_read_word_invm(struct wm_softc *, uint16_t, uint16_t *); |
700 | static int wm_nvm_read_invm(struct wm_softc *, int, int, uint16_t *); | | 702 | static int wm_nvm_read_invm(struct wm_softc *, int, int, uint16_t *); |
701 | /* Lock, detecting NVM type, validate checksum and read */ | | 703 | /* Lock, detecting NVM type, validate checksum and read */ |
702 | static int wm_nvm_acquire(struct wm_softc *); | | 704 | static int wm_nvm_acquire(struct wm_softc *); |
703 | static void wm_nvm_release(struct wm_softc *); | | 705 | static void wm_nvm_release(struct wm_softc *); |
704 | static int wm_nvm_is_onboard_eeprom(struct wm_softc *); | | 706 | static int wm_nvm_is_onboard_eeprom(struct wm_softc *); |
705 | static int wm_nvm_get_flash_presence_i210(struct wm_softc *); | | 707 | static int wm_nvm_get_flash_presence_i210(struct wm_softc *); |
706 | static int wm_nvm_validate_checksum(struct wm_softc *); | | 708 | static int wm_nvm_validate_checksum(struct wm_softc *); |
707 | static void wm_nvm_version_invm(struct wm_softc *); | | 709 | static void wm_nvm_version_invm(struct wm_softc *); |
708 | static void wm_nvm_version(struct wm_softc *); | | 710 | static void wm_nvm_version(struct wm_softc *); |
709 | static int wm_nvm_read(struct wm_softc *, int, int, uint16_t *); | | 711 | static int wm_nvm_read(struct wm_softc *, int, int, uint16_t *); |
710 | | | 712 | |
711 | /* | | 713 | /* |
712 | * Hardware semaphores. | | 714 | * Hardware semaphores. |
713 | * Very complexed... | | 715 | * Very complexed... |
714 | */ | | 716 | */ |
715 | static int wm_get_swsm_semaphore(struct wm_softc *); | | 717 | static int wm_get_swsm_semaphore(struct wm_softc *); |
716 | static void wm_put_swsm_semaphore(struct wm_softc *); | | 718 | static void wm_put_swsm_semaphore(struct wm_softc *); |
717 | static int wm_get_swfw_semaphore(struct wm_softc *, uint16_t); | | 719 | static int wm_get_swfw_semaphore(struct wm_softc *, uint16_t); |
718 | static void wm_put_swfw_semaphore(struct wm_softc *, uint16_t); | | 720 | static void wm_put_swfw_semaphore(struct wm_softc *, uint16_t); |
719 | static int wm_get_swfwhw_semaphore(struct wm_softc *); | | 721 | static int wm_get_swfwhw_semaphore(struct wm_softc *); |
720 | static void wm_put_swfwhw_semaphore(struct wm_softc *); | | 722 | static void wm_put_swfwhw_semaphore(struct wm_softc *); |
721 | static int wm_get_hw_semaphore_82573(struct wm_softc *); | | 723 | static int wm_get_hw_semaphore_82573(struct wm_softc *); |
722 | static void wm_put_hw_semaphore_82573(struct wm_softc *); | | 724 | static void wm_put_hw_semaphore_82573(struct wm_softc *); |
723 | | | 725 | |
724 | /* | | 726 | /* |
725 | * Management mode and power management related subroutines. | | 727 | * Management mode and power management related subroutines. |
726 | * BMC, AMT, suspend/resume and EEE. | | 728 | * BMC, AMT, suspend/resume and EEE. |
727 | */ | | 729 | */ |
728 | static int wm_check_mng_mode(struct wm_softc *); | | 730 | static int wm_check_mng_mode(struct wm_softc *); |
729 | static int wm_check_mng_mode_ich8lan(struct wm_softc *); | | 731 | static int wm_check_mng_mode_ich8lan(struct wm_softc *); |
730 | static int wm_check_mng_mode_82574(struct wm_softc *); | | 732 | static int wm_check_mng_mode_82574(struct wm_softc *); |
731 | static int wm_check_mng_mode_generic(struct wm_softc *); | | 733 | static int wm_check_mng_mode_generic(struct wm_softc *); |
732 | static int wm_enable_mng_pass_thru(struct wm_softc *); | | 734 | static int wm_enable_mng_pass_thru(struct wm_softc *); |
733 | static int wm_check_reset_block(struct wm_softc *); | | 735 | static int wm_check_reset_block(struct wm_softc *); |
734 | static void wm_get_hw_control(struct wm_softc *); | | 736 | static void wm_get_hw_control(struct wm_softc *); |
735 | static void wm_release_hw_control(struct wm_softc *); | | 737 | static void wm_release_hw_control(struct wm_softc *); |
736 | static void wm_gate_hw_phy_config_ich8lan(struct wm_softc *, int); | | 738 | static void wm_gate_hw_phy_config_ich8lan(struct wm_softc *, int); |
737 | static void wm_smbustopci(struct wm_softc *); | | 739 | static void wm_smbustopci(struct wm_softc *); |
738 | static void wm_init_manageability(struct wm_softc *); | | 740 | static void wm_init_manageability(struct wm_softc *); |
739 | static void wm_release_manageability(struct wm_softc *); | | 741 | static void wm_release_manageability(struct wm_softc *); |
740 | static void wm_get_wakeup(struct wm_softc *); | | 742 | static void wm_get_wakeup(struct wm_softc *); |
741 | #ifdef WM_WOL | | 743 | #ifdef WM_WOL |
742 | static void wm_enable_phy_wakeup(struct wm_softc *); | | 744 | static void wm_enable_phy_wakeup(struct wm_softc *); |
743 | static void wm_igp3_phy_powerdown_workaround_ich8lan(struct wm_softc *); | | 745 | static void wm_igp3_phy_powerdown_workaround_ich8lan(struct wm_softc *); |
744 | static void wm_enable_wakeup(struct wm_softc *); | | 746 | static void wm_enable_wakeup(struct wm_softc *); |
745 | #endif | | 747 | #endif |
746 | /* EEE */ | | 748 | /* EEE */ |
747 | static void wm_set_eee_i350(struct wm_softc *); | | 749 | static void wm_set_eee_i350(struct wm_softc *); |
748 | | | 750 | |
749 | /* | | 751 | /* |
750 | * Workarounds (mainly PHY related). | | 752 | * Workarounds (mainly PHY related). |
751 | * Basically, PHY's workarounds are in the PHY drivers. | | 753 | * Basically, PHY's workarounds are in the PHY drivers. |
752 | */ | | 754 | */ |
753 | static void wm_kmrn_lock_loss_workaround_ich8lan(struct wm_softc *); | | 755 | static void wm_kmrn_lock_loss_workaround_ich8lan(struct wm_softc *); |
754 | static void wm_gig_downshift_workaround_ich8lan(struct wm_softc *); | | 756 | static void wm_gig_downshift_workaround_ich8lan(struct wm_softc *); |
755 | static void wm_hv_phy_workaround_ich8lan(struct wm_softc *); | | 757 | static void wm_hv_phy_workaround_ich8lan(struct wm_softc *); |
756 | static void wm_lv_phy_workaround_ich8lan(struct wm_softc *); | | 758 | static void wm_lv_phy_workaround_ich8lan(struct wm_softc *); |
757 | static void wm_k1_gig_workaround_hv(struct wm_softc *, int); | | 759 | static void wm_k1_gig_workaround_hv(struct wm_softc *, int); |
758 | static void wm_set_mdio_slow_mode_hv(struct wm_softc *); | | 760 | static void wm_set_mdio_slow_mode_hv(struct wm_softc *); |
759 | static void wm_configure_k1_ich8lan(struct wm_softc *, int); | | 761 | static void wm_configure_k1_ich8lan(struct wm_softc *, int); |
760 | static void wm_reset_init_script_82575(struct wm_softc *); | | 762 | static void wm_reset_init_script_82575(struct wm_softc *); |
761 | static void wm_reset_mdicnfg_82580(struct wm_softc *); | | 763 | static void wm_reset_mdicnfg_82580(struct wm_softc *); |
762 | static void wm_pll_workaround_i210(struct wm_softc *); | | 764 | static void wm_pll_workaround_i210(struct wm_softc *); |
763 | | | 765 | |
764 | #ifdef WM_MSI_MSIX | | | |
765 | struct _msix_matrix { | | | |
766 | const char *intrname; | | | |
767 | int(*func)(void *); | | | |
768 | int intridx; | | | |
769 | int cpuid; | | | |
770 | } msix_matrix[WM_MSIX_NINTR] = { | | | |
771 | { "TX", wm_txintr_msix, WM_MSIX_TXINTR_IDX, WM_MSIX_TXINTR_CPUID }, | | | |
772 | { "RX", wm_rxintr_msix, WM_MSIX_RXINTR_IDX, WM_MSIX_RXINTR_CPUID }, | | | |
773 | { "LINK", wm_linkintr_msix, WM_MSIX_LINKINTR_IDX, | | | |
774 | WM_MSIX_LINKINTR_CPUID }, | | | |
775 | }; | | | |
776 | #endif | | | |
777 | | | | |
778 | CFATTACH_DECL3_NEW(wm, sizeof(struct wm_softc), | | 766 | CFATTACH_DECL3_NEW(wm, sizeof(struct wm_softc), |
779 | wm_match, wm_attach, wm_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); | | 767 | wm_match, wm_attach, wm_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); |
780 | | | 768 | |
781 | /* | | 769 | /* |
782 | * Devices supported by this driver. | | 770 | * Devices supported by this driver. |
783 | */ | | 771 | */ |
784 | static const struct wm_product { | | 772 | static const struct wm_product { |
785 | pci_vendor_id_t wmp_vendor; | | 773 | pci_vendor_id_t wmp_vendor; |
786 | pci_product_id_t wmp_product; | | 774 | pci_product_id_t wmp_product; |
787 | const char *wmp_name; | | 775 | const char *wmp_name; |
788 | wm_chip_type wmp_type; | | 776 | wm_chip_type wmp_type; |
789 | uint32_t wmp_flags; | | 777 | uint32_t wmp_flags; |
790 | #define WMP_F_UNKNOWN WM_MEDIATYPE_UNKNOWN | | 778 | #define WMP_F_UNKNOWN WM_MEDIATYPE_UNKNOWN |
791 | #define WMP_F_FIBER WM_MEDIATYPE_FIBER | | 779 | #define WMP_F_FIBER WM_MEDIATYPE_FIBER |
792 | #define WMP_F_COPPER WM_MEDIATYPE_COPPER | | 780 | #define WMP_F_COPPER WM_MEDIATYPE_COPPER |
793 | #define WMP_F_SERDES WM_MEDIATYPE_SERDES | | 781 | #define WMP_F_SERDES WM_MEDIATYPE_SERDES |
794 | #define WMP_MEDIATYPE(x) ((x) & 0x03) | | 782 | #define WMP_MEDIATYPE(x) ((x) & 0x03) |
795 | } wm_products[] = { | | 783 | } wm_products[] = { |
796 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542, | | 784 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542, |
797 | "Intel i82542 1000BASE-X Ethernet", | | 785 | "Intel i82542 1000BASE-X Ethernet", |
798 | WM_T_82542_2_1, WMP_F_FIBER }, | | 786 | WM_T_82542_2_1, WMP_F_FIBER }, |
799 | | | 787 | |
800 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER, | | 788 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER, |
801 | "Intel i82543GC 1000BASE-X Ethernet", | | 789 | "Intel i82543GC 1000BASE-X Ethernet", |
802 | WM_T_82543, WMP_F_FIBER }, | | 790 | WM_T_82543, WMP_F_FIBER }, |
803 | | | 791 | |
804 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER, | | 792 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER, |
805 | "Intel i82543GC 1000BASE-T Ethernet", | | 793 | "Intel i82543GC 1000BASE-T Ethernet", |
806 | WM_T_82543, WMP_F_COPPER }, | | 794 | WM_T_82543, WMP_F_COPPER }, |
807 | | | 795 | |
808 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER, | | 796 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER, |
809 | "Intel i82544EI 1000BASE-T Ethernet", | | 797 | "Intel i82544EI 1000BASE-T Ethernet", |
810 | WM_T_82544, WMP_F_COPPER }, | | 798 | WM_T_82544, WMP_F_COPPER }, |
811 | | | 799 | |
812 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER, | | 800 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER, |
813 | "Intel i82544EI 1000BASE-X Ethernet", | | 801 | "Intel i82544EI 1000BASE-X Ethernet", |
814 | WM_T_82544, WMP_F_FIBER }, | | 802 | WM_T_82544, WMP_F_FIBER }, |
815 | | | 803 | |
816 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER, | | 804 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER, |
817 | "Intel i82544GC 1000BASE-T Ethernet", | | 805 | "Intel i82544GC 1000BASE-T Ethernet", |
818 | WM_T_82544, WMP_F_COPPER }, | | 806 | WM_T_82544, WMP_F_COPPER }, |
819 | | | 807 | |
820 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM, | | 808 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM, |
821 | "Intel i82544GC (LOM) 1000BASE-T Ethernet", | | 809 | "Intel i82544GC (LOM) 1000BASE-T Ethernet", |
822 | WM_T_82544, WMP_F_COPPER }, | | 810 | WM_T_82544, WMP_F_COPPER }, |
823 | | | 811 | |
824 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM, | | 812 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM, |
825 | "Intel i82540EM 1000BASE-T Ethernet", | | 813 | "Intel i82540EM 1000BASE-T Ethernet", |
826 | WM_T_82540, WMP_F_COPPER }, | | 814 | WM_T_82540, WMP_F_COPPER }, |
827 | | | 815 | |
828 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM, | | 816 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM, |
829 | "Intel i82540EM (LOM) 1000BASE-T Ethernet", | | 817 | "Intel i82540EM (LOM) 1000BASE-T Ethernet", |
830 | WM_T_82540, WMP_F_COPPER }, | | 818 | WM_T_82540, WMP_F_COPPER }, |
831 | | | 819 | |
832 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM, | | 820 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM, |
833 | "Intel i82540EP 1000BASE-T Ethernet", | | 821 | "Intel i82540EP 1000BASE-T Ethernet", |
834 | WM_T_82540, WMP_F_COPPER }, | | 822 | WM_T_82540, WMP_F_COPPER }, |
835 | | | 823 | |
836 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP, | | 824 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP, |
837 | "Intel i82540EP 1000BASE-T Ethernet", | | 825 | "Intel i82540EP 1000BASE-T Ethernet", |
838 | WM_T_82540, WMP_F_COPPER }, | | 826 | WM_T_82540, WMP_F_COPPER }, |
839 | | | 827 | |
840 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP, | | 828 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP, |
841 | "Intel i82540EP 1000BASE-T Ethernet", | | 829 | "Intel i82540EP 1000BASE-T Ethernet", |
842 | WM_T_82540, WMP_F_COPPER }, | | 830 | WM_T_82540, WMP_F_COPPER }, |
843 | | | 831 | |
844 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER, | | 832 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER, |
845 | "Intel i82545EM 1000BASE-T Ethernet", | | 833 | "Intel i82545EM 1000BASE-T Ethernet", |
846 | WM_T_82545, WMP_F_COPPER }, | | 834 | WM_T_82545, WMP_F_COPPER }, |
847 | | | 835 | |
848 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER, | | 836 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER, |
849 | "Intel i82545GM 1000BASE-T Ethernet", | | 837 | "Intel i82545GM 1000BASE-T Ethernet", |
850 | WM_T_82545_3, WMP_F_COPPER }, | | 838 | WM_T_82545_3, WMP_F_COPPER }, |
851 | | | 839 | |
852 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER, | | 840 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER, |
853 | "Intel i82545GM 1000BASE-X Ethernet", | | 841 | "Intel i82545GM 1000BASE-X Ethernet", |
854 | WM_T_82545_3, WMP_F_FIBER }, | | 842 | WM_T_82545_3, WMP_F_FIBER }, |
855 | | | 843 | |
856 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES, | | 844 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES, |
857 | "Intel i82545GM Gigabit Ethernet (SERDES)", | | 845 | "Intel i82545GM Gigabit Ethernet (SERDES)", |
858 | WM_T_82545_3, WMP_F_SERDES }, | | 846 | WM_T_82545_3, WMP_F_SERDES }, |
859 | | | 847 | |
860 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER, | | 848 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER, |
861 | "Intel i82546EB 1000BASE-T Ethernet", | | 849 | "Intel i82546EB 1000BASE-T Ethernet", |
862 | WM_T_82546, WMP_F_COPPER }, | | 850 | WM_T_82546, WMP_F_COPPER }, |
863 | | | 851 | |
864 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD, | | 852 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD, |
865 | "Intel i82546EB 1000BASE-T Ethernet", | | 853 | "Intel i82546EB 1000BASE-T Ethernet", |
866 | WM_T_82546, WMP_F_COPPER }, | | 854 | WM_T_82546, WMP_F_COPPER }, |
867 | | | 855 | |
868 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER, | | 856 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER, |
869 | "Intel i82545EM 1000BASE-X Ethernet", | | 857 | "Intel i82545EM 1000BASE-X Ethernet", |
870 | WM_T_82545, WMP_F_FIBER }, | | 858 | WM_T_82545, WMP_F_FIBER }, |
871 | | | 859 | |
872 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER, | | 860 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER, |
873 | "Intel i82546EB 1000BASE-X Ethernet", | | 861 | "Intel i82546EB 1000BASE-X Ethernet", |
874 | WM_T_82546, WMP_F_FIBER }, | | 862 | WM_T_82546, WMP_F_FIBER }, |
875 | | | 863 | |
876 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER, | | 864 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER, |
877 | "Intel i82546GB 1000BASE-T Ethernet", | | 865 | "Intel i82546GB 1000BASE-T Ethernet", |
878 | WM_T_82546_3, WMP_F_COPPER }, | | 866 | WM_T_82546_3, WMP_F_COPPER }, |
879 | | | 867 | |
880 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER, | | 868 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER, |
881 | "Intel i82546GB 1000BASE-X Ethernet", | | 869 | "Intel i82546GB 1000BASE-X Ethernet", |
882 | WM_T_82546_3, WMP_F_FIBER }, | | 870 | WM_T_82546_3, WMP_F_FIBER }, |
883 | | | 871 | |
884 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES, | | 872 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES, |
885 | "Intel i82546GB Gigabit Ethernet (SERDES)", | | 873 | "Intel i82546GB Gigabit Ethernet (SERDES)", |
886 | WM_T_82546_3, WMP_F_SERDES }, | | 874 | WM_T_82546_3, WMP_F_SERDES }, |
887 | | | 875 | |
888 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER, | | 876 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER, |
889 | "i82546GB quad-port Gigabit Ethernet", | | 877 | "i82546GB quad-port Gigabit Ethernet", |
890 | WM_T_82546_3, WMP_F_COPPER }, | | 878 | WM_T_82546_3, WMP_F_COPPER }, |
891 | | | 879 | |
892 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER_KSP3, | | 880 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER_KSP3, |
893 | "i82546GB quad-port Gigabit Ethernet (KSP3)", | | 881 | "i82546GB quad-port Gigabit Ethernet (KSP3)", |
894 | WM_T_82546_3, WMP_F_COPPER }, | | 882 | WM_T_82546_3, WMP_F_COPPER }, |
895 | | | 883 | |
896 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_PCIE, | | 884 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_PCIE, |
897 | "Intel PRO/1000MT (82546GB)", | | 885 | "Intel PRO/1000MT (82546GB)", |
898 | WM_T_82546_3, WMP_F_COPPER }, | | 886 | WM_T_82546_3, WMP_F_COPPER }, |
899 | | | 887 | |
900 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI, | | 888 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI, |
901 | "Intel i82541EI 1000BASE-T Ethernet", | | 889 | "Intel i82541EI 1000BASE-T Ethernet", |
902 | WM_T_82541, WMP_F_COPPER }, | | 890 | WM_T_82541, WMP_F_COPPER }, |
903 | | | 891 | |
904 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER_LOM, | | 892 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER_LOM, |
905 | "Intel i82541ER (LOM) 1000BASE-T Ethernet", | | 893 | "Intel i82541ER (LOM) 1000BASE-T Ethernet", |
906 | WM_T_82541, WMP_F_COPPER }, | | 894 | WM_T_82541, WMP_F_COPPER }, |
907 | | | 895 | |
908 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE, | | 896 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE, |
909 | "Intel i82541EI Mobile 1000BASE-T Ethernet", | | 897 | "Intel i82541EI Mobile 1000BASE-T Ethernet", |
910 | WM_T_82541, WMP_F_COPPER }, | | 898 | WM_T_82541, WMP_F_COPPER }, |
911 | | | 899 | |
912 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER, | | 900 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER, |
913 | "Intel i82541ER 1000BASE-T Ethernet", | | 901 | "Intel i82541ER 1000BASE-T Ethernet", |
914 | WM_T_82541_2, WMP_F_COPPER }, | | 902 | WM_T_82541_2, WMP_F_COPPER }, |
915 | | | 903 | |
916 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI, | | 904 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI, |
917 | "Intel i82541GI 1000BASE-T Ethernet", | | 905 | "Intel i82541GI 1000BASE-T Ethernet", |
918 | WM_T_82541_2, WMP_F_COPPER }, | | 906 | WM_T_82541_2, WMP_F_COPPER }, |
919 | | | 907 | |
920 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE, | | 908 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE, |
921 | "Intel i82541GI Mobile 1000BASE-T Ethernet", | | 909 | "Intel i82541GI Mobile 1000BASE-T Ethernet", |
922 | WM_T_82541_2, WMP_F_COPPER }, | | 910 | WM_T_82541_2, WMP_F_COPPER }, |
923 | | | 911 | |
924 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541PI, | | 912 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541PI, |
925 | "Intel i82541PI 1000BASE-T Ethernet", | | 913 | "Intel i82541PI 1000BASE-T Ethernet", |
926 | WM_T_82541_2, WMP_F_COPPER }, | | 914 | WM_T_82541_2, WMP_F_COPPER }, |
927 | | | 915 | |
928 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI, | | 916 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI, |
929 | "Intel i82547EI 1000BASE-T Ethernet", | | 917 | "Intel i82547EI 1000BASE-T Ethernet", |
930 | WM_T_82547, WMP_F_COPPER }, | | 918 | WM_T_82547, WMP_F_COPPER }, |
931 | | | 919 | |
932 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI_MOBILE, | | 920 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI_MOBILE, |
933 | "Intel i82547EI Mobile 1000BASE-T Ethernet", | | 921 | "Intel i82547EI Mobile 1000BASE-T Ethernet", |
934 | WM_T_82547, WMP_F_COPPER }, | | 922 | WM_T_82547, WMP_F_COPPER }, |
935 | | | 923 | |
936 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI, | | 924 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI, |
937 | "Intel i82547GI 1000BASE-T Ethernet", | | 925 | "Intel i82547GI 1000BASE-T Ethernet", |
938 | WM_T_82547_2, WMP_F_COPPER }, | | 926 | WM_T_82547_2, WMP_F_COPPER }, |
939 | | | 927 | |
940 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_COPPER, | | 928 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_COPPER, |
941 | "Intel PRO/1000 PT (82571EB)", | | 929 | "Intel PRO/1000 PT (82571EB)", |
942 | WM_T_82571, WMP_F_COPPER }, | | 930 | WM_T_82571, WMP_F_COPPER }, |
943 | | | 931 | |
944 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_FIBER, | | 932 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_FIBER, |
945 | "Intel PRO/1000 PF (82571EB)", | | 933 | "Intel PRO/1000 PF (82571EB)", |
946 | WM_T_82571, WMP_F_FIBER }, | | 934 | WM_T_82571, WMP_F_FIBER }, |
947 | | | 935 | |
948 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SERDES, | | 936 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SERDES, |
949 | "Intel PRO/1000 PB (82571EB)", | | 937 | "Intel PRO/1000 PB (82571EB)", |
950 | WM_T_82571, WMP_F_SERDES }, | | 938 | WM_T_82571, WMP_F_SERDES }, |
951 | | | 939 | |
952 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_COPPER, | | 940 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_COPPER, |
953 | "Intel PRO/1000 QT (82571EB)", | | 941 | "Intel PRO/1000 QT (82571EB)", |
954 | WM_T_82571, WMP_F_COPPER }, | | 942 | WM_T_82571, WMP_F_COPPER }, |
955 | | | 943 | |
956 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571GB_QUAD_COPPER, | | 944 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571GB_QUAD_COPPER, |
957 | "Intel PRO/1000 PT Quad Port Server Adapter", | | 945 | "Intel PRO/1000 PT Quad Port Server Adapter", |
958 | WM_T_82571, WMP_F_COPPER, }, | | 946 | WM_T_82571, WMP_F_COPPER, }, |
959 | | | 947 | |
960 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571PT_QUAD_COPPER, | | 948 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571PT_QUAD_COPPER, |
961 | "Intel Gigabit PT Quad Port Server ExpressModule", | | 949 | "Intel Gigabit PT Quad Port Server ExpressModule", |
962 | WM_T_82571, WMP_F_COPPER, }, | | 950 | WM_T_82571, WMP_F_COPPER, }, |
963 | | | 951 | |
964 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_DUAL_SERDES, | | 952 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_DUAL_SERDES, |
965 | "Intel 82571EB Dual Gigabit Ethernet (SERDES)", | | 953 | "Intel 82571EB Dual Gigabit Ethernet (SERDES)", |
966 | WM_T_82571, WMP_F_SERDES, }, | | 954 | WM_T_82571, WMP_F_SERDES, }, |
967 | | | 955 | |
968 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_SERDES, | | 956 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_SERDES, |
969 | "Intel 82571EB Quad Gigabit Ethernet (SERDES)", | | 957 | "Intel 82571EB Quad Gigabit Ethernet (SERDES)", |
970 | WM_T_82571, WMP_F_SERDES, }, | | 958 | WM_T_82571, WMP_F_SERDES, }, |
971 | | | 959 | |
972 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_FIBER, | | 960 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_FIBER, |
973 | "Intel 82571EB Quad 1000baseX Ethernet", | | 961 | "Intel 82571EB Quad 1000baseX Ethernet", |
974 | WM_T_82571, WMP_F_FIBER, }, | | 962 | WM_T_82571, WMP_F_FIBER, }, |
975 | | | 963 | |
976 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_COPPER, | | 964 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_COPPER, |
977 | "Intel i82572EI 1000baseT Ethernet", | | 965 | "Intel i82572EI 1000baseT Ethernet", |
978 | WM_T_82572, WMP_F_COPPER }, | | 966 | WM_T_82572, WMP_F_COPPER }, |
979 | | | 967 | |
980 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_FIBER, | | 968 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_FIBER, |
981 | "Intel i82572EI 1000baseX Ethernet", | | 969 | "Intel i82572EI 1000baseX Ethernet", |
982 | WM_T_82572, WMP_F_FIBER }, | | 970 | WM_T_82572, WMP_F_FIBER }, |
983 | | | 971 | |
984 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_SERDES, | | 972 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_SERDES, |
985 | "Intel i82572EI Gigabit Ethernet (SERDES)", | | 973 | "Intel i82572EI Gigabit Ethernet (SERDES)", |
986 | WM_T_82572, WMP_F_SERDES }, | | 974 | WM_T_82572, WMP_F_SERDES }, |
987 | | | 975 | |
988 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI, | | 976 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI, |
989 | "Intel i82572EI 1000baseT Ethernet", | | 977 | "Intel i82572EI 1000baseT Ethernet", |
990 | WM_T_82572, WMP_F_COPPER }, | | 978 | WM_T_82572, WMP_F_COPPER }, |
991 | | | 979 | |
992 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E, | | 980 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E, |
993 | "Intel i82573E", | | 981 | "Intel i82573E", |
994 | WM_T_82573, WMP_F_COPPER }, | | 982 | WM_T_82573, WMP_F_COPPER }, |
995 | | | 983 | |
996 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_IAMT, | | 984 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_IAMT, |
997 | "Intel i82573E IAMT", | | 985 | "Intel i82573E IAMT", |
998 | WM_T_82573, WMP_F_COPPER }, | | 986 | WM_T_82573, WMP_F_COPPER }, |
999 | | | 987 | |
1000 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L, | | 988 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L, |
1001 | "Intel i82573L Gigabit Ethernet", | | 989 | "Intel i82573L Gigabit Ethernet", |
1002 | WM_T_82573, WMP_F_COPPER }, | | 990 | WM_T_82573, WMP_F_COPPER }, |
1003 | | | 991 | |
1004 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574L, | | 992 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574L, |
1005 | "Intel i82574L", | | 993 | "Intel i82574L", |
1006 | WM_T_82574, WMP_F_COPPER }, | | 994 | WM_T_82574, WMP_F_COPPER }, |
1007 | | | 995 | |
1008 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574LA, | | 996 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574LA, |
1009 | "Intel i82574L", | | 997 | "Intel i82574L", |
1010 | WM_T_82574, WMP_F_COPPER }, | | 998 | WM_T_82574, WMP_F_COPPER }, |
1011 | | | 999 | |
1012 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82583V, | | 1000 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82583V, |
1013 | "Intel i82583V", | | 1001 | "Intel i82583V", |
1014 | WM_T_82583, WMP_F_COPPER }, | | 1002 | WM_T_82583, WMP_F_COPPER }, |
1015 | | | 1003 | |
1016 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_CPR_DPT, | | 1004 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_CPR_DPT, |
1017 | "i80003 dual 1000baseT Ethernet", | | 1005 | "i80003 dual 1000baseT Ethernet", |
1018 | WM_T_80003, WMP_F_COPPER }, | | 1006 | WM_T_80003, WMP_F_COPPER }, |
1019 | | | 1007 | |
1020 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_FIB_DPT, | | 1008 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_FIB_DPT, |
1021 | "i80003 dual 1000baseX Ethernet", | | 1009 | "i80003 dual 1000baseX Ethernet", |
1022 | WM_T_80003, WMP_F_COPPER }, | | 1010 | WM_T_80003, WMP_F_COPPER }, |
1023 | | | 1011 | |
1024 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_SDS_DPT, | | 1012 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_SDS_DPT, |
1025 | "Intel i80003ES2 dual Gigabit Ethernet (SERDES)", | | 1013 | "Intel i80003ES2 dual Gigabit Ethernet (SERDES)", |
1026 | WM_T_80003, WMP_F_SERDES }, | | 1014 | WM_T_80003, WMP_F_SERDES }, |
1027 | | | 1015 | |
1028 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_CPR_SPT, | | 1016 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_CPR_SPT, |
1029 | "Intel i80003 1000baseT Ethernet", | | 1017 | "Intel i80003 1000baseT Ethernet", |
1030 | WM_T_80003, WMP_F_COPPER }, | | 1018 | WM_T_80003, WMP_F_COPPER }, |
1031 | | | 1019 | |
1032 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_SDS_SPT, | | 1020 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_SDS_SPT, |
1033 | "Intel i80003 Gigabit Ethernet (SERDES)", | | 1021 | "Intel i80003 Gigabit Ethernet (SERDES)", |
1034 | WM_T_80003, WMP_F_SERDES }, | | 1022 | WM_T_80003, WMP_F_SERDES }, |
1035 | | | 1023 | |
1036 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_M_AMT, | | 1024 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_M_AMT, |
1037 | "Intel i82801H (M_AMT) LAN Controller", | | 1025 | "Intel i82801H (M_AMT) LAN Controller", |
1038 | WM_T_ICH8, WMP_F_COPPER }, | | 1026 | WM_T_ICH8, WMP_F_COPPER }, |
1039 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_AMT, | | 1027 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_AMT, |
1040 | "Intel i82801H (AMT) LAN Controller", | | 1028 | "Intel i82801H (AMT) LAN Controller", |
1041 | WM_T_ICH8, WMP_F_COPPER }, | | 1029 | WM_T_ICH8, WMP_F_COPPER }, |
1042 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LAN, | | 1030 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LAN, |
1043 | "Intel i82801H LAN Controller", | | 1031 | "Intel i82801H LAN Controller", |
1044 | WM_T_ICH8, WMP_F_COPPER }, | | 1032 | WM_T_ICH8, WMP_F_COPPER }, |
1045 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IFE_LAN, | | 1033 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IFE_LAN, |
1046 | "Intel i82801H (IFE) LAN Controller", | | 1034 | "Intel i82801H (IFE) LAN Controller", |
1047 | WM_T_ICH8, WMP_F_COPPER }, | | 1035 | WM_T_ICH8, WMP_F_COPPER }, |
1048 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_M_LAN, | | 1036 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_M_LAN, |
1049 | "Intel i82801H (M) LAN Controller", | | 1037 | "Intel i82801H (M) LAN Controller", |
1050 | WM_T_ICH8, WMP_F_COPPER }, | | 1038 | WM_T_ICH8, WMP_F_COPPER }, |
1051 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IFE_GT, | | 1039 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IFE_GT, |
1052 | "Intel i82801H IFE (GT) LAN Controller", | | 1040 | "Intel i82801H IFE (GT) LAN Controller", |
1053 | WM_T_ICH8, WMP_F_COPPER }, | | 1041 | WM_T_ICH8, WMP_F_COPPER }, |
1054 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IFE_G, | | 1042 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IFE_G, |
1055 | "Intel i82801H IFE (G) LAN Controller", | | 1043 | "Intel i82801H IFE (G) LAN Controller", |
1056 | WM_T_ICH8, WMP_F_COPPER }, | | 1044 | WM_T_ICH8, WMP_F_COPPER }, |
1057 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_AMT, | | 1045 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_AMT, |
1058 | "82801I (AMT) LAN Controller", | | 1046 | "82801I (AMT) LAN Controller", |
1059 | WM_T_ICH9, WMP_F_COPPER }, | | 1047 | WM_T_ICH9, WMP_F_COPPER }, |
1060 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IFE, | | 1048 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IFE, |
1061 | "82801I LAN Controller", | | 1049 | "82801I LAN Controller", |
1062 | WM_T_ICH9, WMP_F_COPPER }, | | 1050 | WM_T_ICH9, WMP_F_COPPER }, |
1063 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IFE_G, | | 1051 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IFE_G, |
1064 | "82801I (G) LAN Controller", | | 1052 | "82801I (G) LAN Controller", |
1065 | WM_T_ICH9, WMP_F_COPPER }, | | 1053 | WM_T_ICH9, WMP_F_COPPER }, |
1066 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IFE_GT, | | 1054 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IFE_GT, |
1067 | "82801I (GT) LAN Controller", | | 1055 | "82801I (GT) LAN Controller", |
1068 | WM_T_ICH9, WMP_F_COPPER }, | | 1056 | WM_T_ICH9, WMP_F_COPPER }, |
1069 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_C, | | 1057 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_C, |
1070 | "82801I (C) LAN Controller", | | 1058 | "82801I (C) LAN Controller", |
1071 | WM_T_ICH9, WMP_F_COPPER }, | | 1059 | WM_T_ICH9, WMP_F_COPPER }, |
1072 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_M, | | 1060 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_M, |
1073 | "82801I mobile LAN Controller", | | 1061 | "82801I mobile LAN Controller", |
1074 | WM_T_ICH9, WMP_F_COPPER }, | | 1062 | WM_T_ICH9, WMP_F_COPPER }, |
1075 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IGP_M_V, | | 1063 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IGP_M_V, |
1076 | "82801I mobile (V) LAN Controller", | | 1064 | "82801I mobile (V) LAN Controller", |
1077 | WM_T_ICH9, WMP_F_COPPER }, | | 1065 | WM_T_ICH9, WMP_F_COPPER }, |
1078 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_M_AMT, | | 1066 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_M_AMT, |
1079 | "82801I mobile (AMT) LAN Controller", | | 1067 | "82801I mobile (AMT) LAN Controller", |
1080 | WM_T_ICH9, WMP_F_COPPER }, | | 1068 | WM_T_ICH9, WMP_F_COPPER }, |
1081 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_BM, | | 1069 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_BM, |
1082 | "82567LM-4 LAN Controller", | | 1070 | "82567LM-4 LAN Controller", |
1083 | WM_T_ICH9, WMP_F_COPPER }, | | 1071 | WM_T_ICH9, WMP_F_COPPER }, |
1084 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_82567V_3, | | 1072 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_82567V_3, |
1085 | "82567V-3 LAN Controller", | | 1073 | "82567V-3 LAN Controller", |
1086 | WM_T_ICH9, WMP_F_COPPER }, | | 1074 | WM_T_ICH9, WMP_F_COPPER }, |
1087 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_R_BM_LM, | | 1075 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_R_BM_LM, |
1088 | "82567LM-2 LAN Controller", | | 1076 | "82567LM-2 LAN Controller", |
1089 | WM_T_ICH10, WMP_F_COPPER }, | | 1077 | WM_T_ICH10, WMP_F_COPPER }, |
1090 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_R_BM_LF, | | 1078 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_R_BM_LF, |
1091 | "82567LF-2 LAN Controller", | | 1079 | "82567LF-2 LAN Controller", |
1092 | WM_T_ICH10, WMP_F_COPPER }, | | 1080 | WM_T_ICH10, WMP_F_COPPER }, |
1093 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_D_BM_LM, | | 1081 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_D_BM_LM, |
1094 | "82567LM-3 LAN Controller", | | 1082 | "82567LM-3 LAN Controller", |
1095 | WM_T_ICH10, WMP_F_COPPER }, | | 1083 | WM_T_ICH10, WMP_F_COPPER }, |
1096 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_D_BM_LF, | | 1084 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_D_BM_LF, |
1097 | "82567LF-3 LAN Controller", | | 1085 | "82567LF-3 LAN Controller", |
1098 | WM_T_ICH10, WMP_F_COPPER }, | | 1086 | WM_T_ICH10, WMP_F_COPPER }, |
1099 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_R_BM_V, | | 1087 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_R_BM_V, |
1100 | "82567V-2 LAN Controller", | | 1088 | "82567V-2 LAN Controller", |
1101 | WM_T_ICH10, WMP_F_COPPER }, | | 1089 | WM_T_ICH10, WMP_F_COPPER }, |
1102 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_D_BM_V, | | 1090 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_D_BM_V, |
1103 | "82567V-3? LAN Controller", | | 1091 | "82567V-3? LAN Controller", |
1104 | WM_T_ICH10, WMP_F_COPPER }, | | 1092 | WM_T_ICH10, WMP_F_COPPER }, |
1105 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HANKSVILLE, | | 1093 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HANKSVILLE, |
1106 | "HANKSVILLE LAN Controller", | | 1094 | "HANKSVILLE LAN Controller", |
1107 | WM_T_ICH10, WMP_F_COPPER }, | | 1095 | WM_T_ICH10, WMP_F_COPPER }, |
1108 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_M_LM, | | 1096 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_M_LM, |
1109 | "PCH LAN (82577LM) Controller", | | 1097 | "PCH LAN (82577LM) Controller", |
1110 | WM_T_PCH, WMP_F_COPPER }, | | 1098 | WM_T_PCH, WMP_F_COPPER }, |
1111 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_M_LC, | | 1099 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_M_LC, |
1112 | "PCH LAN (82577LC) Controller", | | 1100 | "PCH LAN (82577LC) Controller", |
1113 | WM_T_PCH, WMP_F_COPPER }, | | 1101 | WM_T_PCH, WMP_F_COPPER }, |
1114 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_D_DM, | | 1102 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_D_DM, |
1115 | "PCH LAN (82578DM) Controller", | | 1103 | "PCH LAN (82578DM) Controller", |
1116 | WM_T_PCH, WMP_F_COPPER }, | | 1104 | WM_T_PCH, WMP_F_COPPER }, |
1117 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_D_DC, | | 1105 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_D_DC, |
1118 | "PCH LAN (82578DC) Controller", | | 1106 | "PCH LAN (82578DC) Controller", |
1119 | WM_T_PCH, WMP_F_COPPER }, | | 1107 | WM_T_PCH, WMP_F_COPPER }, |
1120 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH2_LV_LM, | | 1108 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH2_LV_LM, |
1121 | "PCH2 LAN (82579LM) Controller", | | 1109 | "PCH2 LAN (82579LM) Controller", |
1122 | WM_T_PCH2, WMP_F_COPPER }, | | 1110 | WM_T_PCH2, WMP_F_COPPER }, |
1123 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH2_LV_V, | | 1111 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH2_LV_V, |
1124 | "PCH2 LAN (82579V) Controller", | | 1112 | "PCH2 LAN (82579V) Controller", |
1125 | WM_T_PCH2, WMP_F_COPPER }, | | 1113 | WM_T_PCH2, WMP_F_COPPER }, |
1126 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_COPPER, | | 1114 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_COPPER, |
1127 | "82575EB dual-1000baseT Ethernet", | | 1115 | "82575EB dual-1000baseT Ethernet", |
1128 | WM_T_82575, WMP_F_COPPER }, | | 1116 | WM_T_82575, WMP_F_COPPER }, |
1129 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_FIBER_SERDES, | | 1117 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_FIBER_SERDES, |
1130 | "82575EB dual-1000baseX Ethernet (SERDES)", | | 1118 | "82575EB dual-1000baseX Ethernet (SERDES)", |
1131 | WM_T_82575, WMP_F_SERDES }, | | 1119 | WM_T_82575, WMP_F_SERDES }, |
1132 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QUAD_COPPER, | | 1120 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QUAD_COPPER, |
1133 | "82575GB quad-1000baseT Ethernet", | | 1121 | "82575GB quad-1000baseT Ethernet", |
1134 | WM_T_82575, WMP_F_COPPER }, | | 1122 | WM_T_82575, WMP_F_COPPER }, |
1135 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QUAD_COPPER_PM, | | 1123 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QUAD_COPPER_PM, |
1136 | "82575GB quad-1000baseT Ethernet (PM)", | | 1124 | "82575GB quad-1000baseT Ethernet (PM)", |
1137 | WM_T_82575, WMP_F_COPPER }, | | 1125 | WM_T_82575, WMP_F_COPPER }, |
1138 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_COPPER, | | 1126 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_COPPER, |
1139 | "82576 1000BaseT Ethernet", | | 1127 | "82576 1000BaseT Ethernet", |
1140 | WM_T_82576, WMP_F_COPPER }, | | 1128 | WM_T_82576, WMP_F_COPPER }, |
1141 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_FIBER, | | 1129 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_FIBER, |
1142 | "82576 1000BaseX Ethernet", | | 1130 | "82576 1000BaseX Ethernet", |
1143 | WM_T_82576, WMP_F_FIBER }, | | 1131 | WM_T_82576, WMP_F_FIBER }, |
1144 | | | 1132 | |
1145 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES, | | 1133 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES, |
1146 | "82576 gigabit Ethernet (SERDES)", | | 1134 | "82576 gigabit Ethernet (SERDES)", |
1147 | WM_T_82576, WMP_F_SERDES }, | | 1135 | WM_T_82576, WMP_F_SERDES }, |
1148 | | | 1136 | |
1149 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_COPPER, | | 1137 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_COPPER, |
1150 | "82576 quad-1000BaseT Ethernet", | | 1138 | "82576 quad-1000BaseT Ethernet", |
1151 | WM_T_82576, WMP_F_COPPER }, | | 1139 | WM_T_82576, WMP_F_COPPER }, |
1152 | | | 1140 | |
1153 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_COPPER_ET2, | | 1141 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_COPPER_ET2, |
1154 | "82576 Gigabit ET2 Quad Port Server Adapter", | | 1142 | "82576 Gigabit ET2 Quad Port Server Adapter", |
1155 | WM_T_82576, WMP_F_COPPER }, | | 1143 | WM_T_82576, WMP_F_COPPER }, |
1156 | | | 1144 | |
1157 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS, | | 1145 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS, |
1158 | "82576 gigabit Ethernet", | | 1146 | "82576 gigabit Ethernet", |
1159 | WM_T_82576, WMP_F_COPPER }, | | 1147 | WM_T_82576, WMP_F_COPPER }, |
1160 | | | 1148 | |
1161 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS_SERDES, | | 1149 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS_SERDES, |
1162 | "82576 gigabit Ethernet (SERDES)", | | 1150 | "82576 gigabit Ethernet (SERDES)", |
1163 | WM_T_82576, WMP_F_SERDES }, | | 1151 | WM_T_82576, WMP_F_SERDES }, |
1164 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES_QUAD, | | 1152 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES_QUAD, |
1165 | "82576 quad-gigabit Ethernet (SERDES)", | | 1153 | "82576 quad-gigabit Ethernet (SERDES)", |
1166 | WM_T_82576, WMP_F_SERDES }, | | 1154 | WM_T_82576, WMP_F_SERDES }, |
1167 | | | 1155 | |
1168 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER, | | 1156 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER, |
1169 | "82580 1000BaseT Ethernet", | | 1157 | "82580 1000BaseT Ethernet", |
1170 | WM_T_82580, WMP_F_COPPER }, | | 1158 | WM_T_82580, WMP_F_COPPER }, |
1171 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_FIBER, | | 1159 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_FIBER, |
1172 | "82580 1000BaseX Ethernet", | | 1160 | "82580 1000BaseX Ethernet", |
1173 | WM_T_82580, WMP_F_FIBER }, | | 1161 | WM_T_82580, WMP_F_FIBER }, |
1174 | | | 1162 | |
1175 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SERDES, | | 1163 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SERDES, |
1176 | "82580 1000BaseT Ethernet (SERDES)", | | 1164 | "82580 1000BaseT Ethernet (SERDES)", |
1177 | WM_T_82580, WMP_F_SERDES }, | | 1165 | WM_T_82580, WMP_F_SERDES }, |
1178 | | | 1166 | |
1179 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SGMII, | | 1167 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SGMII, |
1180 | "82580 gigabit Ethernet (SGMII)", | | 1168 | "82580 gigabit Ethernet (SGMII)", |
1181 | WM_T_82580, WMP_F_COPPER }, | | 1169 | WM_T_82580, WMP_F_COPPER }, |
1182 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER_DUAL, | | 1170 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER_DUAL, |
1183 | "82580 dual-1000BaseT Ethernet", | | 1171 | "82580 dual-1000BaseT Ethernet", |
1184 | WM_T_82580, WMP_F_COPPER }, | | 1172 | WM_T_82580, WMP_F_COPPER }, |
1185 | | | 1173 | |
1186 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_QUAD_FIBER, | | 1174 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_QUAD_FIBER, |
1187 | "82580 quad-1000BaseX Ethernet", | | 1175 | "82580 quad-1000BaseX Ethernet", |
1188 | WM_T_82580, WMP_F_FIBER }, | | 1176 | WM_T_82580, WMP_F_FIBER }, |
1189 | | | 1177 | |
1190 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SGMII, | | 1178 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SGMII, |
1191 | "DH89XXCC Gigabit Ethernet (SGMII)", | | 1179 | "DH89XXCC Gigabit Ethernet (SGMII)", |
1192 | WM_T_82580, WMP_F_COPPER }, | | 1180 | WM_T_82580, WMP_F_COPPER }, |
1193 | | | 1181 | |
1194 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SERDES, | | 1182 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SERDES, |
1195 | "DH89XXCC Gigabit Ethernet (SERDES)", | | 1183 | "DH89XXCC Gigabit Ethernet (SERDES)", |
1196 | WM_T_82580, WMP_F_SERDES }, | | 1184 | WM_T_82580, WMP_F_SERDES }, |
1197 | | | 1185 | |
1198 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_BPLANE, | | 1186 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_BPLANE, |
1199 | "DH89XXCC 1000BASE-KX Ethernet", | | 1187 | "DH89XXCC 1000BASE-KX Ethernet", |
1200 | WM_T_82580, WMP_F_SERDES }, | | 1188 | WM_T_82580, WMP_F_SERDES }, |
1201 | | | 1189 | |
1202 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SFP, | | 1190 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SFP, |
1203 | "DH89XXCC Gigabit Ethernet (SFP)", | | 1191 | "DH89XXCC Gigabit Ethernet (SFP)", |
1204 | WM_T_82580, WMP_F_SERDES }, | | 1192 | WM_T_82580, WMP_F_SERDES }, |
1205 | | | 1193 | |
1206 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_COPPER, | | 1194 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_COPPER, |
1207 | "I350 Gigabit Network Connection", | | 1195 | "I350 Gigabit Network Connection", |
1208 | WM_T_I350, WMP_F_COPPER }, | | 1196 | WM_T_I350, WMP_F_COPPER }, |
1209 | | | 1197 | |
1210 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_FIBER, | | 1198 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_FIBER, |
1211 | "I350 Gigabit Fiber Network Connection", | | 1199 | "I350 Gigabit Fiber Network Connection", |
1212 | WM_T_I350, WMP_F_FIBER }, | | 1200 | WM_T_I350, WMP_F_FIBER }, |
1213 | | | 1201 | |
1214 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_SERDES, | | 1202 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_SERDES, |
1215 | "I350 Gigabit Backplane Connection", | | 1203 | "I350 Gigabit Backplane Connection", |
1216 | WM_T_I350, WMP_F_SERDES }, | | 1204 | WM_T_I350, WMP_F_SERDES }, |
1217 | | | 1205 | |
1218 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_DA4, | | 1206 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_DA4, |
1219 | "I350 Quad Port Gigabit Ethernet", | | 1207 | "I350 Quad Port Gigabit Ethernet", |
1220 | WM_T_I350, WMP_F_SERDES }, | | 1208 | WM_T_I350, WMP_F_SERDES }, |
1221 | | | 1209 | |
1222 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_SGMII, | | 1210 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_SGMII, |
1223 | "I350 Gigabit Connection", | | 1211 | "I350 Gigabit Connection", |
1224 | WM_T_I350, WMP_F_COPPER }, | | 1212 | WM_T_I350, WMP_F_COPPER }, |
1225 | | | 1213 | |
1226 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_1000KX, | | 1214 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_1000KX, |
1227 | "I354 Gigabit Ethernet (KX)", | | 1215 | "I354 Gigabit Ethernet (KX)", |
1228 | WM_T_I354, WMP_F_SERDES }, | | 1216 | WM_T_I354, WMP_F_SERDES }, |
1229 | | | 1217 | |
1230 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_SGMII, | | 1218 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_SGMII, |
1231 | "I354 Gigabit Ethernet (SGMII)", | | 1219 | "I354 Gigabit Ethernet (SGMII)", |
1232 | WM_T_I354, WMP_F_COPPER }, | | 1220 | WM_T_I354, WMP_F_COPPER }, |
1233 | | | 1221 | |
1234 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_25GBE, | | 1222 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_25GBE, |
1235 | "I354 Gigabit Ethernet (2.5G)", | | 1223 | "I354 Gigabit Ethernet (2.5G)", |
1236 | WM_T_I354, WMP_F_COPPER }, | | 1224 | WM_T_I354, WMP_F_COPPER }, |
1237 | | | 1225 | |
1238 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_T1, | | 1226 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_T1, |
1239 | "I210-T1 Ethernet Server Adapter", | | 1227 | "I210-T1 Ethernet Server Adapter", |
1240 | WM_T_I210, WMP_F_COPPER }, | | 1228 | WM_T_I210, WMP_F_COPPER }, |
1241 | | | 1229 | |
1242 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_OEM1, | | 1230 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_OEM1, |
1243 | "I210 Ethernet (Copper OEM)", | | 1231 | "I210 Ethernet (Copper OEM)", |
1244 | WM_T_I210, WMP_F_COPPER }, | | 1232 | WM_T_I210, WMP_F_COPPER }, |
1245 | | | 1233 | |
1246 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_IT, | | 1234 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_IT, |
1247 | "I210 Ethernet (Copper IT)", | | 1235 | "I210 Ethernet (Copper IT)", |
1248 | WM_T_I210, WMP_F_COPPER }, | | 1236 | WM_T_I210, WMP_F_COPPER }, |
1249 | | | 1237 | |
1250 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_WOF, | | 1238 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_WOF, |
1251 | "I210 Ethernet (FLASH less)", | | 1239 | "I210 Ethernet (FLASH less)", |
1252 | WM_T_I210, WMP_F_COPPER }, | | 1240 | WM_T_I210, WMP_F_COPPER }, |
1253 | | | 1241 | |
1254 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_FIBER, | | 1242 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_FIBER, |
1255 | "I210 Gigabit Ethernet (Fiber)", | | 1243 | "I210 Gigabit Ethernet (Fiber)", |
1256 | WM_T_I210, WMP_F_FIBER }, | | 1244 | WM_T_I210, WMP_F_FIBER }, |
1257 | | | 1245 | |
1258 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SERDES, | | 1246 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SERDES, |
1259 | "I210 Gigabit Ethernet (SERDES)", | | 1247 | "I210 Gigabit Ethernet (SERDES)", |
1260 | WM_T_I210, WMP_F_SERDES }, | | 1248 | WM_T_I210, WMP_F_SERDES }, |
1261 | | | 1249 | |
1262 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SERDES_WOF, | | 1250 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SERDES_WOF, |
1263 | "I210 Gigabit Ethernet (FLASH less)", | | 1251 | "I210 Gigabit Ethernet (FLASH less)", |
1264 | WM_T_I210, WMP_F_SERDES }, | | 1252 | WM_T_I210, WMP_F_SERDES }, |
1265 | | | 1253 | |
1266 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SGMII, | | 1254 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SGMII, |
1267 | "I210 Gigabit Ethernet (SGMII)", | | 1255 | "I210 Gigabit Ethernet (SGMII)", |
1268 | WM_T_I210, WMP_F_COPPER }, | | 1256 | WM_T_I210, WMP_F_COPPER }, |
1269 | | | 1257 | |
1270 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I211_COPPER, | | 1258 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I211_COPPER, |
1271 | "I211 Ethernet (COPPER)", | | 1259 | "I211 Ethernet (COPPER)", |
1272 | WM_T_I211, WMP_F_COPPER }, | | 1260 | WM_T_I211, WMP_F_COPPER }, |
1273 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_V, | | 1261 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_V, |
1274 | "I217 V Ethernet Connection", | | 1262 | "I217 V Ethernet Connection", |
1275 | WM_T_PCH_LPT, WMP_F_COPPER }, | | 1263 | WM_T_PCH_LPT, WMP_F_COPPER }, |
1276 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_LM, | | 1264 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_LM, |
1277 | "I217 LM Ethernet Connection", | | 1265 | "I217 LM Ethernet Connection", |
1278 | WM_T_PCH_LPT, WMP_F_COPPER }, | | 1266 | WM_T_PCH_LPT, WMP_F_COPPER }, |
1279 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V, | | 1267 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V, |
1280 | "I218 V Ethernet Connection", | | 1268 | "I218 V Ethernet Connection", |
1281 | WM_T_PCH_LPT, WMP_F_COPPER }, | | 1269 | WM_T_PCH_LPT, WMP_F_COPPER }, |
1282 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V2, | | 1270 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V2, |
1283 | "I218 V Ethernet Connection", | | 1271 | "I218 V Ethernet Connection", |
1284 | WM_T_PCH_LPT, WMP_F_COPPER }, | | 1272 | WM_T_PCH_LPT, WMP_F_COPPER }, |
1285 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V3, | | 1273 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V3, |
1286 | "I218 V Ethernet Connection", | | 1274 | "I218 V Ethernet Connection", |
1287 | WM_T_PCH_LPT, WMP_F_COPPER }, | | 1275 | WM_T_PCH_LPT, WMP_F_COPPER }, |
1288 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM, | | 1276 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM, |
1289 | "I218 LM Ethernet Connection", | | 1277 | "I218 LM Ethernet Connection", |
1290 | WM_T_PCH_LPT, WMP_F_COPPER }, | | 1278 | WM_T_PCH_LPT, WMP_F_COPPER }, |
1291 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM2, | | 1279 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM2, |
1292 | "I218 LM Ethernet Connection", | | 1280 | "I218 LM Ethernet Connection", |
1293 | WM_T_PCH_LPT, WMP_F_COPPER }, | | 1281 | WM_T_PCH_LPT, WMP_F_COPPER }, |
1294 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM3, | | 1282 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM3, |
1295 | "I218 LM Ethernet Connection", | | 1283 | "I218 LM Ethernet Connection", |
1296 | WM_T_PCH_LPT, WMP_F_COPPER }, | | 1284 | WM_T_PCH_LPT, WMP_F_COPPER }, |
1297 | { 0, 0, | | 1285 | { 0, 0, |
1298 | NULL, | | 1286 | NULL, |
1299 | 0, 0 }, | | 1287 | 0, 0 }, |
1300 | }; | | 1288 | }; |
1301 | | | 1289 | |
1302 | #ifdef WM_EVENT_COUNTERS | | 1290 | #ifdef WM_EVENT_COUNTERS |
1303 | static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")]; | | 1291 | static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")]; |
1304 | #endif /* WM_EVENT_COUNTERS */ | | 1292 | #endif /* WM_EVENT_COUNTERS */ |
1305 | | | 1293 | |
1306 | | | 1294 | |
1307 | /* | | 1295 | /* |
1308 | * Register read/write functions. | | 1296 | * Register read/write functions. |
1309 | * Other than CSR_{READ|WRITE}(). | | 1297 | * Other than CSR_{READ|WRITE}(). |
1310 | */ | | 1298 | */ |
1311 | | | 1299 | |
1312 | #if 0 /* Not currently used */ | | 1300 | #if 0 /* Not currently used */ |
1313 | static inline uint32_t | | 1301 | static inline uint32_t |
1314 | wm_io_read(struct wm_softc *sc, int reg) | | 1302 | wm_io_read(struct wm_softc *sc, int reg) |
1315 | { | | 1303 | { |
1316 | | | 1304 | |
1317 | bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); | | 1305 | bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); |
1318 | return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4)); | | 1306 | return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4)); |
1319 | } | | 1307 | } |
1320 | #endif | | 1308 | #endif |
1321 | | | 1309 | |
1322 | static inline void | | 1310 | static inline void |
1323 | wm_io_write(struct wm_softc *sc, int reg, uint32_t val) | | 1311 | wm_io_write(struct wm_softc *sc, int reg, uint32_t val) |
1324 | { | | 1312 | { |
1325 | | | 1313 | |
1326 | bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); | | 1314 | bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); |
1327 | bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val); | | 1315 | bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val); |
1328 | } | | 1316 | } |
1329 | | | 1317 | |
1330 | static inline void | | 1318 | static inline void |
1331 | wm_82575_write_8bit_ctlr_reg(struct wm_softc *sc, uint32_t reg, uint32_t off, | | 1319 | wm_82575_write_8bit_ctlr_reg(struct wm_softc *sc, uint32_t reg, uint32_t off, |
1332 | uint32_t data) | | 1320 | uint32_t data) |
1333 | { | | 1321 | { |
1334 | uint32_t regval; | | 1322 | uint32_t regval; |
1335 | int i; | | 1323 | int i; |
1336 | | | 1324 | |
1337 | regval = (data & SCTL_CTL_DATA_MASK) | (off << SCTL_CTL_ADDR_SHIFT); | | 1325 | regval = (data & SCTL_CTL_DATA_MASK) | (off << SCTL_CTL_ADDR_SHIFT); |
1338 | | | 1326 | |
1339 | CSR_WRITE(sc, reg, regval); | | 1327 | CSR_WRITE(sc, reg, regval); |
1340 | | | 1328 | |
1341 | for (i = 0; i < SCTL_CTL_POLL_TIMEOUT; i++) { | | 1329 | for (i = 0; i < SCTL_CTL_POLL_TIMEOUT; i++) { |
1342 | delay(5); | | 1330 | delay(5); |
1343 | if (CSR_READ(sc, reg) & SCTL_CTL_READY) | | 1331 | if (CSR_READ(sc, reg) & SCTL_CTL_READY) |
1344 | break; | | 1332 | break; |
1345 | } | | 1333 | } |
1346 | if (i == SCTL_CTL_POLL_TIMEOUT) { | | 1334 | if (i == SCTL_CTL_POLL_TIMEOUT) { |
1347 | aprint_error("%s: WARNING:" | | 1335 | aprint_error("%s: WARNING:" |
1348 | " i82575 reg 0x%08x setup did not indicate ready\n", | | 1336 | " i82575 reg 0x%08x setup did not indicate ready\n", |
1349 | device_xname(sc->sc_dev), reg); | | 1337 | device_xname(sc->sc_dev), reg); |
1350 | } | | 1338 | } |
1351 | } | | 1339 | } |
1352 | | | 1340 | |
1353 | static inline void | | 1341 | static inline void |
1354 | wm_set_dma_addr(volatile wiseman_addr_t *wa, bus_addr_t v) | | 1342 | wm_set_dma_addr(volatile wiseman_addr_t *wa, bus_addr_t v) |
1355 | { | | 1343 | { |
1356 | wa->wa_low = htole32(v & 0xffffffffU); | | 1344 | wa->wa_low = htole32(v & 0xffffffffU); |
1357 | if (sizeof(bus_addr_t) == 8) | | 1345 | if (sizeof(bus_addr_t) == 8) |
1358 | wa->wa_high = htole32((uint64_t) v >> 32); | | 1346 | wa->wa_high = htole32((uint64_t) v >> 32); |
1359 | else | | 1347 | else |
1360 | wa->wa_high = 0; | | 1348 | wa->wa_high = 0; |
1361 | } | | 1349 | } |
1362 | | | 1350 | |
1363 | /* | | 1351 | /* |
1364 | * Descriptor sync/init functions. | | 1352 | * Descriptor sync/init functions. |
1365 | */ | | 1353 | */ |
1366 | static inline void | | 1354 | static inline void |
1367 | wm_cdtxsync(struct wm_softc *sc, int start, int num, int ops) | | 1355 | wm_cdtxsync(struct wm_softc *sc, int start, int num, int ops) |
1368 | { | | 1356 | { |
1369 | struct wm_txqueue *txq = sc->sc_txq; | | 1357 | struct wm_txqueue *txq = sc->sc_txq; |
1370 | | | 1358 | |
1371 | /* If it will wrap around, sync to the end of the ring. */ | | 1359 | /* If it will wrap around, sync to the end of the ring. */ |
1372 | if ((start + num) > WM_NTXDESC(txq)) { | | 1360 | if ((start + num) > WM_NTXDESC(txq)) { |
1373 | bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_dmamap, | | 1361 | bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_dmamap, |
1374 | WM_CDTXOFF(start), sizeof(wiseman_txdesc_t) * | | 1362 | WM_CDTXOFF(start), sizeof(wiseman_txdesc_t) * |
1375 | (WM_NTXDESC(txq) - start), ops); | | 1363 | (WM_NTXDESC(txq) - start), ops); |
1376 | num -= (WM_NTXDESC(txq) - start); | | 1364 | num -= (WM_NTXDESC(txq) - start); |
1377 | start = 0; | | 1365 | start = 0; |
1378 | } | | 1366 | } |
1379 | | | 1367 | |
1380 | /* Now sync whatever is left. */ | | 1368 | /* Now sync whatever is left. */ |
1381 | bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_dmamap, | | 1369 | bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_dmamap, |
1382 | WM_CDTXOFF(start), sizeof(wiseman_txdesc_t) * num, ops); | | 1370 | WM_CDTXOFF(start), sizeof(wiseman_txdesc_t) * num, ops); |
1383 | } | | 1371 | } |
1384 | | | 1372 | |
1385 | static inline void | | 1373 | static inline void |
1386 | wm_cdrxsync(struct wm_softc *sc, int start, int ops) | | 1374 | wm_cdrxsync(struct wm_softc *sc, int start, int ops) |
1387 | { | | 1375 | { |
1388 | struct wm_rxqueue *rxq = sc->sc_rxq; | | 1376 | struct wm_rxqueue *rxq = sc->sc_rxq; |
1389 | | | 1377 | |
1390 | bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_dmamap, | | 1378 | bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_dmamap, |
1391 | WM_CDRXOFF(start), sizeof(wiseman_rxdesc_t), ops); | | 1379 | WM_CDRXOFF(start), sizeof(wiseman_rxdesc_t), ops); |
1392 | } | | 1380 | } |
1393 | | | 1381 | |
1394 | static inline void | | 1382 | static inline void |
1395 | wm_init_rxdesc(struct wm_softc *sc, int start) | | 1383 | wm_init_rxdesc(struct wm_softc *sc, int start) |
1396 | { | | 1384 | { |
1397 | struct wm_rxqueue *rxq = sc->sc_rxq; | | 1385 | struct wm_rxqueue *rxq = sc->sc_rxq; |
1398 | struct wm_rxsoft *rxs = &rxq->rxq_soft[start]; | | 1386 | struct wm_rxsoft *rxs = &rxq->rxq_soft[start]; |
1399 | wiseman_rxdesc_t *rxd = &rxq->rxq_descs[start]; | | 1387 | wiseman_rxdesc_t *rxd = &rxq->rxq_descs[start]; |
1400 | struct mbuf *m = rxs->rxs_mbuf; | | 1388 | struct mbuf *m = rxs->rxs_mbuf; |
1401 | | | 1389 | |
1402 | /* | | 1390 | /* |
1403 | * Note: We scoot the packet forward 2 bytes in the buffer | | 1391 | * Note: We scoot the packet forward 2 bytes in the buffer |
1404 | * so that the payload after the Ethernet header is aligned | | 1392 | * so that the payload after the Ethernet header is aligned |
1405 | * to a 4-byte boundary. | | 1393 | * to a 4-byte boundary. |
1406 | | | 1394 | |
1407 | * XXX BRAINDAMAGE ALERT! | | 1395 | * XXX BRAINDAMAGE ALERT! |
1408 | * The stupid chip uses the same size for every buffer, which | | 1396 | * The stupid chip uses the same size for every buffer, which |
1409 | * is set in the Receive Control register. We are using the 2K | | 1397 | * is set in the Receive Control register. We are using the 2K |
1410 | * size option, but what we REALLY want is (2K - 2)! For this | | 1398 | * size option, but what we REALLY want is (2K - 2)! For this |
1411 | * reason, we can't "scoot" packets longer than the standard | | 1399 | * reason, we can't "scoot" packets longer than the standard |
1412 | * Ethernet MTU. On strict-alignment platforms, if the total | | 1400 | * Ethernet MTU. On strict-alignment platforms, if the total |
1413 | * size exceeds (2K - 2) we set align_tweak to 0 and let | | 1401 | * size exceeds (2K - 2) we set align_tweak to 0 and let |
1414 | * the upper layer copy the headers. | | 1402 | * the upper layer copy the headers. |
1415 | */ | | 1403 | */ |
1416 | m->m_data = m->m_ext.ext_buf + sc->sc_align_tweak; | | 1404 | m->m_data = m->m_ext.ext_buf + sc->sc_align_tweak; |
1417 | | | 1405 | |
1418 | wm_set_dma_addr(&rxd->wrx_addr, | | 1406 | wm_set_dma_addr(&rxd->wrx_addr, |
1419 | rxs->rxs_dmamap->dm_segs[0].ds_addr + sc->sc_align_tweak); | | 1407 | rxs->rxs_dmamap->dm_segs[0].ds_addr + sc->sc_align_tweak); |
1420 | rxd->wrx_len = 0; | | 1408 | rxd->wrx_len = 0; |
1421 | rxd->wrx_cksum = 0; | | 1409 | rxd->wrx_cksum = 0; |
1422 | rxd->wrx_status = 0; | | 1410 | rxd->wrx_status = 0; |
1423 | rxd->wrx_errors = 0; | | 1411 | rxd->wrx_errors = 0; |
1424 | rxd->wrx_special = 0; | | 1412 | rxd->wrx_special = 0; |
1425 | wm_cdrxsync(sc, start, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); | | 1413 | wm_cdrxsync(sc, start, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); |
1426 | | | 1414 | |
1427 | CSR_WRITE(sc, rxq->rxq_rdt_reg, start); | | 1415 | CSR_WRITE(sc, rxq->rxq_rdt_reg, start); |
1428 | } | | 1416 | } |
1429 | | | 1417 | |
1430 | /* | | 1418 | /* |
1431 | * Device driver interface functions and commonly used functions. | | 1419 | * Device driver interface functions and commonly used functions. |
1432 | * match, attach, detach, init, start, stop, ioctl, watchdog and so on. | | 1420 | * match, attach, detach, init, start, stop, ioctl, watchdog and so on. |
1433 | */ | | 1421 | */ |
1434 | | | 1422 | |
1435 | /* Lookup supported device table */ | | 1423 | /* Lookup supported device table */ |
1436 | static const struct wm_product * | | 1424 | static const struct wm_product * |
1437 | wm_lookup(const struct pci_attach_args *pa) | | 1425 | wm_lookup(const struct pci_attach_args *pa) |
1438 | { | | 1426 | { |
1439 | const struct wm_product *wmp; | | 1427 | const struct wm_product *wmp; |
1440 | | | 1428 | |
1441 | for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) { | | 1429 | for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) { |
1442 | if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor && | | 1430 | if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor && |
1443 | PCI_PRODUCT(pa->pa_id) == wmp->wmp_product) | | 1431 | PCI_PRODUCT(pa->pa_id) == wmp->wmp_product) |
1444 | return wmp; | | 1432 | return wmp; |
1445 | } | | 1433 | } |
1446 | return NULL; | | 1434 | return NULL; |
1447 | } | | 1435 | } |
1448 | | | 1436 | |
1449 | /* The match function (ca_match) */ | | 1437 | /* The match function (ca_match) */ |
1450 | static int | | 1438 | static int |
1451 | wm_match(device_t parent, cfdata_t cf, void *aux) | | 1439 | wm_match(device_t parent, cfdata_t cf, void *aux) |
1452 | { | | 1440 | { |
1453 | struct pci_attach_args *pa = aux; | | 1441 | struct pci_attach_args *pa = aux; |
1454 | | | 1442 | |
1455 | if (wm_lookup(pa) != NULL) | | 1443 | if (wm_lookup(pa) != NULL) |
1456 | return 1; | | 1444 | return 1; |
1457 | | | 1445 | |
1458 | return 0; | | 1446 | return 0; |
1459 | } | | 1447 | } |
1460 | | | 1448 | |
1461 | /* The attach function (ca_attach) */ | | 1449 | /* The attach function (ca_attach) */ |
1462 | static void | | 1450 | static void |
1463 | wm_attach(device_t parent, device_t self, void *aux) | | 1451 | wm_attach(device_t parent, device_t self, void *aux) |
1464 | { | | 1452 | { |
1465 | struct wm_softc *sc = device_private(self); | | 1453 | struct wm_softc *sc = device_private(self); |
1466 | struct pci_attach_args *pa = aux; | | 1454 | struct pci_attach_args *pa = aux; |
1467 | prop_dictionary_t dict; | | 1455 | prop_dictionary_t dict; |
1468 | struct ifnet *ifp = &sc->sc_ethercom.ec_if; | | 1456 | struct ifnet *ifp = &sc->sc_ethercom.ec_if; |
1469 | pci_chipset_tag_t pc = pa->pa_pc; | | 1457 | pci_chipset_tag_t pc = pa->pa_pc; |
1470 | #ifndef WM_MSI_MSIX | | 1458 | #ifndef WM_MSI_MSIX |
1471 | pci_intr_handle_t ih; | | 1459 | pci_intr_handle_t ih; |
| | | 1460 | const char *intrstr = NULL; |
| | | 1461 | char intrbuf[PCI_INTRSTR_LEN]; |
1472 | #else | | 1462 | #else |
1473 | int counts[PCI_INTR_TYPE_SIZE]; | | 1463 | int counts[PCI_INTR_TYPE_SIZE]; |
1474 | pci_intr_type_t max_type; | | 1464 | pci_intr_type_t max_type; |
1475 | #endif | | 1465 | #endif |
1476 | const char *intrstr = NULL; | | | |
1477 | const char *eetype, *xname; | | 1466 | const char *eetype, *xname; |
1478 | bus_space_tag_t memt; | | 1467 | bus_space_tag_t memt; |
1479 | bus_space_handle_t memh; | | 1468 | bus_space_handle_t memh; |
1480 | bus_size_t memsize; | | 1469 | bus_size_t memsize; |
1481 | int memh_valid; | | 1470 | int memh_valid; |
1482 | int i, error; | | 1471 | int i, error; |
1483 | const struct wm_product *wmp; | | 1472 | const struct wm_product *wmp; |
1484 | prop_data_t ea; | | 1473 | prop_data_t ea; |
1485 | prop_number_t pn; | | 1474 | prop_number_t pn; |
1486 | uint8_t enaddr[ETHER_ADDR_LEN]; | | 1475 | uint8_t enaddr[ETHER_ADDR_LEN]; |
1487 | uint16_t cfg1, cfg2, swdpin, nvmword; | | 1476 | uint16_t cfg1, cfg2, swdpin, nvmword; |
1488 | pcireg_t preg, memtype; | | 1477 | pcireg_t preg, memtype; |
1489 | uint16_t eeprom_data, apme_mask; | | 1478 | uint16_t eeprom_data, apme_mask; |
1490 | bool force_clear_smbi; | | 1479 | bool force_clear_smbi; |
1491 | uint32_t link_mode; | | 1480 | uint32_t link_mode; |
1492 | uint32_t reg; | | 1481 | uint32_t reg; |
1493 | char intrbuf[PCI_INTRSTR_LEN]; | | | |
1494 | | | 1482 | |
1495 | sc->sc_dev = self; | | 1483 | sc->sc_dev = self; |
1496 | callout_init(&sc->sc_tick_ch, CALLOUT_FLAGS); | | 1484 | callout_init(&sc->sc_tick_ch, CALLOUT_FLAGS); |
1497 | sc->sc_stopping = false; | | 1485 | sc->sc_stopping = false; |
1498 | | | 1486 | |
1499 | wmp = wm_lookup(pa); | | 1487 | wmp = wm_lookup(pa); |
1500 | #ifdef DIAGNOSTIC | | 1488 | #ifdef DIAGNOSTIC |
1501 | if (wmp == NULL) { | | 1489 | if (wmp == NULL) { |
1502 | printf("\n"); | | 1490 | printf("\n"); |
1503 | panic("wm_attach: impossible"); | | 1491 | panic("wm_attach: impossible"); |
1504 | } | | 1492 | } |
1505 | #endif | | 1493 | #endif |
1506 | sc->sc_mediatype = WMP_MEDIATYPE(wmp->wmp_flags); | | 1494 | sc->sc_mediatype = WMP_MEDIATYPE(wmp->wmp_flags); |
1507 | | | 1495 | |
1508 | sc->sc_pc = pa->pa_pc; | | 1496 | sc->sc_pc = pa->pa_pc; |
1509 | sc->sc_pcitag = pa->pa_tag; | | 1497 | sc->sc_pcitag = pa->pa_tag; |
1510 | | | 1498 | |
1511 | if (pci_dma64_available(pa)) | | 1499 | if (pci_dma64_available(pa)) |
1512 | sc->sc_dmat = pa->pa_dmat64; | | 1500 | sc->sc_dmat = pa->pa_dmat64; |
1513 | else | | 1501 | else |
1514 | sc->sc_dmat = pa->pa_dmat; | | 1502 | sc->sc_dmat = pa->pa_dmat; |
1515 | | | 1503 | |
1516 | sc->sc_pcidevid = PCI_PRODUCT(pa->pa_id); | | 1504 | sc->sc_pcidevid = PCI_PRODUCT(pa->pa_id); |
1517 | sc->sc_rev = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); | | 1505 | sc->sc_rev = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); |
1518 | pci_aprint_devinfo_fancy(pa, "Ethernet controller", wmp->wmp_name, 1); | | 1506 | pci_aprint_devinfo_fancy(pa, "Ethernet controller", wmp->wmp_name, 1); |
1519 | | | 1507 | |
1520 | sc->sc_type = wmp->wmp_type; | | 1508 | sc->sc_type = wmp->wmp_type; |
1521 | if (sc->sc_type < WM_T_82543) { | | 1509 | if (sc->sc_type < WM_T_82543) { |
1522 | if (sc->sc_rev < 2) { | | 1510 | if (sc->sc_rev < 2) { |
1523 | aprint_error_dev(sc->sc_dev, | | 1511 | aprint_error_dev(sc->sc_dev, |
1524 | "i82542 must be at least rev. 2\n"); | | 1512 | "i82542 must be at least rev. 2\n"); |
1525 | return; | | 1513 | return; |
1526 | } | | 1514 | } |
1527 | if (sc->sc_rev < 3) | | 1515 | if (sc->sc_rev < 3) |
1528 | sc->sc_type = WM_T_82542_2_0; | | 1516 | sc->sc_type = WM_T_82542_2_0; |
1529 | } | | 1517 | } |
1530 | | | 1518 | |
1531 | /* | | 1519 | /* |
1532 | * Disable MSI for Errata: | | 1520 | * Disable MSI for Errata: |
1533 | * "Message Signaled Interrupt Feature May Corrupt Write Transactions" | | 1521 | * "Message Signaled Interrupt Feature May Corrupt Write Transactions" |
1534 | * | | 1522 | * |
1535 | * 82544: Errata 25 | | 1523 | * 82544: Errata 25 |
1536 | * 82540: Errata 6 (easy to reproduce device timeout) | | 1524 | * 82540: Errata 6 (easy to reproduce device timeout) |
1537 | * 82545: Errata 4 (easy to reproduce device timeout) | | 1525 | * 82545: Errata 4 (easy to reproduce device timeout) |
1538 | * 82546: Errata 26 (easy to reproduce device timeout) | | 1526 | * 82546: Errata 26 (easy to reproduce device timeout) |
1539 | * 82541: Errata 7 (easy to reproduce device timeout) | | 1527 | * 82541: Errata 7 (easy to reproduce device timeout) |
1540 | * | | 1528 | * |
1541 | * "Byte Enables 2 and 3 are not set on MSI writes" | | 1529 | * "Byte Enables 2 and 3 are not set on MSI writes" |
1542 | * | | 1530 | * |
1543 | * 82571 & 82572: Errata 63 | | 1531 | * 82571 & 82572: Errata 63 |
1544 | */ | | 1532 | */ |
1545 | if ((sc->sc_type <= WM_T_82541_2) || (sc->sc_type == WM_T_82571) | | 1533 | if ((sc->sc_type <= WM_T_82541_2) || (sc->sc_type == WM_T_82571) |
1546 | || (sc->sc_type == WM_T_82572)) | | 1534 | || (sc->sc_type == WM_T_82572)) |
1547 | pa->pa_flags &= ~PCI_FLAGS_MSI_OKAY; | | 1535 | pa->pa_flags &= ~PCI_FLAGS_MSI_OKAY; |
1548 | | | 1536 | |
1549 | if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576) | | 1537 | if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576) |
1550 | || (sc->sc_type == WM_T_82580) | | 1538 | || (sc->sc_type == WM_T_82580) |
1551 | || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354) | | 1539 | || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354) |
1552 | || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211)) | | 1540 | || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211)) |
1553 | sc->sc_flags |= WM_F_NEWQUEUE; | | 1541 | sc->sc_flags |= WM_F_NEWQUEUE; |
1554 | | | 1542 | |
1555 | /* Set device properties (mactype) */ | | 1543 | /* Set device properties (mactype) */ |
1556 | dict = device_properties(sc->sc_dev); | | 1544 | dict = device_properties(sc->sc_dev); |
1557 | prop_dictionary_set_uint32(dict, "mactype", sc->sc_type); | | 1545 | prop_dictionary_set_uint32(dict, "mactype", sc->sc_type); |
1558 | | | 1546 | |
1559 | /* | | 1547 | /* |
1560 | * Map the device. All devices support memory-mapped acccess, | | 1548 | * Map the device. All devices support memory-mapped acccess, |
1561 | * and it is really required for normal operation. | | 1549 | * and it is really required for normal operation. |
1562 | */ | | 1550 | */ |
1563 | memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA); | | 1551 | memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA); |
1564 | switch (memtype) { | | 1552 | switch (memtype) { |
1565 | case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: | | 1553 | case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: |
1566 | case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: | | 1554 | case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: |
1567 | memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA, | | 1555 | memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA, |
1568 | memtype, 0, &memt, &memh, NULL, &memsize) == 0); | | 1556 | memtype, 0, &memt, &memh, NULL, &memsize) == 0); |
1569 | break; | | 1557 | break; |
1570 | default: | | 1558 | default: |
1571 | memh_valid = 0; | | 1559 | memh_valid = 0; |
1572 | break; | | 1560 | break; |
1573 | } | | 1561 | } |
1574 | | | 1562 | |
1575 | if (memh_valid) { | | 1563 | if (memh_valid) { |
1576 | sc->sc_st = memt; | | 1564 | sc->sc_st = memt; |
1577 | sc->sc_sh = memh; | | 1565 | sc->sc_sh = memh; |
1578 | sc->sc_ss = memsize; | | 1566 | sc->sc_ss = memsize; |
1579 | } else { | | 1567 | } else { |
1580 | aprint_error_dev(sc->sc_dev, | | 1568 | aprint_error_dev(sc->sc_dev, |
1581 | "unable to map device registers\n"); | | 1569 | "unable to map device registers\n"); |
1582 | return; | | 1570 | return; |
1583 | } | | 1571 | } |
1584 | | | 1572 | |
1585 | /* | | 1573 | /* |
1586 | * In addition, i82544 and later support I/O mapped indirect | | 1574 | * In addition, i82544 and later support I/O mapped indirect |
1587 | * register access. It is not desirable (nor supported in | | 1575 | * register access. It is not desirable (nor supported in |
1588 | * this driver) to use it for normal operation, though it is | | 1576 | * this driver) to use it for normal operation, though it is |
1589 | * required to work around bugs in some chip versions. | | 1577 | * required to work around bugs in some chip versions. |
1590 | */ | | 1578 | */ |
1591 | if (sc->sc_type >= WM_T_82544) { | | 1579 | if (sc->sc_type >= WM_T_82544) { |
1592 | /* First we have to find the I/O BAR. */ | | 1580 | /* First we have to find the I/O BAR. */ |
1593 | for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { | | 1581 | for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { |
1594 | memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, i); | | 1582 | memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, i); |
1595 | if (memtype == PCI_MAPREG_TYPE_IO) | | 1583 | if (memtype == PCI_MAPREG_TYPE_IO) |
1596 | break; | | 1584 | break; |
1597 | if (PCI_MAPREG_MEM_TYPE(memtype) == | | 1585 | if (PCI_MAPREG_MEM_TYPE(memtype) == |
1598 | PCI_MAPREG_MEM_TYPE_64BIT) | | 1586 | PCI_MAPREG_MEM_TYPE_64BIT) |
1599 | i += 4; /* skip high bits, too */ | | 1587 | i += 4; /* skip high bits, too */ |
1600 | } | | 1588 | } |
1601 | if (i < PCI_MAPREG_END) { | | 1589 | if (i < PCI_MAPREG_END) { |
1602 | /* | | 1590 | /* |
1603 | * We found PCI_MAPREG_TYPE_IO. Note that 82580 | | 1591 | * We found PCI_MAPREG_TYPE_IO. Note that 82580 |
1604 | * (and newer?) chip has no PCI_MAPREG_TYPE_IO. | | 1592 | * (and newer?) chip has no PCI_MAPREG_TYPE_IO. |
1605 | * It's no problem because newer chips has no this | | 1593 | * It's no problem because newer chips has no this |
1606 | * bug. | | 1594 | * bug. |
1607 | * | | 1595 | * |
1608 | * The i8254x doesn't apparently respond when the | | 1596 | * The i8254x doesn't apparently respond when the |
1609 | * I/O BAR is 0, which looks somewhat like it's not | | 1597 | * I/O BAR is 0, which looks somewhat like it's not |
1610 | * been configured. | | 1598 | * been configured. |
1611 | */ | | 1599 | */ |
1612 | preg = pci_conf_read(pc, pa->pa_tag, i); | | 1600 | preg = pci_conf_read(pc, pa->pa_tag, i); |
1613 | if (PCI_MAPREG_MEM_ADDR(preg) == 0) { | | 1601 | if (PCI_MAPREG_MEM_ADDR(preg) == 0) { |
1614 | aprint_error_dev(sc->sc_dev, | | 1602 | aprint_error_dev(sc->sc_dev, |
1615 | "WARNING: I/O BAR at zero.\n"); | | 1603 | "WARNING: I/O BAR at zero.\n"); |
1616 | } else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO, | | 1604 | } else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO, |
1617 | 0, &sc->sc_iot, &sc->sc_ioh, | | 1605 | 0, &sc->sc_iot, &sc->sc_ioh, |
1618 | NULL, &sc->sc_ios) == 0) { | | 1606 | NULL, &sc->sc_ios) == 0) { |
1619 | sc->sc_flags |= WM_F_IOH_VALID; | | 1607 | sc->sc_flags |= WM_F_IOH_VALID; |
1620 | } else { | | 1608 | } else { |
1621 | aprint_error_dev(sc->sc_dev, | | 1609 | aprint_error_dev(sc->sc_dev, |
1622 | "WARNING: unable to map I/O space\n"); | | 1610 | "WARNING: unable to map I/O space\n"); |
1623 | } | | 1611 | } |
1624 | } | | 1612 | } |
1625 | | | 1613 | |
1626 | } | | 1614 | } |
1627 | | | 1615 | |
1628 | /* Enable bus mastering. Disable MWI on the i82542 2.0. */ | | 1616 | /* Enable bus mastering. Disable MWI on the i82542 2.0. */ |
1629 | preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); | | 1617 | preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); |
1630 | preg |= PCI_COMMAND_MASTER_ENABLE; | | 1618 | preg |= PCI_COMMAND_MASTER_ENABLE; |
1631 | if (sc->sc_type < WM_T_82542_2_1) | | 1619 | if (sc->sc_type < WM_T_82542_2_1) |
1632 | preg &= ~PCI_COMMAND_INVALIDATE_ENABLE; | | 1620 | preg &= ~PCI_COMMAND_INVALIDATE_ENABLE; |
1633 | pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); | | 1621 | pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); |
1634 | | | 1622 | |
1635 | /* power up chip */ | | 1623 | /* power up chip */ |
1636 | if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, | | 1624 | if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, |
1637 | NULL)) && error != EOPNOTSUPP) { | | 1625 | NULL)) && error != EOPNOTSUPP) { |
1638 | aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); | | 1626 | aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); |
1639 | return; | | 1627 | return; |
1640 | } | | 1628 | } |
1641 | | | 1629 | |
1642 | /* XXX Currently, Tx, Rx queue are always one. */ | | 1630 | /* XXX Currently, Tx, Rx queue are always one. */ |
1643 | sc->sc_nrxqueues = 1; | | 1631 | sc->sc_nrxqueues = 1; |
1644 | sc->sc_ntxqueues = 1; | | 1632 | sc->sc_ntxqueues = 1; |
1645 | error = wm_alloc_txrx_queues(sc); | | 1633 | error = wm_alloc_txrx_queues(sc); |
1646 | if (error) | | 1634 | if (error) |
1647 | return; | | 1635 | return; |
1648 | | | 1636 | |
1649 | #ifndef WM_MSI_MSIX | | 1637 | #ifndef WM_MSI_MSIX |
1650 | /* | | 1638 | /* |
1651 | * Map and establish our interrupt. | | 1639 | * Map and establish our interrupt. |
1652 | */ | | 1640 | */ |
1653 | if (pci_intr_map(pa, &ih)) { | | 1641 | if (pci_intr_map(pa, &ih)) { |
1654 | aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); | | 1642 | aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); |
1655 | return; | | 1643 | return; |
1656 | } | | 1644 | } |
1657 | intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); | | 1645 | intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); |
1658 | #ifdef WM_MPSAFE | | 1646 | #ifdef WM_MPSAFE |
1659 | pci_intr_setattr(pc, &ih, PCI_INTR_MPSAFE, true); | | 1647 | pci_intr_setattr(pc, &ih, PCI_INTR_MPSAFE, true); |
1660 | #endif | | 1648 | #endif |
1661 | sc->sc_ihs[0] = pci_intr_establish_xname(pc, ih, IPL_NET, | | 1649 | sc->sc_ihs[0] = pci_intr_establish_xname(pc, ih, IPL_NET, |
1662 | wm_intr_legacy, sc, device_xname(sc->sc_dev)); | | 1650 | wm_intr_legacy, sc, device_xname(sc->sc_dev)); |
1663 | if (sc->sc_ihs[0] == NULL) { | | 1651 | if (sc->sc_ihs[0] == NULL) { |
1664 | aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); | | 1652 | aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); |
1665 | if (intrstr != NULL) | | 1653 | if (intrstr != NULL) |
1666 | aprint_error(" at %s", intrstr); | | 1654 | aprint_error(" at %s", intrstr); |
1667 | aprint_error("\n"); | | 1655 | aprint_error("\n"); |
1668 | return; | | 1656 | return; |
1669 | } | | 1657 | } |
1670 | aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); | | 1658 | aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); |
1671 | sc->sc_nintrs = 1; | | 1659 | sc->sc_nintrs = 1; |
1672 | #else /* WM_MSI_MSIX */ | | 1660 | #else /* WM_MSI_MSIX */ |
1673 | /* Allocation settings */ | | 1661 | /* Allocation settings */ |
1674 | max_type = PCI_INTR_TYPE_MSIX; | | 1662 | max_type = PCI_INTR_TYPE_MSIX; |
1675 | counts[PCI_INTR_TYPE_MSIX] = WM_MAX_NINTR; | | 1663 | counts[PCI_INTR_TYPE_MSIX] = WM_MAX_NINTR; |
1676 | counts[PCI_INTR_TYPE_MSI] = 1; | | 1664 | counts[PCI_INTR_TYPE_MSI] = 1; |
1677 | counts[PCI_INTR_TYPE_INTX] = 1; | | 1665 | counts[PCI_INTR_TYPE_INTX] = 1; |
1678 | | | 1666 | |
1679 | alloc_retry: | | 1667 | alloc_retry: |
1680 | if (pci_intr_alloc(pa, &sc->sc_intrs, counts, max_type) != 0) { | | 1668 | if (pci_intr_alloc(pa, &sc->sc_intrs, counts, max_type) != 0) { |
1681 | aprint_error_dev(sc->sc_dev, "failed to allocate interrupt\n"); | | 1669 | aprint_error_dev(sc->sc_dev, "failed to allocate interrupt\n"); |
1682 | return; | | 1670 | return; |
1683 | } | | 1671 | } |
1684 | | | 1672 | |
1685 | if (pci_intr_type(sc->sc_intrs[0]) == PCI_INTR_TYPE_MSIX) { | | 1673 | if (pci_intr_type(sc->sc_intrs[0]) == PCI_INTR_TYPE_MSIX) { |
1686 | void *vih; | | 1674 | error = wm_setup_msix(sc); |
1687 | kcpuset_t *affinity; | | 1675 | if (error) { |
1688 | char intr_xname[INTRDEVNAMEBUF]; | | 1676 | pci_intr_release(pc, sc->sc_intrs, |
1689 | | | 1677 | counts[PCI_INTR_TYPE_MSIX]); |
1690 | kcpuset_create(&affinity, false); | | 1678 | |
1691 | | | 1679 | /* Setup for MSI: Disable MSI-X */ |
1692 | for (i = 0; i < WM_MSIX_NINTR; i++) { | | 1680 | max_type = PCI_INTR_TYPE_MSI; |
1693 | intrstr = pci_intr_string(pc, | | 1681 | counts[PCI_INTR_TYPE_MSI] = 1; |
1694 | sc->sc_intrs[msix_matrix[i].intridx], intrbuf, | | 1682 | counts[PCI_INTR_TYPE_INTX] = 1; |
1695 | sizeof(intrbuf)); | | 1683 | goto alloc_retry; |
1696 | #ifdef WM_MPSAFE | | | |
1697 | pci_intr_setattr(pc, | | | |
1698 | &sc->sc_intrs[msix_matrix[i].intridx], | | | |
1699 | PCI_INTR_MPSAFE, true); | | | |
1700 | #endif | | | |
1701 | memset(intr_xname, 0, sizeof(intr_xname)); | | | |
1702 | strlcat(intr_xname, device_xname(sc->sc_dev), | | | |
1703 | sizeof(intr_xname)); | | | |
1704 | strlcat(intr_xname, msix_matrix[i].intrname, | | | |
1705 | sizeof(intr_xname)); | | | |
1706 | vih = pci_intr_establish_xname(pc, | | | |
1707 | sc->sc_intrs[msix_matrix[i].intridx], IPL_NET, | | | |
1708 | msix_matrix[i].func, sc, intr_xname); | | | |
1709 | if (vih == NULL) { | | | |
1710 | aprint_error_dev(sc->sc_dev, | | | |
1711 | "unable to establish MSI-X(for %s)%s%s\n", | | | |
1712 | msix_matrix[i].intrname, | | | |
1713 | intrstr ? " at " : "", | | | |
1714 | intrstr ? intrstr : ""); | | | |
1715 | pci_intr_release(sc->sc_pc, sc->sc_intrs, | | | |
1716 | WM_MSIX_NINTR); | | | |
1717 | kcpuset_destroy(affinity); | | | |
1718 | | | | |
1719 | /* Setup for MSI: Disable MSI-X */ | | | |
1720 | max_type = PCI_INTR_TYPE_MSI; | | | |
1721 | counts[PCI_INTR_TYPE_MSI] = 1; | | | |
1722 | counts[PCI_INTR_TYPE_INTX] = 1; | | | |
1723 | goto alloc_retry; | | | |
1724 | } | | | |
1725 | kcpuset_zero(affinity); | | | |
1726 | /* Round-robin affinity */ | | | |
1727 | kcpuset_set(affinity, msix_matrix[i].cpuid % ncpu); | | | |
1728 | error = interrupt_distribute(vih, affinity, NULL); | | | |
1729 | if (error == 0) { | | | |
1730 | aprint_normal_dev(sc->sc_dev, | | | |
1731 | "for %s interrupting at %s affinity to %u\n", | | | |
1732 | msix_matrix[i].intrname, intrstr, | | | |
1733 | msix_matrix[i].cpuid % ncpu); | | | |
1734 | } else { | | | |
1735 | aprint_normal_dev(sc->sc_dev, | | | |
1736 | "for %s interrupting at %s\n", | | | |
1737 | msix_matrix[i].intrname, intrstr); | | | |
1738 | } | | | |
1739 | sc->sc_ihs[msix_matrix[i].intridx] = vih; | | | |
1740 | } | | 1684 | } |
| | | 1685 | } else if (pci_intr_type(sc->sc_intrs[0]) == PCI_INTR_TYPE_MSI) { |
| | | 1686 | error = wm_setup_legacy(sc); |
| | | 1687 | if (error) { |
| | | 1688 | pci_intr_release(sc->sc_pc, sc->sc_intrs, |
| | | 1689 | counts[PCI_INTR_TYPE_MSI]); |
1741 | | | 1690 | |
1742 | sc->sc_nintrs = WM_MSIX_NINTR; | | 1691 | /* The next try is for INTx: Disable MSI */ |
1743 | kcpuset_destroy(affinity); | | 1692 | max_type = PCI_INTR_TYPE_INTX; |
| | | 1693 | counts[PCI_INTR_TYPE_INTX] = 1; |
| | | 1694 | goto alloc_retry; |
| | | 1695 | } |
1744 | } else { | | 1696 | } else { |
1745 | /* MSI or INTx */ | | 1697 | error = wm_setup_legacy(sc); |
1746 | intrstr = pci_intr_string(pc, sc->sc_intrs[0], intrbuf, | | 1698 | if (error) { |
1747 | sizeof(intrbuf)); | | 1699 | pci_intr_release(sc->sc_pc, sc->sc_intrs, |
1748 | #ifdef WM_MPSAFE | | 1700 | counts[PCI_INTR_TYPE_INTX]); |
1749 | pci_intr_setattr(pc, &sc->sc_intrs[0], PCI_INTR_MPSAFE, true); | | 1701 | return; |
1750 | #endif | | | |
1751 | sc->sc_ihs[0] = pci_intr_establish_xname(pc, sc->sc_intrs[0], | | | |
1752 | IPL_NET, wm_intr_legacy, sc, device_xname(sc->sc_dev)); | | | |
1753 | if (sc->sc_ihs[0] == NULL) { | | | |
1754 | aprint_error_dev(sc->sc_dev,"unable to establish %s\n", | | | |
1755 | (pci_intr_type(sc->sc_intrs[0]) | | | |
1756 | == PCI_INTR_TYPE_MSI) ? "MSI" : "INTx"); | | | |
1757 | pci_intr_release(sc->sc_pc, sc->sc_intrs, 1); | | | |
1758 | switch (pci_intr_type(sc->sc_intrs[0])) { | | | |
1759 | case PCI_INTR_TYPE_MSI: | | | |
1760 | /* The next try is for INTx: Disable MSI */ | | | |
1761 | max_type = PCI_INTR_TYPE_INTX; | | | |
1762 | counts[PCI_INTR_TYPE_INTX] = 1; | | | |
1763 | goto alloc_retry; | | | |
1764 | case PCI_INTR_TYPE_INTX: | | | |
1765 | default: | | | |
1766 | return; | | | |
1767 | } | | | |
1768 | } | | 1702 | } |
1769 | aprint_normal_dev(sc->sc_dev, "%s at %s\n", | | | |
1770 | (pci_intr_type(sc->sc_intrs[0]) == PCI_INTR_TYPE_MSI) | | | |
1771 | ? "MSI" : "interrupting", intrstr); | | | |
1772 | | | | |
1773 | sc->sc_nintrs = 1; | | | |
1774 | } | | 1703 | } |
1775 | #endif /* WM_MSI_MSIX */ | | 1704 | #endif /* WM_MSI_MSIX */ |
1776 | | | 1705 | |
1777 | /* | | 1706 | /* |
1778 | * Check the function ID (unit number of the chip). | | 1707 | * Check the function ID (unit number of the chip). |
1779 | */ | | 1708 | */ |
1780 | if ((sc->sc_type == WM_T_82546) || (sc->sc_type == WM_T_82546_3) | | 1709 | if ((sc->sc_type == WM_T_82546) || (sc->sc_type == WM_T_82546_3) |
1781 | || (sc->sc_type == WM_T_82571) || (sc->sc_type == WM_T_80003) | | 1710 | || (sc->sc_type == WM_T_82571) || (sc->sc_type == WM_T_80003) |
1782 | || (sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576) | | 1711 | || (sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576) |
1783 | || (sc->sc_type == WM_T_82580) | | 1712 | || (sc->sc_type == WM_T_82580) |
1784 | || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)) | | 1713 | || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)) |
1785 | sc->sc_funcid = (CSR_READ(sc, WMREG_STATUS) | | 1714 | sc->sc_funcid = (CSR_READ(sc, WMREG_STATUS) |
1786 | >> STATUS_FUNCID_SHIFT) & STATUS_FUNCID_MASK; | | 1715 | >> STATUS_FUNCID_SHIFT) & STATUS_FUNCID_MASK; |
1787 | else | | 1716 | else |
1788 | sc->sc_funcid = 0; | | 1717 | sc->sc_funcid = 0; |
1789 | | | 1718 | |
1790 | /* | | 1719 | /* |
1791 | * Determine a few things about the bus we're connected to. | | 1720 | * Determine a few things about the bus we're connected to. |
1792 | */ | | 1721 | */ |
1793 | if (sc->sc_type < WM_T_82543) { | | 1722 | if (sc->sc_type < WM_T_82543) { |
1794 | /* We don't really know the bus characteristics here. */ | | 1723 | /* We don't really know the bus characteristics here. */ |
1795 | sc->sc_bus_speed = 33; | | 1724 | sc->sc_bus_speed = 33; |
1796 | } else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) { | | 1725 | } else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) { |
1797 | /* | | 1726 | /* |
1798 | * CSA (Communication Streaming Architecture) is about as fast | | 1727 | * CSA (Communication Streaming Architecture) is about as fast |
1799 | * a 32-bit 66MHz PCI Bus. | | 1728 | * a 32-bit 66MHz PCI Bus. |
1800 | */ | | 1729 | */ |
1801 | sc->sc_flags |= WM_F_CSA; | | 1730 | sc->sc_flags |= WM_F_CSA; |
1802 | sc->sc_bus_speed = 66; | | 1731 | sc->sc_bus_speed = 66; |
1803 | aprint_verbose_dev(sc->sc_dev, | | 1732 | aprint_verbose_dev(sc->sc_dev, |
1804 | "Communication Streaming Architecture\n"); | | 1733 | "Communication Streaming Architecture\n"); |
1805 | if (sc->sc_type == WM_T_82547) { | | 1734 | if (sc->sc_type == WM_T_82547) { |
1806 | callout_init(&sc->sc_txfifo_ch, CALLOUT_FLAGS); | | 1735 | callout_init(&sc->sc_txfifo_ch, CALLOUT_FLAGS); |
1807 | callout_setfunc(&sc->sc_txfifo_ch, | | 1736 | callout_setfunc(&sc->sc_txfifo_ch, |
1808 | wm_82547_txfifo_stall, sc); | | 1737 | wm_82547_txfifo_stall, sc); |
1809 | aprint_verbose_dev(sc->sc_dev, | | 1738 | aprint_verbose_dev(sc->sc_dev, |
1810 | "using 82547 Tx FIFO stall work-around\n"); | | 1739 | "using 82547 Tx FIFO stall work-around\n"); |
1811 | } | | 1740 | } |
1812 | } else if (sc->sc_type >= WM_T_82571) { | | 1741 | } else if (sc->sc_type >= WM_T_82571) { |
1813 | sc->sc_flags |= WM_F_PCIE; | | 1742 | sc->sc_flags |= WM_F_PCIE; |
1814 | if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9) | | 1743 | if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9) |
1815 | && (sc->sc_type != WM_T_ICH10) | | 1744 | && (sc->sc_type != WM_T_ICH10) |
1816 | && (sc->sc_type != WM_T_PCH) | | 1745 | && (sc->sc_type != WM_T_PCH) |
1817 | && (sc->sc_type != WM_T_PCH2) | | 1746 | && (sc->sc_type != WM_T_PCH2) |
1818 | && (sc->sc_type != WM_T_PCH_LPT)) { | | 1747 | && (sc->sc_type != WM_T_PCH_LPT)) { |
1819 | /* ICH* and PCH* have no PCIe capability registers */ | | 1748 | /* ICH* and PCH* have no PCIe capability registers */ |
1820 | if (pci_get_capability(pa->pa_pc, pa->pa_tag, | | 1749 | if (pci_get_capability(pa->pa_pc, pa->pa_tag, |
1821 | PCI_CAP_PCIEXPRESS, &sc->sc_pcixe_capoff, | | 1750 | PCI_CAP_PCIEXPRESS, &sc->sc_pcixe_capoff, |
1822 | NULL) == 0) | | 1751 | NULL) == 0) |
1823 | aprint_error_dev(sc->sc_dev, | | 1752 | aprint_error_dev(sc->sc_dev, |
1824 | "unable to find PCIe capability\n"); | | 1753 | "unable to find PCIe capability\n"); |
1825 | } | | 1754 | } |
1826 | aprint_verbose_dev(sc->sc_dev, "PCI-Express bus\n"); | | 1755 | aprint_verbose_dev(sc->sc_dev, "PCI-Express bus\n"); |
1827 | } else { | | 1756 | } else { |
1828 | reg = CSR_READ(sc, WMREG_STATUS); | | 1757 | reg = CSR_READ(sc, WMREG_STATUS); |
1829 | if (reg & STATUS_BUS64) | | 1758 | if (reg & STATUS_BUS64) |
1830 | sc->sc_flags |= WM_F_BUS64; | | 1759 | sc->sc_flags |= WM_F_BUS64; |
1831 | if ((reg & STATUS_PCIX_MODE) != 0) { | | 1760 | if ((reg & STATUS_PCIX_MODE) != 0) { |
1832 | pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb; | | 1761 | pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb; |
1833 | | | 1762 | |
1834 | sc->sc_flags |= WM_F_PCIX; | | 1763 | sc->sc_flags |= WM_F_PCIX; |
1835 | if (pci_get_capability(pa->pa_pc, pa->pa_tag, | | 1764 | if (pci_get_capability(pa->pa_pc, pa->pa_tag, |
1836 | PCI_CAP_PCIX, &sc->sc_pcixe_capoff, NULL) == 0) | | 1765 | PCI_CAP_PCIX, &sc->sc_pcixe_capoff, NULL) == 0) |
1837 | aprint_error_dev(sc->sc_dev, | | 1766 | aprint_error_dev(sc->sc_dev, |
1838 | "unable to find PCIX capability\n"); | | 1767 | "unable to find PCIX capability\n"); |
1839 | else if (sc->sc_type != WM_T_82545_3 && | | 1768 | else if (sc->sc_type != WM_T_82545_3 && |
1840 | sc->sc_type != WM_T_82546_3) { | | 1769 | sc->sc_type != WM_T_82546_3) { |
1841 | /* | | 1770 | /* |
1842 | * Work around a problem caused by the BIOS | | 1771 | * Work around a problem caused by the BIOS |
1843 | * setting the max memory read byte count | | 1772 | * setting the max memory read byte count |
1844 | * incorrectly. | | 1773 | * incorrectly. |
1845 | */ | | 1774 | */ |
1846 | pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, | | 1775 | pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, |
1847 | sc->sc_pcixe_capoff + PCIX_CMD); | | 1776 | sc->sc_pcixe_capoff + PCIX_CMD); |
1848 | pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag, | | 1777 | pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag, |
1849 | sc->sc_pcixe_capoff + PCIX_STATUS); | | 1778 | sc->sc_pcixe_capoff + PCIX_STATUS); |
1850 | | | 1779 | |
1851 | bytecnt = | | 1780 | bytecnt = |
1852 | (pcix_cmd & PCIX_CMD_BYTECNT_MASK) >> | | 1781 | (pcix_cmd & PCIX_CMD_BYTECNT_MASK) >> |
1853 | PCIX_CMD_BYTECNT_SHIFT; | | 1782 | PCIX_CMD_BYTECNT_SHIFT; |
1854 | maxb = | | 1783 | maxb = |
1855 | (pcix_sts & PCIX_STATUS_MAXB_MASK) >> | | 1784 | (pcix_sts & PCIX_STATUS_MAXB_MASK) >> |
1856 | PCIX_STATUS_MAXB_SHIFT; | | 1785 | PCIX_STATUS_MAXB_SHIFT; |
1857 | if (bytecnt > maxb) { | | 1786 | if (bytecnt > maxb) { |
1858 | aprint_verbose_dev(sc->sc_dev, | | 1787 | aprint_verbose_dev(sc->sc_dev, |
1859 | "resetting PCI-X MMRBC: %d -> %d\n", | | 1788 | "resetting PCI-X MMRBC: %d -> %d\n", |
1860 | 512 << bytecnt, 512 << maxb); | | 1789 | 512 << bytecnt, 512 << maxb); |
1861 | pcix_cmd = (pcix_cmd & | | 1790 | pcix_cmd = (pcix_cmd & |
1862 | ~PCIX_CMD_BYTECNT_MASK) | | | 1791 | ~PCIX_CMD_BYTECNT_MASK) | |
1863 | (maxb << PCIX_CMD_BYTECNT_SHIFT); | | 1792 | (maxb << PCIX_CMD_BYTECNT_SHIFT); |
1864 | pci_conf_write(pa->pa_pc, pa->pa_tag, | | 1793 | pci_conf_write(pa->pa_pc, pa->pa_tag, |
1865 | sc->sc_pcixe_capoff + PCIX_CMD, | | 1794 | sc->sc_pcixe_capoff + PCIX_CMD, |
1866 | pcix_cmd); | | 1795 | pcix_cmd); |
1867 | } | | 1796 | } |
1868 | } | | 1797 | } |
1869 | } | | 1798 | } |
1870 | /* | | 1799 | /* |
1871 | * The quad port adapter is special; it has a PCIX-PCIX | | 1800 | * The quad port adapter is special; it has a PCIX-PCIX |
1872 | * bridge on the board, and can run the secondary bus at | | 1801 | * bridge on the board, and can run the secondary bus at |
1873 | * a higher speed. | | 1802 | * a higher speed. |
1874 | */ | | 1803 | */ |
1875 | if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) { | | 1804 | if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) { |
1876 | sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120 | | 1805 | sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120 |
1877 | : 66; | | 1806 | : 66; |
1878 | } else if (sc->sc_flags & WM_F_PCIX) { | | 1807 | } else if (sc->sc_flags & WM_F_PCIX) { |
1879 | switch (reg & STATUS_PCIXSPD_MASK) { | | 1808 | switch (reg & STATUS_PCIXSPD_MASK) { |
1880 | case STATUS_PCIXSPD_50_66: | | 1809 | case STATUS_PCIXSPD_50_66: |
1881 | sc->sc_bus_speed = 66; | | 1810 | sc->sc_bus_speed = 66; |
1882 | break; | | 1811 | break; |
1883 | case STATUS_PCIXSPD_66_100: | | 1812 | case STATUS_PCIXSPD_66_100: |
1884 | sc->sc_bus_speed = 100; | | 1813 | sc->sc_bus_speed = 100; |
1885 | break; | | 1814 | break; |
1886 | case STATUS_PCIXSPD_100_133: | | 1815 | case STATUS_PCIXSPD_100_133: |
1887 | sc->sc_bus_speed = 133; | | 1816 | sc->sc_bus_speed = 133; |
1888 | break; | | 1817 | break; |
1889 | default: | | 1818 | default: |
1890 | aprint_error_dev(sc->sc_dev, | | 1819 | aprint_error_dev(sc->sc_dev, |
1891 | "unknown PCIXSPD %d; assuming 66MHz\n", | | 1820 | "unknown PCIXSPD %d; assuming 66MHz\n", |
1892 | reg & STATUS_PCIXSPD_MASK); | | 1821 | reg & STATUS_PCIXSPD_MASK); |
1893 | sc->sc_bus_speed = 66; | | 1822 | sc->sc_bus_speed = 66; |
1894 | break; | | 1823 | break; |
1895 | } | | 1824 | } |
1896 | } else | | 1825 | } else |
1897 | sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33; | | 1826 | sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33; |
1898 | aprint_verbose_dev(sc->sc_dev, "%d-bit %dMHz %s bus\n", | | 1827 | aprint_verbose_dev(sc->sc_dev, "%d-bit %dMHz %s bus\n", |
1899 | (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed, | | 1828 | (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed, |
1900 | (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI"); | | 1829 | (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI"); |
1901 | } | | 1830 | } |
1902 | | | 1831 | |
1903 | /* clear interesting stat counters */ | | 1832 | /* clear interesting stat counters */ |
1904 | CSR_READ(sc, WMREG_COLC); | | 1833 | CSR_READ(sc, WMREG_COLC); |
1905 | CSR_READ(sc, WMREG_RXERRC); | | 1834 | CSR_READ(sc, WMREG_RXERRC); |
1906 | | | 1835 | |
1907 | /* get PHY control from SMBus to PCIe */ | | 1836 | /* get PHY control from SMBus to PCIe */ |
1908 | if ((sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2) | | 1837 | if ((sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2) |
1909 | || (sc->sc_type == WM_T_PCH_LPT)) | | 1838 | || (sc->sc_type == WM_T_PCH_LPT)) |
1910 | wm_smbustopci(sc); | | 1839 | wm_smbustopci(sc); |
1911 | | | 1840 | |
1912 | /* Reset the chip to a known state. */ | | 1841 | /* Reset the chip to a known state. */ |
1913 | wm_reset(sc); | | 1842 | wm_reset(sc); |
1914 | | | 1843 | |
1915 | /* Get some information about the EEPROM. */ | | 1844 | /* Get some information about the EEPROM. */ |
1916 | switch (sc->sc_type) { | | 1845 | switch (sc->sc_type) { |
1917 | case WM_T_82542_2_0: | | 1846 | case WM_T_82542_2_0: |
1918 | case WM_T_82542_2_1: | | 1847 | case WM_T_82542_2_1: |
1919 | case WM_T_82543: | | 1848 | case WM_T_82543: |
1920 | case WM_T_82544: | | 1849 | case WM_T_82544: |
1921 | /* Microwire */ | | 1850 | /* Microwire */ |
1922 | sc->sc_nvm_wordsize = 64; | | 1851 | sc->sc_nvm_wordsize = 64; |
1923 | sc->sc_nvm_addrbits = 6; | | 1852 | sc->sc_nvm_addrbits = 6; |
1924 | break; | | 1853 | break; |
1925 | case WM_T_82540: | | 1854 | case WM_T_82540: |
1926 | case WM_T_82545: | | 1855 | case WM_T_82545: |
1927 | case WM_T_82545_3: | | 1856 | case WM_T_82545_3: |
1928 | case WM_T_82546: | | 1857 | case WM_T_82546: |
1929 | case WM_T_82546_3: | | 1858 | case WM_T_82546_3: |
1930 | /* Microwire */ | | 1859 | /* Microwire */ |
1931 | reg = CSR_READ(sc, WMREG_EECD); | | 1860 | reg = CSR_READ(sc, WMREG_EECD); |
1932 | if (reg & EECD_EE_SIZE) { | | 1861 | if (reg & EECD_EE_SIZE) { |
1933 | sc->sc_nvm_wordsize = 256; | | 1862 | sc->sc_nvm_wordsize = 256; |
1934 | sc->sc_nvm_addrbits = 8; | | 1863 | sc->sc_nvm_addrbits = 8; |
1935 | } else { | | 1864 | } else { |
1936 | sc->sc_nvm_wordsize = 64; | | 1865 | sc->sc_nvm_wordsize = 64; |
1937 | sc->sc_nvm_addrbits = 6; | | 1866 | sc->sc_nvm_addrbits = 6; |
1938 | } | | 1867 | } |
1939 | sc->sc_flags |= WM_F_LOCK_EECD; | | 1868 | sc->sc_flags |= WM_F_LOCK_EECD; |
1940 | break; | | 1869 | break; |
1941 | case WM_T_82541: | | 1870 | case WM_T_82541: |
1942 | case WM_T_82541_2: | | 1871 | case WM_T_82541_2: |
1943 | case WM_T_82547: | | 1872 | case WM_T_82547: |
1944 | case WM_T_82547_2: | | 1873 | case WM_T_82547_2: |
1945 | sc->sc_flags |= WM_F_LOCK_EECD; | | 1874 | sc->sc_flags |= WM_F_LOCK_EECD; |
1946 | reg = CSR_READ(sc, WMREG_EECD); | | 1875 | reg = CSR_READ(sc, WMREG_EECD); |
1947 | if (reg & EECD_EE_TYPE) { | | 1876 | if (reg & EECD_EE_TYPE) { |
1948 | /* SPI */ | | 1877 | /* SPI */ |
1949 | sc->sc_flags |= WM_F_EEPROM_SPI; | | 1878 | sc->sc_flags |= WM_F_EEPROM_SPI; |
1950 | wm_nvm_set_addrbits_size_eecd(sc); | | 1879 | wm_nvm_set_addrbits_size_eecd(sc); |
1951 | } else { | | 1880 | } else { |
1952 | /* Microwire */ | | 1881 | /* Microwire */ |
1953 | if ((reg & EECD_EE_ABITS) != 0) { | | 1882 | if ((reg & EECD_EE_ABITS) != 0) { |
1954 | sc->sc_nvm_wordsize = 256; | | 1883 | sc->sc_nvm_wordsize = 256; |
1955 | sc->sc_nvm_addrbits = 8; | | 1884 | sc->sc_nvm_addrbits = 8; |
1956 | } else { | | 1885 | } else { |
1957 | sc->sc_nvm_wordsize = 64; | | 1886 | sc->sc_nvm_wordsize = 64; |
1958 | sc->sc_nvm_addrbits = 6; | | 1887 | sc->sc_nvm_addrbits = 6; |
1959 | } | | 1888 | } |
1960 | } | | 1889 | } |
1961 | break; | | 1890 | break; |
1962 | case WM_T_82571: | | 1891 | case WM_T_82571: |
1963 | case WM_T_82572: | | 1892 | case WM_T_82572: |
1964 | /* SPI */ | | 1893 | /* SPI */ |
1965 | sc->sc_flags |= WM_F_EEPROM_SPI; | | 1894 | sc->sc_flags |= WM_F_EEPROM_SPI; |
1966 | wm_nvm_set_addrbits_size_eecd(sc); | | 1895 | wm_nvm_set_addrbits_size_eecd(sc); |
1967 | sc->sc_flags |= WM_F_LOCK_EECD | WM_F_LOCK_SWSM; | | 1896 | sc->sc_flags |= WM_F_LOCK_EECD | WM_F_LOCK_SWSM; |
1968 | break; | | 1897 | break; |
1969 | case WM_T_82573: | | 1898 | case WM_T_82573: |
1970 | sc->sc_flags |= WM_F_LOCK_SWSM; | | 1899 | sc->sc_flags |= WM_F_LOCK_SWSM; |
1971 | /* FALLTHROUGH */ | | 1900 | /* FALLTHROUGH */ |
1972 | case WM_T_82574: | | 1901 | case WM_T_82574: |
1973 | case WM_T_82583: | | 1902 | case WM_T_82583: |
1974 | if (wm_nvm_is_onboard_eeprom(sc) == 0) { | | 1903 | if (wm_nvm_is_onboard_eeprom(sc) == 0) { |
1975 | sc->sc_flags |= WM_F_EEPROM_FLASH; | | 1904 | sc->sc_flags |= WM_F_EEPROM_FLASH; |
1976 | sc->sc_nvm_wordsize = 2048; | | 1905 | sc->sc_nvm_wordsize = 2048; |
1977 | } else { | | 1906 | } else { |
1978 | /* SPI */ | | 1907 | /* SPI */ |
1979 | sc->sc_flags |= WM_F_EEPROM_SPI; | | 1908 | sc->sc_flags |= WM_F_EEPROM_SPI; |
1980 | wm_nvm_set_addrbits_size_eecd(sc); | | 1909 | wm_nvm_set_addrbits_size_eecd(sc); |
1981 | } | | 1910 | } |
1982 | sc->sc_flags |= WM_F_EEPROM_EERDEEWR; | | 1911 | sc->sc_flags |= WM_F_EEPROM_EERDEEWR; |
1983 | break; | | 1912 | break; |
1984 | case WM_T_82575: | | 1913 | case WM_T_82575: |
1985 | case WM_T_82576: | | 1914 | case WM_T_82576: |
1986 | case WM_T_82580: | | 1915 | case WM_T_82580: |
1987 | case WM_T_I350: | | 1916 | case WM_T_I350: |
1988 | case WM_T_I354: | | 1917 | case WM_T_I354: |
1989 | case WM_T_80003: | | 1918 | case WM_T_80003: |
1990 | /* SPI */ | | 1919 | /* SPI */ |
1991 | sc->sc_flags |= WM_F_EEPROM_SPI; | | 1920 | sc->sc_flags |= WM_F_EEPROM_SPI; |
1992 | wm_nvm_set_addrbits_size_eecd(sc); | | 1921 | wm_nvm_set_addrbits_size_eecd(sc); |
1993 | sc->sc_flags |= WM_F_EEPROM_EERDEEWR | WM_F_LOCK_SWFW | | 1922 | sc->sc_flags |= WM_F_EEPROM_EERDEEWR | WM_F_LOCK_SWFW |
1994 | | WM_F_LOCK_SWSM; | | 1923 | | WM_F_LOCK_SWSM; |
1995 | break; | | 1924 | break; |
1996 | case WM_T_ICH8: | | 1925 | case WM_T_ICH8: |
1997 | case WM_T_ICH9: | | 1926 | case WM_T_ICH9: |
1998 | case WM_T_ICH10: | | 1927 | case WM_T_ICH10: |
1999 | case WM_T_PCH: | | 1928 | case WM_T_PCH: |
2000 | case WM_T_PCH2: | | 1929 | case WM_T_PCH2: |
2001 | case WM_T_PCH_LPT: | | 1930 | case WM_T_PCH_LPT: |
2002 | /* FLASH */ | | 1931 | /* FLASH */ |
2003 | sc->sc_flags |= WM_F_EEPROM_FLASH | WM_F_LOCK_EXTCNF; | | 1932 | sc->sc_flags |= WM_F_EEPROM_FLASH | WM_F_LOCK_EXTCNF; |
2004 | sc->sc_nvm_wordsize = 2048; | | 1933 | sc->sc_nvm_wordsize = 2048; |
2005 | memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_ICH8_FLASH); | | 1934 | memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_ICH8_FLASH); |
2006 | if (pci_mapreg_map(pa, WM_ICH8_FLASH, memtype, 0, | | 1935 | if (pci_mapreg_map(pa, WM_ICH8_FLASH, memtype, 0, |
2007 | &sc->sc_flasht, &sc->sc_flashh, NULL, &sc->sc_flashs)) { | | 1936 | &sc->sc_flasht, &sc->sc_flashh, NULL, &sc->sc_flashs)) { |
2008 | aprint_error_dev(sc->sc_dev, | | 1937 | aprint_error_dev(sc->sc_dev, |
2009 | "can't map FLASH registers\n"); | | 1938 | "can't map FLASH registers\n"); |
2010 | goto out; | | 1939 | goto out; |
2011 | } | | 1940 | } |
2012 | reg = ICH8_FLASH_READ32(sc, ICH_FLASH_GFPREG); | | 1941 | reg = ICH8_FLASH_READ32(sc, ICH_FLASH_GFPREG); |
2013 | sc->sc_ich8_flash_base = (reg & ICH_GFPREG_BASE_MASK) * | | 1942 | sc->sc_ich8_flash_base = (reg & ICH_GFPREG_BASE_MASK) * |
2014 | ICH_FLASH_SECTOR_SIZE; | | 1943 | ICH_FLASH_SECTOR_SIZE; |
2015 | sc->sc_ich8_flash_bank_size = | | 1944 | sc->sc_ich8_flash_bank_size = |
2016 | ((reg >> 16) & ICH_GFPREG_BASE_MASK) + 1; | | 1945 | ((reg >> 16) & ICH_GFPREG_BASE_MASK) + 1; |
2017 | sc->sc_ich8_flash_bank_size -= | | 1946 | sc->sc_ich8_flash_bank_size -= |
2018 | (reg & ICH_GFPREG_BASE_MASK); | | 1947 | (reg & ICH_GFPREG_BASE_MASK); |
2019 | sc->sc_ich8_flash_bank_size *= ICH_FLASH_SECTOR_SIZE; | | 1948 | sc->sc_ich8_flash_bank_size *= ICH_FLASH_SECTOR_SIZE; |
2020 | sc->sc_ich8_flash_bank_size /= 2 * sizeof(uint16_t); | | 1949 | sc->sc_ich8_flash_bank_size /= 2 * sizeof(uint16_t); |
2021 | break; | | 1950 | break; |
2022 | case WM_T_I210: | | 1951 | case WM_T_I210: |
2023 | case WM_T_I211: | | 1952 | case WM_T_I211: |
2024 | if (wm_nvm_get_flash_presence_i210(sc)) { | | 1953 | if (wm_nvm_get_flash_presence_i210(sc)) { |
2025 | wm_nvm_set_addrbits_size_eecd(sc); | | 1954 | wm_nvm_set_addrbits_size_eecd(sc); |
2026 | sc->sc_flags |= WM_F_EEPROM_FLASH_HW; | | 1955 | sc->sc_flags |= WM_F_EEPROM_FLASH_HW; |
2027 | sc->sc_flags |= WM_F_EEPROM_EERDEEWR | WM_F_LOCK_SWFW; | | 1956 | sc->sc_flags |= WM_F_EEPROM_EERDEEWR | WM_F_LOCK_SWFW; |
2028 | } else { | | 1957 | } else { |
2029 | sc->sc_nvm_wordsize = INVM_SIZE; | | 1958 | sc->sc_nvm_wordsize = INVM_SIZE; |
2030 | sc->sc_flags |= WM_F_EEPROM_INVM; | | 1959 | sc->sc_flags |= WM_F_EEPROM_INVM; |
2031 | sc->sc_flags |= WM_F_LOCK_SWFW; | | 1960 | sc->sc_flags |= WM_F_LOCK_SWFW; |
2032 | } | | 1961 | } |
2033 | break; | | 1962 | break; |
2034 | default: | | 1963 | default: |
2035 | break; | | 1964 | break; |
2036 | } | | 1965 | } |
2037 | | | 1966 | |
2038 | /* Ensure the SMBI bit is clear before first NVM or PHY access */ | | 1967 | /* Ensure the SMBI bit is clear before first NVM or PHY access */ |
2039 | switch (sc->sc_type) { | | 1968 | switch (sc->sc_type) { |
2040 | case WM_T_82571: | | 1969 | case WM_T_82571: |
2041 | case WM_T_82572: | | 1970 | case WM_T_82572: |
2042 | reg = CSR_READ(sc, WMREG_SWSM2); | | 1971 | reg = CSR_READ(sc, WMREG_SWSM2); |
2043 | if ((reg & SWSM2_LOCK) == 0) { | | 1972 | if ((reg & SWSM2_LOCK) == 0) { |
2044 | CSR_WRITE(sc, WMREG_SWSM2, reg | SWSM2_LOCK); | | 1973 | CSR_WRITE(sc, WMREG_SWSM2, reg | SWSM2_LOCK); |
2045 | force_clear_smbi = true; | | 1974 | force_clear_smbi = true; |
2046 | } else | | 1975 | } else |
2047 | force_clear_smbi = false; | | 1976 | force_clear_smbi = false; |
2048 | break; | | 1977 | break; |
2049 | case WM_T_82573: | | 1978 | case WM_T_82573: |
2050 | case WM_T_82574: | | 1979 | case WM_T_82574: |
2051 | case WM_T_82583: | | 1980 | case WM_T_82583: |
2052 | force_clear_smbi = true; | | 1981 | force_clear_smbi = true; |
2053 | break; | | 1982 | break; |
2054 | default: | | 1983 | default: |
2055 | force_clear_smbi = false; | | 1984 | force_clear_smbi = false; |
2056 | break; | | 1985 | break; |
2057 | } | | 1986 | } |
2058 | if (force_clear_smbi) { | | 1987 | if (force_clear_smbi) { |
2059 | reg = CSR_READ(sc, WMREG_SWSM); | | 1988 | reg = CSR_READ(sc, WMREG_SWSM); |
2060 | if ((reg & SWSM_SMBI) != 0) | | 1989 | if ((reg & SWSM_SMBI) != 0) |
2061 | aprint_error_dev(sc->sc_dev, | | 1990 | aprint_error_dev(sc->sc_dev, |
2062 | "Please update the Bootagent\n"); | | 1991 | "Please update the Bootagent\n"); |
2063 | CSR_WRITE(sc, WMREG_SWSM, reg & ~SWSM_SMBI); | | 1992 | CSR_WRITE(sc, WMREG_SWSM, reg & ~SWSM_SMBI); |
2064 | } | | 1993 | } |
2065 | | | 1994 | |
2066 | /* | | 1995 | /* |
2067 | * Defer printing the EEPROM type until after verifying the checksum | | 1996 | * Defer printing the EEPROM type until after verifying the checksum |
2068 | * This allows the EEPROM type to be printed correctly in the case | | 1997 | * This allows the EEPROM type to be printed correctly in the case |
2069 | * that no EEPROM is attached. | | 1998 | * that no EEPROM is attached. |
2070 | */ | | 1999 | */ |
2071 | /* | | 2000 | /* |
2072 | * Validate the EEPROM checksum. If the checksum fails, flag | | 2001 | * Validate the EEPROM checksum. If the checksum fails, flag |
2073 | * this for later, so we can fail future reads from the EEPROM. | | 2002 | * this for later, so we can fail future reads from the EEPROM. |
2074 | */ | | 2003 | */ |
2075 | if (wm_nvm_validate_checksum(sc)) { | | 2004 | if (wm_nvm_validate_checksum(sc)) { |
2076 | /* | | 2005 | /* |
2077 | * Read twice again because some PCI-e parts fail the | | 2006 | * Read twice again because some PCI-e parts fail the |
2078 | * first check due to the link being in sleep state. | | 2007 | * first check due to the link being in sleep state. |
2079 | */ | | 2008 | */ |
2080 | if (wm_nvm_validate_checksum(sc)) | | 2009 | if (wm_nvm_validate_checksum(sc)) |
2081 | sc->sc_flags |= WM_F_EEPROM_INVALID; | | 2010 | sc->sc_flags |= WM_F_EEPROM_INVALID; |
2082 | } | | 2011 | } |
2083 | | | 2012 | |
2084 | /* Set device properties (macflags) */ | | 2013 | /* Set device properties (macflags) */ |
2085 | prop_dictionary_set_uint32(dict, "macflags", sc->sc_flags); | | 2014 | prop_dictionary_set_uint32(dict, "macflags", sc->sc_flags); |
2086 | | | 2015 | |
2087 | if (sc->sc_flags & WM_F_EEPROM_INVALID) | | 2016 | if (sc->sc_flags & WM_F_EEPROM_INVALID) |
2088 | aprint_verbose_dev(sc->sc_dev, "No EEPROM"); | | 2017 | aprint_verbose_dev(sc->sc_dev, "No EEPROM"); |
2089 | else { | | 2018 | else { |
2090 | aprint_verbose_dev(sc->sc_dev, "%u words ", | | 2019 | aprint_verbose_dev(sc->sc_dev, "%u words ", |
2091 | sc->sc_nvm_wordsize); | | 2020 | sc->sc_nvm_wordsize); |
2092 | if (sc->sc_flags & WM_F_EEPROM_INVM) | | 2021 | if (sc->sc_flags & WM_F_EEPROM_INVM) |
2093 | aprint_verbose("iNVM"); | | 2022 | aprint_verbose("iNVM"); |
2094 | else if (sc->sc_flags & WM_F_EEPROM_FLASH_HW) | | 2023 | else if (sc->sc_flags & WM_F_EEPROM_FLASH_HW) |
2095 | aprint_verbose("FLASH(HW)"); | | 2024 | aprint_verbose("FLASH(HW)"); |
2096 | else if (sc->sc_flags & WM_F_EEPROM_FLASH) | | 2025 | else if (sc->sc_flags & WM_F_EEPROM_FLASH) |
2097 | aprint_verbose("FLASH"); | | 2026 | aprint_verbose("FLASH"); |
2098 | else { | | 2027 | else { |
2099 | if (sc->sc_flags & WM_F_EEPROM_SPI) | | 2028 | if (sc->sc_flags & WM_F_EEPROM_SPI) |
2100 | eetype = "SPI"; | | 2029 | eetype = "SPI"; |
2101 | else | | 2030 | else |
2102 | eetype = "MicroWire"; | | 2031 | eetype = "MicroWire"; |
2103 | aprint_verbose("(%d address bits) %s EEPROM", | | 2032 | aprint_verbose("(%d address bits) %s EEPROM", |
2104 | sc->sc_nvm_addrbits, eetype); | | 2033 | sc->sc_nvm_addrbits, eetype); |
2105 | } | | 2034 | } |
2106 | } | | 2035 | } |
2107 | wm_nvm_version(sc); | | 2036 | wm_nvm_version(sc); |
2108 | aprint_verbose("\n"); | | 2037 | aprint_verbose("\n"); |
2109 | | | 2038 | |
2110 | /* Check for I21[01] PLL workaround */ | | 2039 | /* Check for I21[01] PLL workaround */ |
2111 | if (sc->sc_type == WM_T_I210) | | 2040 | if (sc->sc_type == WM_T_I210) |
2112 | sc->sc_flags |= WM_F_PLL_WA_I210; | | 2041 | sc->sc_flags |= WM_F_PLL_WA_I210; |
2113 | if ((sc->sc_type == WM_T_I210) && wm_nvm_get_flash_presence_i210(sc)) { | | 2042 | if ((sc->sc_type == WM_T_I210) && wm_nvm_get_flash_presence_i210(sc)) { |
2114 | /* NVM image release 3.25 has a workaround */ | | 2043 | /* NVM image release 3.25 has a workaround */ |
2115 | if ((sc->sc_nvm_ver_major < 3) | | 2044 | if ((sc->sc_nvm_ver_major < 3) |
2116 | || ((sc->sc_nvm_ver_major == 3) | | 2045 | || ((sc->sc_nvm_ver_major == 3) |
2117 | && (sc->sc_nvm_ver_minor < 25))) { | | 2046 | && (sc->sc_nvm_ver_minor < 25))) { |
2118 | aprint_verbose_dev(sc->sc_dev, | | 2047 | aprint_verbose_dev(sc->sc_dev, |
2119 | "ROM image version %d.%d is older than 3.25\n", | | 2048 | "ROM image version %d.%d is older than 3.25\n", |
2120 | sc->sc_nvm_ver_major, sc->sc_nvm_ver_minor); | | 2049 | sc->sc_nvm_ver_major, sc->sc_nvm_ver_minor); |
2121 | sc->sc_flags |= WM_F_PLL_WA_I210; | | 2050 | sc->sc_flags |= WM_F_PLL_WA_I210; |
2122 | } | | 2051 | } |
2123 | } | | 2052 | } |
2124 | if ((sc->sc_flags & WM_F_PLL_WA_I210) != 0) | | 2053 | if ((sc->sc_flags & WM_F_PLL_WA_I210) != 0) |
2125 | wm_pll_workaround_i210(sc); | | 2054 | wm_pll_workaround_i210(sc); |
2126 | | | 2055 | |
2127 | switch (sc->sc_type) { | | 2056 | switch (sc->sc_type) { |
2128 | case WM_T_82571: | | 2057 | case WM_T_82571: |
2129 | case WM_T_82572: | | 2058 | case WM_T_82572: |
2130 | case WM_T_82573: | | 2059 | case WM_T_82573: |
2131 | case WM_T_82574: | | 2060 | case WM_T_82574: |
2132 | case WM_T_82583: | | 2061 | case WM_T_82583: |
2133 | case WM_T_80003: | | 2062 | case WM_T_80003: |
2134 | case WM_T_ICH8: | | 2063 | case WM_T_ICH8: |
2135 | case WM_T_ICH9: | | 2064 | case WM_T_ICH9: |
2136 | case WM_T_ICH10: | | 2065 | case WM_T_ICH10: |
2137 | case WM_T_PCH: | | 2066 | case WM_T_PCH: |
2138 | case WM_T_PCH2: | | 2067 | case WM_T_PCH2: |
2139 | case WM_T_PCH_LPT: | | 2068 | case WM_T_PCH_LPT: |
2140 | if (wm_check_mng_mode(sc) != 0) | | 2069 | if (wm_check_mng_mode(sc) != 0) |
2141 | wm_get_hw_control(sc); | | 2070 | wm_get_hw_control(sc); |
2142 | break; | | 2071 | break; |
2143 | default: | | 2072 | default: |
2144 | break; | | 2073 | break; |
2145 | } | | 2074 | } |
2146 | wm_get_wakeup(sc); | | 2075 | wm_get_wakeup(sc); |
2147 | /* | | 2076 | /* |
2148 | * Read the Ethernet address from the EEPROM, if not first found | | 2077 | * Read the Ethernet address from the EEPROM, if not first found |
2149 | * in device properties. | | 2078 | * in device properties. |
2150 | */ | | 2079 | */ |
2151 | ea = prop_dictionary_get(dict, "mac-address"); | | 2080 | ea = prop_dictionary_get(dict, "mac-address"); |
2152 | if (ea != NULL) { | | 2081 | if (ea != NULL) { |
2153 | KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); | | 2082 | KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); |
2154 | KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); | | 2083 | KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); |
2155 | memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); | | 2084 | memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); |
2156 | } else { | | 2085 | } else { |
2157 | if (wm_read_mac_addr(sc, enaddr) != 0) { | | 2086 | if (wm_read_mac_addr(sc, enaddr) != 0) { |
2158 | aprint_error_dev(sc->sc_dev, | | 2087 | aprint_error_dev(sc->sc_dev, |
2159 | "unable to read Ethernet address\n"); | | 2088 | "unable to read Ethernet address\n"); |
2160 | goto out; | | 2089 | goto out; |
2161 | } | | 2090 | } |
2162 | } | | 2091 | } |
2163 | | | 2092 | |
2164 | aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", | | 2093 | aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", |
2165 | ether_sprintf(enaddr)); | | 2094 | ether_sprintf(enaddr)); |
2166 | | | 2095 | |
2167 | /* | | 2096 | /* |
2168 | * Read the config info from the EEPROM, and set up various | | 2097 | * Read the config info from the EEPROM, and set up various |
2169 | * bits in the control registers based on their contents. | | 2098 | * bits in the control registers based on their contents. |
2170 | */ | | 2099 | */ |
2171 | pn = prop_dictionary_get(dict, "i82543-cfg1"); | | 2100 | pn = prop_dictionary_get(dict, "i82543-cfg1"); |
2172 | if (pn != NULL) { | | 2101 | if (pn != NULL) { |
2173 | KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); | | 2102 | KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); |
2174 | cfg1 = (uint16_t) prop_number_integer_value(pn); | | 2103 | cfg1 = (uint16_t) prop_number_integer_value(pn); |
2175 | } else { | | 2104 | } else { |
2176 | if (wm_nvm_read(sc, NVM_OFF_CFG1, 1, &cfg1)) { | | 2105 | if (wm_nvm_read(sc, NVM_OFF_CFG1, 1, &cfg1)) { |
2177 | aprint_error_dev(sc->sc_dev, "unable to read CFG1\n"); | | 2106 | aprint_error_dev(sc->sc_dev, "unable to read CFG1\n"); |
2178 | goto out; | | 2107 | goto out; |
2179 | } | | 2108 | } |
2180 | } | | 2109 | } |
2181 | | | 2110 | |
2182 | pn = prop_dictionary_get(dict, "i82543-cfg2"); | | 2111 | pn = prop_dictionary_get(dict, "i82543-cfg2"); |
2183 | if (pn != NULL) { | | 2112 | if (pn != NULL) { |
2184 | KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); | | 2113 | KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); |
2185 | cfg2 = (uint16_t) prop_number_integer_value(pn); | | 2114 | cfg2 = (uint16_t) prop_number_integer_value(pn); |
2186 | } else { | | 2115 | } else { |
2187 | if (wm_nvm_read(sc, NVM_OFF_CFG2, 1, &cfg2)) { | | 2116 | if (wm_nvm_read(sc, NVM_OFF_CFG2, 1, &cfg2)) { |
2188 | aprint_error_dev(sc->sc_dev, "unable to read CFG2\n"); | | 2117 | aprint_error_dev(sc->sc_dev, "unable to read CFG2\n"); |
2189 | goto out; | | 2118 | goto out; |
2190 | } | | 2119 | } |
2191 | } | | 2120 | } |
2192 | | | 2121 | |
2193 | /* check for WM_F_WOL */ | | 2122 | /* check for WM_F_WOL */ |
2194 | switch (sc->sc_type) { | | 2123 | switch (sc->sc_type) { |
2195 | case WM_T_82542_2_0: | | 2124 | case WM_T_82542_2_0: |
2196 | case WM_T_82542_2_1: | | 2125 | case WM_T_82542_2_1: |
2197 | case WM_T_82543: | | 2126 | case WM_T_82543: |
2198 | /* dummy? */ | | 2127 | /* dummy? */ |
2199 | eeprom_data = 0; | | 2128 | eeprom_data = 0; |
2200 | apme_mask = NVM_CFG3_APME; | | 2129 | apme_mask = NVM_CFG3_APME; |
2201 | break; | | 2130 | break; |
2202 | case WM_T_82544: | | 2131 | case WM_T_82544: |
2203 | apme_mask = NVM_CFG2_82544_APM_EN; | | 2132 | apme_mask = NVM_CFG2_82544_APM_EN; |
2204 | eeprom_data = cfg2; | | 2133 | eeprom_data = cfg2; |
2205 | break; | | 2134 | break; |
2206 | case WM_T_82546: | | 2135 | case WM_T_82546: |
2207 | case WM_T_82546_3: | | 2136 | case WM_T_82546_3: |
2208 | case WM_T_82571: | | 2137 | case WM_T_82571: |
2209 | case WM_T_82572: | | 2138 | case WM_T_82572: |
2210 | case WM_T_82573: | | 2139 | case WM_T_82573: |
2211 | case WM_T_82574: | | 2140 | case WM_T_82574: |
2212 | case WM_T_82583: | | 2141 | case WM_T_82583: |
2213 | case WM_T_80003: | | 2142 | case WM_T_80003: |
2214 | default: | | 2143 | default: |
2215 | apme_mask = NVM_CFG3_APME; | | 2144 | apme_mask = NVM_CFG3_APME; |
2216 | wm_nvm_read(sc, (sc->sc_funcid == 1) ? NVM_OFF_CFG3_PORTB | | 2145 | wm_nvm_read(sc, (sc->sc_funcid == 1) ? NVM_OFF_CFG3_PORTB |
2217 | : NVM_OFF_CFG3_PORTA, 1, &eeprom_data); | | 2146 | : NVM_OFF_CFG3_PORTA, 1, &eeprom_data); |
2218 | break; | | 2147 | break; |
2219 | case WM_T_82575: | | 2148 | case WM_T_82575: |
2220 | case WM_T_82576: | | 2149 | case WM_T_82576: |
2221 | case WM_T_82580: | | 2150 | case WM_T_82580: |
2222 | case WM_T_I350: | | 2151 | case WM_T_I350: |
2223 | case WM_T_I354: /* XXX ok? */ | | 2152 | case WM_T_I354: /* XXX ok? */ |
2224 | case WM_T_ICH8: | | 2153 | case WM_T_ICH8: |
2225 | case WM_T_ICH9: | | 2154 | case WM_T_ICH9: |
2226 | case WM_T_ICH10: | | 2155 | case WM_T_ICH10: |
2227 | case WM_T_PCH: | | 2156 | case WM_T_PCH: |
2228 | case WM_T_PCH2: | | 2157 | case WM_T_PCH2: |
2229 | case WM_T_PCH_LPT: | | 2158 | case WM_T_PCH_LPT: |
2230 | /* XXX The funcid should be checked on some devices */ | | 2159 | /* XXX The funcid should be checked on some devices */ |
2231 | apme_mask = WUC_APME; | | 2160 | apme_mask = WUC_APME; |
2232 | eeprom_data = CSR_READ(sc, WMREG_WUC); | | 2161 | eeprom_data = CSR_READ(sc, WMREG_WUC); |
2233 | break; | | 2162 | break; |
2234 | } | | 2163 | } |
2235 | | | 2164 | |
2236 | /* Check for WM_F_WOL flag after the setting of the EEPROM stuff */ | | 2165 | /* Check for WM_F_WOL flag after the setting of the EEPROM stuff */ |
2237 | if ((eeprom_data & apme_mask) != 0) | | 2166 | if ((eeprom_data & apme_mask) != 0) |
2238 | sc->sc_flags |= WM_F_WOL; | | 2167 | sc->sc_flags |= WM_F_WOL; |
2239 | #ifdef WM_DEBUG | | 2168 | #ifdef WM_DEBUG |
2240 | if ((sc->sc_flags & WM_F_WOL) != 0) | | 2169 | if ((sc->sc_flags & WM_F_WOL) != 0) |
2241 | printf("WOL\n"); | | 2170 | printf("WOL\n"); |
2242 | #endif | | 2171 | #endif |
2243 | | | 2172 | |
2244 | if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)) { | | 2173 | if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)) { |
2245 | /* Check NVM for autonegotiation */ | | 2174 | /* Check NVM for autonegotiation */ |
2246 | if (wm_nvm_read(sc, NVM_OFF_COMPAT, 1, &nvmword) == 0) { | | 2175 | if (wm_nvm_read(sc, NVM_OFF_COMPAT, 1, &nvmword) == 0) { |
2247 | if ((nvmword & NVM_COMPAT_SERDES_FORCE_MODE) != 0) | | 2176 | if ((nvmword & NVM_COMPAT_SERDES_FORCE_MODE) != 0) |
2248 | sc->sc_flags |= WM_F_PCS_DIS_AUTONEGO; | | 2177 | sc->sc_flags |= WM_F_PCS_DIS_AUTONEGO; |
2249 | } | | 2178 | } |
2250 | } | | 2179 | } |
2251 | | | 2180 | |
2252 | /* | | 2181 | /* |
2253 | * XXX need special handling for some multiple port cards | | 2182 | * XXX need special handling for some multiple port cards |
2254 | * to disable a paticular port. | | 2183 | * to disable a paticular port. |
2255 | */ | | 2184 | */ |
2256 | | | 2185 | |
2257 | if (sc->sc_type >= WM_T_82544) { | | 2186 | if (sc->sc_type >= WM_T_82544) { |
2258 | pn = prop_dictionary_get(dict, "i82543-swdpin"); | | 2187 | pn = prop_dictionary_get(dict, "i82543-swdpin"); |
2259 | if (pn != NULL) { | | 2188 | if (pn != NULL) { |
2260 | KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); | | 2189 | KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); |
2261 | swdpin = (uint16_t) prop_number_integer_value(pn); | | 2190 | swdpin = (uint16_t) prop_number_integer_value(pn); |
2262 | } else { | | 2191 | } else { |
2263 | if (wm_nvm_read(sc, NVM_OFF_SWDPIN, 1, &swdpin)) { | | 2192 | if (wm_nvm_read(sc, NVM_OFF_SWDPIN, 1, &swdpin)) { |
2264 | aprint_error_dev(sc->sc_dev, | | 2193 | aprint_error_dev(sc->sc_dev, |
2265 | "unable to read SWDPIN\n"); | | 2194 | "unable to read SWDPIN\n"); |
2266 | goto out; | | 2195 | goto out; |
2267 | } | | 2196 | } |
2268 | } | | 2197 | } |
2269 | } | | 2198 | } |
2270 | | | 2199 | |
2271 | if (cfg1 & NVM_CFG1_ILOS) | | 2200 | if (cfg1 & NVM_CFG1_ILOS) |
2272 | sc->sc_ctrl |= CTRL_ILOS; | | 2201 | sc->sc_ctrl |= CTRL_ILOS; |
2273 | | | 2202 | |
2274 | /* | | 2203 | /* |
2275 | * XXX | | 2204 | * XXX |
2276 | * This code isn't correct because pin 2 and 3 are located | | 2205 | * This code isn't correct because pin 2 and 3 are located |
2277 | * in different position on newer chips. Check all datasheet. | | 2206 | * in different position on newer chips. Check all datasheet. |
2278 | * | | 2207 | * |
2279 | * Until resolve this problem, check if a chip < 82580 | | 2208 | * Until resolve this problem, check if a chip < 82580 |
2280 | */ | | 2209 | */ |
2281 | if (sc->sc_type <= WM_T_82580) { | | 2210 | if (sc->sc_type <= WM_T_82580) { |
2282 | if (sc->sc_type >= WM_T_82544) { | | 2211 | if (sc->sc_type >= WM_T_82544) { |
2283 | sc->sc_ctrl |= | | 2212 | sc->sc_ctrl |= |
2284 | ((swdpin >> NVM_SWDPIN_SWDPIO_SHIFT) & 0xf) << | | 2213 | ((swdpin >> NVM_SWDPIN_SWDPIO_SHIFT) & 0xf) << |
2285 | CTRL_SWDPIO_SHIFT; | | 2214 | CTRL_SWDPIO_SHIFT; |
2286 | sc->sc_ctrl |= | | 2215 | sc->sc_ctrl |= |
2287 | ((swdpin >> NVM_SWDPIN_SWDPIN_SHIFT) & 0xf) << | | 2216 | ((swdpin >> NVM_SWDPIN_SWDPIN_SHIFT) & 0xf) << |
2288 | CTRL_SWDPINS_SHIFT; | | 2217 | CTRL_SWDPINS_SHIFT; |
2289 | } else { | | 2218 | } else { |
2290 | sc->sc_ctrl |= | | 2219 | sc->sc_ctrl |= |
2291 | ((cfg1 >> NVM_CFG1_SWDPIO_SHIFT) & 0xf) << | | 2220 | ((cfg1 >> NVM_CFG1_SWDPIO_SHIFT) & 0xf) << |
2292 | CTRL_SWDPIO_SHIFT; | | 2221 | CTRL_SWDPIO_SHIFT; |
2293 | } | | 2222 | } |
2294 | } | | 2223 | } |
2295 | | | 2224 | |
2296 | /* XXX For other than 82580? */ | | 2225 | /* XXX For other than 82580? */ |
2297 | if (sc->sc_type == WM_T_82580) { | | 2226 | if (sc->sc_type == WM_T_82580) { |
2298 | wm_nvm_read(sc, NVM_OFF_CFG3_PORTA, 1, &nvmword); | | 2227 | wm_nvm_read(sc, NVM_OFF_CFG3_PORTA, 1, &nvmword); |
2299 | printf("CFG3 = %08x\n", (uint32_t)nvmword); | | 2228 | printf("CFG3 = %08x\n", (uint32_t)nvmword); |
2300 | if (nvmword & __BIT(13)) { | | 2229 | if (nvmword & __BIT(13)) { |
2301 | printf("SET ILOS\n"); | | 2230 | printf("SET ILOS\n"); |
2302 | sc->sc_ctrl |= CTRL_ILOS; | | 2231 | sc->sc_ctrl |= CTRL_ILOS; |
2303 | } | | 2232 | } |
2304 | } | | 2233 | } |
2305 | | | 2234 | |
2306 | #if 0 | | 2235 | #if 0 |
2307 | if (sc->sc_type >= WM_T_82544) { | | 2236 | if (sc->sc_type >= WM_T_82544) { |
2308 | if (cfg1 & NVM_CFG1_IPS0) | | 2237 | if (cfg1 & NVM_CFG1_IPS0) |
2309 | sc->sc_ctrl_ext |= CTRL_EXT_IPS; | | 2238 | sc->sc_ctrl_ext |= CTRL_EXT_IPS; |
2310 | if (cfg1 & NVM_CFG1_IPS1) | | 2239 | if (cfg1 & NVM_CFG1_IPS1) |
2311 | sc->sc_ctrl_ext |= CTRL_EXT_IPS1; | | 2240 | sc->sc_ctrl_ext |= CTRL_EXT_IPS1; |
2312 | sc->sc_ctrl_ext |= | | 2241 | sc->sc_ctrl_ext |= |
2313 | ((swdpin >> (NVM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) << | | 2242 | ((swdpin >> (NVM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) << |
2314 | CTRL_EXT_SWDPIO_SHIFT; | | 2243 | CTRL_EXT_SWDPIO_SHIFT; |
2315 | sc->sc_ctrl_ext |= | | 2244 | sc->sc_ctrl_ext |= |
2316 | ((swdpin >> (NVM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) << | | 2245 | ((swdpin >> (NVM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) << |
2317 | CTRL_EXT_SWDPINS_SHIFT; | | 2246 | CTRL_EXT_SWDPINS_SHIFT; |
2318 | } else { | | 2247 | } else { |
2319 | sc->sc_ctrl_ext |= | | 2248 | sc->sc_ctrl_ext |= |
2320 | ((cfg2 >> NVM_CFG2_SWDPIO_SHIFT) & 0xf) << | | 2249 | ((cfg2 >> NVM_CFG2_SWDPIO_SHIFT) & 0xf) << |
2321 | CTRL_EXT_SWDPIO_SHIFT; | | 2250 | CTRL_EXT_SWDPIO_SHIFT; |
2322 | } | | 2251 | } |
2323 | #endif | | 2252 | #endif |
2324 | | | 2253 | |
2325 | CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); | | 2254 | CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); |
2326 | #if 0 | | 2255 | #if 0 |
2327 | CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); | | 2256 | CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); |
2328 | #endif | | 2257 | #endif |
2329 | | | 2258 | |
2330 | if (sc->sc_type == WM_T_PCH) { | | 2259 | if (sc->sc_type == WM_T_PCH) { |
2331 | uint16_t val; | | 2260 | uint16_t val; |
2332 | | | 2261 | |
2333 | /* Save the NVM K1 bit setting */ | | 2262 | /* Save the NVM K1 bit setting */ |
2334 | wm_nvm_read(sc, NVM_OFF_K1_CONFIG, 1, &val); | | 2263 | wm_nvm_read(sc, NVM_OFF_K1_CONFIG, 1, &val); |
2335 | | | 2264 | |
2336 | if ((val & NVM_K1_CONFIG_ENABLE) != 0) | | 2265 | if ((val & NVM_K1_CONFIG_ENABLE) != 0) |
2337 | sc->sc_nvm_k1_enabled = 1; | | 2266 | sc->sc_nvm_k1_enabled = 1; |
2338 | else | | 2267 | else |
2339 | sc->sc_nvm_k1_enabled = 0; | | 2268 | sc->sc_nvm_k1_enabled = 0; |
2340 | } | | 2269 | } |
2341 | | | 2270 | |
2342 | /* | | 2271 | /* |
2343 | * Determine if we're TBI,GMII or SGMII mode, and initialize the | | 2272 | * Determine if we're TBI,GMII or SGMII mode, and initialize the |
2344 | * media structures accordingly. | | 2273 | * media structures accordingly. |
2345 | */ | | 2274 | */ |
2346 | if (sc->sc_type == WM_T_ICH8 || sc->sc_type == WM_T_ICH9 | | 2275 | if (sc->sc_type == WM_T_ICH8 || sc->sc_type == WM_T_ICH9 |
2347 | || sc->sc_type == WM_T_ICH10 || sc->sc_type == WM_T_PCH | | 2276 | || sc->sc_type == WM_T_ICH10 || sc->sc_type == WM_T_PCH |
2348 | || sc->sc_type == WM_T_PCH2 || sc->sc_type == WM_T_PCH_LPT | | 2277 | || sc->sc_type == WM_T_PCH2 || sc->sc_type == WM_T_PCH_LPT |
2349 | || sc->sc_type == WM_T_82573 | | 2278 | || sc->sc_type == WM_T_82573 |
2350 | || sc->sc_type == WM_T_82574 || sc->sc_type == WM_T_82583) { | | 2279 | || sc->sc_type == WM_T_82574 || sc->sc_type == WM_T_82583) { |
2351 | /* STATUS_TBIMODE reserved/reused, can't rely on it */ | | 2280 | /* STATUS_TBIMODE reserved/reused, can't rely on it */ |
2352 | wm_gmii_mediainit(sc, wmp->wmp_product); | | 2281 | wm_gmii_mediainit(sc, wmp->wmp_product); |
2353 | } else if (sc->sc_type < WM_T_82543 || | | 2282 | } else if (sc->sc_type < WM_T_82543 || |
2354 | (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) { | | 2283 | (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) { |
2355 | if (sc->sc_mediatype == WM_MEDIATYPE_COPPER) { | | 2284 | if (sc->sc_mediatype == WM_MEDIATYPE_COPPER) { |
2356 | aprint_error_dev(sc->sc_dev, | | 2285 | aprint_error_dev(sc->sc_dev, |
2357 | "WARNING: TBIMODE set on 1000BASE-T product!\n"); | | 2286 | "WARNING: TBIMODE set on 1000BASE-T product!\n"); |
2358 | sc->sc_mediatype = WM_MEDIATYPE_FIBER; | | 2287 | sc->sc_mediatype = WM_MEDIATYPE_FIBER; |
2359 | } | | 2288 | } |
2360 | wm_tbi_mediainit(sc); | | 2289 | wm_tbi_mediainit(sc); |
2361 | } else { | | 2290 | } else { |
2362 | switch (sc->sc_type) { | | 2291 | switch (sc->sc_type) { |
2363 | case WM_T_82575: | | 2292 | case WM_T_82575: |
2364 | case WM_T_82576: | | 2293 | case WM_T_82576: |
2365 | case WM_T_82580: | | 2294 | case WM_T_82580: |
2366 | case WM_T_I350: | | 2295 | case WM_T_I350: |
2367 | case WM_T_I354: | | 2296 | case WM_T_I354: |
2368 | case WM_T_I210: | | 2297 | case WM_T_I210: |
2369 | case WM_T_I211: | | 2298 | case WM_T_I211: |
2370 | reg = CSR_READ(sc, WMREG_CTRL_EXT); | | 2299 | reg = CSR_READ(sc, WMREG_CTRL_EXT); |
2371 | link_mode = reg & CTRL_EXT_LINK_MODE_MASK; | | 2300 | link_mode = reg & CTRL_EXT_LINK_MODE_MASK; |
2372 | switch (link_mode) { | | 2301 | switch (link_mode) { |
2373 | case CTRL_EXT_LINK_MODE_1000KX: | | 2302 | case CTRL_EXT_LINK_MODE_1000KX: |
2374 | aprint_verbose_dev(sc->sc_dev, "1000KX\n"); | | 2303 | aprint_verbose_dev(sc->sc_dev, "1000KX\n"); |
2375 | sc->sc_mediatype = WM_MEDIATYPE_SERDES; | | 2304 | sc->sc_mediatype = WM_MEDIATYPE_SERDES; |
2376 | break; | | 2305 | break; |
2377 | case CTRL_EXT_LINK_MODE_SGMII: | | 2306 | case CTRL_EXT_LINK_MODE_SGMII: |
2378 | if (wm_sgmii_uses_mdio(sc)) { | | 2307 | if (wm_sgmii_uses_mdio(sc)) { |
2379 | aprint_verbose_dev(sc->sc_dev, | | 2308 | aprint_verbose_dev(sc->sc_dev, |
2380 | "SGMII(MDIO)\n"); | | 2309 | "SGMII(MDIO)\n"); |
2381 | sc->sc_flags |= WM_F_SGMII; | | 2310 | sc->sc_flags |= WM_F_SGMII; |
2382 | sc->sc_mediatype = WM_MEDIATYPE_COPPER; | | 2311 | sc->sc_mediatype = WM_MEDIATYPE_COPPER; |
2383 | break; | | 2312 | break; |
2384 | } | | 2313 | } |
2385 | aprint_verbose_dev(sc->sc_dev, "SGMII(I2C)\n"); | | 2314 | aprint_verbose_dev(sc->sc_dev, "SGMII(I2C)\n"); |
2386 | /*FALLTHROUGH*/ | | 2315 | /*FALLTHROUGH*/ |
2387 | case CTRL_EXT_LINK_MODE_PCIE_SERDES: | | 2316 | case CTRL_EXT_LINK_MODE_PCIE_SERDES: |
2388 | sc->sc_mediatype = wm_sfp_get_media_type(sc); | | 2317 | sc->sc_mediatype = wm_sfp_get_media_type(sc); |
2389 | if (sc->sc_mediatype == WM_MEDIATYPE_UNKNOWN) { | | 2318 | if (sc->sc_mediatype == WM_MEDIATYPE_UNKNOWN) { |
2390 | if (link_mode | | 2319 | if (link_mode |
2391 | == CTRL_EXT_LINK_MODE_SGMII) { | | 2320 | == CTRL_EXT_LINK_MODE_SGMII) { |
2392 | sc->sc_mediatype | | 2321 | sc->sc_mediatype |
2393 | = WM_MEDIATYPE_COPPER; | | 2322 | = WM_MEDIATYPE_COPPER; |
2394 | sc->sc_flags |= WM_F_SGMII; | | 2323 | sc->sc_flags |= WM_F_SGMII; |
2395 | } else { | | 2324 | } else { |
2396 | sc->sc_mediatype | | 2325 | sc->sc_mediatype |
2397 | = WM_MEDIATYPE_SERDES; | | 2326 | = WM_MEDIATYPE_SERDES; |
2398 | aprint_verbose_dev(sc->sc_dev, | | 2327 | aprint_verbose_dev(sc->sc_dev, |
2399 | "SERDES\n"); | | 2328 | "SERDES\n"); |
2400 | } | | 2329 | } |
2401 | break; | | 2330 | break; |
2402 | } | | 2331 | } |
2403 | if (sc->sc_mediatype == WM_MEDIATYPE_SERDES) | | 2332 | if (sc->sc_mediatype == WM_MEDIATYPE_SERDES) |
2404 | aprint_verbose_dev(sc->sc_dev, | | 2333 | aprint_verbose_dev(sc->sc_dev, |
2405 | "SERDES\n"); | | 2334 | "SERDES\n"); |
2406 | | | 2335 | |
2407 | /* Change current link mode setting */ | | 2336 | /* Change current link mode setting */ |
2408 | reg &= ~CTRL_EXT_LINK_MODE_MASK; | | 2337 | reg &= ~CTRL_EXT_LINK_MODE_MASK; |
2409 | switch (sc->sc_mediatype) { | | 2338 | switch (sc->sc_mediatype) { |
2410 | case WM_MEDIATYPE_COPPER: | | 2339 | case WM_MEDIATYPE_COPPER: |
2411 | reg |= CTRL_EXT_LINK_MODE_SGMII; | | 2340 | reg |= CTRL_EXT_LINK_MODE_SGMII; |
2412 | break; | | 2341 | break; |
2413 | case WM_MEDIATYPE_SERDES: | | 2342 | case WM_MEDIATYPE_SERDES: |
2414 | reg |= CTRL_EXT_LINK_MODE_PCIE_SERDES; | | 2343 | reg |= CTRL_EXT_LINK_MODE_PCIE_SERDES; |
2415 | break; | | 2344 | break; |
2416 | default: | | 2345 | default: |
2417 | break; | | 2346 | break; |
2418 | } | | 2347 | } |
2419 | CSR_WRITE(sc, WMREG_CTRL_EXT, reg); | | 2348 | CSR_WRITE(sc, WMREG_CTRL_EXT, reg); |
2420 | break; | | 2349 | break; |
2421 | case CTRL_EXT_LINK_MODE_GMII: | | 2350 | case CTRL_EXT_LINK_MODE_GMII: |
2422 | default: | | 2351 | default: |
2423 | aprint_verbose_dev(sc->sc_dev, "Copper\n"); | | 2352 | aprint_verbose_dev(sc->sc_dev, "Copper\n"); |
2424 | sc->sc_mediatype = WM_MEDIATYPE_COPPER; | | 2353 | sc->sc_mediatype = WM_MEDIATYPE_COPPER; |
2425 | break; | | 2354 | break; |
2426 | } | | 2355 | } |
2427 | | | 2356 | |
2428 | reg &= ~CTRL_EXT_I2C_ENA; | | 2357 | reg &= ~CTRL_EXT_I2C_ENA; |
2429 | if ((sc->sc_flags & WM_F_SGMII) != 0) | | 2358 | if ((sc->sc_flags & WM_F_SGMII) != 0) |
2430 | reg |= CTRL_EXT_I2C_ENA; | | 2359 | reg |= CTRL_EXT_I2C_ENA; |
2431 | else | | 2360 | else |
2432 | reg &= ~CTRL_EXT_I2C_ENA; | | 2361 | reg &= ~CTRL_EXT_I2C_ENA; |
2433 | CSR_WRITE(sc, WMREG_CTRL_EXT, reg); | | 2362 | CSR_WRITE(sc, WMREG_CTRL_EXT, reg); |
2434 | | | 2363 | |
2435 | if (sc->sc_mediatype == WM_MEDIATYPE_COPPER) | | 2364 | if (sc->sc_mediatype == WM_MEDIATYPE_COPPER) |
2436 | wm_gmii_mediainit(sc, wmp->wmp_product); | | 2365 | wm_gmii_mediainit(sc, wmp->wmp_product); |
2437 | else | | 2366 | else |
2438 | wm_tbi_mediainit(sc); | | 2367 | wm_tbi_mediainit(sc); |
2439 | break; | | 2368 | break; |
2440 | default: | | 2369 | default: |
2441 | if (sc->sc_mediatype == WM_MEDIATYPE_FIBER) | | 2370 | if (sc->sc_mediatype == WM_MEDIATYPE_FIBER) |
2442 | aprint_error_dev(sc->sc_dev, | | 2371 | aprint_error_dev(sc->sc_dev, |
2443 | "WARNING: TBIMODE clear on 1000BASE-X product!\n"); | | 2372 | "WARNING: TBIMODE clear on 1000BASE-X product!\n"); |
2444 | sc->sc_mediatype = WM_MEDIATYPE_COPPER; | | 2373 | sc->sc_mediatype = WM_MEDIATYPE_COPPER; |
2445 | wm_gmii_mediainit(sc, wmp->wmp_product); | | 2374 | wm_gmii_mediainit(sc, wmp->wmp_product); |
2446 | } | | 2375 | } |
2447 | } | | 2376 | } |
2448 | | | 2377 | |
2449 | ifp = &sc->sc_ethercom.ec_if; | | 2378 | ifp = &sc->sc_ethercom.ec_if; |
2450 | xname = device_xname(sc->sc_dev); | | 2379 | xname = device_xname(sc->sc_dev); |
2451 | strlcpy(ifp->if_xname, xname, IFNAMSIZ); | | 2380 | strlcpy(ifp->if_xname, xname, IFNAMSIZ); |
2452 | ifp->if_softc = sc; | | 2381 | ifp->if_softc = sc; |
2453 | ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; | | 2382 | ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; |
2454 | ifp->if_ioctl = wm_ioctl; | | 2383 | ifp->if_ioctl = wm_ioctl; |
2455 | if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) | | 2384 | if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) |
2456 | ifp->if_start = wm_nq_start; | | 2385 | ifp->if_start = wm_nq_start; |
2457 | else | | 2386 | else |
2458 | ifp->if_start = wm_start; | | 2387 | ifp->if_start = wm_start; |
2459 | ifp->if_watchdog = wm_watchdog; | | 2388 | ifp->if_watchdog = wm_watchdog; |
2460 | ifp->if_init = wm_init; | | 2389 | ifp->if_init = wm_init; |
2461 | ifp->if_stop = wm_stop; | | 2390 | ifp->if_stop = wm_stop; |
2462 | IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN)); | | 2391 | IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN)); |
2463 | IFQ_SET_READY(&ifp->if_snd); | | 2392 | IFQ_SET_READY(&ifp->if_snd); |
2464 | | | 2393 | |
2465 | /* Check for jumbo frame */ | | 2394 | /* Check for jumbo frame */ |
2466 | switch (sc->sc_type) { | | 2395 | switch (sc->sc_type) { |
2467 | case WM_T_82573: | | 2396 | case WM_T_82573: |
2468 | /* XXX limited to 9234 if ASPM is disabled */ | | 2397 | /* XXX limited to 9234 if ASPM is disabled */ |
2469 | wm_nvm_read(sc, NVM_OFF_INIT_3GIO_3, 1, &nvmword); | | 2398 | wm_nvm_read(sc, NVM_OFF_INIT_3GIO_3, 1, &nvmword); |
2470 | if ((nvmword & NVM_3GIO_3_ASPM_MASK) != 0) | | 2399 | if ((nvmword & NVM_3GIO_3_ASPM_MASK) != 0) |
2471 | sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; | | 2400 | sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; |
2472 | break; | | 2401 | break; |
2473 | case WM_T_82571: | | 2402 | case WM_T_82571: |
2474 | case WM_T_82572: | | 2403 | case WM_T_82572: |
2475 | case WM_T_82574: | | 2404 | case WM_T_82574: |
2476 | case WM_T_82575: | | 2405 | case WM_T_82575: |
2477 | case WM_T_82576: | | 2406 | case WM_T_82576: |
2478 | case WM_T_82580: | | 2407 | case WM_T_82580: |
2479 | case WM_T_I350: | | 2408 | case WM_T_I350: |
2480 | case WM_T_I354: /* XXXX ok? */ | | 2409 | case WM_T_I354: /* XXXX ok? */ |
2481 | case WM_T_I210: | | 2410 | case WM_T_I210: |
2482 | case WM_T_I211: | | 2411 | case WM_T_I211: |
2483 | case WM_T_80003: | | 2412 | case WM_T_80003: |
2484 | case WM_T_ICH9: | | 2413 | case WM_T_ICH9: |
2485 | case WM_T_ICH10: | | 2414 | case WM_T_ICH10: |
2486 | case WM_T_PCH2: /* PCH2 supports 9K frame size */ | | 2415 | case WM_T_PCH2: /* PCH2 supports 9K frame size */ |
2487 | case WM_T_PCH_LPT: | | 2416 | case WM_T_PCH_LPT: |
2488 | /* XXX limited to 9234 */ | | 2417 | /* XXX limited to 9234 */ |
2489 | sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; | | 2418 | sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; |
2490 | break; | | 2419 | break; |
2491 | case WM_T_PCH: | | 2420 | case WM_T_PCH: |
2492 | /* XXX limited to 4096 */ | | 2421 | /* XXX limited to 4096 */ |
2493 | sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; | | 2422 | sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; |
2494 | break; | | 2423 | break; |
2495 | case WM_T_82542_2_0: | | 2424 | case WM_T_82542_2_0: |
2496 | case WM_T_82542_2_1: | | 2425 | case WM_T_82542_2_1: |
2497 | case WM_T_82583: | | 2426 | case WM_T_82583: |
2498 | case WM_T_ICH8: | | 2427 | case WM_T_ICH8: |
2499 | /* No support for jumbo frame */ | | 2428 | /* No support for jumbo frame */ |
2500 | break; | | 2429 | break; |
2501 | default: | | 2430 | default: |
2502 | /* ETHER_MAX_LEN_JUMBO */ | | 2431 | /* ETHER_MAX_LEN_JUMBO */ |
2503 | sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; | | 2432 | sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; |
2504 | break; | | 2433 | break; |
2505 | } | | 2434 | } |
2506 | | | 2435 | |
2507 | /* If we're a i82543 or greater, we can support VLANs. */ | | 2436 | /* If we're a i82543 or greater, we can support VLANs. */ |
2508 | if (sc->sc_type >= WM_T_82543) | | 2437 | if (sc->sc_type >= WM_T_82543) |
2509 | sc->sc_ethercom.ec_capabilities |= | | 2438 | sc->sc_ethercom.ec_capabilities |= |
2510 | ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; | | 2439 | ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; |
2511 | | | 2440 | |
2512 | /* | | 2441 | /* |
2513 | * We can perform TCPv4 and UDPv4 checkums in-bound. Only | | 2442 | * We can perform TCPv4 and UDPv4 checkums in-bound. Only |
2514 | * on i82543 and later. | | 2443 | * on i82543 and later. |
2515 | */ | | 2444 | */ |
2516 | if (sc->sc_type >= WM_T_82543) { | | 2445 | if (sc->sc_type >= WM_T_82543) { |
2517 | ifp->if_capabilities |= | | 2446 | ifp->if_capabilities |= |
2518 | IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | | | 2447 | IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | |
2519 | IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | | | 2448 | IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | |
2520 | IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | | | 2449 | IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | |
2521 | IFCAP_CSUM_TCPv6_Tx | | | 2450 | IFCAP_CSUM_TCPv6_Tx | |
2522 | IFCAP_CSUM_UDPv6_Tx; | | 2451 | IFCAP_CSUM_UDPv6_Tx; |
2523 | } | | 2452 | } |
2524 | | | 2453 | |
2525 | /* | | 2454 | /* |
2526 | * XXXyamt: i'm not sure which chips support RXCSUM_IPV6OFL. | | 2455 | * XXXyamt: i'm not sure which chips support RXCSUM_IPV6OFL. |
2527 | * | | 2456 | * |
2528 | * 82541GI (8086:1076) ... no | | 2457 | * 82541GI (8086:1076) ... no |
2529 | * 82572EI (8086:10b9) ... yes | | 2458 | * 82572EI (8086:10b9) ... yes |
2530 | */ | | 2459 | */ |
2531 | if (sc->sc_type >= WM_T_82571) { | | 2460 | if (sc->sc_type >= WM_T_82571) { |
2532 | ifp->if_capabilities |= | | 2461 | ifp->if_capabilities |= |
2533 | IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; | | 2462 | IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; |
2534 | } | | 2463 | } |
2535 | | | 2464 | |
2536 | /* | | 2465 | /* |
2537 | * If we're a i82544 or greater (except i82547), we can do | | 2466 | * If we're a i82544 or greater (except i82547), we can do |
2538 | * TCP segmentation offload. | | 2467 | * TCP segmentation offload. |
2539 | */ | | 2468 | */ |
2540 | if (sc->sc_type >= WM_T_82544 && sc->sc_type != WM_T_82547) { | | 2469 | if (sc->sc_type >= WM_T_82544 && sc->sc_type != WM_T_82547) { |
2541 | ifp->if_capabilities |= IFCAP_TSOv4; | | 2470 | ifp->if_capabilities |= IFCAP_TSOv4; |
2542 | } | | 2471 | } |
2543 | | | 2472 | |
2544 | if (sc->sc_type >= WM_T_82571) { | | 2473 | if (sc->sc_type >= WM_T_82571) { |
2545 | ifp->if_capabilities |= IFCAP_TSOv6; | | 2474 | ifp->if_capabilities |= IFCAP_TSOv6; |
2546 | } | | 2475 | } |
2547 | | | 2476 | |
2548 | #ifdef WM_MPSAFE | | 2477 | #ifdef WM_MPSAFE |
2549 | sc->sc_core_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET); | | 2478 | sc->sc_core_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET); |
2550 | #else | | 2479 | #else |
2551 | sc->sc_core_lock = NULL; | | 2480 | sc->sc_core_lock = NULL; |
2552 | #endif | | 2481 | #endif |
2553 | | | 2482 | |
2554 | /* Attach the interface. */ | | 2483 | /* Attach the interface. */ |
2555 | if_attach(ifp); | | 2484 | if_attach(ifp); |
2556 | ether_ifattach(ifp, enaddr); | | 2485 | ether_ifattach(ifp, enaddr); |
2557 | ether_set_ifflags_cb(&sc->sc_ethercom, wm_ifflags_cb); | | 2486 | ether_set_ifflags_cb(&sc->sc_ethercom, wm_ifflags_cb); |
2558 | rnd_attach_source(&sc->rnd_source, xname, RND_TYPE_NET, | | 2487 | rnd_attach_source(&sc->rnd_source, xname, RND_TYPE_NET, |
2559 | RND_FLAG_DEFAULT); | | 2488 | RND_FLAG_DEFAULT); |
2560 | | | 2489 | |
2561 | #ifdef WM_EVENT_COUNTERS | | 2490 | #ifdef WM_EVENT_COUNTERS |
2562 | /* Attach event counters. */ | | 2491 | /* Attach event counters. */ |
2563 | evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, | | 2492 | evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, |
2564 | NULL, xname, "txsstall"); | | 2493 | NULL, xname, "txsstall"); |
2565 | evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, | | 2494 | evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, |
2566 | NULL, xname, "txdstall"); | | 2495 | NULL, xname, "txdstall"); |
2567 | evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC, | | 2496 | evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC, |
2568 | NULL, xname, "txfifo_stall"); | | 2497 | NULL, xname, "txfifo_stall"); |
2569 | evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, | | 2498 | evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, |
2570 | NULL, xname, "txdw"); | | 2499 | NULL, xname, "txdw"); |
2571 | evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, | | 2500 | evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, |
2572 | NULL, xname, "txqe"); | | 2501 | NULL, xname, "txqe"); |
2573 | evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, | | 2502 | evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, |
2574 | NULL, xname, "rxintr"); | | 2503 | NULL, xname, "rxintr"); |
2575 | evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, | | 2504 | evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, |
2576 | NULL, xname, "linkintr"); | | 2505 | NULL, xname, "linkintr"); |
2577 | | | 2506 | |
2578 | evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, | | 2507 | evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, |
2579 | NULL, xname, "rxipsum"); | | 2508 | NULL, xname, "rxipsum"); |
2580 | evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, | | 2509 | evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, |
2581 | NULL, xname, "rxtusum"); | | 2510 | NULL, xname, "rxtusum"); |
2582 | evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, | | 2511 | evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, |
2583 | NULL, xname, "txipsum"); | | 2512 | NULL, xname, "txipsum"); |
2584 | evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, | | 2513 | evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, |
2585 | NULL, xname, "txtusum"); | | 2514 | NULL, xname, "txtusum"); |
2586 | evcnt_attach_dynamic(&sc->sc_ev_txtusum6, EVCNT_TYPE_MISC, | | 2515 | evcnt_attach_dynamic(&sc->sc_ev_txtusum6, EVCNT_TYPE_MISC, |
2587 | NULL, xname, "txtusum6"); | | 2516 | NULL, xname, "txtusum6"); |
2588 | | | 2517 | |
2589 | evcnt_attach_dynamic(&sc->sc_ev_txtso, EVCNT_TYPE_MISC, | | 2518 | evcnt_attach_dynamic(&sc->sc_ev_txtso, EVCNT_TYPE_MISC, |
2590 | NULL, xname, "txtso"); | | 2519 | NULL, xname, "txtso"); |
2591 | evcnt_attach_dynamic(&sc->sc_ev_txtso6, EVCNT_TYPE_MISC, | | 2520 | evcnt_attach_dynamic(&sc->sc_ev_txtso6, EVCNT_TYPE_MISC, |
2592 | NULL, xname, "txtso6"); | | 2521 | NULL, xname, "txtso6"); |
2593 | evcnt_attach_dynamic(&sc->sc_ev_txtsopain, EVCNT_TYPE_MISC, | | 2522 | evcnt_attach_dynamic(&sc->sc_ev_txtsopain, EVCNT_TYPE_MISC, |
2594 | NULL, xname, "txtsopain"); | | 2523 | NULL, xname, "txtsopain"); |
2595 | | | 2524 | |
2596 | for (i = 0; i < WM_NTXSEGS; i++) { | | 2525 | for (i = 0; i < WM_NTXSEGS; i++) { |
2597 | snprintf(wm_txseg_evcnt_names[i], | | 2526 | snprintf(wm_txseg_evcnt_names[i], |
2598 | sizeof(wm_txseg_evcnt_names[i]), "txseg%d", i); | | 2527 | sizeof(wm_txseg_evcnt_names[i]), "txseg%d", i); |
2599 | evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, | | 2528 | evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, |
2600 | NULL, xname, wm_txseg_evcnt_names[i]); | | 2529 | NULL, xname, wm_txseg_evcnt_names[i]); |
2601 | } | | 2530 | } |
2602 | | | 2531 | |
2603 | evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, | | 2532 | evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, |
2604 | NULL, xname, "txdrop"); | | 2533 | NULL, xname, "txdrop"); |
2605 | | | 2534 | |
2606 | evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, | | 2535 | evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, |
2607 | NULL, xname, "tu"); | | 2536 | NULL, xname, "tu"); |
2608 | | | 2537 | |
2609 | evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC, | | 2538 | evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC, |
2610 | NULL, xname, "tx_xoff"); | | 2539 | NULL, xname, "tx_xoff"); |
2611 | evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC, | | 2540 | evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC, |
2612 | NULL, xname, "tx_xon"); | | 2541 | NULL, xname, "tx_xon"); |
2613 | evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC, | | 2542 | evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC, |
2614 | NULL, xname, "rx_xoff"); | | 2543 | NULL, xname, "rx_xoff"); |
2615 | evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC, | | 2544 | evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC, |
2616 | NULL, xname, "rx_xon"); | | 2545 | NULL, xname, "rx_xon"); |
2617 | evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC, | | 2546 | evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC, |
2618 | NULL, xname, "rx_macctl"); | | 2547 | NULL, xname, "rx_macctl"); |
2619 | #endif /* WM_EVENT_COUNTERS */ | | 2548 | #endif /* WM_EVENT_COUNTERS */ |
2620 | | | 2549 | |
2621 | if (pmf_device_register(self, wm_suspend, wm_resume)) | | 2550 | if (pmf_device_register(self, wm_suspend, wm_resume)) |
2622 | pmf_class_network_register(self, ifp); | | 2551 | pmf_class_network_register(self, ifp); |
2623 | else | | 2552 | else |
2624 | aprint_error_dev(self, "couldn't establish power handler\n"); | | 2553 | aprint_error_dev(self, "couldn't establish power handler\n"); |
2625 | | | 2554 | |
2626 | sc->sc_flags |= WM_F_ATTACHED; | | 2555 | sc->sc_flags |= WM_F_ATTACHED; |
2627 | out: | | 2556 | out: |
2628 | return; | | 2557 | return; |
2629 | } | | 2558 | } |
2630 | | | 2559 | |
2631 | /* The detach function (ca_detach) */ | | 2560 | /* The detach function (ca_detach) */ |
2632 | static int | | 2561 | static int |
2633 | wm_detach(device_t self, int flags __unused) | | 2562 | wm_detach(device_t self, int flags __unused) |
2634 | { | | 2563 | { |
2635 | struct wm_softc *sc = device_private(self); | | 2564 | struct wm_softc *sc = device_private(self); |
2636 | struct wm_rxqueue *rxq = sc->sc_rxq; | | 2565 | struct wm_rxqueue *rxq = sc->sc_rxq; |
2637 | struct ifnet *ifp = &sc->sc_ethercom.ec_if; | | 2566 | struct ifnet *ifp = &sc->sc_ethercom.ec_if; |
2638 | int i; | | 2567 | int i; |
2639 | #ifndef WM_MPSAFE | | 2568 | #ifndef WM_MPSAFE |
2640 | int s; | | 2569 | int s; |
2641 | #endif | | 2570 | #endif |
2642 | | | 2571 | |
2643 | if ((sc->sc_flags & WM_F_ATTACHED) == 0) | | 2572 | if ((sc->sc_flags & WM_F_ATTACHED) == 0) |
2644 | return 0; | | 2573 | return 0; |
2645 | | | 2574 | |
2646 | #ifndef WM_MPSAFE | | 2575 | #ifndef WM_MPSAFE |
2647 | s = splnet(); | | 2576 | s = splnet(); |
2648 | #endif | | 2577 | #endif |
2649 | /* Stop the interface. Callouts are stopped in it. */ | | 2578 | /* Stop the interface. Callouts are stopped in it. */ |
2650 | wm_stop(ifp, 1); | | 2579 | wm_stop(ifp, 1); |
2651 | | | 2580 | |
2652 | #ifndef WM_MPSAFE | | 2581 | #ifndef WM_MPSAFE |
2653 | splx(s); | | 2582 | splx(s); |
2654 | #endif | | 2583 | #endif |
2655 | | | 2584 | |
2656 | pmf_device_deregister(self); | | 2585 | pmf_device_deregister(self); |
2657 | | | 2586 | |
2658 | /* Tell the firmware about the release */ | | 2587 | /* Tell the firmware about the release */ |
2659 | WM_CORE_LOCK(sc); | | 2588 | WM_CORE_LOCK(sc); |
2660 | wm_release_manageability(sc); | | 2589 | wm_release_manageability(sc); |
2661 | wm_release_hw_control(sc); | | 2590 | wm_release_hw_control(sc); |
2662 | WM_CORE_UNLOCK(sc); | | 2591 | WM_CORE_UNLOCK(sc); |
2663 | | | 2592 | |
2664 | mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); | | 2593 | mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); |
2665 | | | 2594 | |
2666 | /* Delete all remaining media. */ | | 2595 | /* Delete all remaining media. */ |
2667 | ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); | | 2596 | ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); |
2668 | | | 2597 | |
2669 | ether_ifdetach(ifp); | | 2598 | ether_ifdetach(ifp); |
2670 | if_detach(ifp); | | 2599 | if_detach(ifp); |
2671 | | | 2600 | |
2672 | | | 2601 | |
2673 | /* Unload RX dmamaps and free mbufs */ | | 2602 | /* Unload RX dmamaps and free mbufs */ |
2674 | WM_RX_LOCK(rxq); | | 2603 | WM_RX_LOCK(rxq); |
2675 | wm_rxdrain(sc); | | 2604 | wm_rxdrain(sc); |
2676 | WM_RX_UNLOCK(rxq); | | 2605 | WM_RX_UNLOCK(rxq); |
2677 | /* Must unlock here */ | | 2606 | /* Must unlock here */ |
2678 | | | 2607 | |
2679 | wm_free_txrx_queues(sc); | | 2608 | wm_free_txrx_queues(sc); |
2680 | | | 2609 | |
2681 | /* Disestablish the interrupt handler */ | | 2610 | /* Disestablish the interrupt handler */ |
2682 | for (i = 0; i < sc->sc_nintrs; i++) { | | 2611 | for (i = 0; i < sc->sc_nintrs; i++) { |
2683 | if (sc->sc_ihs[i] != NULL) { | | 2612 | if (sc->sc_ihs[i] != NULL) { |
2684 | pci_intr_disestablish(sc->sc_pc, sc->sc_ihs[i]); | | 2613 | pci_intr_disestablish(sc->sc_pc, sc->sc_ihs[i]); |
2685 | sc->sc_ihs[i] = NULL; | | 2614 | sc->sc_ihs[i] = NULL; |
2686 | } | | 2615 | } |
2687 | } | | 2616 | } |
2688 | #ifdef WM_MSI_MSIX | | 2617 | #ifdef WM_MSI_MSIX |
2689 | pci_intr_release(sc->sc_pc, sc->sc_intrs, sc->sc_nintrs); | | 2618 | pci_intr_release(sc->sc_pc, sc->sc_intrs, sc->sc_nintrs); |
2690 | #endif /* WM_MSI_MSIX */ | | 2619 | #endif /* WM_MSI_MSIX */ |
2691 | | | 2620 | |
2692 | /* Unmap the registers */ | | 2621 | /* Unmap the registers */ |
2693 | if (sc->sc_ss) { | | 2622 | if (sc->sc_ss) { |
2694 | bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_ss); | | 2623 | bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_ss); |
2695 | sc->sc_ss = 0; | | 2624 | sc->sc_ss = 0; |
2696 | } | | 2625 | } |
2697 | if (sc->sc_ios) { | | 2626 | if (sc->sc_ios) { |
2698 | bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); | | 2627 | bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); |
2699 | sc->sc_ios = 0; | | 2628 | sc->sc_ios = 0; |
2700 | } | | 2629 | } |
2701 | if (sc->sc_flashs) { | | 2630 | if (sc->sc_flashs) { |
2702 | bus_space_unmap(sc->sc_flasht, sc->sc_flashh, sc->sc_flashs); | | 2631 | bus_space_unmap(sc->sc_flasht, sc->sc_flashh, sc->sc_flashs); |
2703 | sc->sc_flashs = 0; | | 2632 | sc->sc_flashs = 0; |
2704 | } | | 2633 | } |
2705 | | | 2634 | |
2706 | if (sc->sc_core_lock) | | 2635 | if (sc->sc_core_lock) |
2707 | mutex_obj_free(sc->sc_core_lock); | | 2636 | mutex_obj_free(sc->sc_core_lock); |
2708 | | | 2637 | |
2709 | return 0; | | 2638 | return 0; |
2710 | } | | 2639 | } |
2711 | | | 2640 | |
2712 | static bool | | 2641 | static bool |
2713 | wm_suspend(device_t self, const pmf_qual_t *qual) | | 2642 | wm_suspend(device_t self, const pmf_qual_t *qual) |
2714 | { | | 2643 | { |
2715 | struct wm_softc *sc = device_private(self); | | 2644 | struct wm_softc *sc = device_private(self); |
2716 | | | 2645 | |
2717 | wm_release_manageability(sc); | | 2646 | wm_release_manageability(sc); |
2718 | wm_release_hw_control(sc); | | 2647 | wm_release_hw_control(sc); |
2719 | #ifdef WM_WOL | | 2648 | #ifdef WM_WOL |
2720 | wm_enable_wakeup(sc); | | 2649 | wm_enable_wakeup(sc); |
2721 | #endif | | 2650 | #endif |
2722 | | | 2651 | |
2723 | return true; | | 2652 | return true; |
2724 | } | | 2653 | } |
2725 | | | 2654 | |
2726 | static bool | | 2655 | static bool |
2727 | wm_resume(device_t self, const pmf_qual_t *qual) | | 2656 | wm_resume(device_t self, const pmf_qual_t *qual) |
2728 | { | | 2657 | { |
2729 | struct wm_softc *sc = device_private(self); | | 2658 | struct wm_softc *sc = device_private(self); |
2730 | | | 2659 | |
2731 | wm_init_manageability(sc); | | 2660 | wm_init_manageability(sc); |
2732 | | | 2661 | |
2733 | return true; | | 2662 | return true; |
2734 | } | | 2663 | } |
2735 | | | 2664 | |
2736 | /* | | 2665 | /* |
2737 | * wm_watchdog: [ifnet interface function] | | 2666 | * wm_watchdog: [ifnet interface function] |
2738 | * | | 2667 | * |
2739 | * Watchdog timer handler. | | 2668 | * Watchdog timer handler. |
2740 | */ | | 2669 | */ |
2741 | static void | | 2670 | static void |
2742 | wm_watchdog(struct ifnet *ifp) | | 2671 | wm_watchdog(struct ifnet *ifp) |
2743 | { | | 2672 | { |
2744 | struct wm_softc *sc = ifp->if_softc; | | 2673 | struct wm_softc *sc = ifp->if_softc; |
2745 | struct wm_txqueue *txq = sc->sc_txq; | | 2674 | struct wm_txqueue *txq = sc->sc_txq; |
2746 | | | 2675 | |
2747 | /* | | 2676 | /* |
2748 | * Since we're using delayed interrupts, sweep up | | 2677 | * Since we're using delayed interrupts, sweep up |
2749 | * before we report an error. | | 2678 | * before we report an error. |
2750 | */ | | 2679 | */ |
2751 | WM_TX_LOCK(txq); | | 2680 | WM_TX_LOCK(txq); |
2752 | wm_txeof(sc); | | 2681 | wm_txeof(sc); |
2753 | WM_TX_UNLOCK(txq); | | 2682 | WM_TX_UNLOCK(txq); |
2754 | | | 2683 | |
2755 | if (txq->txq_free != WM_NTXDESC(txq)) { | | 2684 | if (txq->txq_free != WM_NTXDESC(txq)) { |
2756 | #ifdef WM_DEBUG | | 2685 | #ifdef WM_DEBUG |
2757 | int i, j; | | 2686 | int i, j; |
2758 | struct wm_txsoft *txs; | | 2687 | struct wm_txsoft *txs; |
2759 | #endif | | 2688 | #endif |
2760 | log(LOG_ERR, | | 2689 | log(LOG_ERR, |
2761 | "%s: device timeout (txfree %d txsfree %d txnext %d)\n", | | 2690 | "%s: device timeout (txfree %d txsfree %d txnext %d)\n", |
2762 | device_xname(sc->sc_dev), txq->txq_free, txq->txq_sfree, | | 2691 | device_xname(sc->sc_dev), txq->txq_free, txq->txq_sfree, |
2763 | txq->txq_next); | | 2692 | txq->txq_next); |
2764 | ifp->if_oerrors++; | | 2693 | ifp->if_oerrors++; |
2765 | #ifdef WM_DEBUG | | 2694 | #ifdef WM_DEBUG |
2766 | for (i = txq->txq_txsdirty; i != txq->txq_txsnext ; | | 2695 | for (i = txq->txq_txsdirty; i != txq->txq_txsnext ; |
2767 | i = WM_NEXTTXS(txq, i)) { | | 2696 | i = WM_NEXTTXS(txq, i)) { |
2768 | txs = &txq->txq_txsoft[i]; | | 2697 | txs = &txq->txq_txsoft[i]; |
2769 | printf("txs %d tx %d -> %d\n", | | 2698 | printf("txs %d tx %d -> %d\n", |
2770 | i, txs->txs_firstdesc, txs->txs_lastdesc); | | 2699 | i, txs->txs_firstdesc, txs->txs_lastdesc); |
2771 | for (j = txs->txs_firstdesc; ; | | 2700 | for (j = txs->txs_firstdesc; ; |
2772 | j = WM_NEXTTX(txq, j)) { | | 2701 | j = WM_NEXTTX(txq, j)) { |
| @@ -3108,1998 +3037,2104 @@ wm_mchash(struct wm_softc *sc, const uin | | | @@ -3108,1998 +3037,2104 @@ wm_mchash(struct wm_softc *sc, const uin |
3108 | if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9) | | 3037 | if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9) |
3109 | || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH) | | 3038 | || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH) |
3110 | || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) { | | 3039 | || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) { |
3111 | hash = (enaddr[4] >> ich8_lo_shift[sc->sc_mchash_type]) | | | 3040 | hash = (enaddr[4] >> ich8_lo_shift[sc->sc_mchash_type]) | |
3112 | (((uint16_t) enaddr[5]) << ich8_hi_shift[sc->sc_mchash_type]); | | 3041 | (((uint16_t) enaddr[5]) << ich8_hi_shift[sc->sc_mchash_type]); |
3113 | return (hash & 0x3ff); | | 3042 | return (hash & 0x3ff); |
3114 | } | | 3043 | } |
3115 | hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | | | 3044 | hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | |
3116 | (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); | | 3045 | (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); |
3117 | | | 3046 | |
3118 | return (hash & 0xfff); | | 3047 | return (hash & 0xfff); |
3119 | } | | 3048 | } |
3120 | | | 3049 | |
3121 | /* | | 3050 | /* |
3122 | * wm_set_filter: | | 3051 | * wm_set_filter: |
3123 | * | | 3052 | * |
3124 | * Set up the receive filter. | | 3053 | * Set up the receive filter. |
3125 | */ | | 3054 | */ |
3126 | static void | | 3055 | static void |
3127 | wm_set_filter(struct wm_softc *sc) | | 3056 | wm_set_filter(struct wm_softc *sc) |
3128 | { | | 3057 | { |
3129 | struct ethercom *ec = &sc->sc_ethercom; | | 3058 | struct ethercom *ec = &sc->sc_ethercom; |
3130 | struct ifnet *ifp = &sc->sc_ethercom.ec_if; | | 3059 | struct ifnet *ifp = &sc->sc_ethercom.ec_if; |
3131 | struct ether_multi *enm; | | 3060 | struct ether_multi *enm; |
3132 | struct ether_multistep step; | | 3061 | struct ether_multistep step; |
3133 | bus_addr_t mta_reg; | | 3062 | bus_addr_t mta_reg; |
3134 | uint32_t hash, reg, bit; | | 3063 | uint32_t hash, reg, bit; |
3135 | int i, size; | | 3064 | int i, size; |
3136 | | | 3065 | |
3137 | if (sc->sc_type >= WM_T_82544) | | 3066 | if (sc->sc_type >= WM_T_82544) |
3138 | mta_reg = WMREG_CORDOVA_MTA; | | 3067 | mta_reg = WMREG_CORDOVA_MTA; |
3139 | else | | 3068 | else |
3140 | mta_reg = WMREG_MTA; | | 3069 | mta_reg = WMREG_MTA; |
3141 | | | 3070 | |
3142 | sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); | | 3071 | sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); |
3143 | | | 3072 | |
3144 | if (ifp->if_flags & IFF_BROADCAST) | | 3073 | if (ifp->if_flags & IFF_BROADCAST) |
3145 | sc->sc_rctl |= RCTL_BAM; | | 3074 | sc->sc_rctl |= RCTL_BAM; |
3146 | if (ifp->if_flags & IFF_PROMISC) { | | 3075 | if (ifp->if_flags & IFF_PROMISC) { |
3147 | sc->sc_rctl |= RCTL_UPE; | | 3076 | sc->sc_rctl |= RCTL_UPE; |
3148 | goto allmulti; | | 3077 | goto allmulti; |
3149 | } | | 3078 | } |
3150 | | | 3079 | |
3151 | /* | | 3080 | /* |
3152 | * Set the station address in the first RAL slot, and | | 3081 | * Set the station address in the first RAL slot, and |
3153 | * clear the remaining slots. | | 3082 | * clear the remaining slots. |
3154 | */ | | 3083 | */ |
3155 | if (sc->sc_type == WM_T_ICH8) | | 3084 | if (sc->sc_type == WM_T_ICH8) |
3156 | size = WM_RAL_TABSIZE_ICH8 -1; | | 3085 | size = WM_RAL_TABSIZE_ICH8 -1; |
3157 | else if ((sc->sc_type == WM_T_ICH9) || (sc->sc_type == WM_T_ICH10) | | 3086 | else if ((sc->sc_type == WM_T_ICH9) || (sc->sc_type == WM_T_ICH10) |
3158 | || (sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2) | | 3087 | || (sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2) |
3159 | || (sc->sc_type == WM_T_PCH_LPT)) | | 3088 | || (sc->sc_type == WM_T_PCH_LPT)) |
3160 | size = WM_RAL_TABSIZE_ICH8; | | 3089 | size = WM_RAL_TABSIZE_ICH8; |
3161 | else if (sc->sc_type == WM_T_82575) | | 3090 | else if (sc->sc_type == WM_T_82575) |
3162 | size = WM_RAL_TABSIZE_82575; | | 3091 | size = WM_RAL_TABSIZE_82575; |
3163 | else if ((sc->sc_type == WM_T_82576) || (sc->sc_type == WM_T_82580)) | | 3092 | else if ((sc->sc_type == WM_T_82576) || (sc->sc_type == WM_T_82580)) |
3164 | size = WM_RAL_TABSIZE_82576; | | 3093 | size = WM_RAL_TABSIZE_82576; |
3165 | else if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)) | | 3094 | else if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)) |
3166 | size = WM_RAL_TABSIZE_I350; | | 3095 | size = WM_RAL_TABSIZE_I350; |
3167 | else | | 3096 | else |
3168 | size = WM_RAL_TABSIZE; | | 3097 | size = WM_RAL_TABSIZE; |
3169 | wm_set_ral(sc, CLLADDR(ifp->if_sadl), 0); | | 3098 | wm_set_ral(sc, CLLADDR(ifp->if_sadl), 0); |
3170 | for (i = 1; i < size; i++) | | 3099 | for (i = 1; i < size; i++) |
3171 | wm_set_ral(sc, NULL, i); | | 3100 | wm_set_ral(sc, NULL, i); |
3172 | | | 3101 | |
3173 | if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9) | | 3102 | if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9) |
3174 | || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH) | | 3103 | || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH) |
3175 | || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) | | 3104 | || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) |
3176 | size = WM_ICH8_MC_TABSIZE; | | 3105 | size = WM_ICH8_MC_TABSIZE; |
3177 | else | | 3106 | else |
3178 | size = WM_MC_TABSIZE; | | 3107 | size = WM_MC_TABSIZE; |
3179 | /* Clear out the multicast table. */ | | 3108 | /* Clear out the multicast table. */ |
3180 | for (i = 0; i < size; i++) | | 3109 | for (i = 0; i < size; i++) |
3181 | CSR_WRITE(sc, mta_reg + (i << 2), 0); | | 3110 | CSR_WRITE(sc, mta_reg + (i << 2), 0); |
3182 | | | 3111 | |
3183 | ETHER_FIRST_MULTI(step, ec, enm); | | 3112 | ETHER_FIRST_MULTI(step, ec, enm); |
3184 | while (enm != NULL) { | | 3113 | while (enm != NULL) { |
3185 | if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { | | 3114 | if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { |
3186 | /* | | 3115 | /* |
3187 | * We must listen to a range of multicast addresses. | | 3116 | * We must listen to a range of multicast addresses. |
3188 | * For now, just accept all multicasts, rather than | | 3117 | * For now, just accept all multicasts, rather than |
3189 | * trying to set only those filter bits needed to match | | 3118 | * trying to set only those filter bits needed to match |
3190 | * the range. (At this time, the only use of address | | 3119 | * the range. (At this time, the only use of address |
3191 | * ranges is for IP multicast routing, for which the | | 3120 | * ranges is for IP multicast routing, for which the |
3192 | * range is big enough to require all bits set.) | | 3121 | * range is big enough to require all bits set.) |
3193 | */ | | 3122 | */ |
3194 | goto allmulti; | | 3123 | goto allmulti; |
3195 | } | | 3124 | } |
3196 | | | 3125 | |
3197 | hash = wm_mchash(sc, enm->enm_addrlo); | | 3126 | hash = wm_mchash(sc, enm->enm_addrlo); |
3198 | | | 3127 | |
3199 | reg = (hash >> 5); | | 3128 | reg = (hash >> 5); |
3200 | if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9) | | 3129 | if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9) |
3201 | || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH) | | 3130 | || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH) |
3202 | || (sc->sc_type == WM_T_PCH2) | | 3131 | || (sc->sc_type == WM_T_PCH2) |
3203 | || (sc->sc_type == WM_T_PCH_LPT)) | | 3132 | || (sc->sc_type == WM_T_PCH_LPT)) |
3204 | reg &= 0x1f; | | 3133 | reg &= 0x1f; |
3205 | else | | 3134 | else |
3206 | reg &= 0x7f; | | 3135 | reg &= 0x7f; |
3207 | bit = hash & 0x1f; | | 3136 | bit = hash & 0x1f; |
3208 | | | 3137 | |
3209 | hash = CSR_READ(sc, mta_reg + (reg << 2)); | | 3138 | hash = CSR_READ(sc, mta_reg + (reg << 2)); |
3210 | hash |= 1U << bit; | | 3139 | hash |= 1U << bit; |
3211 | | | 3140 | |
3212 | /* XXX Hardware bug?? */ | | 3141 | /* XXX Hardware bug?? */ |
3213 | if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) { | | 3142 | if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) { |
3214 | bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2)); | | 3143 | bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2)); |
3215 | CSR_WRITE(sc, mta_reg + (reg << 2), hash); | | 3144 | CSR_WRITE(sc, mta_reg + (reg << 2), hash); |
3216 | CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit); | | 3145 | CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit); |
3217 | } else | | 3146 | } else |
3218 | CSR_WRITE(sc, mta_reg + (reg << 2), hash); | | 3147 | CSR_WRITE(sc, mta_reg + (reg << 2), hash); |
3219 | | | 3148 | |
3220 | ETHER_NEXT_MULTI(step, enm); | | 3149 | ETHER_NEXT_MULTI(step, enm); |
3221 | } | | 3150 | } |
3222 | | | 3151 | |
3223 | ifp->if_flags &= ~IFF_ALLMULTI; | | 3152 | ifp->if_flags &= ~IFF_ALLMULTI; |
3224 | goto setit; | | 3153 | goto setit; |
3225 | | | 3154 | |
3226 | allmulti: | | 3155 | allmulti: |
3227 | ifp->if_flags |= IFF_ALLMULTI; | | 3156 | ifp->if_flags |= IFF_ALLMULTI; |
3228 | sc->sc_rctl |= RCTL_MPE; | | 3157 | sc->sc_rctl |= RCTL_MPE; |
3229 | | | 3158 | |
3230 | setit: | | 3159 | setit: |
3231 | CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl); | | 3160 | CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl); |
3232 | } | | 3161 | } |
3233 | | | 3162 | |
3234 | /* Reset and init related */ | | 3163 | /* Reset and init related */ |
3235 | | | 3164 | |
3236 | static void | | 3165 | static void |
3237 | wm_set_vlan(struct wm_softc *sc) | | 3166 | wm_set_vlan(struct wm_softc *sc) |
3238 | { | | 3167 | { |
3239 | /* Deal with VLAN enables. */ | | 3168 | /* Deal with VLAN enables. */ |
3240 | if (VLAN_ATTACHED(&sc->sc_ethercom)) | | 3169 | if (VLAN_ATTACHED(&sc->sc_ethercom)) |
3241 | sc->sc_ctrl |= CTRL_VME; | | 3170 | sc->sc_ctrl |= CTRL_VME; |
3242 | else | | 3171 | else |
3243 | sc->sc_ctrl &= ~CTRL_VME; | | 3172 | sc->sc_ctrl &= ~CTRL_VME; |
3244 | | | 3173 | |
3245 | /* Write the control registers. */ | | 3174 | /* Write the control registers. */ |
3246 | CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); | | 3175 | CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); |
3247 | } | | 3176 | } |
3248 | | | 3177 | |
3249 | static void | | 3178 | static void |
3250 | wm_set_pcie_completion_timeout(struct wm_softc *sc) | | 3179 | wm_set_pcie_completion_timeout(struct wm_softc *sc) |
3251 | { | | 3180 | { |
3252 | uint32_t gcr; | | 3181 | uint32_t gcr; |
3253 | pcireg_t ctrl2; | | 3182 | pcireg_t ctrl2; |
3254 | | | 3183 | |
3255 | gcr = CSR_READ(sc, WMREG_GCR); | | 3184 | gcr = CSR_READ(sc, WMREG_GCR); |
3256 | | | 3185 | |
3257 | /* Only take action if timeout value is defaulted to 0 */ | | 3186 | /* Only take action if timeout value is defaulted to 0 */ |
3258 | if ((gcr & GCR_CMPL_TMOUT_MASK) != 0) | | 3187 | if ((gcr & GCR_CMPL_TMOUT_MASK) != 0) |
3259 | goto out; | | 3188 | goto out; |
3260 | | | 3189 | |
3261 | if ((gcr & GCR_CAP_VER2) == 0) { | | 3190 | if ((gcr & GCR_CAP_VER2) == 0) { |
3262 | gcr |= GCR_CMPL_TMOUT_10MS; | | 3191 | gcr |= GCR_CMPL_TMOUT_10MS; |
3263 | goto out; | | 3192 | goto out; |
3264 | } | | 3193 | } |
3265 | | | 3194 | |
3266 | ctrl2 = pci_conf_read(sc->sc_pc, sc->sc_pcitag, | | 3195 | ctrl2 = pci_conf_read(sc->sc_pc, sc->sc_pcitag, |
3267 | sc->sc_pcixe_capoff + PCIE_DCSR2); | | 3196 | sc->sc_pcixe_capoff + PCIE_DCSR2); |
3268 | ctrl2 |= WM_PCIE_DCSR2_16MS; | | 3197 | ctrl2 |= WM_PCIE_DCSR2_16MS; |
3269 | pci_conf_write(sc->sc_pc, sc->sc_pcitag, | | 3198 | pci_conf_write(sc->sc_pc, sc->sc_pcitag, |
3270 | sc->sc_pcixe_capoff + PCIE_DCSR2, ctrl2); | | 3199 | sc->sc_pcixe_capoff + PCIE_DCSR2, ctrl2); |
3271 | | | 3200 | |
3272 | out: | | 3201 | out: |
3273 | /* Disable completion timeout resend */ | | 3202 | /* Disable completion timeout resend */ |
3274 | gcr &= ~GCR_CMPL_TMOUT_RESEND; | | 3203 | gcr &= ~GCR_CMPL_TMOUT_RESEND; |
3275 | | | 3204 | |
3276 | CSR_WRITE(sc, WMREG_GCR, gcr); | | 3205 | CSR_WRITE(sc, WMREG_GCR, gcr); |
3277 | } | | 3206 | } |
3278 | | | 3207 | |
3279 | void | | 3208 | void |
3280 | wm_get_auto_rd_done(struct wm_softc *sc) | | 3209 | wm_get_auto_rd_done(struct wm_softc *sc) |
3281 | { | | 3210 | { |
3282 | int i; | | 3211 | int i; |
3283 | | | 3212 | |
3284 | /* wait for eeprom to reload */ | | 3213 | /* wait for eeprom to reload */ |
3285 | switch (sc->sc_type) { | | 3214 | switch (sc->sc_type) { |
3286 | case WM_T_82571: | | 3215 | case WM_T_82571: |
3287 | case WM_T_82572: | | 3216 | case WM_T_82572: |
3288 | case WM_T_82573: | | 3217 | case WM_T_82573: |
3289 | case WM_T_82574: | | 3218 | case WM_T_82574: |
3290 | case WM_T_82583: | | 3219 | case WM_T_82583: |
3291 | case WM_T_82575: | | 3220 | case WM_T_82575: |
3292 | case WM_T_82576: | | 3221 | case WM_T_82576: |
3293 | case WM_T_82580: | | 3222 | case WM_T_82580: |
3294 | case WM_T_I350: | | 3223 | case WM_T_I350: |
3295 | case WM_T_I354: | | 3224 | case WM_T_I354: |
3296 | case WM_T_I210: | | 3225 | case WM_T_I210: |
3297 | case WM_T_I211: | | 3226 | case WM_T_I211: |
3298 | case WM_T_80003: | | 3227 | case WM_T_80003: |
3299 | case WM_T_ICH8: | | 3228 | case WM_T_ICH8: |
3300 | case WM_T_ICH9: | | 3229 | case WM_T_ICH9: |
3301 | for (i = 0; i < 10; i++) { | | 3230 | for (i = 0; i < 10; i++) { |
3302 | if (CSR_READ(sc, WMREG_EECD) & EECD_EE_AUTORD) | | 3231 | if (CSR_READ(sc, WMREG_EECD) & EECD_EE_AUTORD) |
3303 | break; | | 3232 | break; |
3304 | delay(1000); | | 3233 | delay(1000); |
3305 | } | | 3234 | } |
3306 | if (i == 10) { | | 3235 | if (i == 10) { |
3307 | log(LOG_ERR, "%s: auto read from eeprom failed to " | | 3236 | log(LOG_ERR, "%s: auto read from eeprom failed to " |
3308 | "complete\n", device_xname(sc->sc_dev)); | | 3237 | "complete\n", device_xname(sc->sc_dev)); |
3309 | } | | 3238 | } |
3310 | break; | | 3239 | break; |
3311 | default: | | 3240 | default: |
3312 | break; | | 3241 | break; |
3313 | } | | 3242 | } |
3314 | } | | 3243 | } |
3315 | | | 3244 | |
3316 | void | | 3245 | void |
3317 | wm_lan_init_done(struct wm_softc *sc) | | 3246 | wm_lan_init_done(struct wm_softc *sc) |
3318 | { | | 3247 | { |
3319 | uint32_t reg = 0; | | 3248 | uint32_t reg = 0; |
3320 | int i; | | 3249 | int i; |
3321 | | | 3250 | |
3322 | /* wait for eeprom to reload */ | | 3251 | /* wait for eeprom to reload */ |
3323 | switch (sc->sc_type) { | | 3252 | switch (sc->sc_type) { |
3324 | case WM_T_ICH10: | | 3253 | case WM_T_ICH10: |
3325 | case WM_T_PCH: | | 3254 | case WM_T_PCH: |
3326 | case WM_T_PCH2: | | 3255 | case WM_T_PCH2: |
3327 | case WM_T_PCH_LPT: | | 3256 | case WM_T_PCH_LPT: |
3328 | for (i = 0; i < WM_ICH8_LAN_INIT_TIMEOUT; i++) { | | 3257 | for (i = 0; i < WM_ICH8_LAN_INIT_TIMEOUT; i++) { |
3329 | reg = CSR_READ(sc, WMREG_STATUS); | | 3258 | reg = CSR_READ(sc, WMREG_STATUS); |
3330 | if ((reg & STATUS_LAN_INIT_DONE) != 0) | | 3259 | if ((reg & STATUS_LAN_INIT_DONE) != 0) |
3331 | break; | | 3260 | break; |
3332 | delay(100); | | 3261 | delay(100); |
3333 | } | | 3262 | } |
3334 | if (i >= WM_ICH8_LAN_INIT_TIMEOUT) { | | 3263 | if (i >= WM_ICH8_LAN_INIT_TIMEOUT) { |
3335 | log(LOG_ERR, "%s: %s: lan_init_done failed to " | | 3264 | log(LOG_ERR, "%s: %s: lan_init_done failed to " |
3336 | "complete\n", device_xname(sc->sc_dev), __func__); | | 3265 | "complete\n", device_xname(sc->sc_dev), __func__); |
3337 | } | | 3266 | } |
3338 | break; | | 3267 | break; |
3339 | default: | | 3268 | default: |
3340 | panic("%s: %s: unknown type\n", device_xname(sc->sc_dev), | | 3269 | panic("%s: %s: unknown type\n", device_xname(sc->sc_dev), |
3341 | __func__); | | 3270 | __func__); |
3342 | break; | | 3271 | break; |
3343 | } | | 3272 | } |
3344 | | | 3273 | |
3345 | reg &= ~STATUS_LAN_INIT_DONE; | | 3274 | reg &= ~STATUS_LAN_INIT_DONE; |
3346 | CSR_WRITE(sc, WMREG_STATUS, reg); | | 3275 | CSR_WRITE(sc, WMREG_STATUS, reg); |
3347 | } | | 3276 | } |
3348 | | | 3277 | |
3349 | void | | 3278 | void |
3350 | wm_get_cfg_done(struct wm_softc *sc) | | 3279 | wm_get_cfg_done(struct wm_softc *sc) |
3351 | { | | 3280 | { |
3352 | int mask; | | 3281 | int mask; |
3353 | uint32_t reg; | | 3282 | uint32_t reg; |
3354 | int i; | | 3283 | int i; |
3355 | | | 3284 | |
3356 | /* wait for eeprom to reload */ | | 3285 | /* wait for eeprom to reload */ |
3357 | switch (sc->sc_type) { | | 3286 | switch (sc->sc_type) { |
3358 | case WM_T_82542_2_0: | | 3287 | case WM_T_82542_2_0: |
3359 | case WM_T_82542_2_1: | | 3288 | case WM_T_82542_2_1: |
3360 | /* null */ | | 3289 | /* null */ |
3361 | break; | | 3290 | break; |
3362 | case WM_T_82543: | | 3291 | case WM_T_82543: |
3363 | case WM_T_82544: | | 3292 | case WM_T_82544: |
3364 | case WM_T_82540: | | 3293 | case WM_T_82540: |
3365 | case WM_T_82545: | | 3294 | case WM_T_82545: |
3366 | case WM_T_82545_3: | | 3295 | case WM_T_82545_3: |
3367 | case WM_T_82546: | | 3296 | case WM_T_82546: |
3368 | case WM_T_82546_3: | | 3297 | case WM_T_82546_3: |
3369 | case WM_T_82541: | | 3298 | case WM_T_82541: |
3370 | case WM_T_82541_2: | | 3299 | case WM_T_82541_2: |
3371 | case WM_T_82547: | | 3300 | case WM_T_82547: |
3372 | case WM_T_82547_2: | | 3301 | case WM_T_82547_2: |
3373 | case WM_T_82573: | | 3302 | case WM_T_82573: |
3374 | case WM_T_82574: | | 3303 | case WM_T_82574: |
3375 | case WM_T_82583: | | 3304 | case WM_T_82583: |
3376 | /* generic */ | | 3305 | /* generic */ |
3377 | delay(10*1000); | | 3306 | delay(10*1000); |
3378 | break; | | 3307 | break; |
3379 | case WM_T_80003: | | 3308 | case WM_T_80003: |
3380 | case WM_T_82571: | | 3309 | case WM_T_82571: |
3381 | case WM_T_82572: | | 3310 | case WM_T_82572: |
3382 | case WM_T_82575: | | 3311 | case WM_T_82575: |
3383 | case WM_T_82576: | | 3312 | case WM_T_82576: |
3384 | case WM_T_82580: | | 3313 | case WM_T_82580: |
3385 | case WM_T_I350: | | 3314 | case WM_T_I350: |
3386 | case WM_T_I354: | | 3315 | case WM_T_I354: |
3387 | case WM_T_I210: | | 3316 | case WM_T_I210: |
3388 | case WM_T_I211: | | 3317 | case WM_T_I211: |
3389 | if (sc->sc_type == WM_T_82571) { | | 3318 | if (sc->sc_type == WM_T_82571) { |
3390 | /* Only 82571 shares port 0 */ | | 3319 | /* Only 82571 shares port 0 */ |
3391 | mask = EEMNGCTL_CFGDONE_0; | | 3320 | mask = EEMNGCTL_CFGDONE_0; |
3392 | } else | | 3321 | } else |
3393 | mask = EEMNGCTL_CFGDONE_0 << sc->sc_funcid; | | 3322 | mask = EEMNGCTL_CFGDONE_0 << sc->sc_funcid; |
3394 | for (i = 0; i < WM_PHY_CFG_TIMEOUT; i++) { | | 3323 | for (i = 0; i < WM_PHY_CFG_TIMEOUT; i++) { |
3395 | if (CSR_READ(sc, WMREG_EEMNGCTL) & mask) | | 3324 | if (CSR_READ(sc, WMREG_EEMNGCTL) & mask) |
3396 | break; | | 3325 | break; |
3397 | delay(1000); | | 3326 | delay(1000); |
3398 | } | | 3327 | } |
3399 | if (i >= WM_PHY_CFG_TIMEOUT) { | | 3328 | if (i >= WM_PHY_CFG_TIMEOUT) { |
3400 | DPRINTF(WM_DEBUG_GMII, ("%s: %s failed\n", | | 3329 | DPRINTF(WM_DEBUG_GMII, ("%s: %s failed\n", |
3401 | device_xname(sc->sc_dev), __func__)); | | 3330 | device_xname(sc->sc_dev), __func__)); |
3402 | } | | 3331 | } |
3403 | break; | | 3332 | break; |
3404 | case WM_T_ICH8: | | 3333 | case WM_T_ICH8: |
3405 | case WM_T_ICH9: | | 3334 | case WM_T_ICH9: |
3406 | case WM_T_ICH10: | | 3335 | case WM_T_ICH10: |
3407 | case WM_T_PCH: | | 3336 | case WM_T_PCH: |
3408 | case WM_T_PCH2: | | 3337 | case WM_T_PCH2: |
3409 | case WM_T_PCH_LPT: | | 3338 | case WM_T_PCH_LPT: |
3410 | delay(10*1000); | | 3339 | delay(10*1000); |
3411 | if (sc->sc_type >= WM_T_ICH10) | | 3340 | if (sc->sc_type >= WM_T_ICH10) |
3412 | wm_lan_init_done(sc); | | 3341 | wm_lan_init_done(sc); |
3413 | else | | 3342 | else |
3414 | wm_get_auto_rd_done(sc); | | 3343 | wm_get_auto_rd_done(sc); |
3415 | | | 3344 | |
3416 | reg = CSR_READ(sc, WMREG_STATUS); | | 3345 | reg = CSR_READ(sc, WMREG_STATUS); |
3417 | if ((reg & STATUS_PHYRA) != 0) | | 3346 | if ((reg & STATUS_PHYRA) != 0) |
3418 | CSR_WRITE(sc, WMREG_STATUS, reg & ~STATUS_PHYRA); | | 3347 | CSR_WRITE(sc, WMREG_STATUS, reg & ~STATUS_PHYRA); |
3419 | break; | | 3348 | break; |
3420 | default: | | 3349 | default: |
3421 | panic("%s: %s: unknown type\n", device_xname(sc->sc_dev), | | 3350 | panic("%s: %s: unknown type\n", device_xname(sc->sc_dev), |
3422 | __func__); | | 3351 | __func__); |
3423 | break; | | 3352 | break; |
3424 | } | | 3353 | } |
3425 | } | | 3354 | } |
3426 | | | 3355 | |
3427 | /* Init hardware bits */ | | 3356 | /* Init hardware bits */ |
3428 | void | | 3357 | void |
3429 | wm_initialize_hardware_bits(struct wm_softc *sc) | | 3358 | wm_initialize_hardware_bits(struct wm_softc *sc) |
3430 | { | | 3359 | { |
3431 | uint32_t tarc0, tarc1, reg; | | 3360 | uint32_t tarc0, tarc1, reg; |
3432 | | | 3361 | |
3433 | /* For 82571 variant, 80003 and ICHs */ | | 3362 | /* For 82571 variant, 80003 and ICHs */ |
3434 | if (((sc->sc_type >= WM_T_82571) && (sc->sc_type <= WM_T_82583)) | | 3363 | if (((sc->sc_type >= WM_T_82571) && (sc->sc_type <= WM_T_82583)) |
3435 | || (sc->sc_type >= WM_T_80003)) { | | 3364 | || (sc->sc_type >= WM_T_80003)) { |
3436 | | | 3365 | |
3437 | /* Transmit Descriptor Control 0 */ | | 3366 | /* Transmit Descriptor Control 0 */ |
3438 | reg = CSR_READ(sc, WMREG_TXDCTL(0)); | | 3367 | reg = CSR_READ(sc, WMREG_TXDCTL(0)); |
3439 | reg |= TXDCTL_COUNT_DESC; | | 3368 | reg |= TXDCTL_COUNT_DESC; |
3440 | CSR_WRITE(sc, WMREG_TXDCTL(0), reg); | | 3369 | CSR_WRITE(sc, WMREG_TXDCTL(0), reg); |
3441 | | | 3370 | |
3442 | /* Transmit Descriptor Control 1 */ | | 3371 | /* Transmit Descriptor Control 1 */ |
3443 | reg = CSR_READ(sc, WMREG_TXDCTL(1)); | | 3372 | reg = CSR_READ(sc, WMREG_TXDCTL(1)); |
3444 | reg |= TXDCTL_COUNT_DESC; | | 3373 | reg |= TXDCTL_COUNT_DESC; |
3445 | CSR_WRITE(sc, WMREG_TXDCTL(1), reg); | | 3374 | CSR_WRITE(sc, WMREG_TXDCTL(1), reg); |
3446 | | | 3375 | |
3447 | /* TARC0 */ | | 3376 | /* TARC0 */ |
3448 | tarc0 = CSR_READ(sc, WMREG_TARC0); | | 3377 | tarc0 = CSR_READ(sc, WMREG_TARC0); |
3449 | switch (sc->sc_type) { | | 3378 | switch (sc->sc_type) { |
3450 | case WM_T_82571: | | 3379 | case WM_T_82571: |
3451 | case WM_T_82572: | | 3380 | case WM_T_82572: |
3452 | case WM_T_82573: | | 3381 | case WM_T_82573: |
3453 | case WM_T_82574: | | 3382 | case WM_T_82574: |
3454 | case WM_T_82583: | | 3383 | case WM_T_82583: |
3455 | case WM_T_80003: | | 3384 | case WM_T_80003: |
3456 | /* Clear bits 30..27 */ | | 3385 | /* Clear bits 30..27 */ |
3457 | tarc0 &= ~__BITS(30, 27); | | 3386 | tarc0 &= ~__BITS(30, 27); |
3458 | break; | | 3387 | break; |
3459 | default: | | 3388 | default: |
3460 | break; | | 3389 | break; |
3461 | } | | 3390 | } |
3462 | | | 3391 | |
3463 | switch (sc->sc_type) { | | 3392 | switch (sc->sc_type) { |
3464 | case WM_T_82571: | | 3393 | case WM_T_82571: |
3465 | case WM_T_82572: | | 3394 | case WM_T_82572: |
3466 | tarc0 |= __BITS(26, 23); /* TARC0 bits 23-26 */ | | 3395 | tarc0 |= __BITS(26, 23); /* TARC0 bits 23-26 */ |
3467 | | | 3396 | |
3468 | tarc1 = CSR_READ(sc, WMREG_TARC1); | | 3397 | tarc1 = CSR_READ(sc, WMREG_TARC1); |
3469 | tarc1 &= ~__BITS(30, 29); /* Clear bits 30 and 29 */ | | 3398 | tarc1 &= ~__BITS(30, 29); /* Clear bits 30 and 29 */ |
3470 | tarc1 |= __BITS(26, 24); /* TARC1 bits 26-24 */ | | 3399 | tarc1 |= __BITS(26, 24); /* TARC1 bits 26-24 */ |
3471 | /* 8257[12] Errata No.7 */ | | 3400 | /* 8257[12] Errata No.7 */ |
3472 | tarc1 |= __BIT(22); /* TARC1 bits 22 */ | | 3401 | tarc1 |= __BIT(22); /* TARC1 bits 22 */ |
3473 | | | 3402 | |
3474 | /* TARC1 bit 28 */ | | 3403 | /* TARC1 bit 28 */ |
3475 | if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0) | | 3404 | if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0) |
3476 | tarc1 &= ~__BIT(28); | | 3405 | tarc1 &= ~__BIT(28); |
3477 | else | | 3406 | else |
3478 | tarc1 |= __BIT(28); | | 3407 | tarc1 |= __BIT(28); |
3479 | CSR_WRITE(sc, WMREG_TARC1, tarc1); | | 3408 | CSR_WRITE(sc, WMREG_TARC1, tarc1); |
3480 | | | 3409 | |
3481 | /* | | 3410 | /* |
3482 | * 8257[12] Errata No.13 | | 3411 | * 8257[12] Errata No.13 |
3483 | * Disable Dyamic Clock Gating. | | 3412 | * Disable Dyamic Clock Gating. |
3484 | */ | | 3413 | */ |
3485 | reg = CSR_READ(sc, WMREG_CTRL_EXT); | | 3414 | reg = CSR_READ(sc, WMREG_CTRL_EXT); |
3486 | reg &= ~CTRL_EXT_DMA_DYN_CLK; | | 3415 | reg &= ~CTRL_EXT_DMA_DYN_CLK; |
3487 | CSR_WRITE(sc, WMREG_CTRL_EXT, reg); | | 3416 | CSR_WRITE(sc, WMREG_CTRL_EXT, reg); |
3488 | break; | | 3417 | break; |
3489 | case WM_T_82573: | | 3418 | case WM_T_82573: |
3490 | case WM_T_82574: | | 3419 | case WM_T_82574: |
3491 | case WM_T_82583: | | 3420 | case WM_T_82583: |
3492 | if ((sc->sc_type == WM_T_82574) | | 3421 | if ((sc->sc_type == WM_T_82574) |
3493 | || (sc->sc_type == WM_T_82583)) | | 3422 | || (sc->sc_type == WM_T_82583)) |
3494 | tarc0 |= __BIT(26); /* TARC0 bit 26 */ | | 3423 | tarc0 |= __BIT(26); /* TARC0 bit 26 */ |
3495 | | | 3424 | |
3496 | /* Extended Device Control */ | | 3425 | /* Extended Device Control */ |
3497 | reg = CSR_READ(sc, WMREG_CTRL_EXT); | | 3426 | reg = CSR_READ(sc, WMREG_CTRL_EXT); |
3498 | reg &= ~__BIT(23); /* Clear bit 23 */ | | 3427 | reg &= ~__BIT(23); /* Clear bit 23 */ |
3499 | reg |= __BIT(22); /* Set bit 22 */ | | 3428 | reg |= __BIT(22); /* Set bit 22 */ |
3500 | CSR_WRITE(sc, WMREG_CTRL_EXT, reg); | | 3429 | CSR_WRITE(sc, WMREG_CTRL_EXT, reg); |
3501 | | | 3430 | |
3502 | /* Device Control */ | | 3431 | /* Device Control */ |
3503 | sc->sc_ctrl &= ~__BIT(29); /* Clear bit 29 */ | | 3432 | sc->sc_ctrl &= ~__BIT(29); /* Clear bit 29 */ |
3504 | CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); | | 3433 | CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); |
3505 | | | 3434 | |
3506 | /* PCIe Control Register */ | | 3435 | /* PCIe Control Register */ |
3507 | /* | | 3436 | /* |
3508 | * 82573 Errata (unknown). | | 3437 | * 82573 Errata (unknown). |
3509 | * | | 3438 | * |
3510 | * 82574 Errata 25 and 82583 Errata 12 | | 3439 | * 82574 Errata 25 and 82583 Errata 12 |
3511 | * "Dropped Rx Packets": | | 3440 | * "Dropped Rx Packets": |
3512 | * NVM Image Version 2.1.4 and newer has no this bug. | | 3441 | * NVM Image Version 2.1.4 and newer has no this bug. |
3513 | */ | | 3442 | */ |
3514 | reg = CSR_READ(sc, WMREG_GCR); | | 3443 | reg = CSR_READ(sc, WMREG_GCR); |
3515 | reg |= GCR_L1_ACT_WITHOUT_L0S_RX; | | 3444 | reg |= GCR_L1_ACT_WITHOUT_L0S_RX; |
3516 | CSR_WRITE(sc, WMREG_GCR, reg); | | 3445 | CSR_WRITE(sc, WMREG_GCR, reg); |
3517 | | | 3446 | |
3518 | if ((sc->sc_type == WM_T_82574) | | 3447 | if ((sc->sc_type == WM_T_82574) |
3519 | || (sc->sc_type == WM_T_82583)) { | | 3448 | || (sc->sc_type == WM_T_82583)) { |
3520 | /* | | 3449 | /* |
3521 | * Document says this bit must be set for | | 3450 | * Document says this bit must be set for |
3522 | * proper operation. | | 3451 | * proper operation. |
3523 | */ | | 3452 | */ |
3524 | reg = CSR_READ(sc, WMREG_GCR); | | 3453 | reg = CSR_READ(sc, WMREG_GCR); |
3525 | reg |= __BIT(22); | | 3454 | reg |= __BIT(22); |
3526 | CSR_WRITE(sc, WMREG_GCR, reg); | | 3455 | CSR_WRITE(sc, WMREG_GCR, reg); |
3527 | | | 3456 | |
3528 | /* | | 3457 | /* |
3529 | * Apply workaround for hardware errata | | 3458 | * Apply workaround for hardware errata |
3530 | * documented in errata docs Fixes issue where | | 3459 | * documented in errata docs Fixes issue where |
3531 | * some error prone or unreliable PCIe | | 3460 | * some error prone or unreliable PCIe |
3532 | * completions are occurring, particularly | | 3461 | * completions are occurring, particularly |
3533 | * with ASPM enabled. Without fix, issue can | | 3462 | * with ASPM enabled. Without fix, issue can |
3534 | * cause Tx timeouts. | | 3463 | * cause Tx timeouts. |
3535 | */ | | 3464 | */ |
3536 | reg = CSR_READ(sc, WMREG_GCR2); | | 3465 | reg = CSR_READ(sc, WMREG_GCR2); |
3537 | reg |= __BIT(0); | | 3466 | reg |= __BIT(0); |
3538 | CSR_WRITE(sc, WMREG_GCR2, reg); | | 3467 | CSR_WRITE(sc, WMREG_GCR2, reg); |
3539 | } | | 3468 | } |
3540 | break; | | 3469 | break; |
3541 | case WM_T_80003: | | 3470 | case WM_T_80003: |
3542 | /* TARC0 */ | | 3471 | /* TARC0 */ |
3543 | if ((sc->sc_mediatype == WM_MEDIATYPE_FIBER) | | 3472 | if ((sc->sc_mediatype == WM_MEDIATYPE_FIBER) |
3544 | || (sc->sc_mediatype == WM_MEDIATYPE_SERDES)) | | 3473 | || (sc->sc_mediatype == WM_MEDIATYPE_SERDES)) |
3545 | tarc0 &= ~__BIT(20); /* Clear bits 20 */ | | 3474 | tarc0 &= ~__BIT(20); /* Clear bits 20 */ |
3546 | | | 3475 | |
3547 | /* TARC1 bit 28 */ | | 3476 | /* TARC1 bit 28 */ |
3548 | tarc1 = CSR_READ(sc, WMREG_TARC1); | | 3477 | tarc1 = CSR_READ(sc, WMREG_TARC1); |
3549 | if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0) | | 3478 | if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0) |
3550 | tarc1 &= ~__BIT(28); | | 3479 | tarc1 &= ~__BIT(28); |
3551 | else | | 3480 | else |
3552 | tarc1 |= __BIT(28); | | 3481 | tarc1 |= __BIT(28); |
3553 | CSR_WRITE(sc, WMREG_TARC1, tarc1); | | 3482 | CSR_WRITE(sc, WMREG_TARC1, tarc1); |
3554 | break; | | 3483 | break; |
3555 | case WM_T_ICH8: | | 3484 | case WM_T_ICH8: |
3556 | case WM_T_ICH9: | | 3485 | case WM_T_ICH9: |
3557 | case WM_T_ICH10: | | 3486 | case WM_T_ICH10: |
3558 | case WM_T_PCH: | | 3487 | case WM_T_PCH: |
3559 | case WM_T_PCH2: | | 3488 | case WM_T_PCH2: |
3560 | case WM_T_PCH_LPT: | | 3489 | case WM_T_PCH_LPT: |
3561 | /* TARC 0 */ | | 3490 | /* TARC 0 */ |
3562 | if (sc->sc_type == WM_T_ICH8) { | | 3491 | if (sc->sc_type == WM_T_ICH8) { |
3563 | /* Set TARC0 bits 29 and 28 */ | | 3492 | /* Set TARC0 bits 29 and 28 */ |
3564 | tarc0 |= __BITS(29, 28); | | 3493 | tarc0 |= __BITS(29, 28); |
3565 | } | | 3494 | } |
3566 | /* Set TARC0 bits 23,24,26,27 */ | | 3495 | /* Set TARC0 bits 23,24,26,27 */ |
3567 | tarc0 |= __BITS(27, 26) | __BITS(24, 23); | | 3496 | tarc0 |= __BITS(27, 26) | __BITS(24, 23); |
3568 | | | 3497 | |
3569 | /* CTRL_EXT */ | | 3498 | /* CTRL_EXT */ |
3570 | reg = CSR_READ(sc, WMREG_CTRL_EXT); | | 3499 | reg = CSR_READ(sc, WMREG_CTRL_EXT); |
3571 | reg |= __BIT(22); /* Set bit 22 */ | | 3500 | reg |= __BIT(22); /* Set bit 22 */ |
3572 | /* | | 3501 | /* |
3573 | * Enable PHY low-power state when MAC is at D3 | | 3502 | * Enable PHY low-power state when MAC is at D3 |
3574 | * w/o WoL | | 3503 | * w/o WoL |
3575 | */ | | 3504 | */ |
3576 | if (sc->sc_type >= WM_T_PCH) | | 3505 | if (sc->sc_type >= WM_T_PCH) |
3577 | reg |= CTRL_EXT_PHYPDEN; | | 3506 | reg |= CTRL_EXT_PHYPDEN; |
3578 | CSR_WRITE(sc, WMREG_CTRL_EXT, reg); | | 3507 | CSR_WRITE(sc, WMREG_CTRL_EXT, reg); |
3579 | | | 3508 | |
3580 | /* TARC1 */ | | 3509 | /* TARC1 */ |
3581 | tarc1 = CSR_READ(sc, WMREG_TARC1); | | 3510 | tarc1 = CSR_READ(sc, WMREG_TARC1); |
3582 | /* bit 28 */ | | 3511 | /* bit 28 */ |
3583 | if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0) | | 3512 | if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0) |
3584 | tarc1 &= ~__BIT(28); | | 3513 | tarc1 &= ~__BIT(28); |
3585 | else | | 3514 | else |
3586 | tarc1 |= __BIT(28); | | 3515 | tarc1 |= __BIT(28); |
3587 | tarc1 |= __BIT(24) | __BIT(26) | __BIT(30); | | 3516 | tarc1 |= __BIT(24) | __BIT(26) | __BIT(30); |
3588 | CSR_WRITE(sc, WMREG_TARC1, tarc1); | | 3517 | CSR_WRITE(sc, WMREG_TARC1, tarc1); |
3589 | | | 3518 | |
3590 | /* Device Status */ | | 3519 | /* Device Status */ |
3591 | if (sc->sc_type == WM_T_ICH8) { | | 3520 | if (sc->sc_type == WM_T_ICH8) { |
3592 | reg = CSR_READ(sc, WMREG_STATUS); | | 3521 | reg = CSR_READ(sc, WMREG_STATUS); |
3593 | reg &= ~__BIT(31); | | 3522 | reg &= ~__BIT(31); |
3594 | CSR_WRITE(sc, WMREG_STATUS, reg); | | 3523 | CSR_WRITE(sc, WMREG_STATUS, reg); |
3595 | | | 3524 | |
3596 | } | | 3525 | } |
3597 | | | 3526 | |
3598 | /* | | 3527 | /* |
3599 | * Work-around descriptor data corruption issue during | | 3528 | * Work-around descriptor data corruption issue during |
3600 | * NFS v2 UDP traffic, just disable the NFS filtering | | 3529 | * NFS v2 UDP traffic, just disable the NFS filtering |
3601 | * capability. | | 3530 | * capability. |
3602 | */ | | 3531 | */ |
3603 | reg = CSR_READ(sc, WMREG_RFCTL); | | 3532 | reg = CSR_READ(sc, WMREG_RFCTL); |
3604 | reg |= WMREG_RFCTL_NFSWDIS | WMREG_RFCTL_NFSRDIS; | | 3533 | reg |= WMREG_RFCTL_NFSWDIS | WMREG_RFCTL_NFSRDIS; |
3605 | CSR_WRITE(sc, WMREG_RFCTL, reg); | | 3534 | CSR_WRITE(sc, WMREG_RFCTL, reg); |
3606 | break; | | 3535 | break; |
3607 | default: | | 3536 | default: |
3608 | break; | | 3537 | break; |
3609 | } | | 3538 | } |
3610 | CSR_WRITE(sc, WMREG_TARC0, tarc0); | | 3539 | CSR_WRITE(sc, WMREG_TARC0, tarc0); |
3611 | | | 3540 | |
3612 | /* | | 3541 | /* |
3613 | * 8257[12] Errata No.52 and some others. | | 3542 | * 8257[12] Errata No.52 and some others. |
3614 | * Avoid RSS Hash Value bug. | | 3543 | * Avoid RSS Hash Value bug. |
3615 | */ | | 3544 | */ |
3616 | switch (sc->sc_type) { | | 3545 | switch (sc->sc_type) { |
3617 | case WM_T_82571: | | 3546 | case WM_T_82571: |
3618 | case WM_T_82572: | | 3547 | case WM_T_82572: |
3619 | case WM_T_82573: | | 3548 | case WM_T_82573: |
3620 | case WM_T_80003: | | 3549 | case WM_T_80003: |
3621 | case WM_T_ICH8: | | 3550 | case WM_T_ICH8: |
3622 | reg = CSR_READ(sc, WMREG_RFCTL); | | 3551 | reg = CSR_READ(sc, WMREG_RFCTL); |
3623 | reg |= WMREG_RFCTL_NEWIPV6EXDIS |WMREG_RFCTL_IPV6EXDIS; | | 3552 | reg |= WMREG_RFCTL_NEWIPV6EXDIS |WMREG_RFCTL_IPV6EXDIS; |
3624 | CSR_WRITE(sc, WMREG_RFCTL, reg); | | 3553 | CSR_WRITE(sc, WMREG_RFCTL, reg); |
3625 | break; | | 3554 | break; |
3626 | default: | | 3555 | default: |
3627 | break; | | 3556 | break; |
3628 | } | | 3557 | } |
3629 | } | | 3558 | } |
3630 | } | | 3559 | } |
3631 | | | 3560 | |
3632 | static uint32_t | | 3561 | static uint32_t |
3633 | wm_rxpbs_adjust_82580(uint32_t val) | | 3562 | wm_rxpbs_adjust_82580(uint32_t val) |
3634 | { | | 3563 | { |
3635 | uint32_t rv = 0; | | 3564 | uint32_t rv = 0; |
3636 | | | 3565 | |
3637 | if (val < __arraycount(wm_82580_rxpbs_table)) | | 3566 | if (val < __arraycount(wm_82580_rxpbs_table)) |
3638 | rv = wm_82580_rxpbs_table[val]; | | 3567 | rv = wm_82580_rxpbs_table[val]; |
3639 | | | 3568 | |
3640 | return rv; | | 3569 | return rv; |
3641 | } | | 3570 | } |
3642 | | | 3571 | |
3643 | /* | | 3572 | /* |
3644 | * wm_reset: | | 3573 | * wm_reset: |
3645 | * | | 3574 | * |
3646 | * Reset the i82542 chip. | | 3575 | * Reset the i82542 chip. |
3647 | */ | | 3576 | */ |
3648 | static void | | 3577 | static void |
3649 | wm_reset(struct wm_softc *sc) | | 3578 | wm_reset(struct wm_softc *sc) |
3650 | { | | 3579 | { |
3651 | struct wm_txqueue *txq = sc->sc_txq; | | 3580 | struct wm_txqueue *txq = sc->sc_txq; |
3652 | int phy_reset = 0; | | 3581 | int phy_reset = 0; |
3653 | int error = 0; | | 3582 | int error = 0; |
3654 | uint32_t reg, mask; | | 3583 | uint32_t reg, mask; |
3655 | | | 3584 | |
3656 | /* | | 3585 | /* |
3657 | * Allocate on-chip memory according to the MTU size. | | 3586 | * Allocate on-chip memory according to the MTU size. |
3658 | * The Packet Buffer Allocation register must be written | | 3587 | * The Packet Buffer Allocation register must be written |
3659 | * before the chip is reset. | | 3588 | * before the chip is reset. |
3660 | */ | | 3589 | */ |
3661 | switch (sc->sc_type) { | | 3590 | switch (sc->sc_type) { |
3662 | case WM_T_82547: | | 3591 | case WM_T_82547: |
3663 | case WM_T_82547_2: | | 3592 | case WM_T_82547_2: |
3664 | sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? | | 3593 | sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? |
3665 | PBA_22K : PBA_30K; | | 3594 | PBA_22K : PBA_30K; |
3666 | txq->txq_fifo_head = 0; | | 3595 | txq->txq_fifo_head = 0; |
3667 | txq->txq_fifo_addr = sc->sc_pba << PBA_ADDR_SHIFT; | | 3596 | txq->txq_fifo_addr = sc->sc_pba << PBA_ADDR_SHIFT; |
3668 | txq->txq_fifo_size = | | 3597 | txq->txq_fifo_size = |
3669 | (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT; | | 3598 | (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT; |
3670 | txq->txq_fifo_stall = 0; | | 3599 | txq->txq_fifo_stall = 0; |
3671 | break; | | 3600 | break; |
3672 | case WM_T_82571: | | 3601 | case WM_T_82571: |
3673 | case WM_T_82572: | | 3602 | case WM_T_82572: |
3674 | case WM_T_82575: /* XXX need special handing for jumbo frames */ | | 3603 | case WM_T_82575: /* XXX need special handing for jumbo frames */ |
3675 | case WM_T_80003: | | 3604 | case WM_T_80003: |
3676 | sc->sc_pba = PBA_32K; | | 3605 | sc->sc_pba = PBA_32K; |
3677 | break; | | 3606 | break; |
3678 | case WM_T_82573: | | 3607 | case WM_T_82573: |
3679 | sc->sc_pba = PBA_12K; | | 3608 | sc->sc_pba = PBA_12K; |
3680 | break; | | 3609 | break; |
3681 | case WM_T_82574: | | 3610 | case WM_T_82574: |
3682 | case WM_T_82583: | | 3611 | case WM_T_82583: |
3683 | sc->sc_pba = PBA_20K; | | 3612 | sc->sc_pba = PBA_20K; |
3684 | break; | | 3613 | break; |
3685 | case WM_T_82576: | | 3614 | case WM_T_82576: |
3686 | sc->sc_pba = CSR_READ(sc, WMREG_RXPBS); | | 3615 | sc->sc_pba = CSR_READ(sc, WMREG_RXPBS); |
3687 | sc->sc_pba &= RXPBS_SIZE_MASK_82576; | | 3616 | sc->sc_pba &= RXPBS_SIZE_MASK_82576; |
3688 | break; | | 3617 | break; |
3689 | case WM_T_82580: | | 3618 | case WM_T_82580: |
3690 | case WM_T_I350: | | 3619 | case WM_T_I350: |
3691 | case WM_T_I354: | | 3620 | case WM_T_I354: |
3692 | sc->sc_pba = wm_rxpbs_adjust_82580(CSR_READ(sc, WMREG_RXPBS)); | | 3621 | sc->sc_pba = wm_rxpbs_adjust_82580(CSR_READ(sc, WMREG_RXPBS)); |
3693 | break; | | 3622 | break; |
3694 | case WM_T_I210: | | 3623 | case WM_T_I210: |
3695 | case WM_T_I211: | | 3624 | case WM_T_I211: |
3696 | sc->sc_pba = PBA_34K; | | 3625 | sc->sc_pba = PBA_34K; |
3697 | break; | | 3626 | break; |
3698 | case WM_T_ICH8: | | 3627 | case WM_T_ICH8: |
3699 | /* Workaround for a bit corruption issue in FIFO memory */ | | 3628 | /* Workaround for a bit corruption issue in FIFO memory */ |
3700 | sc->sc_pba = PBA_8K; | | 3629 | sc->sc_pba = PBA_8K; |
3701 | CSR_WRITE(sc, WMREG_PBS, PBA_16K); | | 3630 | CSR_WRITE(sc, WMREG_PBS, PBA_16K); |
3702 | break; | | 3631 | break; |
3703 | case WM_T_ICH9: | | 3632 | case WM_T_ICH9: |
3704 | case WM_T_ICH10: | | 3633 | case WM_T_ICH10: |
3705 | sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 4096 ? | | 3634 | sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 4096 ? |
3706 | PBA_14K : PBA_10K; | | 3635 | PBA_14K : PBA_10K; |
3707 | break; | | 3636 | break; |
3708 | case WM_T_PCH: | | 3637 | case WM_T_PCH: |
3709 | case WM_T_PCH2: | | 3638 | case WM_T_PCH2: |
3710 | case WM_T_PCH_LPT: | | 3639 | case WM_T_PCH_LPT: |
3711 | sc->sc_pba = PBA_26K; | | 3640 | sc->sc_pba = PBA_26K; |
3712 | break; | | 3641 | break; |
3713 | default: | | 3642 | default: |
3714 | sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? | | 3643 | sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? |
3715 | PBA_40K : PBA_48K; | | 3644 | PBA_40K : PBA_48K; |
3716 | break; | | 3645 | break; |
3717 | } | | 3646 | } |
3718 | /* | | 3647 | /* |
3719 | * Only old or non-multiqueue devices have the PBA register | | 3648 | * Only old or non-multiqueue devices have the PBA register |
3720 | * XXX Need special handling for 82575. | | 3649 | * XXX Need special handling for 82575. |
3721 | */ | | 3650 | */ |
3722 | if (((sc->sc_flags & WM_F_NEWQUEUE) == 0) | | 3651 | if (((sc->sc_flags & WM_F_NEWQUEUE) == 0) |
3723 | || (sc->sc_type == WM_T_82575)) | | 3652 | || (sc->sc_type == WM_T_82575)) |
3724 | CSR_WRITE(sc, WMREG_PBA, sc->sc_pba); | | 3653 | CSR_WRITE(sc, WMREG_PBA, sc->sc_pba); |
3725 | | | 3654 | |
3726 | /* Prevent the PCI-E bus from sticking */ | | 3655 | /* Prevent the PCI-E bus from sticking */ |
3727 | if (sc->sc_flags & WM_F_PCIE) { | | 3656 | if (sc->sc_flags & WM_F_PCIE) { |
3728 | int timeout = 800; | | 3657 | int timeout = 800; |
3729 | | | 3658 | |
3730 | sc->sc_ctrl |= CTRL_GIO_M_DIS; | | 3659 | sc->sc_ctrl |= CTRL_GIO_M_DIS; |
3731 | CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); | | 3660 | CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); |
3732 | | | 3661 | |
3733 | while (timeout--) { | | 3662 | while (timeout--) { |
3734 | if ((CSR_READ(sc, WMREG_STATUS) & STATUS_GIO_M_ENA) | | 3663 | if ((CSR_READ(sc, WMREG_STATUS) & STATUS_GIO_M_ENA) |
3735 | == 0) | | 3664 | == 0) |
3736 | break; | | 3665 | break; |
3737 | delay(100); | | 3666 | delay(100); |
3738 | } | | 3667 | } |
3739 | } | | 3668 | } |
3740 | | | 3669 | |
3741 | /* Set the completion timeout for interface */ | | 3670 | /* Set the completion timeout for interface */ |
3742 | if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576) | | 3671 | if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576) |
3743 | || (sc->sc_type == WM_T_82580) | | 3672 | || (sc->sc_type == WM_T_82580) |
3744 | || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354) | | 3673 | || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354) |
3745 | || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211)) | | 3674 | || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211)) |
3746 | wm_set_pcie_completion_timeout(sc); | | 3675 | wm_set_pcie_completion_timeout(sc); |
3747 | | | 3676 | |
3748 | /* Clear interrupt */ | | 3677 | /* Clear interrupt */ |
3749 | CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); | | 3678 | CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); |
3750 | if (sc->sc_nintrs > 1) { | | 3679 | if (sc->sc_nintrs > 1) { |
3751 | if (sc->sc_type != WM_T_82574) { | | 3680 | if (sc->sc_type != WM_T_82574) { |
3752 | CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU); | | 3681 | CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU); |
3753 | CSR_WRITE(sc, WMREG_EIAC, 0); | | 3682 | CSR_WRITE(sc, WMREG_EIAC, 0); |
3754 | } else { | | 3683 | } else { |
3755 | CSR_WRITE(sc, WMREG_EIAC_82574, 0); | | 3684 | CSR_WRITE(sc, WMREG_EIAC_82574, 0); |
3756 | } | | 3685 | } |
3757 | } | | 3686 | } |
3758 | | | 3687 | |
3759 | /* Stop the transmit and receive processes. */ | | 3688 | /* Stop the transmit and receive processes. */ |
3760 | CSR_WRITE(sc, WMREG_RCTL, 0); | | 3689 | CSR_WRITE(sc, WMREG_RCTL, 0); |
3761 | sc->sc_rctl &= ~RCTL_EN; | | 3690 | sc->sc_rctl &= ~RCTL_EN; |
3762 | CSR_WRITE(sc, WMREG_TCTL, TCTL_PSP); | | 3691 | CSR_WRITE(sc, WMREG_TCTL, TCTL_PSP); |
3763 | CSR_WRITE_FLUSH(sc); | | 3692 | CSR_WRITE_FLUSH(sc); |
3764 | | | 3693 | |
3765 | /* XXX set_tbi_sbp_82543() */ | | 3694 | /* XXX set_tbi_sbp_82543() */ |
3766 | | | 3695 | |
3767 | delay(10*1000); | | 3696 | delay(10*1000); |
3768 | | | 3697 | |
3769 | /* Must acquire the MDIO ownership before MAC reset */ | | 3698 | /* Must acquire the MDIO ownership before MAC reset */ |
3770 | switch (sc->sc_type) { | | 3699 | switch (sc->sc_type) { |
3771 | case WM_T_82573: | | 3700 | case WM_T_82573: |
3772 | case WM_T_82574: | | 3701 | case WM_T_82574: |
3773 | case WM_T_82583: | | 3702 | case WM_T_82583: |
3774 | error = wm_get_hw_semaphore_82573(sc); | | 3703 | error = wm_get_hw_semaphore_82573(sc); |
3775 | break; | | 3704 | break; |
3776 | default: | | 3705 | default: |
3777 | break; | | 3706 | break; |
3778 | } | | 3707 | } |
3779 | | | 3708 | |
3780 | /* | | 3709 | /* |
3781 | * 82541 Errata 29? & 82547 Errata 28? | | 3710 | * 82541 Errata 29? & 82547 Errata 28? |
3782 | * See also the description about PHY_RST bit in CTRL register | | 3711 | * See also the description about PHY_RST bit in CTRL register |
3783 | * in 8254x_GBe_SDM.pdf. | | 3712 | * in 8254x_GBe_SDM.pdf. |
3784 | */ | | 3713 | */ |
3785 | if ((sc->sc_type == WM_T_82541) || (sc->sc_type == WM_T_82547)) { | | 3714 | if ((sc->sc_type == WM_T_82541) || (sc->sc_type == WM_T_82547)) { |
3786 | CSR_WRITE(sc, WMREG_CTRL, | | 3715 | CSR_WRITE(sc, WMREG_CTRL, |
3787 | CSR_READ(sc, WMREG_CTRL) | CTRL_PHY_RESET); | | 3716 | CSR_READ(sc, WMREG_CTRL) | CTRL_PHY_RESET); |
3788 | CSR_WRITE_FLUSH(sc); | | 3717 | CSR_WRITE_FLUSH(sc); |
3789 | delay(5000); | | 3718 | delay(5000); |
3790 | } | | 3719 | } |
3791 | | | 3720 | |
3792 | switch (sc->sc_type) { | | 3721 | switch (sc->sc_type) { |
3793 | case WM_T_82544: /* XXX check whether WM_F_IOH_VALID is set */ | | 3722 | case WM_T_82544: /* XXX check whether WM_F_IOH_VALID is set */ |
3794 | case WM_T_82541: | | 3723 | case WM_T_82541: |
3795 | case WM_T_82541_2: | | 3724 | case WM_T_82541_2: |
3796 | case WM_T_82547: | | 3725 | case WM_T_82547: |
3797 | case WM_T_82547_2: | | 3726 | case WM_T_82547_2: |
3798 | /* | | 3727 | /* |
3799 | * On some chipsets, a reset through a memory-mapped write | | 3728 | * On some chipsets, a reset through a memory-mapped write |
3800 | * cycle can cause the chip to reset before completing the | | 3729 | * cycle can cause the chip to reset before completing the |
3801 | * write cycle. This causes major headache that can be | | 3730 | * write cycle. This causes major headache that can be |
3802 | * avoided by issuing the reset via indirect register writes | | 3731 | * avoided by issuing the reset via indirect register writes |
3803 | * through I/O space. | | 3732 | * through I/O space. |
3804 | * | | 3733 | * |
3805 | * So, if we successfully mapped the I/O BAR at attach time, | | 3734 | * So, if we successfully mapped the I/O BAR at attach time, |
3806 | * use that. Otherwise, try our luck with a memory-mapped | | 3735 | * use that. Otherwise, try our luck with a memory-mapped |
3807 | * reset. | | 3736 | * reset. |
3808 | */ | | 3737 | */ |
3809 | if (sc->sc_flags & WM_F_IOH_VALID) | | 3738 | if (sc->sc_flags & WM_F_IOH_VALID) |
3810 | wm_io_write(sc, WMREG_CTRL, CTRL_RST); | | 3739 | wm_io_write(sc, WMREG_CTRL, CTRL_RST); |
3811 | else | | 3740 | else |
3812 | CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); | | 3741 | CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); |
3813 | break; | | 3742 | break; |
3814 | case WM_T_82545_3: | | 3743 | case WM_T_82545_3: |
3815 | case WM_T_82546_3: | | 3744 | case WM_T_82546_3: |
3816 | /* Use the shadow control register on these chips. */ | | 3745 | /* Use the shadow control register on these chips. */ |
3817 | CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST); | | 3746 | CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST); |
3818 | break; | | 3747 | break; |
3819 | case WM_T_80003: | | 3748 | case WM_T_80003: |
3820 | mask = swfwphysem[sc->sc_funcid]; | | 3749 | mask = swfwphysem[sc->sc_funcid]; |
3821 | reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST; | | 3750 | reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST; |
3822 | wm_get_swfw_semaphore(sc, mask); | | 3751 | wm_get_swfw_semaphore(sc, mask); |
3823 | CSR_WRITE(sc, WMREG_CTRL, reg); | | 3752 | CSR_WRITE(sc, WMREG_CTRL, reg); |
3824 | wm_put_swfw_semaphore(sc, mask); | | 3753 | wm_put_swfw_semaphore(sc, mask); |
3825 | break; | | 3754 | break; |
3826 | case WM_T_ICH8: | | 3755 | case WM_T_ICH8: |
3827 | case WM_T_ICH9: | | 3756 | case WM_T_ICH9: |
3828 | case WM_T_ICH10: | | 3757 | case WM_T_ICH10: |
3829 | case WM_T_PCH: | | 3758 | case WM_T_PCH: |
3830 | case WM_T_PCH2: | | 3759 | case WM_T_PCH2: |
3831 | case WM_T_PCH_LPT: | | 3760 | case WM_T_PCH_LPT: |
3832 | reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST; | | 3761 | reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST; |
3833 | if (wm_check_reset_block(sc) == 0) { | | 3762 | if (wm_check_reset_block(sc) == 0) { |
3834 | /* | | 3763 | /* |
3835 | * Gate automatic PHY configuration by hardware on | | 3764 | * Gate automatic PHY configuration by hardware on |
3836 | * non-managed 82579 | | 3765 | * non-managed 82579 |
3837 | */ | | 3766 | */ |
3838 | if ((sc->sc_type == WM_T_PCH2) | | 3767 | if ((sc->sc_type == WM_T_PCH2) |
3839 | && ((CSR_READ(sc, WMREG_FWSM) & FWSM_FW_VALID) | | 3768 | && ((CSR_READ(sc, WMREG_FWSM) & FWSM_FW_VALID) |
3840 | != 0)) | | 3769 | != 0)) |
3841 | wm_gate_hw_phy_config_ich8lan(sc, 1); | | 3770 | wm_gate_hw_phy_config_ich8lan(sc, 1); |
3842 | | | 3771 | |
3843 | | | 3772 | |
3844 | reg |= CTRL_PHY_RESET; | | 3773 | reg |= CTRL_PHY_RESET; |
3845 | phy_reset = 1; | | 3774 | phy_reset = 1; |
3846 | } | | 3775 | } |
3847 | wm_get_swfwhw_semaphore(sc); | | 3776 | wm_get_swfwhw_semaphore(sc); |
3848 | CSR_WRITE(sc, WMREG_CTRL, reg); | | 3777 | CSR_WRITE(sc, WMREG_CTRL, reg); |
3849 | /* Don't insert a completion barrier when reset */ | | 3778 | /* Don't insert a completion barrier when reset */ |
3850 | delay(20*1000); | | 3779 | delay(20*1000); |
3851 | wm_put_swfwhw_semaphore(sc); | | 3780 | wm_put_swfwhw_semaphore(sc); |
3852 | break; | | 3781 | break; |
3853 | case WM_T_82580: | | 3782 | case WM_T_82580: |
3854 | case WM_T_I350: | | 3783 | case WM_T_I350: |
3855 | case WM_T_I354: | | 3784 | case WM_T_I354: |
3856 | case WM_T_I210: | | 3785 | case WM_T_I210: |
3857 | case WM_T_I211: | | 3786 | case WM_T_I211: |
3858 | CSR_WRITE(sc, WMREG_CTRL, CSR_READ(sc, WMREG_CTRL) | CTRL_RST); | | 3787 | CSR_WRITE(sc, WMREG_CTRL, CSR_READ(sc, WMREG_CTRL) | CTRL_RST); |
3859 | if (sc->sc_pcidevid != PCI_PRODUCT_INTEL_DH89XXCC_SGMII) | | 3788 | if (sc->sc_pcidevid != PCI_PRODUCT_INTEL_DH89XXCC_SGMII) |
3860 | CSR_WRITE_FLUSH(sc); | | 3789 | CSR_WRITE_FLUSH(sc); |
3861 | delay(5000); | | 3790 | delay(5000); |
3862 | break; | | 3791 | break; |
3863 | case WM_T_82542_2_0: | | 3792 | case WM_T_82542_2_0: |
3864 | case WM_T_82542_2_1: | | 3793 | case WM_T_82542_2_1: |
3865 | case WM_T_82543: | | 3794 | case WM_T_82543: |
3866 | case WM_T_82540: | | 3795 | case WM_T_82540: |
3867 | case WM_T_82545: | | 3796 | case WM_T_82545: |
3868 | case WM_T_82546: | | 3797 | case WM_T_82546: |
3869 | case WM_T_82571: | | 3798 | case WM_T_82571: |
3870 | case WM_T_82572: | | 3799 | case WM_T_82572: |
3871 | case WM_T_82573: | | 3800 | case WM_T_82573: |
3872 | case WM_T_82574: | | 3801 | case WM_T_82574: |
3873 | case WM_T_82575: | | 3802 | case WM_T_82575: |
3874 | case WM_T_82576: | | 3803 | case WM_T_82576: |
3875 | case WM_T_82583: | | 3804 | case WM_T_82583: |
3876 | default: | | 3805 | default: |
3877 | /* Everything else can safely use the documented method. */ | | 3806 | /* Everything else can safely use the documented method. */ |
3878 | CSR_WRITE(sc, WMREG_CTRL, CSR_READ(sc, WMREG_CTRL) | CTRL_RST); | | 3807 | CSR_WRITE(sc, WMREG_CTRL, CSR_READ(sc, WMREG_CTRL) | CTRL_RST); |
3879 | break; | | 3808 | break; |
3880 | } | | 3809 | } |
3881 | | | 3810 | |
3882 | /* Must release the MDIO ownership after MAC reset */ | | 3811 | /* Must release the MDIO ownership after MAC reset */ |
3883 | switch (sc->sc_type) { | | 3812 | switch (sc->sc_type) { |
3884 | case WM_T_82573: | | 3813 | case WM_T_82573: |
3885 | case WM_T_82574: | | 3814 | case WM_T_82574: |
3886 | case WM_T_82583: | | 3815 | case WM_T_82583: |
3887 | if (error == 0) | | 3816 | if (error == 0) |
3888 | wm_put_hw_semaphore_82573(sc); | | 3817 | wm_put_hw_semaphore_82573(sc); |
3889 | break; | | 3818 | break; |
3890 | default: | | 3819 | default: |
3891 | break; | | 3820 | break; |
3892 | } | | 3821 | } |
3893 | | | 3822 | |
3894 | if (phy_reset != 0) | | 3823 | if (phy_reset != 0) |
3895 | wm_get_cfg_done(sc); | | 3824 | wm_get_cfg_done(sc); |
3896 | | | 3825 | |
3897 | /* reload EEPROM */ | | 3826 | /* reload EEPROM */ |
3898 | switch (sc->sc_type) { | | 3827 | switch (sc->sc_type) { |
3899 | case WM_T_82542_2_0: | | 3828 | case WM_T_82542_2_0: |
3900 | case WM_T_82542_2_1: | | 3829 | case WM_T_82542_2_1: |
3901 | case WM_T_82543: | | 3830 | case WM_T_82543: |
3902 | case WM_T_82544: | | 3831 | case WM_T_82544: |
3903 | delay(10); | | 3832 | delay(10); |
3904 | reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST; | | 3833 | reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST; |
3905 | CSR_WRITE(sc, WMREG_CTRL_EXT, reg); | | 3834 | CSR_WRITE(sc, WMREG_CTRL_EXT, reg); |
3906 | CSR_WRITE_FLUSH(sc); | | 3835 | CSR_WRITE_FLUSH(sc); |
3907 | delay(2000); | | 3836 | delay(2000); |
3908 | break; | | 3837 | break; |
3909 | case WM_T_82540: | | 3838 | case WM_T_82540: |
3910 | case WM_T_82545: | | 3839 | case WM_T_82545: |
3911 | case WM_T_82545_3: | | 3840 | case WM_T_82545_3: |
3912 | case WM_T_82546: | | 3841 | case WM_T_82546: |
3913 | case WM_T_82546_3: | | 3842 | case WM_T_82546_3: |
3914 | delay(5*1000); | | 3843 | delay(5*1000); |
3915 | /* XXX Disable HW ARPs on ASF enabled adapters */ | | 3844 | /* XXX Disable HW ARPs on ASF enabled adapters */ |
3916 | break; | | 3845 | break; |
3917 | case WM_T_82541: | | 3846 | case WM_T_82541: |
3918 | case WM_T_82541_2: | | 3847 | case WM_T_82541_2: |
3919 | case WM_T_82547: | | 3848 | case WM_T_82547: |
3920 | case WM_T_82547_2: | | 3849 | case WM_T_82547_2: |
3921 | delay(20000); | | 3850 | delay(20000); |
3922 | /* XXX Disable HW ARPs on ASF enabled adapters */ | | 3851 | /* XXX Disable HW ARPs on ASF enabled adapters */ |
3923 | break; | | 3852 | break; |
3924 | case WM_T_82571: | | 3853 | case WM_T_82571: |
3925 | case WM_T_82572: | | 3854 | case WM_T_82572: |
3926 | case WM_T_82573: | | 3855 | case WM_T_82573: |
3927 | case WM_T_82574: | | 3856 | case WM_T_82574: |
3928 | case WM_T_82583: | | 3857 | case WM_T_82583: |
3929 | if (sc->sc_flags & WM_F_EEPROM_FLASH) { | | 3858 | if (sc->sc_flags & WM_F_EEPROM_FLASH) { |
3930 | delay(10); | | 3859 | delay(10); |
3931 | reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST; | | 3860 | reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST; |
3932 | CSR_WRITE(sc, WMREG_CTRL_EXT, reg); | | 3861 | CSR_WRITE(sc, WMREG_CTRL_EXT, reg); |
3933 | CSR_WRITE_FLUSH(sc); | | 3862 | CSR_WRITE_FLUSH(sc); |
3934 | } | | 3863 | } |
3935 | /* check EECD_EE_AUTORD */ | | 3864 | /* check EECD_EE_AUTORD */ |
3936 | wm_get_auto_rd_done(sc); | | 3865 | wm_get_auto_rd_done(sc); |
3937 | /* | | 3866 | /* |
3938 | * Phy configuration from NVM just starts after EECD_AUTO_RD | | 3867 | * Phy configuration from NVM just starts after EECD_AUTO_RD |
3939 | * is set. | | 3868 | * is set. |
3940 | */ | | 3869 | */ |
3941 | if ((sc->sc_type == WM_T_82573) || (sc->sc_type == WM_T_82574) | | 3870 | if ((sc->sc_type == WM_T_82573) || (sc->sc_type == WM_T_82574) |
3942 | || (sc->sc_type == WM_T_82583)) | | 3871 | || (sc->sc_type == WM_T_82583)) |
3943 | delay(25*1000); | | 3872 | delay(25*1000); |
3944 | break; | | 3873 | break; |
3945 | case WM_T_82575: | | 3874 | case WM_T_82575: |
3946 | case WM_T_82576: | | 3875 | case WM_T_82576: |
3947 | case WM_T_82580: | | 3876 | case WM_T_82580: |
3948 | case WM_T_I350: | | 3877 | case WM_T_I350: |
3949 | case WM_T_I354: | | 3878 | case WM_T_I354: |
3950 | case WM_T_I210: | | 3879 | case WM_T_I210: |
3951 | case WM_T_I211: | | 3880 | case WM_T_I211: |
3952 | case WM_T_80003: | | 3881 | case WM_T_80003: |
3953 | /* check EECD_EE_AUTORD */ | | 3882 | /* check EECD_EE_AUTORD */ |
3954 | wm_get_auto_rd_done(sc); | | 3883 | wm_get_auto_rd_done(sc); |
3955 | break; | | 3884 | break; |
3956 | case WM_T_ICH8: | | 3885 | case WM_T_ICH8: |
3957 | case WM_T_ICH9: | | 3886 | case WM_T_ICH9: |
3958 | case WM_T_ICH10: | | 3887 | case WM_T_ICH10: |
3959 | case WM_T_PCH: | | 3888 | case WM_T_PCH: |
3960 | case WM_T_PCH2: | | 3889 | case WM_T_PCH2: |
3961 | case WM_T_PCH_LPT: | | 3890 | case WM_T_PCH_LPT: |
3962 | break; | | 3891 | break; |
3963 | default: | | 3892 | default: |
3964 | panic("%s: unknown type\n", __func__); | | 3893 | panic("%s: unknown type\n", __func__); |
3965 | } | | 3894 | } |
3966 | | | 3895 | |
3967 | /* Check whether EEPROM is present or not */ | | 3896 | /* Check whether EEPROM is present or not */ |
3968 | switch (sc->sc_type) { | | 3897 | switch (sc->sc_type) { |
3969 | case WM_T_82575: | | 3898 | case WM_T_82575: |
3970 | case WM_T_82576: | | 3899 | case WM_T_82576: |
3971 | case WM_T_82580: | | 3900 | case WM_T_82580: |
3972 | case WM_T_I350: | | 3901 | case WM_T_I350: |
3973 | case WM_T_I354: | | 3902 | case WM_T_I354: |
3974 | case WM_T_ICH8: | | 3903 | case WM_T_ICH8: |
3975 | case WM_T_ICH9: | | 3904 | case WM_T_ICH9: |
3976 | if ((CSR_READ(sc, WMREG_EECD) & EECD_EE_PRES) == 0) { | | 3905 | if ((CSR_READ(sc, WMREG_EECD) & EECD_EE_PRES) == 0) { |
3977 | /* Not found */ | | 3906 | /* Not found */ |
3978 | sc->sc_flags |= WM_F_EEPROM_INVALID; | | 3907 | sc->sc_flags |= WM_F_EEPROM_INVALID; |
3979 | if (sc->sc_type == WM_T_82575) | | 3908 | if (sc->sc_type == WM_T_82575) |
3980 | wm_reset_init_script_82575(sc); | | 3909 | wm_reset_init_script_82575(sc); |
3981 | } | | 3910 | } |
3982 | break; | | 3911 | break; |
3983 | default: | | 3912 | default: |
3984 | break; | | 3913 | break; |
3985 | } | | 3914 | } |
3986 | | | 3915 | |
3987 | if ((sc->sc_type == WM_T_82580) | | 3916 | if ((sc->sc_type == WM_T_82580) |
3988 | || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)) { | | 3917 | || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)) { |
3989 | /* clear global device reset status bit */ | | 3918 | /* clear global device reset status bit */ |
3990 | CSR_WRITE(sc, WMREG_STATUS, STATUS_DEV_RST_SET); | | 3919 | CSR_WRITE(sc, WMREG_STATUS, STATUS_DEV_RST_SET); |
3991 | } | | 3920 | } |
3992 | | | 3921 | |
3993 | /* Clear any pending interrupt events. */ | | 3922 | /* Clear any pending interrupt events. */ |
3994 | CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); | | 3923 | CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); |
3995 | reg = CSR_READ(sc, WMREG_ICR); | | 3924 | reg = CSR_READ(sc, WMREG_ICR); |
3996 | if (sc->sc_nintrs > 1) { | | 3925 | if (sc->sc_nintrs > 1) { |
3997 | if (sc->sc_type != WM_T_82574) { | | 3926 | if (sc->sc_type != WM_T_82574) { |
3998 | CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU); | | 3927 | CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU); |
3999 | CSR_WRITE(sc, WMREG_EIAC, 0); | | 3928 | CSR_WRITE(sc, WMREG_EIAC, 0); |
4000 | } else | | 3929 | } else |
4001 | CSR_WRITE(sc, WMREG_EIAC_82574, 0); | | 3930 | CSR_WRITE(sc, WMREG_EIAC_82574, 0); |
4002 | } | | 3931 | } |
4003 | | | 3932 | |
4004 | /* reload sc_ctrl */ | | 3933 | /* reload sc_ctrl */ |
4005 | sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL); | | 3934 | sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL); |
4006 | | | 3935 | |
4007 | if ((sc->sc_type >= WM_T_I350) && (sc->sc_type <= WM_T_I211)) | | 3936 | if ((sc->sc_type >= WM_T_I350) && (sc->sc_type <= WM_T_I211)) |
4008 | wm_set_eee_i350(sc); | | 3937 | wm_set_eee_i350(sc); |
4009 | | | 3938 | |
4010 | /* dummy read from WUC */ | | 3939 | /* dummy read from WUC */ |
4011 | if (sc->sc_type == WM_T_PCH) | | 3940 | if (sc->sc_type == WM_T_PCH) |
4012 | reg = wm_gmii_hv_readreg(sc->sc_dev, 1, BM_WUC); | | 3941 | reg = wm_gmii_hv_readreg(sc->sc_dev, 1, BM_WUC); |
4013 | /* | | 3942 | /* |
4014 | * For PCH, this write will make sure that any noise will be detected | | 3943 | * For PCH, this write will make sure that any noise will be detected |
4015 | * as a CRC error and be dropped rather than show up as a bad packet | | 3944 | * as a CRC error and be dropped rather than show up as a bad packet |
4016 | * to the DMA engine | | 3945 | * to the DMA engine |
4017 | */ | | 3946 | */ |
4018 | if (sc->sc_type == WM_T_PCH) | | 3947 | if (sc->sc_type == WM_T_PCH) |
4019 | CSR_WRITE(sc, WMREG_CRC_OFFSET, 0x65656565); | | 3948 | CSR_WRITE(sc, WMREG_CRC_OFFSET, 0x65656565); |
4020 | | | 3949 | |
4021 | if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) | | 3950 | if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) |
4022 | CSR_WRITE(sc, WMREG_WUC, 0); | | 3951 | CSR_WRITE(sc, WMREG_WUC, 0); |
4023 | | | 3952 | |
4024 | wm_reset_mdicnfg_82580(sc); | | 3953 | wm_reset_mdicnfg_82580(sc); |
4025 | | | 3954 | |
4026 | if ((sc->sc_flags & WM_F_PLL_WA_I210) != 0) | | 3955 | if ((sc->sc_flags & WM_F_PLL_WA_I210) != 0) |
4027 | wm_pll_workaround_i210(sc); | | 3956 | wm_pll_workaround_i210(sc); |
4028 | } | | 3957 | } |
4029 | | | 3958 | |
4030 | /* | | 3959 | /* |
4031 | * wm_add_rxbuf: | | 3960 | * wm_add_rxbuf: |
4032 | * | | 3961 | * |
4033 | * Add a receive buffer to the indiciated descriptor. | | 3962 | * Add a receive buffer to the indiciated descriptor. |
4034 | */ | | 3963 | */ |
4035 | static int | | 3964 | static int |
4036 | wm_add_rxbuf(struct wm_softc *sc, int idx) | | 3965 | wm_add_rxbuf(struct wm_softc *sc, int idx) |
4037 | { | | 3966 | { |
4038 | struct wm_rxqueue *rxq = sc->sc_rxq; | | 3967 | struct wm_rxqueue *rxq = sc->sc_rxq; |
4039 | struct wm_rxsoft *rxs = &rxq->rxq_soft[idx]; | | 3968 | struct wm_rxsoft *rxs = &rxq->rxq_soft[idx]; |
4040 | struct mbuf *m; | | 3969 | struct mbuf *m; |
4041 | int error; | | 3970 | int error; |
4042 | | | 3971 | |
4043 | KASSERT(WM_RX_LOCKED(rxq)); | | 3972 | KASSERT(WM_RX_LOCKED(rxq)); |
4044 | | | 3973 | |
4045 | MGETHDR(m, M_DONTWAIT, MT_DATA); | | 3974 | MGETHDR(m, M_DONTWAIT, MT_DATA); |
4046 | if (m == NULL) | | 3975 | if (m == NULL) |
4047 | return ENOBUFS; | | 3976 | return ENOBUFS; |
4048 | | | 3977 | |
4049 | MCLGET(m, M_DONTWAIT); | | 3978 | MCLGET(m, M_DONTWAIT); |
4050 | if ((m->m_flags & M_EXT) == 0) { | | 3979 | if ((m->m_flags & M_EXT) == 0) { |
4051 | m_freem(m); | | 3980 | m_freem(m); |
4052 | return ENOBUFS; | | 3981 | return ENOBUFS; |
4053 | } | | 3982 | } |
4054 | | | 3983 | |
4055 | if (rxs->rxs_mbuf != NULL) | | 3984 | if (rxs->rxs_mbuf != NULL) |
4056 | bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); | | 3985 | bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); |
4057 | | | 3986 | |
4058 | rxs->rxs_mbuf = m; | | 3987 | rxs->rxs_mbuf = m; |
4059 | | | 3988 | |
4060 | m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; | | 3989 | m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; |
4061 | error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, | | 3990 | error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, |
4062 | BUS_DMA_READ|BUS_DMA_NOWAIT); | | 3991 | BUS_DMA_READ|BUS_DMA_NOWAIT); |
4063 | if (error) { | | 3992 | if (error) { |
4064 | /* XXX XXX XXX */ | | 3993 | /* XXX XXX XXX */ |
4065 | aprint_error_dev(sc->sc_dev, | | 3994 | aprint_error_dev(sc->sc_dev, |
4066 | "unable to load rx DMA map %d, error = %d\n", | | 3995 | "unable to load rx DMA map %d, error = %d\n", |
4067 | idx, error); | | 3996 | idx, error); |
4068 | panic("wm_add_rxbuf"); | | 3997 | panic("wm_add_rxbuf"); |
4069 | } | | 3998 | } |
4070 | | | 3999 | |
4071 | bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, | | 4000 | bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, |
4072 | rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); | | 4001 | rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); |
4073 | | | 4002 | |
4074 | if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) { | | 4003 | if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) { |
4075 | if ((sc->sc_rctl & RCTL_EN) != 0) | | 4004 | if ((sc->sc_rctl & RCTL_EN) != 0) |
4076 | wm_init_rxdesc(sc, idx); | | 4005 | wm_init_rxdesc(sc, idx); |
4077 | } else | | 4006 | } else |
4078 | wm_init_rxdesc(sc, idx); | | 4007 | wm_init_rxdesc(sc, idx); |
4079 | | | 4008 | |
4080 | return 0; | | 4009 | return 0; |
4081 | } | | 4010 | } |
4082 | | | 4011 | |
4083 | /* | | 4012 | /* |
4084 | * wm_rxdrain: | | 4013 | * wm_rxdrain: |
4085 | * | | 4014 | * |
4086 | * Drain the receive queue. | | 4015 | * Drain the receive queue. |
4087 | */ | | 4016 | */ |
4088 | static void | | 4017 | static void |
4089 | wm_rxdrain(struct wm_softc *sc) | | 4018 | wm_rxdrain(struct wm_softc *sc) |
4090 | { | | 4019 | { |
4091 | struct wm_rxqueue *rxq = sc->sc_rxq; | | 4020 | struct wm_rxqueue *rxq = sc->sc_rxq; |
4092 | struct wm_rxsoft *rxs; | | 4021 | struct wm_rxsoft *rxs; |
4093 | int i; | | 4022 | int i; |
4094 | | | 4023 | |
4095 | KASSERT(WM_RX_LOCKED(rxq)); | | 4024 | KASSERT(WM_RX_LOCKED(rxq)); |
4096 | | | 4025 | |
4097 | for (i = 0; i < WM_NRXDESC; i++) { | | 4026 | for (i = 0; i < WM_NRXDESC; i++) { |
4098 | rxs = &rxq->rxq_soft[i]; | | 4027 | rxs = &rxq->rxq_soft[i]; |
4099 | if (rxs->rxs_mbuf != NULL) { | | 4028 | if (rxs->rxs_mbuf != NULL) { |
4100 | bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); | | 4029 | bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); |
4101 | m_freem(rxs->rxs_mbuf); | | 4030 | m_freem(rxs->rxs_mbuf); |
4102 | rxs->rxs_mbuf = NULL; | | 4031 | rxs->rxs_mbuf = NULL; |
4103 | } | | 4032 | } |
4104 | } | | 4033 | } |
4105 | } | | 4034 | } |
4106 | | | 4035 | |
| | | 4036 | |
| | | 4037 | #ifdef WM_MSI_MSIX |
| | | 4038 | /* |
| | | 4039 | * Both single interrupt MSI and INTx can use this function. |
| | | 4040 | */ |
| | | 4041 | static int |
| | | 4042 | wm_setup_legacy(struct wm_softc *sc) |
| | | 4043 | { |
| | | 4044 | pci_chipset_tag_t pc = sc->sc_pc; |
| | | 4045 | const char *intrstr = NULL; |
| | | 4046 | char intrbuf[PCI_INTRSTR_LEN]; |
| | | 4047 | |
| | | 4048 | intrstr = pci_intr_string(pc, sc->sc_intrs[0], intrbuf, |
| | | 4049 | sizeof(intrbuf)); |
| | | 4050 | #ifdef WM_MPSAFE |
| | | 4051 | pci_intr_setattr(pc, &sc->sc_intrs[0], PCI_INTR_MPSAFE, true); |
| | | 4052 | #endif |
| | | 4053 | sc->sc_ihs[0] = pci_intr_establish_xname(pc, sc->sc_intrs[0], |
| | | 4054 | IPL_NET, wm_intr_legacy, sc, device_xname(sc->sc_dev)); |
| | | 4055 | if (sc->sc_ihs[0] == NULL) { |
| | | 4056 | aprint_error_dev(sc->sc_dev,"unable to establish %s\n", |
| | | 4057 | (pci_intr_type(sc->sc_intrs[0]) |
| | | 4058 | == PCI_INTR_TYPE_MSI) ? "MSI" : "INTx"); |
| | | 4059 | return ENOMEM; |
| | | 4060 | } |
| | | 4061 | |
| | | 4062 | aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); |
| | | 4063 | sc->sc_nintrs = 1; |
| | | 4064 | return 0; |
| | | 4065 | } |
| | | 4066 | |
| | | 4067 | struct _msix_matrix { |
| | | 4068 | const char *intrname; |
| | | 4069 | int(*func)(void *); |
| | | 4070 | int intridx; |
| | | 4071 | int cpuid; |
| | | 4072 | } msix_matrix[WM_MSIX_NINTR] = { |
| | | 4073 | { "TX", wm_txintr_msix, WM_MSIX_TXINTR_IDX, WM_MSIX_TXINTR_CPUID }, |
| | | 4074 | { "RX", wm_rxintr_msix, WM_MSIX_RXINTR_IDX, WM_MSIX_RXINTR_CPUID }, |
| | | 4075 | { "LINK", wm_linkintr_msix, WM_MSIX_LINKINTR_IDX, |
| | | 4076 | WM_MSIX_LINKINTR_CPUID }, |
| | | 4077 | }; |
| | | 4078 | |
| | | 4079 | static int |
| | | 4080 | wm_setup_msix(struct wm_softc *sc) |
| | | 4081 | { |
| | | 4082 | void *vih; |
| | | 4083 | kcpuset_t *affinity; |
| | | 4084 | int i, error; |
| | | 4085 | pci_chipset_tag_t pc = sc->sc_pc; |
| | | 4086 | const char *intrstr = NULL; |
| | | 4087 | char intrbuf[PCI_INTRSTR_LEN]; |
| | | 4088 | char intr_xname[INTRDEVNAMEBUF]; |
| | | 4089 | |
| | | 4090 | kcpuset_create(&affinity, false); |
| | | 4091 | |
| | | 4092 | for (i = 0; i < WM_MSIX_NINTR; i++) { |
| | | 4093 | intrstr = pci_intr_string(pc, |
| | | 4094 | sc->sc_intrs[msix_matrix[i].intridx], intrbuf, |
| | | 4095 | sizeof(intrbuf)); |
| | | 4096 | #ifdef WM_MPSAFE |
| | | 4097 | pci_intr_setattr(pc, |
| | | 4098 | &sc->sc_intrs[msix_matrix[i].intridx], |
| | | 4099 | PCI_INTR_MPSAFE, true); |
| | | 4100 | #endif |
| | | 4101 | memset(intr_xname, 0, sizeof(intr_xname)); |
| | | 4102 | strlcat(intr_xname, device_xname(sc->sc_dev), |
| | | 4103 | sizeof(intr_xname)); |
| | | 4104 | strlcat(intr_xname, msix_matrix[i].intrname, |
| | | 4105 | sizeof(intr_xname)); |
| | | 4106 | vih = pci_intr_establish_xname(pc, |
| | | 4107 | sc->sc_intrs[msix_matrix[i].intridx], IPL_NET, |
| | | 4108 | msix_matrix[i].func, sc, intr_xname); |
| | | 4109 | if (vih == NULL) { |
| | | 4110 | aprint_error_dev(sc->sc_dev, |
| | | 4111 | "unable to establish MSI-X(for %s)%s%s\n", |
| | | 4112 | msix_matrix[i].intrname, |
| | | 4113 | intrstr ? " at " : "", |
| | | 4114 | intrstr ? intrstr : ""); |
| | | 4115 | kcpuset_destroy(affinity); |
| | | 4116 | |
| | | 4117 | return ENOMEM; |
| | | 4118 | } |
| | | 4119 | kcpuset_zero(affinity); |
| | | 4120 | /* Round-robin affinity */ |
| | | 4121 | kcpuset_set(affinity, msix_matrix[i].cpuid % ncpu); |
| | | 4122 | error = interrupt_distribute(vih, affinity, NULL); |
| | | 4123 | if (error == 0) { |
| | | 4124 | aprint_normal_dev(sc->sc_dev, |
| | | 4125 | "for %s interrupting at %s affinity to %u\n", |
| | | 4126 | msix_matrix[i].intrname, intrstr, |
| | | 4127 | msix_matrix[i].cpuid % ncpu); |
| | | 4128 | } else { |
| | | 4129 | aprint_normal_dev(sc->sc_dev, |
| | | 4130 | "for %s interrupting at %s\n", |
| | | 4131 | msix_matrix[i].intrname, intrstr); |
| | | 4132 | } |
| | | 4133 | sc->sc_ihs[msix_matrix[i].intridx] = vih; |
| | | 4134 | } |
| | | 4135 | |
| | | 4136 | sc->sc_nintrs = WM_MSIX_NINTR; |
| | | 4137 | kcpuset_destroy(affinity); |
| | | 4138 | return 0; |
| | | 4139 | } |
| | | 4140 | #endif |
| | | 4141 | |
4107 | /* | | 4142 | /* |
4108 | * wm_init: [ifnet interface function] | | 4143 | * wm_init: [ifnet interface function] |
4109 | * | | 4144 | * |
4110 | * Initialize the interface. | | 4145 | * Initialize the interface. |
4111 | */ | | 4146 | */ |
4112 | static int | | 4147 | static int |
4113 | wm_init(struct ifnet *ifp) | | 4148 | wm_init(struct ifnet *ifp) |
4114 | { | | 4149 | { |
4115 | struct wm_softc *sc = ifp->if_softc; | | 4150 | struct wm_softc *sc = ifp->if_softc; |
4116 | int ret; | | 4151 | int ret; |
4117 | | | 4152 | |
4118 | WM_CORE_LOCK(sc); | | 4153 | WM_CORE_LOCK(sc); |
4119 | ret = wm_init_locked(ifp); | | 4154 | ret = wm_init_locked(ifp); |
4120 | WM_CORE_UNLOCK(sc); | | 4155 | WM_CORE_UNLOCK(sc); |
4121 | | | 4156 | |
4122 | return ret; | | 4157 | return ret; |
4123 | } | | 4158 | } |
4124 | | | 4159 | |
4125 | static int | | 4160 | static int |
4126 | wm_init_locked(struct ifnet *ifp) | | 4161 | wm_init_locked(struct ifnet *ifp) |
4127 | { | | 4162 | { |
4128 | struct wm_softc *sc = ifp->if_softc; | | 4163 | struct wm_softc *sc = ifp->if_softc; |
4129 | int i, j, trynum, error = 0; | | 4164 | int i, j, trynum, error = 0; |
4130 | uint32_t reg; | | 4165 | uint32_t reg; |
4131 | | | 4166 | |
4132 | KASSERT(WM_CORE_LOCKED(sc)); | | 4167 | KASSERT(WM_CORE_LOCKED(sc)); |
4133 | /* | | 4168 | /* |
4134 | * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. | | 4169 | * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. |
4135 | * There is a small but measurable benefit to avoiding the adjusment | | 4170 | * There is a small but measurable benefit to avoiding the adjusment |
4136 | * of the descriptor so that the headers are aligned, for normal mtu, | | 4171 | * of the descriptor so that the headers are aligned, for normal mtu, |
4137 | * on such platforms. One possibility is that the DMA itself is | | 4172 | * on such platforms. One possibility is that the DMA itself is |
4138 | * slightly more efficient if the front of the entire packet (instead | | 4173 | * slightly more efficient if the front of the entire packet (instead |
4139 | * of the front of the headers) is aligned. | | 4174 | * of the front of the headers) is aligned. |
4140 | * | | 4175 | * |
4141 | * Note we must always set align_tweak to 0 if we are using | | 4176 | * Note we must always set align_tweak to 0 if we are using |
4142 | * jumbo frames. | | 4177 | * jumbo frames. |
4143 | */ | | 4178 | */ |
4144 | #ifdef __NO_STRICT_ALIGNMENT | | 4179 | #ifdef __NO_STRICT_ALIGNMENT |
4145 | sc->sc_align_tweak = 0; | | 4180 | sc->sc_align_tweak = 0; |
4146 | #else | | 4181 | #else |
4147 | if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) | | 4182 | if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) |
4148 | sc->sc_align_tweak = 0; | | 4183 | sc->sc_align_tweak = 0; |
4149 | else | | 4184 | else |
4150 | sc->sc_align_tweak = 2; | | 4185 | sc->sc_align_tweak = 2; |
4151 | #endif /* __NO_STRICT_ALIGNMENT */ | | 4186 | #endif /* __NO_STRICT_ALIGNMENT */ |
4152 | | | 4187 | |
4153 | /* Cancel any pending I/O. */ | | 4188 | /* Cancel any pending I/O. */ |
4154 | wm_stop_locked(ifp, 0); | | 4189 | wm_stop_locked(ifp, 0); |
4155 | | | 4190 | |
4156 | /* update statistics before reset */ | | 4191 | /* update statistics before reset */ |
4157 | ifp->if_collisions += CSR_READ(sc, WMREG_COLC); | | 4192 | ifp->if_collisions += CSR_READ(sc, WMREG_COLC); |
4158 | ifp->if_ierrors += CSR_READ(sc, WMREG_RXERRC); | | 4193 | ifp->if_ierrors += CSR_READ(sc, WMREG_RXERRC); |
4159 | | | 4194 | |
4160 | /* Reset the chip to a known state. */ | | 4195 | /* Reset the chip to a known state. */ |
4161 | wm_reset(sc); | | 4196 | wm_reset(sc); |
4162 | | | 4197 | |
4163 | switch (sc->sc_type) { | | 4198 | switch (sc->sc_type) { |
4164 | case WM_T_82571: | | 4199 | case WM_T_82571: |
4165 | case WM_T_82572: | | 4200 | case WM_T_82572: |
4166 | case WM_T_82573: | | 4201 | case WM_T_82573: |
4167 | case WM_T_82574: | | 4202 | case WM_T_82574: |
4168 | case WM_T_82583: | | 4203 | case WM_T_82583: |
4169 | case WM_T_80003: | | 4204 | case WM_T_80003: |
4170 | case WM_T_ICH8: | | 4205 | case WM_T_ICH8: |
4171 | case WM_T_ICH9: | | 4206 | case WM_T_ICH9: |
4172 | case WM_T_ICH10: | | 4207 | case WM_T_ICH10: |
4173 | case WM_T_PCH: | | 4208 | case WM_T_PCH: |
4174 | case WM_T_PCH2: | | 4209 | case WM_T_PCH2: |
4175 | case WM_T_PCH_LPT: | | 4210 | case WM_T_PCH_LPT: |
4176 | if (wm_check_mng_mode(sc) != 0) | | 4211 | if (wm_check_mng_mode(sc) != 0) |
4177 | wm_get_hw_control(sc); | | 4212 | wm_get_hw_control(sc); |
4178 | break; | | 4213 | break; |
4179 | default: | | 4214 | default: |
4180 | break; | | 4215 | break; |
4181 | } | | 4216 | } |
4182 | | | 4217 | |
4183 | /* Init hardware bits */ | | 4218 | /* Init hardware bits */ |
4184 | wm_initialize_hardware_bits(sc); | | 4219 | wm_initialize_hardware_bits(sc); |
4185 | | | 4220 | |
4186 | /* Reset the PHY. */ | | 4221 | /* Reset the PHY. */ |
4187 | if (sc->sc_flags & WM_F_HAS_MII) | | 4222 | if (sc->sc_flags & WM_F_HAS_MII) |
4188 | wm_gmii_reset(sc); | | 4223 | wm_gmii_reset(sc); |
4189 | | | 4224 | |
4190 | /* Calculate (E)ITR value */ | | 4225 | /* Calculate (E)ITR value */ |
4191 | if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) { | | 4226 | if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) { |
4192 | sc->sc_itr = 450; /* For EITR */ | | 4227 | sc->sc_itr = 450; /* For EITR */ |
4193 | } else if (sc->sc_type >= WM_T_82543) { | | 4228 | } else if (sc->sc_type >= WM_T_82543) { |
4194 | /* | | 4229 | /* |
4195 | * Set up the interrupt throttling register (units of 256ns) | | 4230 | * Set up the interrupt throttling register (units of 256ns) |
4196 | * Note that a footnote in Intel's documentation says this | | 4231 | * Note that a footnote in Intel's documentation says this |
4197 | * ticker runs at 1/4 the rate when the chip is in 100Mbit | | 4232 | * ticker runs at 1/4 the rate when the chip is in 100Mbit |
4198 | * or 10Mbit mode. Empirically, it appears to be the case | | 4233 | * or 10Mbit mode. Empirically, it appears to be the case |
4199 | * that that is also true for the 1024ns units of the other | | 4234 | * that that is also true for the 1024ns units of the other |
4200 | * interrupt-related timer registers -- so, really, we ought | | 4235 | * interrupt-related timer registers -- so, really, we ought |
4201 | * to divide this value by 4 when the link speed is low. | | 4236 | * to divide this value by 4 when the link speed is low. |
4202 | * | | 4237 | * |
4203 | * XXX implement this division at link speed change! | | 4238 | * XXX implement this division at link speed change! |
4204 | */ | | 4239 | */ |
4205 | | | 4240 | |
4206 | /* | | 4241 | /* |
4207 | * For N interrupts/sec, set this value to: | | 4242 | * For N interrupts/sec, set this value to: |
4208 | * 1000000000 / (N * 256). Note that we set the | | 4243 | * 1000000000 / (N * 256). Note that we set the |
4209 | * absolute and packet timer values to this value | | 4244 | * absolute and packet timer values to this value |
4210 | * divided by 4 to get "simple timer" behavior. | | 4245 | * divided by 4 to get "simple timer" behavior. |
4211 | */ | | 4246 | */ |
4212 | | | 4247 | |
4213 | sc->sc_itr = 1500; /* 2604 ints/sec */ | | 4248 | sc->sc_itr = 1500; /* 2604 ints/sec */ |
4214 | } | | 4249 | } |
4215 | | | 4250 | |
4216 | error = wm_init_txrx_queues(sc); | | 4251 | error = wm_init_txrx_queues(sc); |
4217 | if (error) | | 4252 | if (error) |
4218 | goto out; | | 4253 | goto out; |
4219 | | | 4254 | |
4220 | /* | | 4255 | /* |
4221 | * Clear out the VLAN table -- we don't use it (yet). | | 4256 | * Clear out the VLAN table -- we don't use it (yet). |
4222 | */ | | 4257 | */ |
4223 | CSR_WRITE(sc, WMREG_VET, 0); | | 4258 | CSR_WRITE(sc, WMREG_VET, 0); |
4224 | if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)) | | 4259 | if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)) |
4225 | trynum = 10; /* Due to hw errata */ | | 4260 | trynum = 10; /* Due to hw errata */ |
4226 | else | | 4261 | else |
4227 | trynum = 1; | | 4262 | trynum = 1; |
4228 | for (i = 0; i < WM_VLAN_TABSIZE; i++) | | 4263 | for (i = 0; i < WM_VLAN_TABSIZE; i++) |
4229 | for (j = 0; j < trynum; j++) | | 4264 | for (j = 0; j < trynum; j++) |
4230 | CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0); | | 4265 | CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0); |
4231 | | | 4266 | |
4232 | /* | | 4267 | /* |
4233 | * Set up flow-control parameters. | | 4268 | * Set up flow-control parameters. |
4234 | * | | 4269 | * |
4235 | * XXX Values could probably stand some tuning. | | 4270 | * XXX Values could probably stand some tuning. |
4236 | */ | | 4271 | */ |
4237 | if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9) | | 4272 | if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9) |
4238 | && (sc->sc_type != WM_T_ICH10) && (sc->sc_type != WM_T_PCH) | | 4273 | && (sc->sc_type != WM_T_ICH10) && (sc->sc_type != WM_T_PCH) |
4239 | && (sc->sc_type != WM_T_PCH2) && (sc->sc_type != WM_T_PCH_LPT)) { | | 4274 | && (sc->sc_type != WM_T_PCH2) && (sc->sc_type != WM_T_PCH_LPT)) { |
4240 | CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST); | | 4275 | CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST); |
4241 | CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST); | | 4276 | CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST); |
4242 | CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL); | | 4277 | CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL); |
4243 | } | | 4278 | } |
4244 | | | 4279 | |
4245 | sc->sc_fcrtl = FCRTL_DFLT; | | 4280 | sc->sc_fcrtl = FCRTL_DFLT; |
4246 | if (sc->sc_type < WM_T_82543) { | | 4281 | if (sc->sc_type < WM_T_82543) { |
4247 | CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT); | | 4282 | CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT); |
4248 | CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl); | | 4283 | CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl); |
4249 | } else { | | 4284 | } else { |
4250 | CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT); | | 4285 | CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT); |
4251 | CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl); | | 4286 | CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl); |
4252 | } | | 4287 | } |
4253 | | | 4288 | |
4254 | if (sc->sc_type == WM_T_80003) | | 4289 | if (sc->sc_type == WM_T_80003) |
4255 | CSR_WRITE(sc, WMREG_FCTTV, 0xffff); | | 4290 | CSR_WRITE(sc, WMREG_FCTTV, 0xffff); |
4256 | else | | 4291 | else |
4257 | CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT); | | 4292 | CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT); |
4258 | | | 4293 | |
4259 | /* Writes the control register. */ | | 4294 | /* Writes the control register. */ |
4260 | wm_set_vlan(sc); | | 4295 | wm_set_vlan(sc); |
4261 | | | 4296 | |
4262 | if (sc->sc_flags & WM_F_HAS_MII) { | | 4297 | if (sc->sc_flags & WM_F_HAS_MII) { |
4263 | int val; | | 4298 | int val; |
4264 | | | 4299 | |
4265 | switch (sc->sc_type) { | | 4300 | switch (sc->sc_type) { |
4266 | case WM_T_80003: | | 4301 | case WM_T_80003: |
4267 | case WM_T_ICH8: | | 4302 | case WM_T_ICH8: |
4268 | case WM_T_ICH9: | | 4303 | case WM_T_ICH9: |
4269 | case WM_T_ICH10: | | 4304 | case WM_T_ICH10: |
4270 | case WM_T_PCH: | | 4305 | case WM_T_PCH: |
4271 | case WM_T_PCH2: | | 4306 | case WM_T_PCH2: |
4272 | case WM_T_PCH_LPT: | | 4307 | case WM_T_PCH_LPT: |
4273 | /* | | 4308 | /* |
4274 | * Set the mac to wait the maximum time between each | | 4309 | * Set the mac to wait the maximum time between each |
4275 | * iteration and increase the max iterations when | | 4310 | * iteration and increase the max iterations when |
4276 | * polling the phy; this fixes erroneous timeouts at | | 4311 | * polling the phy; this fixes erroneous timeouts at |
4277 | * 10Mbps. | | 4312 | * 10Mbps. |
4278 | */ | | 4313 | */ |
4279 | wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_TIMEOUTS, | | 4314 | wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_TIMEOUTS, |
4280 | 0xFFFF); | | 4315 | 0xFFFF); |
4281 | val = wm_kmrn_readreg(sc, | | 4316 | val = wm_kmrn_readreg(sc, |
4282 | KUMCTRLSTA_OFFSET_INB_PARAM); | | 4317 | KUMCTRLSTA_OFFSET_INB_PARAM); |
4283 | val |= 0x3F; | | 4318 | val |= 0x3F; |
4284 | wm_kmrn_writereg(sc, | | 4319 | wm_kmrn_writereg(sc, |
4285 | KUMCTRLSTA_OFFSET_INB_PARAM, val); | | 4320 | KUMCTRLSTA_OFFSET_INB_PARAM, val); |
4286 | break; | | 4321 | break; |
4287 | default: | | 4322 | default: |
4288 | break; | | 4323 | break; |
4289 | } | | 4324 | } |
4290 | | | 4325 | |
4291 | if (sc->sc_type == WM_T_80003) { | | 4326 | if (sc->sc_type == WM_T_80003) { |
4292 | val = CSR_READ(sc, WMREG_CTRL_EXT); | | 4327 | val = CSR_READ(sc, WMREG_CTRL_EXT); |
4293 | val &= ~CTRL_EXT_LINK_MODE_MASK; | | 4328 | val &= ~CTRL_EXT_LINK_MODE_MASK; |
4294 | CSR_WRITE(sc, WMREG_CTRL_EXT, val); | | 4329 | CSR_WRITE(sc, WMREG_CTRL_EXT, val); |
4295 | | | 4330 | |
4296 | /* Bypass RX and TX FIFO's */ | | 4331 | /* Bypass RX and TX FIFO's */ |
4297 | wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_FIFO_CTRL, | | 4332 | wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_FIFO_CTRL, |
4298 | KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | | 4333 | KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
4299 | | KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); | | 4334 | | KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); |
4300 | wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_INB_CTRL, | | 4335 | wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_INB_CTRL, |
4301 | KUMCTRLSTA_INB_CTRL_DIS_PADDING | | | 4336 | KUMCTRLSTA_INB_CTRL_DIS_PADDING | |
4302 | KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT); | | 4337 | KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT); |
4303 | } | | 4338 | } |
4304 | } | | 4339 | } |
4305 | #if 0 | | 4340 | #if 0 |
4306 | CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); | | 4341 | CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); |
4307 | #endif | | 4342 | #endif |
4308 | | | 4343 | |
4309 | /* Set up checksum offload parameters. */ | | 4344 | /* Set up checksum offload parameters. */ |
4310 | reg = CSR_READ(sc, WMREG_RXCSUM); | | 4345 | reg = CSR_READ(sc, WMREG_RXCSUM); |
4311 | reg &= ~(RXCSUM_IPOFL | RXCSUM_IPV6OFL | RXCSUM_TUOFL); | | 4346 | reg &= ~(RXCSUM_IPOFL | RXCSUM_IPV6OFL | RXCSUM_TUOFL); |
4312 | if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) | | 4347 | if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) |
4313 | reg |= RXCSUM_IPOFL; | | 4348 | reg |= RXCSUM_IPOFL; |
4314 | if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) | | 4349 | if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) |
4315 | reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; | | 4350 | reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; |
4316 | if (ifp->if_capenable & (IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) | | 4351 | if (ifp->if_capenable & (IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) |
4317 | reg |= RXCSUM_IPV6OFL | RXCSUM_TUOFL; | | 4352 | reg |= RXCSUM_IPV6OFL | RXCSUM_TUOFL; |
4318 | CSR_WRITE(sc, WMREG_RXCSUM, reg); | | 4353 | CSR_WRITE(sc, WMREG_RXCSUM, reg); |
4319 | | | 4354 | |
4320 | /* Set up MSI-X */ | | 4355 | /* Set up MSI-X */ |
4321 | if (sc->sc_nintrs > 1) { | | 4356 | if (sc->sc_nintrs > 1) { |
4322 | uint32_t ivar; | | 4357 | uint32_t ivar; |
4323 | | | 4358 | |
4324 | if (sc->sc_type == WM_T_82575) { | | 4359 | if (sc->sc_type == WM_T_82575) { |
4325 | /* Interrupt control */ | | 4360 | /* Interrupt control */ |
4326 | reg = CSR_READ(sc, WMREG_CTRL_EXT); | | 4361 | reg = CSR_READ(sc, WMREG_CTRL_EXT); |
4327 | reg |= CTRL_EXT_PBA | CTRL_EXT_EIAME | CTRL_EXT_NSICR; | | 4362 | reg |= CTRL_EXT_PBA | CTRL_EXT_EIAME | CTRL_EXT_NSICR; |
4328 | CSR_WRITE(sc, WMREG_CTRL_EXT, reg); | | 4363 | CSR_WRITE(sc, WMREG_CTRL_EXT, reg); |
4329 | | | 4364 | |
4330 | /* TX */ | | 4365 | /* TX */ |
4331 | CSR_WRITE(sc, WMREG_MSIXBM(WM_MSIX_TXINTR_IDX), | | 4366 | CSR_WRITE(sc, WMREG_MSIXBM(WM_MSIX_TXINTR_IDX), |
4332 | EITR_TX_QUEUE0); | | 4367 | EITR_TX_QUEUE0); |
4333 | /* RX */ | | 4368 | /* RX */ |
4334 | CSR_WRITE(sc, WMREG_MSIXBM(WM_MSIX_RXINTR_IDX), | | 4369 | CSR_WRITE(sc, WMREG_MSIXBM(WM_MSIX_RXINTR_IDX), |
4335 | EITR_RX_QUEUE0); | | 4370 | EITR_RX_QUEUE0); |
4336 | /* Link status */ | | 4371 | /* Link status */ |
4337 | CSR_WRITE(sc, WMREG_MSIXBM(WM_MSIX_LINKINTR_IDX), | | 4372 | CSR_WRITE(sc, WMREG_MSIXBM(WM_MSIX_LINKINTR_IDX), |
4338 | EITR_OTHER); | | 4373 | EITR_OTHER); |
4339 | } else if (sc->sc_type == WM_T_82574) { | | 4374 | } else if (sc->sc_type == WM_T_82574) { |
4340 | /* Interrupt control */ | | 4375 | /* Interrupt control */ |
4341 | reg = CSR_READ(sc, WMREG_CTRL_EXT); | | 4376 | reg = CSR_READ(sc, WMREG_CTRL_EXT); |
4342 | reg |= CTRL_EXT_PBA | CTRL_EXT_EIAME; | | 4377 | reg |= CTRL_EXT_PBA | CTRL_EXT_EIAME; |
4343 | CSR_WRITE(sc, WMREG_CTRL_EXT, reg); | | 4378 | CSR_WRITE(sc, WMREG_CTRL_EXT, reg); |
4344 | | | 4379 | |
4345 | /* TX, RX and Link status */ | | 4380 | /* TX, RX and Link status */ |
4346 | ivar = __SHIFTIN((IVAR_VALID_82574|WM_MSIX_TXINTR_IDX), | | 4381 | ivar = __SHIFTIN((IVAR_VALID_82574|WM_MSIX_TXINTR_IDX), |
4347 | IVAR_TX_MASK_Q_82574(0)); | | 4382 | IVAR_TX_MASK_Q_82574(0)); |
4348 | ivar |= __SHIFTIN((IVAR_VALID_82574 | | 4383 | ivar |= __SHIFTIN((IVAR_VALID_82574 |
4349 | | WM_MSIX_RXINTR_IDX), | | 4384 | | WM_MSIX_RXINTR_IDX), |
4350 | IVAR_RX_MASK_Q_82574(0)); | | 4385 | IVAR_RX_MASK_Q_82574(0)); |
4351 | ivar |=__SHIFTIN((IVAR_VALID_82574|WM_MSIX_LINKINTR_IDX), | | 4386 | ivar |=__SHIFTIN((IVAR_VALID_82574|WM_MSIX_LINKINTR_IDX), |
4352 | IVAR_OTHER_MASK); | | 4387 | IVAR_OTHER_MASK); |
4353 | CSR_WRITE(sc, WMREG_IVAR, ivar | IVAR_INT_ON_ALL_WB); | | 4388 | CSR_WRITE(sc, WMREG_IVAR, ivar | IVAR_INT_ON_ALL_WB); |
4354 | } else { | | 4389 | } else { |
4355 | /* Interrupt control */ | | 4390 | /* Interrupt control */ |
4356 | CSR_WRITE(sc, WMREG_GPIE, GPIE_NSICR | | 4391 | CSR_WRITE(sc, WMREG_GPIE, GPIE_NSICR |
4357 | | GPIE_MULTI_MSIX | GPIE_EIAME | | 4392 | | GPIE_MULTI_MSIX | GPIE_EIAME |
4358 | | GPIE_PBA); | | 4393 | | GPIE_PBA); |
4359 | | | 4394 | |
4360 | switch (sc->sc_type) { | | 4395 | switch (sc->sc_type) { |
4361 | case WM_T_82580: | | 4396 | case WM_T_82580: |
4362 | case WM_T_I350: | | 4397 | case WM_T_I350: |
4363 | case WM_T_I354: | | 4398 | case WM_T_I354: |
4364 | case WM_T_I210: | | 4399 | case WM_T_I210: |
4365 | case WM_T_I211: | | 4400 | case WM_T_I211: |
4366 | /* TX */ | | 4401 | /* TX */ |
4367 | ivar = CSR_READ(sc, WMREG_IVAR_Q(0)); | | 4402 | ivar = CSR_READ(sc, WMREG_IVAR_Q(0)); |
4368 | ivar &= ~IVAR_TX_MASK_Q(0); | | 4403 | ivar &= ~IVAR_TX_MASK_Q(0); |
4369 | ivar |= __SHIFTIN( | | 4404 | ivar |= __SHIFTIN( |
4370 | (WM_MSIX_TXINTR_IDX | IVAR_VALID), | | 4405 | (WM_MSIX_TXINTR_IDX | IVAR_VALID), |
4371 | IVAR_TX_MASK_Q(0)); | | 4406 | IVAR_TX_MASK_Q(0)); |
4372 | CSR_WRITE(sc, WMREG_IVAR_Q(0), ivar); | | 4407 | CSR_WRITE(sc, WMREG_IVAR_Q(0), ivar); |
4373 | | | 4408 | |
4374 | /* RX */ | | 4409 | /* RX */ |
4375 | ivar = CSR_READ(sc, WMREG_IVAR_Q(0)); | | 4410 | ivar = CSR_READ(sc, WMREG_IVAR_Q(0)); |
4376 | ivar &= ~IVAR_RX_MASK_Q(0); | | 4411 | ivar &= ~IVAR_RX_MASK_Q(0); |
4377 | ivar |= __SHIFTIN( | | 4412 | ivar |= __SHIFTIN( |
4378 | (WM_MSIX_RXINTR_IDX | IVAR_VALID), | | 4413 | (WM_MSIX_RXINTR_IDX | IVAR_VALID), |
4379 | IVAR_RX_MASK_Q(0)); | | 4414 | IVAR_RX_MASK_Q(0)); |
4380 | CSR_WRITE(sc, WMREG_IVAR_Q(0), ivar); | | 4415 | CSR_WRITE(sc, WMREG_IVAR_Q(0), ivar); |
4381 | break; | | 4416 | break; |
4382 | case WM_T_82576: | | 4417 | case WM_T_82576: |
4383 | /* TX */ | | 4418 | /* TX */ |
4384 | ivar = CSR_READ(sc, WMREG_IVAR_Q_82576(0)); | | 4419 | ivar = CSR_READ(sc, WMREG_IVAR_Q_82576(0)); |
4385 | ivar &= ~IVAR_TX_MASK_Q_82576(0); | | 4420 | ivar &= ~IVAR_TX_MASK_Q_82576(0); |
4386 | ivar |= __SHIFTIN( | | 4421 | ivar |= __SHIFTIN( |
4387 | (WM_MSIX_TXINTR_IDX | IVAR_VALID), | | 4422 | (WM_MSIX_TXINTR_IDX | IVAR_VALID), |
4388 | IVAR_TX_MASK_Q_82576(0)); | | 4423 | IVAR_TX_MASK_Q_82576(0)); |
4389 | CSR_WRITE(sc, WMREG_IVAR_Q_82576(0), ivar); | | 4424 | CSR_WRITE(sc, WMREG_IVAR_Q_82576(0), ivar); |
4390 | | | 4425 | |
4391 | /* RX */ | | 4426 | /* RX */ |
4392 | ivar = CSR_READ(sc, WMREG_IVAR_Q_82576(0)); | | 4427 | ivar = CSR_READ(sc, WMREG_IVAR_Q_82576(0)); |
4393 | ivar &= ~IVAR_RX_MASK_Q_82576(0); | | 4428 | ivar &= ~IVAR_RX_MASK_Q_82576(0); |
4394 | ivar |= __SHIFTIN( | | 4429 | ivar |= __SHIFTIN( |
4395 | (WM_MSIX_RXINTR_IDX | IVAR_VALID), | | 4430 | (WM_MSIX_RXINTR_IDX | IVAR_VALID), |
4396 | IVAR_RX_MASK_Q_82576(0)); | | 4431 | IVAR_RX_MASK_Q_82576(0)); |
4397 | CSR_WRITE(sc, WMREG_IVAR_Q_82576(0), ivar); | | 4432 | CSR_WRITE(sc, WMREG_IVAR_Q_82576(0), ivar); |
4398 | break; | | 4433 | break; |
4399 | default: | | 4434 | default: |
4400 | break; | | 4435 | break; |
4401 | } | | 4436 | } |
4402 | | | 4437 | |
4403 | /* Link status */ | | 4438 | /* Link status */ |
4404 | ivar = __SHIFTIN((WM_MSIX_LINKINTR_IDX | IVAR_VALID), | | 4439 | ivar = __SHIFTIN((WM_MSIX_LINKINTR_IDX | IVAR_VALID), |
4405 | IVAR_MISC_OTHER); | | 4440 | IVAR_MISC_OTHER); |
4406 | CSR_WRITE(sc, WMREG_IVAR_MISC, ivar); | | 4441 | CSR_WRITE(sc, WMREG_IVAR_MISC, ivar); |
4407 | } | | 4442 | } |
4408 | } | | 4443 | } |
4409 | | | 4444 | |
4410 | /* Set up the interrupt registers. */ | | 4445 | /* Set up the interrupt registers. */ |
4411 | CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); | | 4446 | CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); |
4412 | sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | | | 4447 | sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | |
4413 | ICR_RXO | ICR_RXT0; | | 4448 | ICR_RXO | ICR_RXT0; |
4414 | if (sc->sc_nintrs > 1) { | | 4449 | if (sc->sc_nintrs > 1) { |
4415 | uint32_t mask; | | 4450 | uint32_t mask; |
4416 | switch (sc->sc_type) { | | 4451 | switch (sc->sc_type) { |
4417 | case WM_T_82574: | | 4452 | case WM_T_82574: |
4418 | CSR_WRITE(sc, WMREG_EIAC_82574, | | 4453 | CSR_WRITE(sc, WMREG_EIAC_82574, |
4419 | WMREG_EIAC_82574_MSIX_MASK); | | 4454 | WMREG_EIAC_82574_MSIX_MASK); |
4420 | sc->sc_icr |= WMREG_EIAC_82574_MSIX_MASK; | | 4455 | sc->sc_icr |= WMREG_EIAC_82574_MSIX_MASK; |
4421 | CSR_WRITE(sc, WMREG_IMS, sc->sc_icr); | | 4456 | CSR_WRITE(sc, WMREG_IMS, sc->sc_icr); |
4422 | break; | | 4457 | break; |
4423 | default: | | 4458 | default: |
4424 | if (sc->sc_type == WM_T_82575) | | 4459 | if (sc->sc_type == WM_T_82575) |
4425 | mask = EITR_RX_QUEUE0 |EITR_TX_QUEUE0 | | 4460 | mask = EITR_RX_QUEUE0 |EITR_TX_QUEUE0 |
4426 | | EITR_OTHER; | | 4461 | | EITR_OTHER; |
4427 | else | | 4462 | else |
4428 | mask = (1 << WM_MSIX_RXINTR_IDX) | | 4463 | mask = (1 << WM_MSIX_RXINTR_IDX) |
4429 | | (1 << WM_MSIX_TXINTR_IDX) | | 4464 | | (1 << WM_MSIX_TXINTR_IDX) |
4430 | | (1 << WM_MSIX_LINKINTR_IDX); | | 4465 | | (1 << WM_MSIX_LINKINTR_IDX); |
4431 | CSR_WRITE(sc, WMREG_EIAC, mask); | | 4466 | CSR_WRITE(sc, WMREG_EIAC, mask); |
4432 | CSR_WRITE(sc, WMREG_EIAM, mask); | | 4467 | CSR_WRITE(sc, WMREG_EIAM, mask); |
4433 | CSR_WRITE(sc, WMREG_EIMS, mask); | | 4468 | CSR_WRITE(sc, WMREG_EIMS, mask); |
4434 | CSR_WRITE(sc, WMREG_IMS, ICR_LSC); | | 4469 | CSR_WRITE(sc, WMREG_IMS, ICR_LSC); |
4435 | break; | | 4470 | break; |
4436 | } | | 4471 | } |
4437 | } else | | 4472 | } else |
4438 | CSR_WRITE(sc, WMREG_IMS, sc->sc_icr); | | 4473 | CSR_WRITE(sc, WMREG_IMS, sc->sc_icr); |
4439 | | | 4474 | |
4440 | if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9) | | 4475 | if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9) |
4441 | || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH) | | 4476 | || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH) |
4442 | || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) { | | 4477 | || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) { |
4443 | reg = CSR_READ(sc, WMREG_KABGTXD); | | 4478 | reg = CSR_READ(sc, WMREG_KABGTXD); |
4444 | reg |= KABGTXD_BGSQLBIAS; | | 4479 | reg |= KABGTXD_BGSQLBIAS; |
4445 | CSR_WRITE(sc, WMREG_KABGTXD, reg); | | 4480 | CSR_WRITE(sc, WMREG_KABGTXD, reg); |
4446 | } | | 4481 | } |
4447 | | | 4482 | |
4448 | /* Set up the inter-packet gap. */ | | 4483 | /* Set up the inter-packet gap. */ |
4449 | CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg); | | 4484 | CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg); |
4450 | | | 4485 | |
4451 | if (sc->sc_type >= WM_T_82543) { | | 4486 | if (sc->sc_type >= WM_T_82543) { |
4452 | /* | | 4487 | /* |
4453 | * XXX 82574 has both ITR and EITR. SET EITR when we use | | 4488 | * XXX 82574 has both ITR and EITR. SET EITR when we use |
4454 | * the multi queue function with MSI-X. | | 4489 | * the multi queue function with MSI-X. |
4455 | */ | | 4490 | */ |
4456 | if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) { | | 4491 | if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) { |
4457 | if (sc->sc_nintrs > 1) { | | 4492 | if (sc->sc_nintrs > 1) { |
4458 | CSR_WRITE(sc, WMREG_EITR(WM_MSIX_RXINTR_IDX), | | 4493 | CSR_WRITE(sc, WMREG_EITR(WM_MSIX_RXINTR_IDX), |
4459 | sc->sc_itr); | | 4494 | sc->sc_itr); |
4460 | CSR_WRITE(sc, WMREG_EITR(WM_MSIX_TXINTR_IDX), | | 4495 | CSR_WRITE(sc, WMREG_EITR(WM_MSIX_TXINTR_IDX), |
4461 | sc->sc_itr); | | 4496 | sc->sc_itr); |
4462 | /* | | 4497 | /* |
4463 | * Link interrupts occur much less than TX | | 4498 | * Link interrupts occur much less than TX |
4464 | * interrupts and RX interrupts. So, we don't | | 4499 | * interrupts and RX interrupts. So, we don't |
4465 | * tune EINTR(WM_MSIX_LINKINTR_IDX) value like | | 4500 | * tune EINTR(WM_MSIX_LINKINTR_IDX) value like |
4466 | * FreeBSD's if_igb. | | 4501 | * FreeBSD's if_igb. |
4467 | */ | | 4502 | */ |
4468 | } else | | 4503 | } else |
4469 | CSR_WRITE(sc, WMREG_EITR(0), sc->sc_itr); | | 4504 | CSR_WRITE(sc, WMREG_EITR(0), sc->sc_itr); |
4470 | } else | | 4505 | } else |
4471 | CSR_WRITE(sc, WMREG_ITR, sc->sc_itr); | | 4506 | CSR_WRITE(sc, WMREG_ITR, sc->sc_itr); |
4472 | } | | 4507 | } |
4473 | | | 4508 | |
4474 | /* Set the VLAN ethernetype. */ | | 4509 | /* Set the VLAN ethernetype. */ |
4475 | CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN); | | 4510 | CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN); |
4476 | | | 4511 | |
4477 | /* | | 4512 | /* |
4478 | * Set up the transmit control register; we start out with | | 4513 | * Set up the transmit control register; we start out with |
4479 | * a collision distance suitable for FDX, but update it whe | | 4514 | * a collision distance suitable for FDX, but update it whe |
4480 | * we resolve the media type. | | 4515 | * we resolve the media type. |
4481 | */ | | 4516 | */ |
4482 | sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_RTLC | | 4517 | sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_RTLC |
4483 | | TCTL_CT(TX_COLLISION_THRESHOLD) | | 4518 | | TCTL_CT(TX_COLLISION_THRESHOLD) |
4484 | | TCTL_COLD(TX_COLLISION_DISTANCE_FDX); | | 4519 | | TCTL_COLD(TX_COLLISION_DISTANCE_FDX); |
4485 | if (sc->sc_type >= WM_T_82571) | | 4520 | if (sc->sc_type >= WM_T_82571) |
4486 | sc->sc_tctl |= TCTL_MULR; | | 4521 | sc->sc_tctl |= TCTL_MULR; |
4487 | CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); | | 4522 | CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); |
4488 | | | 4523 | |
4489 | if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) { | | 4524 | if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) { |
4490 | /* Write TDT after TCTL.EN is set. See the document. */ | | 4525 | /* Write TDT after TCTL.EN is set. See the document. */ |
4491 | CSR_WRITE(sc, WMREG_TDT, 0); | | 4526 | CSR_WRITE(sc, WMREG_TDT, 0); |
4492 | } | | 4527 | } |
4493 | | | 4528 | |
4494 | if (sc->sc_type == WM_T_80003) { | | 4529 | if (sc->sc_type == WM_T_80003) { |
4495 | reg = CSR_READ(sc, WMREG_TCTL_EXT); | | 4530 | reg = CSR_READ(sc, WMREG_TCTL_EXT); |
4496 | reg &= ~TCTL_EXT_GCEX_MASK; | | 4531 | reg &= ~TCTL_EXT_GCEX_MASK; |
4497 | reg |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; | | 4532 | reg |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; |
4498 | CSR_WRITE(sc, WMREG_TCTL_EXT, reg); | | 4533 | CSR_WRITE(sc, WMREG_TCTL_EXT, reg); |
4499 | } | | 4534 | } |
4500 | | | 4535 | |
4501 | /* Set the media. */ | | 4536 | /* Set the media. */ |
4502 | if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) | | 4537 | if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) |
4503 | goto out; | | 4538 | goto out; |
4504 | | | 4539 | |
4505 | /* Configure for OS presence */ | | 4540 | /* Configure for OS presence */ |
4506 | wm_init_manageability(sc); | | 4541 | wm_init_manageability(sc); |
4507 | | | 4542 | |
4508 | /* | | 4543 | /* |
4509 | * Set up the receive control register; we actually program | | 4544 | * Set up the receive control register; we actually program |
4510 | * the register when we set the receive filter. Use multicast | | 4545 | * the register when we set the receive filter. Use multicast |
4511 | * address offset type 0. | | 4546 | * address offset type 0. |
4512 | * | | 4547 | * |
4513 | * Only the i82544 has the ability to strip the incoming | | 4548 | * Only the i82544 has the ability to strip the incoming |
4514 | * CRC, so we don't enable that feature. | | 4549 | * CRC, so we don't enable that feature. |
4515 | */ | | 4550 | */ |
4516 | sc->sc_mchash_type = 0; | | 4551 | sc->sc_mchash_type = 0; |
4517 | sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_DPF | | 4552 | sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_DPF |
4518 | | RCTL_MO(sc->sc_mchash_type); | | 4553 | | RCTL_MO(sc->sc_mchash_type); |
4519 | | | 4554 | |
4520 | /* | | 4555 | /* |
4521 | * The I350 has a bug where it always strips the CRC whether | | 4556 | * The I350 has a bug where it always strips the CRC whether |
4522 | * asked to or not. So ask for stripped CRC here and cope in rxeof | | 4557 | * asked to or not. So ask for stripped CRC here and cope in rxeof |
4523 | */ | | 4558 | */ |
4524 | if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354) | | 4559 | if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354) |
4525 | || (sc->sc_type == WM_T_I210)) | | 4560 | || (sc->sc_type == WM_T_I210)) |
4526 | sc->sc_rctl |= RCTL_SECRC; | | 4561 | sc->sc_rctl |= RCTL_SECRC; |
4527 | | | 4562 | |
4528 | if (((sc->sc_ethercom.ec_capabilities & ETHERCAP_JUMBO_MTU) != 0) | | 4563 | if (((sc->sc_ethercom.ec_capabilities & ETHERCAP_JUMBO_MTU) != 0) |
4529 | && (ifp->if_mtu > ETHERMTU)) { | | 4564 | && (ifp->if_mtu > ETHERMTU)) { |
4530 | sc->sc_rctl |= RCTL_LPE; | | 4565 | sc->sc_rctl |= RCTL_LPE; |
4531 | if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) | | 4566 | if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) |
4532 | CSR_WRITE(sc, WMREG_RLPML, ETHER_MAX_LEN_JUMBO); | | 4567 | CSR_WRITE(sc, WMREG_RLPML, ETHER_MAX_LEN_JUMBO); |
4533 | } | | 4568 | } |
4534 | | | 4569 | |
4535 | if (MCLBYTES == 2048) { | | 4570 | if (MCLBYTES == 2048) { |
4536 | sc->sc_rctl |= RCTL_2k; | | 4571 | sc->sc_rctl |= RCTL_2k; |
4537 | } else { | | 4572 | } else { |
4538 | if (sc->sc_type >= WM_T_82543) { | | 4573 | if (sc->sc_type >= WM_T_82543) { |
4539 | switch (MCLBYTES) { | | 4574 | switch (MCLBYTES) { |
4540 | case 4096: | | 4575 | case 4096: |
4541 | sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k; | | 4576 | sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k; |
4542 | break; | | 4577 | break; |
4543 | case 8192: | | 4578 | case 8192: |
4544 | sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k; | | 4579 | sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k; |
4545 | break; | | 4580 | break; |
4546 | case 16384: | | 4581 | case 16384: |
4547 | sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k; | | 4582 | sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k; |
4548 | break; | | 4583 | break; |
4549 | default: | | 4584 | default: |
4550 | panic("wm_init: MCLBYTES %d unsupported", | | 4585 | panic("wm_init: MCLBYTES %d unsupported", |
4551 | MCLBYTES); | | 4586 | MCLBYTES); |
4552 | break; | | 4587 | break; |
4553 | } | | 4588 | } |
4554 | } else panic("wm_init: i82542 requires MCLBYTES = 2048"); | | 4589 | } else panic("wm_init: i82542 requires MCLBYTES = 2048"); |
4555 | } | | 4590 | } |
4556 | | | 4591 | |
4557 | /* Set the receive filter. */ | | 4592 | /* Set the receive filter. */ |
4558 | wm_set_filter(sc); | | 4593 | wm_set_filter(sc); |
4559 | | | 4594 | |
4560 | /* Enable ECC */ | | 4595 | /* Enable ECC */ |
4561 | switch (sc->sc_type) { | | 4596 | switch (sc->sc_type) { |
4562 | case WM_T_82571: | | 4597 | case WM_T_82571: |
4563 | reg = CSR_READ(sc, WMREG_PBA_ECC); | | 4598 | reg = CSR_READ(sc, WMREG_PBA_ECC); |
4564 | reg |= PBA_ECC_CORR_EN; | | 4599 | reg |= PBA_ECC_CORR_EN; |
4565 | CSR_WRITE(sc, WMREG_PBA_ECC, reg); | | 4600 | CSR_WRITE(sc, WMREG_PBA_ECC, reg); |
4566 | break; | | 4601 | break; |
4567 | case WM_T_PCH_LPT: | | 4602 | case WM_T_PCH_LPT: |
4568 | reg = CSR_READ(sc, WMREG_PBECCSTS); | | 4603 | reg = CSR_READ(sc, WMREG_PBECCSTS); |
4569 | reg |= PBECCSTS_UNCORR_ECC_ENABLE; | | 4604 | reg |= PBECCSTS_UNCORR_ECC_ENABLE; |
4570 | CSR_WRITE(sc, WMREG_PBECCSTS, reg); | | 4605 | CSR_WRITE(sc, WMREG_PBECCSTS, reg); |
4571 | | | 4606 | |
4572 | reg = CSR_READ(sc, WMREG_CTRL); | | 4607 | reg = CSR_READ(sc, WMREG_CTRL); |
4573 | reg |= CTRL_MEHE; | | 4608 | reg |= CTRL_MEHE; |
4574 | CSR_WRITE(sc, WMREG_CTRL, reg); | | 4609 | CSR_WRITE(sc, WMREG_CTRL, reg); |
4575 | break; | | 4610 | break; |
4576 | default: | | 4611 | default: |
4577 | break; | | 4612 | break; |
4578 | } | | 4613 | } |
4579 | | | 4614 | |
4580 | /* On 575 and later set RDT only if RX enabled */ | | 4615 | /* On 575 and later set RDT only if RX enabled */ |
4581 | if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) | | 4616 | if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) |
4582 | for (i = 0; i < WM_NRXDESC; i++) | | 4617 | for (i = 0; i < WM_NRXDESC; i++) |
4583 | wm_init_rxdesc(sc, i); | | 4618 | wm_init_rxdesc(sc, i); |
4584 | | | 4619 | |
4585 | sc->sc_stopping = false; | | 4620 | sc->sc_stopping = false; |
4586 | | | 4621 | |
4587 | /* Start the one second link check clock. */ | | 4622 | /* Start the one second link check clock. */ |
4588 | callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); | | 4623 | callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); |
4589 | | | 4624 | |
4590 | /* ...all done! */ | | 4625 | /* ...all done! */ |
4591 | ifp->if_flags |= IFF_RUNNING; | | 4626 | ifp->if_flags |= IFF_RUNNING; |
4592 | ifp->if_flags &= ~IFF_OACTIVE; | | 4627 | ifp->if_flags &= ~IFF_OACTIVE; |
4593 | | | 4628 | |
4594 | out: | | 4629 | out: |
4595 | sc->sc_if_flags = ifp->if_flags; | | 4630 | sc->sc_if_flags = ifp->if_flags; |
4596 | if (error) | | 4631 | if (error) |
4597 | log(LOG_ERR, "%s: interface not running\n", | | 4632 | log(LOG_ERR, "%s: interface not running\n", |
4598 | device_xname(sc->sc_dev)); | | 4633 | device_xname(sc->sc_dev)); |
4599 | return error; | | 4634 | return error; |
4600 | } | | 4635 | } |
4601 | | | 4636 | |
4602 | /* | | 4637 | /* |
4603 | * wm_stop: [ifnet interface function] | | 4638 | * wm_stop: [ifnet interface function] |
4604 | * | | 4639 | * |
4605 | * Stop transmission on the interface. | | 4640 | * Stop transmission on the interface. |
4606 | */ | | 4641 | */ |
4607 | static void | | 4642 | static void |
4608 | wm_stop(struct ifnet *ifp, int disable) | | 4643 | wm_stop(struct ifnet *ifp, int disable) |
4609 | { | | 4644 | { |
4610 | struct wm_softc *sc = ifp->if_softc; | | 4645 | struct wm_softc *sc = ifp->if_softc; |
4611 | | | 4646 | |
4612 | WM_CORE_LOCK(sc); | | 4647 | WM_CORE_LOCK(sc); |
4613 | wm_stop_locked(ifp, disable); | | 4648 | wm_stop_locked(ifp, disable); |
4614 | WM_CORE_UNLOCK(sc); | | 4649 | WM_CORE_UNLOCK(sc); |
4615 | } | | 4650 | } |
4616 | | | 4651 | |
4617 | static void | | 4652 | static void |
4618 | wm_stop_locked(struct ifnet *ifp, int disable) | | 4653 | wm_stop_locked(struct ifnet *ifp, int disable) |
4619 | { | | 4654 | { |
4620 | struct wm_softc *sc = ifp->if_softc; | | 4655 | struct wm_softc *sc = ifp->if_softc; |
4621 | struct wm_txqueue *txq = sc->sc_txq; | | 4656 | struct wm_txqueue *txq = sc->sc_txq; |
4622 | struct wm_rxqueue *rxq = sc->sc_rxq; | | 4657 | struct wm_rxqueue *rxq = sc->sc_rxq; |
4623 | struct wm_txsoft *txs; | | 4658 | struct wm_txsoft *txs; |
4624 | int i; | | 4659 | int i; |
4625 | | | 4660 | |
4626 | KASSERT(WM_CORE_LOCKED(sc)); | | 4661 | KASSERT(WM_CORE_LOCKED(sc)); |
4627 | | | 4662 | |
4628 | sc->sc_stopping = true; | | 4663 | sc->sc_stopping = true; |
4629 | | | 4664 | |
4630 | /* Stop the one second clock. */ | | 4665 | /* Stop the one second clock. */ |
4631 | callout_stop(&sc->sc_tick_ch); | | 4666 | callout_stop(&sc->sc_tick_ch); |
4632 | | | 4667 | |
4633 | /* Stop the 82547 Tx FIFO stall check timer. */ | | 4668 | /* Stop the 82547 Tx FIFO stall check timer. */ |
4634 | if (sc->sc_type == WM_T_82547) | | 4669 | if (sc->sc_type == WM_T_82547) |
4635 | callout_stop(&sc->sc_txfifo_ch); | | 4670 | callout_stop(&sc->sc_txfifo_ch); |
4636 | | | 4671 | |
4637 | if (sc->sc_flags & WM_F_HAS_MII) { | | 4672 | if (sc->sc_flags & WM_F_HAS_MII) { |
4638 | /* Down the MII. */ | | 4673 | /* Down the MII. */ |
4639 | mii_down(&sc->sc_mii); | | 4674 | mii_down(&sc->sc_mii); |
4640 | } else { | | 4675 | } else { |
4641 | #if 0 | | 4676 | #if 0 |
4642 | /* Should we clear PHY's status properly? */ | | 4677 | /* Should we clear PHY's status properly? */ |
4643 | wm_reset(sc); | | 4678 | wm_reset(sc); |
4644 | #endif | | 4679 | #endif |
4645 | } | | 4680 | } |
4646 | | | 4681 | |
4647 | /* Stop the transmit and receive processes. */ | | 4682 | /* Stop the transmit and receive processes. */ |
4648 | CSR_WRITE(sc, WMREG_TCTL, 0); | | 4683 | CSR_WRITE(sc, WMREG_TCTL, 0); |
4649 | CSR_WRITE(sc, WMREG_RCTL, 0); | | 4684 | CSR_WRITE(sc, WMREG_RCTL, 0); |
4650 | sc->sc_rctl &= ~RCTL_EN; | | 4685 | sc->sc_rctl &= ~RCTL_EN; |
4651 | | | 4686 | |
4652 | /* | | 4687 | /* |
4653 | * Clear the interrupt mask to ensure the device cannot assert its | | 4688 | * Clear the interrupt mask to ensure the device cannot assert its |
4654 | * interrupt line. | | 4689 | * interrupt line. |
4655 | * Clear sc->sc_icr to ensure wm_intr_legacy() makes no attempt to | | 4690 | * Clear sc->sc_icr to ensure wm_intr_legacy() makes no attempt to |
4656 | * service any currently pending or shared interrupt. | | 4691 | * service any currently pending or shared interrupt. |
4657 | */ | | 4692 | */ |
4658 | CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); | | 4693 | CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); |
4659 | sc->sc_icr = 0; | | 4694 | sc->sc_icr = 0; |
4660 | if (sc->sc_nintrs > 1) { | | 4695 | if (sc->sc_nintrs > 1) { |
4661 | if (sc->sc_type != WM_T_82574) { | | 4696 | if (sc->sc_type != WM_T_82574) { |
4662 | CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU); | | 4697 | CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU); |
4663 | CSR_WRITE(sc, WMREG_EIAC, 0); | | 4698 | CSR_WRITE(sc, WMREG_EIAC, 0); |
4664 | } else | | 4699 | } else |
4665 | CSR_WRITE(sc, WMREG_EIAC_82574, 0); | | 4700 | CSR_WRITE(sc, WMREG_EIAC_82574, 0); |
4666 | } | | 4701 | } |
4667 | | | 4702 | |
4668 | /* Release any queued transmit buffers. */ | | 4703 | /* Release any queued transmit buffers. */ |
4669 | WM_TX_LOCK(txq); | | 4704 | WM_TX_LOCK(txq); |
4670 | for (i = 0; i < WM_TXQUEUELEN(txq); i++) { | | 4705 | for (i = 0; i < WM_TXQUEUELEN(txq); i++) { |
4671 | txs = &txq->txq_soft[i]; | | 4706 | txs = &txq->txq_soft[i]; |
4672 | if (txs->txs_mbuf != NULL) { | | 4707 | if (txs->txs_mbuf != NULL) { |
4673 | bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); | | 4708 | bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); |
4674 | m_freem(txs->txs_mbuf); | | 4709 | m_freem(txs->txs_mbuf); |
4675 | txs->txs_mbuf = NULL; | | 4710 | txs->txs_mbuf = NULL; |
4676 | } | | 4711 | } |
4677 | } | | 4712 | } |
4678 | WM_TX_UNLOCK(txq); | | 4713 | WM_TX_UNLOCK(txq); |
4679 | | | 4714 | |
4680 | /* Mark the interface as down and cancel the watchdog timer. */ | | 4715 | /* Mark the interface as down and cancel the watchdog timer. */ |
4681 | ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); | | 4716 | ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); |
4682 | ifp->if_timer = 0; | | 4717 | ifp->if_timer = 0; |
4683 | | | 4718 | |
4684 | if (disable) { | | 4719 | if (disable) { |
4685 | WM_RX_LOCK(rxq); | | 4720 | WM_RX_LOCK(rxq); |
4686 | wm_rxdrain(sc); | | 4721 | wm_rxdrain(sc); |
4687 | WM_RX_UNLOCK(rxq); | | 4722 | WM_RX_UNLOCK(rxq); |
4688 | } | | 4723 | } |
4689 | | | 4724 | |
4690 | #if 0 /* notyet */ | | 4725 | #if 0 /* notyet */ |
4691 | if (sc->sc_type >= WM_T_82544) | | 4726 | if (sc->sc_type >= WM_T_82544) |
4692 | CSR_WRITE(sc, WMREG_WUC, 0); | | 4727 | CSR_WRITE(sc, WMREG_WUC, 0); |
4693 | #endif | | 4728 | #endif |
4694 | } | | 4729 | } |
4695 | | | 4730 | |
4696 | /* | | 4731 | /* |
4697 | * wm_tx_offload: | | 4732 | * wm_tx_offload: |
4698 | * | | 4733 | * |
4699 | * Set up TCP/IP checksumming parameters for the | | 4734 | * Set up TCP/IP checksumming parameters for the |
4700 | * specified packet. | | 4735 | * specified packet. |
4701 | */ | | 4736 | */ |
4702 | static int | | 4737 | static int |
4703 | wm_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp, | | 4738 | wm_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp, |
4704 | uint8_t *fieldsp) | | 4739 | uint8_t *fieldsp) |
4705 | { | | 4740 | { |
4706 | struct wm_txqueue *txq = sc->sc_txq; | | 4741 | struct wm_txqueue *txq = sc->sc_txq; |
4707 | struct mbuf *m0 = txs->txs_mbuf; | | 4742 | struct mbuf *m0 = txs->txs_mbuf; |
4708 | struct livengood_tcpip_ctxdesc *t; | | 4743 | struct livengood_tcpip_ctxdesc *t; |
4709 | uint32_t ipcs, tucs, cmd, cmdlen, seg; | | 4744 | uint32_t ipcs, tucs, cmd, cmdlen, seg; |
4710 | uint32_t ipcse; | | 4745 | uint32_t ipcse; |
4711 | struct ether_header *eh; | | 4746 | struct ether_header *eh; |
4712 | int offset, iphl; | | 4747 | int offset, iphl; |
4713 | uint8_t fields; | | 4748 | uint8_t fields; |
4714 | | | 4749 | |
4715 | /* | | 4750 | /* |
4716 | * XXX It would be nice if the mbuf pkthdr had offset | | 4751 | * XXX It would be nice if the mbuf pkthdr had offset |
4717 | * fields for the protocol headers. | | 4752 | * fields for the protocol headers. |
4718 | */ | | 4753 | */ |
4719 | | | 4754 | |
4720 | eh = mtod(m0, struct ether_header *); | | 4755 | eh = mtod(m0, struct ether_header *); |
4721 | switch (htons(eh->ether_type)) { | | 4756 | switch (htons(eh->ether_type)) { |
4722 | case ETHERTYPE_IP: | | 4757 | case ETHERTYPE_IP: |
4723 | case ETHERTYPE_IPV6: | | 4758 | case ETHERTYPE_IPV6: |
4724 | offset = ETHER_HDR_LEN; | | 4759 | offset = ETHER_HDR_LEN; |
4725 | break; | | 4760 | break; |
4726 | | | 4761 | |
4727 | case ETHERTYPE_VLAN: | | 4762 | case ETHERTYPE_VLAN: |
4728 | offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; | | 4763 | offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; |
4729 | break; | | 4764 | break; |
4730 | | | 4765 | |
4731 | default: | | 4766 | default: |
4732 | /* | | 4767 | /* |
4733 | * Don't support this protocol or encapsulation. | | 4768 | * Don't support this protocol or encapsulation. |
4734 | */ | | 4769 | */ |
4735 | *fieldsp = 0; | | 4770 | *fieldsp = 0; |
4736 | *cmdp = 0; | | 4771 | *cmdp = 0; |
4737 | return 0; | | 4772 | return 0; |
4738 | } | | 4773 | } |
4739 | | | 4774 | |
4740 | if ((m0->m_pkthdr.csum_flags & | | 4775 | if ((m0->m_pkthdr.csum_flags & |
4741 | (M_CSUM_TSOv4|M_CSUM_UDPv4|M_CSUM_TCPv4)) != 0) { | | 4776 | (M_CSUM_TSOv4|M_CSUM_UDPv4|M_CSUM_TCPv4)) != 0) { |
4742 | iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); | | 4777 | iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); |
4743 | } else { | | 4778 | } else { |
4744 | iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data); | | 4779 | iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data); |
4745 | } | | 4780 | } |
4746 | ipcse = offset + iphl - 1; | | 4781 | ipcse = offset + iphl - 1; |
4747 | | | 4782 | |
4748 | cmd = WTX_CMD_DEXT | WTX_DTYP_D; | | 4783 | cmd = WTX_CMD_DEXT | WTX_DTYP_D; |
4749 | cmdlen = WTX_CMD_DEXT | WTX_DTYP_C | WTX_CMD_IDE; | | 4784 | cmdlen = WTX_CMD_DEXT | WTX_DTYP_C | WTX_CMD_IDE; |
4750 | seg = 0; | | 4785 | seg = 0; |
4751 | fields = 0; | | 4786 | fields = 0; |
4752 | | | 4787 | |
4753 | if ((m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) { | | 4788 | if ((m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) { |
4754 | int hlen = offset + iphl; | | 4789 | int hlen = offset + iphl; |
4755 | bool v4 = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; | | 4790 | bool v4 = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; |
4756 | | | 4791 | |
4757 | if (__predict_false(m0->m_len < | | 4792 | if (__predict_false(m0->m_len < |
4758 | (hlen + sizeof(struct tcphdr)))) { | | 4793 | (hlen + sizeof(struct tcphdr)))) { |
4759 | /* | | 4794 | /* |
4760 | * TCP/IP headers are not in the first mbuf; we need | | 4795 | * TCP/IP headers are not in the first mbuf; we need |
4761 | * to do this the slow and painful way. Let's just | | 4796 | * to do this the slow and painful way. Let's just |
4762 | * hope this doesn't happen very often. | | 4797 | * hope this doesn't happen very often. |
4763 | */ | | 4798 | */ |
4764 | struct tcphdr th; | | 4799 | struct tcphdr th; |
4765 | | | 4800 | |
4766 | WM_EVCNT_INCR(&sc->sc_ev_txtsopain); | | 4801 | WM_EVCNT_INCR(&sc->sc_ev_txtsopain); |
4767 | | | 4802 | |
4768 | m_copydata(m0, hlen, sizeof(th), &th); | | 4803 | m_copydata(m0, hlen, sizeof(th), &th); |
4769 | if (v4) { | | 4804 | if (v4) { |
4770 | struct ip ip; | | 4805 | struct ip ip; |
4771 | | | 4806 | |
4772 | m_copydata(m0, offset, sizeof(ip), &ip); | | 4807 | m_copydata(m0, offset, sizeof(ip), &ip); |
4773 | ip.ip_len = 0; | | 4808 | ip.ip_len = 0; |
4774 | m_copyback(m0, | | 4809 | m_copyback(m0, |
4775 | offset + offsetof(struct ip, ip_len), | | 4810 | offset + offsetof(struct ip, ip_len), |
4776 | sizeof(ip.ip_len), &ip.ip_len); | | 4811 | sizeof(ip.ip_len), &ip.ip_len); |
4777 | th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, | | 4812 | th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, |
4778 | ip.ip_dst.s_addr, htons(IPPROTO_TCP)); | | 4813 | ip.ip_dst.s_addr, htons(IPPROTO_TCP)); |
4779 | } else { | | 4814 | } else { |
4780 | struct ip6_hdr ip6; | | 4815 | struct ip6_hdr ip6; |
4781 | | | 4816 | |
4782 | m_copydata(m0, offset, sizeof(ip6), &ip6); | | 4817 | m_copydata(m0, offset, sizeof(ip6), &ip6); |
4783 | ip6.ip6_plen = 0; | | 4818 | ip6.ip6_plen = 0; |
4784 | m_copyback(m0, | | 4819 | m_copyback(m0, |
4785 | offset + offsetof(struct ip6_hdr, ip6_plen), | | 4820 | offset + offsetof(struct ip6_hdr, ip6_plen), |
4786 | sizeof(ip6.ip6_plen), &ip6.ip6_plen); | | 4821 | sizeof(ip6.ip6_plen), &ip6.ip6_plen); |
4787 | th.th_sum = in6_cksum_phdr(&ip6.ip6_src, | | 4822 | th.th_sum = in6_cksum_phdr(&ip6.ip6_src, |
4788 | &ip6.ip6_dst, 0, htonl(IPPROTO_TCP)); | | 4823 | &ip6.ip6_dst, 0, htonl(IPPROTO_TCP)); |
4789 | } | | 4824 | } |
4790 | m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), | | 4825 | m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), |
4791 | sizeof(th.th_sum), &th.th_sum); | | 4826 | sizeof(th.th_sum), &th.th_sum); |
4792 | | | 4827 | |
4793 | hlen += th.th_off << 2; | | 4828 | hlen += th.th_off << 2; |
4794 | } else { | | 4829 | } else { |
4795 | /* | | 4830 | /* |
4796 | * TCP/IP headers are in the first mbuf; we can do | | 4831 | * TCP/IP headers are in the first mbuf; we can do |
4797 | * this the easy way. | | 4832 | * this the easy way. |
4798 | */ | | 4833 | */ |
4799 | struct tcphdr *th; | | 4834 | struct tcphdr *th; |
4800 | | | 4835 | |
4801 | if (v4) { | | 4836 | if (v4) { |
4802 | struct ip *ip = | | 4837 | struct ip *ip = |
4803 | (void *)(mtod(m0, char *) + offset); | | 4838 | (void *)(mtod(m0, char *) + offset); |
4804 | th = (void *)(mtod(m0, char *) + hlen); | | 4839 | th = (void *)(mtod(m0, char *) + hlen); |
4805 | | | 4840 | |
4806 | ip->ip_len = 0; | | 4841 | ip->ip_len = 0; |
4807 | th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, | | 4842 | th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, |
4808 | ip->ip_dst.s_addr, htons(IPPROTO_TCP)); | | 4843 | ip->ip_dst.s_addr, htons(IPPROTO_TCP)); |
4809 | } else { | | 4844 | } else { |
4810 | struct ip6_hdr *ip6 = | | 4845 | struct ip6_hdr *ip6 = |
4811 | (void *)(mtod(m0, char *) + offset); | | 4846 | (void *)(mtod(m0, char *) + offset); |
4812 | th = (void *)(mtod(m0, char *) + hlen); | | 4847 | th = (void *)(mtod(m0, char *) + hlen); |
4813 | | | 4848 | |
4814 | ip6->ip6_plen = 0; | | 4849 | ip6->ip6_plen = 0; |
4815 | th->th_sum = in6_cksum_phdr(&ip6->ip6_src, | | 4850 | th->th_sum = in6_cksum_phdr(&ip6->ip6_src, |
4816 | &ip6->ip6_dst, 0, htonl(IPPROTO_TCP)); | | 4851 | &ip6->ip6_dst, 0, htonl(IPPROTO_TCP)); |
4817 | } | | 4852 | } |
4818 | hlen += th->th_off << 2; | | 4853 | hlen += th->th_off << 2; |
4819 | } | | 4854 | } |
4820 | | | 4855 | |
4821 | if (v4) { | | 4856 | if (v4) { |
4822 | WM_EVCNT_INCR(&sc->sc_ev_txtso); | | 4857 | WM_EVCNT_INCR(&sc->sc_ev_txtso); |
4823 | cmdlen |= WTX_TCPIP_CMD_IP; | | 4858 | cmdlen |= WTX_TCPIP_CMD_IP; |
4824 | } else { | | 4859 | } else { |
4825 | WM_EVCNT_INCR(&sc->sc_ev_txtso6); | | 4860 | WM_EVCNT_INCR(&sc->sc_ev_txtso6); |
4826 | ipcse = 0; | | 4861 | ipcse = 0; |
4827 | } | | 4862 | } |
4828 | cmd |= WTX_TCPIP_CMD_TSE; | | 4863 | cmd |= WTX_TCPIP_CMD_TSE; |
4829 | cmdlen |= WTX_TCPIP_CMD_TSE | | | 4864 | cmdlen |= WTX_TCPIP_CMD_TSE | |
4830 | WTX_TCPIP_CMD_TCP | (m0->m_pkthdr.len - hlen); | | 4865 | WTX_TCPIP_CMD_TCP | (m0->m_pkthdr.len - hlen); |
4831 | seg = WTX_TCPIP_SEG_HDRLEN(hlen) | | | 4866 | seg = WTX_TCPIP_SEG_HDRLEN(hlen) | |
4832 | WTX_TCPIP_SEG_MSS(m0->m_pkthdr.segsz); | | 4867 | WTX_TCPIP_SEG_MSS(m0->m_pkthdr.segsz); |
4833 | } | | 4868 | } |
4834 | | | 4869 | |
4835 | /* | | 4870 | /* |
4836 | * NOTE: Even if we're not using the IP or TCP/UDP checksum | | 4871 | * NOTE: Even if we're not using the IP or TCP/UDP checksum |
4837 | * offload feature, if we load the context descriptor, we | | 4872 | * offload feature, if we load the context descriptor, we |
4838 | * MUST provide valid values for IPCSS and TUCSS fields. | | 4873 | * MUST provide valid values for IPCSS and TUCSS fields. |
4839 | */ | | 4874 | */ |
4840 | | | 4875 | |
4841 | ipcs = WTX_TCPIP_IPCSS(offset) | | | 4876 | ipcs = WTX_TCPIP_IPCSS(offset) | |
4842 | WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | | | 4877 | WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | |
4843 | WTX_TCPIP_IPCSE(ipcse); | | 4878 | WTX_TCPIP_IPCSE(ipcse); |
4844 | if (m0->m_pkthdr.csum_flags & (M_CSUM_IPv4|M_CSUM_TSOv4)) { | | 4879 | if (m0->m_pkthdr.csum_flags & (M_CSUM_IPv4|M_CSUM_TSOv4)) { |
4845 | WM_EVCNT_INCR(&sc->sc_ev_txipsum); | | 4880 | WM_EVCNT_INCR(&sc->sc_ev_txipsum); |
4846 | fields |= WTX_IXSM; | | 4881 | fields |= WTX_IXSM; |
4847 | } | | 4882 | } |
4848 | | | 4883 | |
4849 | offset += iphl; | | 4884 | offset += iphl; |
4850 | | | 4885 | |
4851 | if (m0->m_pkthdr.csum_flags & | | 4886 | if (m0->m_pkthdr.csum_flags & |
4852 | (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TSOv4)) { | | 4887 | (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TSOv4)) { |
4853 | WM_EVCNT_INCR(&sc->sc_ev_txtusum); | | 4888 | WM_EVCNT_INCR(&sc->sc_ev_txtusum); |
4854 | fields |= WTX_TXSM; | | 4889 | fields |= WTX_TXSM; |
4855 | tucs = WTX_TCPIP_TUCSS(offset) | | | 4890 | tucs = WTX_TCPIP_TUCSS(offset) | |
4856 | WTX_TCPIP_TUCSO(offset + | | 4891 | WTX_TCPIP_TUCSO(offset + |
4857 | M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) | | | 4892 | M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) | |
4858 | WTX_TCPIP_TUCSE(0) /* rest of packet */; | | 4893 | WTX_TCPIP_TUCSE(0) /* rest of packet */; |
4859 | } else if ((m0->m_pkthdr.csum_flags & | | 4894 | } else if ((m0->m_pkthdr.csum_flags & |
4860 | (M_CSUM_TCPv6|M_CSUM_UDPv6|M_CSUM_TSOv6)) != 0) { | | 4895 | (M_CSUM_TCPv6|M_CSUM_UDPv6|M_CSUM_TSOv6)) != 0) { |
4861 | WM_EVCNT_INCR(&sc->sc_ev_txtusum6); | | 4896 | WM_EVCNT_INCR(&sc->sc_ev_txtusum6); |
4862 | fields |= WTX_TXSM; | | 4897 | fields |= WTX_TXSM; |
4863 | tucs = WTX_TCPIP_TUCSS(offset) | | | 4898 | tucs = WTX_TCPIP_TUCSS(offset) | |
4864 | WTX_TCPIP_TUCSO(offset + | | 4899 | WTX_TCPIP_TUCSO(offset + |
4865 | M_CSUM_DATA_IPv6_OFFSET(m0->m_pkthdr.csum_data)) | | | 4900 | M_CSUM_DATA_IPv6_OFFSET(m0->m_pkthdr.csum_data)) | |
4866 | WTX_TCPIP_TUCSE(0) /* rest of packet */; | | 4901 | WTX_TCPIP_TUCSE(0) /* rest of packet */; |
4867 | } else { | | 4902 | } else { |
4868 | /* Just initialize it to a valid TCP context. */ | | 4903 | /* Just initialize it to a valid TCP context. */ |
4869 | tucs = WTX_TCPIP_TUCSS(offset) | | | 4904 | tucs = WTX_TCPIP_TUCSS(offset) | |
4870 | WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | | | 4905 | WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | |
4871 | WTX_TCPIP_TUCSE(0) /* rest of packet */; | | 4906 | WTX_TCPIP_TUCSE(0) /* rest of packet */; |
4872 | } | | 4907 | } |
4873 | | | 4908 | |
4874 | /* Fill in the context descriptor. */ | | 4909 | /* Fill in the context descriptor. */ |
4875 | t = (struct livengood_tcpip_ctxdesc *) | | 4910 | t = (struct livengood_tcpip_ctxdesc *) |
4876 | &txq->txq_descs[txq->txq_next]; | | 4911 | &txq->txq_descs[txq->txq_next]; |
4877 | t->tcpip_ipcs = htole32(ipcs); | | 4912 | t->tcpip_ipcs = htole32(ipcs); |
4878 | t->tcpip_tucs = htole32(tucs); | | 4913 | t->tcpip_tucs = htole32(tucs); |
4879 | t->tcpip_cmdlen = htole32(cmdlen); | | 4914 | t->tcpip_cmdlen = htole32(cmdlen); |
4880 | t->tcpip_seg = htole32(seg); | | 4915 | t->tcpip_seg = htole32(seg); |
4881 | wm_cdtxsync(sc, txq->txq_next, 1, BUS_DMASYNC_PREWRITE); | | 4916 | wm_cdtxsync(sc, txq->txq_next, 1, BUS_DMASYNC_PREWRITE); |
4882 | | | 4917 | |
4883 | txq->txq_next = WM_NEXTTX(txq, txq->txq_next); | | 4918 | txq->txq_next = WM_NEXTTX(txq, txq->txq_next); |
4884 | txs->txs_ndesc++; | | 4919 | txs->txs_ndesc++; |
4885 | | | 4920 | |
4886 | *cmdp = cmd; | | 4921 | *cmdp = cmd; |
4887 | *fieldsp = fields; | | 4922 | *fieldsp = fields; |
4888 | | | 4923 | |
4889 | return 0; | | 4924 | return 0; |
4890 | } | | 4925 | } |
4891 | | | 4926 | |
4892 | static void | | 4927 | static void |
4893 | wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0) | | 4928 | wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0) |
4894 | { | | 4929 | { |
4895 | struct mbuf *m; | | 4930 | struct mbuf *m; |
4896 | int i; | | 4931 | int i; |
4897 | | | 4932 | |
4898 | log(LOG_DEBUG, "%s: mbuf chain:\n", device_xname(sc->sc_dev)); | | 4933 | log(LOG_DEBUG, "%s: mbuf chain:\n", device_xname(sc->sc_dev)); |
4899 | for (m = m0, i = 0; m != NULL; m = m->m_next, i++) | | 4934 | for (m = m0, i = 0; m != NULL; m = m->m_next, i++) |
4900 | log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, " | | 4935 | log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, " |
4901 | "m_flags = 0x%08x\n", device_xname(sc->sc_dev), | | 4936 | "m_flags = 0x%08x\n", device_xname(sc->sc_dev), |
4902 | m->m_data, m->m_len, m->m_flags); | | 4937 | m->m_data, m->m_len, m->m_flags); |
4903 | log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", device_xname(sc->sc_dev), | | 4938 | log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", device_xname(sc->sc_dev), |
4904 | i, i == 1 ? "" : "s"); | | 4939 | i, i == 1 ? "" : "s"); |
4905 | } | | 4940 | } |
4906 | | | 4941 | |
4907 | /* | | 4942 | /* |
4908 | * wm_82547_txfifo_stall: | | 4943 | * wm_82547_txfifo_stall: |
4909 | * | | 4944 | * |
4910 | * Callout used to wait for the 82547 Tx FIFO to drain, | | 4945 | * Callout used to wait for the 82547 Tx FIFO to drain, |
4911 | * reset the FIFO pointers, and restart packet transmission. | | 4946 | * reset the FIFO pointers, and restart packet transmission. |
4912 | */ | | 4947 | */ |
4913 | static void | | 4948 | static void |
4914 | wm_82547_txfifo_stall(void *arg) | | 4949 | wm_82547_txfifo_stall(void *arg) |
4915 | { | | 4950 | { |
4916 | struct wm_softc *sc = arg; | | 4951 | struct wm_softc *sc = arg; |
4917 | struct wm_txqueue *txq = sc->sc_txq; | | 4952 | struct wm_txqueue *txq = sc->sc_txq; |
4918 | #ifndef WM_MPSAFE | | 4953 | #ifndef WM_MPSAFE |
4919 | int s; | | 4954 | int s; |
4920 | | | 4955 | |
4921 | s = splnet(); | | 4956 | s = splnet(); |
4922 | #endif | | 4957 | #endif |
4923 | WM_TX_LOCK(txq); | | 4958 | WM_TX_LOCK(txq); |
4924 | | | 4959 | |
4925 | if (sc->sc_stopping) | | 4960 | if (sc->sc_stopping) |
4926 | goto out; | | 4961 | goto out; |
4927 | | | 4962 | |
4928 | if (txq->txq_fifo_stall) { | | 4963 | if (txq->txq_fifo_stall) { |
4929 | if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) && | | 4964 | if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) && |
4930 | CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) && | | 4965 | CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) && |
4931 | CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) { | | 4966 | CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) { |
4932 | /* | | 4967 | /* |
4933 | * Packets have drained. Stop transmitter, reset | | 4968 | * Packets have drained. Stop transmitter, reset |
4934 | * FIFO pointers, restart transmitter, and kick | | 4969 | * FIFO pointers, restart transmitter, and kick |
4935 | * the packet queue. | | 4970 | * the packet queue. |
4936 | */ | | 4971 | */ |
4937 | uint32_t tctl = CSR_READ(sc, WMREG_TCTL); | | 4972 | uint32_t tctl = CSR_READ(sc, WMREG_TCTL); |
4938 | CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN); | | 4973 | CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN); |
4939 | CSR_WRITE(sc, WMREG_TDFT, txq->txq_fifo_addr); | | 4974 | CSR_WRITE(sc, WMREG_TDFT, txq->txq_fifo_addr); |
4940 | CSR_WRITE(sc, WMREG_TDFH, txq->txq_fifo_addr); | | 4975 | CSR_WRITE(sc, WMREG_TDFH, txq->txq_fifo_addr); |
4941 | CSR_WRITE(sc, WMREG_TDFTS, txq->txq_fifo_addr); | | 4976 | CSR_WRITE(sc, WMREG_TDFTS, txq->txq_fifo_addr); |
4942 | CSR_WRITE(sc, WMREG_TDFHS, txq->txq_fifo_addr); | | 4977 | CSR_WRITE(sc, WMREG_TDFHS, txq->txq_fifo_addr); |
4943 | CSR_WRITE(sc, WMREG_TCTL, tctl); | | 4978 | CSR_WRITE(sc, WMREG_TCTL, tctl); |
4944 | CSR_WRITE_FLUSH(sc); | | 4979 | CSR_WRITE_FLUSH(sc); |
4945 | | | 4980 | |
4946 | txq->txq_fifo_head = 0; | | 4981 | txq->txq_fifo_head = 0; |
4947 | txq->txq_fifo_stall = 0; | | 4982 | txq->txq_fifo_stall = 0; |
4948 | wm_start_locked(&sc->sc_ethercom.ec_if); | | 4983 | wm_start_locked(&sc->sc_ethercom.ec_if); |
4949 | } else { | | 4984 | } else { |
4950 | /* | | 4985 | /* |
4951 | * Still waiting for packets to drain; try again in | | 4986 | * Still waiting for packets to drain; try again in |
4952 | * another tick. | | 4987 | * another tick. |
4953 | */ | | 4988 | */ |
4954 | callout_schedule(&sc->sc_txfifo_ch, 1); | | 4989 | callout_schedule(&sc->sc_txfifo_ch, 1); |
4955 | } | | 4990 | } |
4956 | } | | 4991 | } |
4957 | | | 4992 | |
4958 | out: | | 4993 | out: |
4959 | WM_TX_UNLOCK(txq); | | 4994 | WM_TX_UNLOCK(txq); |
4960 | #ifndef WM_MPSAFE | | 4995 | #ifndef WM_MPSAFE |
4961 | splx(s); | | 4996 | splx(s); |
4962 | #endif | | 4997 | #endif |
4963 | } | | 4998 | } |
4964 | | | 4999 | |
4965 | /* | | 5000 | /* |
4966 | * wm_82547_txfifo_bugchk: | | 5001 | * wm_82547_txfifo_bugchk: |
4967 | * | | 5002 | * |
4968 | * Check for bug condition in the 82547 Tx FIFO. We need to | | 5003 | * Check for bug condition in the 82547 Tx FIFO. We need to |
4969 | * prevent enqueueing a packet that would wrap around the end | | 5004 | * prevent enqueueing a packet that would wrap around the end |
4970 | * if the Tx FIFO ring buffer, otherwise the chip will croak. | | 5005 | * if the Tx FIFO ring buffer, otherwise the chip will croak. |
4971 | * | | 5006 | * |
4972 | * We do this by checking the amount of space before the end | | 5007 | * We do this by checking the amount of space before the end |
4973 | * of the Tx FIFO buffer. If the packet will not fit, we "stall" | | 5008 | * of the Tx FIFO buffer. If the packet will not fit, we "stall" |
4974 | * the Tx FIFO, wait for all remaining packets to drain, reset | | 5009 | * the Tx FIFO, wait for all remaining packets to drain, reset |
4975 | * the internal FIFO pointers to the beginning, and restart | | 5010 | * the internal FIFO pointers to the beginning, and restart |
4976 | * transmission on the interface. | | 5011 | * transmission on the interface. |
4977 | */ | | 5012 | */ |
4978 | #define WM_FIFO_HDR 0x10 | | 5013 | #define WM_FIFO_HDR 0x10 |
4979 | #define WM_82547_PAD_LEN 0x3e0 | | 5014 | #define WM_82547_PAD_LEN 0x3e0 |
4980 | static int | | 5015 | static int |
4981 | wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0) | | 5016 | wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0) |
4982 | { | | 5017 | { |
4983 | struct wm_txqueue *txq = sc->sc_txq; | | 5018 | struct wm_txqueue *txq = sc->sc_txq; |
4984 | int space = txq->txq_fifo_size - txq->txq_fifo_head; | | 5019 | int space = txq->txq_fifo_size - txq->txq_fifo_head; |
4985 | int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR); | | 5020 | int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR); |
4986 | | | 5021 | |
4987 | /* Just return if already stalled. */ | | 5022 | /* Just return if already stalled. */ |
4988 | if (txq->txq_fifo_stall) | | 5023 | if (txq->txq_fifo_stall) |
4989 | return 1; | | 5024 | return 1; |
4990 | | | 5025 | |
4991 | if (sc->sc_mii.mii_media_active & IFM_FDX) { | | 5026 | if (sc->sc_mii.mii_media_active & IFM_FDX) { |
4992 | /* Stall only occurs in half-duplex mode. */ | | 5027 | /* Stall only occurs in half-duplex mode. */ |
4993 | goto send_packet; | | 5028 | goto send_packet; |
4994 | } | | 5029 | } |
4995 | | | 5030 | |
4996 | if (len >= WM_82547_PAD_LEN + space) { | | 5031 | if (len >= WM_82547_PAD_LEN + space) { |
4997 | txq->txq_fifo_stall = 1; | | 5032 | txq->txq_fifo_stall = 1; |
4998 | callout_schedule(&sc->sc_txfifo_ch, 1); | | 5033 | callout_schedule(&sc->sc_txfifo_ch, 1); |
4999 | return 1; | | 5034 | return 1; |
5000 | } | | 5035 | } |
5001 | | | 5036 | |
5002 | send_packet: | | 5037 | send_packet: |
5003 | txq->txq_fifo_head += len; | | 5038 | txq->txq_fifo_head += len; |
5004 | if (txq->txq_fifo_head >= txq->txq_fifo_size) | | 5039 | if (txq->txq_fifo_head >= txq->txq_fifo_size) |
5005 | txq->txq_fifo_head -= txq->txq_fifo_size; | | 5040 | txq->txq_fifo_head -= txq->txq_fifo_size; |
5006 | | | 5041 | |
5007 | return 0; | | 5042 | return 0; |
5008 | } | | 5043 | } |
5009 | | | 5044 | |
5010 | static int | | 5045 | static int |
5011 | wm_alloc_tx_descs(struct wm_softc *sc) | | 5046 | wm_alloc_tx_descs(struct wm_softc *sc) |
5012 | { | | 5047 | { |
5013 | struct wm_txqueue *txq = sc->sc_txq; | | 5048 | struct wm_txqueue *txq = sc->sc_txq; |
5014 | int error; | | 5049 | int error; |
5015 | | | 5050 | |
5016 | /* | | 5051 | /* |
5017 | * Allocate the control data structures, and create and load the | | 5052 | * Allocate the control data structures, and create and load the |
5018 | * DMA map for it. | | 5053 | * DMA map for it. |
5019 | * | | 5054 | * |
5020 | * NOTE: All Tx descriptors must be in the same 4G segment of | | 5055 | * NOTE: All Tx descriptors must be in the same 4G segment of |
5021 | * memory. So must Rx descriptors. We simplify by allocating | | 5056 | * memory. So must Rx descriptors. We simplify by allocating |
5022 | * both sets within the same 4G segment. | | 5057 | * both sets within the same 4G segment. |
5023 | */ | | 5058 | */ |
5024 | if (sc->sc_type < WM_T_82544) { | | 5059 | if (sc->sc_type < WM_T_82544) { |
5025 | WM_NTXDESC(txq) = WM_NTXDESC_82542; | | 5060 | WM_NTXDESC(txq) = WM_NTXDESC_82542; |
5026 | txq->txq_desc_size = sizeof(wiseman_txdesc_t) * WM_NTXDESC(txq); | | 5061 | txq->txq_desc_size = sizeof(wiseman_txdesc_t) * WM_NTXDESC(txq); |
5027 | } else { | | 5062 | } else { |
5028 | WM_NTXDESC(txq) = WM_NTXDESC_82544; | | 5063 | WM_NTXDESC(txq) = WM_NTXDESC_82544; |
5029 | txq->txq_desc_size = sizeof(txdescs_t); | | 5064 | txq->txq_desc_size = sizeof(txdescs_t); |
5030 | } | | 5065 | } |
5031 | | | 5066 | |
5032 | if ((error = bus_dmamem_alloc(sc->sc_dmat, txq->txq_desc_size, PAGE_SIZE, | | 5067 | if ((error = bus_dmamem_alloc(sc->sc_dmat, txq->txq_desc_size, PAGE_SIZE, |
5033 | (bus_size_t) 0x100000000ULL, &txq->txq_desc_seg, 1, | | 5068 | (bus_size_t) 0x100000000ULL, &txq->txq_desc_seg, 1, |
5034 | &txq->txq_desc_rseg, 0)) != 0) { | | 5069 | &txq->txq_desc_rseg, 0)) != 0) { |
5035 | aprint_error_dev(sc->sc_dev, | | 5070 | aprint_error_dev(sc->sc_dev, |
5036 | "unable to allocate TX control data, error = %d\n", | | 5071 | "unable to allocate TX control data, error = %d\n", |
5037 | error); | | 5072 | error); |
5038 | goto fail_0; | | 5073 | goto fail_0; |
5039 | } | | 5074 | } |
5040 | | | 5075 | |
5041 | if ((error = bus_dmamem_map(sc->sc_dmat, &txq->txq_desc_seg, | | 5076 | if ((error = bus_dmamem_map(sc->sc_dmat, &txq->txq_desc_seg, |
5042 | txq->txq_desc_rseg, txq->txq_desc_size, | | 5077 | txq->txq_desc_rseg, txq->txq_desc_size, |
5043 | (void **)&txq->txq_descs_u, BUS_DMA_COHERENT)) != 0) { | | 5078 | (void **)&txq->txq_descs_u, BUS_DMA_COHERENT)) != 0) { |
5044 | aprint_error_dev(sc->sc_dev, | | 5079 | aprint_error_dev(sc->sc_dev, |
5045 | "unable to map TX control data, error = %d\n", error); | | 5080 | "unable to map TX control data, error = %d\n", error); |
5046 | goto fail_1; | | 5081 | goto fail_1; |
5047 | } | | 5082 | } |
5048 | | | 5083 | |
5049 | if ((error = bus_dmamap_create(sc->sc_dmat, txq->txq_desc_size, 1, | | 5084 | if ((error = bus_dmamap_create(sc->sc_dmat, txq->txq_desc_size, 1, |
5050 | txq->txq_desc_size, 0, 0, &txq->txq_desc_dmamap)) != 0) { | | 5085 | txq->txq_desc_size, 0, 0, &txq->txq_desc_dmamap)) != 0) { |
5051 | aprint_error_dev(sc->sc_dev, | | 5086 | aprint_error_dev(sc->sc_dev, |
5052 | "unable to create TX control data DMA map, error = %d\n", | | 5087 | "unable to create TX control data DMA map, error = %d\n", |
5053 | error); | | 5088 | error); |
5054 | goto fail_2; | | 5089 | goto fail_2; |
5055 | } | | 5090 | } |
5056 | | | 5091 | |
5057 | if ((error = bus_dmamap_load(sc->sc_dmat, txq->txq_desc_dmamap, | | 5092 | if ((error = bus_dmamap_load(sc->sc_dmat, txq->txq_desc_dmamap, |
5058 | txq->txq_descs_u, txq->txq_desc_size, NULL, 0)) != 0) { | | 5093 | txq->txq_descs_u, txq->txq_desc_size, NULL, 0)) != 0) { |
5059 | aprint_error_dev(sc->sc_dev, | | 5094 | aprint_error_dev(sc->sc_dev, |
5060 | "unable to load TX control data DMA map, error = %d\n", | | 5095 | "unable to load TX control data DMA map, error = %d\n", |
5061 | error); | | 5096 | error); |
5062 | goto fail_3; | | 5097 | goto fail_3; |
5063 | } | | 5098 | } |
5064 | | | 5099 | |
5065 | return 0; | | 5100 | return 0; |
5066 | | | 5101 | |
5067 | fail_3: | | 5102 | fail_3: |
5068 | bus_dmamap_destroy(sc->sc_dmat, txq->txq_desc_dmamap); | | 5103 | bus_dmamap_destroy(sc->sc_dmat, txq->txq_desc_dmamap); |
5069 | fail_2: | | 5104 | fail_2: |
5070 | bus_dmamem_unmap(sc->sc_dmat, (void *)txq->txq_descs_u, | | 5105 | bus_dmamem_unmap(sc->sc_dmat, (void *)txq->txq_descs_u, |
5071 | txq->txq_desc_size); | | 5106 | txq->txq_desc_size); |
5072 | fail_1: | | 5107 | fail_1: |
5073 | bus_dmamem_free(sc->sc_dmat, &txq->txq_desc_seg, txq->txq_desc_rseg); | | 5108 | bus_dmamem_free(sc->sc_dmat, &txq->txq_desc_seg, txq->txq_desc_rseg); |
5074 | fail_0: | | 5109 | fail_0: |
5075 | return error; | | 5110 | return error; |
5076 | } | | 5111 | } |
5077 | | | 5112 | |
5078 | static void | | 5113 | static void |
5079 | wm_free_tx_descs(struct wm_softc *sc) | | 5114 | wm_free_tx_descs(struct wm_softc *sc) |
5080 | { | | 5115 | { |
5081 | struct wm_txqueue *txq = sc->sc_txq; | | 5116 | struct wm_txqueue *txq = sc->sc_txq; |
5082 | | | 5117 | |
5083 | bus_dmamap_unload(sc->sc_dmat, txq->txq_desc_dmamap); | | 5118 | bus_dmamap_unload(sc->sc_dmat, txq->txq_desc_dmamap); |
5084 | bus_dmamap_destroy(sc->sc_dmat, txq->txq_desc_dmamap); | | 5119 | bus_dmamap_destroy(sc->sc_dmat, txq->txq_desc_dmamap); |
5085 | bus_dmamem_unmap(sc->sc_dmat, (void *)txq->txq_descs_u, | | 5120 | bus_dmamem_unmap(sc->sc_dmat, (void *)txq->txq_descs_u, |
5086 | txq->txq_desc_size); | | 5121 | txq->txq_desc_size); |
5087 | bus_dmamem_free(sc->sc_dmat, &txq->txq_desc_seg, txq->txq_desc_rseg); | | 5122 | bus_dmamem_free(sc->sc_dmat, &txq->txq_desc_seg, txq->txq_desc_rseg); |
5088 | } | | 5123 | } |
5089 | | | 5124 | |
5090 | static int | | 5125 | static int |
5091 | wm_alloc_rx_descs(struct wm_softc *sc) | | 5126 | wm_alloc_rx_descs(struct wm_softc *sc) |
5092 | { | | 5127 | { |
5093 | struct wm_rxqueue *rxq = sc->sc_rxq; | | 5128 | struct wm_rxqueue *rxq = sc->sc_rxq; |
5094 | int error; | | 5129 | int error; |
5095 | | | 5130 | |
5096 | /* | | 5131 | /* |
5097 | * Allocate the control data structures, and create and load the | | 5132 | * Allocate the control data structures, and create and load the |
5098 | * DMA map for it. | | 5133 | * DMA map for it. |
5099 | * | | 5134 | * |
5100 | * NOTE: All Tx descriptors must be in the same 4G segment of | | 5135 | * NOTE: All Tx descriptors must be in the same 4G segment of |
5101 | * memory. So must Rx descriptors. We simplify by allocating | | 5136 | * memory. So must Rx descriptors. We simplify by allocating |
5102 | * both sets within the same 4G segment. | | 5137 | * both sets within the same 4G segment. |
5103 | */ | | 5138 | */ |
5104 | rxq->rxq_desc_size = sizeof(wiseman_rxdesc_t) * WM_NRXDESC; | | 5139 | rxq->rxq_desc_size = sizeof(wiseman_rxdesc_t) * WM_NRXDESC; |
5105 | if ((error = bus_dmamem_alloc(sc->sc_dmat, rxq->rxq_desc_size, PAGE_SIZE, | | 5140 | if ((error = bus_dmamem_alloc(sc->sc_dmat, rxq->rxq_desc_size, PAGE_SIZE, |