 @@ -1,1085 +1,1085 @@
-/*	$NetBSD: if_wm.c,v 1.366 2015/10/13 09:03:58 knakahara Exp $	*/
+/*	$NetBSD: if_wm.c,v 1.367 2015/10/13 09:10:01 knakahara Exp $	*/
 /*
  * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed for the NetBSD Project by
  *	Wasabi Systems, Inc.
  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  *    or promote products derived from this software without specific prior
  *    written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*******************************************************************************
   Copyright (c) 2001-2005, Intel Corporation
   All rights reserved.
   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions are met:
 . Redistributions of source code must retain the above copyright notice,
       this list of conditions and the following disclaimer.
 . Redistributions in binary form must reproduce the above copyright
       notice, this list of conditions and the following disclaimer in the
       documentation and/or other materials provided with the distribution.
 . Neither the name of the Intel Corporation nor the names of its
       contributors may be used to endorse or promote products derived from
       this software without specific prior written permission.
   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************/
 /*
  * Device driver for the Intel i8254x family of Gigabit Ethernet chips.
+ *
  * TODO (in order of importance):
+ *
  *	- Check XXX'ed comments
  *	- EEE (Energy Efficiency Ethernet)
  *	- Multi queue
  *	- Image Unique ID
  *	- LPLU other than PCH*
  *	- Virtual Function
  *	- Set LED correctly (based on contents in EEPROM)
  *	- Rework how parameters are loaded from the EEPROM.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.366 2015/10/13 09:03:58 knakahara Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.367 2015/10/13 09:10:01 knakahara Exp $");
 #ifdef _KERNEL_OPT
 #include "opt_net_mpsafe.h"
 #endif
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/callout.h>
 #include <sys/mbuf.h>
 #include <sys/malloc.h>
 #include <sys/kmem.h>
 #include <sys/kernel.h>
 #include <sys/socket.h>
 #include <sys/ioctl.h>
 #include <sys/errno.h>
 #include <sys/device.h>
 #include <sys/queue.h>
 #include <sys/syslog.h>
 #include <sys/interrupt.h>
 #include <sys/rndsource.h>
 #include <net/if.h>
 #include <net/if_dl.h>
 #include <net/if_media.h>
 #include <net/if_ether.h>
 #include <net/bpf.h>
 #include <netinet/in.h>			/* XXX for struct ip */
 #include <netinet/in_systm.h>		/* XXX for struct ip */
 #include <netinet/ip.h>			/* XXX for struct ip */
 #include <netinet/ip6.h>		/* XXX for struct ip6_hdr */
 #include <netinet/tcp.h>		/* XXX for struct tcphdr */
 #include <sys/bus.h>
 #include <sys/intr.h>
 #include <machine/endian.h>
 #include <dev/mii/mii.h>
 #include <dev/mii/miivar.h>
 #include <dev/mii/miidevs.h>
 #include <dev/mii/mii_bitbang.h>
 #include <dev/mii/ikphyreg.h>
 #include <dev/mii/igphyreg.h>
 #include <dev/mii/igphyvar.h>
 #include <dev/mii/inbmphyreg.h>
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
 #include <dev/pci/pcidevs.h>
 #include <dev/pci/if_wmreg.h>
 #include <dev/pci/if_wmvar.h>
 #ifdef WM_DEBUG
 #define	WM_DEBUG_LINK		0x01
 #define	WM_DEBUG_TX		0x02
 #define	WM_DEBUG_RX		0x04
 #define	WM_DEBUG_GMII		0x08
 #define	WM_DEBUG_MANAGE		0x10
 #define	WM_DEBUG_NVM		0x20
 int	wm_debug = WM_DEBUG_TX | WM_DEBUG_RX | WM_DEBUG_LINK | WM_DEBUG_GMII
     | WM_DEBUG_MANAGE | WM_DEBUG_NVM;
 #define	DPRINTF(x, y)	if (wm_debug & (x)) printf y
 #else
 #define	DPRINTF(x, y)	/* nothing */
 #endif /* WM_DEBUG */
 #ifdef NET_MPSAFE
 #define WM_MPSAFE	1
 #endif
 #ifdef __HAVE_PCI_MSI_MSIX
 #define WM_MSI_MSIX	1 /* Enable by default */
 #endif
 /*
  * This device driver's max interrupt numbers.
  */
 #define WM_MAX_NTXINTR		16
 #define WM_MAX_NRXINTR		16
 #define WM_MAX_NINTR		(WM_MAX_NTXINTR + WM_MAX_NRXINTR + 1)
 /*
  * Transmit descriptor list size.  Due to errata, we can only have
  * 256 hardware descriptors in the ring on < 82544, but we use 4096
  * on >= 82544.  We tell the upper layers that they can queue a lot
  * of packets, and we go ahead and manage up to 64 (16 for the i82547)
  * of them at a time.
+ *
  * We allow up to 256 (!) DMA segments per packet.  Pathological packet
  * chains containing many small mbufs have been observed in zero-copy
  * situations with jumbo frames.
  */
 #define	WM_NTXSEGS		256
 #define	WM_IFQUEUELEN		256
 #define	WM_TXQUEUELEN_MAX	64
 #define	WM_TXQUEUELEN_MAX_82547	16
 #define	WM_TXQUEUELEN(txq)	((txq)->txq_num)
 #define	WM_TXQUEUELEN_MASK(txq)	(WM_TXQUEUELEN(txq) - 1)
 #define	WM_TXQUEUE_GC(txq)	(WM_TXQUEUELEN(txq) / 8)
 #define	WM_NTXDESC_82542	256
 #define	WM_NTXDESC_82544	4096
 #define	WM_NTXDESC(txq)		((txq)->txq_ndesc)
 #define	WM_NTXDESC_MASK(txq)	(WM_NTXDESC(txq) - 1)
 #define	WM_TXDESCSIZE(txq)	(WM_NTXDESC(txq) * sizeof(wiseman_txdesc_t))
 #define	WM_NEXTTX(txq, x)	(((x) + 1) & WM_NTXDESC_MASK(txq))
 #define	WM_NEXTTXS(txq, x)	(((x) + 1) & WM_TXQUEUELEN_MASK(txq))
 #define	WM_MAXTXDMA		 (2 * round_page(IP_MAXPACKET)) /* for TSO */
 /*
  * Receive descriptor list size.  We have one Rx buffer for normal
  * sized packets.  Jumbo packets consume 5 Rx buffers for a full-sized
  * packet.  We allocate 256 receive descriptors, each with a 2k
  * buffer (MCLBYTES), which gives us room for 50 jumbo packets.
  */
 #define	WM_NRXDESC		256
 #define	WM_NRXDESC_MASK		(WM_NRXDESC - 1)
 #define	WM_NEXTRX(x)		(((x) + 1) & WM_NRXDESC_MASK)
 #define	WM_PREVRX(x)		(((x) - 1) & WM_NRXDESC_MASK)
 typedef union txdescs {
 	wiseman_txdesc_t sctxu_txdescs[WM_NTXDESC_82544];
 	nq_txdesc_t      sctxu_nq_txdescs[WM_NTXDESC_82544];
 } txdescs_t;
 #define	WM_CDTXOFF(x)	(sizeof(wiseman_txdesc_t) * x)
 #define	WM_CDRXOFF(x)	(sizeof(wiseman_rxdesc_t) * x)
 /*
  * Software state for transmit jobs.
  */
 struct wm_txsoft {
 	struct mbuf *txs_mbuf;		/* head of our mbuf chain */
 	bus_dmamap_t txs_dmamap;	/* our DMA map */
 	int txs_firstdesc;		/* first descriptor in packet */
 	int txs_lastdesc;		/* last descriptor in packet */
 	int txs_ndesc;			/* # of descriptors used */
 };
 /*
  * Software state for receive buffers.  Each descriptor gets a
  * 2k (MCLBYTES) buffer and a DMA map.  For packets which fill
  * more than one buffer, we chain them together.
  */
 struct wm_rxsoft {
 	struct mbuf *rxs_mbuf;		/* head of our mbuf chain */
 	bus_dmamap_t rxs_dmamap;	/* our DMA map */
 };
 #define WM_LINKUP_TIMEOUT	50
 static uint16_t swfwphysem[] = {
 	SWFW_PHY0_SM,
 	SWFW_PHY1_SM,
 	SWFW_PHY2_SM,
 	SWFW_PHY3_SM
 };
 static const uint32_t wm_82580_rxpbs_table[] = {
 , 72, 144, 1, 2, 4, 8, 16, 35, 70, 140
 };
 struct wm_softc;
 struct wm_txqueue {
 	kmutex_t *txq_lock;		/* lock for tx operations */
 	struct wm_softc *txq_sc;
 	int txq_id;			/* index of transmit queues */
 	int txq_intr_idx;		/* index of MSI-X tables */
 	/* Software state for the transmit descriptors. */
 	int txq_num;			/* must be a power of two */
 	struct wm_txsoft txq_soft[WM_TXQUEUELEN_MAX];
 	/* TX control data structures. */
 	int txq_ndesc;			/* must be a power of two */
 	txdescs_t *txq_descs_u;
         bus_dmamap_t txq_desc_dmamap;	/* control data DMA map */
 	bus_dma_segment_t txq_desc_seg;	/* control data segment */
 	int txq_desc_rseg;		/* real number of control segment */
 	size_t txq_desc_size;		/* control data size */
 #define	txq_desc_dma	txq_desc_dmamap->dm_segs[0].ds_addr
 #define	txq_descs	txq_descs_u->sctxu_txdescs
 #define	txq_nq_descs	txq_descs_u->sctxu_nq_txdescs
 	bus_addr_t txq_tdt_reg;		/* offset of TDT register */
 	int txq_free;			/* number of free Tx descriptors */
 	int txq_next;			/* next ready Tx descriptor */
 	int txq_sfree;			/* number of free Tx jobs */
 	int txq_snext;			/* next free Tx job */
 	int txq_sdirty;			/* dirty Tx jobs */
 	/* These 4 variables are used only on the 82547. */
 	int txq_fifo_size;		/* Tx FIFO size */
 	int txq_fifo_head;		/* current head of FIFO */
 	uint32_t txq_fifo_addr;		/* internal address of start of FIFO */
 	int txq_fifo_stall;		/* Tx FIFO is stalled */
 	/* XXX which event counter is required? */
 };
 struct wm_rxqueue {
 	kmutex_t *rxq_lock;		/* lock for rx operations */
 	struct wm_softc *rxq_sc;
 	int rxq_id;			/* index of receive queues */
 	int rxq_intr_idx;		/* index of MSI-X tables */
 	/* Software state for the receive descriptors. */
 	wiseman_rxdesc_t *rxq_descs;
 	/* RX control data structures. */
 	struct wm_rxsoft rxq_soft[WM_NRXDESC];
 	bus_dmamap_t rxq_desc_dmamap;	/* control data DMA map */
 	bus_dma_segment_t rxq_desc_seg;	/* control data segment */
 	int rxq_desc_rseg;		/* real number of control segment */
 	size_t rxq_desc_size;		/* control data size */
 #define	rxq_desc_dma	rxq_desc_dmamap->dm_segs[0].ds_addr
 	bus_addr_t rxq_rdt_reg;		/* offset of RDT register */
 	int rxq_ptr;			/* next ready Rx descriptor/queue ent */
 	int rxq_discard;
 	int rxq_len;
 	struct mbuf *rxq_head;
 	struct mbuf *rxq_tail;
 	struct mbuf **rxq_tailp;
 	/* XXX which event counter is required? */
 };
 /*
  * Software state per device.
  */
 struct wm_softc {
 	device_t sc_dev;		/* generic device information */
 	bus_space_tag_t sc_st;		/* bus space tag */
 	bus_space_handle_t sc_sh;	/* bus space handle */
 	bus_size_t sc_ss;		/* bus space size */
 	bus_space_tag_t sc_iot;		/* I/O space tag */
 	bus_space_handle_t sc_ioh;	/* I/O space handle */
 	bus_size_t sc_ios;		/* I/O space size */
 	bus_space_tag_t sc_flasht;	/* flash registers space tag */
 	bus_space_handle_t sc_flashh;	/* flash registers space handle */
 	bus_size_t sc_flashs;		/* flash registers space size */
 	bus_dma_tag_t sc_dmat;		/* bus DMA tag */
 	struct ethercom sc_ethercom;	/* ethernet common data */
 	struct mii_data sc_mii;		/* MII/media information */
 	pci_chipset_tag_t sc_pc;
 	pcitag_t sc_pcitag;
 	int sc_bus_speed;		/* PCI/PCIX bus speed */
 	int sc_pcixe_capoff;		/* PCI[Xe] capability reg offset */
 	uint16_t sc_pcidevid;		/* PCI device ID */
 	wm_chip_type sc_type;		/* MAC type */
 	int sc_rev;			/* MAC revision */
 	wm_phy_type sc_phytype;		/* PHY type */
 	uint32_t sc_mediatype;		/* Media type (Copper, Fiber, SERDES)*/
 #define	WM_MEDIATYPE_UNKNOWN		0x00
 #define	WM_MEDIATYPE_FIBER		0x01
 #define	WM_MEDIATYPE_COPPER		0x02
 #define	WM_MEDIATYPE_SERDES		0x03 /* Internal SERDES */
 	int sc_funcid;			/* unit number of the chip (0 to 3) */
 	int sc_flags;			/* flags; see below */
 	int sc_if_flags;		/* last if_flags */
 	int sc_flowflags;		/* 802.3x flow control flags */
 	int sc_align_tweak;
 	void *sc_ihs[WM_MAX_NINTR];	/*
 					 * interrupt cookie.
 					 * legacy and msi use sc_ihs[0].
 					 */
 	pci_intr_handle_t *sc_intrs;	/* legacy and msi use sc_intrs[0] */
 	int sc_nintrs;			/* number of interrupts */
 	int sc_link_intr_idx;		/* index of MSI-X tables */
 	callout_t sc_tick_ch;		/* tick callout */
 	bool sc_stopping;
 	int sc_nvm_ver_major;
 	int sc_nvm_ver_minor;
 	int sc_nvm_ver_build;
 	int sc_nvm_addrbits;		/* NVM address bits */
 	unsigned int sc_nvm_wordsize;	/* NVM word size */
 	int sc_ich8_flash_base;
 	int sc_ich8_flash_bank_size;
 	int sc_nvm_k1_enabled;
 	int sc_ntxqueues;
 	struct wm_txqueue *sc_txq;
 	int sc_nrxqueues;
 	struct wm_rxqueue *sc_rxq;
 #ifdef WM_EVENT_COUNTERS
 	/* Event counters. */
 	struct evcnt sc_ev_txsstall;	/* Tx stalled due to no txs */
 	struct evcnt sc_ev_txdstall;	/* Tx stalled due to no txd */
 	struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */
 	struct evcnt sc_ev_txdw;	/* Tx descriptor interrupts */
 	struct evcnt sc_ev_txqe;	/* Tx queue empty interrupts */
 	struct evcnt sc_ev_rxintr;	/* Rx interrupts */
 	struct evcnt sc_ev_linkintr;	/* Link interrupts */
 	struct evcnt sc_ev_rxipsum;	/* IP checksums checked in-bound */
 	struct evcnt sc_ev_rxtusum;	/* TCP/UDP cksums checked in-bound */
 	struct evcnt sc_ev_txipsum;	/* IP checksums comp. out-bound */
 	struct evcnt sc_ev_txtusum;	/* TCP/UDP cksums comp. out-bound */
 	struct evcnt sc_ev_txtusum6;	/* TCP/UDP v6 cksums comp. out-bound */
 	struct evcnt sc_ev_txtso;	/* TCP seg offload out-bound (IPv4) */
 	struct evcnt sc_ev_txtso6;	/* TCP seg offload out-bound (IPv6) */
 	struct evcnt sc_ev_txtsopain;	/* painful header manip. for TSO */
 	struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */
 	struct evcnt sc_ev_txdrop;	/* Tx packets dropped (too many segs) */
 	struct evcnt sc_ev_tu;		/* Tx underrun */
 	struct evcnt sc_ev_tx_xoff;	/* Tx PAUSE(!0) frames */
 	struct evcnt sc_ev_tx_xon;	/* Tx PAUSE(0) frames */
 	struct evcnt sc_ev_rx_xoff;	/* Rx PAUSE(!0) frames */
 	struct evcnt sc_ev_rx_xon;	/* Rx PAUSE(0) frames */
 	struct evcnt sc_ev_rx_macctl;	/* Rx Unsupported */
 #endif /* WM_EVENT_COUNTERS */
 	/* This variable are used only on the 82547. */
 	callout_t sc_txfifo_ch;		/* Tx FIFO stall work-around timer */
 	uint32_t sc_ctrl;		/* prototype CTRL register */
 #if 0
 	uint32_t sc_ctrl_ext;		/* prototype CTRL_EXT register */
 #endif
 	uint32_t sc_icr;		/* prototype interrupt bits */
 	uint32_t sc_itr;		/* prototype intr throttling reg */
 	uint32_t sc_tctl;		/* prototype TCTL register */
 	uint32_t sc_rctl;		/* prototype RCTL register */
 	uint32_t sc_txcw;		/* prototype TXCW register */
 	uint32_t sc_tipg;		/* prototype TIPG register */
 	uint32_t sc_fcrtl;		/* prototype FCRTL register */
 	uint32_t sc_pba;		/* prototype PBA register */
 	int sc_tbi_linkup;		/* TBI link status */
 	int sc_tbi_serdes_anegticks;	/* autonegotiation ticks */
 	int sc_tbi_serdes_ticks;	/* tbi ticks */
 	int sc_mchash_type;		/* multicast filter offset */
 	krndsource_t rnd_source;	/* random source */
 	kmutex_t *sc_core_lock;		/* lock for softc operations */
 };
 #define WM_TX_LOCK(_txq)	if ((_txq)->txq_lock) mutex_enter((_txq)->txq_lock)
 #define WM_TX_UNLOCK(_txq)	if ((_txq)->txq_lock) mutex_exit((_txq)->txq_lock)
 #define WM_TX_LOCKED(_txq)	(!(_txq)->txq_lock || mutex_owned((_txq)->txq_lock))
 #define WM_RX_LOCK(_rxq)	if ((_rxq)->rxq_lock) mutex_enter((_rxq)->rxq_lock)
 #define WM_RX_UNLOCK(_rxq)	if ((_rxq)->rxq_lock) mutex_exit((_rxq)->rxq_lock)
 #define WM_RX_LOCKED(_rxq)	(!(_rxq)->rxq_lock || mutex_owned((_rxq)->rxq_lock))
 #define WM_CORE_LOCK(_sc)	if ((_sc)->sc_core_lock) mutex_enter((_sc)->sc_core_lock)
 #define WM_CORE_UNLOCK(_sc)	if ((_sc)->sc_core_lock) mutex_exit((_sc)->sc_core_lock)
 #define WM_CORE_LOCKED(_sc)	(!(_sc)->sc_core_lock || mutex_owned((_sc)->sc_core_lock))
 #ifdef WM_MPSAFE
 #define CALLOUT_FLAGS	CALLOUT_MPSAFE
 #else
 #define CALLOUT_FLAGS	0
 #endif
 #define	WM_RXCHAIN_RESET(rxq)						\
 do {									\
 	(rxq)->rxq_tailp = &(rxq)->rxq_head;				\
 	*(rxq)->rxq_tailp = NULL;					\
 	(rxq)->rxq_len = 0;						\
 } while (/*CONSTCOND*/0)
 #define	WM_RXCHAIN_LINK(rxq, m)						\
 do {									\
 	*(rxq)->rxq_tailp = (rxq)->rxq_tail = (m);			\
 	(rxq)->rxq_tailp = &(m)->m_next;				\
 } while (/*CONSTCOND*/0)
 #ifdef WM_EVENT_COUNTERS
 #define	WM_EVCNT_INCR(ev)	(ev)->ev_count++
 #define	WM_EVCNT_ADD(ev, val)	(ev)->ev_count += (val)
 #else
 #define	WM_EVCNT_INCR(ev)	/* nothing */
 #define	WM_EVCNT_ADD(ev, val)	/* nothing */
 #endif
 #define	CSR_READ(sc, reg)						\
 	bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
 #define	CSR_WRITE(sc, reg, val)						\
 	bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
 #define	CSR_WRITE_FLUSH(sc)						\
 	(void) CSR_READ((sc), WMREG_STATUS)
 #define ICH8_FLASH_READ32(sc, reg) \
 	bus_space_read_4((sc)->sc_flasht, (sc)->sc_flashh, (reg))
 #define ICH8_FLASH_WRITE32(sc, reg, data) \
 	bus_space_write_4((sc)->sc_flasht, (sc)->sc_flashh, (reg), (data))
 #define ICH8_FLASH_READ16(sc, reg) \
 	bus_space_read_2((sc)->sc_flasht, (sc)->sc_flashh, (reg))
 #define ICH8_FLASH_WRITE16(sc, reg, data) \
 	bus_space_write_2((sc)->sc_flasht, (sc)->sc_flashh, (reg), (data))
 #define	WM_CDTXADDR(txq, x)	((txq)->txq_desc_dma + WM_CDTXOFF((x)))
 #define	WM_CDRXADDR(rxq, x)	((rxq)->rxq_desc_dma + WM_CDRXOFF((x)))
 #define	WM_CDTXADDR_LO(txq, x)	(WM_CDTXADDR((txq), (x)) & 0xffffffffU)
 #define	WM_CDTXADDR_HI(txq, x)						\
 	(sizeof(bus_addr_t) == 8 ?					\
 	 (uint64_t)WM_CDTXADDR((txq), (x)) >> 32 : 0)
 #define	WM_CDRXADDR_LO(rxq, x)	(WM_CDRXADDR((rxq), (x)) & 0xffffffffU)
 #define	WM_CDRXADDR_HI(rxq, x)						\
 	(sizeof(bus_addr_t) == 8 ?					\
 	 (uint64_t)WM_CDRXADDR((rxq), (x)) >> 32 : 0)
 /*
  * Register read/write functions.
  * Other than CSR_{READ|WRITE}().
  */
 #if 0
 static inline uint32_t wm_io_read(struct wm_softc *, int);
 #endif
 static inline void wm_io_write(struct wm_softc *, int, uint32_t);
 static inline void wm_82575_write_8bit_ctlr_reg(struct wm_softc *, uint32_t,
 	uint32_t, uint32_t);
 static inline void wm_set_dma_addr(volatile wiseman_addr_t *, bus_addr_t);
 /*
  * Descriptor sync/init functions.
  */
 static inline void wm_cdtxsync(struct wm_txqueue *, int, int, int);
 static inline void wm_cdrxsync(struct wm_rxqueue *, int, int);
 static inline void wm_init_rxdesc(struct wm_rxqueue *, int);
 /*
  * Device driver interface functions and commonly used functions.
  * match, attach, detach, init, start, stop, ioctl, watchdog and so on.
  */
 static const struct wm_product *wm_lookup(const struct pci_attach_args *);
 static int	wm_match(device_t, cfdata_t, void *);
 static void	wm_attach(device_t, device_t, void *);
 static int	wm_detach(device_t, int);
 static bool	wm_suspend(device_t, const pmf_qual_t *);
 static bool	wm_resume(device_t, const pmf_qual_t *);
 static void	wm_watchdog(struct ifnet *);
 static void	wm_tick(void *);
 static int	wm_ifflags_cb(struct ethercom *);
 static int	wm_ioctl(struct ifnet *, u_long, void *);
 /* MAC address related */
 static uint16_t	wm_check_alt_mac_addr(struct wm_softc *);
 static int	wm_read_mac_addr(struct wm_softc *, uint8_t *);
 static void	wm_set_ral(struct wm_softc *, const uint8_t *, int);
 static uint32_t	wm_mchash(struct wm_softc *, const uint8_t *);
 static void	wm_set_filter(struct wm_softc *);
 /* Reset and init related */
 static void	wm_set_vlan(struct wm_softc *);
 static void	wm_set_pcie_completion_timeout(struct wm_softc *);
 static void	wm_get_auto_rd_done(struct wm_softc *);
 static void	wm_lan_init_done(struct wm_softc *);
 static void	wm_get_cfg_done(struct wm_softc *);
 static void	wm_initialize_hardware_bits(struct wm_softc *);
 static uint32_t	wm_rxpbs_adjust_82580(uint32_t);
 static void	wm_reset(struct wm_softc *);
 static int	wm_add_rxbuf(struct wm_rxqueue *, int);
 static void	wm_rxdrain(struct wm_rxqueue *);
 static void	wm_init_rss(struct wm_softc *);
 static int	wm_init(struct ifnet *);
 static int	wm_init_locked(struct ifnet *);
 static void	wm_stop(struct ifnet *, int);
 static void	wm_stop_locked(struct ifnet *, int);
 static int	wm_tx_offload(struct wm_softc *, struct wm_txsoft *,
     uint32_t *, uint8_t *);
 static void	wm_dump_mbuf_chain(struct wm_softc *, struct mbuf *);
 static void	wm_82547_txfifo_stall(void *);
 static int	wm_82547_txfifo_bugchk(struct wm_softc *, struct mbuf *);
 /* DMA related */
 static int	wm_alloc_tx_descs(struct wm_softc *, struct wm_txqueue *);
 static void	wm_free_tx_descs(struct wm_softc *, struct wm_txqueue *);
 static void	wm_init_tx_descs(struct wm_softc *, struct wm_txqueue *);
 static void	wm_init_tx_regs(struct wm_softc *, struct wm_txqueue *);
 static int	wm_alloc_rx_descs(struct wm_softc *, struct wm_rxqueue *);
 static void	wm_free_rx_descs(struct wm_softc *, struct wm_rxqueue *);
 static void	wm_init_rx_regs(struct wm_softc *, struct wm_rxqueue *);
 static int	wm_alloc_tx_buffer(struct wm_softc *, struct wm_txqueue *);
 static void	wm_free_tx_buffer(struct wm_softc *, struct wm_txqueue *);
 static void	wm_init_tx_buffer(struct wm_softc *, struct wm_txqueue *);
 static int	wm_alloc_rx_buffer(struct wm_softc *, struct wm_rxqueue *);
 static void	wm_free_rx_buffer(struct wm_softc *, struct wm_rxqueue *);
 static int	wm_init_rx_buffer(struct wm_softc *, struct wm_rxqueue *);
 static void	wm_init_tx_queue(struct wm_softc *, struct wm_txqueue *);
 static int	wm_init_rx_queue(struct wm_softc *, struct wm_rxqueue *);
 static int	wm_alloc_txrx_queues(struct wm_softc *);
 static void	wm_free_txrx_queues(struct wm_softc *);
 static int	wm_init_txrx_queues(struct wm_softc *);
 /* Start */
 static void	wm_start(struct ifnet *);
 static void	wm_start_locked(struct ifnet *);
 static int	wm_nq_tx_offload(struct wm_softc *, struct wm_txsoft *,
     uint32_t *, uint32_t *, bool *);
 static void	wm_nq_start(struct ifnet *);
 static void	wm_nq_start_locked(struct ifnet *);
 /* Interrupt */
 static int	wm_txeof(struct wm_softc *);
 static void	wm_rxeof(struct wm_rxqueue *);
 static void	wm_linkintr_gmii(struct wm_softc *, uint32_t);
 static void	wm_linkintr_tbi(struct wm_softc *, uint32_t);
 static void	wm_linkintr_serdes(struct wm_softc *, uint32_t);
 static void	wm_linkintr(struct wm_softc *, uint32_t);
 static int	wm_intr_legacy(void *);
 #ifdef WM_MSI_MSIX
 static void	wm_adjust_qnum(struct wm_softc *, int);
 static int	wm_setup_legacy(struct wm_softc *);
 static int	wm_setup_msix(struct wm_softc *);
 static int	wm_txintr_msix(void *);
 static int	wm_rxintr_msix(void *);
 static int	wm_linkintr_msix(void *);
 #endif
 /*
  * Media related.
  * GMII, SGMII, TBI, SERDES and SFP.
  */
 /* Common */
 static void	wm_tbi_serdes_set_linkled(struct wm_softc *);
 /* GMII related */
 static void	wm_gmii_reset(struct wm_softc *);
 static int	wm_get_phy_id_82575(struct wm_softc *);
 static void	wm_gmii_mediainit(struct wm_softc *, pci_product_id_t);
 static int	wm_gmii_mediachange(struct ifnet *);
 static void	wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *);
 static void	wm_i82543_mii_sendbits(struct wm_softc *, uint32_t, int);
 static uint32_t	wm_i82543_mii_recvbits(struct wm_softc *);
 static int	wm_gmii_i82543_readreg(device_t, int, int);
 static void	wm_gmii_i82543_writereg(device_t, int, int, int);
 static int	wm_gmii_i82544_readreg(device_t, int, int);
 static void	wm_gmii_i82544_writereg(device_t, int, int, int);
 static int	wm_gmii_i80003_readreg(device_t, int, int);
 static void	wm_gmii_i80003_writereg(device_t, int, int, int);
 static int	wm_gmii_bm_readreg(device_t, int, int);
 static void	wm_gmii_bm_writereg(device_t, int, int, int);
 static void	wm_access_phy_wakeup_reg_bm(device_t, int, int16_t *, int);
 static int	wm_gmii_hv_readreg(device_t, int, int);
 static void	wm_gmii_hv_writereg(device_t, int, int, int);
 static int	wm_gmii_82580_readreg(device_t, int, int);
 static void	wm_gmii_82580_writereg(device_t, int, int, int);
 static int	wm_gmii_gs40g_readreg(device_t, int, int);
 static void	wm_gmii_gs40g_writereg(device_t, int, int, int);
 static void	wm_gmii_statchg(struct ifnet *);
 static int	wm_kmrn_readreg(struct wm_softc *, int);
 static void	wm_kmrn_writereg(struct wm_softc *, int, int);
 /* SGMII */
 static bool	wm_sgmii_uses_mdio(struct wm_softc *);
 static int	wm_sgmii_readreg(device_t, int, int);
 static void	wm_sgmii_writereg(device_t, int, int, int);
 /* TBI related */
 static void	wm_tbi_mediainit(struct wm_softc *);
 static int	wm_tbi_mediachange(struct ifnet *);
 static void	wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *);
 static int	wm_check_for_link(struct wm_softc *);
 static void	wm_tbi_tick(struct wm_softc *);
 /* SERDES related */
 static void	wm_serdes_power_up_link_82575(struct wm_softc *);
 static int	wm_serdes_mediachange(struct ifnet *);
 static void	wm_serdes_mediastatus(struct ifnet *, struct ifmediareq *);
 static void	wm_serdes_tick(struct wm_softc *);
 /* SFP related */
 static int	wm_sfp_read_data_byte(struct wm_softc *, uint16_t, uint8_t *);
 static uint32_t	wm_sfp_get_media_type(struct wm_softc *);
 /*
  * NVM related.
  * Microwire, SPI (w/wo EERD) and Flash.
  */
 /* Misc functions */
 static void	wm_eeprom_sendbits(struct wm_softc *, uint32_t, int);
 static void	wm_eeprom_recvbits(struct wm_softc *, uint32_t *, int);
 static int	wm_nvm_set_addrbits_size_eecd(struct wm_softc *);
 /* Microwire */
 static int	wm_nvm_read_uwire(struct wm_softc *, int, int, uint16_t *);
 /* SPI */
 static int	wm_nvm_ready_spi(struct wm_softc *);
 static int	wm_nvm_read_spi(struct wm_softc *, int, int, uint16_t *);
 /* Using with EERD */
 static int	wm_poll_eerd_eewr_done(struct wm_softc *, int);
 static int	wm_nvm_read_eerd(struct wm_softc *, int, int, uint16_t *);
 /* Flash */
 static int	wm_nvm_valid_bank_detect_ich8lan(struct wm_softc *,
     unsigned int *);
 static int32_t	wm_ich8_cycle_init(struct wm_softc *);
 static int32_t	wm_ich8_flash_cycle(struct wm_softc *, uint32_t);
 static int32_t	wm_read_ich8_data(struct wm_softc *, uint32_t, uint32_t,
 	uint16_t *);
 static int32_t	wm_read_ich8_byte(struct wm_softc *, uint32_t, uint8_t *);
 static int32_t	wm_read_ich8_word(struct wm_softc *, uint32_t, uint16_t *);
 static int	wm_nvm_read_ich8(struct wm_softc *, int, int, uint16_t *);
 /* iNVM */
 static int	wm_nvm_read_word_invm(struct wm_softc *, uint16_t, uint16_t *);
 static int	wm_nvm_read_invm(struct wm_softc *, int, int, uint16_t *);
 /* Lock, detecting NVM type, validate checksum and read */
 static int	wm_nvm_acquire(struct wm_softc *);
 static void	wm_nvm_release(struct wm_softc *);
 static int	wm_nvm_is_onboard_eeprom(struct wm_softc *);
 static int	wm_nvm_get_flash_presence_i210(struct wm_softc *);
 static int	wm_nvm_validate_checksum(struct wm_softc *);
 static void	wm_nvm_version_invm(struct wm_softc *);
 static void	wm_nvm_version(struct wm_softc *);
 static int	wm_nvm_read(struct wm_softc *, int, int, uint16_t *);
 /*
  * Hardware semaphores.
  * Very complexed...
  */
 static int	wm_get_swsm_semaphore(struct wm_softc *);
 static void	wm_put_swsm_semaphore(struct wm_softc *);
 static int	wm_get_swfw_semaphore(struct wm_softc *, uint16_t);
 static void	wm_put_swfw_semaphore(struct wm_softc *, uint16_t);
 static int	wm_get_swfwhw_semaphore(struct wm_softc *);
 static void	wm_put_swfwhw_semaphore(struct wm_softc *);
 static int	wm_get_hw_semaphore_82573(struct wm_softc *);
 static void	wm_put_hw_semaphore_82573(struct wm_softc *);
 /*
  * Management mode and power management related subroutines.
  * BMC, AMT, suspend/resume and EEE.
  */
 static int	wm_check_mng_mode(struct wm_softc *);
 static int	wm_check_mng_mode_ich8lan(struct wm_softc *);
 static int	wm_check_mng_mode_82574(struct wm_softc *);
 static int	wm_check_mng_mode_generic(struct wm_softc *);
 static int	wm_enable_mng_pass_thru(struct wm_softc *);
 static int	wm_check_reset_block(struct wm_softc *);
 static void	wm_get_hw_control(struct wm_softc *);
 static void	wm_release_hw_control(struct wm_softc *);
 static void	wm_gate_hw_phy_config_ich8lan(struct wm_softc *, int);
 static void	wm_smbustopci(struct wm_softc *);
 static void	wm_init_manageability(struct wm_softc *);
 static void	wm_release_manageability(struct wm_softc *);
 static void	wm_get_wakeup(struct wm_softc *);
 #ifdef WM_WOL
 static void	wm_enable_phy_wakeup(struct wm_softc *);
 static void	wm_igp3_phy_powerdown_workaround_ich8lan(struct wm_softc *);
 static void	wm_enable_wakeup(struct wm_softc *);
 #endif
 /* EEE */
 static void	wm_set_eee_i350(struct wm_softc *);
 /*
  * Workarounds (mainly PHY related).
  * Basically, PHY's workarounds are in the PHY drivers.
  */
 static void	wm_kmrn_lock_loss_workaround_ich8lan(struct wm_softc *);
 static void	wm_gig_downshift_workaround_ich8lan(struct wm_softc *);
 static void	wm_hv_phy_workaround_ich8lan(struct wm_softc *);
 static void	wm_lv_phy_workaround_ich8lan(struct wm_softc *);
 static void	wm_k1_gig_workaround_hv(struct wm_softc *, int);
 static void	wm_set_mdio_slow_mode_hv(struct wm_softc *);
 static void	wm_configure_k1_ich8lan(struct wm_softc *, int);
 static void	wm_reset_init_script_82575(struct wm_softc *);
 static void	wm_reset_mdicnfg_82580(struct wm_softc *);
 static void	wm_pll_workaround_i210(struct wm_softc *);
 CFATTACH_DECL3_NEW(wm, sizeof(struct wm_softc),
     wm_match, wm_attach, wm_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN);
 /*
  * Devices supported by this driver.
  */
 static const struct wm_product {
 	pci_vendor_id_t		wmp_vendor;
 	pci_product_id_t	wmp_product;
 	const char		*wmp_name;
 	wm_chip_type		wmp_type;
 	uint32_t		wmp_flags;
 #define	WMP_F_UNKNOWN		WM_MEDIATYPE_UNKNOWN
 #define	WMP_F_FIBER		WM_MEDIATYPE_FIBER
 #define	WMP_F_COPPER		WM_MEDIATYPE_COPPER
 #define	WMP_F_SERDES		WM_MEDIATYPE_SERDES
 #define WMP_MEDIATYPE(x)	((x) & 0x03)
 } wm_products[] = {
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82542,
 	  "Intel i82542 1000BASE-X Ethernet",
 	  WM_T_82542_2_1,	WMP_F_FIBER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82543GC_FIBER,
 	  "Intel i82543GC 1000BASE-X Ethernet",
 	  WM_T_82543,		WMP_F_FIBER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82543GC_COPPER,
 	  "Intel i82543GC 1000BASE-T Ethernet",
 	  WM_T_82543,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544EI_COPPER,
 	  "Intel i82544EI 1000BASE-T Ethernet",
 	  WM_T_82544,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544EI_FIBER,
 	  "Intel i82544EI 1000BASE-X Ethernet",
 	  WM_T_82544,		WMP_F_FIBER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544GC_COPPER,
 	  "Intel i82544GC 1000BASE-T Ethernet",
 	  WM_T_82544,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544GC_LOM,
 	  "Intel i82544GC (LOM) 1000BASE-T Ethernet",
 	  WM_T_82544,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EM,
 	  "Intel i82540EM 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EM_LOM,
 	  "Intel i82540EM (LOM) 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP_LOM,
 	  "Intel i82540EP 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP,
 	  "Intel i82540EP 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP_LP,
 	  "Intel i82540EP 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545EM_COPPER,
 	  "Intel i82545EM 1000BASE-T Ethernet",
 	  WM_T_82545,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_COPPER,
 	  "Intel i82545GM 1000BASE-T Ethernet",
 	  WM_T_82545_3,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_FIBER,
 	  "Intel i82545GM 1000BASE-X Ethernet",
 	  WM_T_82545_3,		WMP_F_FIBER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_SERDES,
 	  "Intel i82545GM Gigabit Ethernet (SERDES)",
 	  WM_T_82545_3,		WMP_F_SERDES },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_COPPER,
 	  "Intel i82546EB 1000BASE-T Ethernet",
 	  WM_T_82546,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_QUAD,
 	  "Intel i82546EB 1000BASE-T Ethernet",
 	  WM_T_82546,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545EM_FIBER,
 	  "Intel i82545EM 1000BASE-X Ethernet",
 	  WM_T_82545,		WMP_F_FIBER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_FIBER,
 	  "Intel i82546EB 1000BASE-X Ethernet",
 	  WM_T_82546,		WMP_F_FIBER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_COPPER,
 	  "Intel i82546GB 1000BASE-T Ethernet",
 	  WM_T_82546_3,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_FIBER,
 	  "Intel i82546GB 1000BASE-X Ethernet",
 	  WM_T_82546_3,		WMP_F_FIBER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_SERDES,
 	  "Intel i82546GB Gigabit Ethernet (SERDES)",
 	  WM_T_82546_3,		WMP_F_SERDES },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER,
 	  "i82546GB quad-port Gigabit Ethernet",
 	  WM_T_82546_3,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER_KSP3,
 	  "i82546GB quad-port Gigabit Ethernet (KSP3)",
 	  WM_T_82546_3,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_PCIE,
 	  "Intel PRO/1000MT (82546GB)",
 	  WM_T_82546_3,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541EI,
 	  "Intel i82541EI 1000BASE-T Ethernet",
 	  WM_T_82541,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541ER_LOM,
 	  "Intel i82541ER (LOM) 1000BASE-T Ethernet",
 	  WM_T_82541,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541EI_MOBILE,
 	  "Intel i82541EI Mobile 1000BASE-T Ethernet",
 	  WM_T_82541,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541ER,
 	  "Intel i82541ER 1000BASE-T Ethernet",
 	  WM_T_82541_2,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541GI,
 	  "Intel i82541GI 1000BASE-T Ethernet",
 	  WM_T_82541_2,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541GI_MOBILE,
 	  "Intel i82541GI Mobile 1000BASE-T Ethernet",
 	  WM_T_82541_2,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541PI,
 	  "Intel i82541PI 1000BASE-T Ethernet",
 	  WM_T_82541_2,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82547EI,
 	  "Intel i82547EI 1000BASE-T Ethernet",
 	  WM_T_82547,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82547EI_MOBILE,
 	  "Intel i82547EI Mobile 1000BASE-T Ethernet",
 	  WM_T_82547,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82547GI,
 	  "Intel i82547GI 1000BASE-T Ethernet",
 	  WM_T_82547_2,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_COPPER,
 	  "Intel PRO/1000 PT (82571EB)",
 	  WM_T_82571,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_FIBER,
 	  "Intel PRO/1000 PF (82571EB)",
 	  WM_T_82571,		WMP_F_FIBER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_SERDES,
 	  "Intel PRO/1000 PB (82571EB)",
 	  WM_T_82571,		WMP_F_SERDES },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_QUAD_COPPER,
 	  "Intel PRO/1000 QT (82571EB)",
 	  WM_T_82571,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571GB_QUAD_COPPER,
 	  "Intel PRO/1000 PT Quad Port Server Adapter",
 	  WM_T_82571,		WMP_F_COPPER, },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571PT_QUAD_COPPER,
 	  "Intel Gigabit PT Quad Port Server ExpressModule",
 	  WM_T_82571,		WMP_F_COPPER, },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_DUAL_SERDES,
 	  "Intel 82571EB Dual Gigabit Ethernet (SERDES)",
 	  WM_T_82571,		WMP_F_SERDES, },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_QUAD_SERDES,
 	  "Intel 82571EB Quad Gigabit Ethernet (SERDES)",
 	  WM_T_82571,		WMP_F_SERDES, },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_QUAD_FIBER,
 	  "Intel 82571EB Quad 1000baseX Ethernet",
 	  WM_T_82571,		WMP_F_FIBER, },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI_COPPER,
 	  "Intel i82572EI 1000baseT Ethernet",
 	  WM_T_82572,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI_FIBER,
 	  "Intel i82572EI 1000baseX Ethernet",
 	  WM_T_82572,		WMP_F_FIBER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI_SERDES,
 	  "Intel i82572EI Gigabit Ethernet (SERDES)",
 	  WM_T_82572,		WMP_F_SERDES },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI,
 	  "Intel i82572EI 1000baseT Ethernet",
 	  WM_T_82572,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82573E,
 	  "Intel i82573E",
 	  WM_T_82573,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82573E_IAMT,
 	  "Intel i82573E IAMT",
 	  WM_T_82573,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82573L,
 	  "Intel i82573L Gigabit Ethernet",
 	  WM_T_82573,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82574L,
 	  "Intel i82574L",
 	  WM_T_82574,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82574LA,
 	  "Intel i82574L",
 	  WM_T_82574,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82583V,
 	  "Intel i82583V",
 	  WM_T_82583,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_CPR_DPT,
 	  "i80003 dual 1000baseT Ethernet",
 	  WM_T_80003,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_FIB_DPT,
 	  "i80003 dual 1000baseX Ethernet",
 	  WM_T_80003,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_SDS_DPT,
 	  "Intel i80003ES2 dual Gigabit Ethernet (SERDES)",
 	  WM_T_80003,		WMP_F_SERDES },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_CPR_SPT,
 	  "Intel i80003 1000baseT Ethernet",
 	  WM_T_80003,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_SDS_SPT,
 	  "Intel i80003 Gigabit Ethernet (SERDES)",
 	  WM_T_80003,		WMP_F_SERDES },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_M_AMT,
 	  "Intel i82801H (M_AMT) LAN Controller",
 	  WM_T_ICH8,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_AMT,
 	  "Intel i82801H (AMT) LAN Controller",
 	  WM_T_ICH8,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_LAN,
 	  "Intel i82801H LAN Controller",
 	  WM_T_ICH8,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IFE_LAN,
 	  "Intel i82801H (IFE) LAN Controller",
 	  WM_T_ICH8,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_M_LAN,
 	  "Intel i82801H (M) LAN Controller",
 	  WM_T_ICH8,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IFE_GT,
 	  "Intel i82801H IFE (GT) LAN Controller",
 	  WM_T_ICH8,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IFE_G,
 	  "Intel i82801H IFE (G) LAN Controller",
 	  WM_T_ICH8,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_AMT,
 	  "82801I (AMT) LAN Controller",
 	  WM_T_ICH9,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IFE,
 	  "82801I LAN Controller",
 	  WM_T_ICH9,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IFE_G,
 	  "82801I (G) LAN Controller",
 	  WM_T_ICH9,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IFE_GT,
 	  "82801I (GT) LAN Controller",
 	  WM_T_ICH9,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_C,
 	  "82801I (C) LAN Controller",
 	  WM_T_ICH9,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_M,
 	  "82801I mobile LAN Controller",
 	  WM_T_ICH9,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IGP_M_V,
 	  "82801I mobile (V) LAN Controller",
 	  WM_T_ICH9,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_M_AMT,
 	  "82801I mobile (AMT) LAN Controller",
 	  WM_T_ICH9,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_BM,
 	  "82567LM-4 LAN Controller",
 	  WM_T_ICH9,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_82567V_3,
 	  "82567V-3 LAN Controller",
 	  WM_T_ICH9,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_R_BM_LM,
 	  "82567LM-2 LAN Controller",
 	  WM_T_ICH10,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_R_BM_LF,
 	  "82567LF-2 LAN Controller",
 	  WM_T_ICH10,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_D_BM_LM,
 	  "82567LM-3 LAN Controller",
 	  WM_T_ICH10,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_D_BM_LF,
 	  "82567LF-3 LAN Controller",
 	  WM_T_ICH10,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_R_BM_V,
 @@ -3050,2153 +3050,2154 @@ wm_mchash(struct wm_softc *sc, const uin
 		hash = (enaddr[4] >> ich8_lo_shift[sc->sc_mchash_type]) |
 		    (((uint16_t) enaddr[5]) << ich8_hi_shift[sc->sc_mchash_type]);
 		return (hash & 0x3ff);
+	}
 	hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) |
 	    (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]);
 	return (hash & 0xfff);
+}
 /*
  * wm_set_filter:
+ *
  *	Set up the receive filter.
  */
 static void
 wm_set_filter(struct wm_softc *sc)
+{
 	struct ethercom *ec = &sc->sc_ethercom;
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	struct ether_multi *enm;
 	struct ether_multistep step;
 	bus_addr_t mta_reg;
 	uint32_t hash, reg, bit;
 	int i, size;
 	if (sc->sc_type >= WM_T_82544)
 		mta_reg = WMREG_CORDOVA_MTA;
 	else
 		mta_reg = WMREG_MTA;
 	sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE);
 	if (ifp->if_flags & IFF_BROADCAST)
 		sc->sc_rctl |= RCTL_BAM;
 	if (ifp->if_flags & IFF_PROMISC) {
 		sc->sc_rctl |= RCTL_UPE;
 		goto allmulti;
+	}
 	/*
 	 * Set the station address in the first RAL slot, and
 	 * clear the remaining slots.
 	 */
 	if (sc->sc_type == WM_T_ICH8)
 		size = WM_RAL_TABSIZE_ICH8 -1;
 	else if ((sc->sc_type == WM_T_ICH9) || (sc->sc_type == WM_T_ICH10)
 	    || (sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2)
 	    || (sc->sc_type == WM_T_PCH_LPT))
 		size = WM_RAL_TABSIZE_ICH8;
 	else if (sc->sc_type == WM_T_82575)
 		size = WM_RAL_TABSIZE_82575;
 	else if ((sc->sc_type == WM_T_82576) || (sc->sc_type == WM_T_82580))
 		size = WM_RAL_TABSIZE_82576;
 	else if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354))
 		size = WM_RAL_TABSIZE_I350;
 	else
 		size = WM_RAL_TABSIZE;
 	wm_set_ral(sc, CLLADDR(ifp->if_sadl), 0);
 	for (i = 1; i < size; i++)
 		wm_set_ral(sc, NULL, i);
 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
 	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT))
 		size = WM_ICH8_MC_TABSIZE;
 	else
 		size = WM_MC_TABSIZE;
 	/* Clear out the multicast table. */
 	for (i = 0; i < size; i++)
 		CSR_WRITE(sc, mta_reg + (i << 2), 0);
 	ETHER_FIRST_MULTI(step, ec, enm);
 	while (enm != NULL) {
 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
 			/*
 			 * We must listen to a range of multicast addresses.
 			 * For now, just accept all multicasts, rather than
 			 * trying to set only those filter bits needed to match
 			 * the range.  (At this time, the only use of address
 			 * ranges is for IP multicast routing, for which the
 			 * range is big enough to require all bits set.)
 			 */
 			goto allmulti;
+		}
 		hash = wm_mchash(sc, enm->enm_addrlo);
 		reg = (hash >> 5);
 		if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
 		    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
 		    || (sc->sc_type == WM_T_PCH2)
 		    || (sc->sc_type == WM_T_PCH_LPT))
 			reg &= 0x1f;
 		else
 			reg &= 0x7f;
 		bit = hash & 0x1f;
 		hash = CSR_READ(sc, mta_reg + (reg << 2));
 		hash |= 1U << bit;
 		/* XXX Hardware bug?? */
 		if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) {
 			bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2));
 			CSR_WRITE(sc, mta_reg + (reg << 2), hash);
 			CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit);
 		} else
 			CSR_WRITE(sc, mta_reg + (reg << 2), hash);
 		ETHER_NEXT_MULTI(step, enm);
+	}
 	ifp->if_flags &= ~IFF_ALLMULTI;
 	goto setit;
  allmulti:
 	ifp->if_flags |= IFF_ALLMULTI;
 	sc->sc_rctl |= RCTL_MPE;
  setit:
 	CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl);
+}
 /* Reset and init related */
 static void
 wm_set_vlan(struct wm_softc *sc)
+{
 	/* Deal with VLAN enables. */
 	if (VLAN_ATTACHED(&sc->sc_ethercom))
 		sc->sc_ctrl |= CTRL_VME;
 	else
 		sc->sc_ctrl &= ~CTRL_VME;
 	/* Write the control registers. */
 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
+}
 static void
 wm_set_pcie_completion_timeout(struct wm_softc *sc)
+{
 	uint32_t gcr;
 	pcireg_t ctrl2;
 	gcr = CSR_READ(sc, WMREG_GCR);
 	/* Only take action if timeout value is defaulted to 0 */
 	if ((gcr & GCR_CMPL_TMOUT_MASK) != 0)
 		goto out;
 	if ((gcr & GCR_CAP_VER2) == 0) {
 		gcr |= GCR_CMPL_TMOUT_10MS;
 		goto out;
+	}
 	ctrl2 = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
 	    sc->sc_pcixe_capoff + PCIE_DCSR2);
 	ctrl2 |= WM_PCIE_DCSR2_16MS;
 	pci_conf_write(sc->sc_pc, sc->sc_pcitag,
 	    sc->sc_pcixe_capoff + PCIE_DCSR2, ctrl2);
 out:
 	/* Disable completion timeout resend */
 	gcr &= ~GCR_CMPL_TMOUT_RESEND;
 	CSR_WRITE(sc, WMREG_GCR, gcr);
+}
 void
 wm_get_auto_rd_done(struct wm_softc *sc)
+{
 	int i;
 	/* wait for eeprom to reload */
 	switch (sc->sc_type) {
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82583:
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_82580:
 	case WM_T_I350:
 	case WM_T_I354:
 	case WM_T_I210:
 	case WM_T_I211:
 	case WM_T_80003:
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 		for (i = 0; i < 10; i++) {
 			if (CSR_READ(sc, WMREG_EECD) & EECD_EE_AUTORD)
 				break;
 			delay(1000);
+		}
 		if (i == 10) {
 			log(LOG_ERR, "%s: auto read from eeprom failed to "
 			    "complete\n", device_xname(sc->sc_dev));
+		}
 		break;
 	default:
 		break;
+	}
+}
 void
 wm_lan_init_done(struct wm_softc *sc)
+{
 	uint32_t reg = 0;
 	int i;
 	/* wait for eeprom to reload */
 	switch (sc->sc_type) {
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		for (i = 0; i < WM_ICH8_LAN_INIT_TIMEOUT; i++) {
 			reg = CSR_READ(sc, WMREG_STATUS);
 			if ((reg & STATUS_LAN_INIT_DONE) != 0)
 				break;
 			delay(100);
+		}
 		if (i >= WM_ICH8_LAN_INIT_TIMEOUT) {
 			log(LOG_ERR, "%s: %s: lan_init_done failed to "
 			    "complete\n", device_xname(sc->sc_dev), __func__);
+		}
 		break;
 	default:
 		panic("%s: %s: unknown type\n", device_xname(sc->sc_dev),
 		    __func__);
 		break;
+	}
 	reg &= ~STATUS_LAN_INIT_DONE;
 	CSR_WRITE(sc, WMREG_STATUS, reg);
+}
 void
 wm_get_cfg_done(struct wm_softc *sc)
+{
 	int mask;
 	uint32_t reg;
 	int i;
 	/* wait for eeprom to reload */
 	switch (sc->sc_type) {
 	case WM_T_82542_2_0:
 	case WM_T_82542_2_1:
 		/* null */
 		break;
 	case WM_T_82543:
 	case WM_T_82544:
 	case WM_T_82540:
 	case WM_T_82545:
 	case WM_T_82545_3:
 	case WM_T_82546:
 	case WM_T_82546_3:
 	case WM_T_82541:
 	case WM_T_82541_2:
 	case WM_T_82547:
 	case WM_T_82547_2:
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82583:
 		/* generic */
 		delay(10*1000);
 		break;
 	case WM_T_80003:
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_82580:
 	case WM_T_I350:
 	case WM_T_I354:
 	case WM_T_I210:
 	case WM_T_I211:
 		if (sc->sc_type == WM_T_82571) {
 			/* Only 82571 shares port 0 */
 			mask = EEMNGCTL_CFGDONE_0;
 		} else
 			mask = EEMNGCTL_CFGDONE_0 << sc->sc_funcid;
 		for (i = 0; i < WM_PHY_CFG_TIMEOUT; i++) {
 			if (CSR_READ(sc, WMREG_EEMNGCTL) & mask)
 				break;
 			delay(1000);
+		}
 		if (i >= WM_PHY_CFG_TIMEOUT) {
 			DPRINTF(WM_DEBUG_GMII, ("%s: %s failed\n",
 				device_xname(sc->sc_dev), __func__));
+		}
 		break;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		delay(10*1000);
 		if (sc->sc_type >= WM_T_ICH10)
 			wm_lan_init_done(sc);
 		else
 			wm_get_auto_rd_done(sc);
 		reg = CSR_READ(sc, WMREG_STATUS);
 		if ((reg & STATUS_PHYRA) != 0)
 			CSR_WRITE(sc, WMREG_STATUS, reg & ~STATUS_PHYRA);
 		break;
 	default:
 		panic("%s: %s: unknown type\n", device_xname(sc->sc_dev),
 		    __func__);
 		break;
+	}
+}
 /* Init hardware bits */
 void
 wm_initialize_hardware_bits(struct wm_softc *sc)
+{
 	uint32_t tarc0, tarc1, reg;
 	/* For 82571 variant, 80003 and ICHs */
 	if (((sc->sc_type >= WM_T_82571) && (sc->sc_type <= WM_T_82583))
 	    || (sc->sc_type >= WM_T_80003)) {
 		/* Transmit Descriptor Control 0 */
 		reg = CSR_READ(sc, WMREG_TXDCTL(0));
 		reg |= TXDCTL_COUNT_DESC;
 		CSR_WRITE(sc, WMREG_TXDCTL(0), reg);
 		/* Transmit Descriptor Control 1 */
 		reg = CSR_READ(sc, WMREG_TXDCTL(1));
 		reg |= TXDCTL_COUNT_DESC;
 		CSR_WRITE(sc, WMREG_TXDCTL(1), reg);
 		/* TARC0 */
 		tarc0 = CSR_READ(sc, WMREG_TARC0);
 		switch (sc->sc_type) {
 		case WM_T_82571:
 		case WM_T_82572:
 		case WM_T_82573:
 		case WM_T_82574:
 		case WM_T_82583:
 		case WM_T_80003:
 			/* Clear bits 30..27 */
 			tarc0 &= ~__BITS(30, 27);
 			break;
 		default:
 			break;
+		}
 		switch (sc->sc_type) {
 		case WM_T_82571:
 		case WM_T_82572:
 			tarc0 |= __BITS(26, 23); /* TARC0 bits 23-26 */
 			tarc1 = CSR_READ(sc, WMREG_TARC1);
 			tarc1 &= ~__BITS(30, 29); /* Clear bits 30 and 29 */
 			tarc1 |= __BITS(26, 24); /* TARC1 bits 26-24 */
 			/* 8257[12] Errata No.7 */
 			tarc1 |= __BIT(22); /* TARC1 bits 22 */
 			/* TARC1 bit 28 */
 			if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0)
 				tarc1 &= ~__BIT(28);
 			else
 				tarc1 |= __BIT(28);
 			CSR_WRITE(sc, WMREG_TARC1, tarc1);
 			/*
 			 * 8257[12] Errata No.13
 			 * Disable Dyamic Clock Gating.
 			 */
 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
 			reg &= ~CTRL_EXT_DMA_DYN_CLK;
 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
 			break;
 		case WM_T_82573:
 		case WM_T_82574:
 		case WM_T_82583:
 			if ((sc->sc_type == WM_T_82574)
 			    || (sc->sc_type == WM_T_82583))
 				tarc0 |= __BIT(26); /* TARC0 bit 26 */
 			/* Extended Device Control */
 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
 			reg &= ~__BIT(23);	/* Clear bit 23 */
 			reg |= __BIT(22);	/* Set bit 22 */
 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
 			/* Device Control */
 			sc->sc_ctrl &= ~__BIT(29);	/* Clear bit 29 */
 			CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 			/* PCIe Control Register */
 			/*
 			 * 82573 Errata (unknown).
+			 *
 			 * 82574 Errata 25 and 82583 Errata 12
 			 * "Dropped Rx Packets":
 			 *   NVM Image Version 2.1.4 and newer has no this bug.
 			 */
 			reg = CSR_READ(sc, WMREG_GCR);
 			reg |= GCR_L1_ACT_WITHOUT_L0S_RX;
 			CSR_WRITE(sc, WMREG_GCR, reg);
 			if ((sc->sc_type == WM_T_82574)
 			    || (sc->sc_type == WM_T_82583)) {
 				/*
 				 * Document says this bit must be set for
 				 * proper operation.
 				 */
 				reg = CSR_READ(sc, WMREG_GCR);
 				reg |= __BIT(22);
 				CSR_WRITE(sc, WMREG_GCR, reg);
 				/*
 				 * Apply workaround for hardware errata
 				 * documented in errata docs Fixes issue where
 				 * some error prone or unreliable PCIe
 				 * completions are occurring, particularly
 				 * with ASPM enabled. Without fix, issue can
 				 * cause Tx timeouts.
 				 */
 				reg = CSR_READ(sc, WMREG_GCR2);
 				reg |= __BIT(0);
 				CSR_WRITE(sc, WMREG_GCR2, reg);
+			}
 			break;
 		case WM_T_80003:
 			/* TARC0 */
 			if ((sc->sc_mediatype == WM_MEDIATYPE_FIBER)
 			    || (sc->sc_mediatype == WM_MEDIATYPE_SERDES))
 				tarc0 &= ~__BIT(20); /* Clear bits 20 */
 			/* TARC1 bit 28 */
 			tarc1 = CSR_READ(sc, WMREG_TARC1);
 			if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0)
 				tarc1 &= ~__BIT(28);
 			else
 				tarc1 |= __BIT(28);
 			CSR_WRITE(sc, WMREG_TARC1, tarc1);
 			break;
 		case WM_T_ICH8:
 		case WM_T_ICH9:
 		case WM_T_ICH10:
 		case WM_T_PCH:
 		case WM_T_PCH2:
 		case WM_T_PCH_LPT:
 			/* TARC 0 */
 			if (sc->sc_type == WM_T_ICH8) {
 				/* Set TARC0 bits 29 and 28 */
 				tarc0 |= __BITS(29, 28);
+			}
 			/* Set TARC0 bits 23,24,26,27 */
 			tarc0 |= __BITS(27, 26) | __BITS(24, 23);
 			/* CTRL_EXT */
 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
 			reg |= __BIT(22);	/* Set bit 22 */
 			/*
 			 * Enable PHY low-power state when MAC is at D3
 			 * w/o WoL
 			 */
 			if (sc->sc_type >= WM_T_PCH)
 				reg |= CTRL_EXT_PHYPDEN;
 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
 			/* TARC1 */
 			tarc1 = CSR_READ(sc, WMREG_TARC1);
 			/* bit 28 */
 			if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0)
 				tarc1 &= ~__BIT(28);
 			else
 				tarc1 |= __BIT(28);
 			tarc1 |= __BIT(24) | __BIT(26) | __BIT(30);
 			CSR_WRITE(sc, WMREG_TARC1, tarc1);
 			/* Device Status */
 			if (sc->sc_type == WM_T_ICH8) {
 				reg = CSR_READ(sc, WMREG_STATUS);
 				reg &= ~__BIT(31);
 				CSR_WRITE(sc, WMREG_STATUS, reg);
+			}
 			/*
 			 * Work-around descriptor data corruption issue during
 			 * NFS v2 UDP traffic, just disable the NFS filtering
 			 * capability.
 			 */
 			reg = CSR_READ(sc, WMREG_RFCTL);
 			reg |= WMREG_RFCTL_NFSWDIS | WMREG_RFCTL_NFSRDIS;
 			CSR_WRITE(sc, WMREG_RFCTL, reg);
 			break;
 		default:
 			break;
+		}
 		CSR_WRITE(sc, WMREG_TARC0, tarc0);
 		/*
 		 * 8257[12] Errata No.52 and some others.
 		 * Avoid RSS Hash Value bug.
 		 */
 		switch (sc->sc_type) {
 		case WM_T_82571:
 		case WM_T_82572:
 		case WM_T_82573:
 		case WM_T_80003:
 		case WM_T_ICH8:
 			reg = CSR_READ(sc, WMREG_RFCTL);
 			reg |= WMREG_RFCTL_NEWIPV6EXDIS |WMREG_RFCTL_IPV6EXDIS;
 			CSR_WRITE(sc, WMREG_RFCTL, reg);
 			break;
 		default:
 			break;
+		}
+	}
+}
 static uint32_t
 wm_rxpbs_adjust_82580(uint32_t val)
+{
 	uint32_t rv = 0;
 	if (val < __arraycount(wm_82580_rxpbs_table))
 		rv = wm_82580_rxpbs_table[val];
 	return rv;
+}
 /*
  * wm_reset:
+ *
  *	Reset the i82542 chip.
  */
 static void
 wm_reset(struct wm_softc *sc)
+{
 	int phy_reset = 0;
 	int i, error = 0;
 	uint32_t reg, mask;
 	/*
 	 * Allocate on-chip memory according to the MTU size.
 	 * The Packet Buffer Allocation register must be written
 	 * before the chip is reset.
 	 */
 	switch (sc->sc_type) {
 	case WM_T_82547:
 	case WM_T_82547_2:
 		sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ?
 		    PBA_22K : PBA_30K;
 		for (i = 0; i < sc->sc_ntxqueues; i++) {
 			struct wm_txqueue *txq = &sc->sc_txq[i];
 			txq->txq_fifo_head = 0;
 			txq->txq_fifo_addr = sc->sc_pba << PBA_ADDR_SHIFT;
 			txq->txq_fifo_size =
 				(PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT;
 			txq->txq_fifo_stall = 0;
+		}
 		break;
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82575:	/* XXX need special handing for jumbo frames */
 	case WM_T_80003:
 		sc->sc_pba = PBA_32K;
 		break;
 	case WM_T_82573:
 		sc->sc_pba = PBA_12K;
 		break;
 	case WM_T_82574:
 	case WM_T_82583:
 		sc->sc_pba = PBA_20K;
 		break;
 	case WM_T_82576:
 		sc->sc_pba = CSR_READ(sc, WMREG_RXPBS);
 		sc->sc_pba &= RXPBS_SIZE_MASK_82576;
 		break;
 	case WM_T_82580:
 	case WM_T_I350:
 	case WM_T_I354:
 		sc->sc_pba = wm_rxpbs_adjust_82580(CSR_READ(sc, WMREG_RXPBS));
 		break;
 	case WM_T_I210:
 	case WM_T_I211:
 		sc->sc_pba = PBA_34K;
 		break;
 	case WM_T_ICH8:
 		/* Workaround for a bit corruption issue in FIFO memory */
 		sc->sc_pba = PBA_8K;
 		CSR_WRITE(sc, WMREG_PBS, PBA_16K);
 		break;
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 		sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 4096 ?
 		    PBA_14K : PBA_10K;
 		break;
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		sc->sc_pba = PBA_26K;
 		break;
 	default:
 		sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ?
 		    PBA_40K : PBA_48K;
 		break;
+	}
 	/*
 	 * Only old or non-multiqueue devices have the PBA register
 	 * XXX Need special handling for 82575.
 	 */
 	if (((sc->sc_flags & WM_F_NEWQUEUE) == 0)
 	    || (sc->sc_type == WM_T_82575))
 		CSR_WRITE(sc, WMREG_PBA, sc->sc_pba);
 	/* Prevent the PCI-E bus from sticking */
 	if (sc->sc_flags & WM_F_PCIE) {
 		int timeout = 800;
 		sc->sc_ctrl |= CTRL_GIO_M_DIS;
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 		while (timeout--) {
 			if ((CSR_READ(sc, WMREG_STATUS) & STATUS_GIO_M_ENA)
 			    == 0)
 				break;
 			delay(100);
+		}
+	}
 	/* Set the completion timeout for interface */
 	if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
 	    || (sc->sc_type == WM_T_82580)
 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)
 	    || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211))
 		wm_set_pcie_completion_timeout(sc);
 	/* Clear interrupt */
 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
 	if (sc->sc_nintrs > 1) {
 		if (sc->sc_type != WM_T_82574) {
 			CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU);
 			CSR_WRITE(sc, WMREG_EIAC, 0);
 		} else {
 			CSR_WRITE(sc, WMREG_EIAC_82574, 0);
+		}
+	}
 	/* Stop the transmit and receive processes. */
 	CSR_WRITE(sc, WMREG_RCTL, 0);
 	sc->sc_rctl &= ~RCTL_EN;
 	CSR_WRITE(sc, WMREG_TCTL, TCTL_PSP);
 	CSR_WRITE_FLUSH(sc);
 	/* XXX set_tbi_sbp_82543() */
 	delay(10*1000);
 	/* Must acquire the MDIO ownership before MAC reset */
 	switch (sc->sc_type) {
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82583:
 		error = wm_get_hw_semaphore_82573(sc);
 		break;
 	default:
 		break;
+	}
 	/*
 	 * 82541 Errata 29? & 82547 Errata 28?
 	 * See also the description about PHY_RST bit in CTRL register
 	 * in 8254x_GBe_SDM.pdf.
 	 */
 	if ((sc->sc_type == WM_T_82541) || (sc->sc_type == WM_T_82547)) {
 		CSR_WRITE(sc, WMREG_CTRL,
 		    CSR_READ(sc, WMREG_CTRL) | CTRL_PHY_RESET);
 		CSR_WRITE_FLUSH(sc);
 		delay(5000);
+	}
 	switch (sc->sc_type) {
 	case WM_T_82544: /* XXX check whether WM_F_IOH_VALID is set */
 	case WM_T_82541:
 	case WM_T_82541_2:
 	case WM_T_82547:
 	case WM_T_82547_2:
 		/*
 		 * On some chipsets, a reset through a memory-mapped write
 		 * cycle can cause the chip to reset before completing the
 		 * write cycle.  This causes major headache that can be
 		 * avoided by issuing the reset via indirect register writes
 		 * through I/O space.
+		 *
 		 * So, if we successfully mapped the I/O BAR at attach time,
 		 * use that.  Otherwise, try our luck with a memory-mapped
 		 * reset.
 		 */
 		if (sc->sc_flags & WM_F_IOH_VALID)
 			wm_io_write(sc, WMREG_CTRL, CTRL_RST);
 		else
 			CSR_WRITE(sc, WMREG_CTRL, CTRL_RST);
 		break;
 	case WM_T_82545_3:
 	case WM_T_82546_3:
 		/* Use the shadow control register on these chips. */
 		CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST);
 		break;
 	case WM_T_80003:
 		mask = swfwphysem[sc->sc_funcid];
 		reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST;
 		wm_get_swfw_semaphore(sc, mask);
 		CSR_WRITE(sc, WMREG_CTRL, reg);
 		wm_put_swfw_semaphore(sc, mask);
 		break;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST;
 		if (wm_check_reset_block(sc) == 0) {
 			/*
 			 * Gate automatic PHY configuration by hardware on
 			 * non-managed 82579
 			 */
 			if ((sc->sc_type == WM_T_PCH2)
 			    && ((CSR_READ(sc, WMREG_FWSM) & FWSM_FW_VALID)
 				!= 0))
 				wm_gate_hw_phy_config_ich8lan(sc, 1);
 			reg |= CTRL_PHY_RESET;
 			phy_reset = 1;
+		}
 		wm_get_swfwhw_semaphore(sc);
 		CSR_WRITE(sc, WMREG_CTRL, reg);
 		/* Don't insert a completion barrier when reset */
 		delay(20*1000);
 		wm_put_swfwhw_semaphore(sc);
 		break;
 	case WM_T_82580:
 	case WM_T_I350:
 	case WM_T_I354:
 	case WM_T_I210:
 	case WM_T_I211:
 		CSR_WRITE(sc, WMREG_CTRL, CSR_READ(sc, WMREG_CTRL) | CTRL_RST);
 		if (sc->sc_pcidevid != PCI_PRODUCT_INTEL_DH89XXCC_SGMII)
 			CSR_WRITE_FLUSH(sc);
 		delay(5000);
 		break;
 	case WM_T_82542_2_0:
 	case WM_T_82542_2_1:
 	case WM_T_82543:
 	case WM_T_82540:
 	case WM_T_82545:
 	case WM_T_82546:
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_82583:
 	default:
 		/* Everything else can safely use the documented method. */
 		CSR_WRITE(sc, WMREG_CTRL, CSR_READ(sc, WMREG_CTRL) | CTRL_RST);
 		break;
+	}
 	/* Must release the MDIO ownership after MAC reset */
 	switch (sc->sc_type) {
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82583:
 		if (error == 0)
 			wm_put_hw_semaphore_82573(sc);
 		break;
 	default:
 		break;
+	}
 	if (phy_reset != 0)
 		wm_get_cfg_done(sc);
 	/* reload EEPROM */
 	switch (sc->sc_type) {
 	case WM_T_82542_2_0:
 	case WM_T_82542_2_1:
 	case WM_T_82543:
 	case WM_T_82544:
 		delay(10);
 		reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST;
 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
 		CSR_WRITE_FLUSH(sc);
 		delay(2000);
 		break;
 	case WM_T_82540:
 	case WM_T_82545:
 	case WM_T_82545_3:
 	case WM_T_82546:
 	case WM_T_82546_3:
 		delay(5*1000);
 		/* XXX Disable HW ARPs on ASF enabled adapters */
 		break;
 	case WM_T_82541:
 	case WM_T_82541_2:
 	case WM_T_82547:
 	case WM_T_82547_2:
 		delay(20000);
 		/* XXX Disable HW ARPs on ASF enabled adapters */
 		break;
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82583:
 		if (sc->sc_flags & WM_F_EEPROM_FLASH) {
 			delay(10);
 			reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST;
 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
 			CSR_WRITE_FLUSH(sc);
+		}
 		/* check EECD_EE_AUTORD */
 		wm_get_auto_rd_done(sc);
 		/*
 		 * Phy configuration from NVM just starts after EECD_AUTO_RD
 		 * is set.
 		 */
 		if ((sc->sc_type == WM_T_82573) || (sc->sc_type == WM_T_82574)
 		    || (sc->sc_type == WM_T_82583))
 			delay(25*1000);
 		break;
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_82580:
 	case WM_T_I350:
 	case WM_T_I354:
 	case WM_T_I210:
 	case WM_T_I211:
 	case WM_T_80003:
 		/* check EECD_EE_AUTORD */
 		wm_get_auto_rd_done(sc);
 		break;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		break;
 	default:
 		panic("%s: unknown type\n", __func__);
+	}
 	/* Check whether EEPROM is present or not */
 	switch (sc->sc_type) {
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_82580:
 	case WM_T_I350:
 	case WM_T_I354:
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 		if ((CSR_READ(sc, WMREG_EECD) & EECD_EE_PRES) == 0) {
 			/* Not found */
 			sc->sc_flags |= WM_F_EEPROM_INVALID;
 			if (sc->sc_type == WM_T_82575)
 				wm_reset_init_script_82575(sc);
+		}
 		break;
 	default:
 		break;
+	}
 	if ((sc->sc_type == WM_T_82580)
 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)) {
 		/* clear global device reset status bit */
 		CSR_WRITE(sc, WMREG_STATUS, STATUS_DEV_RST_SET);
+	}
 	/* Clear any pending interrupt events. */
 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
 	reg = CSR_READ(sc, WMREG_ICR);
 	if (sc->sc_nintrs > 1) {
 		if (sc->sc_type != WM_T_82574) {
 			CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU);
 			CSR_WRITE(sc, WMREG_EIAC, 0);
 		} else
 			CSR_WRITE(sc, WMREG_EIAC_82574, 0);
+	}
 	/* reload sc_ctrl */
 	sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
 	if ((sc->sc_type >= WM_T_I350) && (sc->sc_type <= WM_T_I211))
 		wm_set_eee_i350(sc);
 	/* dummy read from WUC */
 	if (sc->sc_type == WM_T_PCH)
 		reg = wm_gmii_hv_readreg(sc->sc_dev, 1, BM_WUC);
 	/*
 	 * For PCH, this write will make sure that any noise will be detected
 	 * as a CRC error and be dropped rather than show up as a bad packet
 	 * to the DMA engine
 	 */
 	if (sc->sc_type == WM_T_PCH)
 		CSR_WRITE(sc, WMREG_CRC_OFFSET, 0x65656565);
 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
 		CSR_WRITE(sc, WMREG_WUC, 0);
 	wm_reset_mdicnfg_82580(sc);
 	if ((sc->sc_flags & WM_F_PLL_WA_I210) != 0)
 		wm_pll_workaround_i210(sc);
+}
 /*
  * wm_add_rxbuf:
+ *
  *	Add a receive buffer to the indiciated descriptor.
  */
 static int
 wm_add_rxbuf(struct wm_rxqueue *rxq, int idx)
+{
 	struct wm_softc *sc = rxq->rxq_sc;
 	struct wm_rxsoft *rxs = &rxq->rxq_soft[idx];
 	struct mbuf *m;
 	int error;
 	KASSERT(WM_RX_LOCKED(rxq));
 	MGETHDR(m, M_DONTWAIT, MT_DATA);
 	if (m == NULL)
 		return ENOBUFS;
 	MCLGET(m, M_DONTWAIT);
 	if ((m->m_flags & M_EXT) == 0) {
 		m_freem(m);
 		return ENOBUFS;
+	}
 	if (rxs->rxs_mbuf != NULL)
 		bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
 	rxs->rxs_mbuf = m;
 	m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
 	error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m,
 	    BUS_DMA_READ|BUS_DMA_NOWAIT);
 	if (error) {
 		/* XXX XXX XXX */
 		aprint_error_dev(sc->sc_dev,
 		    "unable to load rx DMA map %d, error = %d\n",
 		    idx, error);
 		panic("wm_add_rxbuf");
+	}
 	bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
 	    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
 		if ((sc->sc_rctl & RCTL_EN) != 0)
 			wm_init_rxdesc(rxq, idx);
 	} else
 		wm_init_rxdesc(rxq, idx);
 	return 0;
+}
 /*
  * wm_rxdrain:
+ *
  *	Drain the receive queue.
  */
 static void
 wm_rxdrain(struct wm_rxqueue *rxq)
+{
 	struct wm_softc *sc = rxq->rxq_sc;
 	struct wm_rxsoft *rxs;
 	int i;
 	KASSERT(WM_RX_LOCKED(rxq));
 	for (i = 0; i < WM_NRXDESC; i++) {
 		rxs = &rxq->rxq_soft[i];
 		if (rxs->rxs_mbuf != NULL) {
 			bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
 			m_freem(rxs->rxs_mbuf);
 			rxs->rxs_mbuf = NULL;
+		}
+	}
+}
 /*
  * Setup registers for RSS.
+ *
  * XXX not yet VMDq support
  */
 static void
 wm_init_rss(struct wm_softc *sc)
+{
 	uint32_t mrqc, reta_reg;
 	int i;
 	for (i = 0; i < RETA_NUM_ENTRIES; i++) {
 		int qid, reta_ent;
 		qid  = i % sc->sc_nrxqueues;
 		switch(sc->sc_type) {
 		case WM_T_82574:
 			reta_ent = __SHIFTIN(qid,
 			    RETA_ENT_QINDEX_MASK_82574);
 			break;
 		case WM_T_82575:
 			reta_ent = __SHIFTIN(qid,
 			    RETA_ENT_QINDEX1_MASK_82575);
 			break;
 		default:
 			reta_ent = __SHIFTIN(qid, RETA_ENT_QINDEX_MASK);
 			break;
+		}
 		reta_reg = CSR_READ(sc, WMREG_RETA_Q(i));
 		reta_reg &= ~RETA_ENTRY_MASK_Q(i);
 		reta_reg |= __SHIFTIN(reta_ent, RETA_ENTRY_MASK_Q(i));
 		CSR_WRITE(sc, WMREG_RETA_Q(i), reta_reg);
+	}
 	for (i = 0; i < RSSRK_NUM_REGS; i++)
 		CSR_WRITE(sc, WMREG_RSSRK(i), (uint32_t)random());
 	if (sc->sc_type == WM_T_82574)
 		mrqc = MRQC_ENABLE_RSS_MQ_82574;
 	else
 		mrqc = MRQC_ENABLE_RSS_MQ;
 	/* XXXX
 	 * The same as FreeBSD igb.
 	 * Why doesn't use MRQC_RSS_FIELD_IPV6_EX?
 	 */
 	mrqc |= (MRQC_RSS_FIELD_IPV4 | MRQC_RSS_FIELD_IPV4_TCP);
 	mrqc |= (MRQC_RSS_FIELD_IPV6 | MRQC_RSS_FIELD_IPV6_TCP);
 	mrqc |= (MRQC_RSS_FIELD_IPV4_UDP | MRQC_RSS_FIELD_IPV6_UDP);
 	mrqc |= (MRQC_RSS_FIELD_IPV6_UDP_EX | MRQC_RSS_FIELD_IPV6_TCP_EX);
 	CSR_WRITE(sc, WMREG_MRQC, mrqc);
+}
 #ifdef WM_MSI_MSIX
 /*
  * Adjust TX and RX queue numbers which the system actulally uses.
+ *
  * The numbers are affected by below parameters.
  *     - The nubmer of hardware queues
  *     - The number of MSI-X vectors (= "nvectors" argument)
  *     - ncpu
  */
 static void
 wm_adjust_qnum(struct wm_softc *sc, int nvectors)
+{
 	int hw_ntxqueues, hw_nrxqueues;
 	if (nvectors < 3) {
 		sc->sc_ntxqueues = 1;
 		sc->sc_nrxqueues = 1;
 		return;
+	}
 	switch(sc->sc_type) {
 	case WM_T_82572:
 		hw_ntxqueues = 2;
 		hw_nrxqueues = 2;
 		break;
 	case WM_T_82574:
 		hw_ntxqueues = 2;
 		hw_nrxqueues = 2;
 		break;
 	case WM_T_82575:
 		hw_ntxqueues = 4;
 		hw_nrxqueues = 4;
 		break;
 	case WM_T_82576:
 		hw_ntxqueues = 16;
 		hw_nrxqueues = 16;
 		break;
 	case WM_T_82580:
 	case WM_T_I350:
 	case WM_T_I354:
 		hw_ntxqueues = 8;
 		hw_nrxqueues = 8;
 		break;
 	case WM_T_I210:
 		hw_ntxqueues = 4;
 		hw_nrxqueues = 4;
 		break;
 	case WM_T_I211:
 		hw_ntxqueues = 2;
 		hw_nrxqueues = 2;
 		break;
 		/*
 		 * As below ethernet controllers does not support MSI-X,
 		 * this driver let them not use multiqueue.
 		 *     - WM_T_80003
 		 *     - WM_T_ICH8
 		 *     - WM_T_ICH9
 		 *     - WM_T_ICH10
 		 *     - WM_T_PCH
 		 *     - WM_T_PCH2
 		 *     - WM_T_PCH_LPT
 		 */
 	default:
 		hw_ntxqueues = 1;
 		hw_nrxqueues = 1;
 		break;
+	}
 	/*
 	 * As queues more then MSI-X vectors cannot improve scaling, we limit
 	 * the number of queues used actually.
+	 *
 	 * XXX
 	 * Currently, we separate TX queue interrupts and RX queue interrupts.
 	 * Howerver, the number of MSI-X vectors of recent controllers (such as
 	 * I354) expects that drivers bundle a TX queue interrupt and a RX
 	 * interrupt to one interrupt. e.g. FreeBSD's igb deals interrupts in
 	 * such a way.
 	 */
 	if (nvectors < hw_ntxqueues + hw_nrxqueues + 1) {
 		sc->sc_ntxqueues = (nvectors - 1) / 2;
 		sc->sc_nrxqueues = (nvectors - 1) / 2;
 	} else {
 		sc->sc_ntxqueues = hw_ntxqueues;
 		sc->sc_nrxqueues = hw_nrxqueues;
+	}
 	/*
 	 * As queues more then cpus cannot improve scaling, we limit
 	 * the number of queues used actually.
 	 */
 	if (ncpu < sc->sc_ntxqueues)
 		sc->sc_ntxqueues = ncpu;
 	if (ncpu < sc->sc_nrxqueues)
 		sc->sc_nrxqueues = ncpu;
 	/* XXX Currently, this driver supports RX multiqueue only. */
 	sc->sc_ntxqueues = 1;
+}
 /*
  * Setup registers for RSS.
  * XXX not yet VMDq support
  */
 static void
 wm_init_rss(struct wm_softc *sc)
 	uint32_t mrqc, reta_reg;
 	int i;
 	for (i = 0; i < RETA_NUM_ENTRIES; i++) {
 		int qid, reta_ent;
 		qid  = i % sc->sc_nrxqueues;
 		switch(sc->sc_type) {
 		case WM_T_82574:
 			reta_ent = __SHIFTIN(qid,
 			    RETA_ENT_QINDEX_MASK_82574);
 			break;
 		case WM_T_82575:
 			reta_ent = __SHIFTIN(qid,
 			    RETA_ENT_QINDEX1_MASK_82575);
 			break;
 		default:
 			reta_ent = __SHIFTIN(qid, RETA_ENT_QINDEX_MASK);
 			break;
 		reta_reg = CSR_READ(sc, WMREG_RETA_Q(i));
 		reta_reg &= ~RETA_ENTRY_MASK_Q(i);
 		reta_reg |= __SHIFTIN(reta_ent, RETA_ENTRY_MASK_Q(i));
 		CSR_WRITE(sc, WMREG_RETA_Q(i), reta_reg);
 	for (i = 0; i < RSSRK_NUM_REGS; i++)
 		CSR_WRITE(sc, WMREG_RSSRK(i), (uint32_t)random());
 	if (sc->sc_type == WM_T_82574)
 		mrqc = MRQC_ENABLE_RSS_MQ_82574;
 	else
 		mrqc = MRQC_ENABLE_RSS_MQ;
 	/* XXXX
 	 * The same as FreeBSD igb.
 	 * Why doesn't use MRQC_RSS_FIELD_IPV6_EX?
 	 */
 	mrqc |= (MRQC_RSS_FIELD_IPV4 | MRQC_RSS_FIELD_IPV4_TCP);
 	mrqc |= (MRQC_RSS_FIELD_IPV6 | MRQC_RSS_FIELD_IPV6_TCP);
 	mrqc |= (MRQC_RSS_FIELD_IPV4_UDP | MRQC_RSS_FIELD_IPV6_UDP);
 	mrqc |= (MRQC_RSS_FIELD_IPV6_UDP_EX | MRQC_RSS_FIELD_IPV6_TCP_EX);
 	CSR_WRITE(sc, WMREG_MRQC, mrqc);
 #ifdef WM_MSI_MSIX
 /*
  * Both single interrupt MSI and INTx can use this function.
  */
 static int
 wm_setup_legacy(struct wm_softc *sc)
+{
 	pci_chipset_tag_t pc = sc->sc_pc;
 	const char *intrstr = NULL;
 	char intrbuf[PCI_INTRSTR_LEN];
 	intrstr = pci_intr_string(pc, sc->sc_intrs[0], intrbuf,
 	    sizeof(intrbuf));
 #ifdef WM_MPSAFE
 	pci_intr_setattr(pc, &sc->sc_intrs[0], PCI_INTR_MPSAFE, true);
 #endif
 	sc->sc_ihs[0] = pci_intr_establish_xname(pc, sc->sc_intrs[0],
 	    IPL_NET, wm_intr_legacy, sc, device_xname(sc->sc_dev));
 	if (sc->sc_ihs[0] == NULL) {
 		aprint_error_dev(sc->sc_dev,"unable to establish %s\n",
 		    (pci_intr_type(sc->sc_intrs[0])
 			== PCI_INTR_TYPE_MSI) ? "MSI" : "INTx");
 		return ENOMEM;
+	}
 	aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr);
 	sc->sc_nintrs = 1;
 	return 0;
+}
 static int
 wm_setup_msix(struct wm_softc *sc)
+{
 	void *vih;
 	kcpuset_t *affinity;
 	int qidx, error, intr_idx, tx_established, rx_established;
 	pci_chipset_tag_t pc = sc->sc_pc;
 	const char *intrstr = NULL;
 	char intrbuf[PCI_INTRSTR_LEN];
 	char intr_xname[INTRDEVNAMEBUF];
 	kcpuset_create(&affinity, false);
 	intr_idx = 0;
 	/*
 	 * TX
 	 */
 	tx_established = 0;
 	for (qidx = 0; qidx < sc->sc_ntxqueues; qidx++) {
 		struct wm_txqueue *txq = &sc->sc_txq[qidx];
 		intrstr = pci_intr_string(pc, sc->sc_intrs[intr_idx], intrbuf,
 		    sizeof(intrbuf));
 #ifdef WM_MPSAFE
 		pci_intr_setattr(pc, &sc->sc_intrs[intr_idx],
 		    PCI_INTR_MPSAFE, true);
 #endif
 		memset(intr_xname, 0, sizeof(intr_xname));
 		snprintf(intr_xname, sizeof(intr_xname), "%sTX%d",
 		    device_xname(sc->sc_dev), qidx);
 		vih = pci_intr_establish_xname(pc, sc->sc_intrs[intr_idx],
 		    IPL_NET, wm_txintr_msix, txq, intr_xname);
 		if (vih == NULL) {
 			aprint_error_dev(sc->sc_dev,
 			    "unable to establish MSI-X(for TX)%s%s\n",
 			    intrstr ? " at " : "",
 			    intrstr ? intrstr : "");
 			goto fail_0;
+		}
 		kcpuset_zero(affinity);
 		/* Round-robin affinity */
 		kcpuset_set(affinity, intr_idx % ncpu);
 		error = interrupt_distribute(vih, affinity, NULL);
 		if (error == 0) {
 			aprint_normal_dev(sc->sc_dev,
 			    "for TX interrupting at %s affinity to %u\n",
 			    intrstr, intr_idx % ncpu);
 		} else {
 			aprint_normal_dev(sc->sc_dev,
 			    "for TX interrupting at %s\n", intrstr);
+		}
 		sc->sc_ihs[intr_idx] = vih;
 		txq->txq_id = qidx;
 		txq->txq_intr_idx = intr_idx;
 		tx_established++;
 		intr_idx++;
+	}
 	/*
 	 * RX
 	 */
 	rx_established = 0;
 	for (qidx = 0; qidx < sc->sc_nrxqueues; qidx++) {
 		struct wm_rxqueue *rxq = &sc->sc_rxq[qidx];
 		intrstr = pci_intr_string(pc, sc->sc_intrs[intr_idx], intrbuf,
 		    sizeof(intrbuf));
 #ifdef WM_MPSAFE
 		pci_intr_setattr(pc, &sc->sc_intrs[intr_idx],
 		    PCI_INTR_MPSAFE, true);
 #endif
 		memset(intr_xname, 0, sizeof(intr_xname));
 		snprintf(intr_xname, sizeof(intr_xname), "%sRX%d",
 		    device_xname(sc->sc_dev), qidx);
 		vih = pci_intr_establish_xname(pc, sc->sc_intrs[intr_idx],
 		    IPL_NET, wm_rxintr_msix, rxq, intr_xname);
 		if (vih == NULL) {
 			aprint_error_dev(sc->sc_dev,
 			    "unable to establish MSI-X(for RX)%s%s\n",
 			    intrstr ? " at " : "",
 			    intrstr ? intrstr : "");
 			goto fail_1;
+		}
 		kcpuset_zero(affinity);
 		/* Round-robin affinity */
 		kcpuset_set(affinity, intr_idx % ncpu);
 		error = interrupt_distribute(vih, affinity, NULL);
 		if (error == 0) {
 			aprint_normal_dev(sc->sc_dev,
 			    "for RX interrupting at %s affinity to %u\n",
 			    intrstr, intr_idx % ncpu);
 		} else {
 			aprint_normal_dev(sc->sc_dev,
 			    "for RX interrupting at %s\n", intrstr);
+		}
 		sc->sc_ihs[intr_idx] = vih;
 		rxq->rxq_id = qidx;
 		rxq->rxq_intr_idx = intr_idx;
 		rx_established++;
 		intr_idx++;
+	}
 	/*
 	 * LINK
 	 */
 	intrstr = pci_intr_string(pc, sc->sc_intrs[intr_idx], intrbuf,
 	    sizeof(intrbuf));
 #ifdef WM_MPSAFE
 	pci_intr_setattr(pc, &sc->sc_intrs[intr_idx],
 	    PCI_INTR_MPSAFE, true);
 #endif
 	memset(intr_xname, 0, sizeof(intr_xname));
 	snprintf(intr_xname, sizeof(intr_xname), "%sLINK",
 	    device_xname(sc->sc_dev));
 	vih = pci_intr_establish_xname(pc, sc->sc_intrs[intr_idx],
 		    IPL_NET, wm_linkintr_msix, sc, intr_xname);
 	if (vih == NULL) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to establish MSI-X(for LINK)%s%s\n",
 		    intrstr ? " at " : "",
 		    intrstr ? intrstr : "");
 		goto fail_1;
+	}
 	/* keep default affinity to LINK interrupt */
 	aprint_normal_dev(sc->sc_dev,
 	    "for LINK interrupting at %s\n", intrstr);
 	sc->sc_ihs[intr_idx] = vih;
 	sc->sc_link_intr_idx = intr_idx;
 	sc->sc_nintrs = sc->sc_ntxqueues + sc->sc_nrxqueues + 1;
 	kcpuset_destroy(affinity);
 	return 0;
  fail_1:
 	for (qidx = 0; qidx < rx_established; qidx++) {
 		struct wm_rxqueue *rxq = &sc->sc_rxq[qidx];
 		pci_intr_disestablish(sc->sc_pc, sc->sc_ihs[rxq->rxq_intr_idx]);
 		sc->sc_ihs[rxq->rxq_intr_idx] = NULL;
+	}
  fail_0:
 	for (qidx = 0; qidx < tx_established; qidx++) {
 		struct wm_txqueue *txq = &sc->sc_txq[qidx];
 		pci_intr_disestablish(sc->sc_pc, sc->sc_ihs[txq->txq_intr_idx]);
 		sc->sc_ihs[txq->txq_intr_idx] = NULL;
+	}
 	kcpuset_destroy(affinity);
 	return ENOMEM;
+}
 #endif
 /*
  * wm_init:		[ifnet interface function]
+ *
  *	Initialize the interface.
  */
 static int
 wm_init(struct ifnet *ifp)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	int ret;
 	WM_CORE_LOCK(sc);
 	ret = wm_init_locked(ifp);
 	WM_CORE_UNLOCK(sc);
 	return ret;
+}
 static int
 wm_init_locked(struct ifnet *ifp)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	int i, j, trynum, error = 0;
 	uint32_t reg;
 	KASSERT(WM_CORE_LOCKED(sc));
 	/*
 	 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set.
 	 * There is a small but measurable benefit to avoiding the adjusment
 	 * of the descriptor so that the headers are aligned, for normal mtu,
 	 * on such platforms.  One possibility is that the DMA itself is
 	 * slightly more efficient if the front of the entire packet (instead
 	 * of the front of the headers) is aligned.
+	 *
 	 * Note we must always set align_tweak to 0 if we are using
 	 * jumbo frames.
 	 */
 #ifdef __NO_STRICT_ALIGNMENT
 	sc->sc_align_tweak = 0;
 #else
 	if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2))
 		sc->sc_align_tweak = 0;
 	else
 		sc->sc_align_tweak = 2;
 #endif /* __NO_STRICT_ALIGNMENT */
 	/* Cancel any pending I/O. */
 	wm_stop_locked(ifp, 0);
 	/* update statistics before reset */
 	ifp->if_collisions += CSR_READ(sc, WMREG_COLC);
 	ifp->if_ierrors += CSR_READ(sc, WMREG_RXERRC);
 	/* Reset the chip to a known state. */
 	wm_reset(sc);
 	switch (sc->sc_type) {
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82583:
 	case WM_T_80003:
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		if (wm_check_mng_mode(sc) != 0)
 			wm_get_hw_control(sc);
 		break;
 	default:
 		break;
+	}
 	/* Init hardware bits */
 	wm_initialize_hardware_bits(sc);
 	/* Reset the PHY. */
 	if (sc->sc_flags & WM_F_HAS_MII)
 		wm_gmii_reset(sc);
 	/* Calculate (E)ITR value */
 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
 		sc->sc_itr = 450;	/* For EITR */
 	} else if (sc->sc_type >= WM_T_82543) {
 		/*
 		 * Set up the interrupt throttling register (units of 256ns)
 		 * Note that a footnote in Intel's documentation says this
 		 * ticker runs at 1/4 the rate when the chip is in 100Mbit
 		 * or 10Mbit mode.  Empirically, it appears to be the case
 		 * that that is also true for the 1024ns units of the other
 		 * interrupt-related timer registers -- so, really, we ought
 		 * to divide this value by 4 when the link speed is low.
+		 *
 		 * XXX implement this division at link speed change!
 		 */
 		/*
 		 * For N interrupts/sec, set this value to:
 		 * 1000000000 / (N * 256).  Note that we set the
 		 * absolute and packet timer values to this value
 		 * divided by 4 to get "simple timer" behavior.
 		 */
 		sc->sc_itr = 1500;		/* 2604 ints/sec */
+	}
 	error = wm_init_txrx_queues(sc);
 	if (error)
 		goto out;
 	/*
 	 * Clear out the VLAN table -- we don't use it (yet).
 	 */
 	CSR_WRITE(sc, WMREG_VET, 0);
 	if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354))
 		trynum = 10; /* Due to hw errata */
 	else
 		trynum = 1;
 	for (i = 0; i < WM_VLAN_TABSIZE; i++)
 		for (j = 0; j < trynum; j++)
 			CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0);
 	/*
 	 * Set up flow-control parameters.
+	 *
 	 * XXX Values could probably stand some tuning.
 	 */
 	if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9)
 	    && (sc->sc_type != WM_T_ICH10) && (sc->sc_type != WM_T_PCH)
 	    && (sc->sc_type != WM_T_PCH2) && (sc->sc_type != WM_T_PCH_LPT)) {
 		CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST);
 		CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST);
 		CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL);
+	}
 	sc->sc_fcrtl = FCRTL_DFLT;
 	if (sc->sc_type < WM_T_82543) {
 		CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT);
 		CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl);
 	} else {
 		CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT);
 		CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl);
+	}
 	if (sc->sc_type == WM_T_80003)
 		CSR_WRITE(sc, WMREG_FCTTV, 0xffff);
 	else
 		CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT);
 	/* Writes the control register. */
 	wm_set_vlan(sc);
 	if (sc->sc_flags & WM_F_HAS_MII) {
 		int val;
 		switch (sc->sc_type) {
 		case WM_T_80003:
 		case WM_T_ICH8:
 		case WM_T_ICH9:
 		case WM_T_ICH10:
 		case WM_T_PCH:
 		case WM_T_PCH2:
 		case WM_T_PCH_LPT:
 			/*
 			 * Set the mac to wait the maximum time between each
 			 * iteration and increase the max iterations when
 			 * polling the phy; this fixes erroneous timeouts at
 			 * 10Mbps.
 			 */
 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_TIMEOUTS,
 xFFFF);
 			val = wm_kmrn_readreg(sc,
 			    KUMCTRLSTA_OFFSET_INB_PARAM);
 			val |= 0x3F;
 			wm_kmrn_writereg(sc,
 			    KUMCTRLSTA_OFFSET_INB_PARAM, val);
 			break;
 		default:
 			break;
+		}
 		if (sc->sc_type == WM_T_80003) {
 			val = CSR_READ(sc, WMREG_CTRL_EXT);
 			val &= ~CTRL_EXT_LINK_MODE_MASK;
 			CSR_WRITE(sc, WMREG_CTRL_EXT, val);
 			/* Bypass RX and TX FIFO's */
 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_FIFO_CTRL,
 			    KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
 			    | KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_INB_CTRL,
 			    KUMCTRLSTA_INB_CTRL_DIS_PADDING |
 			    KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT);
+		}
+	}
 #if 0
 	CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext);
 #endif
 	/* Set up checksum offload parameters. */
 	reg = CSR_READ(sc, WMREG_RXCSUM);
 	reg &= ~(RXCSUM_IPOFL | RXCSUM_IPV6OFL | RXCSUM_TUOFL);
 	if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx)
 		reg |= RXCSUM_IPOFL;
 	if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
 		reg |= RXCSUM_IPOFL | RXCSUM_TUOFL;
 	if (ifp->if_capenable & (IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx))
 		reg |= RXCSUM_IPV6OFL | RXCSUM_TUOFL;
 	CSR_WRITE(sc, WMREG_RXCSUM, reg);
 	/* Set up MSI-X */
 	if (sc->sc_nintrs > 1) {
 		uint32_t ivar;
 		if (sc->sc_type == WM_T_82575) {
 			/* Interrupt control */
 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
 			reg |= CTRL_EXT_PBA | CTRL_EXT_EIAME | CTRL_EXT_NSICR;
 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
 			/* TX */
 			for (i = 0; i < sc->sc_ntxqueues; i++) {
 				struct wm_txqueue *txq = &sc->sc_txq[i];
 				CSR_WRITE(sc, WMREG_MSIXBM(txq->txq_intr_idx),
 				    EITR_TX_QUEUE(txq->txq_id));
+			}
 			/* RX */
 			for (i = 0; i < sc->sc_nrxqueues; i++) {
 				struct wm_rxqueue *rxq = &sc->sc_rxq[i];
 				CSR_WRITE(sc, WMREG_MSIXBM(rxq->rxq_intr_idx),
 				    EITR_RX_QUEUE(rxq->rxq_id));
+			}
 			/* Link status */
 			CSR_WRITE(sc, WMREG_MSIXBM(sc->sc_link_intr_idx),
 			    EITR_OTHER);
 		} else if (sc->sc_type == WM_T_82574) {
 			/* Interrupt control */
 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
 			reg |= CTRL_EXT_PBA | CTRL_EXT_EIAME;
 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
 			ivar = 0;
 			/* TX */
 			for (i = 0; i < sc->sc_ntxqueues; i++) {
 				struct wm_txqueue *txq = &sc->sc_txq[i];
 				ivar |= __SHIFTIN((IVAR_VALID_82574|txq->txq_intr_idx),
 				    IVAR_TX_MASK_Q_82574(txq->txq_id));
+			}
 			/* RX */
 			for (i = 0; i < sc->sc_nrxqueues; i++) {
 				struct wm_rxqueue *rxq = &sc->sc_rxq[i];
 				ivar |= __SHIFTIN((IVAR_VALID_82574|rxq->rxq_intr_idx),
 				    IVAR_RX_MASK_Q_82574(rxq->rxq_id));
+			}
 			/* Link status */
 			ivar |= __SHIFTIN((IVAR_VALID_82574|sc->sc_link_intr_idx),
 			    IVAR_OTHER_MASK);
 			CSR_WRITE(sc, WMREG_IVAR, ivar | IVAR_INT_ON_ALL_WB);
 		} else {
 			/* Interrupt control */
 			CSR_WRITE(sc, WMREG_GPIE, GPIE_NSICR
 			    | GPIE_MULTI_MSIX | GPIE_EIAME
 			    | GPIE_PBA);
 			switch (sc->sc_type) {
 			case WM_T_82580:
 			case WM_T_I350:
 			case WM_T_I354:
 			case WM_T_I210:
 			case WM_T_I211:
 				/* TX */
 				for (i = 0; i < sc->sc_ntxqueues; i++) {
 					struct wm_txqueue *txq = &sc->sc_txq[i];
 					int qid = txq->txq_id;
 					ivar = CSR_READ(sc, WMREG_IVAR_Q(qid));
 					ivar &= ~IVAR_TX_MASK_Q(qid);
 					ivar |= __SHIFTIN(
 						(txq->txq_intr_idx | IVAR_VALID),
 						IVAR_TX_MASK_Q(qid));
 					CSR_WRITE(sc, WMREG_IVAR_Q(qid), ivar);
+				}
 				/* RX */
 				for (i = 0; i < sc->sc_nrxqueues; i++) {
 					struct wm_rxqueue *rxq = &sc->sc_rxq[i];
 					int qid = rxq->rxq_id;
 					ivar = CSR_READ(sc, WMREG_IVAR_Q(qid));
 					ivar &= ~IVAR_RX_MASK_Q(qid);
 					ivar |= __SHIFTIN(
 						(rxq->rxq_intr_idx | IVAR_VALID),
 						IVAR_RX_MASK_Q(qid));
 					CSR_WRITE(sc, WMREG_IVAR_Q(qid), ivar);
+				}
 				break;
 			case WM_T_82576:
 				/* TX */
 				for (i = 0; i < sc->sc_ntxqueues; i++) {
 					struct wm_txqueue *txq = &sc->sc_txq[i];
 					int qid = txq->txq_id;
 					ivar = CSR_READ(sc, WMREG_IVAR_Q_82576(qid));
 					ivar &= ~IVAR_TX_MASK_Q_82576(qid);
 					ivar |= __SHIFTIN(
 						(txq->txq_intr_idx | IVAR_VALID),
 						IVAR_TX_MASK_Q_82576(qid));
 					CSR_WRITE(sc, WMREG_IVAR_Q_82576(qid), ivar);
+				}
 				/* RX */
 				for (i = 0; i < sc->sc_nrxqueues; i++) {
 					struct wm_rxqueue *rxq = &sc->sc_rxq[i];
 					int qid = rxq->rxq_id;
 					ivar = CSR_READ(sc, WMREG_IVAR_Q_82576(qid));
 					ivar &= ~IVAR_RX_MASK_Q_82576(qid);
 					ivar |= __SHIFTIN(
 						(rxq->rxq_intr_idx | IVAR_VALID),
 						IVAR_RX_MASK_Q_82576(qid));
 					CSR_WRITE(sc, WMREG_IVAR_Q_82576(qid), ivar);
+				}
 				break;
 			default:
 				break;
+			}
 			/* Link status */
 			ivar = __SHIFTIN((sc->sc_link_intr_idx | IVAR_VALID),
 			    IVAR_MISC_OTHER);
 			CSR_WRITE(sc, WMREG_IVAR_MISC, ivar);
+		}
 		if (sc->sc_nrxqueues > 1) {
 			wm_init_rss(sc);
 			/*
 			** NOTE: Receive Full-Packet Checksum Offload
 			** is mutually exclusive with Multiqueue. However
 			** this is not the same as TCP/IP checksums which
 			** still work.
 			*/
 			reg = CSR_READ(sc, WMREG_RXCSUM);
 			reg |= RXCSUM_PCSD;
 			CSR_WRITE(sc, WMREG_RXCSUM, reg);
+		}
+	}
 	/* Set up the interrupt registers. */
 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
 	sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 |
 	    ICR_RXO | ICR_RXT0;
 	if (sc->sc_nintrs > 1) {
 		uint32_t mask;
 		switch (sc->sc_type) {
 		case WM_T_82574:
 			CSR_WRITE(sc, WMREG_EIAC_82574,
 			    WMREG_EIAC_82574_MSIX_MASK);
 			sc->sc_icr |= WMREG_EIAC_82574_MSIX_MASK;
 			CSR_WRITE(sc, WMREG_IMS, sc->sc_icr);
 			break;
 		default:
 			if (sc->sc_type == WM_T_82575) {
 				mask = 0;
 				for (i = 0; i < sc->sc_ntxqueues; i++) {
 					struct wm_txqueue *txq = &sc->sc_txq[i];
 					mask |= EITR_TX_QUEUE(txq->txq_id);
+				}
 				for (i = 0; i < sc->sc_nrxqueues; i++) {
 					struct wm_rxqueue *rxq = &sc->sc_rxq[i];
 					mask |= EITR_RX_QUEUE(rxq->rxq_id);
+				}
 				mask |= EITR_OTHER;
 			} else {
 				mask = 0;
 				for (i = 0; i < sc->sc_ntxqueues; i++) {
 					struct wm_txqueue *txq = &sc->sc_txq[i];
 					mask |= 1 << txq->txq_intr_idx;
+				}
 				for (i = 0; i < sc->sc_nrxqueues; i++) {
 					struct wm_rxqueue *rxq = &sc->sc_rxq[i];
 					mask |= 1 << rxq->rxq_intr_idx;
+				}
 				mask |= 1 << sc->sc_link_intr_idx;
+			}
 			CSR_WRITE(sc, WMREG_EIAC, mask);
 			CSR_WRITE(sc, WMREG_EIAM, mask);
 			CSR_WRITE(sc, WMREG_EIMS, mask);
 			CSR_WRITE(sc, WMREG_IMS, ICR_LSC);
 			break;
+		}
 	} else
 		CSR_WRITE(sc, WMREG_IMS, sc->sc_icr);
 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
 	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) {
 		reg = CSR_READ(sc, WMREG_KABGTXD);
 		reg |= KABGTXD_BGSQLBIAS;
 		CSR_WRITE(sc, WMREG_KABGTXD, reg);
+	}
 	/* Set up the inter-packet gap. */
 	CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg);
 	if (sc->sc_type >= WM_T_82543) {
 		/*
 		 * XXX 82574 has both ITR and EITR. SET EITR when we use
 		 * the multi queue function with MSI-X.
 		 */
 		if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
 			int qidx;
 			for (qidx = 0; qidx < sc->sc_ntxqueues; qidx++) {
 				struct wm_txqueue *txq = &sc->sc_txq[qidx];
 				CSR_WRITE(sc, WMREG_EITR(txq->txq_intr_idx),
 				    sc->sc_itr);
+			}
 			for (qidx = 0; qidx < sc->sc_nrxqueues; qidx++) {
 				struct wm_rxqueue *rxq = &sc->sc_rxq[qidx];
 				CSR_WRITE(sc, WMREG_EITR(rxq->rxq_intr_idx),
 				    sc->sc_itr);
+			}
 			/*
 			 * Link interrupts occur much less than TX
 			 * interrupts and RX interrupts. So, we don't
 			 * tune EINTR(WM_MSIX_LINKINTR_IDX) value like
 			 * FreeBSD's if_igb.
 			 */
 		} else
 			CSR_WRITE(sc, WMREG_ITR, sc->sc_itr);
+	}
 	/* Set the VLAN ethernetype. */
 	CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN);
 	/*
 	 * Set up the transmit control register; we start out with
 	 * a collision distance suitable for FDX, but update it whe
 	 * we resolve the media type.
 	 */
 	sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_RTLC
 	    | TCTL_CT(TX_COLLISION_THRESHOLD)
 	    | TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
 	if (sc->sc_type >= WM_T_82571)
 		sc->sc_tctl |= TCTL_MULR;
 	CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
 		/* Write TDT after TCTL.EN is set. See the document. */
 		CSR_WRITE(sc, WMREG_TDT(0), 0);
+	}
 	if (sc->sc_type == WM_T_80003) {
 		reg = CSR_READ(sc, WMREG_TCTL_EXT);
 		reg &= ~TCTL_EXT_GCEX_MASK;
 		reg |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
 		CSR_WRITE(sc, WMREG_TCTL_EXT, reg);
+	}
 	/* Set the media. */
 	if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0)
 		goto out;
 	/* Configure for OS presence */
 	wm_init_manageability(sc);
 	/*
 	 * Set up the receive control register; we actually program
 	 * the register when we set the receive filter.  Use multicast
 	 * address offset type 0.
+	 *
 	 * Only the i82544 has the ability to strip the incoming
 	 * CRC, so we don't enable that feature.
 	 */
 	sc->sc_mchash_type = 0;
 	sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_DPF
 	    | RCTL_MO(sc->sc_mchash_type);
 	/*
 	 * The I350 has a bug where it always strips the CRC whether
 	 * asked to or not. So ask for stripped CRC here and cope in rxeof
 	 */
 	if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)
 	    || (sc->sc_type == WM_T_I210))
 		sc->sc_rctl |= RCTL_SECRC;
 	if (((sc->sc_ethercom.ec_capabilities & ETHERCAP_JUMBO_MTU) != 0)
 	    && (ifp->if_mtu > ETHERMTU)) {
 		sc->sc_rctl |= RCTL_LPE;
 		if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
 			CSR_WRITE(sc, WMREG_RLPML, ETHER_MAX_LEN_JUMBO);
+	}
 	if (MCLBYTES == 2048) {
 		sc->sc_rctl |= RCTL_2k;
 	} else {
 		if (sc->sc_type >= WM_T_82543) {
 			switch (MCLBYTES) {
 			case 4096:
 				sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k;
 				break;
 			case 8192:
 				sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k;
 				break;
 			case 16384:
 				sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k;
 				break;
 			default:
 				panic("wm_init: MCLBYTES %d unsupported",
 				    MCLBYTES);
 				break;
+			}
 		} else panic("wm_init: i82542 requires MCLBYTES = 2048");
+	}
 	/* Set the receive filter. */
 	wm_set_filter(sc);
 	/* Enable ECC */
 	switch (sc->sc_type) {
 	case WM_T_82571:
 		reg = CSR_READ(sc, WMREG_PBA_ECC);
 		reg |= PBA_ECC_CORR_EN;
 		CSR_WRITE(sc, WMREG_PBA_ECC, reg);
 		break;
 	case WM_T_PCH_LPT:
 		reg = CSR_READ(sc, WMREG_PBECCSTS);
 		reg |= PBECCSTS_UNCORR_ECC_ENABLE;
 		CSR_WRITE(sc, WMREG_PBECCSTS, reg);
 		reg = CSR_READ(sc, WMREG_CTRL);
 		reg |= CTRL_MEHE;
 		CSR_WRITE(sc, WMREG_CTRL, reg);
 		break;
 	default:
 		break;
+	}
 	/* On 575 and later set RDT only if RX enabled */
 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
 		int qidx;
 		for (qidx = 0; qidx < sc->sc_nrxqueues; qidx++) {
 			struct wm_rxqueue *rxq = &sc->sc_rxq[qidx];
 			for (i = 0; i < WM_NRXDESC; i++) {
 				WM_RX_LOCK(rxq);
 				wm_init_rxdesc(rxq, i);
 				WM_RX_UNLOCK(rxq);
+			}
+		}
+	}
 	sc->sc_stopping = false;
 	/* Start the one second link check clock. */
 	callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc);
 	/* ...all done! */
 	ifp->if_flags |= IFF_RUNNING;
 	ifp->if_flags &= ~IFF_OACTIVE;
  out:
 	sc->sc_if_flags = ifp->if_flags;
 	if (error)
 		log(LOG_ERR, "%s: interface not running\n",
 		    device_xname(sc->sc_dev));
 	return error;
+}
 /*
  * wm_stop:		[ifnet interface function]
+ *
  *	Stop transmission on the interface.
  */
 static void
 wm_stop(struct ifnet *ifp, int disable)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	WM_CORE_LOCK(sc);
 	wm_stop_locked(ifp, disable);
 	WM_CORE_UNLOCK(sc);
+}
 static void
 wm_stop_locked(struct ifnet *ifp, int disable)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	struct wm_txsoft *txs;
 	int i, qidx;
 	KASSERT(WM_CORE_LOCKED(sc));
 	sc->sc_stopping = true;
 	/* Stop the one second clock. */
 	callout_stop(&sc->sc_tick_ch);
 	/* Stop the 82547 Tx FIFO stall check timer. */
 	if (sc->sc_type == WM_T_82547)
 		callout_stop(&sc->sc_txfifo_ch);
 	if (sc->sc_flags & WM_F_HAS_MII) {
 		/* Down the MII. */
 		mii_down(&sc->sc_mii);
 	} else {
 #if 0
 		/* Should we clear PHY's status properly? */
 		wm_reset(sc);
 #endif
+	}
 	/* Stop the transmit and receive processes. */
 	CSR_WRITE(sc, WMREG_TCTL, 0);
 	CSR_WRITE(sc, WMREG_RCTL, 0);
 	sc->sc_rctl &= ~RCTL_EN;
 	/*
 	 * Clear the interrupt mask to ensure the device cannot assert its
 	 * interrupt line.
 	 * Clear sc->sc_icr to ensure wm_intr_legacy() makes no attempt to
 	 * service any currently pending or shared interrupt.
 	 */
 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
 	sc->sc_icr = 0;
 	if (sc->sc_nintrs > 1) {
 		if (sc->sc_type != WM_T_82574) {
 			CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU);
 			CSR_WRITE(sc, WMREG_EIAC, 0);
 		} else
 			CSR_WRITE(sc, WMREG_EIAC_82574, 0);
+	}
 	/* Release any queued transmit buffers. */
 	for (qidx = 0; qidx < sc->sc_ntxqueues; qidx++) {
 		struct wm_txqueue *txq = &sc->sc_txq[qidx];
 		WM_TX_LOCK(txq);
 		for (i = 0; i < WM_TXQUEUELEN(txq); i++) {
 			txs = &txq->txq_soft[i];
 			if (txs->txs_mbuf != NULL) {
 				bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
 				m_freem(txs->txs_mbuf);
 				txs->txs_mbuf = NULL;
+			}
+		}
 		WM_TX_UNLOCK(txq);
+	}
 	/* Mark the interface as down and cancel the watchdog timer. */
 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 	ifp->if_timer = 0;
 	if (disable) {
 		for (i = 0; i < sc->sc_nrxqueues; i++) {
 			struct wm_rxqueue *rxq = &sc->sc_rxq[i];
 			WM_RX_LOCK(rxq);
 			wm_rxdrain(rxq);
 			WM_RX_UNLOCK(rxq);
+		}
+	}
 #if 0 /* notyet */
 	if (sc->sc_type >= WM_T_82544)
 		CSR_WRITE(sc, WMREG_WUC, 0);
 #endif
+}
 /*
  * wm_tx_offload:
+ *
  *	Set up TCP/IP checksumming parameters for the
  *	specified packet.
  */
 static int
 wm_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp,
     uint8_t *fieldsp)
+{
 	struct wm_txqueue *txq = &sc->sc_txq[0];
 	struct mbuf *m0 = txs->txs_mbuf;
 	struct livengood_tcpip_ctxdesc *t;
 	uint32_t ipcs, tucs, cmd, cmdlen, seg;
 	uint32_t ipcse;
 	struct ether_header *eh;
 	int offset, iphl;
 	uint8_t fields;
 	/*
 	 * XXX It would be nice if the mbuf pkthdr had offset
 	 * fields for the protocol headers.
 	 */
 	eh = mtod(m0, struct ether_header *);
 	switch (htons(eh->ether_type)) {
 	case ETHERTYPE_IP:
 	case ETHERTYPE_IPV6:
 		offset = ETHER_HDR_LEN;
 		break;
 	case ETHERTYPE_VLAN:
 		offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
 		break;
 	default:
 		/*
 		 * Don't support this protocol or encapsulation.
 		 */
 		*fieldsp = 0;
 		*cmdp = 0;
 		return 0;
+	}
 	if ((m0->m_pkthdr.csum_flags &
 	    (M_CSUM_TSOv4|M_CSUM_UDPv4|M_CSUM_TCPv4)) != 0) {
 		iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data);
 	} else {
 		iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data);
+	}
 	ipcse = offset + iphl - 1;
 	cmd = WTX_CMD_DEXT | WTX_DTYP_D;
 	cmdlen = WTX_CMD_DEXT | WTX_DTYP_C | WTX_CMD_IDE;
 	seg = 0;
 	fields = 0;
 	if ((m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) {
 		int hlen = offset + iphl;
 		bool v4 = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0;
 		if (__predict_false(m0->m_len <
 				    (hlen + sizeof(struct tcphdr)))) {
 			/*
 			 * TCP/IP headers are not in the first mbuf; we need
 			 * to do this the slow and painful way.  Let's just
 			 * hope this doesn't happen very often.
 			 */
 			struct tcphdr th;
 			WM_EVCNT_INCR(&sc->sc_ev_txtsopain);
 			m_copydata(m0, hlen, sizeof(th), &th);
 			if (v4) {
 				struct ip ip;
 				m_copydata(m0, offset, sizeof(ip), &ip);
 				ip.ip_len = 0;
 				m_copyback(m0,
 				    offset + offsetof(struct ip, ip_len),
 				    sizeof(ip.ip_len), &ip.ip_len);
 				th.th_sum = in_cksum_phdr(ip.ip_src.s_addr,
 				    ip.ip_dst.s_addr, htons(IPPROTO_TCP));
 			} else {
 				struct ip6_hdr ip6;
 				m_copydata(m0, offset, sizeof(ip6), &ip6);
 				ip6.ip6_plen = 0;
 				m_copyback(m0,
 				    offset + offsetof(struct ip6_hdr, ip6_plen),
 				    sizeof(ip6.ip6_plen), &ip6.ip6_plen);
 				th.th_sum = in6_cksum_phdr(&ip6.ip6_src,
 				    &ip6.ip6_dst, 0, htonl(IPPROTO_TCP));
+			}
 			m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum),
 			    sizeof(th.th_sum), &th.th_sum);
 			hlen += th.th_off << 2;
 		} else {
 			/*
 			 * TCP/IP headers are in the first mbuf; we can do
 			 * this the easy way.
 			 */
 			struct tcphdr *th;
 			if (v4) {
 				struct ip *ip =
 				    (void *)(mtod(m0, char *) + offset);
 				th = (void *)(mtod(m0, char *) + hlen);
 				ip->ip_len = 0;
 				th->th_sum = in_cksum_phdr(ip->ip_src.s_addr,
 				    ip->ip_dst.s_addr, htons(IPPROTO_TCP));
 			} else {
 				struct ip6_hdr *ip6 =
 				    (void *)(mtod(m0, char *) + offset);
 				th = (void *)(mtod(m0, char *) + hlen);
 				ip6->ip6_plen = 0;
 				th->th_sum = in6_cksum_phdr(&ip6->ip6_src,
 				    &ip6->ip6_dst, 0, htonl(IPPROTO_TCP));
+			}
 			hlen += th->th_off << 2;
+		}
 		if (v4) {
 			WM_EVCNT_INCR(&sc->sc_ev_txtso);
 			cmdlen |= WTX_TCPIP_CMD_IP;
 		} else {
 			WM_EVCNT_INCR(&sc->sc_ev_txtso6);
 			ipcse = 0;
+		}
 		cmd |= WTX_TCPIP_CMD_TSE;
 		cmdlen |= WTX_TCPIP_CMD_TSE |
 		    WTX_TCPIP_CMD_TCP | (m0->m_pkthdr.len - hlen);
 		seg = WTX_TCPIP_SEG_HDRLEN(hlen) |
 		    WTX_TCPIP_SEG_MSS(m0->m_pkthdr.segsz);
+	}
 	/*
 	 * NOTE: Even if we're not using the IP or TCP/UDP checksum
 	 * offload feature, if we load the context descriptor, we
 	 * MUST provide valid values for IPCSS and TUCSS fields.
 	 */
 	ipcs = WTX_TCPIP_IPCSS(offset) |
 	    WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) |
 	    WTX_TCPIP_IPCSE(ipcse);
 	if (m0->m_pkthdr.csum_flags & (M_CSUM_IPv4|M_CSUM_TSOv4)) {