 @@ -1,14 +1,14 @@
-/*	$NetBSD: cpufunc.c,v 1.156 2015/07/02 08:33:31 skrll Exp $	*/
+/*	$NetBSD: cpufunc.c,v 1.157 2015/10/15 07:13:50 skrll Exp $	*/
 /*
  * arm7tdmi support code Copyright (c) 2001 John Fremlin
  * arm8 support code Copyright (c) 1997 ARM Limited
  * arm8 support code Copyright (c) 1997 Causality Limited
  * arm9 support code Copyright (C) 2001 ARM Ltd
  * arm11 support code Copyright (c) 2007 Microsoft
  * cortexa8 support code Copyright (c) 2008 3am Software Foundry
  * cortexa8 improvements Copyright (c) Goeran Weinholt
  * Copyright (c) 1997 Mark Brinicombe.
  * Copyright (c) 1997 Causality Limited
  * All rights reserved.
+ *
 @@ -39,27 +39,27 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  * RiscBSD kernel project
+ *
  * cpufuncs.c
+ *
  * C functions for supporting CPU / MMU / TLB specific operations.
+ *
  * Created	: 30/01/97
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.156 2015/07/02 08:33:31 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.157 2015/10/15 07:13:50 skrll Exp $");
 #include "opt_compat_netbsd.h"
 #include "opt_cpuoptions.h"
 #include "opt_perfctrs.h"
 #include <sys/types.h>
 #include <sys/param.h>
 #include <sys/pmc.h>
 #include <sys/systm.h>
 #include <machine/cpu.h>
 #include <machine/bootconfig.h>
 #include <arch/arm/arm/disassem.h>
 @@ -3155,26 +3155,37 @@ armv7_setup(char *args)
 #endif
 	    | CPU_CONTROL_UNAL_ENABLE;
 	int cpuctrlmask = cpuctrl | CPU_CONTROL_AFLT_ENABLE;
 	cpuctrl = parse_cpu_options(args, armv7_options, cpuctrl);
 #ifndef ARM_HAS_VBAR
 	if (vector_page == ARM_VECTORS_HIGH)
 		cpuctrl |= CPU_CONTROL_VECRELOC;
 #endif
 #ifdef TEGRAK1_PMAP_WORKAROUND
 	uint32_t auxctrl = armreg_auxctl_read();
 	// u-boot sets this incorrectly on boot cpu
 	auxctrl &= ~CORTEXA15_ACTLR_BTB;
 	auxctrl |= CORTEXA15_ACTLR_IOBEU;
 	/* Update auxctlr */
 	armreg_auxctl_write(auxctrl);
 #endif
 	/* Clear out the cache */
 	cpu_idcache_wbinv_all();
 	/* Set the control register */
 	curcpu()->ci_ctrl = cpuctrl;
 	cpu_control(cpuctrlmask, cpuctrl);
+}
 #endif /* CPU_ARMV7 */
 #if defined(CPU_ARM1136) || defined(CPU_ARM1176)
 void
 arm11x6_setup(char *args)

 @@ -1,14 +1,14 @@
-/*	$NetBSD: a9_mpsubr.S,v 1.42 2015/06/09 08:08:14 skrll Exp $	*/
+/*	$NetBSD: a9_mpsubr.S,v 1.43 2015/10/15 07:13:50 skrll Exp $	*/
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Matt Thomas of 3am Software Foundry.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
 @@ -488,26 +488,30 @@ cortex_init:
 	// Step 4a, set ACTLR.SMP=1
 	//
 	mrc	p15, 0, r0, c1, c0, 1		// ACTLR read
 	orr	r0, r0, #CORTEXA9_AUXCTL_SMP	// enable SMP
 #if defined(CPU_CORTEXA15)
 	// The A15 requires snoop-delayed exclusive handling to be set
 	// if there are 3 or more CPUs.
 	mrc	p15, 1, r2, c9, c0, 2		// L2CTRL read
 	ubfx	r2, r2, #25, #1			// bit 25 is set when 3+ CPUs
 	bfi	r0, r2, #31, #1			// copy it to bit 31 in ACTRL
 #endif
 #if defined(TEGRAK1_PMAP_WORKAROUND)
 	orr	r0, r0, #CORTEXA15_ACTLR_IOBEU
 #endif
 #if defined(CPU_CORTEXA5) || defined(CPU_CORTEXA9)
 	//
 	// Step 4a (continued on A5/A9), ACTLR.FW=1)
 	//
 	orr	r0, r0, #CORTEXA9_AUXCTL_FW	// enable cache/tlb/coherency
 #endif	/* A5 || A9 */
 #if defined(CPU_CORTEXA9)
 	//
 	// Step 4b (continued on A9), ACTLR.L2PE=1)
 	//
 	orr	r0, r0, #CORTEXA9_AUXCTL_L2PE	// enable L2 cache prefetch
 #endif

 @@ -1,14 +1,14 @@
-/*	$NetBSD: armreg.h,v 1.107 2015/06/09 08:08:14 skrll Exp $	*/
+/*	$NetBSD: armreg.h,v 1.108 2015/10/15 07:13:50 skrll Exp $	*/
 /*
  * Copyright (c) 1998, 2001 Ben Harris
  * Copyright (c) 1994-1996 Mark Brinicombe.
  * Copyright (c) 1994 Brini.
  * All rights reserved.
+ *
  * This code is derived from software written for Brini by Mark Brinicombe
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
 @@ -446,26 +446,31 @@
 #define PJ4B_AUXFMC0_DCSLFD	__BIT(2)  /* Disable DC Speculative linefill */
 #define PJ4B_AUXFMC0_FW		__BIT(8)  /* alias of PJ4B_AUXCTL_FW*/
 /* Cortex-A9 Auxiliary Control Register (CP15 register 1, opcode 1) */
 #define	CORTEXA9_AUXCTL_FW	0x00000001 /* Cache and TLB updates broadcast */
 #define	CORTEXA9_AUXCTL_L2PE	0x00000002 /* Prefetch hint enable */
 #define	CORTEXA9_AUXCTL_L1PE	0x00000004 /* Data prefetch hint enable */
 #define	CORTEXA9_AUXCTL_WR_ZERO	0x00000008 /* Ena. write full line of 0s mode */
 #define	CORTEXA9_AUXCTL_SMP	0x00000040 /* Coherency is active */
 #define	CORTEXA9_AUXCTL_EXCL	0x00000080 /* Exclusive cache bit */
 #define	CORTEXA9_AUXCTL_ONEWAY	0x00000100 /* Allocate in on cache way only */
 #define	CORTEXA9_AUXCTL_PARITY	0x00000200 /* Support parity checking */
 /* Cortex-A15 Auxiliary Control Register (CP15 register 1, opcode 1) */
 #define	CORTEXA15_ACTLR_BTB	__BIT(0)  /* Cache and TLB updates broadcast */
 #define	CORTEXA15_ACTLR_SMP	__BIT(6)  /* SMP */
 #define	CORTEXA15_ACTLR_IOBEU	__BIT(15) /* In order issue in Branch Exec UNIT */
 /* Marvell Feroceon Extra Features Register (CP15 register 1, opcode2 0) */
 #define FC_DCACHE_REPL_LOCK	0x80000000 /* Replace DCache Lock */
 #define FC_DCACHE_STREAM_EN	0x20000000 /* DCache Streaming Switch */
 #define FC_WR_ALLOC_EN		0x10000000 /* Enable Write Allocate */
 #define FC_L2_PREF_DIS		0x01000000 /* L2 Cache Prefetch Disable */
 #define FC_L2_INV_EVICT_LINE	0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */
 #define FC_L2CACHE_EN		0x00400000 /* L2 enable */
 #define FC_ICACHE_REPL_LOCK	0x00080000 /* Replace ICache Lock */
 #define FC_GLOB_HIST_REG_EN	0x00040000 /* Branch Global History Register Enable */
 #define FC_BRANCH_TARG_BUF_DIS	0x00020000 /* Branch Target Buffer Disable */
 #define FC_L1_PAR_ERR_EN	0x00010000 /* L1 Parity Error Enable */
 /* Cache type register definitions 0 */

 @@ -1,29 +1,30 @@
-#	$NetBSD: std.tegra,v 1.7 2015/05/31 20:04:44 jmcneill Exp $
+#	$NetBSD: std.tegra,v 1.8 2015/10/15 07:13:50 skrll Exp $
+#
 machine	evbarm arm
 include 	"arch/evbarm/conf/std.evbarm"
 include		"arch/evbarm/conf/files.tegra"
 options 	MODULAR
 options 	MODULAR_DEFAULT_AUTOLOAD
 options 	__HAVE_CPU_COUNTER
 options 	CORTEX_PMC
 options 	__HAVE_FAST_SOFTINTS		# should be in types.h
 options 	ARM_HAS_VBAR
 #options 	__HAVE_MM_MD_DIRECT_MAPPED_PHYS
 #options 	PMAP_NEED_ALLOC_POOLPAGE
 options 	TPIDRPRW_IS_CURCPU
 options 	KERNEL_BASE_EXT=0x80000000
 options 	FPU_VFP
 options 	PCI_NETBSD_CONFIGURE
 options 	__HAVE_PCI_CONF_HOOK
 options 	TEGRAK1_PMAP_WORKAROUND
 makeoptions	KERNEL_BASE_PHYS="0x81000000"
 makeoptions	KERNEL_BASE_VIRT="0x81000000"
 makeoptions	BOARDTYPE="tegra"
 makeoptions	BOARDMKFRAG="${THISARM}/conf/mk.tegra"
 options 	ARM_INTR_IMPL="<arch/arm/nvidia/tegra_intr.h>"
 options		ARM_GENERIC_TODR