Sat Oct 17 14:46:01 2015 UTC ()
awin_cpu_clk(): Fix reading of CPU_CLK_SRC_CEL bits: doing a shiftin followed
by a shiftout ends up reading bits(0,1) instead of AWIN_CPU_CLK_SRC_SEL.
It happens that these bits (AWIN_AXI_CLK_DIV_RATIO) are 2 (divide by 3) at boot
(at last on cubieboard2 and olimex lime2), which matches
AWIN_CPU_CLK_SRC_SEL_PLL1, so this has gone  unnoticed.


(bouyer)
diff -r1.35 -r1.36 src/sys/arch/arm/allwinner/awin_board.c
cvs diff -r1.35 -r1.36 src/sys/arch/arm/allwinner/Attic/awin_board.c (expand / switch to unified diff)

--- src/sys/arch/arm/allwinner/Attic/awin_board.c 2015/04/20 01:33:22 1.35
+++ src/sys/arch/arm/allwinner/Attic/awin_board.c 2015/10/17 14:46:01 1.36
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: awin_board.c,v 1.35 2015/04/20 01:33:22 matt Exp $ */ 1/* $NetBSD: awin_board.c,v 1.36 2015/10/17 14:46:01 bouyer Exp $ */
2/*- 2/*-
3 * Copyright (c) 2012 The NetBSD Foundation, Inc. 3 * Copyright (c) 2012 The NetBSD Foundation, Inc.
4 * All rights reserved. 4 * All rights reserved.
5 * 5 *
6 * This code is derived from software contributed to The NetBSD Foundation 6 * This code is derived from software contributed to The NetBSD Foundation
7 * by Matt Thomas of 3am Software Foundry. 7 * by Matt Thomas of 3am Software Foundry.
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
11 * are met: 11 * are met:
12 * 1. Redistributions of source code must retain the above copyright 12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer. 13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright 14 * 2. Redistributions in binary form must reproduce the above copyright
@@ -26,27 +26,27 @@ @@ -26,27 +26,27 @@
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE. 28 * POSSIBILITY OF SUCH DAMAGE.
29 */ 29 */
30 30
31#include "opt_allwinner.h" 31#include "opt_allwinner.h"
32#include "opt_arm_debug.h" 32#include "opt_arm_debug.h"
33#include "opt_multiprocessor.h" 33#include "opt_multiprocessor.h"
34 34
35#define _ARM32_BUS_DMA_PRIVATE 35#define _ARM32_BUS_DMA_PRIVATE
36 36
37#include <sys/cdefs.h> 37#include <sys/cdefs.h>
38 38
39__KERNEL_RCSID(1, "$NetBSD: awin_board.c,v 1.35 2015/04/20 01:33:22 matt Exp $"); 39__KERNEL_RCSID(1, "$NetBSD: awin_board.c,v 1.36 2015/10/17 14:46:01 bouyer Exp $");
40 40
41#include <sys/param.h> 41#include <sys/param.h>
42#include <sys/bus.h> 42#include <sys/bus.h>
43#include <sys/cpu.h> 43#include <sys/cpu.h>
44#include <sys/device.h> 44#include <sys/device.h>
45 45
46#include <prop/proplib.h> 46#include <prop/proplib.h>
47 47
48#include <net/if.h> 48#include <net/if.h>
49#include <net/if_ether.h> 49#include <net/if_ether.h>
50 50
51#include <arm/locore.h> 51#include <arm/locore.h>
52 52
@@ -133,28 +133,27 @@ awin_cpu_clk(void) @@ -133,28 +133,27 @@ awin_cpu_clk(void)
133#if defined(ALLWINNER_A80) 133#if defined(ALLWINNER_A80)
134 const uint32_t c0cpux = bus_space_read_4(bst, awin_core_bsh, 134 const uint32_t c0cpux = bus_space_read_4(bst, awin_core_bsh,
135 AWIN_A80_CCU_OFFSET + AWIN_A80_CCU_PLL_C0CPUX_CTRL_REG); 135 AWIN_A80_CCU_OFFSET + AWIN_A80_CCU_PLL_C0CPUX_CTRL_REG);
136 const u_int p = (c0cpux & AWIN_A80_CCU_PLL_CxCPUX_OUT_EXT_DIVP) ? 4 : 1; 136 const u_int p = (c0cpux & AWIN_A80_CCU_PLL_CxCPUX_OUT_EXT_DIVP) ? 4 : 1;
137 const u_int n = __SHIFTOUT(c0cpux, AWIN_A80_CCU_PLL_CxCPUX_FACTOR_N); 137 const u_int n = __SHIFTOUT(c0cpux, AWIN_A80_CCU_PLL_CxCPUX_FACTOR_N);
138 138
139 ci->ci_data.cpu_cc_freq = ((uint64_t)AWIN_REF_FREQ * n) / p; 139 ci->ci_data.cpu_cc_freq = ((uint64_t)AWIN_REF_FREQ * n) / p;
140#else 140#else
141 u_int reg = awin_chip_id() == AWIN_CHIP_ID_A31 ? 141 u_int reg = awin_chip_id() == AWIN_CHIP_ID_A31 ?
142 AWIN_A31_CPU_AXI_CFG_REG : 142 AWIN_A31_CPU_AXI_CFG_REG :
143 AWIN_CPU_AHB_APB0_CFG_REG; 143 AWIN_CPU_AHB_APB0_CFG_REG;
144 const uint32_t cpu0_cfg = bus_space_read_4(bst, awin_core_bsh, 144 const uint32_t cpu0_cfg = bus_space_read_4(bst, awin_core_bsh,
145 AWIN_CCM_OFFSET + reg); 145 AWIN_CCM_OFFSET + reg);
146 const u_int cpu_clk_sel = __SHIFTIN(cpu0_cfg, AWIN_CPU_CLK_SRC_SEL); 146 switch (__SHIFTOUT(cpu0_cfg, AWIN_CPU_CLK_SRC_SEL)) {
147 switch (__SHIFTOUT(cpu_clk_sel, AWIN_CPU_CLK_SRC_SEL)) { 
148 case AWIN_CPU_CLK_SRC_SEL_LOSC: 147 case AWIN_CPU_CLK_SRC_SEL_LOSC:
149 ci->ci_data.cpu_cc_freq = 32768; 148 ci->ci_data.cpu_cc_freq = 32768;
150 break; 149 break;
151 case AWIN_CPU_CLK_SRC_SEL_OSC24M: 150 case AWIN_CPU_CLK_SRC_SEL_OSC24M:
152 ci->ci_data.cpu_cc_freq = AWIN_REF_FREQ; 151 ci->ci_data.cpu_cc_freq = AWIN_REF_FREQ;
153 break; 152 break;
154 case AWIN_CPU_CLK_SRC_SEL_PLL1: { 153 case AWIN_CPU_CLK_SRC_SEL_PLL1: {
155 const uint32_t pll1_cfg = bus_space_read_4(bst, 154 const uint32_t pll1_cfg = bus_space_read_4(bst,
156 awin_core_bsh, AWIN_CCM_OFFSET + AWIN_PLL1_CFG_REG); 155 awin_core_bsh, AWIN_CCM_OFFSET + AWIN_PLL1_CFG_REG);
157 u_int p, n, k, m; 156 u_int p, n, k, m;
158 if (awin_chip_id() == AWIN_CHIP_ID_A31) { 157 if (awin_chip_id() == AWIN_CHIP_ID_A31) {
159 p = 0; 158 p = 0;
160 n = __SHIFTOUT(pll1_cfg, AWIN_PLL_CFG_FACTOR_N) + 1; 159 n = __SHIFTOUT(pll1_cfg, AWIN_PLL_CFG_FACTOR_N) + 1;