Sat Oct 17 21:14:49 2015 UTC ()
GPU power is controlled by a different register on Tegra124, handle this in tegra_pmc_remove_clamping


(jmcneill)
diff -r1.6 -r1.7 src/sys/arch/arm/nvidia/tegra_pmc.c
diff -r1.4 -r1.5 src/sys/arch/arm/nvidia/tegra_pmcreg.h
cvs diff -r1.6 -r1.7 src/sys/arch/arm/nvidia/tegra_pmc.c (switch to unified diff)

--- src/sys/arch/arm/nvidia/tegra_pmc.c 2015/05/25 10:40:23 1.6
+++ src/sys/arch/arm/nvidia/tegra_pmc.c 2015/10/17 21:14:49 1.7
@@ -1,171 +1,180 @@ @@ -1,171 +1,180 @@
1/* $NetBSD: tegra_pmc.c,v 1.6 2015/05/25 10:40:23 jmcneill Exp $ */ 1/* $NetBSD: tegra_pmc.c,v 1.7 2015/10/17 21:14:49 jmcneill Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
15 * 15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE. 26 * SUCH DAMAGE.
27 */ 27 */
28 28
29#include "locators.h" 29#include "locators.h"
30 30
31#include <sys/cdefs.h> 31#include <sys/cdefs.h>
32__KERNEL_RCSID(0, "$NetBSD: tegra_pmc.c,v 1.6 2015/05/25 10:40:23 jmcneill Exp $"); 32__KERNEL_RCSID(0, "$NetBSD: tegra_pmc.c,v 1.7 2015/10/17 21:14:49 jmcneill Exp $");
33 33
34#include <sys/param.h> 34#include <sys/param.h>
35#include <sys/bus.h> 35#include <sys/bus.h>
36#include <sys/device.h> 36#include <sys/device.h>
37#include <sys/intr.h> 37#include <sys/intr.h>
38#include <sys/systm.h> 38#include <sys/systm.h>
39#include <sys/kernel.h> 39#include <sys/kernel.h>
40 40
41#include <arm/nvidia/tegra_reg.h> 41#include <arm/nvidia/tegra_reg.h>
42#include <arm/nvidia/tegra_pmcreg.h> 42#include <arm/nvidia/tegra_pmcreg.h>
43#include <arm/nvidia/tegra_var.h> 43#include <arm/nvidia/tegra_var.h>
44 44
45static int tegra_pmc_match(device_t, cfdata_t, void *); 45static int tegra_pmc_match(device_t, cfdata_t, void *);
46static void tegra_pmc_attach(device_t, device_t, void *); 46static void tegra_pmc_attach(device_t, device_t, void *);
47 47
48struct tegra_pmc_softc { 48struct tegra_pmc_softc {
49 device_t sc_dev; 49 device_t sc_dev;
50 bus_space_tag_t sc_bst; 50 bus_space_tag_t sc_bst;
51 bus_space_handle_t sc_bsh; 51 bus_space_handle_t sc_bsh;
52}; 52};
53 53
54static struct tegra_pmc_softc *pmc_softc = NULL; 54static struct tegra_pmc_softc *pmc_softc = NULL;
55 55
56CFATTACH_DECL_NEW(tegra_pmc, sizeof(struct tegra_pmc_softc), 56CFATTACH_DECL_NEW(tegra_pmc, sizeof(struct tegra_pmc_softc),
57 tegra_pmc_match, tegra_pmc_attach, NULL, NULL); 57 tegra_pmc_match, tegra_pmc_attach, NULL, NULL);
58 58
59static int 59static int
60tegra_pmc_match(device_t parent, cfdata_t cf, void *aux) 60tegra_pmc_match(device_t parent, cfdata_t cf, void *aux)
61{ 61{
62 return 1; 62 return 1;
63} 63}
64 64
65static void 65static void
66tegra_pmc_attach(device_t parent, device_t self, void *aux) 66tegra_pmc_attach(device_t parent, device_t self, void *aux)
67{ 67{
68 struct tegra_pmc_softc * const sc = device_private(self); 68 struct tegra_pmc_softc * const sc = device_private(self);
69 struct tegraio_attach_args * const tio = aux; 69 struct tegraio_attach_args * const tio = aux;
70 const struct tegra_locators * const loc = &tio->tio_loc; 70 const struct tegra_locators * const loc = &tio->tio_loc;
71 71
72 sc->sc_dev = self; 72 sc->sc_dev = self;
73 sc->sc_bst = tio->tio_bst; 73 sc->sc_bst = tio->tio_bst;
74 bus_space_subregion(tio->tio_bst, tio->tio_bsh, 74 bus_space_subregion(tio->tio_bst, tio->tio_bsh,
75 loc->loc_offset, loc->loc_size, &sc->sc_bsh); 75 loc->loc_offset, loc->loc_size, &sc->sc_bsh);
76 76
77 KASSERT(pmc_softc == NULL); 77 KASSERT(pmc_softc == NULL);
78 pmc_softc = sc; 78 pmc_softc = sc;
79 79
80 aprint_naive("\n"); 80 aprint_naive("\n");
81 aprint_normal(": PMC\n"); 81 aprint_normal(": PMC\n");
82} 82}
83 83
84static void 84static void
85tegra_pmc_get_bs(bus_space_tag_t *pbst, bus_space_handle_t *pbsh) 85tegra_pmc_get_bs(bus_space_tag_t *pbst, bus_space_handle_t *pbsh)
86{ 86{
87 if (pmc_softc) { 87 if (pmc_softc) {
88 *pbst = pmc_softc->sc_bst; 88 *pbst = pmc_softc->sc_bst;
89 *pbsh = pmc_softc->sc_bsh; 89 *pbsh = pmc_softc->sc_bsh;
90 } else { 90 } else {
91 *pbst = &armv7_generic_bs_tag; 91 *pbst = &armv7_generic_bs_tag;
92 bus_space_subregion(*pbst, tegra_apb_bsh, 92 bus_space_subregion(*pbst, tegra_apb_bsh,
93 TEGRA_PMC_OFFSET, TEGRA_PMC_SIZE, pbsh); 93 TEGRA_PMC_OFFSET, TEGRA_PMC_SIZE, pbsh);
94 } 94 }
95} 95}
96 96
97void 97void
98tegra_pmc_reset(void) 98tegra_pmc_reset(void)
99{ 99{
100 bus_space_tag_t bst; 100 bus_space_tag_t bst;
101 bus_space_handle_t bsh; 101 bus_space_handle_t bsh;
102 uint32_t cntrl; 102 uint32_t cntrl;
103 103
104 tegra_pmc_get_bs(&bst, &bsh); 104 tegra_pmc_get_bs(&bst, &bsh);
105 105
106 cntrl = bus_space_read_4(bst, bsh, PMC_CNTRL_0_REG); 106 cntrl = bus_space_read_4(bst, bsh, PMC_CNTRL_0_REG);
107 cntrl |= PMC_CNTRL_0_MAIN_RST; 107 cntrl |= PMC_CNTRL_0_MAIN_RST;
108 bus_space_write_4(bst, bsh, PMC_CNTRL_0_REG, cntrl); 108 bus_space_write_4(bst, bsh, PMC_CNTRL_0_REG, cntrl);
109 109
110 for (;;) { 110 for (;;) {
111 __asm("wfi"); 111 __asm("wfi");
112 } 112 }
113} 113}
114 114
115void 115void
116tegra_pmc_power(u_int partid, bool enable) 116tegra_pmc_power(u_int partid, bool enable)
117{ 117{
118 bus_space_tag_t bst; 118 bus_space_tag_t bst;
119 bus_space_handle_t bsh; 119 bus_space_handle_t bsh;
120 uint32_t status, toggle; 120 uint32_t status, toggle;
121 bool state; 121 bool state;
122 int retry = 10000; 122 int retry = 10000;
123 123
124 tegra_pmc_get_bs(&bst, &bsh); 124 tegra_pmc_get_bs(&bst, &bsh);
125 125
126 status = bus_space_read_4(bst, bsh, PMC_PWRGATE_STATUS_0_REG); 126 status = bus_space_read_4(bst, bsh, PMC_PWRGATE_STATUS_0_REG);
127 state = !!(status & __BIT(partid)); 127 state = !!(status & __BIT(partid));
128 if (state == enable) 128 if (state == enable)
129 return; 129 return;
130 130
131 while (--retry > 0) { 131 while (--retry > 0) {
132 toggle = bus_space_read_4(bst, bsh, PMC_PWRGATE_TOGGLE_0_REG); 132 toggle = bus_space_read_4(bst, bsh, PMC_PWRGATE_TOGGLE_0_REG);
133 if ((toggle & PMC_PWRGATE_TOGGLE_0_START) == 0) 133 if ((toggle & PMC_PWRGATE_TOGGLE_0_START) == 0)
134 break; 134 break;
135 delay(1); 135 delay(1);
136 } 136 }
137 if (retry == 0) { 137 if (retry == 0) {
138 printf("ERROR: Couldn't enable PMC partition %#x\n", partid); 138 printf("ERROR: Couldn't enable PMC partition %#x\n", partid);
139 return; 139 return;
140 } 140 }
141 141
142 bus_space_write_4(bst, bsh, PMC_PWRGATE_TOGGLE_0_REG, 142 bus_space_write_4(bst, bsh, PMC_PWRGATE_TOGGLE_0_REG,
143 __SHIFTIN(partid, PMC_PWRGATE_TOGGLE_0_PARTID) | 143 __SHIFTIN(partid, PMC_PWRGATE_TOGGLE_0_PARTID) |
144 PMC_PWRGATE_TOGGLE_0_START); 144 PMC_PWRGATE_TOGGLE_0_START);
145} 145}
146 146
147void 147void
148tegra_pmc_remove_clamping(u_int partid) 148tegra_pmc_remove_clamping(u_int partid)
149{ 149{
150 bus_space_tag_t bst; 150 bus_space_tag_t bst;
151 bus_space_handle_t bsh; 151 bus_space_handle_t bsh;
152 152
153 tegra_pmc_get_bs(&bst, &bsh); 153 tegra_pmc_get_bs(&bst, &bsh);
154 154
 155 if (tegra_chip_id() == CHIP_ID_TEGRA124) {
 156 /*
 157 * On Tegra124 the GPU power clamping is controlled by a
 158 * separate register
 159 */
 160 bus_space_write_4(bst, bsh, PMC_GPU_RG_CNTRL_REG, 0);
 161 return;
 162 }
 163
155 bus_space_write_4(bst, bsh, PMC_REMOVE_CLAMPING_CMD_0_REG, 164 bus_space_write_4(bst, bsh, PMC_REMOVE_CLAMPING_CMD_0_REG,
156 __BIT(partid)); 165 __BIT(partid));
157} 166}
158 167
159void 168void
160tegra_pmc_hdmi_enable(void) 169tegra_pmc_hdmi_enable(void)
161{ 170{
162 bus_space_tag_t bst; 171 bus_space_tag_t bst;
163 bus_space_handle_t bsh; 172 bus_space_handle_t bsh;
164 173
165 tegra_pmc_get_bs(&bst, &bsh); 174 tegra_pmc_get_bs(&bst, &bsh);
166 175
167 tegra_reg_set_clear(bst, bsh, PMC_IO_DPD_STATUS_REG, 176 tegra_reg_set_clear(bst, bsh, PMC_IO_DPD_STATUS_REG,
168 0, PMC_IO_DPD_STATUS_HDMI); 177 0, PMC_IO_DPD_STATUS_HDMI);
169 tegra_reg_set_clear(bst, bsh, PMC_IO_DPD2_STATUS_REG, 178 tegra_reg_set_clear(bst, bsh, PMC_IO_DPD2_STATUS_REG,
170 0, PMC_IO_DPD2_STATUS_HV); 179 0, PMC_IO_DPD2_STATUS_HV);
171} 180}
cvs diff -r1.4 -r1.5 src/sys/arch/arm/nvidia/tegra_pmcreg.h (switch to unified diff)

--- src/sys/arch/arm/nvidia/tegra_pmcreg.h 2015/05/18 21:03:36 1.4
+++ src/sys/arch/arm/nvidia/tegra_pmcreg.h 2015/10/17 21:14:49 1.5
@@ -1,96 +1,99 @@ @@ -1,96 +1,99 @@
1/* $NetBSD: tegra_pmcreg.h,v 1.4 2015/05/18 21:03:36 jmcneill Exp $ */ 1/* $NetBSD: tegra_pmcreg.h,v 1.5 2015/10/17 21:14:49 jmcneill Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
15 * 15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE. 26 * SUCH DAMAGE.
27 */ 27 */
28 28
29#ifndef _ARM_TEGRA_PMCREG_H 29#ifndef _ARM_TEGRA_PMCREG_H
30#define _ARM_TEGRA_PMCREG_H 30#define _ARM_TEGRA_PMCREG_H
31 31
32#define PMC_CNTRL_0_REG 0x00 32#define PMC_CNTRL_0_REG 0x00
33 33
34#define PMC_CNTRL_0_CPUPWRGOOD_SEL __BITS(21,20) 34#define PMC_CNTRL_0_CPUPWRGOOD_SEL __BITS(21,20)
35#define PMC_CNTRL_0_CPUPWRGOOD_EN __BIT(19) 35#define PMC_CNTRL_0_CPUPWRGOOD_EN __BIT(19)
36#define PMC_CNTRL_0_FUSE_OVERRIDE __BIT(18) 36#define PMC_CNTRL_0_FUSE_OVERRIDE __BIT(18)
37#define PMC_CNTRL_0_INTR_POLARITY __BIT(17) 37#define PMC_CNTRL_0_INTR_POLARITY __BIT(17)
38#define PMC_CNTRL_0_CPUPWRREG_OE __BIT(16) 38#define PMC_CNTRL_0_CPUPWRREG_OE __BIT(16)
39#define PMC_CNTRL_0_CPUPWRREG_POLARITY __BIT(15) 39#define PMC_CNTRL_0_CPUPWRREG_POLARITY __BIT(15)
40#define PMC_CNTRL_0_SIDE_EFFECT_LP0 __BIT(14) 40#define PMC_CNTRL_0_SIDE_EFFECT_LP0 __BIT(14)
41#define PMC_CNTRL_0_AOINIT __BIT(13) 41#define PMC_CNTRL_0_AOINIT __BIT(13)
42#define PMC_CNTRL_0_PWRGATE_DIS __BIT(12) 42#define PMC_CNTRL_0_PWRGATE_DIS __BIT(12)
43#define PMC_CNTRL_0_SYSCLK_OE __BIT(11) 43#define PMC_CNTRL_0_SYSCLK_OE __BIT(11)
44#define PMC_CNTRL_0_SYSCLK_POLARITY __BIT(10) 44#define PMC_CNTRL_0_SYSCLK_POLARITY __BIT(10)
45#define PMC_CNTRL_0_PWRREQ_OE __BIT(9) 45#define PMC_CNTRL_0_PWRREQ_OE __BIT(9)
46#define PMC_CNTRL_0_PWRREQ_POLARITY __BIT(8) 46#define PMC_CNTRL_0_PWRREQ_POLARITY __BIT(8)
47#define PMC_CNTRL_0_BLINK_EN __BIT(7) 47#define PMC_CNTRL_0_BLINK_EN __BIT(7)
48#define PMC_CNTRL_0_GLITCHDET_DIS __BIT(6) 48#define PMC_CNTRL_0_GLITCHDET_DIS __BIT(6)
49#define PMC_CNTRL_0_LATCHWAKE_EN __BIT(5) 49#define PMC_CNTRL_0_LATCHWAKE_EN __BIT(5)
50#define PMC_CNTRL_0_MAIN_RST __BIT(4) 50#define PMC_CNTRL_0_MAIN_RST __BIT(4)
51#define PMC_CNTRL_0_KBC_RST __BIT(3) 51#define PMC_CNTRL_0_KBC_RST __BIT(3)
52#define PMC_CNTRL_0_RTC_RST __BIT(2) 52#define PMC_CNTRL_0_RTC_RST __BIT(2)
53#define PMC_CNTRL_0_RTC_CLK_DIS __BIT(1) 53#define PMC_CNTRL_0_RTC_CLK_DIS __BIT(1)
54#define PMC_CNTRL_0_KBC_CLK_DIS __BIT(0) 54#define PMC_CNTRL_0_KBC_CLK_DIS __BIT(0)
55 55
56#define PMC_PWRGATE_TOGGLE_0_REG 0x30 56#define PMC_PWRGATE_TOGGLE_0_REG 0x30
57 57
58#define PMC_PWRGATE_TOGGLE_0_START __BIT(8) 58#define PMC_PWRGATE_TOGGLE_0_START __BIT(8)
59#define PMC_PWRGATE_TOGGLE_0_PARTID __BITS(4,0) 59#define PMC_PWRGATE_TOGGLE_0_PARTID __BITS(4,0)
60 60
61#define PMC_REMOVE_CLAMPING_CMD_0_REG 0x34 61#define PMC_REMOVE_CLAMPING_CMD_0_REG 0x34
62 62
63#define PMC_PWRGATE_STATUS_0_REG 0x38 63#define PMC_PWRGATE_STATUS_0_REG 0x38
64 64
65#define PMC_PARTID_IRAM 24 65#define PMC_PARTID_IRAM 24
66#define PMC_PARTID_VIC 23 66#define PMC_PARTID_VIC 23
67#define PMC_PARTID_XUSBC 22 67#define PMC_PARTID_XUSBC 22
68#define PMC_PARTID_XUSBB 21 68#define PMC_PARTID_XUSBB 21
69#define PMC_PARTID_XUSBA 20 69#define PMC_PARTID_XUSBA 20
70#define PMC_PARTID_DISB 19 70#define PMC_PARTID_DISB 19
71#define PMC_PARTID_DIS 18 71#define PMC_PARTID_DIS 18
72#define PMC_PARTID_SOR 17 72#define PMC_PARTID_SOR 17
73#define PMC_PARTID_C1NC 16 73#define PMC_PARTID_C1NC 16
74#define PMC_PARTID_C0NC 15 74#define PMC_PARTID_C0NC 15
75#define PMC_PARTID_CE0 14 75#define PMC_PARTID_CE0 14
76#define PMC_PARTID_A9LP 12 76#define PMC_PARTID_A9LP 12
77#define PMC_PARTID_CPU3 11 77#define PMC_PARTID_CPU3 11
78#define PMC_PARTID_CPU2 10 78#define PMC_PARTID_CPU2 10
79#define PMC_PARTID_CPU1 9 79#define PMC_PARTID_CPU1 9
80#define PMC_PARTID_SAX 8 80#define PMC_PARTID_SAX 8
81#define PMC_PARTID_HEG 7 81#define PMC_PARTID_HEG 7
82#define PMC_PARTID_MPE 6 82#define PMC_PARTID_MPE 6
83#define PMC_PARTID_L2C 5 83#define PMC_PARTID_L2C 5
84#define PMC_PARTID_VDE 4 84#define PMC_PARTID_VDE 4
85#define PMC_PARTID_PCX 3 85#define PMC_PARTID_PCX 3
86#define PMC_PARTID_VE 2 86#define PMC_PARTID_VE 2
87#define PMC_PARTID_TD 1 87#define PMC_PARTID_TD 1
88#define PMC_PARTID_CPU0 0 88#define PMC_PARTID_CPU0 0
89 89
90#define PMC_IO_DPD_STATUS_REG 0x1bc 90#define PMC_IO_DPD_STATUS_REG 0x1bc
91#define PMC_IO_DPD_STATUS_HDMI __BIT(28) 91#define PMC_IO_DPD_STATUS_HDMI __BIT(28)
92 92
93#define PMC_IO_DPD2_STATUS_REG 0x1c4 93#define PMC_IO_DPD2_STATUS_REG 0x1c4
94#define PMC_IO_DPD2_STATUS_HV __BIT(6) 94#define PMC_IO_DPD2_STATUS_HV __BIT(6)
95 95
 96#define PMC_GPU_RG_CNTRL_REG 0x2d4
 97#define PMC_GPU_RG_CNTRL_RAIL_CLAMP __BIT(0)
 98
96#endif /* _ARM_TEGRA_PMCREG_H */ 99#endif /* _ARM_TEGRA_PMCREG_H */