 @@ -1,833 +1,862 @@
-/* $NetBSD: tegra_car.c,v 1.26 2015/08/01 21:20:11 jmcneill Exp $ */
+/* $NetBSD: tegra_car.c,v 1.27 2015/10/17 21:16:09 jmcneill Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include "locators.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_car.c,v 1.26 2015/08/01 21:20:11 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_car.c,v 1.27 2015/10/17 21:16:09 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/rndpool.h>
 #include <sys/rndsource.h>
 #include <arm/nvidia/tegra_reg.h>
 #include <arm/nvidia/tegra_carreg.h>
 #include <arm/nvidia/tegra_pmcreg.h>
 #include <arm/nvidia/tegra_var.h>
 static int	tegra_car_match(device_t, cfdata_t, void *);
 static void	tegra_car_attach(device_t, device_t, void *);
 struct tegra_car_softc {
 	device_t		sc_dev;
 	bus_space_tag_t		sc_bst;
 	bus_space_handle_t	sc_bsh;
 	kmutex_t		sc_intr_lock;
 	kmutex_t		sc_rnd_lock;
 	u_int			sc_bytes_wanted;
 	void			*sc_sih;
 	krndsource_t		sc_rndsource;
 };
 static void	tegra_car_init(struct tegra_car_softc *);
 static void	tegra_car_rnd_attach(device_t);
 static void	tegra_car_rnd_intr(void *);
 static void	tegra_car_rnd_callback(size_t, void *);
 static struct tegra_car_softc *pmc_softc = NULL;
 CFATTACH_DECL_NEW(tegra_car, sizeof(struct tegra_car_softc),
 	tegra_car_match, tegra_car_attach, NULL, NULL);
 static int
 tegra_car_match(device_t parent, cfdata_t cf, void *aux)
+{
 	return 1;
+}
 static void
 tegra_car_attach(device_t parent, device_t self, void *aux)
+{
 	struct tegra_car_softc * const sc = device_private(self);
 	struct tegraio_attach_args * const tio = aux;
 	const struct tegra_locators * const loc = &tio->tio_loc;
 	sc->sc_dev = self;
 	sc->sc_bst = tio->tio_bst;
 	bus_space_subregion(tio->tio_bst, tio->tio_bsh,
 	    loc->loc_offset, loc->loc_size, &sc->sc_bsh);
 	KASSERT(pmc_softc == NULL);
 	pmc_softc = sc;
 	aprint_naive("\n");
 	aprint_normal(": CAR\n");
 	tegra_car_init(sc);
 	aprint_verbose_dev(self, "PLLX = %u Hz\n", tegra_car_pllx_rate());
 	aprint_verbose_dev(self, "PLLC = %u Hz\n", tegra_car_pllc_rate());
 	aprint_verbose_dev(self, "PLLE = %u Hz\n", tegra_car_plle_rate());
 	aprint_verbose_dev(self, "PLLU = %u Hz\n", tegra_car_pllu_rate());
 	aprint_verbose_dev(self, "PLLP0 = %u Hz\n", tegra_car_pllp0_rate());
 	aprint_verbose_dev(self, "PLLD2 = %u Hz\n", tegra_car_plld2_rate());
 	config_interrupts(self, tegra_car_rnd_attach);
+}
 static void
 tegra_car_init(struct tegra_car_softc *sc)
+{
 	bus_space_tag_t bst = sc->sc_bst;
 	bus_space_handle_t bsh = sc->sc_bsh;
 	tegra_reg_set_clear(bst, bsh, CAR_PLLD2_BASE_REG,
 	    __SHIFTIN(1, CAR_PLLD2_BASE_MDIV) |
 	    __SHIFTIN(99, CAR_PLLD2_BASE_NDIV) |
 	    __SHIFTIN(1, CAR_PLLD2_BASE_PLDIV),
 	    CAR_PLLD2_BASE_REF_SRC_SEL |
 	    CAR_PLLD2_BASE_PLDIV | CAR_PLLD2_BASE_NDIV | CAR_PLLD2_BASE_MDIV);
+}
 static void
 tegra_car_rnd_attach(device_t self)
+{
 	struct tegra_car_softc * const sc = device_private(self);
 	mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SERIAL);
 	mutex_init(&sc->sc_rnd_lock, MUTEX_DEFAULT, IPL_SERIAL);
 	sc->sc_bytes_wanted = 0;
 	sc->sc_sih = softint_establish(SOFTINT_SERIAL|SOFTINT_MPSAFE,
 	    tegra_car_rnd_intr, sc);
 	if (sc->sc_sih == NULL) {
 		aprint_error_dev(sc->sc_dev, "couldn't establish softint\n");
 		return;
+	}
 	rndsource_setcb(&sc->sc_rndsource, tegra_car_rnd_callback, sc);
 	rnd_attach_source(&sc->sc_rndsource, device_xname(sc->sc_dev),
 	    RND_TYPE_RNG, RND_FLAG_COLLECT_VALUE|RND_FLAG_HASCB);
+}
 static void
 tegra_car_rnd_intr(void *priv)
+{
 	struct tegra_car_softc * const sc = priv;
 	uint16_t buf[512];
 	uint32_t cnt;
 	mutex_enter(&sc->sc_intr_lock);
 	while (sc->sc_bytes_wanted) {
 		const u_int nbytes = MIN(sc->sc_bytes_wanted, 1024);
 		for (cnt = 0; cnt < sc->sc_bytes_wanted / 2; cnt++) {
 			buf[cnt] = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
 			    CAR_PLL_LFSR_REG) & 0xffff;
+		}
 		mutex_exit(&sc->sc_intr_lock);
 		mutex_enter(&sc->sc_rnd_lock);
 		rnd_add_data(&sc->sc_rndsource, buf, nbytes, nbytes * NBBY);
 		mutex_exit(&sc->sc_rnd_lock);
 		mutex_enter(&sc->sc_intr_lock);
 		sc->sc_bytes_wanted -= MIN(sc->sc_bytes_wanted, nbytes);
+	}
 	explicit_memset(buf, 0, sizeof(buf));
 	mutex_exit(&sc->sc_intr_lock);
+}
 static void
 tegra_car_rnd_callback(size_t bytes_wanted, void *priv)
+{
 	struct tegra_car_softc * const sc = priv;
 	mutex_enter(&sc->sc_intr_lock);
 	if (sc->sc_bytes_wanted == 0) {
 		softint_schedule(sc->sc_sih);
+	}
 	if (bytes_wanted > (UINT_MAX - sc->sc_bytes_wanted)) {
 		sc->sc_bytes_wanted = UINT_MAX;
 	} else {
 		sc->sc_bytes_wanted += bytes_wanted;
+	}
 	mutex_exit(&sc->sc_intr_lock);
+}
 static void
 tegra_car_get_bs(bus_space_tag_t *pbst, bus_space_handle_t *pbsh)
+{
 	if (pmc_softc) {
 		*pbst = pmc_softc->sc_bst;
 		*pbsh = pmc_softc->sc_bsh;
 	} else {
 		*pbst = &armv7_generic_bs_tag;
 		bus_space_subregion(*pbst, tegra_ppsb_bsh,
 		    TEGRA_CAR_OFFSET, TEGRA_CAR_SIZE, pbsh);
+	}
+}
 u_int
 tegra_car_osc_rate(void)
+{
 	return TEGRA_REF_FREQ;
+}
 static u_int
 tegra_car_pll_rate(u_int base_reg, u_int divm_mask, u_int divn_mask,
     u_int divp_mask)
+{
 	bus_space_tag_t bst;
 	bus_space_handle_t bsh;
 	uint64_t rate;
 	tegra_car_get_bs(&bst, &bsh);
 	const uint32_t base = bus_space_read_4(bst, bsh, base_reg);
 	const u_int divm = __SHIFTOUT(base, divm_mask);
 	const u_int divn = __SHIFTOUT(base, divn_mask);
 	const u_int divp = __SHIFTOUT(base, divp_mask);
 	rate = (uint64_t)tegra_car_osc_rate() * divn;
 	return rate / (divm << divp);
+}
 void
 tegra_car_pllx_set_rate(u_int divm, u_int divn, u_int divp)
+{
 	bus_space_tag_t bst;
 	bus_space_handle_t bsh;
 	uint32_t base, bp;
 	tegra_car_get_bs(&bst, &bsh);
 	bp = bus_space_read_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG);
 	bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE;
 	bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE,
 			CAR_CCLKG_BURST_POLICY_CPU_STATE);
 	bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE;
 	bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM,
 			CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE);
 	bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp);
 	base = bus_space_read_4(bst, bsh, CAR_PLLX_BASE_REG);
 	base &= ~CAR_PLLX_BASE_DIVM;
 	base &= ~CAR_PLLX_BASE_DIVN;
 	base &= ~CAR_PLLX_BASE_DIVP;
 	base |= __SHIFTIN(divm, CAR_PLLX_BASE_DIVM);
 	base |= __SHIFTIN(divn, CAR_PLLX_BASE_DIVN);
 	base |= __SHIFTIN(divp, CAR_PLLX_BASE_DIVP);
 	bus_space_write_4(bst, bsh, CAR_PLLX_BASE_REG, base);
 	tegra_reg_set_clear(bst, bsh, CAR_PLLX_MISC_REG,
 	    CAR_PLLX_MISC_LOCK_ENABLE, 0);
 	do {
 		delay(2);
 		base = bus_space_read_4(bst, bsh, CAR_PLLX_BASE_REG);
 	} while ((base & CAR_PLLX_BASE_LOCK) == 0);
 	delay(100);
 	bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE;
 	bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN,
 			CAR_CCLKG_BURST_POLICY_CPU_STATE);
 	bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE;
 	bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ,
 			CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE);
 	bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp);
+}
 u_int
 tegra_car_pllx_rate(void)
+{
 	return tegra_car_pll_rate(CAR_PLLX_BASE_REG, CAR_PLLX_BASE_DIVM,
 	    CAR_PLLX_BASE_DIVN, CAR_PLLX_BASE_DIVP);
+}
 u_int
 tegra_car_pllc_rate(void)
+{
 	return tegra_car_pll_rate(CAR_PLLC_BASE_REG, CAR_PLLC_BASE_DIVM,
 	    CAR_PLLC_BASE_DIVN, CAR_PLLC_BASE_DIVP);
+}
 u_int
 tegra_car_plle_rate(void)
+{
 	return tegra_car_pll_rate(CAR_PLLE_BASE_REG, CAR_PLLE_BASE_DIVM,
 	    CAR_PLLE_BASE_DIVN, CAR_PLLE_BASE_DIVP_CML);
+}
 u_int
 tegra_car_pllu_rate(void)
+{
 	bus_space_tag_t bst;
 	bus_space_handle_t bsh;
 	uint64_t rate;
 	tegra_car_get_bs(&bst, &bsh);
 	rate = tegra_car_osc_rate();
 	const uint32_t base = bus_space_read_4(bst, bsh, CAR_PLLU_BASE_REG);
 	const u_int divm = __SHIFTOUT(base, CAR_PLLU_BASE_DIVM);
 	const u_int divn = __SHIFTOUT(base, CAR_PLLU_BASE_DIVN);
 	const u_int divp = __SHIFTOUT(base, CAR_PLLU_BASE_VCO_FREQ) ? 0 : 1;
 	rate = (uint64_t)tegra_car_osc_rate() * divn;
 	return rate / (divm << divp);
+}
 u_int
 tegra_car_pllp0_rate(void)
+{
 	return tegra_car_pll_rate(CAR_PLLP_BASE_REG, CAR_PLLP_BASE_DIVM,
 	    CAR_PLLP_BASE_DIVN, CAR_PLLP_BASE_DIVP);
+}
 u_int
 tegra_car_plld2_rate(void)
+{
 	return tegra_car_pll_rate(CAR_PLLD2_BASE_REG, CAR_PLLD2_BASE_MDIV,
 	    CAR_PLLD2_BASE_NDIV, CAR_PLLD2_BASE_PLDIV);
+}
 u_int
 tegra_car_uart_rate(u_int port)
+{
 	bus_space_tag_t bst;
 	bus_space_handle_t bsh;
 	bus_size_t src_reg;
 	u_int src_rate;
 	tegra_car_get_bs(&bst, &bsh);
 	switch (port) {
 	case 0: src_reg = CAR_CLKSRC_UARTA_REG; break;
 	case 1: src_reg = CAR_CLKSRC_UARTB_REG; break;
 	case 2: src_reg = CAR_CLKSRC_UARTC_REG; break;
 	case 3: src_reg = CAR_CLKSRC_UARTD_REG; break;
 	default: return 0;
+	}
 	const uint32_t src = bus_space_read_4(bst, bsh, src_reg);
 	switch (__SHIFTOUT(src, CAR_CLKSRC_UART_SRC)) {
 	case 0:
 		src_rate = tegra_car_pllp0_rate();
 		break;
 	default:
 		panic("%s: unsupported src %#x", __func__, src);
+	}
 	if (__SHIFTOUT(src, CAR_CLKSRC_UART_DIV_ENB)) {
 		const u_int div = (__SHIFTOUT(src, CAR_CLKSRC_UART_DIV) / 2) + 1;
 		return src_rate / div;
 	} else {
 		return src_rate;
+	}
+}
 u_int
 tegra_car_periph_sdmmc_rate(u_int port)
+{
 	bus_space_tag_t bst;
 	bus_space_handle_t bsh;
 	bus_size_t src_reg;
 	tegra_car_get_bs(&bst, &bsh);
 	switch (port) {
 	case 0:	src_reg = CAR_CLKSRC_SDMMC1_REG; break;
 	case 1: src_reg = CAR_CLKSRC_SDMMC2_REG; break;
 	case 2: src_reg = CAR_CLKSRC_SDMMC3_REG; break;
 	case 3: src_reg = CAR_CLKSRC_SDMMC4_REG; break;
 	default: return 0;
+	}
 	const uint32_t src = bus_space_read_4(bst, bsh, src_reg);
 	const u_int div = __SHIFTOUT(src, CAR_CLKSRC_SDMMC_DIV) + 2;
 	return (tegra_car_pllp0_rate() * 2) / div;
+}
 int
 tegra_car_periph_sdmmc_set_rate(u_int port, u_int rate)
+{
 	bus_space_tag_t bst;
 	bus_space_handle_t bsh;
 	bus_size_t src_reg, rst_reg, enb_reg;
 	u_int dev_bit;
 	uint32_t src;
 	KASSERT(rate > 0);
 	tegra_car_get_bs(&bst, &bsh);
 	switch (port) {
 	case 0:
 		src_reg = CAR_CLKSRC_SDMMC1_REG;
 		rst_reg = CAR_RST_DEV_L_SET_REG;
 		enb_reg = CAR_CLK_ENB_L_SET_REG;
 		dev_bit = CAR_DEV_L_SDMMC1;
 		break;
 	case 1:
 		src_reg = CAR_CLKSRC_SDMMC2_REG;
 		rst_reg = CAR_RST_DEV_L_SET_REG;
 		enb_reg = CAR_CLK_ENB_L_SET_REG;
 		dev_bit = CAR_DEV_L_SDMMC2;
 		break;
 	case 2:
 		src_reg = CAR_CLKSRC_SDMMC3_REG;
 		rst_reg = CAR_RST_DEV_U_SET_REG;
 		enb_reg = CAR_CLK_ENB_U_SET_REG;
 		dev_bit = CAR_DEV_U_SDMMC3;
 		break;
 	case 3:
 		src_reg = CAR_CLKSRC_SDMMC4_REG;
 		rst_reg = CAR_RST_DEV_L_SET_REG;
 		enb_reg = CAR_CLK_ENB_L_SET_REG;
 		dev_bit = CAR_DEV_L_SDMMC4;
 		break;
 	default: return EINVAL;
+	}
 	/* enter reset */
 	bus_space_write_4(bst, bsh, rst_reg, dev_bit);
 	/* enable clk */
 	bus_space_write_4(bst, bsh, enb_reg, dev_bit);
 	const u_int div = howmany(tegra_car_pllp0_rate() * 2, rate) - 2;
 	/* update clk div */
 	src = __SHIFTIN(CAR_CLKSRC_SDMMC_SRC_PLLP_OUT0,
 			CAR_CLKSRC_SDMMC_SRC);
 	src |= __SHIFTIN(div, CAR_CLKSRC_SDMMC_DIV);
 	bus_space_write_4(bst, bsh, src_reg, src);
 	/* leave reset */
 	bus_space_write_4(bst, bsh, rst_reg+4, dev_bit);
 	return 0;
+}
 int
 tegra_car_periph_usb_enable(u_int port)
+{
 	bus_space_tag_t bst;
 	bus_space_handle_t bsh;
 	bus_size_t rst_reg, enb_reg;
 	uint32_t dev_bit;
 	tegra_car_get_bs(&bst, &bsh);
 	switch (port) {
 	case 0:
 		rst_reg = CAR_RST_DEV_L_SET_REG;
 		enb_reg = CAR_CLK_ENB_L_SET_REG;
 		dev_bit = CAR_DEV_L_USBD;
 		break;
 	case 1:
 		rst_reg = CAR_RST_DEV_H_SET_REG;
 		enb_reg = CAR_CLK_ENB_H_SET_REG;
 		dev_bit = CAR_DEV_H_USB2;
 		break;
 	case 2:
 		rst_reg = CAR_RST_DEV_H_SET_REG;
 		enb_reg = CAR_CLK_ENB_H_SET_REG;
 		dev_bit = CAR_DEV_H_USB3;
 		break;
 	default:
 		return EINVAL;
+	}
 	/* enter reset */
 	bus_space_write_4(bst, bsh, rst_reg, dev_bit);
 	/* enable clk */
 	bus_space_write_4(bst, bsh, enb_reg, dev_bit);
 	/* leave reset */
 	bus_space_write_4(bst, bsh, rst_reg+4, dev_bit);
 	return 0;
+}
 void
 tegra_car_utmip_init(void)
+{
 	const u_int enable_dly_count = 0x02;
 	const u_int stable_count = 0x2f;
 	const u_int active_dly_count = 0x04;
 	const u_int xtal_freq_count = 0x76;
 	bus_space_tag_t bst;
 	bus_space_handle_t bsh;
 	tegra_car_get_bs(&bst, &bsh);
 	tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG,
 	    __SHIFTIN(stable_count, CAR_UTMIP_PLL_CFG2_STABLE_COUNT) |
 	    __SHIFTIN(active_dly_count, CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT),
 	    CAR_UTMIP_PLL_CFG2_STABLE_COUNT |
 	    CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT);
 	tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG,
 	    __SHIFTIN(enable_dly_count, CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT) |
 	    __SHIFTIN(xtal_freq_count, CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT),
 	    CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT |
 	    CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT);
 	tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG,
 ,
 	    CAR_UTMIP_PLL_CFG1_PLLU_POWERDOWN |
 	    CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN);
+}
 void
 tegra_car_utmip_enable(u_int port)
+{
 	bus_space_tag_t bst;
 	bus_space_handle_t bsh;
 	uint32_t bit = 0;
 	tegra_car_get_bs(&bst, &bsh);
 	switch (port) {
 	case 0:	bit = CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN; break;
 	case 1:	bit = CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN; break;
 	case 2:	bit = CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN; break;
+	}
 	tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG, 0, bit);
+}
 void
 tegra_car_periph_hda_enable(void)
+{
 	bus_space_tag_t bst;
 	bus_space_handle_t bsh;
 	tegra_car_get_bs(&bst, &bsh);
 	bus_space_write_4(bst, bsh, CAR_RST_DEV_V_SET_REG, CAR_DEV_V_HDA);
 	bus_space_write_4(bst, bsh, CAR_CLK_ENB_V_SET_REG, CAR_DEV_V_HDA);
 	bus_space_write_4(bst, bsh, CAR_RST_DEV_V_SET_REG,
 	    CAR_DEV_V_HDA2CODEC_2X);
 	bus_space_write_4(bst, bsh, CAR_CLK_ENB_V_SET_REG,
 	    CAR_DEV_V_HDA2CODEC_2X);
 	bus_space_write_4(bst, bsh, CAR_RST_DEV_W_SET_REG,
 	    CAR_DEV_W_HDA2HDMICODEC);
 	bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG,
 	    CAR_DEV_W_HDA2HDMICODEC);
 	/* configure HDA2CODEC_2X for 48 MHz */
 	const u_int div = howmany(tegra_car_pllp0_rate() * 2, 48000000) - 2;
 	bus_space_write_4(bst, bsh, CAR_CLKSRC_HDA2CODEC_2X_REG,
 	    __SHIFTIN(CAR_CLKSRC_HDA2CODEC_2X_SRC_PLLP_OUT0,
 		      CAR_CLKSRC_HDA2CODEC_2X_SRC) |
 	    __SHIFTIN(div, CAR_CLKSRC_HDA2CODEC_2X_DIV));
 	bus_space_write_4(bst, bsh, CAR_RST_DEV_V_CLR_REG, CAR_DEV_V_HDA);
 	bus_space_write_4(bst, bsh, CAR_RST_DEV_V_CLR_REG,
 	    CAR_DEV_V_HDA2CODEC_2X);
 	bus_space_write_4(bst, bsh, CAR_RST_DEV_W_CLR_REG,
 	    CAR_DEV_W_HDA2HDMICODEC);
+}
 void
 tegra_car_periph_sata_enable(void)
+{
 	bus_space_tag_t bst;
 	bus_space_handle_t bsh;
 	tegra_car_get_bs(&bst, &bsh);
 	/* Assert resets */
 	bus_space_write_4(bst, bsh, CAR_RST_DEV_V_SET_REG, CAR_DEV_V_SATA);
 	bus_space_write_4(bst, bsh, CAR_RST_DEV_W_SET_REG, CAR_DEV_W_SATACOLD);
 	/* Disable software control of SATA PLL */
 	tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG,
 , CAR_SATA_PLL_CFG0_PADPLL_RESET_SWCTL);
 	/* Set SATA_OOB clock source to PLLP, 204MHz */
 	const u_int sataoob_div = 2;
 	bus_space_write_4(bst, bsh, CAR_CLKSRC_SATA_OOB_REG,
 	    __SHIFTIN(CAR_CLKSRC_SATA_OOB_SRC_PLLP_OUT0,
 		      CAR_CLKSRC_SATA_OOB_SRC) |
 	    __SHIFTIN((sataoob_div - 1) * 2, CAR_CLKSRC_SATA_OOB_DIV));
 	/* Set SATA clock source to PLLP, 102MHz */
 	const u_int sata_div = 4;
 	bus_space_write_4(bst, bsh, CAR_CLKSRC_SATA_REG,
 	    CAR_CLKSRC_SATA_AUX_CLK_ENB |
 	    __SHIFTIN(CAR_CLKSRC_SATA_SRC_PLLP_OUT0,
 		      CAR_CLKSRC_SATA_SRC) |
 	    __SHIFTIN((sata_div - 1) * 2, CAR_CLKSRC_SATA_DIV));
 	/* Ungate SAX partition in the PMC */
 	tegra_pmc_power(PMC_PARTID_SAX, true);
 	delay(20);
 	/* Remove clamping from SAX partition in the PMC */
 	tegra_pmc_remove_clamping(PMC_PARTID_SAX);
 	delay(20);
 	/* De-assert reset to SATA PADPLL */
 	tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG,
 , CAR_SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE);
 	delay(15);
 	/* Enable CML clock for SATA */
 	tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG,
 	    CAR_PLLE_AUX_CML1_OEN, 0);
 	/* Turn on the clocks to SATA and de-assert resets */
 	bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_SATACOLD);
 	bus_space_write_4(bst, bsh, CAR_CLK_ENB_V_SET_REG, CAR_DEV_V_SATA);
 	bus_space_write_4(bst, bsh, CAR_CLK_ENB_V_SET_REG, CAR_DEV_V_SATA_OOB);
 	bus_space_write_4(bst, bsh, CAR_RST_DEV_W_CLR_REG, CAR_DEV_W_SATACOLD);
 	bus_space_write_4(bst, bsh, CAR_RST_DEV_V_CLR_REG, CAR_DEV_V_SATA);
+}
 int
 tegra_car_periph_i2c_enable(u_int port, u_int rate)
+{
 	bus_space_tag_t bst;
 	bus_space_handle_t bsh;
 	bus_size_t rst_reg, enb_reg, clksrc_reg;
 	uint32_t dev_bit;
 	tegra_car_get_bs(&bst, &bsh);
 	switch (port) {
 	case 0:
 		rst_reg = CAR_RST_DEV_L_SET_REG;
 		enb_reg = CAR_CLK_ENB_L_SET_REG;
 		dev_bit = CAR_DEV_L_I2C1;
 		clksrc_reg = CAR_CLKSRC_I2C1_REG;
 		break;
 	case 1:
 		rst_reg = CAR_RST_DEV_H_SET_REG;
 		enb_reg = CAR_CLK_ENB_H_SET_REG;
 		dev_bit = CAR_DEV_H_I2C2;
 		clksrc_reg = CAR_CLKSRC_I2C2_REG;
 		break;
 	case 2:
 		rst_reg = CAR_RST_DEV_U_SET_REG;
 		enb_reg = CAR_CLK_ENB_U_SET_REG;
 		dev_bit = CAR_DEV_U_I2C3;
 		clksrc_reg = CAR_CLKSRC_I2C3_REG;
 		break;
 	case 3:
 		rst_reg = CAR_RST_DEV_V_SET_REG;
 		enb_reg = CAR_CLK_ENB_V_SET_REG;
 		dev_bit = CAR_DEV_V_I2C4;
 		clksrc_reg = CAR_CLKSRC_I2C4_REG;
 		break;
 	case 4:
 		rst_reg = CAR_RST_DEV_H_SET_REG;
 		enb_reg = CAR_CLK_ENB_H_SET_REG;
 		dev_bit = CAR_DEV_H_I2C5;
 		clksrc_reg = CAR_CLKSRC_I2C5_REG;
 		break;
 	case 5:
 		rst_reg = CAR_RST_DEV_X_SET_REG;
 		enb_reg = CAR_CLK_ENB_X_SET_REG;
 		dev_bit = CAR_DEV_X_I2C6;
 		clksrc_reg = CAR_CLKSRC_I2C6_REG;
 		break;
 	default:
 		return EINVAL;
+	}
 	/* Enter reset, enable clock */
 	bus_space_write_4(bst, bsh, rst_reg, dev_bit);
 	bus_space_write_4(bst, bsh, enb_reg, dev_bit);
 	/* Set clock source to PLLP */
 	const u_int div = howmany(tegra_car_pllp0_rate() / 1000, rate / 1000);
 	bus_space_write_4(bst, bsh, clksrc_reg,
 	    __SHIFTIN(CAR_CLKSRC_I2C_SRC_PLLP_OUT0, CAR_CLKSRC_I2C_SRC) |
 	    __SHIFTIN(div - 1, CAR_CLKSRC_I2C_DIV));
 	/* Leave reset */
 	bus_space_write_4(bst, bsh, rst_reg+4, dev_bit);
 	return 0;
+}
 void
 tegra_car_periph_cec_enable(void)
+{
 	bus_space_tag_t bst;
 	bus_space_handle_t bsh;
 	tegra_car_get_bs(&bst, &bsh);
 	bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_CEC);
 	bus_space_write_4(bst, bsh, CAR_RST_DEV_W_CLR_REG, CAR_DEV_W_CEC);
+}
 void
 tegra_car_hdmi_enable(u_int rate)
+{
 	bus_space_tag_t bst;
 	bus_space_handle_t bsh;
 	uint32_t base;
 	int retry = 10000;
 	tegra_car_get_bs(&bst, &bsh);
 	/* Enter reset, enable clock */
 	bus_space_write_4(bst, bsh, CAR_RST_DEV_H_SET_REG, CAR_DEV_H_HDMI);
 	bus_space_write_4(bst, bsh, CAR_CLK_ENB_H_SET_REG, CAR_DEV_H_HDMI);
 	/* Change IDDQ from 1 to 0 */
 	tegra_reg_set_clear(bst, bsh, CAR_PLLD2_BASE_REG,
 , CAR_PLLD2_BASE_IDDQ);
 	delay(2);
 	/* Enable lock */
 	tegra_reg_set_clear(bst, bsh, CAR_PLLD2_MISC_REG,
 	    CAR_PLLD2_MISC_LOCK_ENABLE, 0);
 	/* Enable PLLD2 */
 	tegra_reg_set_clear(bst, bsh, CAR_PLLD2_BASE_REG,
 	    CAR_PLLD2_BASE_ENABLE, 0);
 	/* Wait for lock */
 	do {
 		delay(2);
 		base = bus_space_read_4(bst, bsh, CAR_PLLD2_BASE_REG);
 	} while ((base & CAR_PLLD2_BASE_LOCK) == 0 && --retry > 0);
 	delay(100);
 	if (retry == 0) {
 		printf("WARNING: timeout waiting for PLLD2 lock\n");
+	}
 	/* Set clock source to PLLD2 */
 	const u_int div = (tegra_car_plld2_rate() * 2) / rate - 2;
 	bus_space_write_4(bst, bsh, CAR_CLKSRC_HDMI_REG,
 	    __SHIFTIN(CAR_CLKSRC_HDMI_SRC_PLLD2_OUT0, CAR_CLKSRC_HDMI_SRC) |
 	    __SHIFTIN(div, CAR_CLKSRC_HDMI_DIV));
 	/* Leave reset */
 	bus_space_write_4(bst, bsh, CAR_RST_DEV_H_CLR_REG, CAR_DEV_H_HDMI);
+}
 int
 tegra_car_dc_enable(u_int port)
+{
 	bus_space_tag_t bst;
 	bus_space_handle_t bsh;
 	bus_size_t src_reg;
 	uint32_t dev_bit;
 	u_int partid;
 	tegra_car_get_bs(&bst, &bsh);
 	switch (port) {
 	case 0:
 		dev_bit = CAR_DEV_L_DISP1;
 		src_reg = CAR_CLKSRC_DISP1_REG;
 		partid = PMC_PARTID_DIS;
 		break;
 	case 1:
 		dev_bit = CAR_DEV_L_DISP2;
 		src_reg = CAR_CLKSRC_DISP2_REG;
 		partid = PMC_PARTID_DISB;
 		break;
 	default:
 		return EINVAL;
+	}
 	/* Enter reset, enable clock */
 	bus_space_write_4(bst, bsh, CAR_RST_DEV_L_SET_REG, dev_bit);
 	bus_space_write_4(bst, bsh, CAR_CLK_ENB_L_SET_REG, dev_bit);
 	/* Turn on power to display partition */
 	tegra_pmc_power(partid, true);
 	tegra_pmc_remove_clamping(partid);
 	/* Select PLLD2 for clock source */
 	bus_space_write_4(bst, bsh, src_reg,
 	    __SHIFTIN(CAR_CLKSRC_DISP_SRC_PLLD2_OUT0,
 		      CAR_CLKSRC_DISP_SRC));
 	/* Leave reset */
 	bus_space_write_4(bst, bsh, CAR_RST_DEV_L_CLR_REG, dev_bit);
 	return 0;
+}
 void
 tegra_car_host1x_enable(void)
+{
 	bus_space_tag_t bst;
 	bus_space_handle_t bsh;
 	tegra_car_get_bs(&bst, &bsh);
 	/* Enter reset, enable clock */
 	bus_space_write_4(bst, bsh, CAR_RST_DEV_L_SET_REG, CAR_DEV_L_HOST1X);
 	bus_space_write_4(bst, bsh, CAR_CLK_ENB_L_SET_REG, CAR_DEV_L_HOST1X);
 	/* Select PLLP for clock source, 408 MHz */
 	bus_space_write_4(bst, bsh, CAR_CLKSRC_HOST1X_REG,
 	    __SHIFTIN(CAR_CLKSRC_HOST1X_SRC_PLLP_OUT0,
 		      CAR_CLKSRC_HOST1X_SRC) |
 	    __SHIFTIN(0, CAR_CLKSRC_HOST1X_CLK_DIVISOR));
 	delay(2);
 	/* Leave reset */
 	bus_space_write_4(bst, bsh, CAR_RST_DEV_L_CLR_REG, CAR_DEV_L_HOST1X);
+}
 void
 tegra_car_wdt_enable(u_int timer, bool enable)
+{
 	bus_space_tag_t bst;
 	bus_space_handle_t bsh;
 	uint32_t enable_bits;
 	KASSERT(timer == 1 || timer == 2);
 	tegra_car_get_bs(&bst, &bsh);
 	enable_bits = enable ?
 	    (CAR_RST_SOURCE_WDT_EN|CAR_RST_SOURCE_WDT_SYS_RST_EN) : 0;
 	tegra_reg_set_clear(bst, bsh, CAR_RST_SOURCE_REG,
 	    __SHIFTIN(timer - 1, CAR_RST_SOURCE_WDT_SEL) |
 	    enable_bits,
 	    CAR_RST_SOURCE_WDT_SYS_RST_EN |
 	    CAR_RST_SOURCE_WDT_SEL |
 	    CAR_RST_SOURCE_WDT_EN);
+}
 void
 tegra_car_gpu_enable(void)
+{
 	bus_space_tag_t bst;
 	bus_space_handle_t bsh;
 	tegra_car_get_bs(&bst, &bsh);
 	/* Enter reset, enable clock */
 	bus_space_write_4(bst, bsh, CAR_RST_DEV_X_SET_REG, CAR_DEV_X_GPU);
 	bus_space_write_4(bst, bsh, CAR_CLK_ENB_X_SET_REG, CAR_DEV_X_GPU);
 	/* Set PLLP_OUT5 to 204MHz */
 	const u_int rate = 204000000;
 	const u_int div = howmany(tegra_car_pllp0_rate() * 2, rate) - 2;
 	tegra_reg_set_clear(bst, bsh, CAR_PLLP_OUTC_REG,
 	    __SHIFTIN(div, CAR_PLLP_OUTC_OUT5_RATIO) |
 	    CAR_PLLP_OUTC_OUT5_CLKEN,
 	    CAR_PLLP_OUTC_OUT5_RATIO);
 	delay(20);
 	/* Remove clamping from 3D partition in the PMC */
 	tegra_pmc_remove_clamping(PMC_PARTID_TD);
 	delay(20);
 	/* Leave reset */
 	bus_space_write_4(bst, bsh, CAR_RST_DEV_X_CLR_REG, CAR_DEV_X_GPU);
+}

 @@ -1,483 +1,488 @@
-/* $NetBSD: tegra_carreg.h,v 1.20 2015/07/25 15:50:42 jmcneill Exp $ */
+/* $NetBSD: tegra_carreg.h,v 1.21 2015/10/17 21:16:09 jmcneill Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #ifndef _ARM_TEGRA_CARREG_H
 #define _ARM_TEGRA_CARREG_H
 #define CAR_RST_SOURCE_REG	0x00
 #define CAR_RST_SOURCE_WDT_EN		__BIT(5)
 #define CAR_RST_SOURCE_WDT_SEL		__BIT(4)
 #define CAR_RST_SOURCE_WDT_SYS_RST_EN	__BIT(2)
 #define CAR_RST_SOURCE_WDT_COP_RST_EN	__BIT(1)
 #define CAR_RST_SOURCE_WDT_CPU_RST_EN	__BIT(0)
 #define CAR_CLK_OUT_ENB_L_REG	0x10
 #define CAR_CLK_OUT_ENB_H_REG	0x14
 #define CAR_CLK_OUT_ENB_U_REG	0x18
 #define CAR_PLL_LFSR_REG	0x54
 #define CAR_PLL_LFSR_RND		__BITS(15,0)
 #define CAR_PLLP_BASE_REG	0xa0
 #define CAR_PLLP_BASE_BYPASS		__BIT(31)
 #define CAR_PLLP_BASE_ENABLE		__BIT(30)
 #define CAR_PLLP_BASE_REF_DIS		__BIT(29)
 #define CAR_PLLP_BASE_OVERRIDE		__BIT(28)
 #define CAR_PLLP_BASE_LOCK		__BIT(27)
 #define CAR_PLLP_BASE_DIVP		__BITS(22,20)
 #define CAR_PLLP_BASE_DIVN		__BITS(17,8)
 #define CAR_PLLP_BASE_DIVM		__BITS(4,0)
 #define CAR_PLLP_OUTA_REG	0xa4
 #define CAR_PLLP_OUTB_REG	0xa8
 #define CAR_PLLP_OUTB_OUT4_RATIO	__BITS(31,24)
 #define CAR_PLLP_OUTB_OUT4_OVRRIDE	__BIT(18)
 #define CAR_PLLP_OUTB_OUT4_CLKEN	__BIT(17)
 #define CAR_PLLP_OUTB_OUT4_RSTN		__BIT(16)
 #define CAR_PLLP_OUTB_OUT3_RATIO	__BITS(15,8)
 #define CAR_PLLP_OUTB_OUT3_OVRRIDE	__BIT(2)
 #define CAR_PLLP_OUTB_OUT3_CLKEN	__BIT(1)
 #define CAR_PLLP_OUTB_OUT3_RSTN		__BIT(0)
 #define CAR_PLLP_OUTC_REG	0x67c
 #define CAR_PLLP_OUTC_OUT5_RATIO	__BITS(31,24)
 #define CAR_PLLP_OUTC_OUT5_OVERRIDE	__BIT(18)
 #define CAR_PLLP_OUTC_OUT5_CLKEN	__BIT(17)
 #define CAR_PLLP_OUTC_OUT5_RSTN		__BIT(16)
 #define CAR_PLLP_MISC_REG	0xac
 #define CAR_PLLC_BASE_REG	0x80
 #define CAR_PLLC_BASE_ENABLE		__BIT(30)
 #define CAR_PLLC_BASE_REF_DIS		__BIT(29)
 #define CAR_PLLC_BASE_LOCK_OVERRIDE	__BIT(28)
 #define CAR_PLLC_BASE_LOCK		__BIT(27)
 #define CAR_PLLC_BASE_DIVP		__BITS(23,20)
 #define CAR_PLLC_BASE_DIVN		__BITS(15,8)
 #define CAR_PLLC_BASE_DIVM		__BITS(7,0)
 #define CAR_PLLU_BASE_REG	0xc0
 #define CAR_PLLU_BASE_BYPASS		__BIT(31)
 #define CAR_PLLU_BASE_ENABLE		__BIT(30)
 #define CAR_PLLU_BASE_REF_DIS		__BIT(29)
 #define CAR_PLLU_BASE_LOCK		__BIT(27)
 #define CAR_PLLU_BASE_CLKENABLE_48M	__BIT(25)
 #define CAR_PLLU_BASE_OVERRIDE		__BIT(24)
 #define CAR_PLLU_BASE_CLKENABLE_ICUSB	__BIT(23)
 #define CAR_PLLU_BASE_CLKENABLE_HSIC	__BIT(22)
 #define CAR_PLLU_BASE_CLKENABLE_USB	__BIT(21)
 #define CAR_PLLU_BASE_VCO_FREQ		__BIT(20)
 #define CAR_PLLU_BASE_DIVN		__BITS(17,8)
 #define CAR_PLLU_BASE_DIVM		__BITS(4,0)
 #define CAR_PLLD_BASE_REG	0xd0
 #define CAR_PLLD_BASE_BYPASS		__BIT(31)
 #define CAR_PLLD_BASE_ENABLE		__BIT(30)
 #define CAR_PLLD_BASE_REF_DIS		__BIT(29)
 #define CAR_PLLD_BASE_LOCK		__BIT(27)
 #define CAR_PLLD_BASE_CLKENABLE_CSI	__BIT(26)
 #define CAR_PLLD_BASE_DSIA_CLK_SRC	__BIT(25)
 #define CAR_PLLD_BASE_CSI_CLK_SRC	__BIT(23)
 #define CAR_PLLD_BASE_DIVP		__BITS(22,20)
 #define CAR_PLLD_BASE_DIVN		__BITS(18,8)
 #define CAR_PLLD_BASE_DIVM		__BITS(4,0)
 #define CAR_PLLD_MISC_REG	0xdc
 #define CAR_PLLX_BASE_REG	0xe0
 #define CAR_PLLX_BASE_BYPASS		__BIT(31)
 #define CAR_PLLX_BASE_ENABLE		__BIT(30)
 #define CAR_PLLX_BASE_REF_DIS		__BIT(29)
 #define CAR_PLLX_BASE_LOCK		__BIT(27)
 #define CAR_PLLX_BASE_DIVP		__BITS(23,20)
 #define CAR_PLLX_BASE_DIVN		__BITS(15,8)
 #define CAR_PLLX_BASE_DIVM		__BITS(7,0)
 #define CAR_PLLX_MISC_REG	0xe4
 #define CAR_PLLX_MISC_FO_LP_DISABLE	__BIT(29)
 #define CAR_PLLX_MISC_FO_G_DISABLE	__BIT(28)
 #define CAR_PLLX_MISC_PTS		__BITS(23,22)
 #define CAR_PLLX_MISC_LOCK_ENABLE	__BIT(18)
 #define CAR_PLLE_BASE_REG	0xe8
 #define CAR_PLLE_BASE_ENABLE		__BIT(30)
 #define CAR_PLLE_BASE_LOCK_OVERRIDE	__BIT(29)
 #define CAR_PLLE_BASE_FDIV48		__BIT(28)
 #define CAR_PLLE_BASE_DIVP_CML		__BITS(27,24)
 #define CAR_PLLE_BASE_EXT_SETUP_23_16	__BITS(23,16)
 #define CAR_PLLE_BASE_DIVN		__BITS(15,8)
 #define CAR_PLLE_BASE_DIVM		__BITS(7,0)
 #define CAR_PLLE_MISC_REG	0xec
 #define CAR_PLLD2_BASE_REG	0x4b8
 #define CAR_PLLD2_BASE_BYPASS		__BIT(31)
 #define CAR_PLLD2_BASE_ENABLE		__BIT(30)
 #define CAR_PLLD2_BASE_REF_DIS		__BIT(29)
 #define CAR_PLLD2_BASE_FREQLOCK		__BIT(28)
 #define CAR_PLLD2_BASE_LOCK		__BIT(27)
 #define CAR_PLLD2_BASE_REF_SRC_SEL	__BITS(26,25)
 #define CAR_PLLD2_BASE_REF_SRC_SEL_PLL_D	0
 #define CAR_PLLD2_BASE_REF_SRC_SEL_PLL_D2	1
 #define CAR_PLLD2_BASE_LOCK_OVERRIDE	__BIT(24)
 #define CAR_PLLD2_BASE_PLDIV		__BITS(23,20)
 #define CAR_PLLD2_BASE_IDDQ		__BIT(19)
 #define CAR_PLLD2_BASE_PTS		__BIT(16)
 #define CAR_PLLD2_BASE_NDIV		__BITS(15,8)
 #define CAR_PLLD2_BASE_MDIV		__BITS(7,0)
 #define CAR_PLLD2_MISC_REG	0x4bc
 #define CAR_PLLD2_MISC_EN_FSTLCK	__BIT(31)
 #define CAR_PLLD2_MISC_LOCK_ENABLE	__BIT(30)
 #define CAR_PLLD2_MISC_MON_TEST_OUT	__BITS(29,27)
 #define CAR_PLLD2_MISC_KCP		__BITS(26,25)
 #define CAR_PLLD2_MISC_KVCO		__BIT(24)
 #define CAR_PLLD2_MISC_SETUP		__BITS(23,0)
 #define CAR_CLKSRC_I2C1_REG		0x124
 #define CAR_CLKSRC_I2C2_REG		0x198
 #define CAR_CLKSRC_I2C3_REG		0x1b8
 #define CAR_CLKSRC_I2C4_REG		0x3c4
 #define CAR_CLKSRC_I2C5_REG		0x128
 #define CAR_CLKSRC_I2C6_REG		0x65c
 #define CAR_CLKSRC_I2C_SRC		__BITS(31,29)
 #define CAR_CLKSRC_I2C_SRC_PLLP_OUT0	0
 #define CAR_CLKSRC_I2C_SRC_PLLC2_OUT0	1
 #define CAR_CLKSRC_I2C_SRC_PLLC_OUT0	2
 #define CAR_CLKSRC_I2C_SRC_PLLC3_OUT0	3
 #define CAR_CLKSRC_I2C_SRC_PLLM_OUT0	4
 #define CAR_CLKSRC_I2C_SRC_CLK_M	6
 #define CAR_CLKSRC_I2C_DIV		__BITS(15,0)
 #define CAR_CLKSRC_UARTA_REG		0x178
 #define CAR_CLKSRC_UARTB_REG		0x17c
 #define CAR_CLKSRC_UARTC_REG		0x1a0
 #define CAR_CLKSRC_UARTD_REG		0x1c0
 #define CAR_CLKSRC_UART_SRC		__BITS(31,29)
 #define CAR_CLKSRC_UART_SRC_PLLP_OUT0	0
 #define CAR_CLKSRC_UART_SRC_PLLC2_OUT0	1
 #define CAR_CLKSRC_UART_SRC_PLLC_OUT0	2
 #define CAR_CLKSRC_UART_SRC_PLLC3_OUT0	3
 #define CAR_CLKSRC_UART_SRC_PLLM_OUT0	4
 #define CAR_CLKSRC_UART_SRC_CLK_M	6
 #define CAR_CLKSRC_UART_DIV_ENB		__BIT(24)
 #define CAR_CLKSRC_UART_DIV		__BITS(15,0)
 #define CAR_CLKSRC_SDMMC1_REG		0x150
 #define CAR_CLKSRC_SDMMC2_REG		0x154
 #define CAR_CLKSRC_SDMMC4_REG		0x164
 #define CAR_CLKSRC_SDMMC3_REG		0x1bc
 #define CAR_CLKSRC_SDMMC_SRC		__BITS(31,29)
 #define CAR_CLKSRC_SDMMC_SRC_PLLP_OUT0	0
 #define CAR_CLKSRC_SDMMC_SRC_PLLC2_OUT0	1
 #define CAR_CLKSRC_SDMMC_SRC_PLLC_OUT0	2
 #define CAR_CLKSRC_SDMMC_SRC_PLLC3_OUT0	3
 #define CAR_CLKSRC_SDMMC_SRC_PLLM_OUT0	4
 #define CAR_CLKSRC_SDMMC_SRC_PLLE_OUT0	5
 #define CAR_CLKSRC_SDMMC_SRC_CLK_M	6
 #define CAR_CLKSRC_SDMMC_DIV		__BITS(7,0)
 #define CAR_CLKSRC_HDMI_REG		0x18c
 #define CAR_CLKSRC_HDMI_SRC		__BITS(31,29)
 #define CAR_CLKSRC_HDMI_SRC_PLLP_OUT0	0
 #define CAR_CLKSRC_HDMI_SRC_PLLM_OUT0	1
 #define CAR_CLKSRC_HDMI_SRC_PLLD_OUT0	2
 #define CAR_CLKSRC_HDMI_SRC_PLLA_OUT0	3
 #define CAR_CLKSRC_HDMI_SRC_PLLC_OUT0	4
 #define CAR_CLKSRC_HDMI_SRC_PLLD2_OUT0	5
 #define CAR_CLKSRC_HDMI_SRC_CLK_M	6
 #define CAR_CLKSRC_HDMI_DIV		__BITS(7,0)
 #define CAR_CLKSRC_DISP1_REG		0x138
 #define CAR_CLKSRC_DISP2_REG		0x13c
 #define CAR_CLKSRC_DISP_SRC		__BITS(31,29)
 #define CAR_CLKSRC_DISP_SRC_PLLP_OUT0	0
 #define CAR_CLKSRC_DISP_SRC_PLLM_OUT0	1
 #define CAR_CLKSRC_DISP_SRC_PLLD_OUT0	2
 #define CAR_CLKSRC_DISP_SRC_PLLA_OUT0	3
 #define CAR_CLKSRC_DISP_SRC_PLLC_OUT0	4
 #define CAR_CLKSRC_DISP_SRC_PLLD2_OUT0	5
 #define CAR_CLKSRC_DISP_SRC_CLK_M	6
 #define CAR_CLKSRC_HOST1X_REG		0x180
 #define CAR_CLKSRC_HOST1X_SRC		__BITS(31,29)
 #define CAR_CLKSRC_HOST1X_SRC_PLLM_OUT0		0
 #define CAR_CLKSRC_HOST1X_SRC_PLLC2_OUT0	1
 #define CAR_CLKSRC_HOST1X_SRC_PLLC_OUT0		2
 #define CAR_CLKSRC_HOST1X_SRC_PLLC3_OUT0	3
 #define CAR_CLKSRC_HOST1X_SRC_PLLP_OUT0		4
 #define CAR_CLKSRC_HOST1X_SRC_PLLA_OUT0		6
 #define CAR_CLKSRC_HOST1X_IDLE_DIVISOR	__BITS(15,8)
 #define CAR_CLKSRC_HOST1X_CLK_DIVISOR	__BITS(7,0)
 #define CAR_RST_DEV_L_SET_REG		0x300
 #define CAR_RST_DEV_L_CLR_REG		0x304
 #define CAR_RST_DEV_H_SET_REG		0x308
 #define CAR_RST_DEV_H_CLR_REG		0x30c
 #define CAR_RST_DEV_U_SET_REG		0x310
 #define CAR_RST_DEV_U_CLR_REG		0x314
 #define CAR_RST_DEV_V_SET_REG		0x430
 #define CAR_RST_DEV_V_CLR_REG		0x434
 #define CAR_RST_DEV_W_SET_REG		0x438
 #define CAR_RST_DEV_W_CLR_REG		0x43c
 #define CAR_RST_DEV_X_SET_REG		0x290
 #define CAR_RST_DEV_X_CLR_REG		0x294
 #define CAR_CLK_ENB_L_SET_REG		0x320
 #define CAR_CLK_ENB_L_CLR_REG		0x324
 #define CAR_CLK_ENB_H_SET_REG		0x328
 #define CAR_CLK_ENB_H_CLR_REG		0x32c
 #define CAR_CLK_ENB_U_SET_REG		0x330
 #define CAR_CLK_ENB_U_CLR_REG		0x334
 #define CAR_CLK_ENB_V_SET_REG		0x440
 #define CAR_CLK_ENB_V_CLR_REG		0x444
 #define CAR_CLK_ENB_W_SET_REG		0x448
 #define CAR_CLK_ENB_W_CLR_REG		0x44c
 #define CAR_CLK_ENB_X_SET_REG		0x284
 #define CAR_CLK_ENB_X_CLR_REG		0x288
 #define CAR_DEV_L_CACHE2		__BIT(31)
 #define CAR_DEV_L_I2S0			__BIT(30)
 #define CAR_DEV_L_VCP			__BIT(29)
 #define CAR_DEV_L_HOST1X		__BIT(28)
 #define CAR_DEV_L_DISP1			__BIT(27)
 #define CAR_DEV_L_DISP2			__BIT(26)
 #define CAR_DEV_L_ISP			__BIT(23)
 #define CAR_DEV_L_USBD			__BIT(22)
 #define CAR_DEV_L_VI			__BIT(20)
 #define CAR_DEV_L_I2S2			__BIT(18)
 #define CAR_DEV_L_PWM			__BIT(17)
 #define CAR_DEV_L_SDMMC4		__BIT(15)
 #define CAR_DEV_L_SDMMC1		__BIT(14)
 #define CAR_DEV_L_I2C1			__BIT(12)
 #define CAR_DEV_L_I2S1			__BIT(11)
 #define CAR_DEV_L_SPDIF			__BIT(10)
 #define CAR_DEV_L_SDMMC2		__BIT(9)
 #define CAR_DEV_L_GPIO			__BIT(8)
 #define CAR_DEV_L_UARTB			__BIT(7)
 #define CAR_DEV_L_UARTA			__BIT(6)
 #define CAR_DEV_L_TMR			__BIT(5
 #define CAR_DEV_L_RTC			__BIT(4)
 #define CAR_DEV_L_ISPB			__BIT(3)
 #define CAR_DEV_L_CPU			__BIT(0)
 #define CAR_DEV_U_XUSB_DEV		__BIT(31)
 #define CAR_DEV_U_DEV1_OUT		__BIT(30)
 #define CAR_DEV_U_DEV2_OUT		__BIT(29)
 #define CAR_DEV_U_SUS_OUT		__BIT(28)
 #define CAR_DEV_U_MSENC			__BIT(27)
 #define CAR_DEV_U_XUSB_HOST		__BIT(25)
 #define CAR_DEV_U_CRAM2			__BIT(24)
 #define CAR_DEV_U_IRAMD			__BIT(23)
 #define CAR_DEV_U_IRAMC			__BIT(22)
 #define CAR_DEV_U_IRAMB			__BIT(21)
 #define CAR_DEV_U_IRAMA			__BIT(20)
 #define CAR_DEV_U_TSEC			__BIT(19)
 #define CAR_DEV_U_DSIB			__BIT(18)
 #define CAR_DEV_U_I2C_SLOW		__BIT(17)
 #define CAR_DEV_U_DTV			__BIT(15)
 #define CAR_DEV_U_SOC_THERM		__BIT(14)
 #define CAR_DEV_U_TRACECLKIN		__BIT(13)
 #define CAR_DEV_U_AVPUCQ		__BIT(11)
 #define CAR_DEV_U_CSITE			__BIT(9)
 #define CAR_DEV_U_AFI			__BIT(8)
 #define CAR_DEV_U_OWR			__BIT(7)
 #define CAR_DEV_U_PCIE			__BIT(6)
 #define CAR_DEV_U_SDMMC3		__BIT(5)
 #define CAR_DEV_U_SPI4			__BIT(4)
 #define CAR_DEV_U_I2C3			__BIT(3)
 #define CAR_DEV_U_UARTD			__BIT(1)
 #define CAR_DEV_H_BSEV			__BIT(31)
 #define CAR_DEV_H_BSEA			__BIT(30)
 #define CAR_DEV_H_VDE			__BIT(29)
 #define CAR_DEV_H_USB3			__BIT(27)
 #define CAR_DEV_H_USB2			__BIT(26)
 #define CAR_DEV_H_EMC			__BIT(25)
 #define CAR_DEV_H_MIPI_CAL		__BIT(24)
 #define CAR_DEV_H_UARTC			__BIT(23)
 #define CAR_DEV_H_I2C2			__BIT(22)
 #define CAR_DEV_H_CSI			__BIT(20)
 #define CAR_DEV_H_HDMI			__BIT(19)
 #define CAR_DEV_H_HSI			__BIT(18)
 #define CAR_DEV_H_DSI			__BIT(16)
 #define CAR_DEV_H_I2C5			__BIT(15)
 #define CAR_DEV_H_SPI3			__BIT(14)
 #define CAR_DEV_H_SPI2			__BIT(12)
 #define CAR_DEV_H_JTAG2TBC		__BIT(11)
 #define CAR_DEV_H_SNOR			__BIT(10)
 #define CAR_DEV_H_SPI1			__BIT(9)
 #define CAR_DEV_H_KFUSE			__BIT(8)
 #define CAR_DEV_H_FUSE			__BIT(7)
 #define CAR_DEV_H_PMC			__BIT(6)
 #define CAR_DEV_H_STAT_MON		__BIT(5)
 #define CAR_DEV_H_KBC			__BIT(4)
 #define CAR_DEV_H_APBDMA		__BIT(2)
 #define CAR_DEV_H_AHBDMA		__BIT(1)
 #define CAR_DEV_H_MEM			__BIT(0)
 #define CAR_DEV_V_HDA			__BIT(29)
 #define CAR_DEV_V_SATA			__BIT(28)
 #define CAR_DEV_V_SATA_OOB		__BIT(27)
 #define CAR_DEV_V_ACTMON		__BIT(23)
 #define CAR_DEV_V_ATOMICS		__BIT(16)
 #define CAR_DEV_V_HDA2CODEC_2X		__BIT(15)
 #define CAR_DEV_V_DAM2			__BIT(14)
 #define CAR_DEV_V_DAM1			__BIT(13)
 #define CAR_DEV_V_DAM0			__BIT(12)
 #define CAR_DEV_V_APBIF			__BIT(11)
 #define CAR_DEV_V_AUDIO			__BIT(10)
 #define CAR_DEV_V_SPI6			__BIT(9)
 #define CAR_DEV_V_SPI5			__BIT(8)
 #define CAR_DEV_V_I2C4			__BIT(7)
 #define CAR_DEV_V_I2S4			__BIT(6)
 #define CAR_DEV_V_I2S3			__BIT(5)
 #define CAR_DEV_V_MSELECT		__BIT(3)
 #define CAR_DEV_V_CPULP			__BIT(1)
 #define CAR_DEV_V_CPUG			__BIT(0)
 #define CAR_DEV_W_XUSB_SS		__BIT(28)
 #define CAR_DEV_W_DVFS			__BIT(27)
 #define CAR_DEV_W_ADX0			__BIT(26)
 #define CAR_DEV_W_AMX0			__BIT(25)
 #define CAR_DEV_W_ENTROPY		__BIT(21)
 #define CAR_DEV_W_XUSB_PADCTL		__BIT(14)
 #define CAR_DEV_W_CEC			__BIT(8)
 #define CAR_DEV_W_SATACOLD		__BIT(1)
 #define CAR_DEV_W_HDA2HDMICODEC		__BIT(0)
 #define CAR_DEV_X_AMX1			__BIT(25)
 #define CAR_DEV_X_GPU			__BIT(24)
 #define CAR_DEV_X_SOR0			__BIT(22)
 #define CAR_DEV_X_DPAUX			__BIT(21)
 #define CAR_DEV_X_ADX1			__BIT(20)
 #define CAR_DEV_X_VIC			__BIT(18)
 #define CAR_DEV_X_CLK72MHZ		__BIT(17)
 #define CAR_DEV_X_HDMI_AUDIO		__BIT(16)
 #define CAR_DEV_X_EMC_DLL		__BIT(14)
 #define CAR_DEV_X_VIM2_CLK		__BIT(11)
 #define CAR_DEV_X_I2C6			__BIT(6)
 #define CAR_DEV_X_CAM_MCLK2		__BIT(5)
 #define CAR_DEV_X_CAM_MCLK		__BIT(4)
 #define CAR_DEV_X_SPARE			__BIT(0)
 #define CAR_CCLKG_BURST_POLICY_REG	0x368
 #define CAR_CCLKG_BURST_POLICY_CPU_STATE	__BITS(31,28)
 #define CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE			1
 #define CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN			2
 #define CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE __BITS(3,0)
 #define CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM		0
 #define CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ	8
 #define CAR_CLKSRC_HDA2CODEC_2X_REG	0x3e4
 #define CAR_CLKSRC_HDA2CODEC_2X_SRC	__BITS(31,29)
 #define CAR_CLKSRC_HDA2CODEC_2X_SRC_PLLP_OUT0	0
 #define CAR_CLKSRC_HDA2CODEC_2X_SRC_PLLC2_OUT0	1
 #define CAR_CLKSRC_HDA2CODEC_2X_SRC_PLLC_OUT0	2
 #define CAR_CLKSRC_HDA2CODEC_2X_SRC_PLLC3_OUT0	3
 #define CAR_CLKSRC_HDA2CODEC_2X_SRC_PLLM_OUT0	4
 #define CAR_CLKSRC_HDA2CODEC_2X_SRC_CLKM	6
 #define CAR_CLKSRC_HDA2CODEC_2X_DIV	__BITS(7,0)
 #define CAR_CLKSRC_SATA_OOB_REG		0x420
 #define CAR_CLKSRC_SATA_OOB_SRC		__BITS(31,29)
 #define CAR_CLKSRC_SATA_OOB_SRC_PLLP_OUT0	0
 #define CAR_CLKSRC_SATA_OOB_SRC_PLLC_OUT0	2
 #define CAR_CLKSRC_SATA_OOB_SRC_PLLM_OUT0	4
 #define CAR_CLKSRC_SATA_OOB_SRC_CLKM		6
 #define CAR_CLKSRC_SATA_OOB_DIV		__BITS(7,0)
 #define CAR_CLKSRC_SATA_REG		0x424
 #define CAR_CLKSRC_SATA_SRC		__BITS(31,29)
 #define CAR_CLKSRC_SATA_SRC_PLLP_OUT0		0
 #define CAR_CLKSRC_SATA_SRC_PLLC_OUT0		2
 #define CAR_CLKSRC_SATA_SRC_PLLM_OUT0		4
 #define CAR_CLKSRC_SATA_SRC_CLKM		6
 #define CAR_CLKSRC_SATA_AUX_CLK_ENB	__BIT(24)
 #define CAR_CLKSRC_SATA_DIV		__BITS(7,0)
 #define CAR_UTMIP_PLL_CFG0_REG		0x480
 #define CAR_UTMIP_PLL_CFG1_REG		0x484
 #define CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT	__BITS(31,27)
 #define CAR_UTMIP_PLL_CFG1_PLLU_POWERUP		__BIT(17)
 #define CAR_UTMIP_PLL_CFG1_PLLU_POWERDOWN	__BIT(16)
 #define CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERUP 	__BIT(15)
 #define CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN	__BIT(14)
 #define CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT	__BITS(11,0)
 #define CAR_UTMIP_PLL_CFG2_REG		0x488
 #define CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT	__BITS(23,18)
 #define CAR_UTMIP_PLL_CFG2_STABLE_COUNT		__BITS(17,6)
 #define CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERUP	__BIT(5)
 #define CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN	__BIT(4)
 #define CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERUP	__BIT(3)
 #define CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN	__BIT(2)
 #define CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERUP	__BIT(1)
 #define CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN	__BIT(0)
 #define CAR_PLLE_AUX_REG		0x48c
 #define CAR_PLLE_AUX_SS_SEQ_INCLUDE		__BIT(31)
 #define CAR_PLLE_AUX_REF_SEL_PLLREFE		__BIT(28)
 #define CAR_PLLE_AUX_SEQ_STATE			__BITS(27,26)
 #define CAR_PLLE_AUX_SEQ_START_STATE		__BIT(25)
 #define CAR_PLLE_AUX_SEQ_ENABLE			__BIT(24)
 #define CAR_PLLE_AUX_SS_DLY			__BITS(23,16)
 #define CAR_PLLE_AUX_LOCK_DLY			__BITS(15,8)
 #define CAR_PLLE_AUX_FAST_PT			__BIT(7)
 #define CAR_PLLE_AUX_SS_SWCTL			__BIT(6)
 #define CAR_PLLE_AUX_CONFIG_SWCTL		__BIT(5)
 #define CAR_PLLE_AUX_ENABLE_SWCTL		__BIT(4)
 #define CAR_PLLE_AUX_USE_LOCKDET		__BIT(3)
 #define CAR_PLLE_AUX_REF_SRC			__BIT(2)
 #define CAR_PLLE_AUX_CML1_OEN			__BIT(1)
 #define CAR_PLLE_AUX_CML0_OEN			__BIT(0)
 #define CAR_SATA_PLL_CFG0_REG		0x490
 #define CAR_SATA_PLL_CFG0_SEQ_STATE		__BITS(27,26)
 #define CAR_SATA_PLL_CFG0_SEQ_START_STATE	__BIT(25)
 #define CAR_SATA_PLL_CFG0_SEQ_ENABLE		__BIT(24)
 #define CAR_SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE __BIT(7)
 #define CAR_SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE __BIT(6)
 #define CAR_SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE	__BIT(5)
 #define CAR_SATA_PLL_CFG0_SEQ_IN_SWCTL		__BIT(4)
 #define CAR_SATA_PLL_CFG0_PADPLL_USE_LOCKDET	__BIT(2)
 #define CAR_SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE __BIT(1)
 #define CAR_SATA_PLL_CFG0_PADPLL_RESET_SWCTL	__BIT(0)
 #define CAR_SATA_PLL_CFG1_REG		0x494
 #define CAR_SATA_PLL_CFG1_LANE_IDDQ2_PADPLL_RESET_DLY __BITS(31,24)
 #define CAR_SATA_PLL_CFG1_PADPLL_IDDQ2LANE_SLUMBER_DLY __BITS(23,16)
 #define CAR_SATA_PLL_CFG1_PADPLL_PU_POST_DLY	__BITS(15,8)
 #define CAR_SATA_PLL_CFG1_LANE_IDDQ2_PADPLL_IDDQ_DLY __BITS(7,0)
 #define CAR_CLKSRC_HDMI_AUDIO_REG	0x668
 #define CAR_CLKSRC_HDMI_AUDIO_SRC	__BITS(31,29)
 #define CAR_CLKSRC_HDMI_AUDIO_SRC_PLLP_OUT0	0
 #define CAR_CLKSRC_HDMI_AUDIO_SRC_PLLC_OUT0	1
 #define CAR_CLKSRC_HDMI_AUDIO_SRC_PLLC2_OUT0	2
 #define CAR_CLKSRC_HDMI_AUDIO_SRC_CLKM		3
 #define CAR_CLKSRC_HDMI_AUDIO_DIV	__BITS(7,0)
 #endif /* _ARM_TEGRA_CARREG_H */

 @@ -1,181 +1,182 @@
-/* $NetBSD: tegra_var.h,v 1.24 2015/08/01 21:20:11 jmcneill Exp $ */
+/* $NetBSD: tegra_var.h,v 1.25 2015/10/17 21:16:09 jmcneill Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #ifndef _ARM_TEGRA_VAR_H
 #define _ARM_TEGRA_VAR_H
 #include <sys/types.h>
 #include <sys/bus.h>
 #include <sys/gpio.h>
 #include "opt_tegra.h"
 struct tegra_locators {
 	const char *loc_name;
 	bus_addr_t loc_offset;
 	bus_size_t loc_size;
 	int loc_port;
 	int loc_intr;
 #define TEGRAIO_INTR_DEFAULT	0
 };
 struct tegraio_attach_args {
 	struct tegra_locators tio_loc;
 	bus_space_tag_t tio_bst;
 	bus_space_tag_t tio_a4x_bst;
 	bus_space_handle_t tio_bsh;
 	bus_dma_tag_t tio_dmat;
 	bus_dma_tag_t tio_coherent_dmat;
 };
 struct tegrafb_attach_args {
 	bool tfb_console;
 	bus_dma_tag_t tfb_dmat;
 	bus_dmamap_t tfb_dmamap;
 	void *tfb_dmap;
 	u_int tfb_width;
 	u_int tfb_height;
 	u_int tfb_depth;
 	u_int tfb_stride;
 	device_t tfb_outputdev;
 };
 extern struct bus_space armv7_generic_bs_tag;
 extern struct bus_space armv7_generic_a4x_bs_tag;
 extern bus_space_handle_t tegra_host1x_bsh;
 extern bus_space_handle_t tegra_ppsb_bsh;
 extern bus_space_handle_t tegra_apb_bsh;
 extern bus_space_handle_t tegra_ahb_a2_bsh;
 extern struct arm32_bus_dma_tag tegra_dma_tag;
 extern struct arm32_bus_dma_tag tegra_coherent_dma_tag;
 #define CHIP_ID_TEGRA20		0x20
 #define CHIP_ID_TEGRA30		0x30
 #define CHIP_ID_TEGRA114	0x35
 #define CHIP_ID_TEGRA124	0x40
 #define CHIP_ID_TEGRA132	0x13
 u_int	tegra_chip_id(void);
 const char *tegra_chip_name(void);
 void	tegra_bootstrap(void);
 void	tegra_dma_bootstrap(psize_t);
 void	tegra_cpuinit(void);
 u_int	tegra_car_osc_rate(void);
 u_int	tegra_car_pllc_rate(void);
 u_int	tegra_car_plle_rate(void);
 u_int	tegra_car_pllx_rate(void);
 void	tegra_car_pllx_set_rate(u_int, u_int, u_int);
 u_int	tegra_car_pllu_rate(void);
 u_int	tegra_car_pllp0_rate(void);
 u_int	tegra_car_plld2_rate(void);
 u_int	tegra_car_uart_rate(u_int);
 u_int	tegra_car_periph_sdmmc_rate(u_int);
 int	tegra_car_periph_sdmmc_set_rate(u_int, u_int);
 int	tegra_car_periph_usb_enable(u_int);
 void	tegra_car_periph_hda_enable(void);
 void	tegra_car_periph_sata_enable(void);
 int	tegra_car_periph_i2c_enable(u_int, u_int);
 void	tegra_car_periph_cec_enable(void);
 void	tegra_car_utmip_init(void);
 void	tegra_car_utmip_enable(u_int);
 void	tegra_car_hdmi_enable(u_int);
 int	tegra_car_dc_enable(u_int);
 void	tegra_car_host1x_enable(void);
 void	tegra_car_wdt_enable(u_int, bool);
 void	tegra_car_gpu_enable(void);
 struct tegra_gpio_pin;
 struct tegra_gpio_pin *tegra_gpio_acquire(const char *, u_int);
 void	tegra_gpio_release(struct tegra_gpio_pin *);
 int	tegra_gpio_read(struct tegra_gpio_pin *);
 void	tegra_gpio_write(struct tegra_gpio_pin *, int);
 struct tegra_mpio_padctlgrp {
 	int	preemp;
 	int	hsm;
 	int	schmt;
 	int	drv_type;
 	int	drvdn;
 	int	drvup;
 	int	slwr;
 	int	slwf;
 };
 void	tegra_mpio_padctlgrp_read(u_int, struct tegra_mpio_padctlgrp *);
 void	tegra_mpio_padctlgrp_write(u_int, const struct tegra_mpio_padctlgrp *);
 void	tegra_mpio_pinmux_set_config(u_int, int, const char *);
 void	tegra_mpio_pinmux_set_io_reset(u_int, bool);
 void	tegra_mpio_pinmux_set_rcv_sel(u_int, bool);
 void	tegra_mpio_pinmux_get_config(u_int, int *, const char **);
 const char *tegra_mpio_pinmux_get_pm(u_int);
 bool	tegra_mpio_pinmux_get_io_reset(u_int);
 bool	tegra_mpio_pinmux_get_rcv_sel(u_int);
 void	tegra_pmc_reset(void);
 void	tegra_pmc_power(u_int, bool);
 void	tegra_pmc_remove_clamping(u_int);
 void	tegra_pmc_hdmi_enable(void);
 void	tegra_i2c_dvc_write(uint8_t, uint32_t, size_t);
 psize_t	tegra_mc_memsize(void);
 void	tegra_xusbpad_sata_enable(void);
 struct videomode;
 int	tegra_dc_port(device_t);
 int	tegra_dc_enable(device_t, device_t, const struct videomode *,
 			const uint8_t *);
 void	tegra_dc_hdmi_start(device_t);
 #define TEGRA_CPUFREQ_MAX	16
 struct tegra_cpufreq_func {
 	u_int (*set_rate)(u_int);
 	u_int (*get_rate)(void);
 	size_t (*get_available)(u_int *, size_t);
 };
 void	tegra_cpufreq_register(const struct tegra_cpufreq_func *);
 void	tegra_cpufreq_init(void);
 #if defined(SOC_TEGRA124)
 void	tegra124_cpuinit(void);
 void	tegra124_mpinit(void);
 #endif
 static void inline
 tegra_reg_set_clear(bus_space_tag_t bst, bus_space_handle_t bsh,
     bus_size_t o, uint32_t set_mask, uint32_t clr_mask)
+{
 	const uint32_t old = bus_space_read_4(bst, bsh, o);
 	const uint32_t new = set_mask | (old & ~clr_mask);
 	if (old != new) {
 		bus_space_write_4(bst, bsh, o, new);
+	}
+}
 #endif /* _ARM_TEGRA_VAR_H */