Fri Nov 6 00:40:02 2015 UTC ()
Pull up following revision(s) (requested by nat in ticket #984):
	sys/arch/x86/x86/cpu.c: revision 1.116
Don't disable/re-enable interrupts if they are already disabled.
Addresses PR 48196.
This commit was improved and approved by christos@


(riz)
diff -r1.111.2.1 -r1.111.2.2 src/sys/arch/x86/x86/cpu.c
cvs diff -r1.111.2.1 -r1.111.2.2 src/sys/arch/x86/x86/cpu.c (expand / switch to unified diff)

--- src/sys/arch/x86/x86/cpu.c 2015/01/12 21:06:41 1.111.2.1
+++ src/sys/arch/x86/x86/cpu.c 2015/11/06 00:40:02 1.111.2.2
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: cpu.c,v 1.111.2.1 2015/01/12 21:06:41 snj Exp $ */ 1/* $NetBSD: cpu.c,v 1.111.2.2 2015/11/06 00:40:02 riz Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2000-2012 NetBSD Foundation, Inc. 4 * Copyright (c) 2000-2012 NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Bill Sommerfeld of RedBack Networks Inc, and by Andrew Doran. 8 * by Bill Sommerfeld of RedBack Networks Inc, and by Andrew Doran.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -52,27 +52,27 @@ @@ -52,27 +52,27 @@
52 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 52 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
53 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 53 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
54 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 54 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE
55 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 55 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
56 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 56 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
57 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 57 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
59 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 59 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
60 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 60 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
61 * SUCH DAMAGE. 61 * SUCH DAMAGE.
62 */ 62 */
63 63
64#include <sys/cdefs.h> 64#include <sys/cdefs.h>
65__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.111.2.1 2015/01/12 21:06:41 snj Exp $"); 65__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.111.2.2 2015/11/06 00:40:02 riz Exp $");
66 66
67#include "opt_ddb.h" 67#include "opt_ddb.h"
68#include "opt_mpbios.h" /* for MPDEBUG */ 68#include "opt_mpbios.h" /* for MPDEBUG */
69#include "opt_mtrr.h" 69#include "opt_mtrr.h"
70#include "opt_multiprocessor.h" 70#include "opt_multiprocessor.h"
71 71
72#include "lapic.h" 72#include "lapic.h"
73#include "ioapic.h" 73#include "ioapic.h"
74 74
75#include <sys/param.h> 75#include <sys/param.h>
76#include <sys/proc.h> 76#include <sys/proc.h>
77#include <sys/systm.h> 77#include <sys/systm.h>
78#include <sys/device.h> 78#include <sys/device.h>
@@ -1268,39 +1268,45 @@ x86_cpu_idle_halt(void) @@ -1268,39 +1268,45 @@ x86_cpu_idle_halt(void)
1268 } else { 1268 } else {
1269 x86_enable_intr(); 1269 x86_enable_intr();
1270 } 1270 }
1271} 1271}
1272 1272
1273/* 1273/*
1274 * Loads pmap for the current CPU. 1274 * Loads pmap for the current CPU.
1275 */ 1275 */
1276void 1276void
1277cpu_load_pmap(struct pmap *pmap, struct pmap *oldpmap) 1277cpu_load_pmap(struct pmap *pmap, struct pmap *oldpmap)
1278{ 1278{
1279#ifdef PAE 1279#ifdef PAE
1280 struct cpu_info *ci = curcpu(); 1280 struct cpu_info *ci = curcpu();
 1281 bool interrupts_enabled;
1281 pd_entry_t *l3_pd = ci->ci_pae_l3_pdir; 1282 pd_entry_t *l3_pd = ci->ci_pae_l3_pdir;
1282 int i; 1283 int i;
1283 1284
1284 /* 1285 /*
1285 * disable interrupts to block TLB shootdowns, which can reload cr3. 1286 * disable interrupts to block TLB shootdowns, which can reload cr3.
1286 * while this doesn't block NMIs, it's probably ok as NMIs unlikely 1287 * while this doesn't block NMIs, it's probably ok as NMIs unlikely
1287 * reload cr3. 1288 * reload cr3.
1288 */ 1289 */
1289 x86_disable_intr(); 1290 interrupts_enabled = (x86_read_flags() & PSL_I) != 0;
 1291 if (interrupts_enabled)
 1292 x86_disable_intr();
 1293
1290 for (i = 0 ; i < PDP_SIZE; i++) { 1294 for (i = 0 ; i < PDP_SIZE; i++) {
1291 l3_pd[i] = pmap->pm_pdirpa[i] | PG_V; 1295 l3_pd[i] = pmap->pm_pdirpa[i] | PG_V;
1292 } 1296 }
1293 x86_enable_intr(); 1297
 1298 if (interrupts_enabled)
 1299 x86_enable_intr();
1294 tlbflush(); 1300 tlbflush();
1295#else /* PAE */ 1301#else /* PAE */
1296 lcr3(pmap_pdirpa(pmap, 0)); 1302 lcr3(pmap_pdirpa(pmap, 0));
1297#endif /* PAE */ 1303#endif /* PAE */
1298} 1304}
1299 1305
1300/* 1306/*
1301 * Notify all other cpus to halt. 1307 * Notify all other cpus to halt.
1302 */ 1308 */
1303 1309
1304void 1310void
1305cpu_broadcast_halt(void) 1311cpu_broadcast_halt(void)
1306{ 1312{