Fri Nov 6 14:22:17 2015 UTC ()
Always use pci_intr_alloc(9)/pci_intr_release(9).


(nonaka)
diff -r1.38 -r1.39 src/sys/dev/pci/if_iwm.c
diff -r1.8 -r1.9 src/sys/dev/pci/if_iwmvar.h
diff -r1.1 -r1.2 src/sys/dev/pci/if_rtwn.c
diff -r1.1 -r1.2 src/sys/dev/pci/if_rtwnreg.h
diff -r1.4 -r1.5 src/sys/dev/pci/rtsx_pci.c
cvs diff -r1.38 -r1.39 src/sys/dev/pci/if_iwm.c (switch to unified diff)

--- src/sys/dev/pci/if_iwm.c 2015/10/14 02:16:51 1.38
+++ src/sys/dev/pci/if_iwm.c 2015/11/06 14:22:17 1.39
@@ -1,1107 +1,1107 @@ @@ -1,1107 +1,1107 @@
1/* $NetBSD: if_iwm.c,v 1.38 2015/10/14 02:16:51 ozaki-r Exp $ */ 1/* $NetBSD: if_iwm.c,v 1.39 2015/11/06 14:22:17 nonaka Exp $ */
2/* OpenBSD: if_iwm.c,v 1.41 2015/05/22 06:50:54 kettenis Exp */ 2/* OpenBSD: if_iwm.c,v 1.41 2015/05/22 06:50:54 kettenis Exp */
3 3
4/* 4/*
5 * Copyright (c) 2014 genua mbh <info@genua.de> 5 * Copyright (c) 2014 genua mbh <info@genua.de>
6 * Copyright (c) 2014 Fixup Software Ltd. 6 * Copyright (c) 2014 Fixup Software Ltd.
7 * 7 *
8 * Permission to use, copy, modify, and distribute this software for any 8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above 9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies. 10 * copyright notice and this permission notice appear in all copies.
11 * 11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 */ 19 */
20 20
21/*- 21/*-
22 * Based on BSD-licensed source modules in the Linux iwlwifi driver, 22 * Based on BSD-licensed source modules in the Linux iwlwifi driver,
23 * which were used as the reference documentation for this implementation. 23 * which were used as the reference documentation for this implementation.
24 * 24 *
25 * Driver version we are currently based off of is 25 * Driver version we are currently based off of is
26 * Linux 3.14.3 (tag id a2df521e42b1d9a23f620ac79dbfe8655a8391dd) 26 * Linux 3.14.3 (tag id a2df521e42b1d9a23f620ac79dbfe8655a8391dd)
27 * 27 *
28 *********************************************************************** 28 ***********************************************************************
29 * 29 *
30 * This file is provided under a dual BSD/GPLv2 license. When using or 30 * This file is provided under a dual BSD/GPLv2 license. When using or
31 * redistributing this file, you may do so under either license. 31 * redistributing this file, you may do so under either license.
32 * 32 *
33 * GPL LICENSE SUMMARY 33 * GPL LICENSE SUMMARY
34 * 34 *
35 * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved. 35 * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved.
36 * 36 *
37 * This program is free software; you can redistribute it and/or modify 37 * This program is free software; you can redistribute it and/or modify
38 * it under the terms of version 2 of the GNU General Public License as 38 * it under the terms of version 2 of the GNU General Public License as
39 * published by the Free Software Foundation. 39 * published by the Free Software Foundation.
40 * 40 *
41 * This program is distributed in the hope that it will be useful, but 41 * This program is distributed in the hope that it will be useful, but
42 * WITHOUT ANY WARRANTY; without even the implied warranty of 42 * WITHOUT ANY WARRANTY; without even the implied warranty of
43 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 43 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
44 * General Public License for more details. 44 * General Public License for more details.
45 * 45 *
46 * You should have received a copy of the GNU General Public License 46 * You should have received a copy of the GNU General Public License
47 * along with this program; if not, write to the Free Software 47 * along with this program; if not, write to the Free Software
48 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 48 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
49 * USA 49 * USA
50 * 50 *
51 * The full GNU General Public License is included in this distribution 51 * The full GNU General Public License is included in this distribution
52 * in the file called COPYING. 52 * in the file called COPYING.
53 * 53 *
54 * Contact Information: 54 * Contact Information:
55 * Intel Linux Wireless <ilw@linux.intel.com> 55 * Intel Linux Wireless <ilw@linux.intel.com>
56 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 56 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
57 * 57 *
58 * 58 *
59 * BSD LICENSE 59 * BSD LICENSE
60 * 60 *
61 * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved. 61 * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved.
62 * All rights reserved. 62 * All rights reserved.
63 * 63 *
64 * Redistribution and use in source and binary forms, with or without 64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions 65 * modification, are permitted provided that the following conditions
66 * are met: 66 * are met:
67 * 67 *
68 * * Redistributions of source code must retain the above copyright 68 * * Redistributions of source code must retain the above copyright
69 * notice, this list of conditions and the following disclaimer. 69 * notice, this list of conditions and the following disclaimer.
70 * * Redistributions in binary form must reproduce the above copyright 70 * * Redistributions in binary form must reproduce the above copyright
71 * notice, this list of conditions and the following disclaimer in 71 * notice, this list of conditions and the following disclaimer in
72 * the documentation and/or other materials provided with the 72 * the documentation and/or other materials provided with the
73 * distribution. 73 * distribution.
74 * * Neither the name Intel Corporation nor the names of its 74 * * Neither the name Intel Corporation nor the names of its
75 * contributors may be used to endorse or promote products derived 75 * contributors may be used to endorse or promote products derived
76 * from this software without specific prior written permission. 76 * from this software without specific prior written permission.
77 * 77 *
78 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 78 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
79 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 79 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
80 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 80 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
81 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 81 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
82 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 82 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
83 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 83 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
84 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 84 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
85 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 85 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
86 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 86 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
87 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 87 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
88 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 88 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
89 */ 89 */
90 90
91/*- 91/*-
92 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 92 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr>
93 * 93 *
94 * Permission to use, copy, modify, and distribute this software for any 94 * Permission to use, copy, modify, and distribute this software for any
95 * purpose with or without fee is hereby granted, provided that the above 95 * purpose with or without fee is hereby granted, provided that the above
96 * copyright notice and this permission notice appear in all copies. 96 * copyright notice and this permission notice appear in all copies.
97 * 97 *
98 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 98 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
99 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 99 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
100 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 100 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
101 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 101 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
102 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 102 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
103 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 103 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
104 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 104 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
105 */ 105 */
106 106
107#include <sys/cdefs.h> 107#include <sys/cdefs.h>
108__KERNEL_RCSID(0, "$NetBSD: if_iwm.c,v 1.38 2015/10/14 02:16:51 ozaki-r Exp $"); 108__KERNEL_RCSID(0, "$NetBSD: if_iwm.c,v 1.39 2015/11/06 14:22:17 nonaka Exp $");
109 109
110#include <sys/param.h> 110#include <sys/param.h>
111#include <sys/conf.h> 111#include <sys/conf.h>
112#include <sys/kernel.h> 112#include <sys/kernel.h>
113#include <sys/kmem.h> 113#include <sys/kmem.h>
114#include <sys/mbuf.h> 114#include <sys/mbuf.h>
115#include <sys/mutex.h> 115#include <sys/mutex.h>
116#include <sys/proc.h> 116#include <sys/proc.h>
117#include <sys/socket.h> 117#include <sys/socket.h>
118#include <sys/sockio.h> 118#include <sys/sockio.h>
119#include <sys/sysctl.h> 119#include <sys/sysctl.h>
120#include <sys/systm.h> 120#include <sys/systm.h>
121 121
122#include <sys/cpu.h> 122#include <sys/cpu.h>
123#include <sys/bus.h> 123#include <sys/bus.h>
124#include <sys/workqueue.h> 124#include <sys/workqueue.h>
125#include <machine/endian.h> 125#include <machine/endian.h>
126#include <machine/intr.h> 126#include <machine/intr.h>
127 127
128#include <dev/pci/pcireg.h> 128#include <dev/pci/pcireg.h>
129#include <dev/pci/pcivar.h> 129#include <dev/pci/pcivar.h>
130#include <dev/pci/pcidevs.h> 130#include <dev/pci/pcidevs.h>
131#include <dev/firmload.h> 131#include <dev/firmload.h>
132 132
133#include <net/bpf.h> 133#include <net/bpf.h>
134#include <net/if.h> 134#include <net/if.h>
135#include <net/if_arp.h> 135#include <net/if_arp.h>
136#include <net/if_dl.h> 136#include <net/if_dl.h>
137#include <net/if_media.h> 137#include <net/if_media.h>
138#include <net/if_types.h> 138#include <net/if_types.h>
139#include <net/if_ether.h> 139#include <net/if_ether.h>
140 140
141#include <netinet/in.h> 141#include <netinet/in.h>
142#include <netinet/in_systm.h> 142#include <netinet/in_systm.h>
143#include <netinet/ip.h> 143#include <netinet/ip.h>
144 144
145#include <net80211/ieee80211_var.h> 145#include <net80211/ieee80211_var.h>
146#include <net80211/ieee80211_amrr.h> 146#include <net80211/ieee80211_amrr.h>
147#include <net80211/ieee80211_radiotap.h> 147#include <net80211/ieee80211_radiotap.h>
148 148
149#define DEVNAME(_s) device_xname((_s)->sc_dev) 149#define DEVNAME(_s) device_xname((_s)->sc_dev)
150#define IC2IFP(_ic_) ((_ic_)->ic_ifp) 150#define IC2IFP(_ic_) ((_ic_)->ic_ifp)
151 151
152#define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_))) 152#define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_)))
153#define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_))) 153#define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_)))
154 154
155#ifdef IWM_DEBUG 155#ifdef IWM_DEBUG
156#define DPRINTF(x) do { if (iwm_debug > 0) printf x; } while (0) 156#define DPRINTF(x) do { if (iwm_debug > 0) printf x; } while (0)
157#define DPRINTFN(n, x) do { if (iwm_debug >= (n)) printf x; } while (0) 157#define DPRINTFN(n, x) do { if (iwm_debug >= (n)) printf x; } while (0)
158int iwm_debug = 0; 158int iwm_debug = 0;
159#else 159#else
160#define DPRINTF(x) do { ; } while (0) 160#define DPRINTF(x) do { ; } while (0)
161#define DPRINTFN(n, x) do { ; } while (0) 161#define DPRINTFN(n, x) do { ; } while (0)
162#endif 162#endif
163 163
164#include <dev/pci/if_iwmreg.h> 164#include <dev/pci/if_iwmreg.h>
165#include <dev/pci/if_iwmvar.h> 165#include <dev/pci/if_iwmvar.h>
166 166
167static const uint8_t iwm_nvm_channels[] = { 167static const uint8_t iwm_nvm_channels[] = {
168 /* 2.4 GHz */ 168 /* 2.4 GHz */
169 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 169 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
170 /* 5 GHz */ 170 /* 5 GHz */
171 36, 40, 44 , 48, 52, 56, 60, 64, 171 36, 40, 44 , 48, 52, 56, 60, 64,
172 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 172 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
173 149, 153, 157, 161, 165 173 149, 153, 157, 161, 165
174}; 174};
175#define IWM_NUM_2GHZ_CHANNELS 14 175#define IWM_NUM_2GHZ_CHANNELS 14
176 176
177static const struct iwm_rate { 177static const struct iwm_rate {
178 uint8_t rate; 178 uint8_t rate;
179 uint8_t plcp; 179 uint8_t plcp;
180} iwm_rates[] = { 180} iwm_rates[] = {
181 { 2, IWM_RATE_1M_PLCP }, 181 { 2, IWM_RATE_1M_PLCP },
182 { 4, IWM_RATE_2M_PLCP }, 182 { 4, IWM_RATE_2M_PLCP },
183 { 11, IWM_RATE_5M_PLCP }, 183 { 11, IWM_RATE_5M_PLCP },
184 { 22, IWM_RATE_11M_PLCP }, 184 { 22, IWM_RATE_11M_PLCP },
185 { 12, IWM_RATE_6M_PLCP }, 185 { 12, IWM_RATE_6M_PLCP },
186 { 18, IWM_RATE_9M_PLCP }, 186 { 18, IWM_RATE_9M_PLCP },
187 { 24, IWM_RATE_12M_PLCP }, 187 { 24, IWM_RATE_12M_PLCP },
188 { 36, IWM_RATE_18M_PLCP }, 188 { 36, IWM_RATE_18M_PLCP },
189 { 48, IWM_RATE_24M_PLCP }, 189 { 48, IWM_RATE_24M_PLCP },
190 { 72, IWM_RATE_36M_PLCP }, 190 { 72, IWM_RATE_36M_PLCP },
191 { 96, IWM_RATE_48M_PLCP }, 191 { 96, IWM_RATE_48M_PLCP },
192 { 108, IWM_RATE_54M_PLCP }, 192 { 108, IWM_RATE_54M_PLCP },
193}; 193};
194#define IWM_RIDX_CCK 0 194#define IWM_RIDX_CCK 0
195#define IWM_RIDX_OFDM 4 195#define IWM_RIDX_OFDM 4
196#define IWM_RIDX_MAX (__arraycount(iwm_rates)-1) 196#define IWM_RIDX_MAX (__arraycount(iwm_rates)-1)
197#define IWM_RIDX_IS_CCK(_i_) ((_i_) < IWM_RIDX_OFDM) 197#define IWM_RIDX_IS_CCK(_i_) ((_i_) < IWM_RIDX_OFDM)
198#define IWM_RIDX_IS_OFDM(_i_) ((_i_) >= IWM_RIDX_OFDM) 198#define IWM_RIDX_IS_OFDM(_i_) ((_i_) >= IWM_RIDX_OFDM)
199 199
200struct iwm_newstate_state { 200struct iwm_newstate_state {
201 struct work ns_wk; 201 struct work ns_wk;
202 enum ieee80211_state ns_nstate; 202 enum ieee80211_state ns_nstate;
203 int ns_arg; 203 int ns_arg;
204 int ns_generation; 204 int ns_generation;
205}; 205};
206 206
207static int iwm_store_cscheme(struct iwm_softc *, uint8_t *, size_t); 207static int iwm_store_cscheme(struct iwm_softc *, uint8_t *, size_t);
208static int iwm_firmware_store_section(struct iwm_softc *, 208static int iwm_firmware_store_section(struct iwm_softc *,
209 enum iwm_ucode_type, uint8_t *, size_t); 209 enum iwm_ucode_type, uint8_t *, size_t);
210static int iwm_set_default_calib(struct iwm_softc *, const void *); 210static int iwm_set_default_calib(struct iwm_softc *, const void *);
211static int iwm_read_firmware(struct iwm_softc *); 211static int iwm_read_firmware(struct iwm_softc *);
212static uint32_t iwm_read_prph(struct iwm_softc *, uint32_t); 212static uint32_t iwm_read_prph(struct iwm_softc *, uint32_t);
213static void iwm_write_prph(struct iwm_softc *, uint32_t, uint32_t); 213static void iwm_write_prph(struct iwm_softc *, uint32_t, uint32_t);
214#ifdef IWM_DEBUG 214#ifdef IWM_DEBUG
215static int iwm_read_mem(struct iwm_softc *, uint32_t, void *, int); 215static int iwm_read_mem(struct iwm_softc *, uint32_t, void *, int);
216#endif 216#endif
217static int iwm_write_mem(struct iwm_softc *, uint32_t, const void *, int); 217static int iwm_write_mem(struct iwm_softc *, uint32_t, const void *, int);
218static int iwm_write_mem32(struct iwm_softc *, uint32_t, uint32_t); 218static int iwm_write_mem32(struct iwm_softc *, uint32_t, uint32_t);
219static int iwm_poll_bit(struct iwm_softc *, int, uint32_t, uint32_t, int); 219static int iwm_poll_bit(struct iwm_softc *, int, uint32_t, uint32_t, int);
220static int iwm_nic_lock(struct iwm_softc *); 220static int iwm_nic_lock(struct iwm_softc *);
221static void iwm_nic_unlock(struct iwm_softc *); 221static void iwm_nic_unlock(struct iwm_softc *);
222static void iwm_set_bits_mask_prph(struct iwm_softc *, uint32_t, uint32_t, 222static void iwm_set_bits_mask_prph(struct iwm_softc *, uint32_t, uint32_t,
223 uint32_t); 223 uint32_t);
224static void iwm_set_bits_prph(struct iwm_softc *, uint32_t, uint32_t); 224static void iwm_set_bits_prph(struct iwm_softc *, uint32_t, uint32_t);
225static void iwm_clear_bits_prph(struct iwm_softc *, uint32_t, uint32_t); 225static void iwm_clear_bits_prph(struct iwm_softc *, uint32_t, uint32_t);
226static int iwm_dma_contig_alloc(bus_dma_tag_t, struct iwm_dma_info *, 226static int iwm_dma_contig_alloc(bus_dma_tag_t, struct iwm_dma_info *,
227 bus_size_t, bus_size_t); 227 bus_size_t, bus_size_t);
228static void iwm_dma_contig_free(struct iwm_dma_info *); 228static void iwm_dma_contig_free(struct iwm_dma_info *);
229static int iwm_alloc_fwmem(struct iwm_softc *); 229static int iwm_alloc_fwmem(struct iwm_softc *);
230static void iwm_free_fwmem(struct iwm_softc *); 230static void iwm_free_fwmem(struct iwm_softc *);
231static int iwm_alloc_sched(struct iwm_softc *); 231static int iwm_alloc_sched(struct iwm_softc *);
232static void iwm_free_sched(struct iwm_softc *); 232static void iwm_free_sched(struct iwm_softc *);
233static int iwm_alloc_kw(struct iwm_softc *); 233static int iwm_alloc_kw(struct iwm_softc *);
234static void iwm_free_kw(struct iwm_softc *); 234static void iwm_free_kw(struct iwm_softc *);
235static int iwm_alloc_ict(struct iwm_softc *); 235static int iwm_alloc_ict(struct iwm_softc *);
236static void iwm_free_ict(struct iwm_softc *); 236static void iwm_free_ict(struct iwm_softc *);
237static int iwm_alloc_rx_ring(struct iwm_softc *, struct iwm_rx_ring *); 237static int iwm_alloc_rx_ring(struct iwm_softc *, struct iwm_rx_ring *);
238static void iwm_reset_rx_ring(struct iwm_softc *, struct iwm_rx_ring *); 238static void iwm_reset_rx_ring(struct iwm_softc *, struct iwm_rx_ring *);
239static void iwm_free_rx_ring(struct iwm_softc *, struct iwm_rx_ring *); 239static void iwm_free_rx_ring(struct iwm_softc *, struct iwm_rx_ring *);
240static int iwm_alloc_tx_ring(struct iwm_softc *, struct iwm_tx_ring *, 240static int iwm_alloc_tx_ring(struct iwm_softc *, struct iwm_tx_ring *,
241 int); 241 int);
242static void iwm_reset_tx_ring(struct iwm_softc *, struct iwm_tx_ring *); 242static void iwm_reset_tx_ring(struct iwm_softc *, struct iwm_tx_ring *);
243static void iwm_free_tx_ring(struct iwm_softc *, struct iwm_tx_ring *); 243static void iwm_free_tx_ring(struct iwm_softc *, struct iwm_tx_ring *);
244static void iwm_enable_rfkill_int(struct iwm_softc *); 244static void iwm_enable_rfkill_int(struct iwm_softc *);
245static int iwm_check_rfkill(struct iwm_softc *); 245static int iwm_check_rfkill(struct iwm_softc *);
246static void iwm_enable_interrupts(struct iwm_softc *); 246static void iwm_enable_interrupts(struct iwm_softc *);
247static void iwm_restore_interrupts(struct iwm_softc *); 247static void iwm_restore_interrupts(struct iwm_softc *);
248static void iwm_disable_interrupts(struct iwm_softc *); 248static void iwm_disable_interrupts(struct iwm_softc *);
249static void iwm_ict_reset(struct iwm_softc *); 249static void iwm_ict_reset(struct iwm_softc *);
250static int iwm_set_hw_ready(struct iwm_softc *); 250static int iwm_set_hw_ready(struct iwm_softc *);
251static int iwm_prepare_card_hw(struct iwm_softc *); 251static int iwm_prepare_card_hw(struct iwm_softc *);
252static void iwm_apm_config(struct iwm_softc *); 252static void iwm_apm_config(struct iwm_softc *);
253static int iwm_apm_init(struct iwm_softc *); 253static int iwm_apm_init(struct iwm_softc *);
254static void iwm_apm_stop(struct iwm_softc *); 254static void iwm_apm_stop(struct iwm_softc *);
255static int iwm_allow_mcast(struct iwm_softc *); 255static int iwm_allow_mcast(struct iwm_softc *);
256static int iwm_start_hw(struct iwm_softc *); 256static int iwm_start_hw(struct iwm_softc *);
257static void iwm_stop_device(struct iwm_softc *); 257static void iwm_stop_device(struct iwm_softc *);
258static void iwm_set_pwr(struct iwm_softc *); 258static void iwm_set_pwr(struct iwm_softc *);
259static void iwm_mvm_nic_config(struct iwm_softc *); 259static void iwm_mvm_nic_config(struct iwm_softc *);
260static int iwm_nic_rx_init(struct iwm_softc *); 260static int iwm_nic_rx_init(struct iwm_softc *);
261static int iwm_nic_tx_init(struct iwm_softc *); 261static int iwm_nic_tx_init(struct iwm_softc *);
262static int iwm_nic_init(struct iwm_softc *); 262static int iwm_nic_init(struct iwm_softc *);
263static void iwm_enable_txq(struct iwm_softc *, int, int); 263static void iwm_enable_txq(struct iwm_softc *, int, int);
264static int iwm_post_alive(struct iwm_softc *); 264static int iwm_post_alive(struct iwm_softc *);
265static int iwm_is_valid_channel(uint16_t); 265static int iwm_is_valid_channel(uint16_t);
266static uint8_t iwm_ch_id_to_ch_index(uint16_t); 266static uint8_t iwm_ch_id_to_ch_index(uint16_t);
267static uint16_t iwm_channel_id_to_papd(uint16_t); 267static uint16_t iwm_channel_id_to_papd(uint16_t);
268static uint16_t iwm_channel_id_to_txp(struct iwm_softc *, uint16_t); 268static uint16_t iwm_channel_id_to_txp(struct iwm_softc *, uint16_t);
269static int iwm_phy_db_get_section_data(struct iwm_softc *, uint32_t, 269static int iwm_phy_db_get_section_data(struct iwm_softc *, uint32_t,
270 uint8_t **, uint16_t *, uint16_t); 270 uint8_t **, uint16_t *, uint16_t);
271static int iwm_send_phy_db_cmd(struct iwm_softc *, uint16_t, uint16_t, 271static int iwm_send_phy_db_cmd(struct iwm_softc *, uint16_t, uint16_t,
272 void *); 272 void *);
273static int iwm_send_phy_db_data(struct iwm_softc *); 273static int iwm_send_phy_db_data(struct iwm_softc *);
274static int iwm_send_phy_db_data(struct iwm_softc *); 274static int iwm_send_phy_db_data(struct iwm_softc *);
275static void iwm_mvm_te_v2_to_v1(const struct iwm_time_event_cmd_v2 *, 275static void iwm_mvm_te_v2_to_v1(const struct iwm_time_event_cmd_v2 *,
276 struct iwm_time_event_cmd_v1 *); 276 struct iwm_time_event_cmd_v1 *);
277static int iwm_mvm_send_time_event_cmd(struct iwm_softc *, 277static int iwm_mvm_send_time_event_cmd(struct iwm_softc *,
278 const struct iwm_time_event_cmd_v2 *); 278 const struct iwm_time_event_cmd_v2 *);
279static int iwm_mvm_time_event_send_add(struct iwm_softc *, 279static int iwm_mvm_time_event_send_add(struct iwm_softc *,
280 struct iwm_node *, void *, struct iwm_time_event_cmd_v2 *); 280 struct iwm_node *, void *, struct iwm_time_event_cmd_v2 *);
281static void iwm_mvm_protect_session(struct iwm_softc *, struct iwm_node *, 281static void iwm_mvm_protect_session(struct iwm_softc *, struct iwm_node *,
282 uint32_t, uint32_t, uint32_t); 282 uint32_t, uint32_t, uint32_t);
283static int iwm_nvm_read_chunk(struct iwm_softc *, uint16_t, uint16_t, 283static int iwm_nvm_read_chunk(struct iwm_softc *, uint16_t, uint16_t,
284 uint16_t, uint8_t *, uint16_t *); 284 uint16_t, uint8_t *, uint16_t *);
285static int iwm_nvm_read_section(struct iwm_softc *, uint16_t, uint8_t *, 285static int iwm_nvm_read_section(struct iwm_softc *, uint16_t, uint8_t *,
286 uint16_t *); 286 uint16_t *);
287static void iwm_init_channel_map(struct iwm_softc *, 287static void iwm_init_channel_map(struct iwm_softc *,
288 const uint16_t * const); 288 const uint16_t * const);
289static int iwm_parse_nvm_data(struct iwm_softc *, const uint16_t *, 289static int iwm_parse_nvm_data(struct iwm_softc *, const uint16_t *,
290 const uint16_t *, const uint16_t *, uint8_t, uint8_t); 290 const uint16_t *, const uint16_t *, uint8_t, uint8_t);
291static int iwm_nvm_init(struct iwm_softc *); 291static int iwm_nvm_init(struct iwm_softc *);
292static int iwm_firmware_load_chunk(struct iwm_softc *, uint32_t, 292static int iwm_firmware_load_chunk(struct iwm_softc *, uint32_t,
293 const uint8_t *, uint32_t); 293 const uint8_t *, uint32_t);
294static int iwm_load_firmware(struct iwm_softc *, enum iwm_ucode_type); 294static int iwm_load_firmware(struct iwm_softc *, enum iwm_ucode_type);
295static int iwm_start_fw(struct iwm_softc *, enum iwm_ucode_type); 295static int iwm_start_fw(struct iwm_softc *, enum iwm_ucode_type);
296static int iwm_fw_alive(struct iwm_softc *, uint32_t); 296static int iwm_fw_alive(struct iwm_softc *, uint32_t);
297static int iwm_send_tx_ant_cfg(struct iwm_softc *, uint8_t); 297static int iwm_send_tx_ant_cfg(struct iwm_softc *, uint8_t);
298static int iwm_send_phy_cfg_cmd(struct iwm_softc *); 298static int iwm_send_phy_cfg_cmd(struct iwm_softc *);
299static int iwm_mvm_load_ucode_wait_alive(struct iwm_softc *, 299static int iwm_mvm_load_ucode_wait_alive(struct iwm_softc *,
300 enum iwm_ucode_type); 300 enum iwm_ucode_type);
301static int iwm_run_init_mvm_ucode(struct iwm_softc *, int); 301static int iwm_run_init_mvm_ucode(struct iwm_softc *, int);
302static int iwm_rx_addbuf(struct iwm_softc *, int, int); 302static int iwm_rx_addbuf(struct iwm_softc *, int, int);
303static int iwm_mvm_calc_rssi(struct iwm_softc *, struct iwm_rx_phy_info *); 303static int iwm_mvm_calc_rssi(struct iwm_softc *, struct iwm_rx_phy_info *);
304static int iwm_mvm_get_signal_strength(struct iwm_softc *, 304static int iwm_mvm_get_signal_strength(struct iwm_softc *,
305 struct iwm_rx_phy_info *); 305 struct iwm_rx_phy_info *);
306static void iwm_mvm_rx_rx_phy_cmd(struct iwm_softc *, 306static void iwm_mvm_rx_rx_phy_cmd(struct iwm_softc *,
307 struct iwm_rx_packet *, struct iwm_rx_data *); 307 struct iwm_rx_packet *, struct iwm_rx_data *);
308static int iwm_get_noise(const struct iwm_mvm_statistics_rx_non_phy *); 308static int iwm_get_noise(const struct iwm_mvm_statistics_rx_non_phy *);
309static void iwm_mvm_rx_rx_mpdu(struct iwm_softc *, struct iwm_rx_packet *, 309static void iwm_mvm_rx_rx_mpdu(struct iwm_softc *, struct iwm_rx_packet *,
310 struct iwm_rx_data *); 310 struct iwm_rx_data *);
311static void iwm_mvm_rx_tx_cmd_single(struct iwm_softc *, 311static void iwm_mvm_rx_tx_cmd_single(struct iwm_softc *,
312 struct iwm_rx_packet *, struct iwm_node *); 312 struct iwm_rx_packet *, struct iwm_node *);
313static void iwm_mvm_rx_tx_cmd(struct iwm_softc *, struct iwm_rx_packet *, 313static void iwm_mvm_rx_tx_cmd(struct iwm_softc *, struct iwm_rx_packet *,
314 struct iwm_rx_data *); 314 struct iwm_rx_data *);
315static int iwm_mvm_binding_cmd(struct iwm_softc *, struct iwm_node *, 315static int iwm_mvm_binding_cmd(struct iwm_softc *, struct iwm_node *,
316 uint32_t); 316 uint32_t);
317static int iwm_mvm_binding_update(struct iwm_softc *, struct iwm_node *, 317static int iwm_mvm_binding_update(struct iwm_softc *, struct iwm_node *,
318 int); 318 int);
319static int iwm_mvm_binding_add_vif(struct iwm_softc *, struct iwm_node *); 319static int iwm_mvm_binding_add_vif(struct iwm_softc *, struct iwm_node *);
320static void iwm_mvm_phy_ctxt_cmd_hdr(struct iwm_softc *, 320static void iwm_mvm_phy_ctxt_cmd_hdr(struct iwm_softc *,
321 struct iwm_mvm_phy_ctxt *, struct iwm_phy_context_cmd *, 321 struct iwm_mvm_phy_ctxt *, struct iwm_phy_context_cmd *,
322 uint32_t, uint32_t); 322 uint32_t, uint32_t);
323static void iwm_mvm_phy_ctxt_cmd_data(struct iwm_softc *, 323static void iwm_mvm_phy_ctxt_cmd_data(struct iwm_softc *,
324 struct iwm_phy_context_cmd *, struct ieee80211_channel *, 324 struct iwm_phy_context_cmd *, struct ieee80211_channel *,
325 uint8_t, uint8_t); 325 uint8_t, uint8_t);
326static int iwm_mvm_phy_ctxt_apply(struct iwm_softc *, 326static int iwm_mvm_phy_ctxt_apply(struct iwm_softc *,
327 struct iwm_mvm_phy_ctxt *, uint8_t, uint8_t, uint32_t, 327 struct iwm_mvm_phy_ctxt *, uint8_t, uint8_t, uint32_t,
328 uint32_t); 328 uint32_t);
329static int iwm_mvm_phy_ctxt_add(struct iwm_softc *, 329static int iwm_mvm_phy_ctxt_add(struct iwm_softc *,
330 struct iwm_mvm_phy_ctxt *, struct ieee80211_channel *, 330 struct iwm_mvm_phy_ctxt *, struct ieee80211_channel *,
331 uint8_t, uint8_t); 331 uint8_t, uint8_t);
332static int iwm_mvm_phy_ctxt_changed(struct iwm_softc *, 332static int iwm_mvm_phy_ctxt_changed(struct iwm_softc *,
333 struct iwm_mvm_phy_ctxt *, struct ieee80211_channel *, 333 struct iwm_mvm_phy_ctxt *, struct ieee80211_channel *,
334 uint8_t, uint8_t); 334 uint8_t, uint8_t);
335static int iwm_send_cmd(struct iwm_softc *, struct iwm_host_cmd *); 335static int iwm_send_cmd(struct iwm_softc *, struct iwm_host_cmd *);
336static int iwm_mvm_send_cmd_pdu(struct iwm_softc *, uint8_t, uint32_t, 336static int iwm_mvm_send_cmd_pdu(struct iwm_softc *, uint8_t, uint32_t,
337 uint16_t, const void *); 337 uint16_t, const void *);
338static int iwm_mvm_send_cmd_status(struct iwm_softc *, 338static int iwm_mvm_send_cmd_status(struct iwm_softc *,
339 struct iwm_host_cmd *, uint32_t *); 339 struct iwm_host_cmd *, uint32_t *);
340static int iwm_mvm_send_cmd_pdu_status(struct iwm_softc *, uint8_t, 340static int iwm_mvm_send_cmd_pdu_status(struct iwm_softc *, uint8_t,
341 uint16_t, const void *, uint32_t *); 341 uint16_t, const void *, uint32_t *);
342static void iwm_free_resp(struct iwm_softc *, struct iwm_host_cmd *); 342static void iwm_free_resp(struct iwm_softc *, struct iwm_host_cmd *);
343static void iwm_cmd_done(struct iwm_softc *, struct iwm_rx_packet *); 343static void iwm_cmd_done(struct iwm_softc *, struct iwm_rx_packet *);
344#if 0 344#if 0
345static void iwm_update_sched(struct iwm_softc *, int, int, uint8_t, 345static void iwm_update_sched(struct iwm_softc *, int, int, uint8_t,
346 uint16_t); 346 uint16_t);
347#endif 347#endif
348static const struct iwm_rate *iwm_tx_fill_cmd(struct iwm_softc *, 348static const struct iwm_rate *iwm_tx_fill_cmd(struct iwm_softc *,
349 struct iwm_node *, struct ieee80211_frame *, 349 struct iwm_node *, struct ieee80211_frame *,
350 struct iwm_tx_cmd *); 350 struct iwm_tx_cmd *);
351static int iwm_tx(struct iwm_softc *, struct mbuf *, 351static int iwm_tx(struct iwm_softc *, struct mbuf *,
352 struct ieee80211_node *, int); 352 struct ieee80211_node *, int);
353static int iwm_mvm_beacon_filter_send_cmd(struct iwm_softc *, 353static int iwm_mvm_beacon_filter_send_cmd(struct iwm_softc *,
354 struct iwm_beacon_filter_cmd *); 354 struct iwm_beacon_filter_cmd *);
355static void iwm_mvm_beacon_filter_set_cqm_params(struct iwm_softc *, 355static void iwm_mvm_beacon_filter_set_cqm_params(struct iwm_softc *,
356 struct iwm_node *, struct iwm_beacon_filter_cmd *); 356 struct iwm_node *, struct iwm_beacon_filter_cmd *);
357static int iwm_mvm_update_beacon_abort(struct iwm_softc *, 357static int iwm_mvm_update_beacon_abort(struct iwm_softc *,
358 struct iwm_node *, int); 358 struct iwm_node *, int);
359static void iwm_mvm_power_log(struct iwm_softc *, 359static void iwm_mvm_power_log(struct iwm_softc *,
360 struct iwm_mac_power_cmd *); 360 struct iwm_mac_power_cmd *);
361static void iwm_mvm_power_build_cmd(struct iwm_softc *, struct iwm_node *, 361static void iwm_mvm_power_build_cmd(struct iwm_softc *, struct iwm_node *,
362 struct iwm_mac_power_cmd *); 362 struct iwm_mac_power_cmd *);
363static int iwm_mvm_power_mac_update_mode(struct iwm_softc *, 363static int iwm_mvm_power_mac_update_mode(struct iwm_softc *,
364 struct iwm_node *); 364 struct iwm_node *);
365static int iwm_mvm_power_update_device(struct iwm_softc *); 365static int iwm_mvm_power_update_device(struct iwm_softc *);
366static int iwm_mvm_enable_beacon_filter(struct iwm_softc *, 366static int iwm_mvm_enable_beacon_filter(struct iwm_softc *,
367 struct iwm_node *); 367 struct iwm_node *);
368static int iwm_mvm_disable_beacon_filter(struct iwm_softc *, 368static int iwm_mvm_disable_beacon_filter(struct iwm_softc *,
369 struct iwm_node *); 369 struct iwm_node *);
370static void iwm_mvm_add_sta_cmd_v6_to_v5(struct iwm_mvm_add_sta_cmd_v6 *, 370static void iwm_mvm_add_sta_cmd_v6_to_v5(struct iwm_mvm_add_sta_cmd_v6 *,
371 struct iwm_mvm_add_sta_cmd_v5 *); 371 struct iwm_mvm_add_sta_cmd_v5 *);
372static int iwm_mvm_send_add_sta_cmd_status(struct iwm_softc *, 372static int iwm_mvm_send_add_sta_cmd_status(struct iwm_softc *,
373 struct iwm_mvm_add_sta_cmd_v6 *, int *); 373 struct iwm_mvm_add_sta_cmd_v6 *, int *);
374static int iwm_mvm_sta_send_to_fw(struct iwm_softc *, struct iwm_node *, 374static int iwm_mvm_sta_send_to_fw(struct iwm_softc *, struct iwm_node *,
375 int); 375 int);
376static int iwm_mvm_add_sta(struct iwm_softc *, struct iwm_node *); 376static int iwm_mvm_add_sta(struct iwm_softc *, struct iwm_node *);
377static int iwm_mvm_update_sta(struct iwm_softc *, struct iwm_node *); 377static int iwm_mvm_update_sta(struct iwm_softc *, struct iwm_node *);
378static int iwm_mvm_add_int_sta_common(struct iwm_softc *, 378static int iwm_mvm_add_int_sta_common(struct iwm_softc *,
379 struct iwm_int_sta *, const uint8_t *, uint16_t, uint16_t); 379 struct iwm_int_sta *, const uint8_t *, uint16_t, uint16_t);
380static int iwm_mvm_add_aux_sta(struct iwm_softc *); 380static int iwm_mvm_add_aux_sta(struct iwm_softc *);
381static uint16_t iwm_mvm_scan_rx_chain(struct iwm_softc *); 381static uint16_t iwm_mvm_scan_rx_chain(struct iwm_softc *);
382static uint32_t iwm_mvm_scan_max_out_time(struct iwm_softc *, uint32_t, int); 382static uint32_t iwm_mvm_scan_max_out_time(struct iwm_softc *, uint32_t, int);
383static uint32_t iwm_mvm_scan_suspend_time(struct iwm_softc *, int); 383static uint32_t iwm_mvm_scan_suspend_time(struct iwm_softc *, int);
384static uint32_t iwm_mvm_scan_rxon_flags(struct iwm_softc *, int); 384static uint32_t iwm_mvm_scan_rxon_flags(struct iwm_softc *, int);
385static uint32_t iwm_mvm_scan_rate_n_flags(struct iwm_softc *, int, int); 385static uint32_t iwm_mvm_scan_rate_n_flags(struct iwm_softc *, int, int);
386static uint16_t iwm_mvm_get_active_dwell(struct iwm_softc *, int, int); 386static uint16_t iwm_mvm_get_active_dwell(struct iwm_softc *, int, int);
387static uint16_t iwm_mvm_get_passive_dwell(struct iwm_softc *, int); 387static uint16_t iwm_mvm_get_passive_dwell(struct iwm_softc *, int);
388static int iwm_mvm_scan_fill_channels(struct iwm_softc *, 388static int iwm_mvm_scan_fill_channels(struct iwm_softc *,
389 struct iwm_scan_cmd *, int, int, int); 389 struct iwm_scan_cmd *, int, int, int);
390static uint16_t iwm_mvm_fill_probe_req(struct iwm_softc *, 390static uint16_t iwm_mvm_fill_probe_req(struct iwm_softc *,
391 struct ieee80211_frame *, const uint8_t *, int, 391 struct ieee80211_frame *, const uint8_t *, int,
392 const uint8_t *, int, const uint8_t *, int, int); 392 const uint8_t *, int, const uint8_t *, int, int);
393static int iwm_mvm_scan_request(struct iwm_softc *, int, int, uint8_t *, 393static int iwm_mvm_scan_request(struct iwm_softc *, int, int, uint8_t *,
394 int); 394 int);
395static void iwm_mvm_ack_rates(struct iwm_softc *, struct iwm_node *, int *, 395static void iwm_mvm_ack_rates(struct iwm_softc *, struct iwm_node *, int *,
396 int *); 396 int *);
397static void iwm_mvm_mac_ctxt_cmd_common(struct iwm_softc *, 397static void iwm_mvm_mac_ctxt_cmd_common(struct iwm_softc *,
398 struct iwm_node *, struct iwm_mac_ctx_cmd *, uint32_t); 398 struct iwm_node *, struct iwm_mac_ctx_cmd *, uint32_t);
399static int iwm_mvm_mac_ctxt_send_cmd(struct iwm_softc *, 399static int iwm_mvm_mac_ctxt_send_cmd(struct iwm_softc *,
400 struct iwm_mac_ctx_cmd *); 400 struct iwm_mac_ctx_cmd *);
401static void iwm_mvm_mac_ctxt_cmd_fill_sta(struct iwm_softc *, 401static void iwm_mvm_mac_ctxt_cmd_fill_sta(struct iwm_softc *,
402 struct iwm_node *, struct iwm_mac_data_sta *, int); 402 struct iwm_node *, struct iwm_mac_data_sta *, int);
403static int iwm_mvm_mac_ctxt_cmd_station(struct iwm_softc *, 403static int iwm_mvm_mac_ctxt_cmd_station(struct iwm_softc *,
404 struct iwm_node *, uint32_t); 404 struct iwm_node *, uint32_t);
405static int iwm_mvm_mac_ctx_send(struct iwm_softc *, struct iwm_node *, 405static int iwm_mvm_mac_ctx_send(struct iwm_softc *, struct iwm_node *,
406 uint32_t); 406 uint32_t);
407static int iwm_mvm_mac_ctxt_add(struct iwm_softc *, struct iwm_node *); 407static int iwm_mvm_mac_ctxt_add(struct iwm_softc *, struct iwm_node *);
408static int iwm_mvm_mac_ctxt_changed(struct iwm_softc *, struct iwm_node *); 408static int iwm_mvm_mac_ctxt_changed(struct iwm_softc *, struct iwm_node *);
409static int iwm_mvm_update_quotas(struct iwm_softc *, struct iwm_node *); 409static int iwm_mvm_update_quotas(struct iwm_softc *, struct iwm_node *);
410static int iwm_auth(struct iwm_softc *); 410static int iwm_auth(struct iwm_softc *);
411static int iwm_assoc(struct iwm_softc *); 411static int iwm_assoc(struct iwm_softc *);
412static int iwm_release(struct iwm_softc *, struct iwm_node *); 412static int iwm_release(struct iwm_softc *, struct iwm_node *);
413static void iwm_calib_timeout(void *); 413static void iwm_calib_timeout(void *);
414static void iwm_setrates(struct iwm_node *); 414static void iwm_setrates(struct iwm_node *);
415static int iwm_media_change(struct ifnet *); 415static int iwm_media_change(struct ifnet *);
416static void iwm_newstate_cb(struct work *, void *); 416static void iwm_newstate_cb(struct work *, void *);
417static int iwm_newstate(struct ieee80211com *, enum ieee80211_state, int); 417static int iwm_newstate(struct ieee80211com *, enum ieee80211_state, int);
418static void iwm_endscan_cb(struct work *, void *); 418static void iwm_endscan_cb(struct work *, void *);
419static int iwm_init_hw(struct iwm_softc *); 419static int iwm_init_hw(struct iwm_softc *);
420static int iwm_init(struct ifnet *); 420static int iwm_init(struct ifnet *);
421static void iwm_start(struct ifnet *); 421static void iwm_start(struct ifnet *);
422static void iwm_stop(struct ifnet *, int); 422static void iwm_stop(struct ifnet *, int);
423static void iwm_watchdog(struct ifnet *); 423static void iwm_watchdog(struct ifnet *);
424static int iwm_ioctl(struct ifnet *, u_long, void *); 424static int iwm_ioctl(struct ifnet *, u_long, void *);
425#ifdef IWM_DEBUG 425#ifdef IWM_DEBUG
426static const char *iwm_desc_lookup(uint32_t); 426static const char *iwm_desc_lookup(uint32_t);
427static void iwm_nic_error(struct iwm_softc *); 427static void iwm_nic_error(struct iwm_softc *);
428#endif 428#endif
429static void iwm_notif_intr(struct iwm_softc *); 429static void iwm_notif_intr(struct iwm_softc *);
430static int iwm_intr(void *); 430static int iwm_intr(void *);
431static int iwm_preinit(struct iwm_softc *); 431static int iwm_preinit(struct iwm_softc *);
432static void iwm_attach_hook(device_t); 432static void iwm_attach_hook(device_t);
433static void iwm_attach(device_t, device_t, void *); 433static void iwm_attach(device_t, device_t, void *);
434#if 0 434#if 0
435static void iwm_init_task(void *); 435static void iwm_init_task(void *);
436static int iwm_activate(device_t, enum devact); 436static int iwm_activate(device_t, enum devact);
437static void iwm_wakeup(struct iwm_softc *); 437static void iwm_wakeup(struct iwm_softc *);
438#endif 438#endif
439static void iwm_radiotap_attach(struct iwm_softc *); 439static void iwm_radiotap_attach(struct iwm_softc *);
440static int iwm_sysctl_fw_loaded_handler(SYSCTLFN_PROTO); 440static int iwm_sysctl_fw_loaded_handler(SYSCTLFN_PROTO);
441 441
442static int iwm_sysctl_root_num; 442static int iwm_sysctl_root_num;
443 443
444static int 444static int
445iwm_firmload(struct iwm_softc *sc) 445iwm_firmload(struct iwm_softc *sc)
446{ 446{
447 struct iwm_fw_info *fw = &sc->sc_fw; 447 struct iwm_fw_info *fw = &sc->sc_fw;
448 firmware_handle_t fwh; 448 firmware_handle_t fwh;
449 int error; 449 int error;
450 450
451 if (ISSET(sc->sc_flags, IWM_FLAG_FW_LOADED)) 451 if (ISSET(sc->sc_flags, IWM_FLAG_FW_LOADED))
452 return 0; 452 return 0;
453 453
454 /* Open firmware image. */ 454 /* Open firmware image. */
455 if ((error = firmware_open("if_iwm", sc->sc_fwname, &fwh)) != 0) { 455 if ((error = firmware_open("if_iwm", sc->sc_fwname, &fwh)) != 0) {
456 aprint_error_dev(sc->sc_dev, 456 aprint_error_dev(sc->sc_dev,
457 "could not get firmware handle %s\n", sc->sc_fwname); 457 "could not get firmware handle %s\n", sc->sc_fwname);
458 return error; 458 return error;
459 } 459 }
460 460
461 if (fw->fw_rawdata != NULL && fw->fw_rawsize > 0) { 461 if (fw->fw_rawdata != NULL && fw->fw_rawsize > 0) {
462 kmem_free(fw->fw_rawdata, fw->fw_rawsize); 462 kmem_free(fw->fw_rawdata, fw->fw_rawsize);
463 fw->fw_rawdata = NULL; 463 fw->fw_rawdata = NULL;
464 } 464 }
465 465
466 fw->fw_rawsize = firmware_get_size(fwh); 466 fw->fw_rawsize = firmware_get_size(fwh);
467 /* 467 /*
468 * Well, this is how the Linux driver checks it .... 468 * Well, this is how the Linux driver checks it ....
469 */ 469 */
470 if (fw->fw_rawsize < sizeof(uint32_t)) { 470 if (fw->fw_rawsize < sizeof(uint32_t)) {
471 aprint_error_dev(sc->sc_dev, 471 aprint_error_dev(sc->sc_dev,
472 "firmware too short: %zd bytes\n", fw->fw_rawsize); 472 "firmware too short: %zd bytes\n", fw->fw_rawsize);
473 error = EINVAL; 473 error = EINVAL;
474 goto out; 474 goto out;
475 } 475 }
476 476
477 /* some sanity */ 477 /* some sanity */
478 if (fw->fw_rawsize > IWM_FWMAXSIZE) { 478 if (fw->fw_rawsize > IWM_FWMAXSIZE) {
479 aprint_error_dev(sc->sc_dev, 479 aprint_error_dev(sc->sc_dev,
480 "firmware size is ridiculous: %zd bytes\n", fw->fw_rawsize); 480 "firmware size is ridiculous: %zd bytes\n", fw->fw_rawsize);
481 error = EINVAL; 481 error = EINVAL;
482 goto out; 482 goto out;
483 } 483 }
484 484
485 /* Read the firmware. */ 485 /* Read the firmware. */
486 fw->fw_rawdata = kmem_alloc(fw->fw_rawsize, KM_SLEEP); 486 fw->fw_rawdata = kmem_alloc(fw->fw_rawsize, KM_SLEEP);
487 if (fw->fw_rawdata == NULL) { 487 if (fw->fw_rawdata == NULL) {
488 aprint_error_dev(sc->sc_dev, 488 aprint_error_dev(sc->sc_dev,
489 "not enough memory to stock firmware %s\n", sc->sc_fwname); 489 "not enough memory to stock firmware %s\n", sc->sc_fwname);
490 error = ENOMEM; 490 error = ENOMEM;
491 goto out; 491 goto out;
492 } 492 }
493 error = firmware_read(fwh, 0, fw->fw_rawdata, fw->fw_rawsize); 493 error = firmware_read(fwh, 0, fw->fw_rawdata, fw->fw_rawsize);
494 if (error) { 494 if (error) {
495 aprint_error_dev(sc->sc_dev, 495 aprint_error_dev(sc->sc_dev,
496 "could not read firmware %s\n", sc->sc_fwname); 496 "could not read firmware %s\n", sc->sc_fwname);
497 goto out; 497 goto out;
498 } 498 }
499 499
500 SET(sc->sc_flags, IWM_FLAG_FW_LOADED); 500 SET(sc->sc_flags, IWM_FLAG_FW_LOADED);
501 out: 501 out:
502 /* caller will release memory, if necessary */ 502 /* caller will release memory, if necessary */
503 503
504 firmware_close(fwh); 504 firmware_close(fwh);
505 return error; 505 return error;
506} 506}
507 507
508/* 508/*
509 * just maintaining status quo. 509 * just maintaining status quo.
510 */ 510 */
511static void 511static void
512iwm_fix_channel(struct ieee80211com *ic, struct mbuf *m) 512iwm_fix_channel(struct ieee80211com *ic, struct mbuf *m)
513{ 513{
514 struct iwm_softc *sc = ic->ic_ifp->if_softc; 514 struct iwm_softc *sc = ic->ic_ifp->if_softc;
515 struct ieee80211_frame *wh; 515 struct ieee80211_frame *wh;
516 uint8_t subtype; 516 uint8_t subtype;
517 uint8_t *frm, *efrm; 517 uint8_t *frm, *efrm;
518 518
519 wh = mtod(m, struct ieee80211_frame *); 519 wh = mtod(m, struct ieee80211_frame *);
520 520
521 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 521 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT)
522 return; 522 return;
523 523
524 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 524 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
525 525
526 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 526 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON &&
527 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 527 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP)
528 return; 528 return;
529 529
530 if (sc->sc_scanband == IEEE80211_CHAN_5GHZ) { 530 if (sc->sc_scanband == IEEE80211_CHAN_5GHZ) {
531 int chan = le32toh(sc->sc_last_phy_info.channel); 531 int chan = le32toh(sc->sc_last_phy_info.channel);
532 if (chan < __arraycount(ic->ic_channels)) 532 if (chan < __arraycount(ic->ic_channels))
533 ic->ic_curchan = &ic->ic_channels[chan]; 533 ic->ic_curchan = &ic->ic_channels[chan];
534 return; 534 return;
535 } 535 }
536 536
537 frm = (uint8_t *)(wh + 1); 537 frm = (uint8_t *)(wh + 1);
538 efrm = mtod(m, uint8_t *) + m->m_len; 538 efrm = mtod(m, uint8_t *) + m->m_len;
539 539
540 frm += 12; /* skip tstamp, bintval and capinfo fields */ 540 frm += 12; /* skip tstamp, bintval and capinfo fields */
541 while (frm < efrm) { 541 while (frm < efrm) {
542 if (*frm == IEEE80211_ELEMID_DSPARMS) { 542 if (*frm == IEEE80211_ELEMID_DSPARMS) {
543#if IEEE80211_CHAN_MAX < 255 543#if IEEE80211_CHAN_MAX < 255
544 if (frm[2] <= IEEE80211_CHAN_MAX) 544 if (frm[2] <= IEEE80211_CHAN_MAX)
545#endif 545#endif
546 ic->ic_curchan = &ic->ic_channels[frm[2]]; 546 ic->ic_curchan = &ic->ic_channels[frm[2]];
547 } 547 }
548 frm += frm[1] + 2; 548 frm += frm[1] + 2;
549 } 549 }
550} 550}
551 551
552/* 552/*
553 * Firmware parser. 553 * Firmware parser.
554 */ 554 */
555 555
556static int 556static int
557iwm_store_cscheme(struct iwm_softc *sc, uint8_t *data, size_t dlen) 557iwm_store_cscheme(struct iwm_softc *sc, uint8_t *data, size_t dlen)
558{ 558{
559 struct iwm_fw_cscheme_list *l = (void *)data; 559 struct iwm_fw_cscheme_list *l = (void *)data;
560 560
561 if (dlen < sizeof(*l) || 561 if (dlen < sizeof(*l) ||
562 dlen < sizeof(l->size) + l->size * sizeof(*l->cs)) 562 dlen < sizeof(l->size) + l->size * sizeof(*l->cs))
563 return EINVAL; 563 return EINVAL;
564 564
565 /* we don't actually store anything for now, always use s/w crypto */ 565 /* we don't actually store anything for now, always use s/w crypto */
566 566
567 return 0; 567 return 0;
568} 568}
569 569
570static int 570static int
571iwm_firmware_store_section(struct iwm_softc *sc, 571iwm_firmware_store_section(struct iwm_softc *sc,
572 enum iwm_ucode_type type, uint8_t *data, size_t dlen) 572 enum iwm_ucode_type type, uint8_t *data, size_t dlen)
573{ 573{
574 struct iwm_fw_sects *fws; 574 struct iwm_fw_sects *fws;
575 struct iwm_fw_onesect *fwone; 575 struct iwm_fw_onesect *fwone;
576 576
577 if (type >= IWM_UCODE_TYPE_MAX) 577 if (type >= IWM_UCODE_TYPE_MAX)
578 return EINVAL; 578 return EINVAL;
579 if (dlen < sizeof(uint32_t)) 579 if (dlen < sizeof(uint32_t))
580 return EINVAL; 580 return EINVAL;
581 581
582 fws = &sc->sc_fw.fw_sects[type]; 582 fws = &sc->sc_fw.fw_sects[type];
583 if (fws->fw_count >= IWM_UCODE_SECT_MAX) 583 if (fws->fw_count >= IWM_UCODE_SECT_MAX)
584 return EINVAL; 584 return EINVAL;
585 585
586 fwone = &fws->fw_sect[fws->fw_count]; 586 fwone = &fws->fw_sect[fws->fw_count];
587 587
588 /* first 32bit are device load offset */ 588 /* first 32bit are device load offset */
589 memcpy(&fwone->fws_devoff, data, sizeof(uint32_t)); 589 memcpy(&fwone->fws_devoff, data, sizeof(uint32_t));
590 590
591 /* rest is data */ 591 /* rest is data */
592 fwone->fws_data = data + sizeof(uint32_t); 592 fwone->fws_data = data + sizeof(uint32_t);
593 fwone->fws_len = dlen - sizeof(uint32_t); 593 fwone->fws_len = dlen - sizeof(uint32_t);
594 594
595 /* for freeing the buffer during driver unload */ 595 /* for freeing the buffer during driver unload */
596 fwone->fws_alloc = data; 596 fwone->fws_alloc = data;
597 fwone->fws_allocsize = dlen; 597 fwone->fws_allocsize = dlen;
598 598
599 fws->fw_count++; 599 fws->fw_count++;
600 fws->fw_totlen += fwone->fws_len; 600 fws->fw_totlen += fwone->fws_len;
601 601
602 return 0; 602 return 0;
603} 603}
604 604
605/* iwlwifi: iwl-drv.c */ 605/* iwlwifi: iwl-drv.c */
606struct iwm_tlv_calib_data { 606struct iwm_tlv_calib_data {
607 uint32_t ucode_type; 607 uint32_t ucode_type;
608 struct iwm_tlv_calib_ctrl calib; 608 struct iwm_tlv_calib_ctrl calib;
609} __packed; 609} __packed;
610 610
611static int 611static int
612iwm_set_default_calib(struct iwm_softc *sc, const void *data) 612iwm_set_default_calib(struct iwm_softc *sc, const void *data)
613{ 613{
614 const struct iwm_tlv_calib_data *def_calib = data; 614 const struct iwm_tlv_calib_data *def_calib = data;
615 uint32_t ucode_type = le32toh(def_calib->ucode_type); 615 uint32_t ucode_type = le32toh(def_calib->ucode_type);
616 616
617 if (ucode_type >= IWM_UCODE_TYPE_MAX) { 617 if (ucode_type >= IWM_UCODE_TYPE_MAX) {
618 DPRINTF(("%s: Wrong ucode_type %u for default " 618 DPRINTF(("%s: Wrong ucode_type %u for default "
619 "calibration.\n", DEVNAME(sc), ucode_type)); 619 "calibration.\n", DEVNAME(sc), ucode_type));
620 return EINVAL; 620 return EINVAL;
621 } 621 }
622 622
623 sc->sc_default_calib[ucode_type].flow_trigger = 623 sc->sc_default_calib[ucode_type].flow_trigger =
624 def_calib->calib.flow_trigger; 624 def_calib->calib.flow_trigger;
625 sc->sc_default_calib[ucode_type].event_trigger = 625 sc->sc_default_calib[ucode_type].event_trigger =
626 def_calib->calib.event_trigger; 626 def_calib->calib.event_trigger;
627 627
628 return 0; 628 return 0;
629} 629}
630 630
631static int 631static int
632iwm_read_firmware(struct iwm_softc *sc) 632iwm_read_firmware(struct iwm_softc *sc)
633{ 633{
634 struct iwm_fw_info *fw = &sc->sc_fw; 634 struct iwm_fw_info *fw = &sc->sc_fw;
635 struct iwm_tlv_ucode_header *uhdr; 635 struct iwm_tlv_ucode_header *uhdr;
636 struct iwm_ucode_tlv tlv; 636 struct iwm_ucode_tlv tlv;
637 enum iwm_ucode_tlv_type tlv_type; 637 enum iwm_ucode_tlv_type tlv_type;
638 uint8_t *data; 638 uint8_t *data;
639 int error, status; 639 int error, status;
640 size_t len; 640 size_t len;
641 641
642 if (fw->fw_status == IWM_FW_STATUS_NONE) { 642 if (fw->fw_status == IWM_FW_STATUS_NONE) {
643 fw->fw_status = IWM_FW_STATUS_INPROGRESS; 643 fw->fw_status = IWM_FW_STATUS_INPROGRESS;
644 } else { 644 } else {
645 while (fw->fw_status == IWM_FW_STATUS_INPROGRESS) 645 while (fw->fw_status == IWM_FW_STATUS_INPROGRESS)
646 tsleep(&sc->sc_fw, 0, "iwmfwp", 0); 646 tsleep(&sc->sc_fw, 0, "iwmfwp", 0);
647 } 647 }
648 status = fw->fw_status; 648 status = fw->fw_status;
649 649
650 if (status == IWM_FW_STATUS_DONE) 650 if (status == IWM_FW_STATUS_DONE)
651 return 0; 651 return 0;
652 652
653 /* 653 /*
654 * Load firmware into driver memory. 654 * Load firmware into driver memory.
655 * fw_rawdata and fw_rawsize will be set. 655 * fw_rawdata and fw_rawsize will be set.
656 */ 656 */
657 error = iwm_firmload(sc); 657 error = iwm_firmload(sc);
658 if (error != 0) { 658 if (error != 0) {
659 aprint_error_dev(sc->sc_dev, 659 aprint_error_dev(sc->sc_dev,
660 "could not read firmware %s (error %d)\n", 660 "could not read firmware %s (error %d)\n",
661 sc->sc_fwname, error); 661 sc->sc_fwname, error);
662 goto out; 662 goto out;
663 } 663 }
664 664
665 /* 665 /*
666 * Parse firmware contents 666 * Parse firmware contents
667 */ 667 */
668 668
669 uhdr = (void *)fw->fw_rawdata; 669 uhdr = (void *)fw->fw_rawdata;
670 if (*(uint32_t *)fw->fw_rawdata != 0 670 if (*(uint32_t *)fw->fw_rawdata != 0
671 || le32toh(uhdr->magic) != IWM_TLV_UCODE_MAGIC) { 671 || le32toh(uhdr->magic) != IWM_TLV_UCODE_MAGIC) {
672 aprint_error_dev(sc->sc_dev, "invalid firmware %s\n", 672 aprint_error_dev(sc->sc_dev, "invalid firmware %s\n",
673 sc->sc_fwname); 673 sc->sc_fwname);
674 error = EINVAL; 674 error = EINVAL;
675 goto out; 675 goto out;
676 } 676 }
677 677
678 sc->sc_fwver = le32toh(uhdr->ver); 678 sc->sc_fwver = le32toh(uhdr->ver);
679 data = uhdr->data; 679 data = uhdr->data;
680 len = fw->fw_rawsize - sizeof(*uhdr); 680 len = fw->fw_rawsize - sizeof(*uhdr);
681 681
682 while (len >= sizeof(tlv)) { 682 while (len >= sizeof(tlv)) {
683 size_t tlv_len; 683 size_t tlv_len;
684 void *tlv_data; 684 void *tlv_data;
685 685
686 memcpy(&tlv, data, sizeof(tlv)); 686 memcpy(&tlv, data, sizeof(tlv));
687 tlv_len = le32toh(tlv.length); 687 tlv_len = le32toh(tlv.length);
688 tlv_type = le32toh(tlv.type); 688 tlv_type = le32toh(tlv.type);
689 689
690 len -= sizeof(tlv); 690 len -= sizeof(tlv);
691 data += sizeof(tlv); 691 data += sizeof(tlv);
692 tlv_data = data; 692 tlv_data = data;
693 693
694 if (len < tlv_len) { 694 if (len < tlv_len) {
695 aprint_error_dev(sc->sc_dev, 695 aprint_error_dev(sc->sc_dev,
696 "firmware too short: %zu bytes\n", len); 696 "firmware too short: %zu bytes\n", len);
697 error = EINVAL; 697 error = EINVAL;
698 goto parse_out; 698 goto parse_out;
699 } 699 }
700 700
701 switch ((int)tlv_type) { 701 switch ((int)tlv_type) {
702 case IWM_UCODE_TLV_PROBE_MAX_LEN: 702 case IWM_UCODE_TLV_PROBE_MAX_LEN:
703 if (tlv_len < sizeof(uint32_t)) { 703 if (tlv_len < sizeof(uint32_t)) {
704 error = EINVAL; 704 error = EINVAL;
705 goto parse_out; 705 goto parse_out;
706 } 706 }
707 sc->sc_capa_max_probe_len 707 sc->sc_capa_max_probe_len
708 = le32toh(*(uint32_t *)tlv_data); 708 = le32toh(*(uint32_t *)tlv_data);
709 /* limit it to something sensible */ 709 /* limit it to something sensible */
710 if (sc->sc_capa_max_probe_len > (1<<16)) { 710 if (sc->sc_capa_max_probe_len > (1<<16)) {
711 DPRINTF(("%s: IWM_UCODE_TLV_PROBE_MAX_LEN " 711 DPRINTF(("%s: IWM_UCODE_TLV_PROBE_MAX_LEN "
712 "ridiculous\n", DEVNAME(sc))); 712 "ridiculous\n", DEVNAME(sc)));
713 error = EINVAL; 713 error = EINVAL;
714 goto parse_out; 714 goto parse_out;
715 } 715 }
716 break; 716 break;
717 case IWM_UCODE_TLV_PAN: 717 case IWM_UCODE_TLV_PAN:
718 if (tlv_len) { 718 if (tlv_len) {
719 error = EINVAL; 719 error = EINVAL;
720 goto parse_out; 720 goto parse_out;
721 } 721 }
722 sc->sc_capaflags |= IWM_UCODE_TLV_FLAGS_PAN; 722 sc->sc_capaflags |= IWM_UCODE_TLV_FLAGS_PAN;
723 break; 723 break;
724 case IWM_UCODE_TLV_FLAGS: 724 case IWM_UCODE_TLV_FLAGS:
725 if (tlv_len < sizeof(uint32_t)) { 725 if (tlv_len < sizeof(uint32_t)) {
726 error = EINVAL; 726 error = EINVAL;
727 goto parse_out; 727 goto parse_out;
728 } 728 }
729 /* 729 /*
730 * Apparently there can be many flags, but Linux driver 730 * Apparently there can be many flags, but Linux driver
731 * parses only the first one, and so do we. 731 * parses only the first one, and so do we.
732 * 732 *
733 * XXX: why does this override IWM_UCODE_TLV_PAN? 733 * XXX: why does this override IWM_UCODE_TLV_PAN?
734 * Intentional or a bug? Observations from 734 * Intentional or a bug? Observations from
735 * current firmware file: 735 * current firmware file:
736 * 1) TLV_PAN is parsed first 736 * 1) TLV_PAN is parsed first
737 * 2) TLV_FLAGS contains TLV_FLAGS_PAN 737 * 2) TLV_FLAGS contains TLV_FLAGS_PAN
738 * ==> this resets TLV_PAN to itself... hnnnk 738 * ==> this resets TLV_PAN to itself... hnnnk
739 */ 739 */
740 sc->sc_capaflags = le32toh(*(uint32_t *)tlv_data); 740 sc->sc_capaflags = le32toh(*(uint32_t *)tlv_data);
741 break; 741 break;
742 case IWM_UCODE_TLV_CSCHEME: 742 case IWM_UCODE_TLV_CSCHEME:
743 if ((error = iwm_store_cscheme(sc, 743 if ((error = iwm_store_cscheme(sc,
744 tlv_data, tlv_len)) != 0) 744 tlv_data, tlv_len)) != 0)
745 goto parse_out; 745 goto parse_out;
746 break; 746 break;
747 case IWM_UCODE_TLV_NUM_OF_CPU: 747 case IWM_UCODE_TLV_NUM_OF_CPU:
748 if (tlv_len != sizeof(uint32_t)) { 748 if (tlv_len != sizeof(uint32_t)) {
749 error = EINVAL; 749 error = EINVAL;
750 goto parse_out; 750 goto parse_out;
751 } 751 }
752 if (le32toh(*(uint32_t*)tlv_data) != 1) { 752 if (le32toh(*(uint32_t*)tlv_data) != 1) {
753 DPRINTF(("%s: driver supports " 753 DPRINTF(("%s: driver supports "
754 "only TLV_NUM_OF_CPU == 1", DEVNAME(sc))); 754 "only TLV_NUM_OF_CPU == 1", DEVNAME(sc)));
755 error = EINVAL; 755 error = EINVAL;
756 goto parse_out; 756 goto parse_out;
757 } 757 }
758 break; 758 break;
759 case IWM_UCODE_TLV_SEC_RT: 759 case IWM_UCODE_TLV_SEC_RT:
760 if ((error = iwm_firmware_store_section(sc, 760 if ((error = iwm_firmware_store_section(sc,
761 IWM_UCODE_TYPE_REGULAR, tlv_data, tlv_len)) != 0) 761 IWM_UCODE_TYPE_REGULAR, tlv_data, tlv_len)) != 0)
762 goto parse_out; 762 goto parse_out;
763 break; 763 break;
764 case IWM_UCODE_TLV_SEC_INIT: 764 case IWM_UCODE_TLV_SEC_INIT:
765 if ((error = iwm_firmware_store_section(sc, 765 if ((error = iwm_firmware_store_section(sc,
766 IWM_UCODE_TYPE_INIT, tlv_data, tlv_len)) != 0) 766 IWM_UCODE_TYPE_INIT, tlv_data, tlv_len)) != 0)
767 goto parse_out; 767 goto parse_out;
768 break; 768 break;
769 case IWM_UCODE_TLV_SEC_WOWLAN: 769 case IWM_UCODE_TLV_SEC_WOWLAN:
770 if ((error = iwm_firmware_store_section(sc, 770 if ((error = iwm_firmware_store_section(sc,
771 IWM_UCODE_TYPE_WOW, tlv_data, tlv_len)) != 0) 771 IWM_UCODE_TYPE_WOW, tlv_data, tlv_len)) != 0)
772 goto parse_out; 772 goto parse_out;
773 break; 773 break;
774 case IWM_UCODE_TLV_DEF_CALIB: 774 case IWM_UCODE_TLV_DEF_CALIB:
775 if (tlv_len != sizeof(struct iwm_tlv_calib_data)) { 775 if (tlv_len != sizeof(struct iwm_tlv_calib_data)) {
776 error = EINVAL; 776 error = EINVAL;
777 goto parse_out; 777 goto parse_out;
778 } 778 }
779 if ((error = iwm_set_default_calib(sc, tlv_data)) != 0) 779 if ((error = iwm_set_default_calib(sc, tlv_data)) != 0)
780 goto parse_out; 780 goto parse_out;
781 break; 781 break;
782 case IWM_UCODE_TLV_PHY_SKU: 782 case IWM_UCODE_TLV_PHY_SKU:
783 if (tlv_len != sizeof(uint32_t)) { 783 if (tlv_len != sizeof(uint32_t)) {
784 error = EINVAL; 784 error = EINVAL;
785 goto parse_out; 785 goto parse_out;
786 } 786 }
787 sc->sc_fw_phy_config = le32toh(*(uint32_t *)tlv_data); 787 sc->sc_fw_phy_config = le32toh(*(uint32_t *)tlv_data);
788 break; 788 break;
789 789
790 case IWM_UCODE_TLV_API_CHANGES_SET: 790 case IWM_UCODE_TLV_API_CHANGES_SET:
791 case IWM_UCODE_TLV_ENABLED_CAPABILITIES: 791 case IWM_UCODE_TLV_ENABLED_CAPABILITIES:
792 /* ignore, not used by current driver */ 792 /* ignore, not used by current driver */
793 break; 793 break;
794 794
795 default: 795 default:
796 DPRINTF(("%s: unknown firmware section %d, abort\n", 796 DPRINTF(("%s: unknown firmware section %d, abort\n",
797 DEVNAME(sc), tlv_type)); 797 DEVNAME(sc), tlv_type));
798 error = EINVAL; 798 error = EINVAL;
799 goto parse_out; 799 goto parse_out;
800 } 800 }
801 801
802 len -= roundup(tlv_len, 4); 802 len -= roundup(tlv_len, 4);
803 data += roundup(tlv_len, 4); 803 data += roundup(tlv_len, 4);
804 } 804 }
805 805
806 KASSERT(error == 0); 806 KASSERT(error == 0);
807 807
808 parse_out: 808 parse_out:
809 if (error) { 809 if (error) {
810 aprint_error_dev(sc->sc_dev, 810 aprint_error_dev(sc->sc_dev,
811 "firmware parse error, section type %d\n", tlv_type); 811 "firmware parse error, section type %d\n", tlv_type);
812 } 812 }
813 813
814 if (!(sc->sc_capaflags & IWM_UCODE_TLV_FLAGS_PM_CMD_SUPPORT)) { 814 if (!(sc->sc_capaflags & IWM_UCODE_TLV_FLAGS_PM_CMD_SUPPORT)) {
815 aprint_error_dev(sc->sc_dev, 815 aprint_error_dev(sc->sc_dev,
816 "device uses unsupported power ops\n"); 816 "device uses unsupported power ops\n");
817 error = ENOTSUP; 817 error = ENOTSUP;
818 } 818 }
819 819
820 out: 820 out:
821 if (error) 821 if (error)
822 fw->fw_status = IWM_FW_STATUS_NONE; 822 fw->fw_status = IWM_FW_STATUS_NONE;
823 else 823 else
824 fw->fw_status = IWM_FW_STATUS_DONE; 824 fw->fw_status = IWM_FW_STATUS_DONE;
825 wakeup(&sc->sc_fw); 825 wakeup(&sc->sc_fw);
826 826
827 if (error && fw->fw_rawdata != NULL) { 827 if (error && fw->fw_rawdata != NULL) {
828 kmem_free(fw->fw_rawdata, fw->fw_rawsize); 828 kmem_free(fw->fw_rawdata, fw->fw_rawsize);
829 fw->fw_rawdata = NULL; 829 fw->fw_rawdata = NULL;
830 CLR(sc->sc_flags, IWM_FLAG_FW_LOADED); 830 CLR(sc->sc_flags, IWM_FLAG_FW_LOADED);
831 } 831 }
832 return error; 832 return error;
833} 833}
834 834
835/* 835/*
836 * basic device access 836 * basic device access
837 */ 837 */
838 838
839static uint32_t 839static uint32_t
840iwm_read_prph(struct iwm_softc *sc, uint32_t addr) 840iwm_read_prph(struct iwm_softc *sc, uint32_t addr)
841{ 841{
842 IWM_WRITE(sc, 842 IWM_WRITE(sc,
843 IWM_HBUS_TARG_PRPH_RADDR, ((addr & 0x000fffff) | (3 << 24))); 843 IWM_HBUS_TARG_PRPH_RADDR, ((addr & 0x000fffff) | (3 << 24)));
844 IWM_BARRIER_READ_WRITE(sc); 844 IWM_BARRIER_READ_WRITE(sc);
845 return IWM_READ(sc, IWM_HBUS_TARG_PRPH_RDAT); 845 return IWM_READ(sc, IWM_HBUS_TARG_PRPH_RDAT);
846} 846}
847 847
848static void 848static void
849iwm_write_prph(struct iwm_softc *sc, uint32_t addr, uint32_t val) 849iwm_write_prph(struct iwm_softc *sc, uint32_t addr, uint32_t val)
850{ 850{
851 IWM_WRITE(sc, 851 IWM_WRITE(sc,
852 IWM_HBUS_TARG_PRPH_WADDR, ((addr & 0x000fffff) | (3 << 24))); 852 IWM_HBUS_TARG_PRPH_WADDR, ((addr & 0x000fffff) | (3 << 24)));
853 IWM_BARRIER_WRITE(sc); 853 IWM_BARRIER_WRITE(sc);
854 IWM_WRITE(sc, IWM_HBUS_TARG_PRPH_WDAT, val); 854 IWM_WRITE(sc, IWM_HBUS_TARG_PRPH_WDAT, val);
855} 855}
856 856
857#ifdef IWM_DEBUG 857#ifdef IWM_DEBUG
858/* iwlwifi: pcie/trans.c */ 858/* iwlwifi: pcie/trans.c */
859static int 859static int
860iwm_read_mem(struct iwm_softc *sc, uint32_t addr, void *buf, int dwords) 860iwm_read_mem(struct iwm_softc *sc, uint32_t addr, void *buf, int dwords)
861{ 861{
862 int offs, ret = 0; 862 int offs, ret = 0;
863 uint32_t *vals = buf; 863 uint32_t *vals = buf;
864 864
865 if (iwm_nic_lock(sc)) { 865 if (iwm_nic_lock(sc)) {
866 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_RADDR, addr); 866 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_RADDR, addr);
867 for (offs = 0; offs < dwords; offs++) 867 for (offs = 0; offs < dwords; offs++)
868 vals[offs] = IWM_READ(sc, IWM_HBUS_TARG_MEM_RDAT); 868 vals[offs] = IWM_READ(sc, IWM_HBUS_TARG_MEM_RDAT);
869 iwm_nic_unlock(sc); 869 iwm_nic_unlock(sc);
870 } else { 870 } else {
871 ret = EBUSY; 871 ret = EBUSY;
872 } 872 }
873 return ret; 873 return ret;
874} 874}
875#endif 875#endif
876 876
877/* iwlwifi: pcie/trans.c */ 877/* iwlwifi: pcie/trans.c */
878static int 878static int
879iwm_write_mem(struct iwm_softc *sc, uint32_t addr, const void *buf, int dwords) 879iwm_write_mem(struct iwm_softc *sc, uint32_t addr, const void *buf, int dwords)
880{ 880{
881 int offs; 881 int offs;
882 const uint32_t *vals = buf; 882 const uint32_t *vals = buf;
883 883
884 if (iwm_nic_lock(sc)) { 884 if (iwm_nic_lock(sc)) {
885 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WADDR, addr); 885 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WADDR, addr);
886 /* WADDR auto-increments */ 886 /* WADDR auto-increments */
887 for (offs = 0; offs < dwords; offs++) { 887 for (offs = 0; offs < dwords; offs++) {
888 uint32_t val = vals ? vals[offs] : 0; 888 uint32_t val = vals ? vals[offs] : 0;
889 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WDAT, val); 889 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WDAT, val);
890 } 890 }
891 iwm_nic_unlock(sc); 891 iwm_nic_unlock(sc);
892 } else { 892 } else {
893 DPRINTF(("%s: write_mem failed\n", DEVNAME(sc))); 893 DPRINTF(("%s: write_mem failed\n", DEVNAME(sc)));
894 return EBUSY; 894 return EBUSY;
895 } 895 }
896 return 0; 896 return 0;
897} 897}
898 898
899static int 899static int
900iwm_write_mem32(struct iwm_softc *sc, uint32_t addr, uint32_t val) 900iwm_write_mem32(struct iwm_softc *sc, uint32_t addr, uint32_t val)
901{ 901{
902 return iwm_write_mem(sc, addr, &val, 1); 902 return iwm_write_mem(sc, addr, &val, 1);
903} 903}
904 904
905static int 905static int
906iwm_poll_bit(struct iwm_softc *sc, int reg, 906iwm_poll_bit(struct iwm_softc *sc, int reg,
907 uint32_t bits, uint32_t mask, int timo) 907 uint32_t bits, uint32_t mask, int timo)
908{ 908{
909 for (;;) { 909 for (;;) {
910 if ((IWM_READ(sc, reg) & mask) == (bits & mask)) { 910 if ((IWM_READ(sc, reg) & mask) == (bits & mask)) {
911 return 1; 911 return 1;
912 } 912 }
913 if (timo < 10) { 913 if (timo < 10) {
914 return 0; 914 return 0;
915 } 915 }
916 timo -= 10; 916 timo -= 10;
917 DELAY(10); 917 DELAY(10);
918 } 918 }
919} 919}
920 920
921static int 921static int
922iwm_nic_lock(struct iwm_softc *sc) 922iwm_nic_lock(struct iwm_softc *sc)
923{ 923{
924 int rv = 0; 924 int rv = 0;
925 925
926 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL, 926 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL,
927 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 927 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
928 928
929 if (iwm_poll_bit(sc, IWM_CSR_GP_CNTRL, 929 if (iwm_poll_bit(sc, IWM_CSR_GP_CNTRL,
930 IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 930 IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
931 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY 931 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
932 | IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP, 15000)) { 932 | IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP, 15000)) {
933 rv = 1; 933 rv = 1;
934 } else { 934 } else {
935 /* jolt */ 935 /* jolt */
936 IWM_WRITE(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_FORCE_NMI); 936 IWM_WRITE(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_FORCE_NMI);
937 } 937 }
938 938
939 return rv; 939 return rv;
940} 940}
941 941
942static void 942static void
943iwm_nic_unlock(struct iwm_softc *sc) 943iwm_nic_unlock(struct iwm_softc *sc)
944{ 944{
945 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL, 945 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL,
946 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 946 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
947} 947}
948 948
949static void 949static void
950iwm_set_bits_mask_prph(struct iwm_softc *sc, 950iwm_set_bits_mask_prph(struct iwm_softc *sc,
951 uint32_t reg, uint32_t bits, uint32_t mask) 951 uint32_t reg, uint32_t bits, uint32_t mask)
952{ 952{
953 uint32_t val; 953 uint32_t val;
954 954
955 /* XXX: no error path? */ 955 /* XXX: no error path? */
956 if (iwm_nic_lock(sc)) { 956 if (iwm_nic_lock(sc)) {
957 val = iwm_read_prph(sc, reg) & mask; 957 val = iwm_read_prph(sc, reg) & mask;
958 val |= bits; 958 val |= bits;
959 iwm_write_prph(sc, reg, val); 959 iwm_write_prph(sc, reg, val);
960 iwm_nic_unlock(sc); 960 iwm_nic_unlock(sc);
961 } 961 }
962} 962}
963 963
964static void 964static void
965iwm_set_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits) 965iwm_set_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits)
966{ 966{
967 iwm_set_bits_mask_prph(sc, reg, bits, ~0); 967 iwm_set_bits_mask_prph(sc, reg, bits, ~0);
968} 968}
969 969
970static void 970static void
971iwm_clear_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits) 971iwm_clear_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits)
972{ 972{
973 iwm_set_bits_mask_prph(sc, reg, 0, ~bits); 973 iwm_set_bits_mask_prph(sc, reg, 0, ~bits);
974} 974}
975 975
976/* 976/*
977 * DMA resource routines 977 * DMA resource routines
978 */ 978 */
979 979
980static int 980static int
981iwm_dma_contig_alloc(bus_dma_tag_t tag, struct iwm_dma_info *dma, 981iwm_dma_contig_alloc(bus_dma_tag_t tag, struct iwm_dma_info *dma,
982 bus_size_t size, bus_size_t alignment) 982 bus_size_t size, bus_size_t alignment)
983{ 983{
984 int nsegs, error; 984 int nsegs, error;
985 void *va; 985 void *va;
986 986
987 dma->tag = tag; 987 dma->tag = tag;
988 dma->size = size; 988 dma->size = size;
989 989
990 error = bus_dmamap_create(tag, size, 1, size, 0, BUS_DMA_NOWAIT, 990 error = bus_dmamap_create(tag, size, 1, size, 0, BUS_DMA_NOWAIT,
991 &dma->map); 991 &dma->map);
992 if (error != 0) 992 if (error != 0)
993 goto fail; 993 goto fail;
994 994
995 error = bus_dmamem_alloc(tag, size, alignment, 0, &dma->seg, 1, &nsegs, 995 error = bus_dmamem_alloc(tag, size, alignment, 0, &dma->seg, 1, &nsegs,
996 BUS_DMA_NOWAIT); 996 BUS_DMA_NOWAIT);
997 if (error != 0) 997 if (error != 0)
998 goto fail; 998 goto fail;
999 999
1000 error = bus_dmamem_map(tag, &dma->seg, 1, size, &va, 1000 error = bus_dmamem_map(tag, &dma->seg, 1, size, &va,
1001 BUS_DMA_NOWAIT); 1001 BUS_DMA_NOWAIT);
1002 if (error != 0) 1002 if (error != 0)
1003 goto fail; 1003 goto fail;
1004 dma->vaddr = va; 1004 dma->vaddr = va;
1005 1005
1006 error = bus_dmamap_load(tag, dma->map, dma->vaddr, size, NULL, 1006 error = bus_dmamap_load(tag, dma->map, dma->vaddr, size, NULL,
1007 BUS_DMA_NOWAIT); 1007 BUS_DMA_NOWAIT);
1008 if (error != 0) 1008 if (error != 0)
1009 goto fail; 1009 goto fail;
1010 1010
1011 memset(dma->vaddr, 0, size); 1011 memset(dma->vaddr, 0, size);
1012 bus_dmamap_sync(tag, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 1012 bus_dmamap_sync(tag, dma->map, 0, size, BUS_DMASYNC_PREWRITE);
1013 dma->paddr = dma->map->dm_segs[0].ds_addr; 1013 dma->paddr = dma->map->dm_segs[0].ds_addr;
1014 1014
1015 return 0; 1015 return 0;
1016 1016
1017fail: iwm_dma_contig_free(dma); 1017fail: iwm_dma_contig_free(dma);
1018 return error; 1018 return error;
1019} 1019}
1020 1020
1021static void 1021static void
1022iwm_dma_contig_free(struct iwm_dma_info *dma) 1022iwm_dma_contig_free(struct iwm_dma_info *dma)
1023{ 1023{
1024 if (dma->map != NULL) { 1024 if (dma->map != NULL) {
1025 if (dma->vaddr != NULL) { 1025 if (dma->vaddr != NULL) {
1026 bus_dmamap_sync(dma->tag, dma->map, 0, dma->size, 1026 bus_dmamap_sync(dma->tag, dma->map, 0, dma->size,
1027 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1027 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1028 bus_dmamap_unload(dma->tag, dma->map); 1028 bus_dmamap_unload(dma->tag, dma->map);
1029 bus_dmamem_unmap(dma->tag, dma->vaddr, dma->size); 1029 bus_dmamem_unmap(dma->tag, dma->vaddr, dma->size);
1030 bus_dmamem_free(dma->tag, &dma->seg, 1); 1030 bus_dmamem_free(dma->tag, &dma->seg, 1);
1031 dma->vaddr = NULL; 1031 dma->vaddr = NULL;
1032 } 1032 }
1033 bus_dmamap_destroy(dma->tag, dma->map); 1033 bus_dmamap_destroy(dma->tag, dma->map);
1034 dma->map = NULL; 1034 dma->map = NULL;
1035 } 1035 }
1036} 1036}
1037 1037
1038/* fwmem is used to load firmware onto the card */ 1038/* fwmem is used to load firmware onto the card */
1039static int 1039static int
1040iwm_alloc_fwmem(struct iwm_softc *sc) 1040iwm_alloc_fwmem(struct iwm_softc *sc)
1041{ 1041{
1042 /* Must be aligned on a 16-byte boundary. */ 1042 /* Must be aligned on a 16-byte boundary. */
1043 return iwm_dma_contig_alloc(sc->sc_dmat, &sc->fw_dma, 1043 return iwm_dma_contig_alloc(sc->sc_dmat, &sc->fw_dma,
1044 sc->sc_fwdmasegsz, 16); 1044 sc->sc_fwdmasegsz, 16);
1045} 1045}
1046 1046
1047static void 1047static void
1048iwm_free_fwmem(struct iwm_softc *sc) 1048iwm_free_fwmem(struct iwm_softc *sc)
1049{ 1049{
1050 iwm_dma_contig_free(&sc->fw_dma); 1050 iwm_dma_contig_free(&sc->fw_dma);
1051} 1051}
1052 1052
1053/* tx scheduler rings. not used? */ 1053/* tx scheduler rings. not used? */
1054static int 1054static int
1055iwm_alloc_sched(struct iwm_softc *sc) 1055iwm_alloc_sched(struct iwm_softc *sc)
1056{ 1056{
1057 int rv; 1057 int rv;
1058 1058
1059 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1059 /* TX scheduler rings must be aligned on a 1KB boundary. */
1060 rv = iwm_dma_contig_alloc(sc->sc_dmat, &sc->sched_dma, 1060 rv = iwm_dma_contig_alloc(sc->sc_dmat, &sc->sched_dma,
1061 __arraycount(sc->txq) * sizeof(struct iwm_agn_scd_bc_tbl), 1024); 1061 __arraycount(sc->txq) * sizeof(struct iwm_agn_scd_bc_tbl), 1024);
1062 return rv; 1062 return rv;
1063} 1063}
1064 1064
1065static void 1065static void
1066iwm_free_sched(struct iwm_softc *sc) 1066iwm_free_sched(struct iwm_softc *sc)
1067{ 1067{
1068 iwm_dma_contig_free(&sc->sched_dma); 1068 iwm_dma_contig_free(&sc->sched_dma);
1069} 1069}
1070 1070
1071/* keep-warm page is used internally by the card. see iwl-fh.h for more info */ 1071/* keep-warm page is used internally by the card. see iwl-fh.h for more info */
1072static int 1072static int
1073iwm_alloc_kw(struct iwm_softc *sc) 1073iwm_alloc_kw(struct iwm_softc *sc)
1074{ 1074{
1075 return iwm_dma_contig_alloc(sc->sc_dmat, &sc->kw_dma, 4096, 4096); 1075 return iwm_dma_contig_alloc(sc->sc_dmat, &sc->kw_dma, 4096, 4096);
1076} 1076}
1077 1077
1078static void 1078static void
1079iwm_free_kw(struct iwm_softc *sc) 1079iwm_free_kw(struct iwm_softc *sc)
1080{ 1080{
1081 iwm_dma_contig_free(&sc->kw_dma); 1081 iwm_dma_contig_free(&sc->kw_dma);
1082} 1082}
1083 1083
1084/* interrupt cause table */ 1084/* interrupt cause table */
1085static int 1085static int
1086iwm_alloc_ict(struct iwm_softc *sc) 1086iwm_alloc_ict(struct iwm_softc *sc)
1087{ 1087{
1088 return iwm_dma_contig_alloc(sc->sc_dmat, &sc->ict_dma, 1088 return iwm_dma_contig_alloc(sc->sc_dmat, &sc->ict_dma,
1089 IWM_ICT_SIZE, 1<<IWM_ICT_PADDR_SHIFT); 1089 IWM_ICT_SIZE, 1<<IWM_ICT_PADDR_SHIFT);
1090} 1090}
1091 1091
1092static void 1092static void
1093iwm_free_ict(struct iwm_softc *sc) 1093iwm_free_ict(struct iwm_softc *sc)
1094{ 1094{
1095 iwm_dma_contig_free(&sc->ict_dma); 1095 iwm_dma_contig_free(&sc->ict_dma);
1096} 1096}
1097 1097
1098static int 1098static int
1099iwm_alloc_rx_ring(struct iwm_softc *sc, struct iwm_rx_ring *ring) 1099iwm_alloc_rx_ring(struct iwm_softc *sc, struct iwm_rx_ring *ring)
1100{ 1100{
1101 bus_size_t size; 1101 bus_size_t size;
1102 int i, error; 1102 int i, error;
1103 1103
1104 ring->cur = 0; 1104 ring->cur = 0;
1105 1105
1106 /* Allocate RX descriptors (256-byte aligned). */ 1106 /* Allocate RX descriptors (256-byte aligned). */
1107 size = IWM_RX_RING_COUNT * sizeof(uint32_t); 1107 size = IWM_RX_RING_COUNT * sizeof(uint32_t);
@@ -5607,1398 +5607,1386 @@ iwm_endscan_cb(struct work *work __unuse @@ -5607,1398 +5607,1386 @@ iwm_endscan_cb(struct work *work __unuse
5607 int done; 5607 int done;
5608 5608
5609 DPRINTF(("scan ended\n")); 5609 DPRINTF(("scan ended\n"));
5610 5610
5611 if (sc->sc_scanband == IEEE80211_CHAN_2GHZ && 5611 if (sc->sc_scanband == IEEE80211_CHAN_2GHZ &&
5612 sc->sc_nvm.sku_cap_band_52GHz_enable) { 5612 sc->sc_nvm.sku_cap_band_52GHz_enable) {
5613 int error; 5613 int error;
5614 done = 0; 5614 done = 0;
5615 if ((error = iwm_mvm_scan_request(sc, 5615 if ((error = iwm_mvm_scan_request(sc,
5616 IEEE80211_CHAN_5GHZ, ic->ic_des_esslen != 0, 5616 IEEE80211_CHAN_5GHZ, ic->ic_des_esslen != 0,
5617 ic->ic_des_essid, ic->ic_des_esslen)) != 0) { 5617 ic->ic_des_essid, ic->ic_des_esslen)) != 0) {
5618 DPRINTF(("%s: could not initiate scan\n", DEVNAME(sc))); 5618 DPRINTF(("%s: could not initiate scan\n", DEVNAME(sc)));
5619 done = 1; 5619 done = 1;
5620 } 5620 }
5621 } else { 5621 } else {
5622 done = 1; 5622 done = 1;
5623 } 5623 }
5624 5624
5625 if (done) { 5625 if (done) {
5626 if (!sc->sc_scanband) { 5626 if (!sc->sc_scanband) {
5627 ieee80211_cancel_scan(ic); 5627 ieee80211_cancel_scan(ic);
5628 } else { 5628 } else {
5629 ieee80211_end_scan(ic); 5629 ieee80211_end_scan(ic);
5630 } 5630 }
5631 sc->sc_scanband = 0; 5631 sc->sc_scanband = 0;
5632 } 5632 }
5633} 5633}
5634 5634
5635static int 5635static int
5636iwm_init_hw(struct iwm_softc *sc) 5636iwm_init_hw(struct iwm_softc *sc)
5637{ 5637{
5638 struct ieee80211com *ic = &sc->sc_ic; 5638 struct ieee80211com *ic = &sc->sc_ic;
5639 int error, i, qid; 5639 int error, i, qid;
5640 5640
5641 if ((error = iwm_preinit(sc)) != 0) 5641 if ((error = iwm_preinit(sc)) != 0)
5642 return error; 5642 return error;
5643 5643
5644 if ((error = iwm_start_hw(sc)) != 0) 5644 if ((error = iwm_start_hw(sc)) != 0)
5645 return error; 5645 return error;
5646 5646
5647 if ((error = iwm_run_init_mvm_ucode(sc, 0)) != 0) { 5647 if ((error = iwm_run_init_mvm_ucode(sc, 0)) != 0) {
5648 return error; 5648 return error;
5649 } 5649 }
5650 5650
5651 /* 5651 /*
5652 * should stop and start HW since that INIT 5652 * should stop and start HW since that INIT
5653 * image just loaded 5653 * image just loaded
5654 */ 5654 */
5655 iwm_stop_device(sc); 5655 iwm_stop_device(sc);
5656 if ((error = iwm_start_hw(sc)) != 0) { 5656 if ((error = iwm_start_hw(sc)) != 0) {
5657 aprint_error_dev(sc->sc_dev, "could not initialize hardware\n"); 5657 aprint_error_dev(sc->sc_dev, "could not initialize hardware\n");
5658 return error; 5658 return error;
5659 } 5659 }
5660 5660
5661 /* omstart, this time with the regular firmware */ 5661 /* omstart, this time with the regular firmware */
5662 error = iwm_mvm_load_ucode_wait_alive(sc, IWM_UCODE_TYPE_REGULAR); 5662 error = iwm_mvm_load_ucode_wait_alive(sc, IWM_UCODE_TYPE_REGULAR);
5663 if (error) { 5663 if (error) {
5664 aprint_error_dev(sc->sc_dev, "could not load firmware\n"); 5664 aprint_error_dev(sc->sc_dev, "could not load firmware\n");
5665 goto error; 5665 goto error;
5666 } 5666 }
5667 5667
5668 if ((error = iwm_send_tx_ant_cfg(sc, IWM_FW_VALID_TX_ANT(sc))) != 0) 5668 if ((error = iwm_send_tx_ant_cfg(sc, IWM_FW_VALID_TX_ANT(sc))) != 0)
5669 goto error; 5669 goto error;
5670 5670
5671 /* Send phy db control command and then phy db calibration*/ 5671 /* Send phy db control command and then phy db calibration*/
5672 if ((error = iwm_send_phy_db_data(sc)) != 0) 5672 if ((error = iwm_send_phy_db_data(sc)) != 0)
5673 goto error; 5673 goto error;
5674 5674
5675 if ((error = iwm_send_phy_cfg_cmd(sc)) != 0) 5675 if ((error = iwm_send_phy_cfg_cmd(sc)) != 0)
5676 goto error; 5676 goto error;
5677 5677
5678 /* Add auxiliary station for scanning */ 5678 /* Add auxiliary station for scanning */
5679 if ((error = iwm_mvm_add_aux_sta(sc)) != 0) 5679 if ((error = iwm_mvm_add_aux_sta(sc)) != 0)
5680 goto error; 5680 goto error;
5681 5681
5682 for (i = 0; i < IWM_NUM_PHY_CTX; i++) { 5682 for (i = 0; i < IWM_NUM_PHY_CTX; i++) {
5683 /* 5683 /*
5684 * The channel used here isn't relevant as it's 5684 * The channel used here isn't relevant as it's
5685 * going to be overwritten in the other flows. 5685 * going to be overwritten in the other flows.
5686 * For now use the first channel we have. 5686 * For now use the first channel we have.
5687 */ 5687 */
5688 if ((error = iwm_mvm_phy_ctxt_add(sc, 5688 if ((error = iwm_mvm_phy_ctxt_add(sc,
5689 &sc->sc_phyctxt[i], &ic->ic_channels[1], 1, 1)) != 0) 5689 &sc->sc_phyctxt[i], &ic->ic_channels[1], 1, 1)) != 0)
5690 goto error; 5690 goto error;
5691 } 5691 }
5692 5692
5693 error = iwm_mvm_power_update_device(sc); 5693 error = iwm_mvm_power_update_device(sc);
5694 if (error) 5694 if (error)
5695 goto error; 5695 goto error;
5696 5696
5697 /* Mark TX rings as active. */ 5697 /* Mark TX rings as active. */
5698 for (qid = 0; qid < 4; qid++) { 5698 for (qid = 0; qid < 4; qid++) {
5699 iwm_enable_txq(sc, qid, qid); 5699 iwm_enable_txq(sc, qid, qid);
5700 } 5700 }
5701 5701
5702 return 0; 5702 return 0;
5703 5703
5704 error: 5704 error:
5705 iwm_stop_device(sc); 5705 iwm_stop_device(sc);
5706 return error; 5706 return error;
5707} 5707}
5708 5708
5709/* Allow multicast from our BSSID. */ 5709/* Allow multicast from our BSSID. */
5710static int 5710static int
5711iwm_allow_mcast(struct iwm_softc *sc) 5711iwm_allow_mcast(struct iwm_softc *sc)
5712{ 5712{
5713 struct ieee80211com *ic = &sc->sc_ic; 5713 struct ieee80211com *ic = &sc->sc_ic;
5714 struct ieee80211_node *ni = ic->ic_bss; 5714 struct ieee80211_node *ni = ic->ic_bss;
5715 struct iwm_mcast_filter_cmd *cmd; 5715 struct iwm_mcast_filter_cmd *cmd;
5716 size_t size; 5716 size_t size;
5717 int error; 5717 int error;
5718 5718
5719 size = roundup(sizeof(*cmd), 4); 5719 size = roundup(sizeof(*cmd), 4);
5720 cmd = kmem_intr_zalloc(size, KM_NOSLEEP); 5720 cmd = kmem_intr_zalloc(size, KM_NOSLEEP);
5721 if (cmd == NULL) 5721 if (cmd == NULL)
5722 return ENOMEM; 5722 return ENOMEM;
5723 cmd->filter_own = 1; 5723 cmd->filter_own = 1;
5724 cmd->port_id = 0; 5724 cmd->port_id = 0;
5725 cmd->count = 0; 5725 cmd->count = 0;
5726 cmd->pass_all = 1; 5726 cmd->pass_all = 1;
5727 IEEE80211_ADDR_COPY(cmd->bssid, ni->ni_bssid); 5727 IEEE80211_ADDR_COPY(cmd->bssid, ni->ni_bssid);
5728 5728
5729 error = iwm_mvm_send_cmd_pdu(sc, IWM_MCAST_FILTER_CMD, 5729 error = iwm_mvm_send_cmd_pdu(sc, IWM_MCAST_FILTER_CMD,
5730 IWM_CMD_SYNC, size, cmd); 5730 IWM_CMD_SYNC, size, cmd);
5731 kmem_intr_free(cmd, size); 5731 kmem_intr_free(cmd, size);
5732 return error; 5732 return error;
5733} 5733}
5734 5734
5735/* 5735/*
5736 * ifnet interfaces 5736 * ifnet interfaces
5737 */ 5737 */
5738 5738
5739static int 5739static int
5740iwm_init(struct ifnet *ifp) 5740iwm_init(struct ifnet *ifp)
5741{ 5741{
5742 struct iwm_softc *sc = ifp->if_softc; 5742 struct iwm_softc *sc = ifp->if_softc;
5743 int error; 5743 int error;
5744 5744
5745 if (sc->sc_flags & IWM_FLAG_HW_INITED) { 5745 if (sc->sc_flags & IWM_FLAG_HW_INITED) {
5746 return 0; 5746 return 0;
5747 } 5747 }
5748 sc->sc_generation++; 5748 sc->sc_generation++;
5749 sc->sc_flags &= ~IWM_FLAG_STOPPED; 5749 sc->sc_flags &= ~IWM_FLAG_STOPPED;
5750 5750
5751 if ((error = iwm_init_hw(sc)) != 0) { 5751 if ((error = iwm_init_hw(sc)) != 0) {
5752 iwm_stop(ifp, 1); 5752 iwm_stop(ifp, 1);
5753 return error; 5753 return error;
5754 } 5754 }
5755 5755
5756 /* 5756 /*
5757 * Ok, firmware loaded and we are jogging 5757 * Ok, firmware loaded and we are jogging
5758 */ 5758 */
5759 5759
5760 ifp->if_flags &= ~IFF_OACTIVE; 5760 ifp->if_flags &= ~IFF_OACTIVE;
5761 ifp->if_flags |= IFF_RUNNING; 5761 ifp->if_flags |= IFF_RUNNING;
5762 5762
5763 ieee80211_begin_scan(&sc->sc_ic, 0); 5763 ieee80211_begin_scan(&sc->sc_ic, 0);
5764 sc->sc_flags |= IWM_FLAG_HW_INITED; 5764 sc->sc_flags |= IWM_FLAG_HW_INITED;
5765 5765
5766 return 0; 5766 return 0;
5767} 5767}
5768 5768
5769/* 5769/*
5770 * Dequeue packets from sendq and call send. 5770 * Dequeue packets from sendq and call send.
5771 * mostly from iwn 5771 * mostly from iwn
5772 */ 5772 */
5773static void 5773static void
5774iwm_start(struct ifnet *ifp) 5774iwm_start(struct ifnet *ifp)
5775{ 5775{
5776 struct iwm_softc *sc = ifp->if_softc; 5776 struct iwm_softc *sc = ifp->if_softc;
5777 struct ieee80211com *ic = &sc->sc_ic; 5777 struct ieee80211com *ic = &sc->sc_ic;
5778 struct ieee80211_node *ni; 5778 struct ieee80211_node *ni;
5779 struct ether_header *eh; 5779 struct ether_header *eh;
5780 struct mbuf *m; 5780 struct mbuf *m;
5781 int ac; 5781 int ac;
5782 5782
5783 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 5783 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
5784 return; 5784 return;
5785 5785
5786 for (;;) { 5786 for (;;) {
5787 /* why isn't this done per-queue? */ 5787 /* why isn't this done per-queue? */
5788 if (sc->qfullmsk != 0) { 5788 if (sc->qfullmsk != 0) {
5789 ifp->if_flags |= IFF_OACTIVE; 5789 ifp->if_flags |= IFF_OACTIVE;
5790 break; 5790 break;
5791 } 5791 }
5792 5792
5793 /* need to send management frames even if we're not RUNning */ 5793 /* need to send management frames even if we're not RUNning */
5794 IF_DEQUEUE(&ic->ic_mgtq, m); 5794 IF_DEQUEUE(&ic->ic_mgtq, m);
5795 if (m) { 5795 if (m) {
5796 ni = (void *)m->m_pkthdr.rcvif; 5796 ni = (void *)m->m_pkthdr.rcvif;
5797 ac = 0; 5797 ac = 0;
5798 goto sendit; 5798 goto sendit;
5799 } 5799 }
5800 if (ic->ic_state != IEEE80211_S_RUN) { 5800 if (ic->ic_state != IEEE80211_S_RUN) {
5801 break; 5801 break;
5802 } 5802 }
5803 5803
5804 IFQ_DEQUEUE(&ifp->if_snd, m); 5804 IFQ_DEQUEUE(&ifp->if_snd, m);
5805 if (!m) 5805 if (!m)
5806 break; 5806 break;
5807 if (m->m_len < sizeof (*eh) && 5807 if (m->m_len < sizeof (*eh) &&
5808 (m = m_pullup(m, sizeof (*eh))) == NULL) { 5808 (m = m_pullup(m, sizeof (*eh))) == NULL) {
5809 ifp->if_oerrors++; 5809 ifp->if_oerrors++;
5810 continue; 5810 continue;
5811 } 5811 }
5812 if (ifp->if_bpf != NULL) 5812 if (ifp->if_bpf != NULL)
5813 bpf_mtap(ifp, m); 5813 bpf_mtap(ifp, m);
5814 5814
5815 eh = mtod(m, struct ether_header *); 5815 eh = mtod(m, struct ether_header *);
5816 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 5816 ni = ieee80211_find_txnode(ic, eh->ether_dhost);
5817 if (ni == NULL) { 5817 if (ni == NULL) {
5818 m_freem(m); 5818 m_freem(m);
5819 ifp->if_oerrors++; 5819 ifp->if_oerrors++;
5820 continue; 5820 continue;
5821 } 5821 }
5822 /* classify mbuf so we can find which tx ring to use */ 5822 /* classify mbuf so we can find which tx ring to use */
5823 if (ieee80211_classify(ic, m, ni) != 0) { 5823 if (ieee80211_classify(ic, m, ni) != 0) {
5824 m_freem(m); 5824 m_freem(m);
5825 ieee80211_free_node(ni); 5825 ieee80211_free_node(ni);
5826 ifp->if_oerrors++; 5826 ifp->if_oerrors++;
5827 continue; 5827 continue;
5828 } 5828 }
5829 5829
5830 /* No QoS encapsulation for EAPOL frames. */ 5830 /* No QoS encapsulation for EAPOL frames. */
5831 ac = (eh->ether_type != htons(ETHERTYPE_PAE)) ? 5831 ac = (eh->ether_type != htons(ETHERTYPE_PAE)) ?
5832 M_WME_GETAC(m) : WME_AC_BE; 5832 M_WME_GETAC(m) : WME_AC_BE;
5833 5833
5834 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 5834 if ((m = ieee80211_encap(ic, m, ni)) == NULL) {
5835 ieee80211_free_node(ni); 5835 ieee80211_free_node(ni);
5836 ifp->if_oerrors++; 5836 ifp->if_oerrors++;
5837 continue; 5837 continue;
5838 } 5838 }
5839 5839
5840 sendit: 5840 sendit:
5841 if (ic->ic_rawbpf != NULL) 5841 if (ic->ic_rawbpf != NULL)
5842 bpf_mtap3(ic->ic_rawbpf, m); 5842 bpf_mtap3(ic->ic_rawbpf, m);
5843 if (iwm_tx(sc, m, ni, ac) != 0) { 5843 if (iwm_tx(sc, m, ni, ac) != 0) {
5844 ieee80211_free_node(ni); 5844 ieee80211_free_node(ni);
5845 ifp->if_oerrors++; 5845 ifp->if_oerrors++;
5846 continue; 5846 continue;
5847 } 5847 }
5848 5848
5849 if (ifp->if_flags & IFF_UP) { 5849 if (ifp->if_flags & IFF_UP) {
5850 sc->sc_tx_timer = 15; 5850 sc->sc_tx_timer = 15;
5851 ifp->if_timer = 1; 5851 ifp->if_timer = 1;
5852 } 5852 }
5853 } 5853 }
5854 5854
5855 return; 5855 return;
5856} 5856}
5857 5857
5858static void 5858static void
5859iwm_stop(struct ifnet *ifp, int disable) 5859iwm_stop(struct ifnet *ifp, int disable)
5860{ 5860{
5861 struct iwm_softc *sc = ifp->if_softc; 5861 struct iwm_softc *sc = ifp->if_softc;
5862 struct ieee80211com *ic = &sc->sc_ic; 5862 struct ieee80211com *ic = &sc->sc_ic;
5863 5863
5864 sc->sc_flags &= ~IWM_FLAG_HW_INITED; 5864 sc->sc_flags &= ~IWM_FLAG_HW_INITED;
5865 sc->sc_flags |= IWM_FLAG_STOPPED; 5865 sc->sc_flags |= IWM_FLAG_STOPPED;
5866 sc->sc_generation++; 5866 sc->sc_generation++;
5867 sc->sc_scanband = 0; 5867 sc->sc_scanband = 0;
5868 sc->sc_auth_prot = 0; 5868 sc->sc_auth_prot = 0;
5869 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5869 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
5870 5870
5871 if (ic->ic_state != IEEE80211_S_INIT) 5871 if (ic->ic_state != IEEE80211_S_INIT)
5872 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 5872 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
5873 5873
5874 callout_stop(&sc->sc_calib_to); 5874 callout_stop(&sc->sc_calib_to);
5875 ifp->if_timer = sc->sc_tx_timer = 0; 5875 ifp->if_timer = sc->sc_tx_timer = 0;
5876 iwm_stop_device(sc); 5876 iwm_stop_device(sc);
5877} 5877}
5878 5878
5879static void 5879static void
5880iwm_watchdog(struct ifnet *ifp) 5880iwm_watchdog(struct ifnet *ifp)
5881{ 5881{
5882 struct iwm_softc *sc = ifp->if_softc; 5882 struct iwm_softc *sc = ifp->if_softc;
5883 5883
5884 ifp->if_timer = 0; 5884 ifp->if_timer = 0;
5885 if (sc->sc_tx_timer > 0) { 5885 if (sc->sc_tx_timer > 0) {
5886 if (--sc->sc_tx_timer == 0) { 5886 if (--sc->sc_tx_timer == 0) {
5887 aprint_error_dev(sc->sc_dev, "device timeout\n"); 5887 aprint_error_dev(sc->sc_dev, "device timeout\n");
5888#ifdef IWM_DEBUG 5888#ifdef IWM_DEBUG
5889 iwm_nic_error(sc); 5889 iwm_nic_error(sc);
5890#endif 5890#endif
5891 ifp->if_flags &= ~IFF_UP; 5891 ifp->if_flags &= ~IFF_UP;
5892 iwm_stop(ifp, 1); 5892 iwm_stop(ifp, 1);
5893 ifp->if_oerrors++; 5893 ifp->if_oerrors++;
5894 return; 5894 return;
5895 } 5895 }
5896 ifp->if_timer = 1; 5896 ifp->if_timer = 1;
5897 } 5897 }
5898 5898
5899 ieee80211_watchdog(&sc->sc_ic); 5899 ieee80211_watchdog(&sc->sc_ic);
5900} 5900}
5901 5901
5902static int 5902static int
5903iwm_ioctl(struct ifnet *ifp, u_long cmd, void *data) 5903iwm_ioctl(struct ifnet *ifp, u_long cmd, void *data)
5904{ 5904{
5905 struct iwm_softc *sc = ifp->if_softc; 5905 struct iwm_softc *sc = ifp->if_softc;
5906 struct ieee80211com *ic = &sc->sc_ic; 5906 struct ieee80211com *ic = &sc->sc_ic;
5907 const struct sockaddr *sa; 5907 const struct sockaddr *sa;
5908 int s, error = 0; 5908 int s, error = 0;
5909 5909
5910 s = splnet(); 5910 s = splnet();
5911 5911
5912 switch (cmd) { 5912 switch (cmd) {
5913 case SIOCSIFADDR: 5913 case SIOCSIFADDR:
5914 ifp->if_flags |= IFF_UP; 5914 ifp->if_flags |= IFF_UP;
5915 /* FALLTHROUGH */ 5915 /* FALLTHROUGH */
5916 case SIOCSIFFLAGS: 5916 case SIOCSIFFLAGS:
5917 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 5917 if ((error = ifioctl_common(ifp, cmd, data)) != 0)
5918 break; 5918 break;
5919 if (ifp->if_flags & IFF_UP) { 5919 if (ifp->if_flags & IFF_UP) {
5920 if (!(ifp->if_flags & IFF_RUNNING)) { 5920 if (!(ifp->if_flags & IFF_RUNNING)) {
5921 if ((error = iwm_init(ifp)) != 0) 5921 if ((error = iwm_init(ifp)) != 0)
5922 ifp->if_flags &= ~IFF_UP; 5922 ifp->if_flags &= ~IFF_UP;
5923 } 5923 }
5924 } else { 5924 } else {
5925 if (ifp->if_flags & IFF_RUNNING) 5925 if (ifp->if_flags & IFF_RUNNING)
5926 iwm_stop(ifp, 1); 5926 iwm_stop(ifp, 1);
5927 } 5927 }
5928 break; 5928 break;
5929 5929
5930 case SIOCADDMULTI: 5930 case SIOCADDMULTI:
5931 case SIOCDELMULTI: 5931 case SIOCDELMULTI:
5932 if (!ISSET(sc->sc_flags, IWM_FLAG_ATTACHED)) { 5932 if (!ISSET(sc->sc_flags, IWM_FLAG_ATTACHED)) {
5933 error = ENXIO; 5933 error = ENXIO;
5934 break; 5934 break;
5935 } 5935 }
5936 sa = ifreq_getaddr(SIOCADDMULTI, (struct ifreq *)data); 5936 sa = ifreq_getaddr(SIOCADDMULTI, (struct ifreq *)data);
5937 error = (cmd == SIOCADDMULTI) ? 5937 error = (cmd == SIOCADDMULTI) ?
5938 ether_addmulti(sa, &sc->sc_ec) : 5938 ether_addmulti(sa, &sc->sc_ec) :
5939 ether_delmulti(sa, &sc->sc_ec); 5939 ether_delmulti(sa, &sc->sc_ec);
5940 if (error == ENETRESET) 5940 if (error == ENETRESET)
5941 error = 0; 5941 error = 0;
5942 break; 5942 break;
5943 5943
5944 default: 5944 default:
5945 if (!ISSET(sc->sc_flags, IWM_FLAG_ATTACHED)) { 5945 if (!ISSET(sc->sc_flags, IWM_FLAG_ATTACHED)) {
5946 error = ether_ioctl(ifp, cmd, data); 5946 error = ether_ioctl(ifp, cmd, data);
5947 break; 5947 break;
5948 } 5948 }
5949 error = ieee80211_ioctl(ic, cmd, data); 5949 error = ieee80211_ioctl(ic, cmd, data);
5950 break; 5950 break;
5951 } 5951 }
5952 5952
5953 if (error == ENETRESET) { 5953 if (error == ENETRESET) {
5954 error = 0; 5954 error = 0;
5955 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 5955 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
5956 (IFF_UP | IFF_RUNNING)) { 5956 (IFF_UP | IFF_RUNNING)) {
5957 iwm_stop(ifp, 0); 5957 iwm_stop(ifp, 0);
5958 error = iwm_init(ifp); 5958 error = iwm_init(ifp);
5959 } 5959 }
5960 } 5960 }
5961 5961
5962 splx(s); 5962 splx(s);
5963 return error; 5963 return error;
5964} 5964}
5965 5965
5966/* 5966/*
5967 * The interrupt side of things 5967 * The interrupt side of things
5968 */ 5968 */
5969 5969
5970/* 5970/*
5971 * error dumping routines are from iwlwifi/mvm/utils.c 5971 * error dumping routines are from iwlwifi/mvm/utils.c
5972 */ 5972 */
5973 5973
5974/* 5974/*
5975 * Note: This structure is read from the device with IO accesses, 5975 * Note: This structure is read from the device with IO accesses,
5976 * and the reading already does the endian conversion. As it is 5976 * and the reading already does the endian conversion. As it is
5977 * read with uint32_t-sized accesses, any members with a different size 5977 * read with uint32_t-sized accesses, any members with a different size
5978 * need to be ordered correctly though! 5978 * need to be ordered correctly though!
5979 */ 5979 */
5980struct iwm_error_event_table { 5980struct iwm_error_event_table {
5981 uint32_t valid; /* (nonzero) valid, (0) log is empty */ 5981 uint32_t valid; /* (nonzero) valid, (0) log is empty */
5982 uint32_t error_id; /* type of error */ 5982 uint32_t error_id; /* type of error */
5983 uint32_t pc; /* program counter */ 5983 uint32_t pc; /* program counter */
5984 uint32_t blink1; /* branch link */ 5984 uint32_t blink1; /* branch link */
5985 uint32_t blink2; /* branch link */ 5985 uint32_t blink2; /* branch link */
5986 uint32_t ilink1; /* interrupt link */ 5986 uint32_t ilink1; /* interrupt link */
5987 uint32_t ilink2; /* interrupt link */ 5987 uint32_t ilink2; /* interrupt link */
5988 uint32_t data1; /* error-specific data */ 5988 uint32_t data1; /* error-specific data */
5989 uint32_t data2; /* error-specific data */ 5989 uint32_t data2; /* error-specific data */
5990 uint32_t data3; /* error-specific data */ 5990 uint32_t data3; /* error-specific data */
5991 uint32_t bcon_time; /* beacon timer */ 5991 uint32_t bcon_time; /* beacon timer */
5992 uint32_t tsf_low; /* network timestamp function timer */ 5992 uint32_t tsf_low; /* network timestamp function timer */
5993 uint32_t tsf_hi; /* network timestamp function timer */ 5993 uint32_t tsf_hi; /* network timestamp function timer */
5994 uint32_t gp1; /* GP1 timer register */ 5994 uint32_t gp1; /* GP1 timer register */
5995 uint32_t gp2; /* GP2 timer register */ 5995 uint32_t gp2; /* GP2 timer register */
5996 uint32_t gp3; /* GP3 timer register */ 5996 uint32_t gp3; /* GP3 timer register */
5997 uint32_t ucode_ver; /* uCode version */ 5997 uint32_t ucode_ver; /* uCode version */
5998 uint32_t hw_ver; /* HW Silicon version */ 5998 uint32_t hw_ver; /* HW Silicon version */
5999 uint32_t brd_ver; /* HW board version */ 5999 uint32_t brd_ver; /* HW board version */
6000 uint32_t log_pc; /* log program counter */ 6000 uint32_t log_pc; /* log program counter */
6001 uint32_t frame_ptr; /* frame pointer */ 6001 uint32_t frame_ptr; /* frame pointer */
6002 uint32_t stack_ptr; /* stack pointer */ 6002 uint32_t stack_ptr; /* stack pointer */
6003 uint32_t hcmd; /* last host command header */ 6003 uint32_t hcmd; /* last host command header */
6004 uint32_t isr0; /* isr status register LMPM_NIC_ISR0: 6004 uint32_t isr0; /* isr status register LMPM_NIC_ISR0:
6005 * rxtx_flag */ 6005 * rxtx_flag */
6006 uint32_t isr1; /* isr status register LMPM_NIC_ISR1: 6006 uint32_t isr1; /* isr status register LMPM_NIC_ISR1:
6007 * host_flag */ 6007 * host_flag */
6008 uint32_t isr2; /* isr status register LMPM_NIC_ISR2: 6008 uint32_t isr2; /* isr status register LMPM_NIC_ISR2:
6009 * enc_flag */ 6009 * enc_flag */
6010 uint32_t isr3; /* isr status register LMPM_NIC_ISR3: 6010 uint32_t isr3; /* isr status register LMPM_NIC_ISR3:
6011 * time_flag */ 6011 * time_flag */
6012 uint32_t isr4; /* isr status register LMPM_NIC_ISR4: 6012 uint32_t isr4; /* isr status register LMPM_NIC_ISR4:
6013 * wico interrupt */ 6013 * wico interrupt */
6014 uint32_t isr_pref; /* isr status register LMPM_NIC_PREF_STAT */ 6014 uint32_t isr_pref; /* isr status register LMPM_NIC_PREF_STAT */
6015 uint32_t wait_event; /* wait event() caller address */ 6015 uint32_t wait_event; /* wait event() caller address */
6016 uint32_t l2p_control; /* L2pControlField */ 6016 uint32_t l2p_control; /* L2pControlField */
6017 uint32_t l2p_duration; /* L2pDurationField */ 6017 uint32_t l2p_duration; /* L2pDurationField */
6018 uint32_t l2p_mhvalid; /* L2pMhValidBits */ 6018 uint32_t l2p_mhvalid; /* L2pMhValidBits */
6019 uint32_t l2p_addr_match; /* L2pAddrMatchStat */ 6019 uint32_t l2p_addr_match; /* L2pAddrMatchStat */
6020 uint32_t lmpm_pmg_sel; /* indicate which clocks are turned on 6020 uint32_t lmpm_pmg_sel; /* indicate which clocks are turned on
6021 * (LMPM_PMG_SEL) */ 6021 * (LMPM_PMG_SEL) */
6022 uint32_t u_timestamp; /* indicate when the date and time of the 6022 uint32_t u_timestamp; /* indicate when the date and time of the
6023 * compilation */ 6023 * compilation */
6024 uint32_t flow_handler; /* FH read/write pointers, RX credit */ 6024 uint32_t flow_handler; /* FH read/write pointers, RX credit */
6025} __packed; 6025} __packed;
6026 6026
6027#define ERROR_START_OFFSET (1 * sizeof(uint32_t)) 6027#define ERROR_START_OFFSET (1 * sizeof(uint32_t))
6028#define ERROR_ELEM_SIZE (7 * sizeof(uint32_t)) 6028#define ERROR_ELEM_SIZE (7 * sizeof(uint32_t))
6029 6029
6030#ifdef IWM_DEBUG 6030#ifdef IWM_DEBUG
6031static const struct { 6031static const struct {
6032 const char *name; 6032 const char *name;
6033 uint8_t num; 6033 uint8_t num;
6034} advanced_lookup[] = { 6034} advanced_lookup[] = {
6035 { "NMI_INTERRUPT_WDG", 0x34 }, 6035 { "NMI_INTERRUPT_WDG", 0x34 },
6036 { "SYSASSERT", 0x35 }, 6036 { "SYSASSERT", 0x35 },
6037 { "UCODE_VERSION_MISMATCH", 0x37 }, 6037 { "UCODE_VERSION_MISMATCH", 0x37 },
6038 { "BAD_COMMAND", 0x38 }, 6038 { "BAD_COMMAND", 0x38 },
6039 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C }, 6039 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
6040 { "FATAL_ERROR", 0x3D }, 6040 { "FATAL_ERROR", 0x3D },
6041 { "NMI_TRM_HW_ERR", 0x46 }, 6041 { "NMI_TRM_HW_ERR", 0x46 },
6042 { "NMI_INTERRUPT_TRM", 0x4C }, 6042 { "NMI_INTERRUPT_TRM", 0x4C },
6043 { "NMI_INTERRUPT_BREAK_POINT", 0x54 }, 6043 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
6044 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C }, 6044 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
6045 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 }, 6045 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
6046 { "NMI_INTERRUPT_HOST", 0x66 }, 6046 { "NMI_INTERRUPT_HOST", 0x66 },
6047 { "NMI_INTERRUPT_ACTION_PT", 0x7C }, 6047 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
6048 { "NMI_INTERRUPT_UNKNOWN", 0x84 }, 6048 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
6049 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 }, 6049 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
6050 { "ADVANCED_SYSASSERT", 0 }, 6050 { "ADVANCED_SYSASSERT", 0 },
6051}; 6051};
6052 6052
6053static const char * 6053static const char *
6054iwm_desc_lookup(uint32_t num) 6054iwm_desc_lookup(uint32_t num)
6055{ 6055{
6056 int i; 6056 int i;
6057 6057
6058 for (i = 0; i < __arraycount(advanced_lookup) - 1; i++) 6058 for (i = 0; i < __arraycount(advanced_lookup) - 1; i++)
6059 if (advanced_lookup[i].num == num) 6059 if (advanced_lookup[i].num == num)
6060 return advanced_lookup[i].name; 6060 return advanced_lookup[i].name;
6061 6061
6062 /* No entry matches 'num', so it is the last: ADVANCED_SYSASSERT */ 6062 /* No entry matches 'num', so it is the last: ADVANCED_SYSASSERT */
6063 return advanced_lookup[i].name; 6063 return advanced_lookup[i].name;
6064} 6064}
6065 6065
6066/* 6066/*
6067 * Support for dumping the error log seemed like a good idea ... 6067 * Support for dumping the error log seemed like a good idea ...
6068 * but it's mostly hex junk and the only sensible thing is the 6068 * but it's mostly hex junk and the only sensible thing is the
6069 * hw/ucode revision (which we know anyway). Since it's here, 6069 * hw/ucode revision (which we know anyway). Since it's here,
6070 * I'll just leave it in, just in case e.g. the Intel guys want to 6070 * I'll just leave it in, just in case e.g. the Intel guys want to
6071 * help us decipher some "ADVANCED_SYSASSERT" later. 6071 * help us decipher some "ADVANCED_SYSASSERT" later.
6072 */ 6072 */
6073static void 6073static void
6074iwm_nic_error(struct iwm_softc *sc) 6074iwm_nic_error(struct iwm_softc *sc)
6075{ 6075{
6076 struct iwm_error_event_table table; 6076 struct iwm_error_event_table table;
6077 uint32_t base; 6077 uint32_t base;
6078 6078
6079 aprint_error_dev(sc->sc_dev, "dumping device error log\n"); 6079 aprint_error_dev(sc->sc_dev, "dumping device error log\n");
6080 base = sc->sc_uc.uc_error_event_table; 6080 base = sc->sc_uc.uc_error_event_table;
6081 if (base < 0x800000 || base >= 0x80C000) { 6081 if (base < 0x800000 || base >= 0x80C000) {
6082 aprint_error_dev(sc->sc_dev, 6082 aprint_error_dev(sc->sc_dev,
6083 "Not valid error log pointer 0x%08x\n", base); 6083 "Not valid error log pointer 0x%08x\n", base);
6084 return; 6084 return;
6085 } 6085 }
6086 6086
6087 if (iwm_read_mem(sc, base, &table, sizeof(table)/sizeof(uint32_t)) != 0) { 6087 if (iwm_read_mem(sc, base, &table, sizeof(table)/sizeof(uint32_t)) != 0) {
6088 aprint_error_dev(sc->sc_dev, "reading errlog failed\n"); 6088 aprint_error_dev(sc->sc_dev, "reading errlog failed\n");
6089 return; 6089 return;
6090 } 6090 }
6091 6091
6092 if (!table.valid) { 6092 if (!table.valid) {
6093 aprint_error_dev(sc->sc_dev, "errlog not found, skipping\n"); 6093 aprint_error_dev(sc->sc_dev, "errlog not found, skipping\n");
6094 return; 6094 return;
6095 } 6095 }
6096 6096
6097 if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) { 6097 if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
6098 aprint_error_dev(sc->sc_dev, "Start IWL Error Log Dump:\n"); 6098 aprint_error_dev(sc->sc_dev, "Start IWL Error Log Dump:\n");
6099 aprint_error_dev(sc->sc_dev, "Status: 0x%x, count: %d\n", 6099 aprint_error_dev(sc->sc_dev, "Status: 0x%x, count: %d\n",
6100 sc->sc_flags, table.valid); 6100 sc->sc_flags, table.valid);
6101 } 6101 }
6102 6102
6103 aprint_error_dev(sc->sc_dev, "%08X | %-28s\n", table.error_id, 6103 aprint_error_dev(sc->sc_dev, "%08X | %-28s\n", table.error_id,
6104 iwm_desc_lookup(table.error_id)); 6104 iwm_desc_lookup(table.error_id));
6105 aprint_error_dev(sc->sc_dev, "%08X | uPc\n", table.pc); 6105 aprint_error_dev(sc->sc_dev, "%08X | uPc\n", table.pc);
6106 aprint_error_dev(sc->sc_dev, "%08X | branchlink1\n", table.blink1); 6106 aprint_error_dev(sc->sc_dev, "%08X | branchlink1\n", table.blink1);
6107 aprint_error_dev(sc->sc_dev, "%08X | branchlink2\n", table.blink2); 6107 aprint_error_dev(sc->sc_dev, "%08X | branchlink2\n", table.blink2);
6108 aprint_error_dev(sc->sc_dev, "%08X | interruptlink1\n", table.ilink1); 6108 aprint_error_dev(sc->sc_dev, "%08X | interruptlink1\n", table.ilink1);
6109 aprint_error_dev(sc->sc_dev, "%08X | interruptlink2\n", table.ilink2); 6109 aprint_error_dev(sc->sc_dev, "%08X | interruptlink2\n", table.ilink2);
6110 aprint_error_dev(sc->sc_dev, "%08X | data1\n", table.data1); 6110 aprint_error_dev(sc->sc_dev, "%08X | data1\n", table.data1);
6111 aprint_error_dev(sc->sc_dev, "%08X | data2\n", table.data2); 6111 aprint_error_dev(sc->sc_dev, "%08X | data2\n", table.data2);
6112 aprint_error_dev(sc->sc_dev, "%08X | data3\n", table.data3); 6112 aprint_error_dev(sc->sc_dev, "%08X | data3\n", table.data3);
6113 aprint_error_dev(sc->sc_dev, "%08X | beacon time\n", table.bcon_time); 6113 aprint_error_dev(sc->sc_dev, "%08X | beacon time\n", table.bcon_time);
6114 aprint_error_dev(sc->sc_dev, "%08X | tsf low\n", table.tsf_low); 6114 aprint_error_dev(sc->sc_dev, "%08X | tsf low\n", table.tsf_low);
6115 aprint_error_dev(sc->sc_dev, "%08X | tsf hi\n", table.tsf_hi); 6115 aprint_error_dev(sc->sc_dev, "%08X | tsf hi\n", table.tsf_hi);
6116 aprint_error_dev(sc->sc_dev, "%08X | time gp1\n", table.gp1); 6116 aprint_error_dev(sc->sc_dev, "%08X | time gp1\n", table.gp1);
6117 aprint_error_dev(sc->sc_dev, "%08X | time gp2\n", table.gp2); 6117 aprint_error_dev(sc->sc_dev, "%08X | time gp2\n", table.gp2);
6118 aprint_error_dev(sc->sc_dev, "%08X | time gp3\n", table.gp3); 6118 aprint_error_dev(sc->sc_dev, "%08X | time gp3\n", table.gp3);
6119 aprint_error_dev(sc->sc_dev, "%08X | uCode version\n", table.ucode_ver); 6119 aprint_error_dev(sc->sc_dev, "%08X | uCode version\n", table.ucode_ver);
6120 aprint_error_dev(sc->sc_dev, "%08X | hw version\n", table.hw_ver); 6120 aprint_error_dev(sc->sc_dev, "%08X | hw version\n", table.hw_ver);
6121 aprint_error_dev(sc->sc_dev, "%08X | board version\n", table.brd_ver); 6121 aprint_error_dev(sc->sc_dev, "%08X | board version\n", table.brd_ver);
6122 aprint_error_dev(sc->sc_dev, "%08X | hcmd\n", table.hcmd); 6122 aprint_error_dev(sc->sc_dev, "%08X | hcmd\n", table.hcmd);
6123 aprint_error_dev(sc->sc_dev, "%08X | isr0\n", table.isr0); 6123 aprint_error_dev(sc->sc_dev, "%08X | isr0\n", table.isr0);
6124 aprint_error_dev(sc->sc_dev, "%08X | isr1\n", table.isr1); 6124 aprint_error_dev(sc->sc_dev, "%08X | isr1\n", table.isr1);
6125 aprint_error_dev(sc->sc_dev, "%08X | isr2\n", table.isr2); 6125 aprint_error_dev(sc->sc_dev, "%08X | isr2\n", table.isr2);
6126 aprint_error_dev(sc->sc_dev, "%08X | isr3\n", table.isr3); 6126 aprint_error_dev(sc->sc_dev, "%08X | isr3\n", table.isr3);
6127 aprint_error_dev(sc->sc_dev, "%08X | isr4\n", table.isr4); 6127 aprint_error_dev(sc->sc_dev, "%08X | isr4\n", table.isr4);
6128 aprint_error_dev(sc->sc_dev, "%08X | isr_pref\n", table.isr_pref); 6128 aprint_error_dev(sc->sc_dev, "%08X | isr_pref\n", table.isr_pref);
6129 aprint_error_dev(sc->sc_dev, "%08X | wait_event\n", table.wait_event); 6129 aprint_error_dev(sc->sc_dev, "%08X | wait_event\n", table.wait_event);
6130 aprint_error_dev(sc->sc_dev, "%08X | l2p_control\n", table.l2p_control); 6130 aprint_error_dev(sc->sc_dev, "%08X | l2p_control\n", table.l2p_control);
6131 aprint_error_dev(sc->sc_dev, "%08X | l2p_duration\n", 6131 aprint_error_dev(sc->sc_dev, "%08X | l2p_duration\n",
6132 table.l2p_duration); 6132 table.l2p_duration);
6133 aprint_error_dev(sc->sc_dev, "%08X | l2p_mhvalid\n", table.l2p_mhvalid); 6133 aprint_error_dev(sc->sc_dev, "%08X | l2p_mhvalid\n", table.l2p_mhvalid);
6134 aprint_error_dev(sc->sc_dev, "%08X | l2p_addr_match\n", 6134 aprint_error_dev(sc->sc_dev, "%08X | l2p_addr_match\n",
6135 table.l2p_addr_match); 6135 table.l2p_addr_match);
6136 aprint_error_dev(sc->sc_dev, "%08X | lmpm_pmg_sel\n", 6136 aprint_error_dev(sc->sc_dev, "%08X | lmpm_pmg_sel\n",
6137 table.lmpm_pmg_sel); 6137 table.lmpm_pmg_sel);
6138 aprint_error_dev(sc->sc_dev, "%08X | timestamp\n", table.u_timestamp); 6138 aprint_error_dev(sc->sc_dev, "%08X | timestamp\n", table.u_timestamp);
6139 aprint_error_dev(sc->sc_dev, "%08X | flow_handler\n", 6139 aprint_error_dev(sc->sc_dev, "%08X | flow_handler\n",
6140 table.flow_handler); 6140 table.flow_handler);
6141} 6141}
6142#endif 6142#endif
6143 6143
6144#define SYNC_RESP_STRUCT(_var_, _pkt_) \ 6144#define SYNC_RESP_STRUCT(_var_, _pkt_) \
6145do { \ 6145do { \
6146 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof(*(_pkt_)), \ 6146 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof(*(_pkt_)), \
6147 sizeof(*(_var_)), BUS_DMASYNC_POSTREAD); \ 6147 sizeof(*(_var_)), BUS_DMASYNC_POSTREAD); \
6148 _var_ = (void *)((_pkt_)+1); \ 6148 _var_ = (void *)((_pkt_)+1); \
6149} while (/*CONSTCOND*/0) 6149} while (/*CONSTCOND*/0)
6150 6150
6151#define SYNC_RESP_PTR(_ptr_, _len_, _pkt_) \ 6151#define SYNC_RESP_PTR(_ptr_, _len_, _pkt_) \
6152do { \ 6152do { \
6153 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof(*(_pkt_)), \ 6153 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof(*(_pkt_)), \
6154 sizeof(len), BUS_DMASYNC_POSTREAD); \ 6154 sizeof(len), BUS_DMASYNC_POSTREAD); \
6155 _ptr_ = (void *)((_pkt_)+1); \ 6155 _ptr_ = (void *)((_pkt_)+1); \
6156} while (/*CONSTCOND*/0) 6156} while (/*CONSTCOND*/0)
6157 6157
6158#define ADVANCE_RXQ(sc) (sc->rxq.cur = (sc->rxq.cur + 1) % IWM_RX_RING_COUNT); 6158#define ADVANCE_RXQ(sc) (sc->rxq.cur = (sc->rxq.cur + 1) % IWM_RX_RING_COUNT);
6159 6159
6160/* 6160/*
6161 * Process an IWM_CSR_INT_BIT_FH_RX or IWM_CSR_INT_BIT_SW_RX interrupt. 6161 * Process an IWM_CSR_INT_BIT_FH_RX or IWM_CSR_INT_BIT_SW_RX interrupt.
6162 * Basic structure from if_iwn 6162 * Basic structure from if_iwn
6163 */ 6163 */
6164static void 6164static void
6165iwm_notif_intr(struct iwm_softc *sc) 6165iwm_notif_intr(struct iwm_softc *sc)
6166{ 6166{
6167 uint16_t hw; 6167 uint16_t hw;
6168 6168
6169 bus_dmamap_sync(sc->sc_dmat, sc->rxq.stat_dma.map, 6169 bus_dmamap_sync(sc->sc_dmat, sc->rxq.stat_dma.map,
6170 0, sc->rxq.stat_dma.size, BUS_DMASYNC_POSTREAD); 6170 0, sc->rxq.stat_dma.size, BUS_DMASYNC_POSTREAD);
6171 6171
6172 hw = le16toh(sc->rxq.stat->closed_rb_num) & 0xfff; 6172 hw = le16toh(sc->rxq.stat->closed_rb_num) & 0xfff;
6173 while (sc->rxq.cur != hw) { 6173 while (sc->rxq.cur != hw) {
6174 struct iwm_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 6174 struct iwm_rx_data *data = &sc->rxq.data[sc->rxq.cur];
6175 struct iwm_rx_packet *pkt, tmppkt; 6175 struct iwm_rx_packet *pkt, tmppkt;
6176 struct iwm_cmd_response *cresp; 6176 struct iwm_cmd_response *cresp;
6177 int qid, idx; 6177 int qid, idx;
6178 6178
6179 bus_dmamap_sync(sc->sc_dmat, data->map, 0, sizeof(*pkt), 6179 bus_dmamap_sync(sc->sc_dmat, data->map, 0, sizeof(*pkt),
6180 BUS_DMASYNC_POSTREAD); 6180 BUS_DMASYNC_POSTREAD);
6181 pkt = mtod(data->m, struct iwm_rx_packet *); 6181 pkt = mtod(data->m, struct iwm_rx_packet *);
6182 6182
6183 qid = pkt->hdr.qid & ~0x80; 6183 qid = pkt->hdr.qid & ~0x80;
6184 idx = pkt->hdr.idx; 6184 idx = pkt->hdr.idx;
6185 6185
6186 DPRINTFN(12, ("rx packet qid=%d idx=%d flags=%x type=%x %d %d\n", 6186 DPRINTFN(12, ("rx packet qid=%d idx=%d flags=%x type=%x %d %d\n",
6187 pkt->hdr.qid & ~0x80, pkt->hdr.idx, pkt->hdr.flags, 6187 pkt->hdr.qid & ~0x80, pkt->hdr.idx, pkt->hdr.flags,
6188 pkt->hdr.code, sc->rxq.cur, hw)); 6188 pkt->hdr.code, sc->rxq.cur, hw));
6189 6189
6190 /* 6190 /*
6191 * randomly get these from the firmware, no idea why. 6191 * randomly get these from the firmware, no idea why.
6192 * they at least seem harmless, so just ignore them for now 6192 * they at least seem harmless, so just ignore them for now
6193 */ 6193 */
6194 if (__predict_false((pkt->hdr.code == 0 && qid == 0 && idx == 0) 6194 if (__predict_false((pkt->hdr.code == 0 && qid == 0 && idx == 0)
6195 || pkt->len_n_flags == htole32(0x55550000))) { 6195 || pkt->len_n_flags == htole32(0x55550000))) {
6196 ADVANCE_RXQ(sc); 6196 ADVANCE_RXQ(sc);
6197 continue; 6197 continue;
6198 } 6198 }
6199 6199
6200 switch (pkt->hdr.code) { 6200 switch (pkt->hdr.code) {
6201 case IWM_REPLY_RX_PHY_CMD: 6201 case IWM_REPLY_RX_PHY_CMD:
6202 iwm_mvm_rx_rx_phy_cmd(sc, pkt, data); 6202 iwm_mvm_rx_rx_phy_cmd(sc, pkt, data);
6203 break; 6203 break;
6204 6204
6205 case IWM_REPLY_RX_MPDU_CMD: 6205 case IWM_REPLY_RX_MPDU_CMD:
6206 tmppkt = *pkt; // XXX m is freed by ieee80211_input() 6206 tmppkt = *pkt; // XXX m is freed by ieee80211_input()
6207 iwm_mvm_rx_rx_mpdu(sc, pkt, data); 6207 iwm_mvm_rx_rx_mpdu(sc, pkt, data);
6208 pkt = &tmppkt; 6208 pkt = &tmppkt;
6209 break; 6209 break;
6210 6210
6211 case IWM_TX_CMD: 6211 case IWM_TX_CMD:
6212 iwm_mvm_rx_tx_cmd(sc, pkt, data); 6212 iwm_mvm_rx_tx_cmd(sc, pkt, data);
6213 break; 6213 break;
6214 6214
6215 case IWM_MISSED_BEACONS_NOTIFICATION: 6215 case IWM_MISSED_BEACONS_NOTIFICATION:
6216 iwm_mvm_rx_missed_beacons_notif(sc, pkt, data); 6216 iwm_mvm_rx_missed_beacons_notif(sc, pkt, data);
6217 break; 6217 break;
6218 6218
6219 case IWM_MVM_ALIVE: { 6219 case IWM_MVM_ALIVE: {
6220 struct iwm_mvm_alive_resp *resp; 6220 struct iwm_mvm_alive_resp *resp;
6221 SYNC_RESP_STRUCT(resp, pkt); 6221 SYNC_RESP_STRUCT(resp, pkt);
6222 6222
6223 sc->sc_uc.uc_error_event_table 6223 sc->sc_uc.uc_error_event_table
6224 = le32toh(resp->error_event_table_ptr); 6224 = le32toh(resp->error_event_table_ptr);
6225 sc->sc_uc.uc_log_event_table 6225 sc->sc_uc.uc_log_event_table
6226 = le32toh(resp->log_event_table_ptr); 6226 = le32toh(resp->log_event_table_ptr);
6227 sc->sched_base = le32toh(resp->scd_base_ptr); 6227 sc->sched_base = le32toh(resp->scd_base_ptr);
6228 sc->sc_uc.uc_ok = resp->status == IWM_ALIVE_STATUS_OK; 6228 sc->sc_uc.uc_ok = resp->status == IWM_ALIVE_STATUS_OK;
6229 6229
6230 sc->sc_uc.uc_intr = 1; 6230 sc->sc_uc.uc_intr = 1;
6231 wakeup(&sc->sc_uc); 6231 wakeup(&sc->sc_uc);
6232 break; } 6232 break; }
6233 6233
6234 case IWM_CALIB_RES_NOTIF_PHY_DB: { 6234 case IWM_CALIB_RES_NOTIF_PHY_DB: {
6235 struct iwm_calib_res_notif_phy_db *phy_db_notif; 6235 struct iwm_calib_res_notif_phy_db *phy_db_notif;
6236 SYNC_RESP_STRUCT(phy_db_notif, pkt); 6236 SYNC_RESP_STRUCT(phy_db_notif, pkt);
6237 6237
6238 uint16_t size = le16toh(phy_db_notif->length); 6238 uint16_t size = le16toh(phy_db_notif->length);
6239 bus_dmamap_sync(sc->sc_dmat, data->map, 6239 bus_dmamap_sync(sc->sc_dmat, data->map,
6240 sizeof(*pkt) + sizeof(*phy_db_notif), 6240 sizeof(*pkt) + sizeof(*phy_db_notif),
6241 size, BUS_DMASYNC_POSTREAD); 6241 size, BUS_DMASYNC_POSTREAD);
6242 iwm_phy_db_set_section(sc, phy_db_notif, size); 6242 iwm_phy_db_set_section(sc, phy_db_notif, size);
6243 6243
6244 break; } 6244 break; }
6245 6245
6246 case IWM_STATISTICS_NOTIFICATION: { 6246 case IWM_STATISTICS_NOTIFICATION: {
6247 struct iwm_notif_statistics *stats; 6247 struct iwm_notif_statistics *stats;
6248 SYNC_RESP_STRUCT(stats, pkt); 6248 SYNC_RESP_STRUCT(stats, pkt);
6249 memcpy(&sc->sc_stats, stats, sizeof(sc->sc_stats)); 6249 memcpy(&sc->sc_stats, stats, sizeof(sc->sc_stats));
6250 sc->sc_noise = iwm_get_noise(&stats->rx.general); 6250 sc->sc_noise = iwm_get_noise(&stats->rx.general);
6251 break; } 6251 break; }
6252 6252
6253 case IWM_NVM_ACCESS_CMD: 6253 case IWM_NVM_ACCESS_CMD:
6254 if (sc->sc_wantresp == ((qid << 16) | idx)) { 6254 if (sc->sc_wantresp == ((qid << 16) | idx)) {
6255 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 6255 bus_dmamap_sync(sc->sc_dmat, data->map, 0,
6256 sizeof(sc->sc_cmd_resp), 6256 sizeof(sc->sc_cmd_resp),
6257 BUS_DMASYNC_POSTREAD); 6257 BUS_DMASYNC_POSTREAD);
6258 memcpy(sc->sc_cmd_resp, 6258 memcpy(sc->sc_cmd_resp,
6259 pkt, sizeof(sc->sc_cmd_resp)); 6259 pkt, sizeof(sc->sc_cmd_resp));
6260 } 6260 }
6261 break; 6261 break;
6262 6262
6263 case IWM_PHY_CONFIGURATION_CMD: 6263 case IWM_PHY_CONFIGURATION_CMD:
6264 case IWM_TX_ANT_CONFIGURATION_CMD: 6264 case IWM_TX_ANT_CONFIGURATION_CMD:
6265 case IWM_ADD_STA: 6265 case IWM_ADD_STA:
6266 case IWM_MAC_CONTEXT_CMD: 6266 case IWM_MAC_CONTEXT_CMD:
6267 case IWM_REPLY_SF_CFG_CMD: 6267 case IWM_REPLY_SF_CFG_CMD:
6268 case IWM_POWER_TABLE_CMD: 6268 case IWM_POWER_TABLE_CMD:
6269 case IWM_PHY_CONTEXT_CMD: 6269 case IWM_PHY_CONTEXT_CMD:
6270 case IWM_BINDING_CONTEXT_CMD: 6270 case IWM_BINDING_CONTEXT_CMD:
6271 case IWM_TIME_EVENT_CMD: 6271 case IWM_TIME_EVENT_CMD:
6272 case IWM_SCAN_REQUEST_CMD: 6272 case IWM_SCAN_REQUEST_CMD:
6273 case IWM_REPLY_BEACON_FILTERING_CMD: 6273 case IWM_REPLY_BEACON_FILTERING_CMD:
6274 case IWM_MAC_PM_POWER_TABLE: 6274 case IWM_MAC_PM_POWER_TABLE:
6275 case IWM_TIME_QUOTA_CMD: 6275 case IWM_TIME_QUOTA_CMD:
6276 case IWM_REMOVE_STA: 6276 case IWM_REMOVE_STA:
6277 case IWM_TXPATH_FLUSH: 6277 case IWM_TXPATH_FLUSH:
6278 case IWM_LQ_CMD: 6278 case IWM_LQ_CMD:
6279 SYNC_RESP_STRUCT(cresp, pkt); 6279 SYNC_RESP_STRUCT(cresp, pkt);
6280 if (sc->sc_wantresp == ((qid << 16) | idx)) { 6280 if (sc->sc_wantresp == ((qid << 16) | idx)) {
6281 memcpy(sc->sc_cmd_resp, 6281 memcpy(sc->sc_cmd_resp,
6282 pkt, sizeof(*pkt)+sizeof(*cresp)); 6282 pkt, sizeof(*pkt)+sizeof(*cresp));
6283 } 6283 }
6284 break; 6284 break;
6285 6285
6286 /* ignore */ 6286 /* ignore */
6287 case 0x6c: /* IWM_PHY_DB_CMD, no idea why it's not in fw-api.h */ 6287 case 0x6c: /* IWM_PHY_DB_CMD, no idea why it's not in fw-api.h */
6288 break; 6288 break;
6289 6289
6290 case IWM_INIT_COMPLETE_NOTIF: 6290 case IWM_INIT_COMPLETE_NOTIF:
6291 sc->sc_init_complete = 1; 6291 sc->sc_init_complete = 1;
6292 wakeup(&sc->sc_init_complete); 6292 wakeup(&sc->sc_init_complete);
6293 break; 6293 break;
6294 6294
6295 case IWM_SCAN_COMPLETE_NOTIFICATION: { 6295 case IWM_SCAN_COMPLETE_NOTIFICATION: {
6296 struct iwm_scan_complete_notif *notif; 6296 struct iwm_scan_complete_notif *notif;
6297 SYNC_RESP_STRUCT(notif, pkt); 6297 SYNC_RESP_STRUCT(notif, pkt);
6298 6298
6299 workqueue_enqueue(sc->sc_eswq, &sc->sc_eswk, NULL); 6299 workqueue_enqueue(sc->sc_eswq, &sc->sc_eswk, NULL);
6300 break; } 6300 break; }
6301 6301
6302 case IWM_REPLY_ERROR: { 6302 case IWM_REPLY_ERROR: {
6303 struct iwm_error_resp *resp; 6303 struct iwm_error_resp *resp;
6304 SYNC_RESP_STRUCT(resp, pkt); 6304 SYNC_RESP_STRUCT(resp, pkt);
6305 6305
6306 aprint_error_dev(sc->sc_dev, 6306 aprint_error_dev(sc->sc_dev,
6307 "firmware error 0x%x, cmd 0x%x\n", 6307 "firmware error 0x%x, cmd 0x%x\n",
6308 le32toh(resp->error_type), resp->cmd_id); 6308 le32toh(resp->error_type), resp->cmd_id);
6309 break; } 6309 break; }
6310 6310
6311 case IWM_TIME_EVENT_NOTIFICATION: { 6311 case IWM_TIME_EVENT_NOTIFICATION: {
6312 struct iwm_time_event_notif *notif; 6312 struct iwm_time_event_notif *notif;
6313 SYNC_RESP_STRUCT(notif, pkt); 6313 SYNC_RESP_STRUCT(notif, pkt);
6314 6314
6315 if (notif->status) { 6315 if (notif->status) {
6316 if (le32toh(notif->action) & 6316 if (le32toh(notif->action) &
6317 IWM_TE_V2_NOTIF_HOST_EVENT_START) 6317 IWM_TE_V2_NOTIF_HOST_EVENT_START)
6318 sc->sc_auth_prot = 2; 6318 sc->sc_auth_prot = 2;
6319 else 6319 else
6320 sc->sc_auth_prot = 0; 6320 sc->sc_auth_prot = 0;
6321 } else { 6321 } else {
6322 sc->sc_auth_prot = -1; 6322 sc->sc_auth_prot = -1;
6323 } 6323 }
6324 wakeup(&sc->sc_auth_prot); 6324 wakeup(&sc->sc_auth_prot);
6325 break; } 6325 break; }
6326 6326
6327 case IWM_MCAST_FILTER_CMD: 6327 case IWM_MCAST_FILTER_CMD:
6328 break; 6328 break;
6329 6329
6330 default: 6330 default:
6331 aprint_error_dev(sc->sc_dev, 6331 aprint_error_dev(sc->sc_dev,
6332 "code %02x frame %d/%d %x UNHANDLED " 6332 "code %02x frame %d/%d %x UNHANDLED "
6333 "(this should not happen)\n", 6333 "(this should not happen)\n",
6334 pkt->hdr.code, qid, idx, pkt->len_n_flags); 6334 pkt->hdr.code, qid, idx, pkt->len_n_flags);
6335 break; 6335 break;
6336 } 6336 }
6337 6337
6338 /* 6338 /*
6339 * Why test bit 0x80? The Linux driver: 6339 * Why test bit 0x80? The Linux driver:
6340 * 6340 *
6341 * There is one exception: uCode sets bit 15 when it 6341 * There is one exception: uCode sets bit 15 when it
6342 * originates the response/notification, i.e. when the 6342 * originates the response/notification, i.e. when the
6343 * response/notification is not a direct response to a 6343 * response/notification is not a direct response to a
6344 * command sent by the driver. For example, uCode issues 6344 * command sent by the driver. For example, uCode issues
6345 * IWM_REPLY_RX when it sends a received frame to the driver; 6345 * IWM_REPLY_RX when it sends a received frame to the driver;
6346 * it is not a direct response to any driver command. 6346 * it is not a direct response to any driver command.
6347 * 6347 *
6348 * Ok, so since when is 7 == 15? Well, the Linux driver 6348 * Ok, so since when is 7 == 15? Well, the Linux driver
6349 * uses a slightly different format for pkt->hdr, and "qid" 6349 * uses a slightly different format for pkt->hdr, and "qid"
6350 * is actually the upper byte of a two-byte field. 6350 * is actually the upper byte of a two-byte field.
6351 */ 6351 */
6352 if (!(pkt->hdr.qid & (1 << 7))) { 6352 if (!(pkt->hdr.qid & (1 << 7))) {
6353 iwm_cmd_done(sc, pkt); 6353 iwm_cmd_done(sc, pkt);
6354 } 6354 }
6355 6355
6356 ADVANCE_RXQ(sc); 6356 ADVANCE_RXQ(sc);
6357 } 6357 }
6358 6358
6359 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL, 6359 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL,
6360 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 6360 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
6361 6361
6362 /* 6362 /*
6363 * Tell the firmware what we have processed. 6363 * Tell the firmware what we have processed.
6364 * Seems like the hardware gets upset unless we align 6364 * Seems like the hardware gets upset unless we align
6365 * the write by 8?? 6365 * the write by 8??
6366 */ 6366 */
6367 hw = (hw == 0) ? IWM_RX_RING_COUNT - 1 : hw - 1; 6367 hw = (hw == 0) ? IWM_RX_RING_COUNT - 1 : hw - 1;
6368 IWM_WRITE(sc, IWM_FH_RSCSR_CHNL0_WPTR, hw & ~7); 6368 IWM_WRITE(sc, IWM_FH_RSCSR_CHNL0_WPTR, hw & ~7);
6369} 6369}
6370 6370
6371static int 6371static int
6372iwm_intr(void *arg) 6372iwm_intr(void *arg)
6373{ 6373{
6374 struct iwm_softc *sc = arg; 6374 struct iwm_softc *sc = arg;
6375 struct ifnet *ifp = IC2IFP(&sc->sc_ic); 6375 struct ifnet *ifp = IC2IFP(&sc->sc_ic);
6376 int handled = 0; 6376 int handled = 0;
6377 int r1, r2, rv = 0; 6377 int r1, r2, rv = 0;
6378 int isperiodic = 0; 6378 int isperiodic = 0;
6379 6379
6380 IWM_WRITE(sc, IWM_CSR_INT_MASK, 0); 6380 IWM_WRITE(sc, IWM_CSR_INT_MASK, 0);
6381 6381
6382 if (sc->sc_flags & IWM_FLAG_USE_ICT) { 6382 if (sc->sc_flags & IWM_FLAG_USE_ICT) {
6383 uint32_t *ict = sc->ict_dma.vaddr; 6383 uint32_t *ict = sc->ict_dma.vaddr;
6384 int tmp; 6384 int tmp;
6385 6385
6386 tmp = htole32(ict[sc->ict_cur]); 6386 tmp = htole32(ict[sc->ict_cur]);
6387 if (!tmp) 6387 if (!tmp)
6388 goto out_ena; 6388 goto out_ena;
6389 6389
6390 /* 6390 /*
6391 * ok, there was something. keep plowing until we have all. 6391 * ok, there was something. keep plowing until we have all.
6392 */ 6392 */
6393 r1 = r2 = 0; 6393 r1 = r2 = 0;
6394 while (tmp) { 6394 while (tmp) {
6395 r1 |= tmp; 6395 r1 |= tmp;
6396 ict[sc->ict_cur] = 0; 6396 ict[sc->ict_cur] = 0;
6397 sc->ict_cur = (sc->ict_cur+1) % IWM_ICT_COUNT; 6397 sc->ict_cur = (sc->ict_cur+1) % IWM_ICT_COUNT;
6398 tmp = htole32(ict[sc->ict_cur]); 6398 tmp = htole32(ict[sc->ict_cur]);
6399 } 6399 }
6400 6400
6401 /* this is where the fun begins. don't ask */ 6401 /* this is where the fun begins. don't ask */
6402 if (r1 == 0xffffffff) 6402 if (r1 == 0xffffffff)
6403 r1 = 0; 6403 r1 = 0;
6404 6404
6405 /* i am not expected to understand this */ 6405 /* i am not expected to understand this */
6406 if (r1 & 0xc0000) 6406 if (r1 & 0xc0000)
6407 r1 |= 0x8000; 6407 r1 |= 0x8000;
6408 r1 = (0xff & r1) | ((0xff00 & r1) << 16); 6408 r1 = (0xff & r1) | ((0xff00 & r1) << 16);
6409 } else { 6409 } else {
6410 r1 = IWM_READ(sc, IWM_CSR_INT); 6410 r1 = IWM_READ(sc, IWM_CSR_INT);
6411 /* "hardware gone" (where, fishing?) */ 6411 /* "hardware gone" (where, fishing?) */
6412 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 6412 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0)
6413 goto out; 6413 goto out;
6414 r2 = IWM_READ(sc, IWM_CSR_FH_INT_STATUS); 6414 r2 = IWM_READ(sc, IWM_CSR_FH_INT_STATUS);
6415 } 6415 }
6416 if (r1 == 0 && r2 == 0) { 6416 if (r1 == 0 && r2 == 0) {
6417 goto out_ena; 6417 goto out_ena;
6418 } 6418 }
6419 6419
6420 IWM_WRITE(sc, IWM_CSR_INT, r1 | ~sc->sc_intmask); 6420 IWM_WRITE(sc, IWM_CSR_INT, r1 | ~sc->sc_intmask);
6421 6421
6422 /* ignored */ 6422 /* ignored */
6423 handled |= (r1 & (IWM_CSR_INT_BIT_ALIVE /*| IWM_CSR_INT_BIT_SCD*/)); 6423 handled |= (r1 & (IWM_CSR_INT_BIT_ALIVE /*| IWM_CSR_INT_BIT_SCD*/));
6424 6424
6425 if (r1 & IWM_CSR_INT_BIT_SW_ERR) { 6425 if (r1 & IWM_CSR_INT_BIT_SW_ERR) {
6426#ifdef IWM_DEBUG 6426#ifdef IWM_DEBUG
6427 int i; 6427 int i;
6428 6428
6429 iwm_nic_error(sc); 6429 iwm_nic_error(sc);
6430 6430
6431 /* Dump driver status (TX and RX rings) while we're here. */ 6431 /* Dump driver status (TX and RX rings) while we're here. */
6432 DPRINTF(("driver status:\n")); 6432 DPRINTF(("driver status:\n"));
6433 for (i = 0; i < IWM_MVM_MAX_QUEUES; i++) { 6433 for (i = 0; i < IWM_MVM_MAX_QUEUES; i++) {
6434 struct iwm_tx_ring *ring = &sc->txq[i]; 6434 struct iwm_tx_ring *ring = &sc->txq[i];
6435 DPRINTF((" tx ring %2d: qid=%-2d cur=%-3d " 6435 DPRINTF((" tx ring %2d: qid=%-2d cur=%-3d "
6436 "queued=%-3d\n", 6436 "queued=%-3d\n",
6437 i, ring->qid, ring->cur, ring->queued)); 6437 i, ring->qid, ring->cur, ring->queued));
6438 } 6438 }
6439 DPRINTF((" rx ring: cur=%d\n", sc->rxq.cur)); 6439 DPRINTF((" rx ring: cur=%d\n", sc->rxq.cur));
6440 DPRINTF((" 802.11 state %d\n", sc->sc_ic.ic_state)); 6440 DPRINTF((" 802.11 state %d\n", sc->sc_ic.ic_state));
6441#endif 6441#endif
6442 6442
6443 aprint_error_dev(sc->sc_dev, "fatal firmware error\n"); 6443 aprint_error_dev(sc->sc_dev, "fatal firmware error\n");
6444 ifp->if_flags &= ~IFF_UP; 6444 ifp->if_flags &= ~IFF_UP;
6445 iwm_stop(ifp, 1); 6445 iwm_stop(ifp, 1);
6446 rv = 1; 6446 rv = 1;
6447 goto out; 6447 goto out;
6448 6448
6449 } 6449 }
6450 6450
6451 if (r1 & IWM_CSR_INT_BIT_HW_ERR) { 6451 if (r1 & IWM_CSR_INT_BIT_HW_ERR) {
6452 handled |= IWM_CSR_INT_BIT_HW_ERR; 6452 handled |= IWM_CSR_INT_BIT_HW_ERR;
6453 aprint_error_dev(sc->sc_dev, 6453 aprint_error_dev(sc->sc_dev,
6454 "hardware error, stopping device\n"); 6454 "hardware error, stopping device\n");
6455 ifp->if_flags &= ~IFF_UP; 6455 ifp->if_flags &= ~IFF_UP;
6456 iwm_stop(ifp, 1); 6456 iwm_stop(ifp, 1);
6457 rv = 1; 6457 rv = 1;
6458 goto out; 6458 goto out;
6459 } 6459 }
6460 6460
6461 /* firmware chunk loaded */ 6461 /* firmware chunk loaded */
6462 if (r1 & IWM_CSR_INT_BIT_FH_TX) { 6462 if (r1 & IWM_CSR_INT_BIT_FH_TX) {
6463 IWM_WRITE(sc, IWM_CSR_FH_INT_STATUS, IWM_CSR_FH_INT_TX_MASK); 6463 IWM_WRITE(sc, IWM_CSR_FH_INT_STATUS, IWM_CSR_FH_INT_TX_MASK);
6464 handled |= IWM_CSR_INT_BIT_FH_TX; 6464 handled |= IWM_CSR_INT_BIT_FH_TX;
6465 6465
6466 sc->sc_fw_chunk_done = 1; 6466 sc->sc_fw_chunk_done = 1;
6467 wakeup(&sc->sc_fw); 6467 wakeup(&sc->sc_fw);
6468 } 6468 }
6469 6469
6470 if (r1 & IWM_CSR_INT_BIT_RF_KILL) { 6470 if (r1 & IWM_CSR_INT_BIT_RF_KILL) {
6471 handled |= IWM_CSR_INT_BIT_RF_KILL; 6471 handled |= IWM_CSR_INT_BIT_RF_KILL;
6472 if (iwm_check_rfkill(sc) && (ifp->if_flags & IFF_UP)) { 6472 if (iwm_check_rfkill(sc) && (ifp->if_flags & IFF_UP)) {
6473 DPRINTF(("%s: rfkill switch, disabling interface\n", 6473 DPRINTF(("%s: rfkill switch, disabling interface\n",
6474 DEVNAME(sc))); 6474 DEVNAME(sc)));
6475 ifp->if_flags &= ~IFF_UP; 6475 ifp->if_flags &= ~IFF_UP;
6476 iwm_stop(ifp, 1); 6476 iwm_stop(ifp, 1);
6477 } 6477 }
6478 } 6478 }
6479 6479
6480 /* 6480 /*
6481 * The Linux driver uses periodic interrupts to avoid races. 6481 * The Linux driver uses periodic interrupts to avoid races.
6482 * We cargo-cult like it's going out of fashion. 6482 * We cargo-cult like it's going out of fashion.
6483 */ 6483 */
6484 if (r1 & IWM_CSR_INT_BIT_RX_PERIODIC) { 6484 if (r1 & IWM_CSR_INT_BIT_RX_PERIODIC) {
6485 handled |= IWM_CSR_INT_BIT_RX_PERIODIC; 6485 handled |= IWM_CSR_INT_BIT_RX_PERIODIC;
6486 IWM_WRITE(sc, IWM_CSR_INT, IWM_CSR_INT_BIT_RX_PERIODIC); 6486 IWM_WRITE(sc, IWM_CSR_INT, IWM_CSR_INT_BIT_RX_PERIODIC);
6487 if ((r1 & (IWM_CSR_INT_BIT_FH_RX | IWM_CSR_INT_BIT_SW_RX)) == 0) 6487 if ((r1 & (IWM_CSR_INT_BIT_FH_RX | IWM_CSR_INT_BIT_SW_RX)) == 0)
6488 IWM_WRITE_1(sc, 6488 IWM_WRITE_1(sc,
6489 IWM_CSR_INT_PERIODIC_REG, IWM_CSR_INT_PERIODIC_DIS); 6489 IWM_CSR_INT_PERIODIC_REG, IWM_CSR_INT_PERIODIC_DIS);
6490 isperiodic = 1; 6490 isperiodic = 1;
6491 } 6491 }
6492 6492
6493 if ((r1 & (IWM_CSR_INT_BIT_FH_RX | IWM_CSR_INT_BIT_SW_RX)) || isperiodic) { 6493 if ((r1 & (IWM_CSR_INT_BIT_FH_RX | IWM_CSR_INT_BIT_SW_RX)) || isperiodic) {
6494 handled |= (IWM_CSR_INT_BIT_FH_RX | IWM_CSR_INT_BIT_SW_RX); 6494 handled |= (IWM_CSR_INT_BIT_FH_RX | IWM_CSR_INT_BIT_SW_RX);
6495 IWM_WRITE(sc, IWM_CSR_FH_INT_STATUS, IWM_CSR_FH_INT_RX_MASK); 6495 IWM_WRITE(sc, IWM_CSR_FH_INT_STATUS, IWM_CSR_FH_INT_RX_MASK);
6496 6496
6497 iwm_notif_intr(sc); 6497 iwm_notif_intr(sc);
6498 6498
6499 /* enable periodic interrupt, see above */ 6499 /* enable periodic interrupt, see above */
6500 if (r1 & (IWM_CSR_INT_BIT_FH_RX | IWM_CSR_INT_BIT_SW_RX) && !isperiodic) 6500 if (r1 & (IWM_CSR_INT_BIT_FH_RX | IWM_CSR_INT_BIT_SW_RX) && !isperiodic)
6501 IWM_WRITE_1(sc, IWM_CSR_INT_PERIODIC_REG, 6501 IWM_WRITE_1(sc, IWM_CSR_INT_PERIODIC_REG,
6502 IWM_CSR_INT_PERIODIC_ENA); 6502 IWM_CSR_INT_PERIODIC_ENA);
6503 } 6503 }
6504 6504
6505 if (__predict_false(r1 & ~handled)) 6505 if (__predict_false(r1 & ~handled))
6506 DPRINTF(("%s: unhandled interrupts: %x\n", DEVNAME(sc), r1)); 6506 DPRINTF(("%s: unhandled interrupts: %x\n", DEVNAME(sc), r1));
6507 rv = 1; 6507 rv = 1;
6508 6508
6509 out_ena: 6509 out_ena:
6510 iwm_restore_interrupts(sc); 6510 iwm_restore_interrupts(sc);
6511 out: 6511 out:
6512 return rv; 6512 return rv;
6513} 6513}
6514 6514
6515/* 6515/*
6516 * Autoconf glue-sniffing 6516 * Autoconf glue-sniffing
6517 */ 6517 */
6518 6518
6519static const pci_product_id_t iwm_devices[] = { 6519static const pci_product_id_t iwm_devices[] = {
6520 PCI_PRODUCT_INTEL_WIFI_LINK_7260_1, 6520 PCI_PRODUCT_INTEL_WIFI_LINK_7260_1,
6521 PCI_PRODUCT_INTEL_WIFI_LINK_7260_2, 6521 PCI_PRODUCT_INTEL_WIFI_LINK_7260_2,
6522 PCI_PRODUCT_INTEL_WIFI_LINK_3160_1, 6522 PCI_PRODUCT_INTEL_WIFI_LINK_3160_1,
6523 PCI_PRODUCT_INTEL_WIFI_LINK_3160_2, 6523 PCI_PRODUCT_INTEL_WIFI_LINK_3160_2,
6524 PCI_PRODUCT_INTEL_WIFI_LINK_7265_1, 6524 PCI_PRODUCT_INTEL_WIFI_LINK_7265_1,
6525 PCI_PRODUCT_INTEL_WIFI_LINK_7265_2, 6525 PCI_PRODUCT_INTEL_WIFI_LINK_7265_2,
6526}; 6526};
6527 6527
6528static int 6528static int
6529iwm_match(device_t parent, cfdata_t match __unused, void *aux) 6529iwm_match(device_t parent, cfdata_t match __unused, void *aux)
6530{ 6530{
6531 struct pci_attach_args *pa = aux; 6531 struct pci_attach_args *pa = aux;
6532 6532
6533 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 6533 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL)
6534 return 0; 6534 return 0;
6535 6535
6536 for (size_t i = 0; i < __arraycount(iwm_devices); i++) 6536 for (size_t i = 0; i < __arraycount(iwm_devices); i++)
6537 if (PCI_PRODUCT(pa->pa_id) == iwm_devices[i]) 6537 if (PCI_PRODUCT(pa->pa_id) == iwm_devices[i])
6538 return 1; 6538 return 1;
6539 6539
6540 return 0; 6540 return 0;
6541} 6541}
6542 6542
6543static int 6543static int
6544iwm_preinit(struct iwm_softc *sc) 6544iwm_preinit(struct iwm_softc *sc)
6545{ 6545{
6546 struct ieee80211com *ic = &sc->sc_ic; 6546 struct ieee80211com *ic = &sc->sc_ic;
6547 int error; 6547 int error;
6548 6548
6549 if (sc->sc_flags & IWM_FLAG_ATTACHED) 6549 if (sc->sc_flags & IWM_FLAG_ATTACHED)
6550 return 0; 6550 return 0;
6551 6551
6552 if ((error = iwm_start_hw(sc)) != 0) { 6552 if ((error = iwm_start_hw(sc)) != 0) {
6553 aprint_error_dev(sc->sc_dev, "could not initialize hardware\n"); 6553 aprint_error_dev(sc->sc_dev, "could not initialize hardware\n");
6554 return error; 6554 return error;
6555 } 6555 }
6556 6556
6557 error = iwm_run_init_mvm_ucode(sc, 1); 6557 error = iwm_run_init_mvm_ucode(sc, 1);
6558 iwm_stop_device(sc); 6558 iwm_stop_device(sc);
6559 if (error) 6559 if (error)
6560 return error; 6560 return error;
6561 6561
6562 sc->sc_flags |= IWM_FLAG_ATTACHED; 6562 sc->sc_flags |= IWM_FLAG_ATTACHED;
6563 6563
6564 aprint_normal_dev(sc->sc_dev, 6564 aprint_normal_dev(sc->sc_dev,
6565 "hw rev: 0x%x, fw ver %d.%d (API ver %d), address %s\n", 6565 "hw rev: 0x%x, fw ver %d.%d (API ver %d), address %s\n",
6566 sc->sc_hw_rev & IWM_CSR_HW_REV_TYPE_MSK, 6566 sc->sc_hw_rev & IWM_CSR_HW_REV_TYPE_MSK,
6567 IWM_UCODE_MAJOR(sc->sc_fwver), 6567 IWM_UCODE_MAJOR(sc->sc_fwver),
6568 IWM_UCODE_MINOR(sc->sc_fwver), 6568 IWM_UCODE_MINOR(sc->sc_fwver),
6569 IWM_UCODE_API(sc->sc_fwver), 6569 IWM_UCODE_API(sc->sc_fwver),
6570 ether_sprintf(sc->sc_nvm.hw_addr)); 6570 ether_sprintf(sc->sc_nvm.hw_addr));
6571 6571
6572 /* not all hardware can do 5GHz band */ 6572 /* not all hardware can do 5GHz band */
6573 if (sc->sc_nvm.sku_cap_band_52GHz_enable) 6573 if (sc->sc_nvm.sku_cap_band_52GHz_enable)
6574 ic->ic_sup_rates[IEEE80211_MODE_11A] = ieee80211_std_rateset_11a; 6574 ic->ic_sup_rates[IEEE80211_MODE_11A] = ieee80211_std_rateset_11a;
6575 6575
6576 ieee80211_ifattach(ic); 6576 ieee80211_ifattach(ic);
6577 6577
6578 ic->ic_node_alloc = iwm_node_alloc; 6578 ic->ic_node_alloc = iwm_node_alloc;
6579 6579
6580 /* Override 802.11 state transition machine. */ 6580 /* Override 802.11 state transition machine. */
6581 sc->sc_newstate = ic->ic_newstate; 6581 sc->sc_newstate = ic->ic_newstate;
6582 ic->ic_newstate = iwm_newstate; 6582 ic->ic_newstate = iwm_newstate;
6583 ieee80211_media_init(ic, iwm_media_change, ieee80211_media_status); 6583 ieee80211_media_init(ic, iwm_media_change, ieee80211_media_status);
6584 ieee80211_announce(ic); 6584 ieee80211_announce(ic);
6585 6585
6586 iwm_radiotap_attach(sc); 6586 iwm_radiotap_attach(sc);
6587 6587
6588 return 0; 6588 return 0;
6589} 6589}
6590 6590
6591static void 6591static void
6592iwm_attach_hook(device_t dev) 6592iwm_attach_hook(device_t dev)
6593{ 6593{
6594 struct iwm_softc *sc = device_private(dev); 6594 struct iwm_softc *sc = device_private(dev);
6595 6595
6596 iwm_preinit(sc); 6596 iwm_preinit(sc);
6597} 6597}
6598 6598
6599static void 6599static void
6600iwm_attach(device_t parent, device_t self, void *aux) 6600iwm_attach(device_t parent, device_t self, void *aux)
6601{ 6601{
6602 struct iwm_softc *sc = device_private(self); 6602 struct iwm_softc *sc = device_private(self);
6603 struct pci_attach_args *pa = aux; 6603 struct pci_attach_args *pa = aux;
6604 struct ieee80211com *ic = &sc->sc_ic; 6604 struct ieee80211com *ic = &sc->sc_ic;
6605 struct ifnet *ifp = &sc->sc_ec.ec_if; 6605 struct ifnet *ifp = &sc->sc_ec.ec_if;
6606#ifndef __HAVE_PCI_MSI_MSIX 
6607 pci_intr_handle_t ih; 
6608#endif 
6609 pcireg_t reg, memtype; 6606 pcireg_t reg, memtype;
6610 char intrbuf[PCI_INTRSTR_LEN]; 6607 char intrbuf[PCI_INTRSTR_LEN];
6611 const char *intrstr; 6608 const char *intrstr;
6612 int error; 6609 int error;
6613 int txq_i; 6610 int txq_i;
6614 const struct sysctlnode *node; 6611 const struct sysctlnode *node;
6615 6612
6616 sc->sc_dev = self; 6613 sc->sc_dev = self;
6617 sc->sc_pct = pa->pa_pc; 6614 sc->sc_pct = pa->pa_pc;
6618 sc->sc_pcitag = pa->pa_tag; 6615 sc->sc_pcitag = pa->pa_tag;
6619 sc->sc_dmat = pa->pa_dmat; 6616 sc->sc_dmat = pa->pa_dmat;
6620 sc->sc_pciid = pa->pa_id; 6617 sc->sc_pciid = pa->pa_id;
6621 6618
6622 pci_aprint_devinfo(pa, NULL); 6619 pci_aprint_devinfo(pa, NULL);
6623 6620
6624 /* 6621 /*
6625 * Get the offset of the PCI Express Capability Structure in PCI 6622 * Get the offset of the PCI Express Capability Structure in PCI
6626 * Configuration Space. 6623 * Configuration Space.
6627 */ 6624 */
6628 error = pci_get_capability(sc->sc_pct, sc->sc_pcitag, 6625 error = pci_get_capability(sc->sc_pct, sc->sc_pcitag,
6629 PCI_CAP_PCIEXPRESS, &sc->sc_cap_off, NULL); 6626 PCI_CAP_PCIEXPRESS, &sc->sc_cap_off, NULL);
6630 if (error == 0) { 6627 if (error == 0) {
6631 aprint_error_dev(self, 6628 aprint_error_dev(self,
6632 "PCIe capability structure not found!\n"); 6629 "PCIe capability structure not found!\n");
6633 return; 6630 return;
6634 } 6631 }
6635 6632
6636 /* Clear device-specific "PCI retry timeout" register (41h). */ 6633 /* Clear device-specific "PCI retry timeout" register (41h). */
6637 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 6634 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40);
6638 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00); 6635 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00);
6639 6636
6640 /* Enable bus-mastering and hardware bug workaround. */ 6637 /* Enable bus-mastering and hardware bug workaround. */
6641 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 6638 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG);
6642 reg |= PCI_COMMAND_MASTER_ENABLE; 6639 reg |= PCI_COMMAND_MASTER_ENABLE;
6643 /* if !MSI */ 6640 /* if !MSI */
6644 if (reg & PCI_COMMAND_INTERRUPT_DISABLE) { 6641 if (reg & PCI_COMMAND_INTERRUPT_DISABLE) {
6645 reg &= ~PCI_COMMAND_INTERRUPT_DISABLE; 6642 reg &= ~PCI_COMMAND_INTERRUPT_DISABLE;
6646 } 6643 }
6647 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg); 6644 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg);
6648 6645
6649 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START); 6646 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START);
6650 error = pci_mapreg_map(pa, PCI_MAPREG_START, memtype, 0, 6647 error = pci_mapreg_map(pa, PCI_MAPREG_START, memtype, 0,
6651 &sc->sc_st, &sc->sc_sh, NULL, &sc->sc_sz); 6648 &sc->sc_st, &sc->sc_sh, NULL, &sc->sc_sz);
6652 if (error != 0) { 6649 if (error != 0) {
6653 aprint_error_dev(self, "can't map mem space\n"); 6650 aprint_error_dev(self, "can't map mem space\n");
6654 return; 6651 return;
6655 } 6652 }
6656 6653
6657 /* Install interrupt handler. */ 6654 /* Install interrupt handler. */
6658#ifdef __HAVE_PCI_MSI_MSIX 
6659 error = pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0); 6655 error = pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0);
6660 if (error != 0) { 6656 if (error != 0) {
6661 aprint_error_dev(self, "can't allocate interrupt\n"); 6657 aprint_error_dev(self, "can't allocate interrupt\n");
6662 return; 6658 return;
6663 } 6659 }
6664 intrstr = pci_intr_string(sc->sc_pct, sc->sc_pihp[0], intrbuf, 6660 intrstr = pci_intr_string(sc->sc_pct, sc->sc_pihp[0], intrbuf,
6665 sizeof(intrbuf)); 6661 sizeof(intrbuf));
6666 sc->sc_ih = pci_intr_establish(sc->sc_pct, sc->sc_pihp[0], IPL_NET, 6662 sc->sc_ih = pci_intr_establish(sc->sc_pct, sc->sc_pihp[0], IPL_NET,
6667 iwm_intr, sc); 6663 iwm_intr, sc);
6668#else /* !__HAVE_PCI_MSI_MSIX */ 
6669 if (pci_intr_map(pa, &ih)) { 
6670 aprint_error_dev(self, "can't map interrupt\n"); 
6671 return; 
6672 } 
6673 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf)); 
6674 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, iwm_intr, sc); 
6675#endif /* __HAVE_PCI_MSI_MSIX */ 
6676 if (sc->sc_ih == NULL) { 6664 if (sc->sc_ih == NULL) {
6677 aprint_error_dev(self, "can't establish interrupt"); 6665 aprint_error_dev(self, "can't establish interrupt");
6678 if (intrstr != NULL) 6666 if (intrstr != NULL)
6679 aprint_error(" at %s", intrstr); 6667 aprint_error(" at %s", intrstr);
6680 aprint_error("\n"); 6668 aprint_error("\n");
6681 return; 6669 return;
6682 } 6670 }
6683 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 6671 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
6684 6672
6685 sc->sc_wantresp = -1; 6673 sc->sc_wantresp = -1;
6686 6674
6687 switch (PCI_PRODUCT(sc->sc_pciid)) { 6675 switch (PCI_PRODUCT(sc->sc_pciid)) {
6688 case PCI_PRODUCT_INTEL_WIFI_LINK_7260_1: 6676 case PCI_PRODUCT_INTEL_WIFI_LINK_7260_1:
6689 case PCI_PRODUCT_INTEL_WIFI_LINK_7260_2: 6677 case PCI_PRODUCT_INTEL_WIFI_LINK_7260_2:
6690 sc->sc_fwname = "iwlwifi-7260-9.ucode"; 6678 sc->sc_fwname = "iwlwifi-7260-9.ucode";
6691 sc->host_interrupt_operation_mode = 1; 6679 sc->host_interrupt_operation_mode = 1;
6692 break; 6680 break;
6693 case PCI_PRODUCT_INTEL_WIFI_LINK_3160_1: 6681 case PCI_PRODUCT_INTEL_WIFI_LINK_3160_1:
6694 case PCI_PRODUCT_INTEL_WIFI_LINK_3160_2: 6682 case PCI_PRODUCT_INTEL_WIFI_LINK_3160_2:
6695 sc->sc_fwname = "iwlwifi-3160-9.ucode"; 6683 sc->sc_fwname = "iwlwifi-3160-9.ucode";
6696 sc->host_interrupt_operation_mode = 1; 6684 sc->host_interrupt_operation_mode = 1;
6697 break; 6685 break;
6698 case PCI_PRODUCT_INTEL_WIFI_LINK_7265_1: 6686 case PCI_PRODUCT_INTEL_WIFI_LINK_7265_1:
6699 case PCI_PRODUCT_INTEL_WIFI_LINK_7265_2: 6687 case PCI_PRODUCT_INTEL_WIFI_LINK_7265_2:
6700 sc->sc_fwname = "iwlwifi-7265-9.ucode"; 6688 sc->sc_fwname = "iwlwifi-7265-9.ucode";
6701 sc->host_interrupt_operation_mode = 0; 6689 sc->host_interrupt_operation_mode = 0;
6702 break; 6690 break;
6703 default: 6691 default:
6704 aprint_error_dev(self, "unknown product %#x", 6692 aprint_error_dev(self, "unknown product %#x",
6705 PCI_PRODUCT(sc->sc_pciid)); 6693 PCI_PRODUCT(sc->sc_pciid));
6706 return; 6694 return;
6707 } 6695 }
6708 DPRINTF(("%s: firmware=%s\n", DEVNAME(sc), sc->sc_fwname)); 6696 DPRINTF(("%s: firmware=%s\n", DEVNAME(sc), sc->sc_fwname));
6709 sc->sc_fwdmasegsz = IWM_FWDMASEGSZ; 6697 sc->sc_fwdmasegsz = IWM_FWDMASEGSZ;
6710 6698
6711 /* 6699 /*
6712 * We now start fiddling with the hardware 6700 * We now start fiddling with the hardware
6713 */ 6701 */
6714 6702
6715 sc->sc_hw_rev = IWM_READ(sc, IWM_CSR_HW_REV); 6703 sc->sc_hw_rev = IWM_READ(sc, IWM_CSR_HW_REV);
6716 if (iwm_prepare_card_hw(sc) != 0) { 6704 if (iwm_prepare_card_hw(sc) != 0) {
6717 aprint_error_dev(sc->sc_dev, "could not initialize hardware\n"); 6705 aprint_error_dev(sc->sc_dev, "could not initialize hardware\n");
6718 return; 6706 return;
6719 } 6707 }
6720 6708
6721 /* Allocate DMA memory for firmware transfers. */ 6709 /* Allocate DMA memory for firmware transfers. */
6722 if ((error = iwm_alloc_fwmem(sc)) != 0) { 6710 if ((error = iwm_alloc_fwmem(sc)) != 0) {
6723 aprint_error_dev(sc->sc_dev, 6711 aprint_error_dev(sc->sc_dev,
6724 "could not allocate memory for firmware\n"); 6712 "could not allocate memory for firmware\n");
6725 return; 6713 return;
6726 } 6714 }
6727 6715
6728 /* Allocate "Keep Warm" page. */ 6716 /* Allocate "Keep Warm" page. */
6729 if ((error = iwm_alloc_kw(sc)) != 0) { 6717 if ((error = iwm_alloc_kw(sc)) != 0) {
6730 aprint_error_dev(sc->sc_dev, 6718 aprint_error_dev(sc->sc_dev,
6731 "could not allocate keep warm page\n"); 6719 "could not allocate keep warm page\n");
6732 goto fail1; 6720 goto fail1;
6733 } 6721 }
6734 6722
6735 /* We use ICT interrupts */ 6723 /* We use ICT interrupts */
6736 if ((error = iwm_alloc_ict(sc)) != 0) { 6724 if ((error = iwm_alloc_ict(sc)) != 0) {
6737 aprint_error_dev(sc->sc_dev, "could not allocate ICT table\n"); 6725 aprint_error_dev(sc->sc_dev, "could not allocate ICT table\n");
6738 goto fail2; 6726 goto fail2;
6739 } 6727 }
6740 6728
6741 /* Allocate TX scheduler "rings". */ 6729 /* Allocate TX scheduler "rings". */
6742 if ((error = iwm_alloc_sched(sc)) != 0) { 6730 if ((error = iwm_alloc_sched(sc)) != 0) {
6743 aprint_error_dev(sc->sc_dev, 6731 aprint_error_dev(sc->sc_dev,
6744 "could not allocate TX scheduler rings\n"); 6732 "could not allocate TX scheduler rings\n");
6745 goto fail3; 6733 goto fail3;
6746 } 6734 }
6747 6735
6748 /* Allocate TX rings */ 6736 /* Allocate TX rings */
6749 for (txq_i = 0; txq_i < __arraycount(sc->txq); txq_i++) { 6737 for (txq_i = 0; txq_i < __arraycount(sc->txq); txq_i++) {
6750 if ((error = iwm_alloc_tx_ring(sc, 6738 if ((error = iwm_alloc_tx_ring(sc,
6751 &sc->txq[txq_i], txq_i)) != 0) { 6739 &sc->txq[txq_i], txq_i)) != 0) {
6752 aprint_error_dev(sc->sc_dev, 6740 aprint_error_dev(sc->sc_dev,
6753 "could not allocate TX ring %d\n", txq_i); 6741 "could not allocate TX ring %d\n", txq_i);
6754 goto fail4; 6742 goto fail4;
6755 } 6743 }
6756 } 6744 }
6757 6745
6758 /* Allocate RX ring. */ 6746 /* Allocate RX ring. */
6759 if ((error = iwm_alloc_rx_ring(sc, &sc->rxq)) != 0) { 6747 if ((error = iwm_alloc_rx_ring(sc, &sc->rxq)) != 0) {
6760 aprint_error_dev(sc->sc_dev, "could not allocate RX ring\n"); 6748 aprint_error_dev(sc->sc_dev, "could not allocate RX ring\n");
6761 goto fail4; 6749 goto fail4;
6762 } 6750 }
6763 6751
6764 workqueue_create(&sc->sc_eswq, "iwmes", 6752 workqueue_create(&sc->sc_eswq, "iwmes",
6765 iwm_endscan_cb, sc, PRI_NONE, IPL_NET, 0); 6753 iwm_endscan_cb, sc, PRI_NONE, IPL_NET, 0);
6766 workqueue_create(&sc->sc_nswq, "iwmns", 6754 workqueue_create(&sc->sc_nswq, "iwmns",
6767 iwm_newstate_cb, sc, PRI_NONE, IPL_NET, 0); 6755 iwm_newstate_cb, sc, PRI_NONE, IPL_NET, 0);
6768 6756
6769 /* Clear pending interrupts. */ 6757 /* Clear pending interrupts. */
6770 IWM_WRITE(sc, IWM_CSR_INT, 0xffffffff); 6758 IWM_WRITE(sc, IWM_CSR_INT, 0xffffffff);
6771 6759
6772 if ((error = sysctl_createv(&sc->sc_clog, 0, NULL, &node, 6760 if ((error = sysctl_createv(&sc->sc_clog, 0, NULL, &node,
6773 0, CTLTYPE_NODE, device_xname(sc->sc_dev), 6761 0, CTLTYPE_NODE, device_xname(sc->sc_dev),
6774 SYSCTL_DESCR("iwm per-controller controls"), 6762 SYSCTL_DESCR("iwm per-controller controls"),
6775 NULL, 0, NULL, 0, 6763 NULL, 0, NULL, 0,
6776 CTL_HW, iwm_sysctl_root_num, CTL_CREATE, 6764 CTL_HW, iwm_sysctl_root_num, CTL_CREATE,
6777 CTL_EOL)) != 0) { 6765 CTL_EOL)) != 0) {
6778 aprint_normal_dev(sc->sc_dev, 6766 aprint_normal_dev(sc->sc_dev,
6779 "couldn't create iwm per-controller sysctl node\n"); 6767 "couldn't create iwm per-controller sysctl node\n");
6780 } 6768 }
6781 if (error == 0) { 6769 if (error == 0) {
6782 int iwm_nodenum = node->sysctl_num; 6770 int iwm_nodenum = node->sysctl_num;
6783 6771
6784 /* Reload firmware sysctl node */ 6772 /* Reload firmware sysctl node */
6785 if ((error = sysctl_createv(&sc->sc_clog, 0, NULL, &node, 6773 if ((error = sysctl_createv(&sc->sc_clog, 0, NULL, &node,
6786 CTLFLAG_READWRITE, CTLTYPE_INT, "fw_loaded", 6774 CTLFLAG_READWRITE, CTLTYPE_INT, "fw_loaded",
6787 SYSCTL_DESCR("Reload firmware"), 6775 SYSCTL_DESCR("Reload firmware"),
6788 iwm_sysctl_fw_loaded_handler, 0, (void *)sc, 0, 6776 iwm_sysctl_fw_loaded_handler, 0, (void *)sc, 0,
6789 CTL_HW, iwm_sysctl_root_num, iwm_nodenum, CTL_CREATE, 6777 CTL_HW, iwm_sysctl_root_num, iwm_nodenum, CTL_CREATE,
6790 CTL_EOL)) != 0) { 6778 CTL_EOL)) != 0) {
6791 aprint_normal_dev(sc->sc_dev, 6779 aprint_normal_dev(sc->sc_dev,
6792 "couldn't create load_fw sysctl node\n"); 6780 "couldn't create load_fw sysctl node\n");
6793 } 6781 }
6794 } 6782 }
6795 6783
6796 /* 6784 /*
6797 * Attach interface 6785 * Attach interface
6798 */ 6786 */
6799 ic->ic_ifp = ifp; 6787 ic->ic_ifp = ifp;
6800 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 6788 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
6801 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 6789 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
6802 ic->ic_state = IEEE80211_S_INIT; 6790 ic->ic_state = IEEE80211_S_INIT;
6803 6791
6804 /* Set device capabilities. */ 6792 /* Set device capabilities. */
6805 ic->ic_caps = 6793 ic->ic_caps =
6806 IEEE80211_C_WEP | /* WEP */ 6794 IEEE80211_C_WEP | /* WEP */
6807 IEEE80211_C_WPA | /* 802.11i */ 6795 IEEE80211_C_WPA | /* 802.11i */
6808 IEEE80211_C_SHSLOT | /* short slot time supported */ 6796 IEEE80211_C_SHSLOT | /* short slot time supported */
6809 IEEE80211_C_SHPREAMBLE; /* short preamble supported */ 6797 IEEE80211_C_SHPREAMBLE; /* short preamble supported */
6810 6798
6811 /* all hardware can do 2.4GHz band */ 6799 /* all hardware can do 2.4GHz band */
6812 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 6800 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b;
6813 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 6801 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g;
6814 6802
6815 for (int i = 0; i < __arraycount(sc->sc_phyctxt); i++) { 6803 for (int i = 0; i < __arraycount(sc->sc_phyctxt); i++) {
6816 sc->sc_phyctxt[i].id = i; 6804 sc->sc_phyctxt[i].id = i;
6817 } 6805 }
6818 6806
6819 sc->sc_amrr.amrr_min_success_threshold = 1; 6807 sc->sc_amrr.amrr_min_success_threshold = 1;
6820 sc->sc_amrr.amrr_max_success_threshold = 15; 6808 sc->sc_amrr.amrr_max_success_threshold = 15;
6821 6809
6822 /* IBSS channel undefined for now. */ 6810 /* IBSS channel undefined for now. */
6823 ic->ic_ibss_chan = &ic->ic_channels[1]; 6811 ic->ic_ibss_chan = &ic->ic_channels[1];
6824 6812
6825#if 0 6813#if 0
6826 /* Max RSSI */ 6814 /* Max RSSI */
6827 ic->ic_max_rssi = IWM_MAX_DBM - IWM_MIN_DBM; 6815 ic->ic_max_rssi = IWM_MAX_DBM - IWM_MIN_DBM;
6828#endif 6816#endif
6829 6817
6830 ifp->if_softc = sc; 6818 ifp->if_softc = sc;
6831 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 6819 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
6832 ifp->if_init = iwm_init; 6820 ifp->if_init = iwm_init;
6833 ifp->if_stop = iwm_stop; 6821 ifp->if_stop = iwm_stop;
6834 ifp->if_ioctl = iwm_ioctl; 6822 ifp->if_ioctl = iwm_ioctl;
6835 ifp->if_start = iwm_start; 6823 ifp->if_start = iwm_start;
6836 ifp->if_watchdog = iwm_watchdog; 6824 ifp->if_watchdog = iwm_watchdog;
6837 IFQ_SET_READY(&ifp->if_snd); 6825 IFQ_SET_READY(&ifp->if_snd);
6838 memcpy(ifp->if_xname, DEVNAME(sc), IFNAMSIZ); 6826 memcpy(ifp->if_xname, DEVNAME(sc), IFNAMSIZ);
6839 6827
6840 if_initialize(ifp); 6828 if_initialize(ifp);
6841#if 0 6829#if 0
6842 ieee80211_ifattach(ic); 6830 ieee80211_ifattach(ic);
6843#else 6831#else
6844 ether_ifattach(ifp, ic->ic_myaddr); /* XXX */ 6832 ether_ifattach(ifp, ic->ic_myaddr); /* XXX */
6845#endif 6833#endif
6846 if_register(ifp); 6834 if_register(ifp);
6847 6835
6848 callout_init(&sc->sc_calib_to, 0); 6836 callout_init(&sc->sc_calib_to, 0);
6849 callout_setfunc(&sc->sc_calib_to, iwm_calib_timeout, sc); 6837 callout_setfunc(&sc->sc_calib_to, iwm_calib_timeout, sc);
6850 6838
6851 //task_set(&sc->init_task, iwm_init_task, sc); 6839 //task_set(&sc->init_task, iwm_init_task, sc);
6852 6840
6853 if (pmf_device_register(self, NULL, NULL)) 6841 if (pmf_device_register(self, NULL, NULL))
6854 pmf_class_network_register(self, ifp); 6842 pmf_class_network_register(self, ifp);
6855 else 6843 else
6856 aprint_error_dev(self, "couldn't establish power handler\n"); 6844 aprint_error_dev(self, "couldn't establish power handler\n");
6857 6845
6858 /* 6846 /*
6859 * We can't do normal attach before the file system is mounted 6847 * We can't do normal attach before the file system is mounted
6860 * because we cannot read the MAC address without loading the 6848 * because we cannot read the MAC address without loading the
6861 * firmware from disk. So we postpone until mountroot is done. 6849 * firmware from disk. So we postpone until mountroot is done.
6862 * Notably, this will require a full driver unload/load cycle 6850 * Notably, this will require a full driver unload/load cycle
6863 * (or reboot) in case the firmware is not present when the 6851 * (or reboot) in case the firmware is not present when the
6864 * hook runs. 6852 * hook runs.
6865 */ 6853 */
6866 config_mountroot(self, iwm_attach_hook); 6854 config_mountroot(self, iwm_attach_hook);
6867 6855
6868 return; 6856 return;
6869 6857
6870 /* Free allocated memory if something failed during attachment. */ 6858 /* Free allocated memory if something failed during attachment. */
6871fail4: while (--txq_i >= 0) 6859fail4: while (--txq_i >= 0)
6872 iwm_free_tx_ring(sc, &sc->txq[txq_i]); 6860 iwm_free_tx_ring(sc, &sc->txq[txq_i]);
6873 iwm_free_sched(sc); 6861 iwm_free_sched(sc);
6874fail3: if (sc->ict_dma.vaddr != NULL) 6862fail3: if (sc->ict_dma.vaddr != NULL)
6875 iwm_free_ict(sc); 6863 iwm_free_ict(sc);
6876fail2: iwm_free_kw(sc); 6864fail2: iwm_free_kw(sc);
6877fail1: iwm_free_fwmem(sc); 6865fail1: iwm_free_fwmem(sc);
6878} 6866}
6879 6867
6880/* 6868/*
6881 * Attach the interface to 802.11 radiotap. 6869 * Attach the interface to 802.11 radiotap.
6882 */ 6870 */
6883void 6871void
6884iwm_radiotap_attach(struct iwm_softc *sc) 6872iwm_radiotap_attach(struct iwm_softc *sc)
6885{ 6873{
6886 struct ifnet *ifp = sc->sc_ic.ic_ifp; 6874 struct ifnet *ifp = sc->sc_ic.ic_ifp;
6887 6875
6888 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 6876 bpf_attach2(ifp, DLT_IEEE802_11_RADIO,
6889 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 6877 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN,
6890 &sc->sc_drvbpf); 6878 &sc->sc_drvbpf);
6891 6879
6892 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 6880 sc->sc_rxtap_len = sizeof sc->sc_rxtapu;
6893 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 6881 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len);
6894 sc->sc_rxtap.wr_ihdr.it_present = htole32(IWM_RX_RADIOTAP_PRESENT); 6882 sc->sc_rxtap.wr_ihdr.it_present = htole32(IWM_RX_RADIOTAP_PRESENT);
6895 6883
6896 sc->sc_txtap_len = sizeof sc->sc_txtapu; 6884 sc->sc_txtap_len = sizeof sc->sc_txtapu;
6897 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 6885 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len);
6898 sc->sc_txtap.wt_ihdr.it_present = htole32(IWM_TX_RADIOTAP_PRESENT); 6886 sc->sc_txtap.wt_ihdr.it_present = htole32(IWM_TX_RADIOTAP_PRESENT);
6899} 6887}
6900 6888
6901#if 0 6889#if 0
6902static void 6890static void
6903iwm_init_task(void *arg1) 6891iwm_init_task(void *arg1)
6904{ 6892{
6905 struct iwm_softc *sc = arg1; 6893 struct iwm_softc *sc = arg1;
6906 struct ifnet *ifp = &sc->sc_ic.ic_if; 6894 struct ifnet *ifp = &sc->sc_ic.ic_if;
6907 int s; 6895 int s;
6908 6896
6909 s = splnet(); 6897 s = splnet();
6910 while (sc->sc_flags & IWM_FLAG_BUSY) 6898 while (sc->sc_flags & IWM_FLAG_BUSY)
6911 tsleep(&sc->sc_flags, 0, "iwmpwr", 0); 6899 tsleep(&sc->sc_flags, 0, "iwmpwr", 0);
6912 sc->sc_flags |= IWM_FLAG_BUSY; 6900 sc->sc_flags |= IWM_FLAG_BUSY;
6913 6901
6914 iwm_stop(ifp, 0); 6902 iwm_stop(ifp, 0);
6915 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == IFF_UP) 6903 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == IFF_UP)
6916 iwm_init(ifp); 6904 iwm_init(ifp);
6917 6905
6918 sc->sc_flags &= ~IWM_FLAG_BUSY; 6906 sc->sc_flags &= ~IWM_FLAG_BUSY;
6919 wakeup(&sc->sc_flags); 6907 wakeup(&sc->sc_flags);
6920 splx(s); 6908 splx(s);
6921} 6909}
6922 6910
6923static void 6911static void
6924iwm_wakeup(struct iwm_softc *sc) 6912iwm_wakeup(struct iwm_softc *sc)
6925{ 6913{
6926 pcireg_t reg; 6914 pcireg_t reg;
6927 6915
6928 /* Clear device-specific "PCI retry timeout" register (41h). */ 6916 /* Clear device-specific "PCI retry timeout" register (41h). */
6929 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 6917 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40);
6930 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00); 6918 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00);
6931 6919
6932 iwm_init_task(sc); 6920 iwm_init_task(sc);
6933} 6921}
6934 6922
6935static int 6923static int
6936iwm_activate(device_t self, enum devact act) 6924iwm_activate(device_t self, enum devact act)
6937{ 6925{
6938 struct iwm_softc *sc = device_private(self); 6926 struct iwm_softc *sc = device_private(self);
6939 struct ifnet *ifp = IC2IFP(&sc->sc_ic); 6927 struct ifnet *ifp = IC2IFP(&sc->sc_ic);
6940 6928
6941 switch (act) { 6929 switch (act) {
6942 case DVACT_DEACTIVATE: 6930 case DVACT_DEACTIVATE:
6943 if (ifp->if_flags & IFF_RUNNING) 6931 if (ifp->if_flags & IFF_RUNNING)
6944 iwm_stop(ifp, 0); 6932 iwm_stop(ifp, 0);
6945 return 0; 6933 return 0;
6946 default: 6934 default:
6947 return EOPNOTSUPP; 6935 return EOPNOTSUPP;
6948 } 6936 }
6949} 6937}
6950#endif 6938#endif
6951 6939
6952CFATTACH_DECL_NEW(iwm, sizeof(struct iwm_softc), iwm_match, iwm_attach, 6940CFATTACH_DECL_NEW(iwm, sizeof(struct iwm_softc), iwm_match, iwm_attach,
6953 NULL, NULL); 6941 NULL, NULL);
6954 6942
6955static int 6943static int
6956iwm_sysctl_fw_loaded_handler(SYSCTLFN_ARGS) 6944iwm_sysctl_fw_loaded_handler(SYSCTLFN_ARGS)
6957{ 6945{
6958 struct sysctlnode node; 6946 struct sysctlnode node;
6959 struct iwm_softc *sc; 6947 struct iwm_softc *sc;
6960 int error, t; 6948 int error, t;
6961 6949
6962 node = *rnode; 6950 node = *rnode;
6963 sc = node.sysctl_data; 6951 sc = node.sysctl_data;
6964 t = ISSET(sc->sc_flags, IWM_FLAG_FW_LOADED) ? 1 : 0; 6952 t = ISSET(sc->sc_flags, IWM_FLAG_FW_LOADED) ? 1 : 0;
6965 node.sysctl_data = &t; 6953 node.sysctl_data = &t;
6966 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 6954 error = sysctl_lookup(SYSCTLFN_CALL(&node));
6967 if (error || newp == NULL) 6955 if (error || newp == NULL)
6968 return error; 6956 return error;
6969 6957
6970 if (t == 0) 6958 if (t == 0)
6971 CLR(sc->sc_flags, IWM_FLAG_FW_LOADED); 6959 CLR(sc->sc_flags, IWM_FLAG_FW_LOADED);
6972 return 0; 6960 return 0;
6973} 6961}
6974 6962
6975SYSCTL_SETUP(sysctl_iwm, "sysctl iwm(4) subtree setup") 6963SYSCTL_SETUP(sysctl_iwm, "sysctl iwm(4) subtree setup")
6976{ 6964{
6977 const struct sysctlnode *rnode; 6965 const struct sysctlnode *rnode;
6978#ifdef IWM_DEBUG 6966#ifdef IWM_DEBUG
6979 const struct sysctlnode *cnode; 6967 const struct sysctlnode *cnode;
6980#endif /* IWM_DEBUG */ 6968#endif /* IWM_DEBUG */
6981 int rc; 6969 int rc;
6982 6970
6983 if ((rc = sysctl_createv(clog, 0, NULL, &rnode, 6971 if ((rc = sysctl_createv(clog, 0, NULL, &rnode,
6984 CTLFLAG_PERMANENT, CTLTYPE_NODE, "iwm", 6972 CTLFLAG_PERMANENT, CTLTYPE_NODE, "iwm",
6985 SYSCTL_DESCR("iwm global controls"), 6973 SYSCTL_DESCR("iwm global controls"),
6986 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) 6974 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0)
6987 goto err; 6975 goto err;
6988 6976
6989 iwm_sysctl_root_num = rnode->sysctl_num; 6977 iwm_sysctl_root_num = rnode->sysctl_num;
6990 6978
6991#ifdef IWM_DEBUG 6979#ifdef IWM_DEBUG
6992 /* control debugging printfs */ 6980 /* control debugging printfs */
6993 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 6981 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode,
6994 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 6982 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
6995 "debug", SYSCTL_DESCR("Enable debugging output"), 6983 "debug", SYSCTL_DESCR("Enable debugging output"),
6996 NULL, 0, &iwm_debug, 0, CTL_CREATE, CTL_EOL)) != 0) 6984 NULL, 0, &iwm_debug, 0, CTL_CREATE, CTL_EOL)) != 0)
6997 goto err; 6985 goto err;
6998#endif /* IWM_DEBUG */ 6986#endif /* IWM_DEBUG */
6999 6987
7000 return; 6988 return;
7001 6989
7002 err: 6990 err:
7003 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 6991 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc);
7004} 6992}
cvs diff -r1.8 -r1.9 src/sys/dev/pci/if_iwmvar.h (switch to unified diff)

--- src/sys/dev/pci/if_iwmvar.h 2015/07/22 15:18:01 1.8
+++ src/sys/dev/pci/if_iwmvar.h 2015/11/06 14:22:17 1.9
@@ -1,521 +1,519 @@ @@ -1,521 +1,519 @@
1/* $NetBSD: if_iwmvar.h,v 1.8 2015/07/22 15:18:01 nonaka Exp $ */ 1/* $NetBSD: if_iwmvar.h,v 1.9 2015/11/06 14:22:17 nonaka Exp $ */
2/* OpenBSD: if_iwmvar.h,v 1.7 2015/03/02 13:51:10 jsg Exp */ 2/* OpenBSD: if_iwmvar.h,v 1.7 2015/03/02 13:51:10 jsg Exp */
3 3
4/* 4/*
5 * Copyright (c) 2014 genua mbh <info@genua.de> 5 * Copyright (c) 2014 genua mbh <info@genua.de>
6 * Copyright (c) 2014 Fixup Software Ltd. 6 * Copyright (c) 2014 Fixup Software Ltd.
7 * 7 *
8 * Permission to use, copy, modify, and distribute this software for any 8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above 9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies. 10 * copyright notice and this permission notice appear in all copies.
11 * 11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 */ 19 */
20 20
21/*- 21/*-
22 * Based on BSD-licensed source modules in the Linux iwlwifi driver, 22 * Based on BSD-licensed source modules in the Linux iwlwifi driver,
23 * which were used as the reference documentation for this implementation. 23 * which were used as the reference documentation for this implementation.
24 * 24 *
25 * Driver version we are currently based off of is 25 * Driver version we are currently based off of is
26 * Linux 3.14.3 (tag id a2df521e42b1d9a23f620ac79dbfe8655a8391dd) 26 * Linux 3.14.3 (tag id a2df521e42b1d9a23f620ac79dbfe8655a8391dd)
27 * 27 *
28 *********************************************************************** 28 ***********************************************************************
29 * 29 *
30 * This file is provided under a dual BSD/GPLv2 license. When using or 30 * This file is provided under a dual BSD/GPLv2 license. When using or
31 * redistributing this file, you may do so under either license. 31 * redistributing this file, you may do so under either license.
32 * 32 *
33 * GPL LICENSE SUMMARY 33 * GPL LICENSE SUMMARY
34 * 34 *
35 * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved. 35 * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved.
36 * 36 *
37 * This program is free software; you can redistribute it and/or modify 37 * This program is free software; you can redistribute it and/or modify
38 * it under the terms of version 2 of the GNU General Public License as 38 * it under the terms of version 2 of the GNU General Public License as
39 * published by the Free Software Foundation. 39 * published by the Free Software Foundation.
40 * 40 *
41 * This program is distributed in the hope that it will be useful, but 41 * This program is distributed in the hope that it will be useful, but
42 * WITHOUT ANY WARRANTY; without even the implied warranty of 42 * WITHOUT ANY WARRANTY; without even the implied warranty of
43 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 43 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
44 * General Public License for more details. 44 * General Public License for more details.
45 * 45 *
46 * You should have received a copy of the GNU General Public License 46 * You should have received a copy of the GNU General Public License
47 * along with this program; if not, write to the Free Software 47 * along with this program; if not, write to the Free Software
48 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 48 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
49 * USA 49 * USA
50 * 50 *
51 * The full GNU General Public License is included in this distribution 51 * The full GNU General Public License is included in this distribution
52 * in the file called COPYING. 52 * in the file called COPYING.
53 * 53 *
54 * Contact Information: 54 * Contact Information:
55 * Intel Linux Wireless <ilw@linux.intel.com> 55 * Intel Linux Wireless <ilw@linux.intel.com>
56 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 56 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
57 * 57 *
58 * 58 *
59 * BSD LICENSE 59 * BSD LICENSE
60 * 60 *
61 * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved. 61 * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved.
62 * All rights reserved. 62 * All rights reserved.
63 * 63 *
64 * Redistribution and use in source and binary forms, with or without 64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions 65 * modification, are permitted provided that the following conditions
66 * are met: 66 * are met:
67 * 67 *
68 * * Redistributions of source code must retain the above copyright 68 * * Redistributions of source code must retain the above copyright
69 * notice, this list of conditions and the following disclaimer. 69 * notice, this list of conditions and the following disclaimer.
70 * * Redistributions in binary form must reproduce the above copyright 70 * * Redistributions in binary form must reproduce the above copyright
71 * notice, this list of conditions and the following disclaimer in 71 * notice, this list of conditions and the following disclaimer in
72 * the documentation and/or other materials provided with the 72 * the documentation and/or other materials provided with the
73 * distribution. 73 * distribution.
74 * * Neither the name Intel Corporation nor the names of its 74 * * Neither the name Intel Corporation nor the names of its
75 * contributors may be used to endorse or promote products derived 75 * contributors may be used to endorse or promote products derived
76 * from this software without specific prior written permission. 76 * from this software without specific prior written permission.
77 * 77 *
78 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 78 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
79 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 79 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
80 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 80 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
81 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 81 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
82 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 82 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
83 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 83 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
84 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 84 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
85 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 85 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
86 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 86 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
87 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 87 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
88 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 88 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
89 */ 89 */
90 90
91/*- 91/*-
92 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 92 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr>
93 * 93 *
94 * Permission to use, copy, modify, and distribute this software for any 94 * Permission to use, copy, modify, and distribute this software for any
95 * purpose with or without fee is hereby granted, provided that the above 95 * purpose with or without fee is hereby granted, provided that the above
96 * copyright notice and this permission notice appear in all copies. 96 * copyright notice and this permission notice appear in all copies.
97 * 97 *
98 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 98 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
99 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 99 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
100 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 100 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
101 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 101 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
102 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 102 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
103 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 103 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
104 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 104 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
105 */ 105 */
106 106
107struct iwm_rx_radiotap_header { 107struct iwm_rx_radiotap_header {
108 struct ieee80211_radiotap_header wr_ihdr; 108 struct ieee80211_radiotap_header wr_ihdr;
109 uint64_t wr_tsft; 109 uint64_t wr_tsft;
110 uint8_t wr_flags; 110 uint8_t wr_flags;
111 uint8_t wr_rate; 111 uint8_t wr_rate;
112 uint16_t wr_chan_freq; 112 uint16_t wr_chan_freq;
113 uint16_t wr_chan_flags; 113 uint16_t wr_chan_flags;
114 int8_t wr_dbm_antsignal; 114 int8_t wr_dbm_antsignal;
115 int8_t wr_dbm_antnoise; 115 int8_t wr_dbm_antnoise;
116} __packed; 116} __packed;
117 117
118#define IWM_RX_RADIOTAP_PRESENT \ 118#define IWM_RX_RADIOTAP_PRESENT \
119 ((1 << IEEE80211_RADIOTAP_TSFT) | \ 119 ((1 << IEEE80211_RADIOTAP_TSFT) | \
120 (1 << IEEE80211_RADIOTAP_FLAGS) | \ 120 (1 << IEEE80211_RADIOTAP_FLAGS) | \
121 (1 << IEEE80211_RADIOTAP_RATE) | \ 121 (1 << IEEE80211_RADIOTAP_RATE) | \
122 (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 122 (1 << IEEE80211_RADIOTAP_CHANNEL) | \
123 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \ 123 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \
124 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE)) 124 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE))
125 125
126struct iwm_tx_radiotap_header { 126struct iwm_tx_radiotap_header {
127 struct ieee80211_radiotap_header wt_ihdr; 127 struct ieee80211_radiotap_header wt_ihdr;
128 uint8_t wt_flags; 128 uint8_t wt_flags;
129 uint8_t wt_rate; 129 uint8_t wt_rate;
130 uint16_t wt_chan_freq; 130 uint16_t wt_chan_freq;
131 uint16_t wt_chan_flags; 131 uint16_t wt_chan_flags;
132 uint8_t wt_hwqueue; 132 uint8_t wt_hwqueue;
133} __packed; 133} __packed;
134 134
135#define IWM_TX_RADIOTAP_PRESENT \ 135#define IWM_TX_RADIOTAP_PRESENT \
136 ((1 << IEEE80211_RADIOTAP_FLAGS) | \ 136 ((1 << IEEE80211_RADIOTAP_FLAGS) | \
137 (1 << IEEE80211_RADIOTAP_RATE) | \ 137 (1 << IEEE80211_RADIOTAP_RATE) | \
138 (1 << IEEE80211_RADIOTAP_CHANNEL)) 138 (1 << IEEE80211_RADIOTAP_CHANNEL))
139 139
140#define IWM_UCODE_SECT_MAX 6 140#define IWM_UCODE_SECT_MAX 6
141#define IWM_FWDMASEGSZ (192*1024) 141#define IWM_FWDMASEGSZ (192*1024)
142/* sanity check value */ 142/* sanity check value */
143#define IWM_FWMAXSIZE (2*1024*1024) 143#define IWM_FWMAXSIZE (2*1024*1024)
144 144
145/* 145/*
146 * fw_status is used to determine if we've already parsed the firmware file 146 * fw_status is used to determine if we've already parsed the firmware file
147 * 147 *
148 * In addition to the following, status < 0 ==> -error 148 * In addition to the following, status < 0 ==> -error
149 */ 149 */
150#define IWM_FW_STATUS_NONE 0 150#define IWM_FW_STATUS_NONE 0
151#define IWM_FW_STATUS_INPROGRESS 1 151#define IWM_FW_STATUS_INPROGRESS 1
152#define IWM_FW_STATUS_DONE 2 152#define IWM_FW_STATUS_DONE 2
153 153
154enum iwm_ucode_type { 154enum iwm_ucode_type {
155 IWM_UCODE_TYPE_INIT, 155 IWM_UCODE_TYPE_INIT,
156 IWM_UCODE_TYPE_REGULAR, 156 IWM_UCODE_TYPE_REGULAR,
157 IWM_UCODE_TYPE_WOW, 157 IWM_UCODE_TYPE_WOW,
158 IWM_UCODE_TYPE_MAX 158 IWM_UCODE_TYPE_MAX
159}; 159};
160 160
161struct iwm_fw_info { 161struct iwm_fw_info {
162 void *fw_rawdata; 162 void *fw_rawdata;
163 size_t fw_rawsize; 163 size_t fw_rawsize;
164 int fw_status; 164 int fw_status;
165 165
166 struct iwm_fw_sects { 166 struct iwm_fw_sects {
167 struct iwm_fw_onesect { 167 struct iwm_fw_onesect {
168 void *fws_data; 168 void *fws_data;
169 uint32_t fws_len; 169 uint32_t fws_len;
170 uint32_t fws_devoff; 170 uint32_t fws_devoff;
171 171
172 void *fws_alloc; 172 void *fws_alloc;
173 size_t fws_allocsize; 173 size_t fws_allocsize;
174 } fw_sect[IWM_UCODE_SECT_MAX]; 174 } fw_sect[IWM_UCODE_SECT_MAX];
175 size_t fw_totlen; 175 size_t fw_totlen;
176 int fw_count; 176 int fw_count;
177 } fw_sects[IWM_UCODE_TYPE_MAX]; 177 } fw_sects[IWM_UCODE_TYPE_MAX];
178}; 178};
179 179
180struct iwm_nvm_data { 180struct iwm_nvm_data {
181 int n_hw_addrs; 181 int n_hw_addrs;
182 uint8_t hw_addr[ETHER_ADDR_LEN]; 182 uint8_t hw_addr[ETHER_ADDR_LEN];
183 183
184 uint8_t calib_version; 184 uint8_t calib_version;
185 uint16_t calib_voltage; 185 uint16_t calib_voltage;
186 186
187 uint16_t raw_temperature; 187 uint16_t raw_temperature;
188 uint16_t kelvin_temperature; 188 uint16_t kelvin_temperature;
189 uint16_t kelvin_voltage; 189 uint16_t kelvin_voltage;
190 uint16_t xtal_calib[2]; 190 uint16_t xtal_calib[2];
191 191
192 int sku_cap_band_24GHz_enable; 192 int sku_cap_band_24GHz_enable;
193 int sku_cap_band_52GHz_enable; 193 int sku_cap_band_52GHz_enable;
194 int sku_cap_11n_enable; 194 int sku_cap_11n_enable;
195 int sku_cap_amt_enable; 195 int sku_cap_amt_enable;
196 int sku_cap_ipan_enable; 196 int sku_cap_ipan_enable;
197 197
198 uint8_t radio_cfg_type; 198 uint8_t radio_cfg_type;
199 uint8_t radio_cfg_step; 199 uint8_t radio_cfg_step;
200 uint8_t radio_cfg_dash; 200 uint8_t radio_cfg_dash;
201 uint8_t radio_cfg_pnum; 201 uint8_t radio_cfg_pnum;
202 uint8_t valid_tx_ant, valid_rx_ant; 202 uint8_t valid_tx_ant, valid_rx_ant;
203 203
204 uint16_t nvm_version; 204 uint16_t nvm_version;
205 uint8_t max_tx_pwr_half_dbm; 205 uint8_t max_tx_pwr_half_dbm;
206}; 206};
207 207
208/* max bufs per tfd the driver will use */ 208/* max bufs per tfd the driver will use */
209#define IWM_MAX_CMD_TBS_PER_TFD 2 209#define IWM_MAX_CMD_TBS_PER_TFD 2
210 210
211struct iwm_rx_packet; 211struct iwm_rx_packet;
212struct iwm_host_cmd { 212struct iwm_host_cmd {
213 const void *data[IWM_MAX_CMD_TBS_PER_TFD]; 213 const void *data[IWM_MAX_CMD_TBS_PER_TFD];
214 struct iwm_rx_packet *resp_pkt; 214 struct iwm_rx_packet *resp_pkt;
215 unsigned long _rx_page_addr; 215 unsigned long _rx_page_addr;
216 uint32_t _rx_page_order; 216 uint32_t _rx_page_order;
217 int handler_status; 217 int handler_status;
218 218
219 uint32_t flags; 219 uint32_t flags;
220 uint16_t len[IWM_MAX_CMD_TBS_PER_TFD]; 220 uint16_t len[IWM_MAX_CMD_TBS_PER_TFD];
221 uint8_t dataflags[IWM_MAX_CMD_TBS_PER_TFD]; 221 uint8_t dataflags[IWM_MAX_CMD_TBS_PER_TFD];
222 uint8_t id; 222 uint8_t id;
223}; 223};
224 224
225/* 225/*
226 * DMA glue is from iwn 226 * DMA glue is from iwn
227 */ 227 */
228 228
229struct iwm_dma_info { 229struct iwm_dma_info {
230 bus_dma_tag_t tag; 230 bus_dma_tag_t tag;
231 bus_dmamap_t map; 231 bus_dmamap_t map;
232 bus_dma_segment_t seg; 232 bus_dma_segment_t seg;
233 bus_addr_t paddr; 233 bus_addr_t paddr;
234 void *vaddr; 234 void *vaddr;
235 bus_size_t size; 235 bus_size_t size;
236}; 236};
237 237
238#define IWM_TX_RING_COUNT 256 238#define IWM_TX_RING_COUNT 256
239#define IWM_TX_RING_LOMARK 192 239#define IWM_TX_RING_LOMARK 192
240#define IWM_TX_RING_HIMARK 224 240#define IWM_TX_RING_HIMARK 224
241 241
242struct iwm_tx_data { 242struct iwm_tx_data {
243 bus_dmamap_t map; 243 bus_dmamap_t map;
244 bus_addr_t cmd_paddr; 244 bus_addr_t cmd_paddr;
245 bus_addr_t scratch_paddr; 245 bus_addr_t scratch_paddr;
246 struct mbuf *m; 246 struct mbuf *m;
247 struct iwm_node *in; 247 struct iwm_node *in;
248 int done; 248 int done;
249}; 249};
250 250
251struct iwm_tx_ring { 251struct iwm_tx_ring {
252 struct iwm_dma_info desc_dma; 252 struct iwm_dma_info desc_dma;
253 struct iwm_dma_info cmd_dma; 253 struct iwm_dma_info cmd_dma;
254 struct iwm_tfd *desc; 254 struct iwm_tfd *desc;
255 struct iwm_device_cmd *cmd; 255 struct iwm_device_cmd *cmd;
256 struct iwm_tx_data data[IWM_TX_RING_COUNT]; 256 struct iwm_tx_data data[IWM_TX_RING_COUNT];
257 int qid; 257 int qid;
258 int queued; 258 int queued;
259 int cur; 259 int cur;
260}; 260};
261 261
262#define IWM_RX_RING_COUNT 256 262#define IWM_RX_RING_COUNT 256
263#define IWM_RBUF_COUNT (IWM_RX_RING_COUNT + 32) 263#define IWM_RBUF_COUNT (IWM_RX_RING_COUNT + 32)
264/* Linux driver optionally uses 8k buffer */ 264/* Linux driver optionally uses 8k buffer */
265#define IWM_RBUF_SIZE 4096 265#define IWM_RBUF_SIZE 4096
266 266
267struct iwm_softc; 267struct iwm_softc;
268struct iwm_rbuf { 268struct iwm_rbuf {
269 struct iwm_softc *sc; 269 struct iwm_softc *sc;
270 void *vaddr; 270 void *vaddr;
271 bus_addr_t paddr; 271 bus_addr_t paddr;
272}; 272};
273 273
274struct iwm_rx_data { 274struct iwm_rx_data {
275 struct mbuf *m; 275 struct mbuf *m;
276 bus_dmamap_t map; 276 bus_dmamap_t map;
277 int wantresp; 277 int wantresp;
278}; 278};
279 279
280struct iwm_rx_ring { 280struct iwm_rx_ring {
281 struct iwm_dma_info desc_dma; 281 struct iwm_dma_info desc_dma;
282 struct iwm_dma_info stat_dma; 282 struct iwm_dma_info stat_dma;
283 struct iwm_dma_info buf_dma; 283 struct iwm_dma_info buf_dma;
284 uint32_t *desc; 284 uint32_t *desc;
285 struct iwm_rb_status *stat; 285 struct iwm_rb_status *stat;
286 struct iwm_rx_data data[IWM_RX_RING_COUNT]; 286 struct iwm_rx_data data[IWM_RX_RING_COUNT];
287 int cur; 287 int cur;
288}; 288};
289 289
290#define IWM_FLAG_USE_ICT __BIT(0) 290#define IWM_FLAG_USE_ICT __BIT(0)
291#define IWM_FLAG_HW_INITED __BIT(1) 291#define IWM_FLAG_HW_INITED __BIT(1)
292#define IWM_FLAG_STOPPED __BIT(2) 292#define IWM_FLAG_STOPPED __BIT(2)
293#define IWM_FLAG_RFKILL __BIT(3) 293#define IWM_FLAG_RFKILL __BIT(3)
294#define IWM_FLAG_BUSY __BIT(4) 294#define IWM_FLAG_BUSY __BIT(4)
295#define IWM_FLAG_ATTACHED __BIT(5) 295#define IWM_FLAG_ATTACHED __BIT(5)
296#define IWM_FLAG_FW_LOADED __BIT(6) 296#define IWM_FLAG_FW_LOADED __BIT(6)
297 297
298struct iwm_ucode_status { 298struct iwm_ucode_status {
299 uint32_t uc_error_event_table; 299 uint32_t uc_error_event_table;
300 uint32_t uc_log_event_table; 300 uint32_t uc_log_event_table;
301 301
302 int uc_ok; 302 int uc_ok;
303 int uc_intr; 303 int uc_intr;
304}; 304};
305 305
306#define IWM_CMD_RESP_MAX PAGE_SIZE 306#define IWM_CMD_RESP_MAX PAGE_SIZE
307 307
308#define IWM_OTP_LOW_IMAGE_SIZE 2048 308#define IWM_OTP_LOW_IMAGE_SIZE 2048
309 309
310#define IWM_MVM_TE_SESSION_PROTECTION_MAX_TIME_MS 500 310#define IWM_MVM_TE_SESSION_PROTECTION_MAX_TIME_MS 500
311#define IWM_MVM_TE_SESSION_PROTECTION_MIN_TIME_MS 400 311#define IWM_MVM_TE_SESSION_PROTECTION_MIN_TIME_MS 400
312 312
313/* 313/*
314 * Command headers are in iwl-trans.h, which is full of all 314 * Command headers are in iwl-trans.h, which is full of all
315 * kinds of other junk, so we just replicate the structures here. 315 * kinds of other junk, so we just replicate the structures here.
316 * First the software bits: 316 * First the software bits:
317 */ 317 */
318enum IWM_CMD_MODE { 318enum IWM_CMD_MODE {
319 IWM_CMD_SYNC = 0, 319 IWM_CMD_SYNC = 0,
320 IWM_CMD_ASYNC = (1 << 0), 320 IWM_CMD_ASYNC = (1 << 0),
321 IWM_CMD_WANT_SKB = (1 << 1), 321 IWM_CMD_WANT_SKB = (1 << 1),
322 IWM_CMD_SEND_IN_RFKILL = (1 << 2), 322 IWM_CMD_SEND_IN_RFKILL = (1 << 2),
323}; 323};
324enum iwm_hcmd_dataflag { 324enum iwm_hcmd_dataflag {
325 IWM_HCMD_DFL_NOCOPY = (1 << 0), 325 IWM_HCMD_DFL_NOCOPY = (1 << 0),
326 IWM_HCMD_DFL_DUP = (1 << 1), 326 IWM_HCMD_DFL_DUP = (1 << 1),
327}; 327};
328 328
329/* 329/*
330 * iwlwifi/iwl-phy-db 330 * iwlwifi/iwl-phy-db
331 */ 331 */
332 332
333#define IWM_NUM_PAPD_CH_GROUPS 4 333#define IWM_NUM_PAPD_CH_GROUPS 4
334#define IWM_NUM_TXP_CH_GROUPS 9 334#define IWM_NUM_TXP_CH_GROUPS 9
335 335
336struct iwm_phy_db_entry { 336struct iwm_phy_db_entry {
337 uint16_t size; 337 uint16_t size;
338 uint8_t *data; 338 uint8_t *data;
339}; 339};
340 340
341struct iwm_phy_db { 341struct iwm_phy_db {
342 struct iwm_phy_db_entry cfg; 342 struct iwm_phy_db_entry cfg;
343 struct iwm_phy_db_entry calib_nch; 343 struct iwm_phy_db_entry calib_nch;
344 struct iwm_phy_db_entry calib_ch_group_papd[IWM_NUM_PAPD_CH_GROUPS]; 344 struct iwm_phy_db_entry calib_ch_group_papd[IWM_NUM_PAPD_CH_GROUPS];
345 struct iwm_phy_db_entry calib_ch_group_txp[IWM_NUM_TXP_CH_GROUPS]; 345 struct iwm_phy_db_entry calib_ch_group_txp[IWM_NUM_TXP_CH_GROUPS];
346}; 346};
347 347
348struct iwm_int_sta { 348struct iwm_int_sta {
349 uint32_t sta_id; 349 uint32_t sta_id;
350 uint32_t tfd_queue_msk; 350 uint32_t tfd_queue_msk;
351}; 351};
352 352
353struct iwm_mvm_phy_ctxt { 353struct iwm_mvm_phy_ctxt {
354 uint16_t id; 354 uint16_t id;
355 uint16_t color; 355 uint16_t color;
356 uint32_t ref; 356 uint32_t ref;
357 struct ieee80211_channel *channel; 357 struct ieee80211_channel *channel;
358}; 358};
359 359
360struct iwm_bf_data { 360struct iwm_bf_data {
361 int bf_enabled; /* filtering */ 361 int bf_enabled; /* filtering */
362 int ba_enabled; /* abort */ 362 int ba_enabled; /* abort */
363 int ave_beacon_signal; 363 int ave_beacon_signal;
364 int last_cqm_event; 364 int last_cqm_event;
365}; 365};
366 366
367struct iwm_softc { 367struct iwm_softc {
368 device_t sc_dev; 368 device_t sc_dev;
369 struct ethercom sc_ec; 369 struct ethercom sc_ec;
370 struct ieee80211com sc_ic; 370 struct ieee80211com sc_ic;
371 371
372 int (*sc_newstate)(struct ieee80211com *, enum ieee80211_state, int); 372 int (*sc_newstate)(struct ieee80211com *, enum ieee80211_state, int);
373 int sc_newstate_pending; 373 int sc_newstate_pending;
374 374
375 struct ieee80211_amrr sc_amrr; 375 struct ieee80211_amrr sc_amrr;
376 struct callout sc_calib_to; 376 struct callout sc_calib_to;
377 377
378 bus_space_tag_t sc_st; 378 bus_space_tag_t sc_st;
379 bus_space_handle_t sc_sh; 379 bus_space_handle_t sc_sh;
380#ifdef __HAVE_PCI_MSI_MSIX 
381 pci_intr_handle_t *sc_pihp; 380 pci_intr_handle_t *sc_pihp;
382#endif 
383 381
384 bus_size_t sc_sz; 382 bus_size_t sc_sz;
385 bus_dma_tag_t sc_dmat; 383 bus_dma_tag_t sc_dmat;
386 pci_chipset_tag_t sc_pct; 384 pci_chipset_tag_t sc_pct;
387 pcitag_t sc_pcitag; 385 pcitag_t sc_pcitag;
388 pcireg_t sc_pciid; 386 pcireg_t sc_pciid;
389 const void *sc_ih; 387 const void *sc_ih;
390 388
391 /* TX scheduler rings. */ 389 /* TX scheduler rings. */
392 struct iwm_dma_info sched_dma; 390 struct iwm_dma_info sched_dma;
393 uint32_t sched_base; 391 uint32_t sched_base;
394 392
395 /* TX/RX rings. */ 393 /* TX/RX rings. */
396 struct iwm_tx_ring txq[IWM_MVM_MAX_QUEUES]; 394 struct iwm_tx_ring txq[IWM_MVM_MAX_QUEUES];
397 struct iwm_rx_ring rxq; 395 struct iwm_rx_ring rxq;
398 int qfullmsk; 396 int qfullmsk;
399 397
400 int sc_sf_state; 398 int sc_sf_state;
401 399
402 /* ICT table. */ 400 /* ICT table. */
403 struct iwm_dma_info ict_dma; 401 struct iwm_dma_info ict_dma;
404 int ict_cur; 402 int ict_cur;
405 403
406 int sc_hw_rev; 404 int sc_hw_rev;
407 int sc_hw_id; 405 int sc_hw_id;
408 406
409 struct iwm_dma_info kw_dma; 407 struct iwm_dma_info kw_dma;
410 struct iwm_dma_info fw_dma; 408 struct iwm_dma_info fw_dma;
411 409
412 int sc_fw_chunk_done; 410 int sc_fw_chunk_done;
413 int sc_init_complete; 411 int sc_init_complete;
414 412
415 struct iwm_ucode_status sc_uc; 413 struct iwm_ucode_status sc_uc;
416 enum iwm_ucode_type sc_uc_current; 414 enum iwm_ucode_type sc_uc_current;
417 int sc_fwver; 415 int sc_fwver;
418 416
419 int sc_capaflags; 417 int sc_capaflags;
420 int sc_capa_max_probe_len; 418 int sc_capa_max_probe_len;
421 419
422 int sc_intmask; 420 int sc_intmask;
423 int sc_flags; 421 int sc_flags;
424 422
425 /* 423 /*
426 * So why do we need a separate stopped flag and a generation? 424 * So why do we need a separate stopped flag and a generation?
427 * the former protects the device from issueing commands when it's 425 * the former protects the device from issueing commands when it's
428 * stopped (duh). The latter protects against race from a very 426 * stopped (duh). The latter protects against race from a very
429 * fast stop/unstop cycle where threads waiting for responses do 427 * fast stop/unstop cycle where threads waiting for responses do
430 * not have a chance to run in between. Notably: we want to stop 428 * not have a chance to run in between. Notably: we want to stop
431 * the device from interrupt context when it craps out, so we 429 * the device from interrupt context when it craps out, so we
432 * don't have the luxury of waiting for quiescense. 430 * don't have the luxury of waiting for quiescense.
433 */ 431 */
434 int sc_generation; 432 int sc_generation;
435 433
436 int sc_cap_off; /* PCIe caps */ 434 int sc_cap_off; /* PCIe caps */
437 435
438 const char *sc_fwname; 436 const char *sc_fwname;
439 bus_size_t sc_fwdmasegsz; 437 bus_size_t sc_fwdmasegsz;
440 struct iwm_fw_info sc_fw; 438 struct iwm_fw_info sc_fw;
441 int sc_fw_phy_config; 439 int sc_fw_phy_config;
442 struct iwm_tlv_calib_ctrl sc_default_calib[IWM_UCODE_TYPE_MAX]; 440 struct iwm_tlv_calib_ctrl sc_default_calib[IWM_UCODE_TYPE_MAX];
443 441
444 struct iwm_nvm_data sc_nvm; 442 struct iwm_nvm_data sc_nvm;
445 struct iwm_phy_db sc_phy_db; 443 struct iwm_phy_db sc_phy_db;
446 444
447 struct iwm_bf_data sc_bf; 445 struct iwm_bf_data sc_bf;
448 446
449 int sc_tx_timer; 447 int sc_tx_timer;
450 448
451 struct iwm_scan_cmd *sc_scan_cmd; 449 struct iwm_scan_cmd *sc_scan_cmd;
452 size_t sc_scan_cmd_len; 450 size_t sc_scan_cmd_len;
453 int sc_scan_last_antenna; 451 int sc_scan_last_antenna;
454 int sc_scanband; 452 int sc_scanband;
455 453
456 int sc_auth_prot; 454 int sc_auth_prot;
457 455
458 int sc_fixed_ridx; 456 int sc_fixed_ridx;
459 457
460 int sc_staid; 458 int sc_staid;
461 int sc_nodecolor; 459 int sc_nodecolor;
462 460
463 uint8_t sc_cmd_resp[IWM_CMD_RESP_MAX]; 461 uint8_t sc_cmd_resp[IWM_CMD_RESP_MAX];
464 int sc_wantresp; 462 int sc_wantresp;
465 463
466 struct workqueue *sc_nswq, *sc_eswq; 464 struct workqueue *sc_nswq, *sc_eswq;
467 struct work sc_eswk; 465 struct work sc_eswk;
468 466
469 struct iwm_rx_phy_info sc_last_phy_info; 467 struct iwm_rx_phy_info sc_last_phy_info;
470 int sc_ampdu_ref; 468 int sc_ampdu_ref;
471 469
472 struct iwm_int_sta sc_aux_sta; 470 struct iwm_int_sta sc_aux_sta;
473 471
474 /* phy contexts. we only use the first one */ 472 /* phy contexts. we only use the first one */
475 struct iwm_mvm_phy_ctxt sc_phyctxt[IWM_NUM_PHY_CTX]; 473 struct iwm_mvm_phy_ctxt sc_phyctxt[IWM_NUM_PHY_CTX];
476 474
477 struct iwm_notif_statistics sc_stats; 475 struct iwm_notif_statistics sc_stats;
478 int sc_noise; 476 int sc_noise;
479 477
480 int host_interrupt_operation_mode; 478 int host_interrupt_operation_mode;
481 479
482 struct sysctllog *sc_clog; 480 struct sysctllog *sc_clog;
483 481
484 struct bpf_if * sc_drvbpf; 482 struct bpf_if * sc_drvbpf;
485 483
486 union { 484 union {
487 struct iwm_rx_radiotap_header th; 485 struct iwm_rx_radiotap_header th;
488 uint8_t pad[IEEE80211_RADIOTAP_HDRLEN]; 486 uint8_t pad[IEEE80211_RADIOTAP_HDRLEN];
489 } sc_rxtapu; 487 } sc_rxtapu;
490#define sc_rxtap sc_rxtapu.th 488#define sc_rxtap sc_rxtapu.th
491 int sc_rxtap_len; 489 int sc_rxtap_len;
492 490
493 union { 491 union {
494 struct iwm_tx_radiotap_header th; 492 struct iwm_tx_radiotap_header th;
495 uint8_t pad[IEEE80211_RADIOTAP_HDRLEN]; 493 uint8_t pad[IEEE80211_RADIOTAP_HDRLEN];
496 } sc_txtapu; 494 } sc_txtapu;
497#define sc_txtap sc_txtapu.th 495#define sc_txtap sc_txtapu.th
498 int sc_txtap_len; 496 int sc_txtap_len;
499}; 497};
500 498
501struct iwm_node { 499struct iwm_node {
502 struct ieee80211_node in_ni; 500 struct ieee80211_node in_ni;
503 struct iwm_mvm_phy_ctxt *in_phyctxt; 501 struct iwm_mvm_phy_ctxt *in_phyctxt;
504 502
505 uint16_t in_id; 503 uint16_t in_id;
506 uint16_t in_color; 504 uint16_t in_color;
507 int in_tsfid; 505 int in_tsfid;
508 506
509 /* status "bits" */ 507 /* status "bits" */
510 int in_assoc; 508 int in_assoc;
511 509
512 struct iwm_lq_cmd in_lq; 510 struct iwm_lq_cmd in_lq;
513 struct ieee80211_amrr_node in_amn; 511 struct ieee80211_amrr_node in_amn;
514 512
515 uint8_t in_ridx[IEEE80211_RATE_MAXSIZE]; 513 uint8_t in_ridx[IEEE80211_RATE_MAXSIZE];
516}; 514};
517#define IWM_STATION_ID 0 515#define IWM_STATION_ID 0
518 516
519#define IWM_ICT_SIZE 4096 517#define IWM_ICT_SIZE 4096
520#define IWM_ICT_COUNT (IWM_ICT_SIZE / sizeof (uint32_t)) 518#define IWM_ICT_COUNT (IWM_ICT_SIZE / sizeof (uint32_t))
521#define IWM_ICT_PADDR_SHIFT 12 519#define IWM_ICT_PADDR_SHIFT 12
cvs diff -r1.1 -r1.2 src/sys/dev/pci/if_rtwn.c (switch to unified diff)

--- src/sys/dev/pci/if_rtwn.c 2015/08/27 14:04:08 1.1
+++ src/sys/dev/pci/if_rtwn.c 2015/11/06 14:22:17 1.2
@@ -1,1440 +1,1426 @@ @@ -1,1440 +1,1426 @@
1/* $NetBSD: if_rtwn.c,v 1.1 2015/08/27 14:04:08 nonaka Exp $ */ 1/* $NetBSD: if_rtwn.c,v 1.2 2015/11/06 14:22:17 nonaka Exp $ */
2/* $OpenBSD: if_rtwn.c,v 1.5 2015/06/14 08:02:47 stsp Exp $ */ 2/* $OpenBSD: if_rtwn.c,v 1.5 2015/06/14 08:02:47 stsp Exp $ */
3#define IEEE80211_NO_HT 3#define IEEE80211_NO_HT
4/*- 4/*-
5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
6 * Copyright (c) 2015 Stefan Sperling <stsp@openbsd.org> 6 * Copyright (c) 2015 Stefan Sperling <stsp@openbsd.org>
7 * 7 *
8 * Permission to use, copy, modify, and distribute this software for any 8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above 9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies. 10 * copyright notice and this permission notice appear in all copies.
11 * 11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 */ 19 */
20 20
21/* 21/*
22 * Driver for Realtek RTL8188CE 22 * Driver for Realtek RTL8188CE
23 */ 23 */
24 24
25#include <sys/cdefs.h> 25#include <sys/cdefs.h>
26__KERNEL_RCSID(0, "$NetBSD: if_rtwn.c,v 1.1 2015/08/27 14:04:08 nonaka Exp $"); 26__KERNEL_RCSID(0, "$NetBSD: if_rtwn.c,v 1.2 2015/11/06 14:22:17 nonaka Exp $");
27 27
28#include <sys/param.h> 28#include <sys/param.h>
29#include <sys/sockio.h> 29#include <sys/sockio.h>
30#include <sys/mbuf.h> 30#include <sys/mbuf.h>
31#include <sys/kernel.h> 31#include <sys/kernel.h>
32#include <sys/socket.h> 32#include <sys/socket.h>
33#include <sys/systm.h> 33#include <sys/systm.h>
34#include <sys/callout.h> 34#include <sys/callout.h>
35#include <sys/conf.h> 35#include <sys/conf.h>
36#include <sys/device.h> 36#include <sys/device.h>
37#include <sys/endian.h> 37#include <sys/endian.h>
38#include <sys/mutex.h> 38#include <sys/mutex.h>
39 39
40#include <sys/bus.h> 40#include <sys/bus.h>
41#include <sys/intr.h> 41#include <sys/intr.h>
42 42
43#include <net/bpf.h> 43#include <net/bpf.h>
44#include <net/if.h> 44#include <net/if.h>
45#include <net/if_arp.h> 45#include <net/if_arp.h>
46#include <net/if_dl.h> 46#include <net/if_dl.h>
47#include <net/if_ether.h> 47#include <net/if_ether.h>
48#include <net/if_media.h> 48#include <net/if_media.h>
49#include <net/if_types.h> 49#include <net/if_types.h>
50 50
51#include <netinet/in.h> 51#include <netinet/in.h>
52 52
53#include <net80211/ieee80211_var.h> 53#include <net80211/ieee80211_var.h>
54#include <net80211/ieee80211_radiotap.h> 54#include <net80211/ieee80211_radiotap.h>
55 55
56#include <dev/firmload.h> 56#include <dev/firmload.h>
57 57
58#include <dev/pci/pcireg.h> 58#include <dev/pci/pcireg.h>
59#include <dev/pci/pcivar.h> 59#include <dev/pci/pcivar.h>
60#include <dev/pci/pcidevs.h> 60#include <dev/pci/pcidevs.h>
61 61
62#include <dev/pci/if_rtwnreg.h> 62#include <dev/pci/if_rtwnreg.h>
63 63
64#ifdef RTWN_DEBUG 64#ifdef RTWN_DEBUG
65#define DPRINTF(x) do { if (rtwn_debug) printf x; } while (0) 65#define DPRINTF(x) do { if (rtwn_debug) printf x; } while (0)
66#define DPRINTFN(n, x) do { if (rtwn_debug >= (n)) printf x; } while (0) 66#define DPRINTFN(n, x) do { if (rtwn_debug >= (n)) printf x; } while (0)
67int rtwn_debug = 0; 67int rtwn_debug = 0;
68#else 68#else
69#define DPRINTF(x) 69#define DPRINTF(x)
70#define DPRINTFN(n, x) 70#define DPRINTFN(n, x)
71#endif 71#endif
72 72
73/* 73/*
74 * PCI configuration space registers. 74 * PCI configuration space registers.
75 */ 75 */
76#define RTWN_PCI_IOBA 0x10 /* i/o mapped base */ 76#define RTWN_PCI_IOBA 0x10 /* i/o mapped base */
77#define RTWN_PCI_MMBA 0x18 /* memory mapped base */ 77#define RTWN_PCI_MMBA 0x18 /* memory mapped base */
78 78
79#define RTWN_INT_ENABLE_TX \ 79#define RTWN_INT_ENABLE_TX \
80 (R92C_IMR_VODOK | R92C_IMR_VIDOK | R92C_IMR_BEDOK | \ 80 (R92C_IMR_VODOK | R92C_IMR_VIDOK | R92C_IMR_BEDOK | \
81 R92C_IMR_BKDOK | R92C_IMR_MGNTDOK | \ 81 R92C_IMR_BKDOK | R92C_IMR_MGNTDOK | \
82 R92C_IMR_HIGHDOK | R92C_IMR_BDOK) 82 R92C_IMR_HIGHDOK | R92C_IMR_BDOK)
83#define RTWN_INT_ENABLE_RX \ 83#define RTWN_INT_ENABLE_RX \
84 (R92C_IMR_ROK | R92C_IMR_RDU | R92C_IMR_RXFOVW) 84 (R92C_IMR_ROK | R92C_IMR_RDU | R92C_IMR_RXFOVW)
85#define RTWN_INT_ENABLE (RTWN_INT_ENABLE_TX | RTWN_INT_ENABLE_RX) 85#define RTWN_INT_ENABLE (RTWN_INT_ENABLE_TX | RTWN_INT_ENABLE_RX)
86 86
87static const struct rtwn_device { 87static const struct rtwn_device {
88 pci_vendor_id_t rd_vendor; 88 pci_vendor_id_t rd_vendor;
89 pci_product_id_t rd_product; 89 pci_product_id_t rd_product;
90} rtwn_devices[] = { 90} rtwn_devices[] = {
91 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8188CE }, 91 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8188CE },
92 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8192CE } 92 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8192CE }
93}; 93};
94 94
95static int rtwn_match(device_t, cfdata_t, void *); 95static int rtwn_match(device_t, cfdata_t, void *);
96static void rtwn_attach(device_t, device_t, void *); 96static void rtwn_attach(device_t, device_t, void *);
97static int rtwn_detach(device_t, int); 97static int rtwn_detach(device_t, int);
98static int rtwn_activate(device_t, enum devact); 98static int rtwn_activate(device_t, enum devact);
99 99
100CFATTACH_DECL_NEW(rtwn, sizeof(struct rtwn_softc), rtwn_match, 100CFATTACH_DECL_NEW(rtwn, sizeof(struct rtwn_softc), rtwn_match,
101 rtwn_attach, rtwn_detach, rtwn_activate); 101 rtwn_attach, rtwn_detach, rtwn_activate);
102 102
103static int rtwn_alloc_rx_list(struct rtwn_softc *); 103static int rtwn_alloc_rx_list(struct rtwn_softc *);
104static void rtwn_reset_rx_list(struct rtwn_softc *); 104static void rtwn_reset_rx_list(struct rtwn_softc *);
105static void rtwn_free_rx_list(struct rtwn_softc *); 105static void rtwn_free_rx_list(struct rtwn_softc *);
106static void rtwn_setup_rx_desc(struct rtwn_softc *, struct r92c_rx_desc *, 106static void rtwn_setup_rx_desc(struct rtwn_softc *, struct r92c_rx_desc *,
107 bus_addr_t, size_t, int); 107 bus_addr_t, size_t, int);
108static int rtwn_alloc_tx_list(struct rtwn_softc *, int); 108static int rtwn_alloc_tx_list(struct rtwn_softc *, int);
109static void rtwn_reset_tx_list(struct rtwn_softc *, int); 109static void rtwn_reset_tx_list(struct rtwn_softc *, int);
110static void rtwn_free_tx_list(struct rtwn_softc *, int); 110static void rtwn_free_tx_list(struct rtwn_softc *, int);
111static void rtwn_write_1(struct rtwn_softc *, uint16_t, uint8_t); 111static void rtwn_write_1(struct rtwn_softc *, uint16_t, uint8_t);
112static void rtwn_write_2(struct rtwn_softc *, uint16_t, uint16_t); 112static void rtwn_write_2(struct rtwn_softc *, uint16_t, uint16_t);
113static void rtwn_write_4(struct rtwn_softc *, uint16_t, uint32_t); 113static void rtwn_write_4(struct rtwn_softc *, uint16_t, uint32_t);
114static uint8_t rtwn_read_1(struct rtwn_softc *, uint16_t); 114static uint8_t rtwn_read_1(struct rtwn_softc *, uint16_t);
115static uint16_t rtwn_read_2(struct rtwn_softc *, uint16_t); 115static uint16_t rtwn_read_2(struct rtwn_softc *, uint16_t);
116static uint32_t rtwn_read_4(struct rtwn_softc *, uint16_t); 116static uint32_t rtwn_read_4(struct rtwn_softc *, uint16_t);
117static int rtwn_fw_cmd(struct rtwn_softc *, uint8_t, const void *, int); 117static int rtwn_fw_cmd(struct rtwn_softc *, uint8_t, const void *, int);
118static void rtwn_rf_write(struct rtwn_softc *, int, uint8_t, uint32_t); 118static void rtwn_rf_write(struct rtwn_softc *, int, uint8_t, uint32_t);
119static uint32_t rtwn_rf_read(struct rtwn_softc *, int, uint8_t); 119static uint32_t rtwn_rf_read(struct rtwn_softc *, int, uint8_t);
120static int rtwn_llt_write(struct rtwn_softc *, uint32_t, uint32_t); 120static int rtwn_llt_write(struct rtwn_softc *, uint32_t, uint32_t);
121static uint8_t rtwn_efuse_read_1(struct rtwn_softc *, uint16_t); 121static uint8_t rtwn_efuse_read_1(struct rtwn_softc *, uint16_t);
122static void rtwn_efuse_read(struct rtwn_softc *); 122static void rtwn_efuse_read(struct rtwn_softc *);
123static int rtwn_read_chipid(struct rtwn_softc *); 123static int rtwn_read_chipid(struct rtwn_softc *);
124static void rtwn_efuse_switch_power(struct rtwn_softc *); 124static void rtwn_efuse_switch_power(struct rtwn_softc *);
125static void rtwn_read_rom(struct rtwn_softc *); 125static void rtwn_read_rom(struct rtwn_softc *);
126static int rtwn_media_change(struct ifnet *); 126static int rtwn_media_change(struct ifnet *);
127static int rtwn_ra_init(struct rtwn_softc *); 127static int rtwn_ra_init(struct rtwn_softc *);
128static int rtwn_get_nettype(struct rtwn_softc *); 128static int rtwn_get_nettype(struct rtwn_softc *);
129static void rtwn_set_nettype0_msr(struct rtwn_softc *, uint8_t); 129static void rtwn_set_nettype0_msr(struct rtwn_softc *, uint8_t);
130static void rtwn_tsf_sync_enable(struct rtwn_softc *); 130static void rtwn_tsf_sync_enable(struct rtwn_softc *);
131static void rtwn_set_led(struct rtwn_softc *, int, int); 131static void rtwn_set_led(struct rtwn_softc *, int, int);
132static void rtwn_calib_to(void *); 132static void rtwn_calib_to(void *);
133static void rtwn_next_scan(void *); 133static void rtwn_next_scan(void *);
134static void rtwn_newassoc(struct ieee80211_node *, int); 134static void rtwn_newassoc(struct ieee80211_node *, int);
135static int rtwn_reset(struct ifnet *); 135static int rtwn_reset(struct ifnet *);
136static int rtwn_newstate(struct ieee80211com *, enum ieee80211_state, 136static int rtwn_newstate(struct ieee80211com *, enum ieee80211_state,
137 int); 137 int);
138static int rtwn_wme_update(struct ieee80211com *); 138static int rtwn_wme_update(struct ieee80211com *);
139static void rtwn_update_avgrssi(struct rtwn_softc *, int, int8_t); 139static void rtwn_update_avgrssi(struct rtwn_softc *, int, int8_t);
140static int8_t rtwn_get_rssi(struct rtwn_softc *, int, void *); 140static int8_t rtwn_get_rssi(struct rtwn_softc *, int, void *);
141static void rtwn_rx_frame(struct rtwn_softc *, struct r92c_rx_desc *, 141static void rtwn_rx_frame(struct rtwn_softc *, struct r92c_rx_desc *,
142 struct rtwn_rx_data *, int); 142 struct rtwn_rx_data *, int);
143static int rtwn_tx(struct rtwn_softc *, struct mbuf *, 143static int rtwn_tx(struct rtwn_softc *, struct mbuf *,
144 struct ieee80211_node *); 144 struct ieee80211_node *);
145static void rtwn_tx_done(struct rtwn_softc *, int); 145static void rtwn_tx_done(struct rtwn_softc *, int);
146static void rtwn_start(struct ifnet *); 146static void rtwn_start(struct ifnet *);
147static void rtwn_watchdog(struct ifnet *); 147static void rtwn_watchdog(struct ifnet *);
148static int rtwn_ioctl(struct ifnet *, u_long, void *); 148static int rtwn_ioctl(struct ifnet *, u_long, void *);
149static int rtwn_power_on(struct rtwn_softc *); 149static int rtwn_power_on(struct rtwn_softc *);
150static int rtwn_llt_init(struct rtwn_softc *); 150static int rtwn_llt_init(struct rtwn_softc *);
151static void rtwn_fw_reset(struct rtwn_softc *); 151static void rtwn_fw_reset(struct rtwn_softc *);
152static int rtwn_fw_loadpage(struct rtwn_softc *, int, uint8_t *, int); 152static int rtwn_fw_loadpage(struct rtwn_softc *, int, uint8_t *, int);
153static int rtwn_load_firmware(struct rtwn_softc *); 153static int rtwn_load_firmware(struct rtwn_softc *);
154static int rtwn_dma_init(struct rtwn_softc *); 154static int rtwn_dma_init(struct rtwn_softc *);
155static void rtwn_mac_init(struct rtwn_softc *); 155static void rtwn_mac_init(struct rtwn_softc *);
156static void rtwn_bb_init(struct rtwn_softc *); 156static void rtwn_bb_init(struct rtwn_softc *);
157static void rtwn_rf_init(struct rtwn_softc *); 157static void rtwn_rf_init(struct rtwn_softc *);
158static void rtwn_cam_init(struct rtwn_softc *); 158static void rtwn_cam_init(struct rtwn_softc *);
159static void rtwn_pa_bias_init(struct rtwn_softc *); 159static void rtwn_pa_bias_init(struct rtwn_softc *);
160static void rtwn_rxfilter_init(struct rtwn_softc *); 160static void rtwn_rxfilter_init(struct rtwn_softc *);
161static void rtwn_edca_init(struct rtwn_softc *); 161static void rtwn_edca_init(struct rtwn_softc *);
162static void rtwn_write_txpower(struct rtwn_softc *, int, uint16_t[]); 162static void rtwn_write_txpower(struct rtwn_softc *, int, uint16_t[]);
163static void rtwn_get_txpower(struct rtwn_softc *, int, 163static void rtwn_get_txpower(struct rtwn_softc *, int,
164 struct ieee80211_channel *, struct ieee80211_channel *, 164 struct ieee80211_channel *, struct ieee80211_channel *,
165 uint16_t[]); 165 uint16_t[]);
166static void rtwn_set_txpower(struct rtwn_softc *, 166static void rtwn_set_txpower(struct rtwn_softc *,
167 struct ieee80211_channel *, struct ieee80211_channel *); 167 struct ieee80211_channel *, struct ieee80211_channel *);
168static void rtwn_set_chan(struct rtwn_softc *, 168static void rtwn_set_chan(struct rtwn_softc *,
169 struct ieee80211_channel *, struct ieee80211_channel *); 169 struct ieee80211_channel *, struct ieee80211_channel *);
170static void rtwn_iq_calib(struct rtwn_softc *); 170static void rtwn_iq_calib(struct rtwn_softc *);
171static void rtwn_lc_calib(struct rtwn_softc *); 171static void rtwn_lc_calib(struct rtwn_softc *);
172static void rtwn_temp_calib(struct rtwn_softc *); 172static void rtwn_temp_calib(struct rtwn_softc *);
173static int rtwn_init(struct ifnet *); 173static int rtwn_init(struct ifnet *);
174static void rtwn_init_task(void *); 174static void rtwn_init_task(void *);
175static void rtwn_stop(struct ifnet *, int); 175static void rtwn_stop(struct ifnet *, int);
176static int rtwn_intr(void *); 176static int rtwn_intr(void *);
177 177
178/* Aliases. */ 178/* Aliases. */
179#define rtwn_bb_write rtwn_write_4 179#define rtwn_bb_write rtwn_write_4
180#define rtwn_bb_read rtwn_read_4 180#define rtwn_bb_read rtwn_read_4
181 181
182static const struct rtwn_device * 182static const struct rtwn_device *
183rtwn_lookup(const struct pci_attach_args *pa) 183rtwn_lookup(const struct pci_attach_args *pa)
184{ 184{
185 const struct rtwn_device *rd; 185 const struct rtwn_device *rd;
186 int i; 186 int i;
187 187
188 for (i = 0; i < __arraycount(rtwn_devices); i++) { 188 for (i = 0; i < __arraycount(rtwn_devices); i++) {
189 rd = &rtwn_devices[i]; 189 rd = &rtwn_devices[i];
190 if (PCI_VENDOR(pa->pa_id) == rd->rd_vendor && 190 if (PCI_VENDOR(pa->pa_id) == rd->rd_vendor &&
191 PCI_PRODUCT(pa->pa_id) == rd->rd_product) 191 PCI_PRODUCT(pa->pa_id) == rd->rd_product)
192 return rd; 192 return rd;
193 } 193 }
194 return NULL; 194 return NULL;
195} 195}
196 196
197static int 197static int
198rtwn_match(device_t parent, cfdata_t match, void *aux) 198rtwn_match(device_t parent, cfdata_t match, void *aux)
199{ 199{
200 struct pci_attach_args *pa = aux; 200 struct pci_attach_args *pa = aux;
201 201
202 if (rtwn_lookup(pa) != NULL) 202 if (rtwn_lookup(pa) != NULL)
203 return 1; 203 return 1;
204 return 0; 204 return 0;
205} 205}
206 206
207static void 207static void
208rtwn_attach(device_t parent, device_t self, void *aux) 208rtwn_attach(device_t parent, device_t self, void *aux)
209{ 209{
210 struct rtwn_softc *sc = device_private(self); 210 struct rtwn_softc *sc = device_private(self);
211 struct pci_attach_args *pa = aux; 211 struct pci_attach_args *pa = aux;
212 struct ieee80211com *ic = &sc->sc_ic; 212 struct ieee80211com *ic = &sc->sc_ic;
213 struct ifnet *ifp = GET_IFP(sc); 213 struct ifnet *ifp = GET_IFP(sc);
214 int i, error; 214 int i, error;
215 pcireg_t memtype; 215 pcireg_t memtype;
216#ifndef __HAVE_PCI_MSI_MSIX 
217 pci_intr_handle_t ih; 
218#endif 
219 const char *intrstr; 216 const char *intrstr;
220 char intrbuf[PCI_INTRSTR_LEN]; 217 char intrbuf[PCI_INTRSTR_LEN];
221 218
222 sc->sc_dev = self; 219 sc->sc_dev = self;
223 sc->sc_dmat = pa->pa_dmat; 220 sc->sc_dmat = pa->pa_dmat;
224 sc->sc_pc = pa->pa_pc; 221 sc->sc_pc = pa->pa_pc;
225 sc->sc_tag = pa->pa_tag; 222 sc->sc_tag = pa->pa_tag;
226 223
227 pci_aprint_devinfo(pa, NULL); 224 pci_aprint_devinfo(pa, NULL);
228 225
229 callout_init(&sc->scan_to, 0); 226 callout_init(&sc->scan_to, 0);
230 callout_setfunc(&sc->scan_to, rtwn_next_scan, sc); 227 callout_setfunc(&sc->scan_to, rtwn_next_scan, sc);
231 callout_init(&sc->calib_to, 0); 228 callout_init(&sc->calib_to, 0);
232 callout_setfunc(&sc->calib_to, rtwn_calib_to, sc); 229 callout_setfunc(&sc->calib_to, rtwn_calib_to, sc);
233 230
234 sc->init_task = softint_establish(SOFTINT_NET, rtwn_init_task, sc); 231 sc->init_task = softint_establish(SOFTINT_NET, rtwn_init_task, sc);
235 232
236 /* Power up the device */ 233 /* Power up the device */
237 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 234 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0);
238 235
239 /* Map control/status registers. */ 236 /* Map control/status registers. */
240 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, RTWN_PCI_MMBA); 237 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, RTWN_PCI_MMBA);
241 error = pci_mapreg_map(pa, RTWN_PCI_MMBA, memtype, 0, &sc->sc_st, 238 error = pci_mapreg_map(pa, RTWN_PCI_MMBA, memtype, 0, &sc->sc_st,
242 &sc->sc_sh, NULL, &sc->sc_mapsize); 239 &sc->sc_sh, NULL, &sc->sc_mapsize);
243 if (error != 0) { 240 if (error != 0) {
244 aprint_error_dev(self, "can't map mem space\n"); 241 aprint_error_dev(self, "can't map mem space\n");
245 return; 242 return;
246 } 243 }
247 244
248 /* Install interrupt handler. */ 245 /* Install interrupt handler. */
249#ifdef __HAVE_PCI_MSI_MSIX 
250 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0)) { 246 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0)) {
251 aprint_error_dev(self, "can't map interrupt\n"); 247 aprint_error_dev(self, "can't map interrupt\n");
252 return; 248 return;
253 } 249 }
254 intrstr = pci_intr_string(sc->sc_pc, sc->sc_pihp[0], intrbuf, 250 intrstr = pci_intr_string(sc->sc_pc, sc->sc_pihp[0], intrbuf,
255 sizeof(intrbuf)); 251 sizeof(intrbuf));
256 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->sc_pihp[0], IPL_NET, 252 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->sc_pihp[0], IPL_NET,
257 rtwn_intr, sc); 253 rtwn_intr, sc);
258#else /* !__HAVE_PCI_MSI_MSIX */ 
259 if (pci_intr_map(pa, &ih)) { 
260 aprint_error_dev(self, "can't map interrupt\n"); 
261 return; 
262 } 
263 intrstr = pci_intr_string(sc->sc_pc, ih, intrbuf, sizeof(intrbuf)); 
264 sc->sc_ih = pci_intr_establish(sc->sc_pc, ih, IPL_NET, rtwn_intr, sc); 
265#endif /* __HAVE_PCI_MSI_MSIX */ 
266 if (sc->sc_ih == NULL) { 254 if (sc->sc_ih == NULL) {
267 aprint_error_dev(self, "can't establish interrupt"); 255 aprint_error_dev(self, "can't establish interrupt");
268 if (intrstr != NULL) 256 if (intrstr != NULL)
269 aprint_error(" at %s", intrstr); 257 aprint_error(" at %s", intrstr);
270 aprint_error("\n"); 258 aprint_error("\n");
271 return; 259 return;
272 } 260 }
273 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 261 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
274 262
275 error = rtwn_read_chipid(sc); 263 error = rtwn_read_chipid(sc);
276 if (error != 0) { 264 if (error != 0) {
277 aprint_error_dev(self, "unsupported test or unknown chip\n"); 265 aprint_error_dev(self, "unsupported test or unknown chip\n");
278 return; 266 return;
279 } 267 }
280 268
281 /* Disable PCIe Active State Power Management (ASPM). */ 269 /* Disable PCIe Active State Power Management (ASPM). */
282 if (pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_PCIEXPRESS, 270 if (pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_PCIEXPRESS,
283 &sc->sc_cap_off, NULL)) { 271 &sc->sc_cap_off, NULL)) {
284 uint32_t lcsr = pci_conf_read(sc->sc_pc, sc->sc_tag, 272 uint32_t lcsr = pci_conf_read(sc->sc_pc, sc->sc_tag,
285 sc->sc_cap_off + PCIE_LCSR); 273 sc->sc_cap_off + PCIE_LCSR);
286 lcsr &= ~(PCIE_LCSR_ASPM_L0S | PCIE_LCSR_ASPM_L1); 274 lcsr &= ~(PCIE_LCSR_ASPM_L0S | PCIE_LCSR_ASPM_L1);
287 pci_conf_write(sc->sc_pc, sc->sc_tag, 275 pci_conf_write(sc->sc_pc, sc->sc_tag,
288 sc->sc_cap_off + PCIE_LCSR, lcsr); 276 sc->sc_cap_off + PCIE_LCSR, lcsr);
289 } 277 }
290 278
291 /* Allocate Tx/Rx buffers. */ 279 /* Allocate Tx/Rx buffers. */
292 error = rtwn_alloc_rx_list(sc); 280 error = rtwn_alloc_rx_list(sc);
293 if (error != 0) { 281 if (error != 0) {
294 aprint_error_dev(self, "could not allocate Rx buffers\n"); 282 aprint_error_dev(self, "could not allocate Rx buffers\n");
295 return; 283 return;
296 } 284 }
297 for (i = 0; i < RTWN_NTXQUEUES; i++) { 285 for (i = 0; i < RTWN_NTXQUEUES; i++) {
298 error = rtwn_alloc_tx_list(sc, i); 286 error = rtwn_alloc_tx_list(sc, i);
299 if (error != 0) { 287 if (error != 0) {
300 aprint_error_dev(self, 288 aprint_error_dev(self,
301 "could not allocate Tx buffers\n"); 289 "could not allocate Tx buffers\n");
302 return; 290 return;
303 } 291 }
304 } 292 }
305 293
306 /* Determine number of Tx/Rx chains. */ 294 /* Determine number of Tx/Rx chains. */
307 if (sc->chip & RTWN_CHIP_92C) { 295 if (sc->chip & RTWN_CHIP_92C) {
308 sc->ntxchains = (sc->chip & RTWN_CHIP_92C_1T2R) ? 1 : 2; 296 sc->ntxchains = (sc->chip & RTWN_CHIP_92C_1T2R) ? 1 : 2;
309 sc->nrxchains = 2; 297 sc->nrxchains = 2;
310 } else { 298 } else {
311 sc->ntxchains = 1; 299 sc->ntxchains = 1;
312 sc->nrxchains = 1; 300 sc->nrxchains = 1;
313 } 301 }
314 rtwn_read_rom(sc); 302 rtwn_read_rom(sc);
315 303
316 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %dT%dR, address %s\n", 304 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %dT%dR, address %s\n",
317 (sc->chip & RTWN_CHIP_92C) ? "8192CE" : "8188CE", 305 (sc->chip & RTWN_CHIP_92C) ? "8192CE" : "8188CE",
318 sc->ntxchains, sc->nrxchains, ether_sprintf(ic->ic_myaddr)); 306 sc->ntxchains, sc->nrxchains, ether_sprintf(ic->ic_myaddr));
319 307
320 /* 308 /*
321 * Setup the 802.11 device. 309 * Setup the 802.11 device.
322 */ 310 */
323 ic->ic_ifp = ifp; 311 ic->ic_ifp = ifp;
324 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 312 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */
325 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 313 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */
326 ic->ic_state = IEEE80211_S_INIT; 314 ic->ic_state = IEEE80211_S_INIT;
327 315
328 /* Set device capabilities. */ 316 /* Set device capabilities. */
329 ic->ic_caps = 317 ic->ic_caps =
330 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 318 IEEE80211_C_MONITOR | /* Monitor mode supported. */
331 IEEE80211_C_IBSS | /* IBSS mode supported */ 319 IEEE80211_C_IBSS | /* IBSS mode supported */
332 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 320 IEEE80211_C_HOSTAP | /* HostAp mode supported */
333 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 321 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */
334 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 322 IEEE80211_C_SHSLOT | /* Short slot time supported. */
335 IEEE80211_C_WME | /* 802.11e */ 323 IEEE80211_C_WME | /* 802.11e */
336 IEEE80211_C_WPA; /* WPA/RSN. */ 324 IEEE80211_C_WPA; /* WPA/RSN. */
337 325
338#ifndef IEEE80211_NO_HT 326#ifndef IEEE80211_NO_HT
339 /* Set HT capabilities. */ 327 /* Set HT capabilities. */
340 ic->ic_htcaps = 328 ic->ic_htcaps =
341 IEEE80211_HTCAP_CBW20_40 | 329 IEEE80211_HTCAP_CBW20_40 |
342 IEEE80211_HTCAP_DSSSCCK40; 330 IEEE80211_HTCAP_DSSSCCK40;
343 /* Set supported HT rates. */ 331 /* Set supported HT rates. */
344 for (i = 0; i < sc->nrxchains; i++) 332 for (i = 0; i < sc->nrxchains; i++)
345 ic->ic_sup_mcs[i] = 0xff; 333 ic->ic_sup_mcs[i] = 0xff;
346#endif 334#endif
347 335
348 /* Set supported .11b and .11g rates. */ 336 /* Set supported .11b and .11g rates. */
349 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 337 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b;
350 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 338 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g;
351 339
352 /* Set supported .11b and .11g channels (1 through 14). */ 340 /* Set supported .11b and .11g channels (1 through 14). */
353 for (i = 1; i <= 14; i++) { 341 for (i = 1; i <= 14; i++) {
354 ic->ic_channels[i].ic_freq = 342 ic->ic_channels[i].ic_freq =
355 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 343 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
356 ic->ic_channels[i].ic_flags = 344 ic->ic_channels[i].ic_flags =
357 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 345 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM |
358 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 346 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ;
359 } 347 }
360 348
361 ifp->if_softc = sc; 349 ifp->if_softc = sc;
362 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 350 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
363 ifp->if_init = rtwn_init; 351 ifp->if_init = rtwn_init;
364 ifp->if_ioctl = rtwn_ioctl; 352 ifp->if_ioctl = rtwn_ioctl;
365 ifp->if_start = rtwn_start; 353 ifp->if_start = rtwn_start;
366 ifp->if_watchdog = rtwn_watchdog; 354 ifp->if_watchdog = rtwn_watchdog;
367 IFQ_SET_READY(&ifp->if_snd); 355 IFQ_SET_READY(&ifp->if_snd);
368 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 356 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
369 357
370 if_initialize(ifp); 358 if_initialize(ifp);
371 ieee80211_ifattach(ic); 359 ieee80211_ifattach(ic);
372 if_register(ifp); 360 if_register(ifp);
373 361
374 /* override default methods */ 362 /* override default methods */
375 ic->ic_newassoc = rtwn_newassoc; 363 ic->ic_newassoc = rtwn_newassoc;
376 ic->ic_reset = rtwn_reset; 364 ic->ic_reset = rtwn_reset;
377 ic->ic_wme.wme_update = rtwn_wme_update; 365 ic->ic_wme.wme_update = rtwn_wme_update;
378 366
379 /* Override state transition machine. */ 367 /* Override state transition machine. */
380 sc->sc_newstate = ic->ic_newstate; 368 sc->sc_newstate = ic->ic_newstate;
381 ic->ic_newstate = rtwn_newstate; 369 ic->ic_newstate = rtwn_newstate;
382 ieee80211_media_init(ic, rtwn_media_change, ieee80211_media_status); 370 ieee80211_media_init(ic, rtwn_media_change, ieee80211_media_status);
383 371
384 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 372 bpf_attach2(ifp, DLT_IEEE802_11_RADIO,
385 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 373 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN,
386 &sc->sc_drvbpf); 374 &sc->sc_drvbpf);
387 375
388 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 376 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu);
389 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 377 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len);
390 sc->sc_rxtap.wr_ihdr.it_present = htole32(RTWN_RX_RADIOTAP_PRESENT); 378 sc->sc_rxtap.wr_ihdr.it_present = htole32(RTWN_RX_RADIOTAP_PRESENT);
391 379
392 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 380 sc->sc_txtap_len = sizeof(sc->sc_txtapu);
393 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 381 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len);
394 sc->sc_txtap.wt_ihdr.it_present = htole32(RTWN_TX_RADIOTAP_PRESENT); 382 sc->sc_txtap.wt_ihdr.it_present = htole32(RTWN_TX_RADIOTAP_PRESENT);
395 383
396 ieee80211_announce(ic); 384 ieee80211_announce(ic);
397 385
398 if (!pmf_device_register(self, NULL, NULL)) 386 if (!pmf_device_register(self, NULL, NULL))
399 aprint_error_dev(self, "couldn't establish power handler\n"); 387 aprint_error_dev(self, "couldn't establish power handler\n");
400} 388}
401 389
402static int 390static int
403rtwn_detach(device_t self, int flags) 391rtwn_detach(device_t self, int flags)
404{ 392{
405 struct rtwn_softc *sc = device_private(self); 393 struct rtwn_softc *sc = device_private(self);
406 struct ieee80211com *ic = &sc->sc_ic; 394 struct ieee80211com *ic = &sc->sc_ic;
407 struct ifnet *ifp = GET_IFP(sc); 395 struct ifnet *ifp = GET_IFP(sc);
408 int s, i; 396 int s, i;
409 397
410 callout_stop(&sc->scan_to); 398 callout_stop(&sc->scan_to);
411 callout_stop(&sc->calib_to); 399 callout_stop(&sc->calib_to);
412 400
413 s = splnet(); 401 s = splnet();
414 402
415 if (ifp->if_softc != NULL) { 403 if (ifp->if_softc != NULL) {
416 rtwn_stop(ifp, 0); 404 rtwn_stop(ifp, 0);
417 405
418 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 406 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
419 bpf_detach(ifp); 407 bpf_detach(ifp);
420 ieee80211_ifdetach(ic); 408 ieee80211_ifdetach(ic);
421 if_detach(ifp); 409 if_detach(ifp);
422 } 410 }
423 411
424 /* Free Tx/Rx buffers. */ 412 /* Free Tx/Rx buffers. */
425 for (i = 0; i < RTWN_NTXQUEUES; i++) 413 for (i = 0; i < RTWN_NTXQUEUES; i++)
426 rtwn_free_tx_list(sc, i); 414 rtwn_free_tx_list(sc, i);
427 rtwn_free_rx_list(sc); 415 rtwn_free_rx_list(sc);
428 416
429 splx(s); 417 splx(s);
430 418
431 callout_destroy(&sc->scan_to); 419 callout_destroy(&sc->scan_to);
432 callout_destroy(&sc->calib_to); 420 callout_destroy(&sc->calib_to);
433 421
434 if (sc->init_task != NULL) 422 if (sc->init_task != NULL)
435 softint_disestablish(sc->init_task); 423 softint_disestablish(sc->init_task);
436 424
437 if (sc->sc_ih != NULL) { 425 if (sc->sc_ih != NULL) {
438 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 426 pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
439#ifdef __HAVE_PCI_MSI_MSIX 
440 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 427 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1);
441#endif 
442 } 428 }
443 429
444 pmf_device_deregister(self); 430 pmf_device_deregister(self);
445 431
446 return 0; 432 return 0;
447} 433}
448 434
449static int 435static int
450rtwn_activate(device_t self, enum devact act) 436rtwn_activate(device_t self, enum devact act)
451{ 437{
452 struct rtwn_softc *sc = device_private(self); 438 struct rtwn_softc *sc = device_private(self);
453 struct ifnet *ifp = GET_IFP(sc); 439 struct ifnet *ifp = GET_IFP(sc);
454 440
455 switch (act) { 441 switch (act) {
456 case DVACT_DEACTIVATE: 442 case DVACT_DEACTIVATE:
457 if (ifp->if_flags & IFF_RUNNING) 443 if (ifp->if_flags & IFF_RUNNING)
458 rtwn_stop(ifp, 0); 444 rtwn_stop(ifp, 0);
459 return 0; 445 return 0;
460 default: 446 default:
461 return EOPNOTSUPP; 447 return EOPNOTSUPP;
462 } 448 }
463} 449}
464 450
465static void 451static void
466rtwn_setup_rx_desc(struct rtwn_softc *sc, struct r92c_rx_desc *desc, 452rtwn_setup_rx_desc(struct rtwn_softc *sc, struct r92c_rx_desc *desc,
467 bus_addr_t addr, size_t len, int idx) 453 bus_addr_t addr, size_t len, int idx)
468{ 454{
469 455
470 memset(desc, 0, sizeof(*desc)); 456 memset(desc, 0, sizeof(*desc));
471 desc->rxdw0 = htole32(SM(R92C_RXDW0_PKTLEN, len) | 457 desc->rxdw0 = htole32(SM(R92C_RXDW0_PKTLEN, len) |
472 ((idx == RTWN_RX_LIST_COUNT - 1) ? R92C_RXDW0_EOR : 0)); 458 ((idx == RTWN_RX_LIST_COUNT - 1) ? R92C_RXDW0_EOR : 0));
473 desc->rxbufaddr = htole32(addr); 459 desc->rxbufaddr = htole32(addr);
474 bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize, 460 bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize,
475 BUS_SPACE_BARRIER_WRITE); 461 BUS_SPACE_BARRIER_WRITE);
476 desc->rxdw0 |= htole32(R92C_RXDW0_OWN); 462 desc->rxdw0 |= htole32(R92C_RXDW0_OWN);
477} 463}
478 464
479static int 465static int
480rtwn_alloc_rx_list(struct rtwn_softc *sc) 466rtwn_alloc_rx_list(struct rtwn_softc *sc)
481{ 467{
482 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 468 struct rtwn_rx_ring *rx_ring = &sc->rx_ring;
483 struct rtwn_rx_data *rx_data; 469 struct rtwn_rx_data *rx_data;
484 const size_t size = sizeof(struct r92c_rx_desc) * RTWN_RX_LIST_COUNT; 470 const size_t size = sizeof(struct r92c_rx_desc) * RTWN_RX_LIST_COUNT;
485 int i, error = 0; 471 int i, error = 0;
486 472
487 /* Allocate Rx descriptors. */ 473 /* Allocate Rx descriptors. */
488 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT, 474 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT,
489 &rx_ring->map); 475 &rx_ring->map);
490 if (error != 0) { 476 if (error != 0) {
491 aprint_error_dev(sc->sc_dev, 477 aprint_error_dev(sc->sc_dev,
492 "could not create rx desc DMA map\n"); 478 "could not create rx desc DMA map\n");
493 rx_ring->map = NULL; 479 rx_ring->map = NULL;
494 goto fail; 480 goto fail;
495 } 481 }
496 482
497 error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &rx_ring->seg, 1, 483 error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &rx_ring->seg, 1,
498 &rx_ring->nsegs, BUS_DMA_NOWAIT); 484 &rx_ring->nsegs, BUS_DMA_NOWAIT);
499 if (error != 0) { 485 if (error != 0) {
500 aprint_error_dev(sc->sc_dev, "could not allocate rx desc\n"); 486 aprint_error_dev(sc->sc_dev, "could not allocate rx desc\n");
501 goto fail; 487 goto fail;
502 } 488 }
503 489
504 error = bus_dmamem_map(sc->sc_dmat, &rx_ring->seg, rx_ring->nsegs, 490 error = bus_dmamem_map(sc->sc_dmat, &rx_ring->seg, rx_ring->nsegs,
505 size, (void **)&rx_ring->desc, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 491 size, (void **)&rx_ring->desc, BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
506 if (error != 0) { 492 if (error != 0) {
507 bus_dmamem_free(sc->sc_dmat, &rx_ring->seg, rx_ring->nsegs); 493 bus_dmamem_free(sc->sc_dmat, &rx_ring->seg, rx_ring->nsegs);
508 rx_ring->desc = NULL; 494 rx_ring->desc = NULL;
509 aprint_error_dev(sc->sc_dev, "could not map rx desc\n"); 495 aprint_error_dev(sc->sc_dev, "could not map rx desc\n");
510 goto fail; 496 goto fail;
511 } 497 }
512 memset(rx_ring->desc, 0, size); 498 memset(rx_ring->desc, 0, size);
513 499
514 error = bus_dmamap_load_raw(sc->sc_dmat, rx_ring->map, &rx_ring->seg, 500 error = bus_dmamap_load_raw(sc->sc_dmat, rx_ring->map, &rx_ring->seg,
515 1, size, BUS_DMA_NOWAIT); 501 1, size, BUS_DMA_NOWAIT);
516 if (error != 0) { 502 if (error != 0) {
517 aprint_error_dev(sc->sc_dev, "could not load rx desc\n"); 503 aprint_error_dev(sc->sc_dev, "could not load rx desc\n");
518 goto fail; 504 goto fail;
519 } 505 }
520 506
521 /* Allocate Rx buffers. */ 507 /* Allocate Rx buffers. */
522 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 508 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) {
523 rx_data = &rx_ring->rx_data[i]; 509 rx_data = &rx_ring->rx_data[i];
524 510
525 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 511 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES,
526 0, BUS_DMA_NOWAIT, &rx_data->map); 512 0, BUS_DMA_NOWAIT, &rx_data->map);
527 if (error != 0) { 513 if (error != 0) {
528 aprint_error_dev(sc->sc_dev, 514 aprint_error_dev(sc->sc_dev,
529 "could not create rx buf DMA map\n"); 515 "could not create rx buf DMA map\n");
530 goto fail; 516 goto fail;
531 } 517 }
532 518
533 MGETHDR(rx_data->m, M_DONTWAIT, MT_DATA); 519 MGETHDR(rx_data->m, M_DONTWAIT, MT_DATA);
534 if (__predict_false(rx_data->m == NULL)) { 520 if (__predict_false(rx_data->m == NULL)) {
535 aprint_error_dev(sc->sc_dev, 521 aprint_error_dev(sc->sc_dev,
536 "couldn't allocate rx mbuf\n"); 522 "couldn't allocate rx mbuf\n");
537 error = ENOMEM; 523 error = ENOMEM;
538 goto fail; 524 goto fail;
539 } 525 }
540 MCLGET(rx_data->m, M_DONTWAIT); 526 MCLGET(rx_data->m, M_DONTWAIT);
541 if (__predict_false(!(rx_data->m->m_flags & M_EXT))) { 527 if (__predict_false(!(rx_data->m->m_flags & M_EXT))) {
542 aprint_error_dev(sc->sc_dev, 528 aprint_error_dev(sc->sc_dev,
543 "couldn't allocate rx mbuf cluster\n"); 529 "couldn't allocate rx mbuf cluster\n");
544 m_free(rx_data->m); 530 m_free(rx_data->m);
545 rx_data->m = NULL; 531 rx_data->m = NULL;
546 error = ENOMEM; 532 error = ENOMEM;
547 goto fail; 533 goto fail;
548 } 534 }
549 535
550 error = bus_dmamap_load(sc->sc_dmat, rx_data->map, 536 error = bus_dmamap_load(sc->sc_dmat, rx_data->map,
551 mtod(rx_data->m, void *), MCLBYTES, NULL, 537 mtod(rx_data->m, void *), MCLBYTES, NULL,
552 BUS_DMA_NOWAIT | BUS_DMA_READ); 538 BUS_DMA_NOWAIT | BUS_DMA_READ);
553 if (error != 0) { 539 if (error != 0) {
554 aprint_error_dev(sc->sc_dev, 540 aprint_error_dev(sc->sc_dev,
555 "could not load rx buf DMA map\n"); 541 "could not load rx buf DMA map\n");
556 goto fail; 542 goto fail;
557 } 543 }
558 544
559 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 545 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES,
560 BUS_DMASYNC_PREREAD); 546 BUS_DMASYNC_PREREAD);
561 547
562 rtwn_setup_rx_desc(sc, &rx_ring->desc[i], 548 rtwn_setup_rx_desc(sc, &rx_ring->desc[i],
563 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, i); 549 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, i);
564 } 550 }
565fail: if (error != 0) 551fail: if (error != 0)
566 rtwn_free_rx_list(sc); 552 rtwn_free_rx_list(sc);
567 return error; 553 return error;
568} 554}
569 555
570static void 556static void
571rtwn_reset_rx_list(struct rtwn_softc *sc) 557rtwn_reset_rx_list(struct rtwn_softc *sc)
572{ 558{
573 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 559 struct rtwn_rx_ring *rx_ring = &sc->rx_ring;
574 struct rtwn_rx_data *rx_data; 560 struct rtwn_rx_data *rx_data;
575 int i; 561 int i;
576 562
577 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 563 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) {
578 rx_data = &rx_ring->rx_data[i]; 564 rx_data = &rx_ring->rx_data[i];
579 rtwn_setup_rx_desc(sc, &rx_ring->desc[i], 565 rtwn_setup_rx_desc(sc, &rx_ring->desc[i],
580 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, i); 566 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, i);
581 } 567 }
582} 568}
583 569
584static void 570static void
585rtwn_free_rx_list(struct rtwn_softc *sc) 571rtwn_free_rx_list(struct rtwn_softc *sc)
586{ 572{
587 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 573 struct rtwn_rx_ring *rx_ring = &sc->rx_ring;
588 struct rtwn_rx_data *rx_data; 574 struct rtwn_rx_data *rx_data;
589 int i, s; 575 int i, s;
590 576
591 s = splnet(); 577 s = splnet();
592 578
593 if (rx_ring->map) { 579 if (rx_ring->map) {
594 if (rx_ring->desc) { 580 if (rx_ring->desc) {
595 bus_dmamap_unload(sc->sc_dmat, rx_ring->map); 581 bus_dmamap_unload(sc->sc_dmat, rx_ring->map);
596 bus_dmamem_unmap(sc->sc_dmat, rx_ring->desc, 582 bus_dmamem_unmap(sc->sc_dmat, rx_ring->desc,
597 sizeof (struct r92c_rx_desc) * RTWN_RX_LIST_COUNT); 583 sizeof (struct r92c_rx_desc) * RTWN_RX_LIST_COUNT);
598 bus_dmamem_free(sc->sc_dmat, &rx_ring->seg, 584 bus_dmamem_free(sc->sc_dmat, &rx_ring->seg,
599 rx_ring->nsegs); 585 rx_ring->nsegs);
600 rx_ring->desc = NULL; 586 rx_ring->desc = NULL;
601 } 587 }
602 bus_dmamap_destroy(sc->sc_dmat, rx_ring->map); 588 bus_dmamap_destroy(sc->sc_dmat, rx_ring->map);
603 rx_ring->map = NULL; 589 rx_ring->map = NULL;
604 } 590 }
605 591
606 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 592 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) {
607 rx_data = &rx_ring->rx_data[i]; 593 rx_data = &rx_ring->rx_data[i];
608 594
609 if (rx_data->m != NULL) { 595 if (rx_data->m != NULL) {
610 bus_dmamap_unload(sc->sc_dmat, rx_data->map); 596 bus_dmamap_unload(sc->sc_dmat, rx_data->map);
611 m_freem(rx_data->m); 597 m_freem(rx_data->m);
612 rx_data->m = NULL; 598 rx_data->m = NULL;
613 } 599 }
614 bus_dmamap_destroy(sc->sc_dmat, rx_data->map); 600 bus_dmamap_destroy(sc->sc_dmat, rx_data->map);
615 rx_data->map = NULL; 601 rx_data->map = NULL;
616 } 602 }
617 603
618 splx(s); 604 splx(s);
619} 605}
620 606
621static int 607static int
622rtwn_alloc_tx_list(struct rtwn_softc *sc, int qid) 608rtwn_alloc_tx_list(struct rtwn_softc *sc, int qid)
623{ 609{
624 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 610 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid];
625 struct rtwn_tx_data *tx_data; 611 struct rtwn_tx_data *tx_data;
626 const size_t size = sizeof(struct r92c_tx_desc) * RTWN_TX_LIST_COUNT; 612 const size_t size = sizeof(struct r92c_tx_desc) * RTWN_TX_LIST_COUNT;
627 int i = 0, error = 0; 613 int i = 0, error = 0;
628 614
629 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT, 615 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT,
630 &tx_ring->map); 616 &tx_ring->map);
631 if (error != 0) { 617 if (error != 0) {
632 aprint_error_dev(sc->sc_dev, 618 aprint_error_dev(sc->sc_dev,
633 "could not create tx ring DMA map\n"); 619 "could not create tx ring DMA map\n");
634 goto fail; 620 goto fail;
635 } 621 }
636 622
637 error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 623 error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0,
638 &tx_ring->seg, 1, &tx_ring->nsegs, BUS_DMA_NOWAIT); 624 &tx_ring->seg, 1, &tx_ring->nsegs, BUS_DMA_NOWAIT);
639 if (error != 0) { 625 if (error != 0) {
640 aprint_error_dev(sc->sc_dev, 626 aprint_error_dev(sc->sc_dev,
641 "could not allocate tx ring DMA memory\n"); 627 "could not allocate tx ring DMA memory\n");
642 goto fail; 628 goto fail;
643 } 629 }
644 630
645 error = bus_dmamem_map(sc->sc_dmat, &tx_ring->seg, tx_ring->nsegs, 631 error = bus_dmamem_map(sc->sc_dmat, &tx_ring->seg, tx_ring->nsegs,
646 size, (void **)&tx_ring->desc, BUS_DMA_NOWAIT); 632 size, (void **)&tx_ring->desc, BUS_DMA_NOWAIT);
647 if (error != 0) { 633 if (error != 0) {
648 bus_dmamem_free(sc->sc_dmat, &tx_ring->seg, tx_ring->nsegs); 634 bus_dmamem_free(sc->sc_dmat, &tx_ring->seg, tx_ring->nsegs);
649 aprint_error_dev(sc->sc_dev, "can't map tx ring DMA memory\n"); 635 aprint_error_dev(sc->sc_dev, "can't map tx ring DMA memory\n");
650 goto fail; 636 goto fail;
651 } 637 }
652 memset(tx_ring->desc, 0, size); 638 memset(tx_ring->desc, 0, size);
653 639
654 error = bus_dmamap_load(sc->sc_dmat, tx_ring->map, tx_ring->desc, 640 error = bus_dmamap_load(sc->sc_dmat, tx_ring->map, tx_ring->desc,
655 size, NULL, BUS_DMA_NOWAIT); 641 size, NULL, BUS_DMA_NOWAIT);
656 if (error != 0) { 642 if (error != 0) {
657 aprint_error_dev(sc->sc_dev, 643 aprint_error_dev(sc->sc_dev,
658 "could not load tx ring DMA map\n"); 644 "could not load tx ring DMA map\n");
659 goto fail; 645 goto fail;
660 } 646 }
661 647
662 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 648 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) {
663 struct r92c_tx_desc *desc = &tx_ring->desc[i]; 649 struct r92c_tx_desc *desc = &tx_ring->desc[i];
664 650
665 /* setup tx desc */ 651 /* setup tx desc */
666 desc->nextdescaddr = htole32(tx_ring->map->dm_segs[0].ds_addr 652 desc->nextdescaddr = htole32(tx_ring->map->dm_segs[0].ds_addr
667 + sizeof(*desc) * ((i + 1) % RTWN_TX_LIST_COUNT)); 653 + sizeof(*desc) * ((i + 1) % RTWN_TX_LIST_COUNT));
668 654
669 tx_data = &tx_ring->tx_data[i]; 655 tx_data = &tx_ring->tx_data[i];
670 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 656 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES,
671 0, BUS_DMA_NOWAIT, &tx_data->map); 657 0, BUS_DMA_NOWAIT, &tx_data->map);
672 if (error != 0) { 658 if (error != 0) {
673 aprint_error_dev(sc->sc_dev, 659 aprint_error_dev(sc->sc_dev,
674 "could not create tx buf DMA map\n"); 660 "could not create tx buf DMA map\n");
675 goto fail; 661 goto fail;
676 } 662 }
677 tx_data->m = NULL; 663 tx_data->m = NULL;
678 tx_data->ni = NULL; 664 tx_data->ni = NULL;
679 } 665 }
680 666
681fail: 667fail:
682 if (error != 0) 668 if (error != 0)
683 rtwn_free_tx_list(sc, qid); 669 rtwn_free_tx_list(sc, qid);
684 return error; 670 return error;
685} 671}
686 672
687static void 673static void
688rtwn_reset_tx_list(struct rtwn_softc *sc, int qid) 674rtwn_reset_tx_list(struct rtwn_softc *sc, int qid)
689{ 675{
690 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 676 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid];
691 int i; 677 int i;
692 678
693 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 679 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) {
694 struct r92c_tx_desc *desc = &tx_ring->desc[i]; 680 struct r92c_tx_desc *desc = &tx_ring->desc[i];
695 struct rtwn_tx_data *tx_data = &tx_ring->tx_data[i]; 681 struct rtwn_tx_data *tx_data = &tx_ring->tx_data[i];
696 682
697 memset(desc, 0, sizeof(*desc) - 683 memset(desc, 0, sizeof(*desc) -
698 (sizeof(desc->reserved) + sizeof(desc->nextdescaddr64) + 684 (sizeof(desc->reserved) + sizeof(desc->nextdescaddr64) +
699 sizeof(desc->nextdescaddr))); 685 sizeof(desc->nextdescaddr)));
700 686
701 if (tx_data->m != NULL) { 687 if (tx_data->m != NULL) {
702 bus_dmamap_unload(sc->sc_dmat, tx_data->map); 688 bus_dmamap_unload(sc->sc_dmat, tx_data->map);
703 m_freem(tx_data->m); 689 m_freem(tx_data->m);
704 tx_data->m = NULL; 690 tx_data->m = NULL;
705 ieee80211_free_node(tx_data->ni); 691 ieee80211_free_node(tx_data->ni);
706 tx_data->ni = NULL; 692 tx_data->ni = NULL;
707 } 693 }
708 } 694 }
709 695
710 sc->qfullmsk &= ~(1 << qid); 696 sc->qfullmsk &= ~(1 << qid);
711 tx_ring->queued = 0; 697 tx_ring->queued = 0;
712 tx_ring->cur = 0; 698 tx_ring->cur = 0;
713} 699}
714 700
715static void 701static void
716rtwn_free_tx_list(struct rtwn_softc *sc, int qid) 702rtwn_free_tx_list(struct rtwn_softc *sc, int qid)
717{ 703{
718 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 704 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid];
719 struct rtwn_tx_data *tx_data; 705 struct rtwn_tx_data *tx_data;
720 int i; 706 int i;
721 707
722 if (tx_ring->map != NULL) { 708 if (tx_ring->map != NULL) {
723 if (tx_ring->desc != NULL) { 709 if (tx_ring->desc != NULL) {
724 bus_dmamap_unload(sc->sc_dmat, tx_ring->map); 710 bus_dmamap_unload(sc->sc_dmat, tx_ring->map);
725 bus_dmamem_unmap(sc->sc_dmat, tx_ring->desc, 711 bus_dmamem_unmap(sc->sc_dmat, tx_ring->desc,
726 sizeof (struct r92c_tx_desc) * RTWN_TX_LIST_COUNT); 712 sizeof (struct r92c_tx_desc) * RTWN_TX_LIST_COUNT);
727 bus_dmamem_free(sc->sc_dmat, &tx_ring->seg, 713 bus_dmamem_free(sc->sc_dmat, &tx_ring->seg,
728 tx_ring->nsegs); 714 tx_ring->nsegs);
729 } 715 }
730 bus_dmamap_destroy(sc->sc_dmat, tx_ring->map); 716 bus_dmamap_destroy(sc->sc_dmat, tx_ring->map);
731 } 717 }
732 718
733 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 719 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) {
734 tx_data = &tx_ring->tx_data[i]; 720 tx_data = &tx_ring->tx_data[i];
735 721
736 if (tx_data->m != NULL) { 722 if (tx_data->m != NULL) {
737 bus_dmamap_unload(sc->sc_dmat, tx_data->map); 723 bus_dmamap_unload(sc->sc_dmat, tx_data->map);
738 m_freem(tx_data->m); 724 m_freem(tx_data->m);
739 tx_data->m = NULL; 725 tx_data->m = NULL;
740 } 726 }
741 bus_dmamap_destroy(sc->sc_dmat, tx_data->map); 727 bus_dmamap_destroy(sc->sc_dmat, tx_data->map);
742 } 728 }
743 729
744 sc->qfullmsk &= ~(1 << qid); 730 sc->qfullmsk &= ~(1 << qid);
745 tx_ring->queued = 0; 731 tx_ring->queued = 0;
746 tx_ring->cur = 0; 732 tx_ring->cur = 0;
747} 733}
748 734
749static void 735static void
750rtwn_write_1(struct rtwn_softc *sc, uint16_t addr, uint8_t val) 736rtwn_write_1(struct rtwn_softc *sc, uint16_t addr, uint8_t val)
751{ 737{
752 bus_space_write_1(sc->sc_st, sc->sc_sh, addr, val); 738 bus_space_write_1(sc->sc_st, sc->sc_sh, addr, val);
753} 739}
754 740
755static void 741static void
756rtwn_write_2(struct rtwn_softc *sc, uint16_t addr, uint16_t val) 742rtwn_write_2(struct rtwn_softc *sc, uint16_t addr, uint16_t val)
757{ 743{
758 bus_space_write_2(sc->sc_st, sc->sc_sh, addr, htole16(val)); 744 bus_space_write_2(sc->sc_st, sc->sc_sh, addr, htole16(val));
759} 745}
760 746
761static void 747static void
762rtwn_write_4(struct rtwn_softc *sc, uint16_t addr, uint32_t val) 748rtwn_write_4(struct rtwn_softc *sc, uint16_t addr, uint32_t val)
763{ 749{
764 bus_space_write_4(sc->sc_st, sc->sc_sh, addr, htole32(val)); 750 bus_space_write_4(sc->sc_st, sc->sc_sh, addr, htole32(val));
765} 751}
766 752
767static uint8_t 753static uint8_t
768rtwn_read_1(struct rtwn_softc *sc, uint16_t addr) 754rtwn_read_1(struct rtwn_softc *sc, uint16_t addr)
769{ 755{
770 return bus_space_read_1(sc->sc_st, sc->sc_sh, addr); 756 return bus_space_read_1(sc->sc_st, sc->sc_sh, addr);
771} 757}
772 758
773static uint16_t 759static uint16_t
774rtwn_read_2(struct rtwn_softc *sc, uint16_t addr) 760rtwn_read_2(struct rtwn_softc *sc, uint16_t addr)
775{ 761{
776 return le16toh(bus_space_read_2(sc->sc_st, sc->sc_sh, addr)); 762 return le16toh(bus_space_read_2(sc->sc_st, sc->sc_sh, addr));
777} 763}
778 764
779static uint32_t 765static uint32_t
780rtwn_read_4(struct rtwn_softc *sc, uint16_t addr) 766rtwn_read_4(struct rtwn_softc *sc, uint16_t addr)
781{ 767{
782 return le32toh(bus_space_read_4(sc->sc_st, sc->sc_sh, addr)); 768 return le32toh(bus_space_read_4(sc->sc_st, sc->sc_sh, addr));
783} 769}
784 770
785static int 771static int
786rtwn_fw_cmd(struct rtwn_softc *sc, uint8_t id, const void *buf, int len) 772rtwn_fw_cmd(struct rtwn_softc *sc, uint8_t id, const void *buf, int len)
787{ 773{
788 struct r92c_fw_cmd cmd; 774 struct r92c_fw_cmd cmd;
789 uint8_t *cp; 775 uint8_t *cp;
790 int fwcur; 776 int fwcur;
791 int ntries; 777 int ntries;
792 778
793 DPRINTFN(3, ("%s: %s: id=0x%02x, buf=%p, len=%d\n", 779 DPRINTFN(3, ("%s: %s: id=0x%02x, buf=%p, len=%d\n",
794 device_xname(sc->sc_dev), __func__, id, buf, len)); 780 device_xname(sc->sc_dev), __func__, id, buf, len));
795 781
796 fwcur = sc->fwcur; 782 fwcur = sc->fwcur;
797 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 783 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX;
798 784
799 /* Wait for current FW box to be empty. */ 785 /* Wait for current FW box to be empty. */
800 for (ntries = 0; ntries < 100; ntries++) { 786 for (ntries = 0; ntries < 100; ntries++) {
801 if (!(rtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 787 if (!(rtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur)))
802 break; 788 break;
803 DELAY(1); 789 DELAY(1);
804 } 790 }
805 if (ntries == 100) { 791 if (ntries == 100) {
806 aprint_error_dev(sc->sc_dev, 792 aprint_error_dev(sc->sc_dev,
807 "could not send firmware command %d\n", id); 793 "could not send firmware command %d\n", id);
808 return ETIMEDOUT; 794 return ETIMEDOUT;
809 } 795 }
810 796
811 memset(&cmd, 0, sizeof(cmd)); 797 memset(&cmd, 0, sizeof(cmd));
812 KASSERT(len <= sizeof(cmd.msg)); 798 KASSERT(len <= sizeof(cmd.msg));
813 memcpy(cmd.msg, buf, len); 799 memcpy(cmd.msg, buf, len);
814 800
815 /* Write the first word last since that will trigger the FW. */ 801 /* Write the first word last since that will trigger the FW. */
816 cp = (uint8_t *)&cmd; 802 cp = (uint8_t *)&cmd;
817 if (len >= 4) { 803 if (len >= 4) {
818 cmd.id = id | R92C_CMD_FLAG_EXT; 804 cmd.id = id | R92C_CMD_FLAG_EXT;
819 rtwn_write_2(sc, R92C_HMEBOX_EXT(fwcur), cp[1] + (cp[2] << 8)); 805 rtwn_write_2(sc, R92C_HMEBOX_EXT(fwcur), cp[1] + (cp[2] << 8));
820 rtwn_write_4(sc, R92C_HMEBOX(fwcur), 806 rtwn_write_4(sc, R92C_HMEBOX(fwcur),
821 cp[0] + (cp[3] << 8) + (cp[4] << 16) + (cp[5] << 24)); 807 cp[0] + (cp[3] << 8) + (cp[4] << 16) + (cp[5] << 24));
822 } else { 808 } else {
823 cmd.id = id; 809 cmd.id = id;
824 rtwn_write_4(sc, R92C_HMEBOX(fwcur), 810 rtwn_write_4(sc, R92C_HMEBOX(fwcur),
825 cp[0] + (cp[1] << 8) + (cp[2] << 16) + (cp[3] << 24)); 811 cp[0] + (cp[1] << 8) + (cp[2] << 16) + (cp[3] << 24));
826 } 812 }
827 813
828 /* Give firmware some time for processing. */ 814 /* Give firmware some time for processing. */
829 DELAY(2000); 815 DELAY(2000);
830 816
831 return 0; 817 return 0;
832} 818}
833 819
834static void 820static void
835rtwn_rf_write(struct rtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 821rtwn_rf_write(struct rtwn_softc *sc, int chain, uint8_t addr, uint32_t val)
836{ 822{
837 823
838 rtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 824 rtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
839 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 825 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val));
840} 826}
841 827
842static uint32_t 828static uint32_t
843rtwn_rf_read(struct rtwn_softc *sc, int chain, uint8_t addr) 829rtwn_rf_read(struct rtwn_softc *sc, int chain, uint8_t addr)
844{ 830{
845 uint32_t reg[R92C_MAX_CHAINS], val; 831 uint32_t reg[R92C_MAX_CHAINS], val;
846 832
847 reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 833 reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0));
848 if (chain != 0) 834 if (chain != 0)
849 reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 835 reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain));
850 836
851 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 837 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
852 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 838 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE);
853 DELAY(1000); 839 DELAY(1000);
854 840
855 rtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 841 rtwn_bb_write(sc, R92C_HSSI_PARAM2(chain),
856 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 842 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) |
857 R92C_HSSI_PARAM2_READ_EDGE); 843 R92C_HSSI_PARAM2_READ_EDGE);
858 DELAY(1000); 844 DELAY(1000);
859 845
860 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 846 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
861 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 847 reg[0] | R92C_HSSI_PARAM2_READ_EDGE);
862 DELAY(1000); 848 DELAY(1000);
863 849
864 if (rtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 850 if (rtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI)
865 val = rtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 851 val = rtwn_bb_read(sc, R92C_HSPI_READBACK(chain));
866 else 852 else
867 val = rtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 853 val = rtwn_bb_read(sc, R92C_LSSI_READBACK(chain));
868 return MS(val, R92C_LSSI_READBACK_DATA); 854 return MS(val, R92C_LSSI_READBACK_DATA);
869} 855}
870 856
871static int 857static int
872rtwn_llt_write(struct rtwn_softc *sc, uint32_t addr, uint32_t data) 858rtwn_llt_write(struct rtwn_softc *sc, uint32_t addr, uint32_t data)
873{ 859{
874 int ntries; 860 int ntries;
875 861
876 rtwn_write_4(sc, R92C_LLT_INIT, 862 rtwn_write_4(sc, R92C_LLT_INIT,
877 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 863 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) |
878 SM(R92C_LLT_INIT_ADDR, addr) | 864 SM(R92C_LLT_INIT_ADDR, addr) |
879 SM(R92C_LLT_INIT_DATA, data)); 865 SM(R92C_LLT_INIT_DATA, data));
880 /* Wait for write operation to complete. */ 866 /* Wait for write operation to complete. */
881 for (ntries = 0; ntries < 20; ntries++) { 867 for (ntries = 0; ntries < 20; ntries++) {
882 if (MS(rtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 868 if (MS(rtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) ==
883 R92C_LLT_INIT_OP_NO_ACTIVE) 869 R92C_LLT_INIT_OP_NO_ACTIVE)
884 return 0; 870 return 0;
885 DELAY(5); 871 DELAY(5);
886 } 872 }
887 return ETIMEDOUT; 873 return ETIMEDOUT;
888} 874}
889 875
890static uint8_t 876static uint8_t
891rtwn_efuse_read_1(struct rtwn_softc *sc, uint16_t addr) 877rtwn_efuse_read_1(struct rtwn_softc *sc, uint16_t addr)
892{ 878{
893 uint32_t reg; 879 uint32_t reg;
894 int ntries; 880 int ntries;
895 881
896 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 882 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL);
897 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 883 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr);
898 reg &= ~R92C_EFUSE_CTRL_VALID; 884 reg &= ~R92C_EFUSE_CTRL_VALID;
899 rtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 885 rtwn_write_4(sc, R92C_EFUSE_CTRL, reg);
900 /* Wait for read operation to complete. */ 886 /* Wait for read operation to complete. */
901 for (ntries = 0; ntries < 100; ntries++) { 887 for (ntries = 0; ntries < 100; ntries++) {
902 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 888 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL);
903 if (reg & R92C_EFUSE_CTRL_VALID) 889 if (reg & R92C_EFUSE_CTRL_VALID)
904 return MS(reg, R92C_EFUSE_CTRL_DATA); 890 return MS(reg, R92C_EFUSE_CTRL_DATA);
905 DELAY(5); 891 DELAY(5);
906 } 892 }
907 aprint_error_dev(sc->sc_dev, 893 aprint_error_dev(sc->sc_dev,
908 "could not read efuse byte at address 0x%x\n", addr); 894 "could not read efuse byte at address 0x%x\n", addr);
909 return 0xff; 895 return 0xff;
910} 896}
911 897
912static void 898static void
913rtwn_efuse_read(struct rtwn_softc *sc) 899rtwn_efuse_read(struct rtwn_softc *sc)
914{ 900{
915 uint8_t *rom = (uint8_t *)&sc->rom; 901 uint8_t *rom = (uint8_t *)&sc->rom;
916 uint32_t reg; 902 uint32_t reg;
917 uint16_t addr = 0; 903 uint16_t addr = 0;
918 uint8_t off, msk; 904 uint8_t off, msk;
919 int i; 905 int i;
920 906
921 rtwn_efuse_switch_power(sc); 907 rtwn_efuse_switch_power(sc);
922 908
923 memset(&sc->rom, 0xff, sizeof(sc->rom)); 909 memset(&sc->rom, 0xff, sizeof(sc->rom));
924 while (addr < 512) { 910 while (addr < 512) {
925 reg = rtwn_efuse_read_1(sc, addr); 911 reg = rtwn_efuse_read_1(sc, addr);
926 if (reg == 0xff) 912 if (reg == 0xff)
927 break; 913 break;
928 addr++; 914 addr++;
929 off = reg >> 4; 915 off = reg >> 4;
930 msk = reg & 0xf; 916 msk = reg & 0xf;
931 for (i = 0; i < 4; i++) { 917 for (i = 0; i < 4; i++) {
932 if (msk & (1 << i)) 918 if (msk & (1 << i))
933 continue; 919 continue;
934 rom[off * 8 + i * 2 + 0] = rtwn_efuse_read_1(sc, addr); 920 rom[off * 8 + i * 2 + 0] = rtwn_efuse_read_1(sc, addr);
935 addr++; 921 addr++;
936 rom[off * 8 + i * 2 + 1] = rtwn_efuse_read_1(sc, addr); 922 rom[off * 8 + i * 2 + 1] = rtwn_efuse_read_1(sc, addr);
937 addr++; 923 addr++;
938 } 924 }
939 } 925 }
940#ifdef RTWN_DEBUG 926#ifdef RTWN_DEBUG
941 if (rtwn_debug >= 2) { 927 if (rtwn_debug >= 2) {
942 /* Dump ROM content. */ 928 /* Dump ROM content. */
943 printf("\n"); 929 printf("\n");
944 for (i = 0; i < sizeof(sc->rom); i++) 930 for (i = 0; i < sizeof(sc->rom); i++)
945 printf("%02x:", rom[i]); 931 printf("%02x:", rom[i]);
946 printf("\n"); 932 printf("\n");
947 } 933 }
948#endif 934#endif
949} 935}
950 936
951static void 937static void
952rtwn_efuse_switch_power(struct rtwn_softc *sc) 938rtwn_efuse_switch_power(struct rtwn_softc *sc)
953{ 939{
954 uint32_t reg; 940 uint32_t reg;
955 941
956 reg = rtwn_read_2(sc, R92C_SYS_ISO_CTRL); 942 reg = rtwn_read_2(sc, R92C_SYS_ISO_CTRL);
957 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 943 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) {
958 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 944 rtwn_write_2(sc, R92C_SYS_ISO_CTRL,
959 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 945 reg | R92C_SYS_ISO_CTRL_PWC_EV12V);
960 } 946 }
961 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 947 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN);
962 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 948 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) {
963 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 949 rtwn_write_2(sc, R92C_SYS_FUNC_EN,
964 reg | R92C_SYS_FUNC_EN_ELDR); 950 reg | R92C_SYS_FUNC_EN_ELDR);
965 } 951 }
966 reg = rtwn_read_2(sc, R92C_SYS_CLKR); 952 reg = rtwn_read_2(sc, R92C_SYS_CLKR);
967 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 953 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) !=
968 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 954 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) {
969 rtwn_write_2(sc, R92C_SYS_CLKR, 955 rtwn_write_2(sc, R92C_SYS_CLKR,
970 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 956 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M);
971 } 957 }
972} 958}
973 959
974/* rtwn_read_chipid: reg=0x40073b chipid=0x0 */ 960/* rtwn_read_chipid: reg=0x40073b chipid=0x0 */
975static int 961static int
976rtwn_read_chipid(struct rtwn_softc *sc) 962rtwn_read_chipid(struct rtwn_softc *sc)
977{ 963{
978 uint32_t reg; 964 uint32_t reg;
979 965
980 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 966 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
981 967
982 reg = rtwn_read_4(sc, R92C_SYS_CFG); 968 reg = rtwn_read_4(sc, R92C_SYS_CFG);
983 DPRINTF(("%s: version=0x%08x\n", device_xname(sc->sc_dev), reg)); 969 DPRINTF(("%s: version=0x%08x\n", device_xname(sc->sc_dev), reg));
984 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 970 if (reg & R92C_SYS_CFG_TRP_VAUX_EN)
985 /* Unsupported test chip. */ 971 /* Unsupported test chip. */
986 return EIO; 972 return EIO;
987 973
988 if (reg & R92C_SYS_CFG_TYPE_92C) { 974 if (reg & R92C_SYS_CFG_TYPE_92C) {
989 sc->chip |= RTWN_CHIP_92C; 975 sc->chip |= RTWN_CHIP_92C;
990 /* Check if it is a castrated 8192C. */ 976 /* Check if it is a castrated 8192C. */
991 if (MS(rtwn_read_4(sc, R92C_HPON_FSM), 977 if (MS(rtwn_read_4(sc, R92C_HPON_FSM),
992 R92C_HPON_FSM_CHIP_BONDING_ID) == 978 R92C_HPON_FSM_CHIP_BONDING_ID) ==
993 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 979 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R)
994 sc->chip |= RTWN_CHIP_92C_1T2R; 980 sc->chip |= RTWN_CHIP_92C_1T2R;
995 } 981 }
996 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 982 if (reg & R92C_SYS_CFG_VENDOR_UMC) {
997 sc->chip |= RTWN_CHIP_UMC; 983 sc->chip |= RTWN_CHIP_UMC;
998 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 984 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0)
999 sc->chip |= RTWN_CHIP_UMC_A_CUT; 985 sc->chip |= RTWN_CHIP_UMC_A_CUT;
1000 } else if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) != 0) { 986 } else if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) != 0) {
1001 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 1) 987 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 1)
1002 sc->chip |= RTWN_CHIP_UMC | RTWN_CHIP_UMC_B_CUT; 988 sc->chip |= RTWN_CHIP_UMC | RTWN_CHIP_UMC_B_CUT;
1003 else 989 else
1004 /* Unsupported unknown chip. */ 990 /* Unsupported unknown chip. */
1005 return EIO; 991 return EIO;
1006 } 992 }
1007 return 0; 993 return 0;
1008} 994}
1009 995
1010static void 996static void
1011rtwn_read_rom(struct rtwn_softc *sc) 997rtwn_read_rom(struct rtwn_softc *sc)
1012{ 998{
1013 struct ieee80211com *ic = &sc->sc_ic; 999 struct ieee80211com *ic = &sc->sc_ic;
1014 struct r92c_rom *rom = &sc->rom; 1000 struct r92c_rom *rom = &sc->rom;
1015 1001
1016 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1002 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
1017 1003
1018 /* Read full ROM image. */ 1004 /* Read full ROM image. */
1019 rtwn_efuse_read(sc); 1005 rtwn_efuse_read(sc);
1020 1006
1021 if (rom->id != 0x8129) { 1007 if (rom->id != 0x8129) {
1022 aprint_error_dev(sc->sc_dev, "invalid EEPROM ID 0x%x\n", 1008 aprint_error_dev(sc->sc_dev, "invalid EEPROM ID 0x%x\n",
1023 rom->id); 1009 rom->id);
1024 } 1010 }
1025 1011
1026 /* XXX Weird but this is what the vendor driver does. */ 1012 /* XXX Weird but this is what the vendor driver does. */
1027 sc->pa_setting = rtwn_efuse_read_1(sc, 0x1fa); 1013 sc->pa_setting = rtwn_efuse_read_1(sc, 0x1fa);
1028 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1014 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE);
1029 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1015 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY);
1030 1016
1031 DPRINTF(("PA setting=0x%x, board=0x%x, regulatory=%d\n", 1017 DPRINTF(("PA setting=0x%x, board=0x%x, regulatory=%d\n",
1032 sc->pa_setting, sc->board_type, sc->regulatory)); 1018 sc->pa_setting, sc->board_type, sc->regulatory));
1033 1019
1034 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1020 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr);
1035} 1021}
1036 1022
1037static int 1023static int
1038rtwn_media_change(struct ifnet *ifp) 1024rtwn_media_change(struct ifnet *ifp)
1039{ 1025{
1040 int error; 1026 int error;
1041 1027
1042 error = ieee80211_media_change(ifp); 1028 error = ieee80211_media_change(ifp);
1043 if (error != ENETRESET) 1029 if (error != ENETRESET)
1044 return error; 1030 return error;
1045 1031
1046 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1032 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
1047 (IFF_UP | IFF_RUNNING)) { 1033 (IFF_UP | IFF_RUNNING)) {
1048 rtwn_stop(ifp, 0); 1034 rtwn_stop(ifp, 0);
1049 error = rtwn_init(ifp); 1035 error = rtwn_init(ifp);
1050 } 1036 }
1051 return error; 1037 return error;
1052} 1038}
1053 1039
1054/* 1040/*
1055 * Initialize rate adaptation in firmware. 1041 * Initialize rate adaptation in firmware.
1056 */ 1042 */
1057static int 1043static int
1058rtwn_ra_init(struct rtwn_softc *sc) 1044rtwn_ra_init(struct rtwn_softc *sc)
1059{ 1045{
1060 static const uint8_t map[] = { 1046 static const uint8_t map[] = {
1061 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1047 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108
1062 }; 1048 };
1063 struct ieee80211com *ic = &sc->sc_ic; 1049 struct ieee80211com *ic = &sc->sc_ic;
1064 struct ieee80211_node *ni = ic->ic_bss; 1050 struct ieee80211_node *ni = ic->ic_bss;
1065 struct ieee80211_rateset *rs = &ni->ni_rates; 1051 struct ieee80211_rateset *rs = &ni->ni_rates;
1066 struct r92c_fw_cmd_macid_cfg cmd; 1052 struct r92c_fw_cmd_macid_cfg cmd;
1067 uint32_t rates, basicrates; 1053 uint32_t rates, basicrates;
1068 uint8_t mode; 1054 uint8_t mode;
1069 int maxrate, maxbasicrate, error, i, j; 1055 int maxrate, maxbasicrate, error, i, j;
1070 1056
1071 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1057 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
1072 1058
1073 /* Get normal and basic rates mask. */ 1059 /* Get normal and basic rates mask. */
1074 rates = basicrates = 0; 1060 rates = basicrates = 0;
1075 maxrate = maxbasicrate = 0; 1061 maxrate = maxbasicrate = 0;
1076 for (i = 0; i < rs->rs_nrates; i++) { 1062 for (i = 0; i < rs->rs_nrates; i++) {
1077 /* Convert 802.11 rate to HW rate index. */ 1063 /* Convert 802.11 rate to HW rate index. */
1078 for (j = 0; j < __arraycount(map); j++) 1064 for (j = 0; j < __arraycount(map); j++)
1079 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) 1065 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j])
1080 break; 1066 break;
1081 if (j == __arraycount(map)) /* Unknown rate, skip. */ 1067 if (j == __arraycount(map)) /* Unknown rate, skip. */
1082 continue; 1068 continue;
1083 rates |= 1 << j; 1069 rates |= 1 << j;
1084 if (j > maxrate) 1070 if (j > maxrate)
1085 maxrate = j; 1071 maxrate = j;
1086 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1072 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) {
1087 basicrates |= 1 << j; 1073 basicrates |= 1 << j;
1088 if (j > maxbasicrate) 1074 if (j > maxbasicrate)
1089 maxbasicrate = j; 1075 maxbasicrate = j;
1090 } 1076 }
1091 } 1077 }
1092 if (ic->ic_curmode == IEEE80211_MODE_11B) 1078 if (ic->ic_curmode == IEEE80211_MODE_11B)
1093 mode = R92C_RAID_11B; 1079 mode = R92C_RAID_11B;
1094 else 1080 else
1095 mode = R92C_RAID_11BG; 1081 mode = R92C_RAID_11BG;
1096 DPRINTF(("%s: mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1082 DPRINTF(("%s: mode=0x%x rates=0x%08x, basicrates=0x%08x\n",
1097 device_xname(sc->sc_dev), mode, rates, basicrates)); 1083 device_xname(sc->sc_dev), mode, rates, basicrates));
1098 if (basicrates == 0) 1084 if (basicrates == 0)
1099 basicrates |= 1; /* add 1Mbps */ 1085 basicrates |= 1; /* add 1Mbps */
1100 1086
1101 /* Set rates mask for group addressed frames. */ 1087 /* Set rates mask for group addressed frames. */
1102 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1088 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID;
1103 cmd.mask = htole32((mode << 28) | basicrates); 1089 cmd.mask = htole32((mode << 28) | basicrates);
1104 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1090 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd));
1105 if (error != 0) { 1091 if (error != 0) {
1106 aprint_error_dev(sc->sc_dev, 1092 aprint_error_dev(sc->sc_dev,
1107 "could not add broadcast station\n"); 1093 "could not add broadcast station\n");
1108 return error; 1094 return error;
1109 } 1095 }
1110 /* Set initial MRR rate. */ 1096 /* Set initial MRR rate. */
1111 DPRINTF(("%s: maxbasicrate=%d\n", device_xname(sc->sc_dev), 1097 DPRINTF(("%s: maxbasicrate=%d\n", device_xname(sc->sc_dev),
1112 maxbasicrate)); 1098 maxbasicrate));
1113 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1099 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate);
1114 1100
1115 /* Set rates mask for unicast frames. */ 1101 /* Set rates mask for unicast frames. */
1116 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1102 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID;
1117 cmd.mask = htole32((mode << 28) | rates); 1103 cmd.mask = htole32((mode << 28) | rates);
1118 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1104 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd));
1119 if (error != 0) { 1105 if (error != 0) {
1120 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1106 aprint_error_dev(sc->sc_dev, "could not add BSS station\n");
1121 return error; 1107 return error;
1122 } 1108 }
1123 /* Set initial MRR rate. */ 1109 /* Set initial MRR rate. */
1124 DPRINTF(("%s: maxrate=%d\n", device_xname(sc->sc_dev), maxrate)); 1110 DPRINTF(("%s: maxrate=%d\n", device_xname(sc->sc_dev), maxrate));
1125 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1111 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate);
1126 1112
1127 /* Configure Automatic Rate Fallback Register. */ 1113 /* Configure Automatic Rate Fallback Register. */
1128 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1114 if (ic->ic_curmode == IEEE80211_MODE_11B) {
1129 if (rates & 0x0c) 1115 if (rates & 0x0c)
1130 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0d)); 1116 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0d));
1131 else 1117 else
1132 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0f)); 1118 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0f));
1133 } else 1119 } else
1134 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0ff5)); 1120 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0ff5));
1135 1121
1136 /* Indicate highest supported rate. */ 1122 /* Indicate highest supported rate. */
1137 ni->ni_txrate = rs->rs_nrates - 1; 1123 ni->ni_txrate = rs->rs_nrates - 1;
1138 return 0; 1124 return 0;
1139} 1125}
1140 1126
1141static int 1127static int
1142rtwn_get_nettype(struct rtwn_softc *sc) 1128rtwn_get_nettype(struct rtwn_softc *sc)
1143{ 1129{
1144 struct ieee80211com *ic = &sc->sc_ic; 1130 struct ieee80211com *ic = &sc->sc_ic;
1145 int type; 1131 int type;
1146 1132
1147 switch (ic->ic_opmode) { 1133 switch (ic->ic_opmode) {
1148 case IEEE80211_M_STA: 1134 case IEEE80211_M_STA:
1149 type = R92C_CR_NETTYPE_INFRA; 1135 type = R92C_CR_NETTYPE_INFRA;
1150 break; 1136 break;
1151 1137
1152 case IEEE80211_M_HOSTAP: 1138 case IEEE80211_M_HOSTAP:
1153 type = R92C_CR_NETTYPE_AP; 1139 type = R92C_CR_NETTYPE_AP;
1154 break; 1140 break;
1155 1141
1156 case IEEE80211_M_IBSS: 1142 case IEEE80211_M_IBSS:
1157 type = R92C_CR_NETTYPE_ADHOC; 1143 type = R92C_CR_NETTYPE_ADHOC;
1158 break; 1144 break;
1159 1145
1160 default: 1146 default:
1161 type = R92C_CR_NETTYPE_NOLINK; 1147 type = R92C_CR_NETTYPE_NOLINK;
1162 break; 1148 break;
1163 } 1149 }
1164 1150
1165 return type; 1151 return type;
1166} 1152}
1167 1153
1168static void 1154static void
1169rtwn_set_nettype0_msr(struct rtwn_softc *sc, uint8_t type) 1155rtwn_set_nettype0_msr(struct rtwn_softc *sc, uint8_t type)
1170{ 1156{
1171 uint32_t reg; 1157 uint32_t reg;
1172 1158
1173 reg = rtwn_read_4(sc, R92C_CR); 1159 reg = rtwn_read_4(sc, R92C_CR);
1174 reg = RW(reg, R92C_CR_NETTYPE, type); 1160 reg = RW(reg, R92C_CR_NETTYPE, type);
1175 rtwn_write_4(sc, R92C_CR, reg); 1161 rtwn_write_4(sc, R92C_CR, reg);
1176} 1162}
1177 1163
1178static void 1164static void
1179rtwn_tsf_sync_enable(struct rtwn_softc *sc) 1165rtwn_tsf_sync_enable(struct rtwn_softc *sc)
1180{ 1166{
1181 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1167 struct ieee80211_node *ni = sc->sc_ic.ic_bss;
1182 uint64_t tsf; 1168 uint64_t tsf;
1183 1169
1184 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1170 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
1185 1171
1186 /* Enable TSF synchronization. */ 1172 /* Enable TSF synchronization. */
1187 rtwn_write_1(sc, R92C_BCN_CTRL, 1173 rtwn_write_1(sc, R92C_BCN_CTRL,
1188 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1174 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0);
1189 1175
1190 rtwn_write_1(sc, R92C_BCN_CTRL, 1176 rtwn_write_1(sc, R92C_BCN_CTRL,
1191 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1177 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN);
1192 1178
1193 /* Set initial TSF. */ 1179 /* Set initial TSF. */
1194 tsf = ni->ni_tstamp.tsf; 1180 tsf = ni->ni_tstamp.tsf;
1195 tsf = le64toh(tsf); 1181 tsf = le64toh(tsf);
1196 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1182 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU));
1197 tsf -= IEEE80211_DUR_TU; 1183 tsf -= IEEE80211_DUR_TU;
1198 rtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1184 rtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf);
1199 rtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1185 rtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32));
1200 1186
1201 rtwn_write_1(sc, R92C_BCN_CTRL, 1187 rtwn_write_1(sc, R92C_BCN_CTRL,
1202 rtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1188 rtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN);
1203} 1189}
1204 1190
1205static void 1191static void
1206rtwn_set_led(struct rtwn_softc *sc, int led, int on) 1192rtwn_set_led(struct rtwn_softc *sc, int led, int on)
1207{ 1193{
1208 uint8_t reg; 1194 uint8_t reg;
1209 1195
1210 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1196 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
1211 1197
1212 if (led == RTWN_LED_LINK) { 1198 if (led == RTWN_LED_LINK) {
1213 reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1199 reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0;
1214 if (!on) 1200 if (!on)
1215 reg |= R92C_LEDCFG2_DIS; 1201 reg |= R92C_LEDCFG2_DIS;
1216 else 1202 else
1217 reg |= R92C_LEDCFG2_EN; 1203 reg |= R92C_LEDCFG2_EN;
1218 rtwn_write_1(sc, R92C_LEDCFG2, reg); 1204 rtwn_write_1(sc, R92C_LEDCFG2, reg);
1219 sc->ledlink = on; /* Save LED state. */ 1205 sc->ledlink = on; /* Save LED state. */
1220 } 1206 }
1221} 1207}
1222 1208
1223static void 1209static void
1224rtwn_calib_to(void *arg) 1210rtwn_calib_to(void *arg)
1225{ 1211{
1226 struct rtwn_softc *sc = arg; 1212 struct rtwn_softc *sc = arg;
1227 struct r92c_fw_cmd_rssi cmd; 1213 struct r92c_fw_cmd_rssi cmd;
1228 1214
1229 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1215 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
1230 1216
1231 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1217 if (sc->sc_ic.ic_state != IEEE80211_S_RUN)
1232 goto restart_timer; 1218 goto restart_timer;
1233 1219
1234 if (sc->avg_pwdb != -1) { 1220 if (sc->avg_pwdb != -1) {
1235 /* Indicate Rx signal strength to FW for rate adaptation. */ 1221 /* Indicate Rx signal strength to FW for rate adaptation. */
1236 memset(&cmd, 0, sizeof(cmd)); 1222 memset(&cmd, 0, sizeof(cmd));
1237 cmd.macid = 0; /* BSS. */ 1223 cmd.macid = 0; /* BSS. */
1238 cmd.pwdb = sc->avg_pwdb; 1224 cmd.pwdb = sc->avg_pwdb;
1239 DPRINTFN(3, ("sending RSSI command avg=%d\n", sc->avg_pwdb)); 1225 DPRINTFN(3, ("sending RSSI command avg=%d\n", sc->avg_pwdb));
1240 rtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, sizeof(cmd)); 1226 rtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, sizeof(cmd));
1241 } 1227 }
1242 1228
1243 /* Do temperature compensation. */ 1229 /* Do temperature compensation. */
1244 rtwn_temp_calib(sc); 1230 rtwn_temp_calib(sc);
1245 1231
1246 restart_timer: 1232 restart_timer:
1247 callout_schedule(&sc->calib_to, mstohz(2000)); 1233 callout_schedule(&sc->calib_to, mstohz(2000));
1248} 1234}
1249 1235
1250static void 1236static void
1251rtwn_next_scan(void *arg) 1237rtwn_next_scan(void *arg)
1252{ 1238{
1253 struct rtwn_softc *sc = arg; 1239 struct rtwn_softc *sc = arg;
1254 struct ieee80211com *ic = &sc->sc_ic; 1240 struct ieee80211com *ic = &sc->sc_ic;
1255 int s; 1241 int s;
1256 1242
1257 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1243 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
1258 1244
1259 s = splnet(); 1245 s = splnet();
1260 if (ic->ic_state == IEEE80211_S_SCAN) 1246 if (ic->ic_state == IEEE80211_S_SCAN)
1261 ieee80211_next_scan(ic); 1247 ieee80211_next_scan(ic);
1262 splx(s); 1248 splx(s);
1263} 1249}
1264 1250
1265static void 1251static void
1266rtwn_newassoc(struct ieee80211_node *ni, int isnew) 1252rtwn_newassoc(struct ieee80211_node *ni, int isnew)
1267{ 1253{
1268 1254
1269 DPRINTF(("%s: new node %s\n", __func__, ether_sprintf(ni->ni_macaddr))); 1255 DPRINTF(("%s: new node %s\n", __func__, ether_sprintf(ni->ni_macaddr)));
1270 1256
1271 /* start with lowest Tx rate */ 1257 /* start with lowest Tx rate */
1272 ni->ni_txrate = 0; 1258 ni->ni_txrate = 0;
1273} 1259}
1274 1260
1275static int 1261static int
1276rtwn_reset(struct ifnet *ifp) 1262rtwn_reset(struct ifnet *ifp)
1277{ 1263{
1278 struct rtwn_softc *sc = ifp->if_softc; 1264 struct rtwn_softc *sc = ifp->if_softc;
1279 struct ieee80211com *ic = &sc->sc_ic; 1265 struct ieee80211com *ic = &sc->sc_ic;
1280 1266
1281 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1267 if (ic->ic_opmode != IEEE80211_M_MONITOR)
1282 return ENETRESET; 1268 return ENETRESET;
1283 1269
1284 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1270 rtwn_set_chan(sc, ic->ic_curchan, NULL);
1285 1271
1286 return 0; 1272 return 0;
1287} 1273}
1288 1274
1289static int 1275static int
1290rtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1276rtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
1291{ 1277{
1292 struct rtwn_softc *sc = IC2IFP(ic)->if_softc; 1278 struct rtwn_softc *sc = IC2IFP(ic)->if_softc;
1293 struct ieee80211_node *ni; 1279 struct ieee80211_node *ni;
1294 enum ieee80211_state ostate = ic->ic_state; 1280 enum ieee80211_state ostate = ic->ic_state;
1295 uint32_t reg; 1281 uint32_t reg;
1296 int s; 1282 int s;
1297 1283
1298 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1284 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
1299 1285
1300 s = splnet(); 1286 s = splnet();
1301 1287
1302 callout_stop(&sc->scan_to); 1288 callout_stop(&sc->scan_to);
1303 callout_stop(&sc->calib_to); 1289 callout_stop(&sc->calib_to);
1304 1290
1305 if (ostate != nstate) { 1291 if (ostate != nstate) {
1306 DPRINTF(("%s: %s -> %s\n", __func__, 1292 DPRINTF(("%s: %s -> %s\n", __func__,
1307 ieee80211_state_name[ostate], 1293 ieee80211_state_name[ostate],
1308 ieee80211_state_name[nstate])); 1294 ieee80211_state_name[nstate]));
1309 } 1295 }
1310 1296
1311 switch (ostate) { 1297 switch (ostate) {
1312 case IEEE80211_S_INIT: 1298 case IEEE80211_S_INIT:
1313 break; 1299 break;
1314 1300
1315 case IEEE80211_S_SCAN: 1301 case IEEE80211_S_SCAN:
1316 if (nstate != IEEE80211_S_SCAN) { 1302 if (nstate != IEEE80211_S_SCAN) {
1317 /* 1303 /*
1318 * End of scanning 1304 * End of scanning
1319 */ 1305 */
1320 /* flush 4-AC Queue after site_survey */ 1306 /* flush 4-AC Queue after site_survey */
1321 rtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1307 rtwn_write_1(sc, R92C_TXPAUSE, 0x0);
1322 1308
1323 /* Allow Rx from our BSSID only. */ 1309 /* Allow Rx from our BSSID only. */
1324 rtwn_write_4(sc, R92C_RCR, 1310 rtwn_write_4(sc, R92C_RCR,
1325 rtwn_read_4(sc, R92C_RCR) | 1311 rtwn_read_4(sc, R92C_RCR) |
1326 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1312 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN);
1327 } 1313 }
1328 break; 1314 break;
1329 1315
1330 case IEEE80211_S_AUTH: 1316 case IEEE80211_S_AUTH:
1331 case IEEE80211_S_ASSOC: 1317 case IEEE80211_S_ASSOC:
1332 break; 1318 break;
1333 1319
1334 case IEEE80211_S_RUN: 1320 case IEEE80211_S_RUN:
1335 /* Turn link LED off. */ 1321 /* Turn link LED off. */
1336 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1322 rtwn_set_led(sc, RTWN_LED_LINK, 0);
1337 1323
1338 /* Set media status to 'No Link'. */ 1324 /* Set media status to 'No Link'. */
1339 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1325 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK);
1340 1326
1341 /* Stop Rx of data frames. */ 1327 /* Stop Rx of data frames. */
1342 rtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1328 rtwn_write_2(sc, R92C_RXFLTMAP2, 0);
1343 1329
1344 /* Rest TSF. */ 1330 /* Rest TSF. */
1345 rtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1331 rtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03);
1346 1332
1347 /* Disable TSF synchronization. */ 1333 /* Disable TSF synchronization. */
1348 rtwn_write_1(sc, R92C_BCN_CTRL, 1334 rtwn_write_1(sc, R92C_BCN_CTRL,
1349 rtwn_read_1(sc, R92C_BCN_CTRL) | 1335 rtwn_read_1(sc, R92C_BCN_CTRL) |
1350 R92C_BCN_CTRL_DIS_TSF_UDT0); 1336 R92C_BCN_CTRL_DIS_TSF_UDT0);
1351 1337
1352 /* Back to 20MHz mode */ 1338 /* Back to 20MHz mode */
1353 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1339 rtwn_set_chan(sc, ic->ic_curchan, NULL);
1354 1340
1355 /* Reset EDCA parameters. */ 1341 /* Reset EDCA parameters. */
1356 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1342 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217);
1357 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1343 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317);
1358 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1344 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320);
1359 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1345 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444);
1360 1346
1361 /* flush all cam entries */ 1347 /* flush all cam entries */
1362 rtwn_cam_init(sc); 1348 rtwn_cam_init(sc);
1363 break; 1349 break;
1364 } 1350 }
1365 1351
1366 switch (nstate) { 1352 switch (nstate) {
1367 case IEEE80211_S_INIT: 1353 case IEEE80211_S_INIT:
1368 /* Turn link LED off. */ 1354 /* Turn link LED off. */
1369 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1355 rtwn_set_led(sc, RTWN_LED_LINK, 0);
1370 break; 1356 break;
1371 1357
1372 case IEEE80211_S_SCAN: 1358 case IEEE80211_S_SCAN:
1373 if (ostate != IEEE80211_S_SCAN) { 1359 if (ostate != IEEE80211_S_SCAN) {
1374 /* 1360 /*
1375 * Begin of scanning 1361 * Begin of scanning
1376 */ 1362 */
1377 1363
1378 /* Set gain for scanning. */ 1364 /* Set gain for scanning. */
1379 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1365 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));
1380 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1366 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);
1381 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1367 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
1382 1368
1383 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1369 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
1384 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1370 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);
1385 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1371 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
1386 1372
1387 /* Allow Rx from any BSSID. */ 1373 /* Allow Rx from any BSSID. */
1388 rtwn_write_4(sc, R92C_RCR, 1374 rtwn_write_4(sc, R92C_RCR,
1389 rtwn_read_4(sc, R92C_RCR) & 1375 rtwn_read_4(sc, R92C_RCR) &
1390 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1376 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN));
1391 1377
1392 /* Stop Rx of data frames. */ 1378 /* Stop Rx of data frames. */
1393 rtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1379 rtwn_write_2(sc, R92C_RXFLTMAP2, 0);
1394 1380
1395 /* Disable update TSF */ 1381 /* Disable update TSF */
1396 rtwn_write_1(sc, R92C_BCN_CTRL, 1382 rtwn_write_1(sc, R92C_BCN_CTRL,
1397 rtwn_read_1(sc, R92C_BCN_CTRL) | 1383 rtwn_read_1(sc, R92C_BCN_CTRL) |
1398 R92C_BCN_CTRL_DIS_TSF_UDT0); 1384 R92C_BCN_CTRL_DIS_TSF_UDT0);
1399 } 1385 }
1400 1386
1401 /* Make link LED blink during scan. */ 1387 /* Make link LED blink during scan. */
1402 rtwn_set_led(sc, RTWN_LED_LINK, !sc->ledlink); 1388 rtwn_set_led(sc, RTWN_LED_LINK, !sc->ledlink);
1403 1389
1404 /* Pause AC Tx queues. */ 1390 /* Pause AC Tx queues. */
1405 rtwn_write_1(sc, R92C_TXPAUSE, 1391 rtwn_write_1(sc, R92C_TXPAUSE,
1406 rtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1392 rtwn_read_1(sc, R92C_TXPAUSE) | 0x0f);
1407 1393
1408 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1394 rtwn_set_chan(sc, ic->ic_curchan, NULL);
1409 1395
1410 /* Start periodic scan. */ 1396 /* Start periodic scan. */
1411 callout_schedule(&sc->scan_to, mstohz(200)); 1397 callout_schedule(&sc->scan_to, mstohz(200));
1412 break; 1398 break;
1413 1399
1414 case IEEE80211_S_AUTH: 1400 case IEEE80211_S_AUTH:
1415 /* Set initial gain under link. */ 1401 /* Set initial gain under link. */
1416 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1402 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));
1417#ifdef doaslinux 1403#ifdef doaslinux
1418 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1404 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);
1419#else 1405#else
1420 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1406 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);
1421#endif 1407#endif
1422 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1408 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
1423 1409
1424 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1410 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
1425#ifdef doaslinux 1411#ifdef doaslinux
1426 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1412 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);
1427#else 1413#else
1428 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1414 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);
1429#endif 1415#endif
1430 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1416 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
1431 1417
1432 /* Set media status to 'No Link'. */ 1418 /* Set media status to 'No Link'. */
1433 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1419 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK);
1434 1420
1435 /* Allow Rx from any BSSID. */ 1421 /* Allow Rx from any BSSID. */
1436 rtwn_write_4(sc, R92C_RCR, 1422 rtwn_write_4(sc, R92C_RCR,
1437 rtwn_read_4(sc, R92C_RCR) & 1423 rtwn_read_4(sc, R92C_RCR) &
1438 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1424 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN));
1439 1425
1440 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1426 rtwn_set_chan(sc, ic->ic_curchan, NULL);
cvs diff -r1.1 -r1.2 src/sys/dev/pci/if_rtwnreg.h (switch to unified diff)

--- src/sys/dev/pci/if_rtwnreg.h 2015/08/27 14:04:08 1.1
+++ src/sys/dev/pci/if_rtwnreg.h 2015/11/06 14:22:17 1.2
@@ -1,2106 +1,2104 @@ @@ -1,2106 +1,2104 @@
1/* $NetBSD: if_rtwnreg.h,v 1.1 2015/08/27 14:04:08 nonaka Exp $ */ 1/* $NetBSD: if_rtwnreg.h,v 1.2 2015/11/06 14:22:17 nonaka Exp $ */
2/* $OpenBSD: if_rtwnreg.h,v 1.3 2015/06/14 08:02:47 stsp Exp $ */ 2/* $OpenBSD: if_rtwnreg.h,v 1.3 2015/06/14 08:02:47 stsp Exp $ */
3 3
4/*- 4/*-
5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
6 * Copyright (c) 2015 Stefan Sperling <stsp@openbsd.org> 6 * Copyright (c) 2015 Stefan Sperling <stsp@openbsd.org>
7 * 7 *
8 * Permission to use, copy, modify, and distribute this software for any 8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above 9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies. 10 * copyright notice and this permission notice appear in all copies.
11 * 11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 */ 19 */
20 20
21#define R92C_MAX_CHAINS 2 21#define R92C_MAX_CHAINS 2
22 22
23/* Maximum number of output pipes is 3. */ 23/* Maximum number of output pipes is 3. */
24#define R92C_MAX_EPOUT 3 24#define R92C_MAX_EPOUT 3
25 25
26#define R92C_MAX_TX_PWR 0x3f 26#define R92C_MAX_TX_PWR 0x3f
27 27
28#define R92C_PUBQ_NPAGES 176 28#define R92C_PUBQ_NPAGES 176
29#define R92C_HPQ_NPAGES 41 29#define R92C_HPQ_NPAGES 41
30#define R92C_LPQ_NPAGES 28 30#define R92C_LPQ_NPAGES 28
31#define R92C_TXPKTBUF_COUNT 256 31#define R92C_TXPKTBUF_COUNT 256
32#define R92C_TX_PAGE_COUNT \ 32#define R92C_TX_PAGE_COUNT \
33 (R92C_PUBQ_NPAGES + R92C_HPQ_NPAGES + R92C_LPQ_NPAGES) 33 (R92C_PUBQ_NPAGES + R92C_HPQ_NPAGES + R92C_LPQ_NPAGES)
34#define R92C_TX_PAGE_BOUNDARY (R92C_TX_PAGE_COUNT + 1) 34#define R92C_TX_PAGE_BOUNDARY (R92C_TX_PAGE_COUNT + 1)
35 35
36#define R92C_H2C_NBOX 4 36#define R92C_H2C_NBOX 4
37 37
38/* USB Requests. */ 38/* USB Requests. */
39#define R92C_REQ_REGS 0x05 39#define R92C_REQ_REGS 0x05
40 40
41/* 41/*
42 * MAC registers. 42 * MAC registers.
43 */ 43 */
44/* System Configuration. */ 44/* System Configuration. */
45#define R92C_SYS_ISO_CTRL 0x000 45#define R92C_SYS_ISO_CTRL 0x000
46#define R92C_SYS_FUNC_EN 0x002 46#define R92C_SYS_FUNC_EN 0x002
47#define R92C_APS_FSMCO 0x004 47#define R92C_APS_FSMCO 0x004
48#define R92C_SYS_CLKR 0x008 48#define R92C_SYS_CLKR 0x008
49#define R92C_AFE_MISC 0x010 49#define R92C_AFE_MISC 0x010
50#define R92C_SPS0_CTRL 0x011 50#define R92C_SPS0_CTRL 0x011
51#define R92C_SPS_OCP_CFG 0x018 51#define R92C_SPS_OCP_CFG 0x018
52#define R92C_RSV_CTRL 0x01c 52#define R92C_RSV_CTRL 0x01c
53#define R92C_RF_CTRL 0x01f 53#define R92C_RF_CTRL 0x01f
54#define R92C_LDOA15_CTRL 0x020 54#define R92C_LDOA15_CTRL 0x020
55#define R92C_LDOV12D_CTRL 0x021 55#define R92C_LDOV12D_CTRL 0x021
56#define R92C_LDOHCI12_CTRL 0x022 56#define R92C_LDOHCI12_CTRL 0x022
57#define R92C_LPLDO_CTRL 0x023 57#define R92C_LPLDO_CTRL 0x023
58#define R92C_AFE_XTAL_CTRL 0x024 58#define R92C_AFE_XTAL_CTRL 0x024
59#define R92C_AFE_PLL_CTRL 0x028 59#define R92C_AFE_PLL_CTRL 0x028
60#define R92C_EFUSE_CTRL 0x030 60#define R92C_EFUSE_CTRL 0x030
61#define R92C_EFUSE_TEST 0x034 61#define R92C_EFUSE_TEST 0x034
62#define R92C_PWR_DATA 0x038 62#define R92C_PWR_DATA 0x038
63#define R92C_CAL_TIMER 0x03c 63#define R92C_CAL_TIMER 0x03c
64#define R92C_ACLK_MON 0x03e 64#define R92C_ACLK_MON 0x03e
65#define R92C_GPIO_MUXCFG 0x040 65#define R92C_GPIO_MUXCFG 0x040
66#define R92C_GPIO_IO_SEL 0x042 66#define R92C_GPIO_IO_SEL 0x042
67#define R92C_MAC_PINMUX_CFG 0x043 67#define R92C_MAC_PINMUX_CFG 0x043
68#define R92C_GPIO_PIN_CTRL 0x044 68#define R92C_GPIO_PIN_CTRL 0x044
69#define R92C_GPIO_INTM 0x048 69#define R92C_GPIO_INTM 0x048
70#define R92C_LEDCFG0 0x04c 70#define R92C_LEDCFG0 0x04c
71#define R92C_LEDCFG1 0x04d 71#define R92C_LEDCFG1 0x04d
72#define R92C_LEDCFG2 0x04e 72#define R92C_LEDCFG2 0x04e
73#define R92C_LEDCFG3 0x04f 73#define R92C_LEDCFG3 0x04f
74#define R92C_FSIMR 0x050 74#define R92C_FSIMR 0x050
75#define R92C_FSISR 0x054 75#define R92C_FSISR 0x054
76#define R92C_HSIMR 0x058 76#define R92C_HSIMR 0x058
77#define R92C_HSISR 0x05c 77#define R92C_HSISR 0x05c
78#define R92C_MCUFWDL 0x080 78#define R92C_MCUFWDL 0x080
79#define R92C_HMEBOX_EXT(idx) (0x088 + (idx) * 2) 79#define R92C_HMEBOX_EXT(idx) (0x088 + (idx) * 2)
80#define R92C_BIST_SCAN 0x0d0 80#define R92C_BIST_SCAN 0x0d0
81#define R92C_BIST_RPT 0x0d4 81#define R92C_BIST_RPT 0x0d4
82#define R92C_BIST_ROM_RPT 0x0d8 82#define R92C_BIST_ROM_RPT 0x0d8
83#define R92C_USB_SIE_INTF 0x0e0 83#define R92C_USB_SIE_INTF 0x0e0
84#define R92C_PCIE_MIO_INTF 0x0e4 84#define R92C_PCIE_MIO_INTF 0x0e4
85#define R92C_PCIE_MIO_INTD 0x0e8 85#define R92C_PCIE_MIO_INTD 0x0e8
86#define R92C_HPON_FSM 0x0ec 86#define R92C_HPON_FSM 0x0ec
87#define R92C_SYS_CFG 0x0f0 87#define R92C_SYS_CFG 0x0f0
88/* MAC General Configuration. */ 88/* MAC General Configuration. */
89#define R92C_CR 0x100 89#define R92C_CR 0x100
90#define R92C_PBP 0x104 90#define R92C_PBP 0x104
91#define R92C_TRXDMA_CTRL 0x10c 91#define R92C_TRXDMA_CTRL 0x10c
92#define R92C_TRXFF_BNDY 0x114 92#define R92C_TRXFF_BNDY 0x114
93#define R92C_TRXFF_STATUS 0x118 93#define R92C_TRXFF_STATUS 0x118
94#define R92C_RXFF_PTR 0x11c 94#define R92C_RXFF_PTR 0x11c
95#define R92C_HIMR 0x120 95#define R92C_HIMR 0x120
96#define R92C_HISR 0x124 96#define R92C_HISR 0x124
97#define R92C_HIMRE 0x128 97#define R92C_HIMRE 0x128
98#define R92C_HISRE 0x12c 98#define R92C_HISRE 0x12c
99#define R92C_CPWM 0x12f 99#define R92C_CPWM 0x12f
100#define R92C_FWIMR 0x130 100#define R92C_FWIMR 0x130
101#define R92C_FWISR 0x134 101#define R92C_FWISR 0x134
102#define R92C_PKTBUF_DBG_CTRL 0x140 102#define R92C_PKTBUF_DBG_CTRL 0x140
103#define R92C_PKTBUF_DBG_DATA_L 0x144 103#define R92C_PKTBUF_DBG_DATA_L 0x144
104#define R92C_PKTBUF_DBG_DATA_H 0x148 104#define R92C_PKTBUF_DBG_DATA_H 0x148
105#define R92C_TC0_CTRL(i) (0x150 + (i) * 4) 105#define R92C_TC0_CTRL(i) (0x150 + (i) * 4)
106#define R92C_TCUNIT_BASE 0x164 106#define R92C_TCUNIT_BASE 0x164
107#define R92C_MBIST_START 0x174 107#define R92C_MBIST_START 0x174
108#define R92C_MBIST_DONE 0x178 108#define R92C_MBIST_DONE 0x178
109#define R92C_MBIST_FAIL 0x17c 109#define R92C_MBIST_FAIL 0x17c
110#define R92C_C2HEVT_MSG_NORMAL 0x1a0 110#define R92C_C2HEVT_MSG_NORMAL 0x1a0
111#define R92C_C2HEVT_MSG_TEST 0x1b8 111#define R92C_C2HEVT_MSG_TEST 0x1b8
112#define R92C_C2HEVT_CLEAR 0x1bf 112#define R92C_C2HEVT_CLEAR 0x1bf
113#define R92C_MCUTST_1 0x1c0 113#define R92C_MCUTST_1 0x1c0
114#define R92C_FMETHR 0x1c8 114#define R92C_FMETHR 0x1c8
115#define R92C_HMETFR 0x1cc 115#define R92C_HMETFR 0x1cc
116#define R92C_HMEBOX(idx) (0x1d0 + (idx) * 4) 116#define R92C_HMEBOX(idx) (0x1d0 + (idx) * 4)
117#define R92C_LLT_INIT 0x1e0 117#define R92C_LLT_INIT 0x1e0
118#define R92C_BB_ACCESS_CTRL 0x1e8 118#define R92C_BB_ACCESS_CTRL 0x1e8
119#define R92C_BB_ACCESS_DATA 0x1ec 119#define R92C_BB_ACCESS_DATA 0x1ec
120/* Tx DMA Configuration. */ 120/* Tx DMA Configuration. */
121#define R92C_RQPN 0x200 121#define R92C_RQPN 0x200
122#define R92C_FIFOPAGE 0x204 122#define R92C_FIFOPAGE 0x204
123#define R92C_TDECTRL 0x208 123#define R92C_TDECTRL 0x208
124#define R92C_TXDMA_OFFSET_CHK 0x20c 124#define R92C_TXDMA_OFFSET_CHK 0x20c
125#define R92C_TXDMA_STATUS 0x210 125#define R92C_TXDMA_STATUS 0x210
126#define R92C_RQPN_NPQ 0x214 126#define R92C_RQPN_NPQ 0x214
127/* Rx DMA Configuration. */ 127/* Rx DMA Configuration. */
128#define R92C_RXDMA_AGG_PG_TH 0x280 128#define R92C_RXDMA_AGG_PG_TH 0x280
129#define R92C_RXPKT_NUM 0x284 129#define R92C_RXPKT_NUM 0x284
130#define R92C_RXDMA_STATUS 0x288 130#define R92C_RXDMA_STATUS 0x288
131 131
132#define R92C_PCIE_CTRL_REG 0x300 132#define R92C_PCIE_CTRL_REG 0x300
133#define R92C_INT_MIG 0x304 133#define R92C_INT_MIG 0x304
134#define R92C_BCNQ_DESA 0x308 134#define R92C_BCNQ_DESA 0x308
135#define R92C_HQ_DESA 0x310 135#define R92C_HQ_DESA 0x310
136#define R92C_MGQ_DESA 0x318 136#define R92C_MGQ_DESA 0x318
137#define R92C_VOQ_DESA 0x320 137#define R92C_VOQ_DESA 0x320
138#define R92C_VIQ_DESA 0x328 138#define R92C_VIQ_DESA 0x328
139#define R92C_BEQ_DESA 0x330 139#define R92C_BEQ_DESA 0x330
140#define R92C_BKQ_DESA 0x338 140#define R92C_BKQ_DESA 0x338
141#define R92C_RX_DESA 0x340 141#define R92C_RX_DESA 0x340
142#define R92C_DBI 0x348 142#define R92C_DBI 0x348
143#define R92C_MDIO 0x354 143#define R92C_MDIO 0x354
144#define R92C_DBG_SEL 0x360 144#define R92C_DBG_SEL 0x360
145#define R92C_PCIE_HRPWM 0x361 145#define R92C_PCIE_HRPWM 0x361
146#define R92C_PCIE_HCPWM 0x363 146#define R92C_PCIE_HCPWM 0x363
147#define R92C_UART_CTRL 0x364 147#define R92C_UART_CTRL 0x364
148#define R92C_UART_TX_DES 0x370 148#define R92C_UART_TX_DES 0x370
149#define R92C_UART_RX_DES 0x378 149#define R92C_UART_RX_DES 0x378
150 150
151#define R92C_VOQ_INFORMATION 0x0400 151#define R92C_VOQ_INFORMATION 0x0400
152#define R92C_VIQ_INFORMATION 0x0404 152#define R92C_VIQ_INFORMATION 0x0404
153#define R92C_BEQ_INFORMATION 0x0408 153#define R92C_BEQ_INFORMATION 0x0408
154#define R92C_BKQ_INFORMATION 0x040C 154#define R92C_BKQ_INFORMATION 0x040C
155#define R92C_MGQ_INFORMATION 0x0410 155#define R92C_MGQ_INFORMATION 0x0410
156#define R92C_HGQ_INFORMATION 0x0414 156#define R92C_HGQ_INFORMATION 0x0414
157#define R92C_BCNQ_INFORMATION 0x0418 157#define R92C_BCNQ_INFORMATION 0x0418
158#define R92C_CPU_MGQ_INFORMATION 0x041C 158#define R92C_CPU_MGQ_INFORMATION 0x041C
159 159
160/* Protocol Configuration. */ 160/* Protocol Configuration. */
161#define R92C_FWHW_TXQ_CTRL 0x420 161#define R92C_FWHW_TXQ_CTRL 0x420
162#define R92C_HWSEQ_CTRL 0x423 162#define R92C_HWSEQ_CTRL 0x423
163#define R92C_TXPKTBUF_BCNQ_BDNY 0x424 163#define R92C_TXPKTBUF_BCNQ_BDNY 0x424
164#define R92C_TXPKTBUF_MGQ_BDNY 0x425 164#define R92C_TXPKTBUF_MGQ_BDNY 0x425
165#define R92C_SPEC_SIFS 0x428 165#define R92C_SPEC_SIFS 0x428
166#define R92C_RL 0x42a 166#define R92C_RL 0x42a
167#define R92C_DARFRC 0x430 167#define R92C_DARFRC 0x430
168#define R92C_RARFRC 0x438 168#define R92C_RARFRC 0x438
169#define R92C_RRSR 0x440 169#define R92C_RRSR 0x440
170#define R92C_ARFR(i) (0x444 + (i) * 4) 170#define R92C_ARFR(i) (0x444 + (i) * 4)
171#define R92C_AGGLEN_LMT 0x458 171#define R92C_AGGLEN_LMT 0x458
172#define R92C_AMPDU_MIN_SPACE 0x45c 172#define R92C_AMPDU_MIN_SPACE 0x45c
173#define R92C_TXPKTBUF_WMAC_LBK_BF_HD 0x45d 173#define R92C_TXPKTBUF_WMAC_LBK_BF_HD 0x45d
174#define R92C_FAST_EDCA_CTRL 0x460 174#define R92C_FAST_EDCA_CTRL 0x460
175#define R92C_RD_RESP_PKT_TH 0x463 175#define R92C_RD_RESP_PKT_TH 0x463
176#define R92C_INIRTS_RATE_SEL 0x480 176#define R92C_INIRTS_RATE_SEL 0x480
177#define R92C_INIDATA_RATE_SEL(macid) (0x484 + (macid)) 177#define R92C_INIDATA_RATE_SEL(macid) (0x484 + (macid))
178/* EDCA Configuration. */ 178/* EDCA Configuration. */
179#define R92C_EDCA_VO_PARAM 0x500 179#define R92C_EDCA_VO_PARAM 0x500
180#define R92C_EDCA_VI_PARAM 0x504 180#define R92C_EDCA_VI_PARAM 0x504
181#define R92C_EDCA_BE_PARAM 0x508 181#define R92C_EDCA_BE_PARAM 0x508
182#define R92C_EDCA_BK_PARAM 0x50c 182#define R92C_EDCA_BK_PARAM 0x50c
183#define R92C_BCNTCFG 0x510 183#define R92C_BCNTCFG 0x510
184#define R92C_PIFS 0x512 184#define R92C_PIFS 0x512
185#define R92C_RDG_PIFS 0x513 185#define R92C_RDG_PIFS 0x513
186#define R92C_SIFS_CCK 0x514 186#define R92C_SIFS_CCK 0x514
187#define R92C_SIFS_OFDM 0x516 187#define R92C_SIFS_OFDM 0x516
188#define R92C_AGGR_BREAK_TIME 0x51a 188#define R92C_AGGR_BREAK_TIME 0x51a
189#define R92C_SLOT 0x51b 189#define R92C_SLOT 0x51b
190#define R92C_TX_PTCL_CTRL 0x520 190#define R92C_TX_PTCL_CTRL 0x520
191#define R92C_TXPAUSE 0x522 191#define R92C_TXPAUSE 0x522
192#define R92C_DIS_TXREQ_CLR 0x523 192#define R92C_DIS_TXREQ_CLR 0x523
193#define R92C_RD_CTRL 0x524 193#define R92C_RD_CTRL 0x524
194#define R92C_TBTT_PROHIBIT 0x540 194#define R92C_TBTT_PROHIBIT 0x540
195#define R92C_RD_NAV_NXT 0x544 195#define R92C_RD_NAV_NXT 0x544
196#define R92C_NAV_PROT_LEN 0x546 196#define R92C_NAV_PROT_LEN 0x546
197#define R92C_BCN_CTRL 0x550 197#define R92C_BCN_CTRL 0x550
198#define R92C_USTIME_TSF 0x551 198#define R92C_USTIME_TSF 0x551
199#define R92C_MBID_NUM 0x552 199#define R92C_MBID_NUM 0x552
200#define R92C_DUAL_TSF_RST 0x553 200#define R92C_DUAL_TSF_RST 0x553
201#define R92C_BCN_INTERVAL 0x554 201#define R92C_BCN_INTERVAL 0x554
202#define R92C_DRVERLYINT 0x558 202#define R92C_DRVERLYINT 0x558
203#define R92C_BCNDMATIM 0x559 203#define R92C_BCNDMATIM 0x559
204#define R92C_ATIMWND 0x55a 204#define R92C_ATIMWND 0x55a
205#define R92C_BCN_MAX_ERR 0x55d 205#define R92C_BCN_MAX_ERR 0x55d
206#define R92C_RXTSF_OFFSET_CCK 0x55e 206#define R92C_RXTSF_OFFSET_CCK 0x55e
207#define R92C_RXTSF_OFFSET_OFDM 0x55f 207#define R92C_RXTSF_OFFSET_OFDM 0x55f
208#define R92C_TSFTR 0x560 208#define R92C_TSFTR 0x560
209#define R92C_INIT_TSFTR 0x564 209#define R92C_INIT_TSFTR 0x564
210#define R92C_PSTIMER 0x580 210#define R92C_PSTIMER 0x580
211#define R92C_TIMER0 0x584 211#define R92C_TIMER0 0x584
212#define R92C_TIMER1 0x588 212#define R92C_TIMER1 0x588
213#define R92C_ACMHWCTRL 0x5c0 213#define R92C_ACMHWCTRL 0x5c0
214#define R92C_ACMRSTCTRL 0x5c1 214#define R92C_ACMRSTCTRL 0x5c1
215#define R92C_ACMAVG 0x5c2 215#define R92C_ACMAVG 0x5c2
216#define R92C_VO_ADMTIME 0x5c4 216#define R92C_VO_ADMTIME 0x5c4
217#define R92C_VI_ADMTIME 0x5c6 217#define R92C_VI_ADMTIME 0x5c6
218#define R92C_BE_ADMTIME 0x5c8 218#define R92C_BE_ADMTIME 0x5c8
219#define R92C_EDCA_RANDOM_GEN 0x5cc 219#define R92C_EDCA_RANDOM_GEN 0x5cc
220#define R92C_SCH_TXCMD 0x5d0 220#define R92C_SCH_TXCMD 0x5d0
221/* WMAC Configuration. */ 221/* WMAC Configuration. */
222#define R92C_APSD_CTRL 0x600 222#define R92C_APSD_CTRL 0x600
223#define R92C_BWOPMODE 0x603 223#define R92C_BWOPMODE 0x603
224#define R92C_TCR 0x604 224#define R92C_TCR 0x604
225#define R92C_RCR 0x608 225#define R92C_RCR 0x608
226#define R92C_RX_DRVINFO_SZ 0x60f 226#define R92C_RX_DRVINFO_SZ 0x60f
227#define R92C_MACID 0x610 227#define R92C_MACID 0x610
228#define R92C_BSSID 0x618 228#define R92C_BSSID 0x618
229#define R92C_MAR 0x620 229#define R92C_MAR 0x620
230#define R92C_MAC_SPEC_SIFS 0x63a 230#define R92C_MAC_SPEC_SIFS 0x63a
231#define R92C_R2T_SIFS 0x63c 231#define R92C_R2T_SIFS 0x63c
232#define R92C_T2T_SIFS 0x63e 232#define R92C_T2T_SIFS 0x63e
233#define R92C_ACKTO 0x640 233#define R92C_ACKTO 0x640
234#define R92C_CAMCMD 0x670 234#define R92C_CAMCMD 0x670
235#define R92C_CAMWRITE 0x674 235#define R92C_CAMWRITE 0x674
236#define R92C_CAMREAD 0x678 236#define R92C_CAMREAD 0x678
237#define R92C_CAMDBG 0x67c 237#define R92C_CAMDBG 0x67c
238#define R92C_SECCFG 0x680 238#define R92C_SECCFG 0x680
239#define R92C_RXFLTMAP0 0x6a0 239#define R92C_RXFLTMAP0 0x6a0
240#define R92C_RXFLTMAP1 0x6a2 240#define R92C_RXFLTMAP1 0x6a2
241#define R92C_RXFLTMAP2 0x6a4 241#define R92C_RXFLTMAP2 0x6a4
242 242
243/* Bits for R92C_SYS_ISO_CTRL. */ 243/* Bits for R92C_SYS_ISO_CTRL. */
244#define R92C_SYS_ISO_CTRL_MD2PP 0x0001 244#define R92C_SYS_ISO_CTRL_MD2PP 0x0001
245#define R92C_SYS_ISO_CTRL_UA2USB 0x0002 245#define R92C_SYS_ISO_CTRL_UA2USB 0x0002
246#define R92C_SYS_ISO_CTRL_UD2CORE 0x0004 246#define R92C_SYS_ISO_CTRL_UD2CORE 0x0004
247#define R92C_SYS_ISO_CTRL_PA2PCIE 0x0008 247#define R92C_SYS_ISO_CTRL_PA2PCIE 0x0008
248#define R92C_SYS_ISO_CTRL_PD2CORE 0x0010 248#define R92C_SYS_ISO_CTRL_PD2CORE 0x0010
249#define R92C_SYS_ISO_CTRL_IP2MAC 0x0020 249#define R92C_SYS_ISO_CTRL_IP2MAC 0x0020
250#define R92C_SYS_ISO_CTRL_DIOP 0x0040 250#define R92C_SYS_ISO_CTRL_DIOP 0x0040
251#define R92C_SYS_ISO_CTRL_DIOE 0x0080 251#define R92C_SYS_ISO_CTRL_DIOE 0x0080
252#define R92C_SYS_ISO_CTRL_EB2CORE 0x0100 252#define R92C_SYS_ISO_CTRL_EB2CORE 0x0100
253#define R92C_SYS_ISO_CTRL_DIOR 0x0200 253#define R92C_SYS_ISO_CTRL_DIOR 0x0200
254#define R92C_SYS_ISO_CTRL_PWC_EV25V 0x4000 254#define R92C_SYS_ISO_CTRL_PWC_EV25V 0x4000
255#define R92C_SYS_ISO_CTRL_PWC_EV12V 0x8000 255#define R92C_SYS_ISO_CTRL_PWC_EV12V 0x8000
256 256
257/* Bits for R92C_SYS_FUNC_EN. */ 257/* Bits for R92C_SYS_FUNC_EN. */
258#define R92C_SYS_FUNC_EN_BBRSTB 0x0001 258#define R92C_SYS_FUNC_EN_BBRSTB 0x0001
259#define R92C_SYS_FUNC_EN_BB_GLB_RST 0x0002 259#define R92C_SYS_FUNC_EN_BB_GLB_RST 0x0002
260#define R92C_SYS_FUNC_EN_USBA 0x0004 260#define R92C_SYS_FUNC_EN_USBA 0x0004
261#define R92C_SYS_FUNC_EN_UPLL 0x0008 261#define R92C_SYS_FUNC_EN_UPLL 0x0008
262#define R92C_SYS_FUNC_EN_USBD 0x0010 262#define R92C_SYS_FUNC_EN_USBD 0x0010
263#define R92C_SYS_FUNC_EN_DIO_PCIE 0x0020 263#define R92C_SYS_FUNC_EN_DIO_PCIE 0x0020
264#define R92C_SYS_FUNC_EN_PCIEA 0x0040 264#define R92C_SYS_FUNC_EN_PCIEA 0x0040
265#define R92C_SYS_FUNC_EN_PPLL 0x0080 265#define R92C_SYS_FUNC_EN_PPLL 0x0080
266#define R92C_SYS_FUNC_EN_PCIED 0x0100 266#define R92C_SYS_FUNC_EN_PCIED 0x0100
267#define R92C_SYS_FUNC_EN_DIOE 0x0200 267#define R92C_SYS_FUNC_EN_DIOE 0x0200
268#define R92C_SYS_FUNC_EN_CPUEN 0x0400 268#define R92C_SYS_FUNC_EN_CPUEN 0x0400
269#define R92C_SYS_FUNC_EN_DCORE 0x0800 269#define R92C_SYS_FUNC_EN_DCORE 0x0800
270#define R92C_SYS_FUNC_EN_ELDR 0x1000 270#define R92C_SYS_FUNC_EN_ELDR 0x1000
271#define R92C_SYS_FUNC_EN_DIO_RF 0x2000 271#define R92C_SYS_FUNC_EN_DIO_RF 0x2000
272#define R92C_SYS_FUNC_EN_HWPDN 0x4000 272#define R92C_SYS_FUNC_EN_HWPDN 0x4000
273#define R92C_SYS_FUNC_EN_MREGEN 0x8000 273#define R92C_SYS_FUNC_EN_MREGEN 0x8000
274 274
275/* Bits for R92C_APS_FSMCO. */ 275/* Bits for R92C_APS_FSMCO. */
276#define R92C_APS_FSMCO_PFM_LDALL 0x00000001 276#define R92C_APS_FSMCO_PFM_LDALL 0x00000001
277#define R92C_APS_FSMCO_PFM_ALDN 0x00000002 277#define R92C_APS_FSMCO_PFM_ALDN 0x00000002
278#define R92C_APS_FSMCO_PFM_LDKP 0x00000004 278#define R92C_APS_FSMCO_PFM_LDKP 0x00000004
279#define R92C_APS_FSMCO_PFM_WOWL 0x00000008 279#define R92C_APS_FSMCO_PFM_WOWL 0x00000008
280#define R92C_APS_FSMCO_PDN_EN 0x00000010 280#define R92C_APS_FSMCO_PDN_EN 0x00000010
281#define R92C_APS_FSMCO_PDN_PL 0x00000020 281#define R92C_APS_FSMCO_PDN_PL 0x00000020
282#define R92C_APS_FSMCO_APFM_ONMAC 0x00000100 282#define R92C_APS_FSMCO_APFM_ONMAC 0x00000100
283#define R92C_APS_FSMCO_APFM_OFF 0x00000200 283#define R92C_APS_FSMCO_APFM_OFF 0x00000200
284#define R92C_APS_FSMCO_APFM_RSM 0x00000400 284#define R92C_APS_FSMCO_APFM_RSM 0x00000400
285#define R92C_APS_FSMCO_AFSM_HSUS 0x00000800 285#define R92C_APS_FSMCO_AFSM_HSUS 0x00000800
286#define R92C_APS_FSMCO_AFSM_PCIE 0x00001000 286#define R92C_APS_FSMCO_AFSM_PCIE 0x00001000
287#define R92C_APS_FSMCO_APDM_MAC 0x00002000 287#define R92C_APS_FSMCO_APDM_MAC 0x00002000
288#define R92C_APS_FSMCO_APDM_HOST 0x00004000 288#define R92C_APS_FSMCO_APDM_HOST 0x00004000
289#define R92C_APS_FSMCO_APDM_HPDN 0x00008000 289#define R92C_APS_FSMCO_APDM_HPDN 0x00008000
290#define R92C_APS_FSMCO_RDY_MACON 0x00010000 290#define R92C_APS_FSMCO_RDY_MACON 0x00010000
291#define R92C_APS_FSMCO_SUS_HOST 0x00020000 291#define R92C_APS_FSMCO_SUS_HOST 0x00020000
292#define R92C_APS_FSMCO_ROP_ALD 0x00100000 292#define R92C_APS_FSMCO_ROP_ALD 0x00100000
293#define R92C_APS_FSMCO_ROP_PWR 0x00200000 293#define R92C_APS_FSMCO_ROP_PWR 0x00200000
294#define R92C_APS_FSMCO_ROP_SPS 0x00400000 294#define R92C_APS_FSMCO_ROP_SPS 0x00400000
295#define R92C_APS_FSMCO_SOP_MRST 0x02000000 295#define R92C_APS_FSMCO_SOP_MRST 0x02000000
296#define R92C_APS_FSMCO_SOP_FUSE 0x04000000 296#define R92C_APS_FSMCO_SOP_FUSE 0x04000000
297#define R92C_APS_FSMCO_SOP_ABG 0x08000000 297#define R92C_APS_FSMCO_SOP_ABG 0x08000000
298#define R92C_APS_FSMCO_SOP_AMB 0x10000000 298#define R92C_APS_FSMCO_SOP_AMB 0x10000000
299#define R92C_APS_FSMCO_SOP_RCK 0x20000000 299#define R92C_APS_FSMCO_SOP_RCK 0x20000000
300#define R92C_APS_FSMCO_SOP_A8M 0x40000000 300#define R92C_APS_FSMCO_SOP_A8M 0x40000000
301#define R92C_APS_FSMCO_XOP_BTCK 0x80000000 301#define R92C_APS_FSMCO_XOP_BTCK 0x80000000
302 302
303/* Bits for R92C_SYS_CLKR. */ 303/* Bits for R92C_SYS_CLKR. */
304#define R92C_SYS_CLKR_ANAD16V_EN 0x00000001 304#define R92C_SYS_CLKR_ANAD16V_EN 0x00000001
305#define R92C_SYS_CLKR_ANA8M 0x00000002 305#define R92C_SYS_CLKR_ANA8M 0x00000002
306#define R92C_SYS_CLKR_MACSLP 0x00000010 306#define R92C_SYS_CLKR_MACSLP 0x00000010
307#define R92C_SYS_CLKR_LOADER_EN 0x00000020 307#define R92C_SYS_CLKR_LOADER_EN 0x00000020
308#define R92C_SYS_CLKR_80M_SSC_DIS 0x00000080 308#define R92C_SYS_CLKR_80M_SSC_DIS 0x00000080
309#define R92C_SYS_CLKR_80M_SSC_EN_HO 0x00000100 309#define R92C_SYS_CLKR_80M_SSC_EN_HO 0x00000100
310#define R92C_SYS_CLKR_PHY_SSC_RSTB 0x00000200 310#define R92C_SYS_CLKR_PHY_SSC_RSTB 0x00000200
311#define R92C_SYS_CLKR_SEC_EN 0x00000400 311#define R92C_SYS_CLKR_SEC_EN 0x00000400
312#define R92C_SYS_CLKR_MAC_EN 0x00000800 312#define R92C_SYS_CLKR_MAC_EN 0x00000800
313#define R92C_SYS_CLKR_SYS_EN 0x00001000 313#define R92C_SYS_CLKR_SYS_EN 0x00001000
314#define R92C_SYS_CLKR_RING_EN 0x00002000 314#define R92C_SYS_CLKR_RING_EN 0x00002000
315 315
316/* Bits for R92C_RF_CTRL. */ 316/* Bits for R92C_RF_CTRL. */
317#define R92C_RF_CTRL_EN 0x01 317#define R92C_RF_CTRL_EN 0x01
318#define R92C_RF_CTRL_RSTB 0x02 318#define R92C_RF_CTRL_RSTB 0x02
319#define R92C_RF_CTRL_SDMRSTB 0x04 319#define R92C_RF_CTRL_SDMRSTB 0x04
320 320
321/* Bits for R92C_LDOV12D_CTRL. */ 321/* Bits for R92C_LDOV12D_CTRL. */
322#define R92C_LDOV12D_CTRL_LDV12_EN 0x01 322#define R92C_LDOV12D_CTRL_LDV12_EN 0x01
323 323
324/* Bits for R92C_EFUSE_CTRL. */ 324/* Bits for R92C_EFUSE_CTRL. */
325#define R92C_EFUSE_CTRL_DATA_M 0x000000ff 325#define R92C_EFUSE_CTRL_DATA_M 0x000000ff
326#define R92C_EFUSE_CTRL_DATA_S 0 326#define R92C_EFUSE_CTRL_DATA_S 0
327#define R92C_EFUSE_CTRL_ADDR_M 0x0003ff00 327#define R92C_EFUSE_CTRL_ADDR_M 0x0003ff00
328#define R92C_EFUSE_CTRL_ADDR_S 8 328#define R92C_EFUSE_CTRL_ADDR_S 8
329#define R92C_EFUSE_CTRL_VALID 0x80000000 329#define R92C_EFUSE_CTRL_VALID 0x80000000
330 330
331/* Bits for R92C_GPIO_MUXCFG. */ 331/* Bits for R92C_GPIO_MUXCFG. */
332#define R92C_GPIO_MUXCFG_RFKILL 0x0008 332#define R92C_GPIO_MUXCFG_RFKILL 0x0008
333#define R92C_GPIO_MUXCFG_ENBT 0x0020 333#define R92C_GPIO_MUXCFG_ENBT 0x0020
334 334
335/* Bits for R92C_GPIO_IO_SEL. */ 335/* Bits for R92C_GPIO_IO_SEL. */
336#define R92C_GPIO_IO_SEL_RFKILL 0x0008 336#define R92C_GPIO_IO_SEL_RFKILL 0x0008
337 337
338/* Bits for R92C_LEDCFG0. */ 338/* Bits for R92C_LEDCFG0. */
339#define R92C_LEDCFG0_DIS 0x08 339#define R92C_LEDCFG0_DIS 0x08
340 340
341/* Bits for R92C_LEDCFG2. */ 341/* Bits for R92C_LEDCFG2. */
342#define R92C_LEDCFG2_EN 0x60 342#define R92C_LEDCFG2_EN 0x60
343#define R92C_LEDCFG2_DIS 0x68 343#define R92C_LEDCFG2_DIS 0x68
344 344
345/* Bits for R92C_MCUFWDL. */ 345/* Bits for R92C_MCUFWDL. */
346#define R92C_MCUFWDL_EN 0x00000001 346#define R92C_MCUFWDL_EN 0x00000001
347#define R92C_MCUFWDL_RDY 0x00000002 347#define R92C_MCUFWDL_RDY 0x00000002
348#define R92C_MCUFWDL_CHKSUM_RPT 0x00000004 348#define R92C_MCUFWDL_CHKSUM_RPT 0x00000004
349#define R92C_MCUFWDL_MACINI_RDY 0x00000008 349#define R92C_MCUFWDL_MACINI_RDY 0x00000008
350#define R92C_MCUFWDL_BBINI_RDY 0x00000010 350#define R92C_MCUFWDL_BBINI_RDY 0x00000010
351#define R92C_MCUFWDL_RFINI_RDY 0x00000020 351#define R92C_MCUFWDL_RFINI_RDY 0x00000020
352#define R92C_MCUFWDL_WINTINI_RDY 0x00000040 352#define R92C_MCUFWDL_WINTINI_RDY 0x00000040
353#define R92C_MCUFWDL_RAM_DL_SEL 0x00000080 /* 1: RAM, 0: ROM */ 353#define R92C_MCUFWDL_RAM_DL_SEL 0x00000080 /* 1: RAM, 0: ROM */
354#define R92C_MCUFWDL_PAGE_M 0x00070000 354#define R92C_MCUFWDL_PAGE_M 0x00070000
355#define R92C_MCUFWDL_PAGE_S 16 355#define R92C_MCUFWDL_PAGE_S 16
356#define R92C_MCUFWDL_CPRST 0x00800000 356#define R92C_MCUFWDL_CPRST 0x00800000
357 357
358/* Bits for R92C_HPON_FSM. */ 358/* Bits for R92C_HPON_FSM. */
359#define R92C_HPON_FSM_CHIP_BONDING_ID_S 22 359#define R92C_HPON_FSM_CHIP_BONDING_ID_S 22
360#define R92C_HPON_FSM_CHIP_BONDING_ID_M 0x00c00000 360#define R92C_HPON_FSM_CHIP_BONDING_ID_M 0x00c00000
361#define R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R 1 361#define R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R 1
362 362
363/* Bits for R92C_SYS_CFG. */ 363/* Bits for R92C_SYS_CFG. */
364#define R92C_SYS_CFG_XCLK_VLD 0x00000001 364#define R92C_SYS_CFG_XCLK_VLD 0x00000001
365#define R92C_SYS_CFG_ACLK_VLD 0x00000002 365#define R92C_SYS_CFG_ACLK_VLD 0x00000002
366#define R92C_SYS_CFG_UCLK_VLD 0x00000004 366#define R92C_SYS_CFG_UCLK_VLD 0x00000004
367#define R92C_SYS_CFG_PCLK_VLD 0x00000008 367#define R92C_SYS_CFG_PCLK_VLD 0x00000008
368#define R92C_SYS_CFG_PCIRSTB 0x00000010 368#define R92C_SYS_CFG_PCIRSTB 0x00000010
369#define R92C_SYS_CFG_V15_VLD 0x00000020 369#define R92C_SYS_CFG_V15_VLD 0x00000020
370#define R92C_SYS_CFG_TRP_B15V_EN 0x00000080 370#define R92C_SYS_CFG_TRP_B15V_EN 0x00000080
371#define R92C_SYS_CFG_SIC_IDLE 0x00000100 371#define R92C_SYS_CFG_SIC_IDLE 0x00000100
372#define R92C_SYS_CFG_BD_MAC2 0x00000200 372#define R92C_SYS_CFG_BD_MAC2 0x00000200
373#define R92C_SYS_CFG_BD_MAC1 0x00000400 373#define R92C_SYS_CFG_BD_MAC1 0x00000400
374#define R92C_SYS_CFG_IC_MACPHY_MODE 0x00000800 374#define R92C_SYS_CFG_IC_MACPHY_MODE 0x00000800
375#define R92C_SYS_CFG_CHIP_VER_RTL_M 0x0000f000 375#define R92C_SYS_CFG_CHIP_VER_RTL_M 0x0000f000
376#define R92C_SYS_CFG_CHIP_VER_RTL_S 12 376#define R92C_SYS_CFG_CHIP_VER_RTL_S 12
377#define R92C_SYS_CFG_BT_FUNC 0x00010000 377#define R92C_SYS_CFG_BT_FUNC 0x00010000
378#define R92C_SYS_CFG_VENDOR_UMC 0x00080000 378#define R92C_SYS_CFG_VENDOR_UMC 0x00080000
379#define R92C_SYS_CFG_PAD_HWPD_IDN 0x00400000 379#define R92C_SYS_CFG_PAD_HWPD_IDN 0x00400000
380#define R92C_SYS_CFG_TRP_VAUX_EN 0x00800000 380#define R92C_SYS_CFG_TRP_VAUX_EN 0x00800000
381#define R92C_SYS_CFG_TRP_BT_EN 0x01000000 381#define R92C_SYS_CFG_TRP_BT_EN 0x01000000
382#define R92C_SYS_CFG_BD_PKG_SEL 0x02000000 382#define R92C_SYS_CFG_BD_PKG_SEL 0x02000000
383#define R92C_SYS_CFG_BD_HCI_SEL 0x04000000 383#define R92C_SYS_CFG_BD_HCI_SEL 0x04000000
384#define R92C_SYS_CFG_TYPE_92C 0x08000000 384#define R92C_SYS_CFG_TYPE_92C 0x08000000
385 385
386/* Bits for R92C_CR. */ 386/* Bits for R92C_CR. */
387#define R92C_CR_HCI_TXDMA_EN 0x00000001 387#define R92C_CR_HCI_TXDMA_EN 0x00000001
388#define R92C_CR_HCI_RXDMA_EN 0x00000002 388#define R92C_CR_HCI_RXDMA_EN 0x00000002
389#define R92C_CR_TXDMA_EN 0x00000004 389#define R92C_CR_TXDMA_EN 0x00000004
390#define R92C_CR_RXDMA_EN 0x00000008 390#define R92C_CR_RXDMA_EN 0x00000008
391#define R92C_CR_PROTOCOL_EN 0x00000010 391#define R92C_CR_PROTOCOL_EN 0x00000010
392#define R92C_CR_SCHEDULE_EN 0x00000020 392#define R92C_CR_SCHEDULE_EN 0x00000020
393#define R92C_CR_MACTXEN 0x00000040 393#define R92C_CR_MACTXEN 0x00000040
394#define R92C_CR_MACRXEN 0x00000080 394#define R92C_CR_MACRXEN 0x00000080
395#define R92C_CR_ENSEC 0x00000200 395#define R92C_CR_ENSEC 0x00000200
396#define R92C_CR_NETTYPE_S 16 396#define R92C_CR_NETTYPE_S 16
397#define R92C_CR_NETTYPE_M 0x00030000 397#define R92C_CR_NETTYPE_M 0x00030000
398#define R92C_CR_NETTYPE_NOLINK 0 398#define R92C_CR_NETTYPE_NOLINK 0
399#define R92C_CR_NETTYPE_ADHOC 1 399#define R92C_CR_NETTYPE_ADHOC 1
400#define R92C_CR_NETTYPE_INFRA 2 400#define R92C_CR_NETTYPE_INFRA 2
401#define R92C_CR_NETTYPE_AP 3 401#define R92C_CR_NETTYPE_AP 3
402 402
403/* Bits for R92C_PBP. */ 403/* Bits for R92C_PBP. */
404#define R92C_PBP_PSRX_M 0x0f 404#define R92C_PBP_PSRX_M 0x0f
405#define R92C_PBP_PSRX_S 0 405#define R92C_PBP_PSRX_S 0
406#define R92C_PBP_PSTX_M 0xf0 406#define R92C_PBP_PSTX_M 0xf0
407#define R92C_PBP_PSTX_S 4 407#define R92C_PBP_PSTX_S 4
408#define R92C_PBP_64 0 408#define R92C_PBP_64 0
409#define R92C_PBP_128 1 409#define R92C_PBP_128 1
410#define R92C_PBP_256 2 410#define R92C_PBP_256 2
411#define R92C_PBP_512 3 411#define R92C_PBP_512 3
412#define R92C_PBP_1024 4 412#define R92C_PBP_1024 4
413 413
414/* Bits for R92C_TRXDMA_CTRL. */ 414/* Bits for R92C_TRXDMA_CTRL. */
415#define R92C_TRXDMA_CTRL_RXDMA_AGG_EN 0x0004 415#define R92C_TRXDMA_CTRL_RXDMA_AGG_EN 0x0004
416#define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_M 0x0030 416#define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_M 0x0030
417#define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_S 4 417#define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_S 4
418#define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_M 0x00c0 418#define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_M 0x00c0
419#define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_S 6 419#define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_S 6
420#define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_M 0x0300 420#define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_M 0x0300
421#define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_S 8 421#define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_S 8
422#define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_M 0x0c00 422#define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_M 0x0c00
423#define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_S 10 423#define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_S 10
424#define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_M 0x3000 424#define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_M 0x3000
425#define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_S 12 425#define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_S 12
426#define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_M 0xc000 426#define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_M 0xc000
427#define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_S 14 427#define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_S 14
428#define R92C_TRXDMA_CTRL_QUEUE_LOW 1 428#define R92C_TRXDMA_CTRL_QUEUE_LOW 1
429#define R92C_TRXDMA_CTRL_QUEUE_NORMAL 2 429#define R92C_TRXDMA_CTRL_QUEUE_NORMAL 2
430#define R92C_TRXDMA_CTRL_QUEUE_HIGH 3 430#define R92C_TRXDMA_CTRL_QUEUE_HIGH 3
431#define R92C_TRXDMA_CTRL_QMAP_M 0xfff0 431#define R92C_TRXDMA_CTRL_QMAP_M 0xfff0
432#define R92C_TRXDMA_CTRL_QMAP_S 4 432#define R92C_TRXDMA_CTRL_QMAP_S 4
433/* Shortcuts. */ 433/* Shortcuts. */
434#define R92C_TRXDMA_CTRL_QMAP_3EP 0xf5b0 434#define R92C_TRXDMA_CTRL_QMAP_3EP 0xf5b0
435#define R92C_TRXDMA_CTRL_QMAP_HQ_LQ 0xf5f0 435#define R92C_TRXDMA_CTRL_QMAP_HQ_LQ 0xf5f0
436#define R92C_TRXDMA_CTRL_QMAP_HQ_NQ 0xfaf0 436#define R92C_TRXDMA_CTRL_QMAP_HQ_NQ 0xfaf0
437#define R92C_TRXDMA_CTRL_QMAP_LQ 0x5550 437#define R92C_TRXDMA_CTRL_QMAP_LQ 0x5550
438#define R92C_TRXDMA_CTRL_QMAP_NQ 0xaaa0 438#define R92C_TRXDMA_CTRL_QMAP_NQ 0xaaa0
439#define R92C_TRXDMA_CTRL_QMAP_HQ 0xfff0 439#define R92C_TRXDMA_CTRL_QMAP_HQ 0xfff0
440 440
441/* Bits for R92C_LLT_INIT. */ 441/* Bits for R92C_LLT_INIT. */
442#define R92C_LLT_INIT_DATA_M 0x000000ff 442#define R92C_LLT_INIT_DATA_M 0x000000ff
443#define R92C_LLT_INIT_DATA_S 0 443#define R92C_LLT_INIT_DATA_S 0
444#define R92C_LLT_INIT_ADDR_M 0x0000ff00 444#define R92C_LLT_INIT_ADDR_M 0x0000ff00
445#define R92C_LLT_INIT_ADDR_S 8 445#define R92C_LLT_INIT_ADDR_S 8
446#define R92C_LLT_INIT_OP_M 0xc0000000 446#define R92C_LLT_INIT_OP_M 0xc0000000
447#define R92C_LLT_INIT_OP_S 30 447#define R92C_LLT_INIT_OP_S 30
448#define R92C_LLT_INIT_OP_NO_ACTIVE 0 448#define R92C_LLT_INIT_OP_NO_ACTIVE 0
449#define R92C_LLT_INIT_OP_WRITE 1 449#define R92C_LLT_INIT_OP_WRITE 1
450 450
451/* Bits for R92C_RQPN. */ 451/* Bits for R92C_RQPN. */
452#define R92C_RQPN_HPQ_M 0x000000ff 452#define R92C_RQPN_HPQ_M 0x000000ff
453#define R92C_RQPN_HPQ_S 0 453#define R92C_RQPN_HPQ_S 0
454#define R92C_RQPN_LPQ_M 0x0000ff00 454#define R92C_RQPN_LPQ_M 0x0000ff00
455#define R92C_RQPN_LPQ_S 8 455#define R92C_RQPN_LPQ_S 8
456#define R92C_RQPN_PUBQ_M 0x00ff0000 456#define R92C_RQPN_PUBQ_M 0x00ff0000
457#define R92C_RQPN_PUBQ_S 16 457#define R92C_RQPN_PUBQ_S 16
458#define R92C_RQPN_LD 0x80000000 458#define R92C_RQPN_LD 0x80000000
459 459
460/* Bits for R92C_TDECTRL. */ 460/* Bits for R92C_TDECTRL. */
461#define R92C_TDECTRL_BLK_DESC_NUM_M 0x0000000f 461#define R92C_TDECTRL_BLK_DESC_NUM_M 0x0000000f
462#define R92C_TDECTRL_BLK_DESC_NUM_S 4 462#define R92C_TDECTRL_BLK_DESC_NUM_S 4
463 463
464/* Bits for R92C_FWHW_TXQ_CTRL. */ 464/* Bits for R92C_FWHW_TXQ_CTRL. */
465#define R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW 0x80 465#define R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW 0x80
466 466
467/* Bits for R92C_SPEC_SIFS. */ 467/* Bits for R92C_SPEC_SIFS. */
468#define R92C_SPEC_SIFS_CCK_M 0x00ff 468#define R92C_SPEC_SIFS_CCK_M 0x00ff
469#define R92C_SPEC_SIFS_CCK_S 0 469#define R92C_SPEC_SIFS_CCK_S 0
470#define R92C_SPEC_SIFS_OFDM_M 0xff00 470#define R92C_SPEC_SIFS_OFDM_M 0xff00
471#define R92C_SPEC_SIFS_OFDM_S 8 471#define R92C_SPEC_SIFS_OFDM_S 8
472 472
473/* Bits for R92C_RL. */ 473/* Bits for R92C_RL. */
474#define R92C_RL_LRL_M 0x003f 474#define R92C_RL_LRL_M 0x003f
475#define R92C_RL_LRL_S 0 475#define R92C_RL_LRL_S 0
476#define R92C_RL_SRL_M 0x3f00 476#define R92C_RL_SRL_M 0x3f00
477#define R92C_RL_SRL_S 8 477#define R92C_RL_SRL_S 8
478 478
479/* Bits for R92C_RRSR. */ 479/* Bits for R92C_RRSR. */
480#define R92C_RRSR_RATE_BITMAP_M 0x000fffff 480#define R92C_RRSR_RATE_BITMAP_M 0x000fffff
481#define R92C_RRSR_RATE_BITMAP_S 0 481#define R92C_RRSR_RATE_BITMAP_S 0
482#define R92C_RRSR_RATE_CCK_ONLY_1M 0xffff1 482#define R92C_RRSR_RATE_CCK_ONLY_1M 0xffff1
483#define R92C_RRSR_RATE_ALL 0xfffff 483#define R92C_RRSR_RATE_ALL 0xfffff
484#define R92C_RRSR_RSC_LOWSUBCHNL 0x00200000 484#define R92C_RRSR_RSC_LOWSUBCHNL 0x00200000
485#define R92C_RRSR_RSC_UPSUBCHNL 0x00400000 485#define R92C_RRSR_RSC_UPSUBCHNL 0x00400000
486#define R92C_RRSR_SHORT 0x00800000 486#define R92C_RRSR_SHORT 0x00800000
487 487
488/* Bits for R92C_EDCA_XX_PARAM. */ 488/* Bits for R92C_EDCA_XX_PARAM. */
489#define R92C_EDCA_PARAM_AIFS_M 0x000000ff 489#define R92C_EDCA_PARAM_AIFS_M 0x000000ff
490#define R92C_EDCA_PARAM_AIFS_S 0 490#define R92C_EDCA_PARAM_AIFS_S 0
491#define R92C_EDCA_PARAM_ECWMIN_M 0x00000f00 491#define R92C_EDCA_PARAM_ECWMIN_M 0x00000f00
492#define R92C_EDCA_PARAM_ECWMIN_S 8 492#define R92C_EDCA_PARAM_ECWMIN_S 8
493#define R92C_EDCA_PARAM_ECWMAX_M 0x0000f000 493#define R92C_EDCA_PARAM_ECWMAX_M 0x0000f000
494#define R92C_EDCA_PARAM_ECWMAX_S 12 494#define R92C_EDCA_PARAM_ECWMAX_S 12
495#define R92C_EDCA_PARAM_TXOP_M 0xffff0000 495#define R92C_EDCA_PARAM_TXOP_M 0xffff0000
496#define R92C_EDCA_PARAM_TXOP_S 16 496#define R92C_EDCA_PARAM_TXOP_S 16
497 497
498/* Bits for R92C_TXPAUSE. */ 498/* Bits for R92C_TXPAUSE. */
499#define R92C_TXPAUSE_AC_VO 0x01 499#define R92C_TXPAUSE_AC_VO 0x01
500#define R92C_TXPAUSE_AC_VI 0x02 500#define R92C_TXPAUSE_AC_VI 0x02
501#define R92C_TXPAUSE_AC_BE 0x04 501#define R92C_TXPAUSE_AC_BE 0x04
502#define R92C_TXPAUSE_AC_BK 0x08 502#define R92C_TXPAUSE_AC_BK 0x08
503 503
504/* Bits for R92C_BCN_CTRL. */ 504/* Bits for R92C_BCN_CTRL. */
505#define R92C_BCN_CTRL_EN_MBSSID 0x02 505#define R92C_BCN_CTRL_EN_MBSSID 0x02
506#define R92C_BCN_CTRL_TXBCN_RPT 0x04 506#define R92C_BCN_CTRL_TXBCN_RPT 0x04
507#define R92C_BCN_CTRL_EN_BCN 0x08 507#define R92C_BCN_CTRL_EN_BCN 0x08
508#define R92C_BCN_CTRL_DIS_TSF_UDT0 0x10 508#define R92C_BCN_CTRL_DIS_TSF_UDT0 0x10
509 509
510/* Bits for R92C_APSD_CTRL. */ 510/* Bits for R92C_APSD_CTRL. */
511#define R92C_APSD_CTRL_OFF 0x40 511#define R92C_APSD_CTRL_OFF 0x40
512#define R92C_APSD_CTRL_OFF_STATUS 0x80 512#define R92C_APSD_CTRL_OFF_STATUS 0x80
513 513
514/* Bits for R92C_BWOPMODE. */ 514/* Bits for R92C_BWOPMODE. */
515#define R92C_BWOPMODE_11J 0x01 515#define R92C_BWOPMODE_11J 0x01
516#define R92C_BWOPMODE_5G 0x02 516#define R92C_BWOPMODE_5G 0x02
517#define R92C_BWOPMODE_20MHZ 0x04 517#define R92C_BWOPMODE_20MHZ 0x04
518 518
519/* Bits for R92C_TCR. */ 519/* Bits for R92C_TCR. */
520#define R92C_TCR_TSFRST 0x00000001 520#define R92C_TCR_TSFRST 0x00000001
521#define R92C_TCR_DIS_GCLK 0x00000002 521#define R92C_TCR_DIS_GCLK 0x00000002
522#define R92C_TCR_PAD_SEL 0x00000004 522#define R92C_TCR_PAD_SEL 0x00000004
523#define R92C_TCR_PWR_ST 0x00000040 523#define R92C_TCR_PWR_ST 0x00000040
524#define R92C_TCR_PWRBIT_OW_EN 0x00000080 524#define R92C_TCR_PWRBIT_OW_EN 0x00000080
525#define R92C_TCR_ACRC 0x00000100 525#define R92C_TCR_ACRC 0x00000100
526#define R92C_TCR_CFENDFORM 0x00000200 526#define R92C_TCR_CFENDFORM 0x00000200
527#define R92C_TCR_ICV 0x00000400 527#define R92C_TCR_ICV 0x00000400
528 528
529/* Bits for R92C_RCR. */ 529/* Bits for R92C_RCR. */
530#define R92C_RCR_AAP 0x00000001 530#define R92C_RCR_AAP 0x00000001
531#define R92C_RCR_APM 0x00000002 531#define R92C_RCR_APM 0x00000002
532#define R92C_RCR_AM 0x00000004 532#define R92C_RCR_AM 0x00000004
533#define R92C_RCR_AB 0x00000008 533#define R92C_RCR_AB 0x00000008
534#define R92C_RCR_ADD3 0x00000010 534#define R92C_RCR_ADD3 0x00000010
535#define R92C_RCR_APWRMGT 0x00000020 535#define R92C_RCR_APWRMGT 0x00000020
536#define R92C_RCR_CBSSID_DATA 0x00000040 536#define R92C_RCR_CBSSID_DATA 0x00000040
537#define R92C_RCR_CBSSID_BCN 0x00000080 537#define R92C_RCR_CBSSID_BCN 0x00000080
538#define R92C_RCR_ACRC32 0x00000100 538#define R92C_RCR_ACRC32 0x00000100
539#define R92C_RCR_AICV 0x00000200 539#define R92C_RCR_AICV 0x00000200
540#define R92C_RCR_ADF 0x00000800 540#define R92C_RCR_ADF 0x00000800
541#define R92C_RCR_ACF 0x00001000 541#define R92C_RCR_ACF 0x00001000
542#define R92C_RCR_AMF 0x00002000 542#define R92C_RCR_AMF 0x00002000
543#define R92C_RCR_HTC_LOC_CTRL 0x00004000 543#define R92C_RCR_HTC_LOC_CTRL 0x00004000
544#define R92C_RCR_MFBEN 0x00400000 544#define R92C_RCR_MFBEN 0x00400000
545#define R92C_RCR_LSIGEN 0x00800000 545#define R92C_RCR_LSIGEN 0x00800000
546#define R92C_RCR_ENMBID 0x01000000 546#define R92C_RCR_ENMBID 0x01000000
547#define R92C_RCR_APP_BA_SSN 0x08000000 547#define R92C_RCR_APP_BA_SSN 0x08000000
548#define R92C_RCR_APP_PHYSTS 0x10000000 548#define R92C_RCR_APP_PHYSTS 0x10000000
549#define R92C_RCR_APP_ICV 0x20000000 549#define R92C_RCR_APP_ICV 0x20000000
550#define R92C_RCR_APP_MIC 0x40000000 550#define R92C_RCR_APP_MIC 0x40000000
551#define R92C_RCR_APPFCS 0x80000000 551#define R92C_RCR_APPFCS 0x80000000
552 552
553/* Bits for R92C_CAMCMD. */ 553/* Bits for R92C_CAMCMD. */
554#define R92C_CAMCMD_ADDR_M 0x0000ffff 554#define R92C_CAMCMD_ADDR_M 0x0000ffff
555#define R92C_CAMCMD_ADDR_S 0 555#define R92C_CAMCMD_ADDR_S 0
556#define R92C_CAMCMD_WRITE 0x00010000 556#define R92C_CAMCMD_WRITE 0x00010000
557#define R92C_CAMCMD_CLR 0x40000000 557#define R92C_CAMCMD_CLR 0x40000000
558#define R92C_CAMCMD_POLLING 0x80000000 558#define R92C_CAMCMD_POLLING 0x80000000
559 559
560/* IMR */ 560/* IMR */
561 561
562/*Beacon DMA interrupt 6 */ 562/*Beacon DMA interrupt 6 */
563#define R92C_IMR_BCNDMAINT6 0x80000000 563#define R92C_IMR_BCNDMAINT6 0x80000000
564/*Beacon DMA interrupt 5 */ 564/*Beacon DMA interrupt 5 */
565#define R92C_IMR_BCNDMAINT5 0x40000000 565#define R92C_IMR_BCNDMAINT5 0x40000000
566/*Beacon DMA interrupt 4 */ 566/*Beacon DMA interrupt 4 */
567#define R92C_IMR_BCNDMAINT4 0x20000000 567#define R92C_IMR_BCNDMAINT4 0x20000000
568/*Beacon DMA interrupt 3 */ 568/*Beacon DMA interrupt 3 */
569#define R92C_IMR_BCNDMAINT3 0x10000000 569#define R92C_IMR_BCNDMAINT3 0x10000000
570/*Beacon DMA interrupt 2 */ 570/*Beacon DMA interrupt 2 */
571#define R92C_IMR_BCNDMAINT2 0x08000000 571#define R92C_IMR_BCNDMAINT2 0x08000000
572/*Beacon DMA interrupt 1 */ 572/*Beacon DMA interrupt 1 */
573#define R92C_IMR_BCNDMAINT1 0x04000000  573#define R92C_IMR_BCNDMAINT1 0x04000000
574/*Beacon Queue DMA OK interrupt 8 */ 574/*Beacon Queue DMA OK interrupt 8 */
575#define R92C_IMR_BCNDOK8 0x02000000 575#define R92C_IMR_BCNDOK8 0x02000000
576/*Beacon Queue DMA OK interrupt 7 */ 576/*Beacon Queue DMA OK interrupt 7 */
577#define R92C_IMR_BCNDOK7 0x01000000 577#define R92C_IMR_BCNDOK7 0x01000000
578/*Beacon Queue DMA OK interrupt 6 */ 578/*Beacon Queue DMA OK interrupt 6 */
579#define R92C_IMR_BCNDOK6 0x00800000 579#define R92C_IMR_BCNDOK6 0x00800000
580/*Beacon Queue DMA OK interrupt 5 */ 580/*Beacon Queue DMA OK interrupt 5 */
581#define R92C_IMR_BCNDOK5 0x00400000 581#define R92C_IMR_BCNDOK5 0x00400000
582/*Beacon Queue DMA OK interrupt 4 */ 582/*Beacon Queue DMA OK interrupt 4 */
583#define R92C_IMR_BCNDOK4 0x00200000 583#define R92C_IMR_BCNDOK4 0x00200000
584/*Beacon Queue DMA OK interrupt 3 */ 584/*Beacon Queue DMA OK interrupt 3 */
585#define R92C_IMR_BCNDOK3 0x00100000 585#define R92C_IMR_BCNDOK3 0x00100000
586/*Beacon Queue DMA OK interrupt 2 */ 586/*Beacon Queue DMA OK interrupt 2 */
587#define R92C_IMR_BCNDOK2 0x00080000 587#define R92C_IMR_BCNDOK2 0x00080000
588/*Beacon Queue DMA OK interrupt 1 */ 588/*Beacon Queue DMA OK interrupt 1 */
589#define R92C_IMR_BCNDOK1 0x00040000 589#define R92C_IMR_BCNDOK1 0x00040000
590/*Timeout interrupt 2 */ 590/*Timeout interrupt 2 */
591#define R92C_IMR_TIMEOUT2 0x00020000 591#define R92C_IMR_TIMEOUT2 0x00020000
592/*Timeout interrupt 1 */ 592/*Timeout interrupt 1 */
593#define R92C_IMR_TIMEOUT1 0x00010000 593#define R92C_IMR_TIMEOUT1 0x00010000
594/*Transmit FIFO Overflow */ 594/*Transmit FIFO Overflow */
595#define R92C_IMR_TXFOVW 0x00008000 595#define R92C_IMR_TXFOVW 0x00008000
596/*Power save time out interrupt */ 596/*Power save time out interrupt */
597#define R92C_IMR_PSTIMEOUT 0x00004000 597#define R92C_IMR_PSTIMEOUT 0x00004000
598/*Beacon DMA interrupt 0 */ 598/*Beacon DMA interrupt 0 */
599#define R92C_IMR_BCNINT 0x00002000 599#define R92C_IMR_BCNINT 0x00002000
600/*Receive FIFO Overflow */ 600/*Receive FIFO Overflow */
601#define R92C_IMR_RXFOVW 0x00001000 601#define R92C_IMR_RXFOVW 0x00001000
602/*Receive Descriptor Unavailable */ 602/*Receive Descriptor Unavailable */
603#define R92C_IMR_RDU 0x00000800 603#define R92C_IMR_RDU 0x00000800
604/*For 92C,ATIM Window End interrupt */ 604/*For 92C,ATIM Window End interrupt */
605#define R92C_IMR_ATIMEND 0x00000400 605#define R92C_IMR_ATIMEND 0x00000400
606/*Beacon Queue DMA OK interrupt */ 606/*Beacon Queue DMA OK interrupt */
607#define R92C_IMR_BDOK 0x00000200 607#define R92C_IMR_BDOK 0x00000200
608/*High Queue DMA OK interrupt */ 608/*High Queue DMA OK interrupt */
609#define R92C_IMR_HIGHDOK 0x00000100 609#define R92C_IMR_HIGHDOK 0x00000100
610/*Transmit Beacon OK interrupt */ 610/*Transmit Beacon OK interrupt */
611#define R92C_IMR_TBDOK 0x00000080 611#define R92C_IMR_TBDOK 0x00000080
612/*Management Queue DMA OK interrupt */ 612/*Management Queue DMA OK interrupt */
613#define R92C_IMR_MGNTDOK 0x00000040 613#define R92C_IMR_MGNTDOK 0x00000040
614/*For 92C,Transmit Beacon Error interrupt */ 614/*For 92C,Transmit Beacon Error interrupt */
615#define R92C_IMR_TBDER 0x00000020 615#define R92C_IMR_TBDER 0x00000020
616/*AC_BK DMA OK interrupt */ 616/*AC_BK DMA OK interrupt */
617#define R92C_IMR_BKDOK 0x00000010 617#define R92C_IMR_BKDOK 0x00000010
618/*AC_BE DMA OK interrupt */ 618/*AC_BE DMA OK interrupt */
619#define R92C_IMR_BEDOK 0x00000008 619#define R92C_IMR_BEDOK 0x00000008
620/*AC_VI DMA OK interrupt */ 620/*AC_VI DMA OK interrupt */
621#define R92C_IMR_VIDOK 0x00000004 621#define R92C_IMR_VIDOK 0x00000004
622/*AC_VO DMA interrupt */ 622/*AC_VO DMA interrupt */
623#define R92C_IMR_VODOK 0x00000002 623#define R92C_IMR_VODOK 0x00000002
624/*Receive DMA OK interrupt */ 624/*Receive DMA OK interrupt */
625#define R92C_IMR_ROK 0x00000001 625#define R92C_IMR_ROK 0x00000001
626 626
627#define R92C_IBSS_INT_MASK (R92C_IMR_BCNINT | R92C_IMR_TBDOK | R92C_IMR_TBDER) 627#define R92C_IBSS_INT_MASK (R92C_IMR_BCNINT | R92C_IMR_TBDOK | R92C_IMR_TBDER)
628 628
629/* 629/*
630 * Baseband registers. 630 * Baseband registers.
631 */ 631 */
632#define R92C_FPGA0_RFMOD 0x800 632#define R92C_FPGA0_RFMOD 0x800
633#define R92C_FPGA0_TXINFO 0x804 633#define R92C_FPGA0_TXINFO 0x804
634#define R92C_HSSI_PARAM1(chain) (0x820 + (chain) * 8) 634#define R92C_HSSI_PARAM1(chain) (0x820 + (chain) * 8)
635#define R92C_HSSI_PARAM2(chain) (0x824 + (chain) * 8) 635#define R92C_HSSI_PARAM2(chain) (0x824 + (chain) * 8)
636#define R92C_TXAGC_RATE18_06(i) (((i) == 0) ? 0xe00 : 0x830) 636#define R92C_TXAGC_RATE18_06(i) (((i) == 0) ? 0xe00 : 0x830)
637#define R92C_TXAGC_RATE54_24(i) (((i) == 0) ? 0xe04 : 0x834) 637#define R92C_TXAGC_RATE54_24(i) (((i) == 0) ? 0xe04 : 0x834)
638#define R92C_TXAGC_A_CCK1_MCS32 0xe08 638#define R92C_TXAGC_A_CCK1_MCS32 0xe08
639#define R92C_TXAGC_B_CCK1_55_MCS32 0x838 639#define R92C_TXAGC_B_CCK1_55_MCS32 0x838
640#define R92C_TXAGC_B_CCK11_A_CCK2_11 0x86c 640#define R92C_TXAGC_B_CCK11_A_CCK2_11 0x86c
641#define R92C_TXAGC_MCS03_MCS00(i) (((i) == 0) ? 0xe10 : 0x83c) 641#define R92C_TXAGC_MCS03_MCS00(i) (((i) == 0) ? 0xe10 : 0x83c)
642#define R92C_TXAGC_MCS07_MCS04(i) (((i) == 0) ? 0xe14 : 0x848) 642#define R92C_TXAGC_MCS07_MCS04(i) (((i) == 0) ? 0xe14 : 0x848)
643#define R92C_TXAGC_MCS11_MCS08(i) (((i) == 0) ? 0xe18 : 0x84c) 643#define R92C_TXAGC_MCS11_MCS08(i) (((i) == 0) ? 0xe18 : 0x84c)
644#define R92C_TXAGC_MCS15_MCS12(i) (((i) == 0) ? 0xe1c : 0x868) 644#define R92C_TXAGC_MCS15_MCS12(i) (((i) == 0) ? 0xe1c : 0x868)
645#define R92C_LSSI_PARAM(chain) (0x840 + (chain) * 4) 645#define R92C_LSSI_PARAM(chain) (0x840 + (chain) * 4)
646#define R92C_FPGA0_RFIFACEOE(chain) (0x860 + (chain) * 4) 646#define R92C_FPGA0_RFIFACEOE(chain) (0x860 + (chain) * 4)
647#define R92C_FPGA0_RFIFACESW(idx) (0x870 + (idx) * 4) 647#define R92C_FPGA0_RFIFACESW(idx) (0x870 + (idx) * 4)
648#define R92C_FPGA0_RFPARAM(idx) (0x878 + (idx) * 4) 648#define R92C_FPGA0_RFPARAM(idx) (0x878 + (idx) * 4)
649#define R92C_FPGA0_ANAPARAM2 0x884 649#define R92C_FPGA0_ANAPARAM2 0x884
650#define R92C_LSSI_READBACK(chain) (0x8a0 + (chain) * 4) 650#define R92C_LSSI_READBACK(chain) (0x8a0 + (chain) * 4)
651#define R92C_HSPI_READBACK(chain) (0x8b8 + (chain) * 4) 651#define R92C_HSPI_READBACK(chain) (0x8b8 + (chain) * 4)
652#define R92C_FPGA1_RFMOD 0x900 652#define R92C_FPGA1_RFMOD 0x900
653#define R92C_FPGA1_TXINFO 0x90c 653#define R92C_FPGA1_TXINFO 0x90c
654#define R92C_CCK0_SYSTEM 0xa00 654#define R92C_CCK0_SYSTEM 0xa00
655#define R92C_CCK0_AFESETTING 0xa04 655#define R92C_CCK0_AFESETTING 0xa04
656#define R92C_OFDM0_TRXPATHENA 0xc04 656#define R92C_OFDM0_TRXPATHENA 0xc04
657#define R92C_OFDM0_TRMUXPAR 0xc08 657#define R92C_OFDM0_TRMUXPAR 0xc08
658#define R92C_OFDM0_RXIQIMBALANCE(chain) (0xc14 + (chain) * 8) 658#define R92C_OFDM0_RXIQIMBALANCE(chain) (0xc14 + (chain) * 8)
659#define R92C_OFDM0_ECCATHRESHOLD 0xc4c 659#define R92C_OFDM0_ECCATHRESHOLD 0xc4c
660#define R92C_OFDM0_AGCCORE1(chain) (0xc50 + (chain) * 8) 660#define R92C_OFDM0_AGCCORE1(chain) (0xc50 + (chain) * 8)
661#define R92C_OFDM0_AGCPARAM1 0xc70 661#define R92C_OFDM0_AGCPARAM1 0xc70
662#define R92C_OFDM0_AGCRSSITABLE 0xc78 662#define R92C_OFDM0_AGCRSSITABLE 0xc78
663#define R92C_OFDM0_TXIQIMBALANCE(chain) (0xc80 + (chain) * 8) 663#define R92C_OFDM0_TXIQIMBALANCE(chain) (0xc80 + (chain) * 8)
664#define R92C_OFDM0_TXAFE(chain) (0xc94 + (chain) * 8) 664#define R92C_OFDM0_TXAFE(chain) (0xc94 + (chain) * 8)
665#define R92C_OFDM0_RXIQEXTANTA 0xca0 665#define R92C_OFDM0_RXIQEXTANTA 0xca0
666#define R92C_OFDM1_LSTF 0xd00 666#define R92C_OFDM1_LSTF 0xd00
667 667
668/* Bits for R92C_FPGA[01]_RFMOD. */ 668/* Bits for R92C_FPGA[01]_RFMOD. */
669#define R92C_RFMOD_40MHZ 0x00000001 669#define R92C_RFMOD_40MHZ 0x00000001
670#define R92C_RFMOD_JAPAN 0x00000002 670#define R92C_RFMOD_JAPAN 0x00000002
671#define R92C_RFMOD_CCK_TXSC 0x00000030 671#define R92C_RFMOD_CCK_TXSC 0x00000030
672#define R92C_RFMOD_CCK_EN 0x01000000 672#define R92C_RFMOD_CCK_EN 0x01000000
673#define R92C_RFMOD_OFDM_EN 0x02000000 673#define R92C_RFMOD_OFDM_EN 0x02000000
674 674
675/* Bits for R92C_HSSI_PARAM1(i). */ 675/* Bits for R92C_HSSI_PARAM1(i). */
676#define R92C_HSSI_PARAM1_PI 0x00000100 676#define R92C_HSSI_PARAM1_PI 0x00000100
677 677
678/* Bits for R92C_HSSI_PARAM2(i). */ 678/* Bits for R92C_HSSI_PARAM2(i). */
679#define R92C_HSSI_PARAM2_CCK_HIPWR 0x00000200 679#define R92C_HSSI_PARAM2_CCK_HIPWR 0x00000200
680#define R92C_HSSI_PARAM2_ADDR_LENGTH 0x00000400 680#define R92C_HSSI_PARAM2_ADDR_LENGTH 0x00000400
681#define R92C_HSSI_PARAM2_DATA_LENGTH 0x00000800 681#define R92C_HSSI_PARAM2_DATA_LENGTH 0x00000800
682#define R92C_HSSI_PARAM2_READ_ADDR_M 0x7f800000 682#define R92C_HSSI_PARAM2_READ_ADDR_M 0x7f800000
683#define R92C_HSSI_PARAM2_READ_ADDR_S 23 683#define R92C_HSSI_PARAM2_READ_ADDR_S 23
684#define R92C_HSSI_PARAM2_READ_EDGE 0x80000000 684#define R92C_HSSI_PARAM2_READ_EDGE 0x80000000
685 685
686/* Bits for R92C_TXAGC_A_CCK1_MCS32. */ 686/* Bits for R92C_TXAGC_A_CCK1_MCS32. */
687#define R92C_TXAGC_A_CCK1_M 0x0000ff00 687#define R92C_TXAGC_A_CCK1_M 0x0000ff00
688#define R92C_TXAGC_A_CCK1_S 8 688#define R92C_TXAGC_A_CCK1_S 8
689 689
690/* Bits for R92C_TXAGC_B_CCK11_A_CCK2_11. */ 690/* Bits for R92C_TXAGC_B_CCK11_A_CCK2_11. */
691#define R92C_TXAGC_B_CCK11_M 0x000000ff 691#define R92C_TXAGC_B_CCK11_M 0x000000ff
692#define R92C_TXAGC_B_CCK11_S 0 692#define R92C_TXAGC_B_CCK11_S 0
693#define R92C_TXAGC_A_CCK2_M 0x0000ff00 693#define R92C_TXAGC_A_CCK2_M 0x0000ff00
694#define R92C_TXAGC_A_CCK2_S 8 694#define R92C_TXAGC_A_CCK2_S 8
695#define R92C_TXAGC_A_CCK55_M 0x00ff0000 695#define R92C_TXAGC_A_CCK55_M 0x00ff0000
696#define R92C_TXAGC_A_CCK55_S 16 696#define R92C_TXAGC_A_CCK55_S 16
697#define R92C_TXAGC_A_CCK11_M 0xff000000 697#define R92C_TXAGC_A_CCK11_M 0xff000000
698#define R92C_TXAGC_A_CCK11_S 24 698#define R92C_TXAGC_A_CCK11_S 24
699 699
700/* Bits for R92C_TXAGC_B_CCK1_55_MCS32. */ 700/* Bits for R92C_TXAGC_B_CCK1_55_MCS32. */
701#define R92C_TXAGC_B_CCK1_M 0x0000ff00 701#define R92C_TXAGC_B_CCK1_M 0x0000ff00
702#define R92C_TXAGC_B_CCK1_S 8 702#define R92C_TXAGC_B_CCK1_S 8
703#define R92C_TXAGC_B_CCK2_M 0x00ff0000 703#define R92C_TXAGC_B_CCK2_M 0x00ff0000
704#define R92C_TXAGC_B_CCK2_S 16 704#define R92C_TXAGC_B_CCK2_S 16
705#define R92C_TXAGC_B_CCK55_M 0xff000000 705#define R92C_TXAGC_B_CCK55_M 0xff000000
706#define R92C_TXAGC_B_CCK55_S 24 706#define R92C_TXAGC_B_CCK55_S 24
707 707
708/* Bits for R92C_TXAGC_RATE18_06(x). */ 708/* Bits for R92C_TXAGC_RATE18_06(x). */
709#define R92C_TXAGC_RATE06_M 0x000000ff 709#define R92C_TXAGC_RATE06_M 0x000000ff
710#define R92C_TXAGC_RATE06_S 0 710#define R92C_TXAGC_RATE06_S 0
711#define R92C_TXAGC_RATE09_M 0x0000ff00 711#define R92C_TXAGC_RATE09_M 0x0000ff00
712#define R92C_TXAGC_RATE09_S 8 712#define R92C_TXAGC_RATE09_S 8
713#define R92C_TXAGC_RATE12_M 0x00ff0000 713#define R92C_TXAGC_RATE12_M 0x00ff0000
714#define R92C_TXAGC_RATE12_S 16 714#define R92C_TXAGC_RATE12_S 16
715#define R92C_TXAGC_RATE18_M 0xff000000 715#define R92C_TXAGC_RATE18_M 0xff000000
716#define R92C_TXAGC_RATE18_S 24 716#define R92C_TXAGC_RATE18_S 24
717 717
718/* Bits for R92C_TXAGC_RATE54_24(x). */ 718/* Bits for R92C_TXAGC_RATE54_24(x). */
719#define R92C_TXAGC_RATE24_M 0x000000ff 719#define R92C_TXAGC_RATE24_M 0x000000ff
720#define R92C_TXAGC_RATE24_S 0 720#define R92C_TXAGC_RATE24_S 0
721#define R92C_TXAGC_RATE36_M 0x0000ff00 721#define R92C_TXAGC_RATE36_M 0x0000ff00
722#define R92C_TXAGC_RATE36_S 8 722#define R92C_TXAGC_RATE36_S 8
723#define R92C_TXAGC_RATE48_M 0x00ff0000 723#define R92C_TXAGC_RATE48_M 0x00ff0000
724#define R92C_TXAGC_RATE48_S 16 724#define R92C_TXAGC_RATE48_S 16
725#define R92C_TXAGC_RATE54_M 0xff000000 725#define R92C_TXAGC_RATE54_M 0xff000000
726#define R92C_TXAGC_RATE54_S 24 726#define R92C_TXAGC_RATE54_S 24
727 727
728/* Bits for R92C_TXAGC_MCS03_MCS00(x). */ 728/* Bits for R92C_TXAGC_MCS03_MCS00(x). */
729#define R92C_TXAGC_MCS00_M 0x000000ff 729#define R92C_TXAGC_MCS00_M 0x000000ff
730#define R92C_TXAGC_MCS00_S 0 730#define R92C_TXAGC_MCS00_S 0
731#define R92C_TXAGC_MCS01_M 0x0000ff00 731#define R92C_TXAGC_MCS01_M 0x0000ff00
732#define R92C_TXAGC_MCS01_S 8 732#define R92C_TXAGC_MCS01_S 8
733#define R92C_TXAGC_MCS02_M 0x00ff0000 733#define R92C_TXAGC_MCS02_M 0x00ff0000
734#define R92C_TXAGC_MCS02_S 16 734#define R92C_TXAGC_MCS02_S 16
735#define R92C_TXAGC_MCS03_M 0xff000000 735#define R92C_TXAGC_MCS03_M 0xff000000
736#define R92C_TXAGC_MCS03_S 24 736#define R92C_TXAGC_MCS03_S 24
737 737
738/* Bits for R92C_TXAGC_MCS07_MCS04(x). */ 738/* Bits for R92C_TXAGC_MCS07_MCS04(x). */
739#define R92C_TXAGC_MCS04_M 0x000000ff 739#define R92C_TXAGC_MCS04_M 0x000000ff
740#define R92C_TXAGC_MCS04_S 0 740#define R92C_TXAGC_MCS04_S 0
741#define R92C_TXAGC_MCS05_M 0x0000ff00 741#define R92C_TXAGC_MCS05_M 0x0000ff00
742#define R92C_TXAGC_MCS05_S 8 742#define R92C_TXAGC_MCS05_S 8
743#define R92C_TXAGC_MCS06_M 0x00ff0000 743#define R92C_TXAGC_MCS06_M 0x00ff0000
744#define R92C_TXAGC_MCS06_S 16 744#define R92C_TXAGC_MCS06_S 16
745#define R92C_TXAGC_MCS07_M 0xff000000 745#define R92C_TXAGC_MCS07_M 0xff000000
746#define R92C_TXAGC_MCS07_S 24 746#define R92C_TXAGC_MCS07_S 24
747 747
748/* Bits for R92C_TXAGC_MCS11_MCS08(x). */ 748/* Bits for R92C_TXAGC_MCS11_MCS08(x). */
749#define R92C_TXAGC_MCS08_M 0x000000ff 749#define R92C_TXAGC_MCS08_M 0x000000ff
750#define R92C_TXAGC_MCS08_S 0 750#define R92C_TXAGC_MCS08_S 0
751#define R92C_TXAGC_MCS09_M 0x0000ff00 751#define R92C_TXAGC_MCS09_M 0x0000ff00
752#define R92C_TXAGC_MCS09_S 8 752#define R92C_TXAGC_MCS09_S 8
753#define R92C_TXAGC_MCS10_M 0x00ff0000 753#define R92C_TXAGC_MCS10_M 0x00ff0000
754#define R92C_TXAGC_MCS10_S 16 754#define R92C_TXAGC_MCS10_S 16
755#define R92C_TXAGC_MCS11_M 0xff000000 755#define R92C_TXAGC_MCS11_M 0xff000000
756#define R92C_TXAGC_MCS11_S 24 756#define R92C_TXAGC_MCS11_S 24
757 757
758/* Bits for R92C_TXAGC_MCS15_MCS12(x). */ 758/* Bits for R92C_TXAGC_MCS15_MCS12(x). */
759#define R92C_TXAGC_MCS12_M 0x000000ff 759#define R92C_TXAGC_MCS12_M 0x000000ff
760#define R92C_TXAGC_MCS12_S 0 760#define R92C_TXAGC_MCS12_S 0
761#define R92C_TXAGC_MCS13_M 0x0000ff00 761#define R92C_TXAGC_MCS13_M 0x0000ff00
762#define R92C_TXAGC_MCS13_S 8 762#define R92C_TXAGC_MCS13_S 8
763#define R92C_TXAGC_MCS14_M 0x00ff0000 763#define R92C_TXAGC_MCS14_M 0x00ff0000
764#define R92C_TXAGC_MCS14_S 16 764#define R92C_TXAGC_MCS14_S 16
765#define R92C_TXAGC_MCS15_M 0xff000000 765#define R92C_TXAGC_MCS15_M 0xff000000
766#define R92C_TXAGC_MCS15_S 24 766#define R92C_TXAGC_MCS15_S 24
767 767
768/* Bits for R92C_LSSI_PARAM(i). */ 768/* Bits for R92C_LSSI_PARAM(i). */
769#define R92C_LSSI_PARAM_DATA_M 0x000fffff 769#define R92C_LSSI_PARAM_DATA_M 0x000fffff
770#define R92C_LSSI_PARAM_DATA_S 0 770#define R92C_LSSI_PARAM_DATA_S 0
771#define R92C_LSSI_PARAM_ADDR_M 0x03f00000 771#define R92C_LSSI_PARAM_ADDR_M 0x03f00000
772#define R92C_LSSI_PARAM_ADDR_S 20 772#define R92C_LSSI_PARAM_ADDR_S 20
773 773
774/* Bits for R92C_FPGA0_ANAPARAM2. */ 774/* Bits for R92C_FPGA0_ANAPARAM2. */
775#define R92C_FPGA0_ANAPARAM2_CBW20 0x00000400 775#define R92C_FPGA0_ANAPARAM2_CBW20 0x00000400
776 776
777/* Bits for R92C_LSSI_READBACK(i). */ 777/* Bits for R92C_LSSI_READBACK(i). */
778#define R92C_LSSI_READBACK_DATA_M 0x000fffff 778#define R92C_LSSI_READBACK_DATA_M 0x000fffff
779#define R92C_LSSI_READBACK_DATA_S 0 779#define R92C_LSSI_READBACK_DATA_S 0
780 780
781/* Bits for R92C_OFDM0_AGCCORE1(i). */ 781/* Bits for R92C_OFDM0_AGCCORE1(i). */
782#define R92C_OFDM0_AGCCORE1_GAIN_M 0x0000007f 782#define R92C_OFDM0_AGCCORE1_GAIN_M 0x0000007f
783#define R92C_OFDM0_AGCCORE1_GAIN_S 0 783#define R92C_OFDM0_AGCCORE1_GAIN_S 0
784 784
785 785
786/* 786/*
787 * USB registers. 787 * USB registers.
788 */ 788 */
789#define R92C_USB_INFO 0xfe17 789#define R92C_USB_INFO 0xfe17
790#define R92C_USB_SPECIAL_OPTION 0xfe55 790#define R92C_USB_SPECIAL_OPTION 0xfe55
791#define R92C_USB_HCPWM 0xfe57 791#define R92C_USB_HCPWM 0xfe57
792#define R92C_USB_HRPWM 0xfe58 792#define R92C_USB_HRPWM 0xfe58
793#define R92C_USB_DMA_AGG_TO 0xfe5b 793#define R92C_USB_DMA_AGG_TO 0xfe5b
794#define R92C_USB_AGG_TO 0xfe5c 794#define R92C_USB_AGG_TO 0xfe5c
795#define R92C_USB_AGG_TH 0xfe5d 795#define R92C_USB_AGG_TH 0xfe5d
796#define R92C_USB_VID 0xfe60 796#define R92C_USB_VID 0xfe60
797#define R92C_USB_PID 0xfe62 797#define R92C_USB_PID 0xfe62
798#define R92C_USB_OPTIONAL 0xfe64 798#define R92C_USB_OPTIONAL 0xfe64
799#define R92C_USB_EP 0xfe65 799#define R92C_USB_EP 0xfe65
800#define R92C_USB_PHY 0xfe68 800#define R92C_USB_PHY 0xfe68
801#define R92C_USB_MAC_ADDR 0xfe70 801#define R92C_USB_MAC_ADDR 0xfe70
802#define R92C_USB_STRING 0xfe80 802#define R92C_USB_STRING 0xfe80
803 803
804/* Bits for R92C_USB_SPECIAL_OPTION. */ 804/* Bits for R92C_USB_SPECIAL_OPTION. */
805#define R92C_USB_SPECIAL_OPTION_AGG_EN 0x08 805#define R92C_USB_SPECIAL_OPTION_AGG_EN 0x08
806 806
807/* Bits for R92C_USB_EP. */ 807/* Bits for R92C_USB_EP. */
808#define R92C_USB_EP_HQ_M 0x000f 808#define R92C_USB_EP_HQ_M 0x000f
809#define R92C_USB_EP_HQ_S 0 809#define R92C_USB_EP_HQ_S 0
810#define R92C_USB_EP_NQ_M 0x00f0 810#define R92C_USB_EP_NQ_M 0x00f0
811#define R92C_USB_EP_NQ_S 4 811#define R92C_USB_EP_NQ_S 4
812#define R92C_USB_EP_LQ_M 0x0f00 812#define R92C_USB_EP_LQ_M 0x0f00
813#define R92C_USB_EP_LQ_S 8 813#define R92C_USB_EP_LQ_S 8
814 814
815 815
816/* 816/*
817 * Firmware base address. 817 * Firmware base address.
818 */ 818 */
819#define R92C_FW_START_ADDR 0x1000 819#define R92C_FW_START_ADDR 0x1000
820#define R92C_FW_PAGE_SIZE 4096 820#define R92C_FW_PAGE_SIZE 4096
821 821
822 822
823/* 823/*
824 * RF (6052) registers. 824 * RF (6052) registers.
825 */ 825 */
826#define R92C_RF_AC 0x00 826#define R92C_RF_AC 0x00
827#define R92C_RF_IQADJ_G(i) (0x01 + (i)) 827#define R92C_RF_IQADJ_G(i) (0x01 + (i))
828#define R92C_RF_POW_TRSW 0x05 828#define R92C_RF_POW_TRSW 0x05
829#define R92C_RF_GAIN_RX 0x06 829#define R92C_RF_GAIN_RX 0x06
830#define R92C_RF_GAIN_TX 0x07 830#define R92C_RF_GAIN_TX 0x07
831#define R92C_RF_TXM_IDAC 0x08 831#define R92C_RF_TXM_IDAC 0x08
832#define R92C_RF_BS_IQGEN 0x0f 832#define R92C_RF_BS_IQGEN 0x0f
833#define R92C_RF_MODE1 0x10 833#define R92C_RF_MODE1 0x10
834#define R92C_RF_MODE2 0x11 834#define R92C_RF_MODE2 0x11
835#define R92C_RF_RX_AGC_HP 0x12 835#define R92C_RF_RX_AGC_HP 0x12
836#define R92C_RF_TX_AGC 0x13 836#define R92C_RF_TX_AGC 0x13
837#define R92C_RF_BIAS 0x14 837#define R92C_RF_BIAS 0x14
838#define R92C_RF_IPA 0x15 838#define R92C_RF_IPA 0x15
839#define R92C_RF_POW_ABILITY 0x17 839#define R92C_RF_POW_ABILITY 0x17
840#define R92C_RF_CHNLBW 0x18 840#define R92C_RF_CHNLBW 0x18
841#define R92C_RF_RX_G1 0x1a 841#define R92C_RF_RX_G1 0x1a
842#define R92C_RF_RX_G2 0x1b 842#define R92C_RF_RX_G2 0x1b
843#define R92C_RF_RX_BB2 0x1c 843#define R92C_RF_RX_BB2 0x1c
844#define R92C_RF_RX_BB1 0x1d 844#define R92C_RF_RX_BB1 0x1d
845#define R92C_RF_RCK1 0x1e 845#define R92C_RF_RCK1 0x1e
846#define R92C_RF_RCK2 0x1f 846#define R92C_RF_RCK2 0x1f
847#define R92C_RF_TX_G(i) (0x20 + (i)) 847#define R92C_RF_TX_G(i) (0x20 + (i))
848#define R92C_RF_TX_BB1 0x23 848#define R92C_RF_TX_BB1 0x23
849#define R92C_RF_T_METER 0x24 849#define R92C_RF_T_METER 0x24
850#define R92C_RF_SYN_G(i) (0x25 + (i)) 850#define R92C_RF_SYN_G(i) (0x25 + (i))
851#define R92C_RF_RCK_OS 0x30 851#define R92C_RF_RCK_OS 0x30
852#define R92C_RF_TXPA_G(i) (0x31 + (i)) 852#define R92C_RF_TXPA_G(i) (0x31 + (i))
853 853
854/* Bits for R92C_RF_AC. */ 854/* Bits for R92C_RF_AC. */
855#define R92C_RF_AC_MODE_M 0x70000 855#define R92C_RF_AC_MODE_M 0x70000
856#define R92C_RF_AC_MODE_S 16 856#define R92C_RF_AC_MODE_S 16
857#define R92C_RF_AC_MODE_STANDBY 1 857#define R92C_RF_AC_MODE_STANDBY 1
858 858
859/* Bits for R92C_RF_CHNLBW. */ 859/* Bits for R92C_RF_CHNLBW. */
860#define R92C_RF_CHNLBW_CHNL_M 0x003ff 860#define R92C_RF_CHNLBW_CHNL_M 0x003ff
861#define R92C_RF_CHNLBW_CHNL_S 0 861#define R92C_RF_CHNLBW_CHNL_S 0
862#define R92C_RF_CHNLBW_BW20 0x00400 862#define R92C_RF_CHNLBW_BW20 0x00400
863#define R92C_RF_CHNLBW_LCSTART 0x08000 863#define R92C_RF_CHNLBW_LCSTART 0x08000
864 864
865 865
866/* 866/*
867 * CAM entries. 867 * CAM entries.
868 */ 868 */
869#define R92C_CAM_ENTRY_COUNT 32 869#define R92C_CAM_ENTRY_COUNT 32
870 870
871#define R92C_CAM_CTL0(entry) ((entry) * 8 + 0) 871#define R92C_CAM_CTL0(entry) ((entry) * 8 + 0)
872#define R92C_CAM_CTL1(entry) ((entry) * 8 + 1) 872#define R92C_CAM_CTL1(entry) ((entry) * 8 + 1)
873#define R92C_CAM_KEY(entry, i) ((entry) * 8 + 2 + (i)) 873#define R92C_CAM_KEY(entry, i) ((entry) * 8 + 2 + (i))
874 874
875/* Bits for R92C_CAM_CTL0(i). */ 875/* Bits for R92C_CAM_CTL0(i). */
876#define R92C_CAM_KEYID_M 0x00000003 876#define R92C_CAM_KEYID_M 0x00000003
877#define R92C_CAM_KEYID_S 0 877#define R92C_CAM_KEYID_S 0
878#define R92C_CAM_ALGO_M 0x0000001c 878#define R92C_CAM_ALGO_M 0x0000001c
879#define R92C_CAM_ALGO_S 2 879#define R92C_CAM_ALGO_S 2
880#define R92C_CAM_ALGO_NONE 0 880#define R92C_CAM_ALGO_NONE 0
881#define R92C_CAM_ALGO_WEP40 1 881#define R92C_CAM_ALGO_WEP40 1
882#define R92C_CAM_ALGO_TKIP 2 882#define R92C_CAM_ALGO_TKIP 2
883#define R92C_CAM_ALGO_AES 4 883#define R92C_CAM_ALGO_AES 4
884#define R92C_CAM_ALGO_WEP104 5 884#define R92C_CAM_ALGO_WEP104 5
885#define R92C_CAM_VALID 0x00008000 885#define R92C_CAM_VALID 0x00008000
886#define R92C_CAM_MACLO_M 0xffff0000 886#define R92C_CAM_MACLO_M 0xffff0000
887#define R92C_CAM_MACLO_S 16 887#define R92C_CAM_MACLO_S 16
888 888
889/* Rate adaptation modes. */ 889/* Rate adaptation modes. */
890#define R92C_RAID_11GN 1 890#define R92C_RAID_11GN 1
891#define R92C_RAID_11N 3 891#define R92C_RAID_11N 3
892#define R92C_RAID_11BG 4 892#define R92C_RAID_11BG 4
893#define R92C_RAID_11G 5 /* "pure" 11g */ 893#define R92C_RAID_11G 5 /* "pure" 11g */
894#define R92C_RAID_11B 6 894#define R92C_RAID_11B 6
895 895
896 896
897/* Macros to access unaligned little-endian memory. */ 897/* Macros to access unaligned little-endian memory. */
898#define LE_READ_2(x) ((x)[0] | (x)[1] << 8) 898#define LE_READ_2(x) ((x)[0] | (x)[1] << 8)
899#define LE_READ_4(x) ((x)[0] | (x)[1] << 8 | (x)[2] << 16 | (x)[3] << 24) 899#define LE_READ_4(x) ((x)[0] | (x)[1] << 8 | (x)[2] << 16 | (x)[3] << 24)
900 900
901/* 901/*
902 * Macros to access subfields in registers. 902 * Macros to access subfields in registers.
903 */ 903 */
904/* Mask and Shift (getter). */ 904/* Mask and Shift (getter). */
905#define MS(val, field) \ 905#define MS(val, field) \
906 (((val) & field##_M) >> field##_S) 906 (((val) & field##_M) >> field##_S)
907 907
908/* Shift and Mask (setter). */ 908/* Shift and Mask (setter). */
909#define SM(field, val) \ 909#define SM(field, val) \
910 (((val) << field##_S) & field##_M) 910 (((val) << field##_S) & field##_M)
911 911
912/* Rewrite. */ 912/* Rewrite. */
913#define RW(var, field, val) \ 913#define RW(var, field, val) \
914 (((var) & ~field##_M) | SM(field, val)) 914 (((var) & ~field##_M) | SM(field, val))
915 915
916/* 916/*
917 * Firmware image header. 917 * Firmware image header.
918 */ 918 */
919struct r92c_fw_hdr { 919struct r92c_fw_hdr {
920 /* QWORD0 */ 920 /* QWORD0 */
921 uint16_t signature; 921 uint16_t signature;
922 uint8_t category; 922 uint8_t category;
923 uint8_t function; 923 uint8_t function;
924 uint16_t version; 924 uint16_t version;
925 uint16_t subversion; 925 uint16_t subversion;
926 /* QWORD1 */ 926 /* QWORD1 */
927 uint8_t month; 927 uint8_t month;
928 uint8_t date; 928 uint8_t date;
929 uint8_t hour; 929 uint8_t hour;
930 uint8_t minute; 930 uint8_t minute;
931 uint16_t ramcodesize; 931 uint16_t ramcodesize;
932 uint16_t reserved2; 932 uint16_t reserved2;
933 /* QWORD2 */ 933 /* QWORD2 */
934 uint32_t svnidx; 934 uint32_t svnidx;
935 uint32_t reserved3; 935 uint32_t reserved3;
936 /* QWORD3 */ 936 /* QWORD3 */
937 uint32_t reserved4; 937 uint32_t reserved4;
938 uint32_t reserved5; 938 uint32_t reserved5;
939} __packed; 939} __packed;
940 940
941/* 941/*
942 * Host to firmware commands. 942 * Host to firmware commands.
943 */ 943 */
944struct r92c_fw_cmd { 944struct r92c_fw_cmd {
945 uint8_t id; 945 uint8_t id;
946#define R92C_CMD_AP_OFFLOAD 0 946#define R92C_CMD_AP_OFFLOAD 0
947#define R92C_CMD_SET_PWRMODE 1 947#define R92C_CMD_SET_PWRMODE 1
948#define R92C_CMD_JOINBSS_RPT 2 948#define R92C_CMD_JOINBSS_RPT 2
949#define R92C_CMD_RSVD_PAGE 3 949#define R92C_CMD_RSVD_PAGE 3
950#define R92C_CMD_RSSI 4 950#define R92C_CMD_RSSI 4
951#define R92C_CMD_RSSI_SETTING 5 951#define R92C_CMD_RSSI_SETTING 5
952#define R92C_CMD_MACID_CONFIG 6 952#define R92C_CMD_MACID_CONFIG 6
953#define R92C_CMD_MACID_PS_MODE 7 953#define R92C_CMD_MACID_PS_MODE 7
954#define R92C_CMD_P2P_PS_OFFLOAD 8 954#define R92C_CMD_P2P_PS_OFFLOAD 8
955#define R92C_CMD_SELECTIVE_SUSPEND 9 955#define R92C_CMD_SELECTIVE_SUSPEND 9
956#define R92C_CMD_FLAG_EXT 0x80 956#define R92C_CMD_FLAG_EXT 0x80
957 957
958 uint8_t msg[5]; 958 uint8_t msg[5];
959} __packed; 959} __packed;
960 960
961/* Structure for R92C_CMD_RSSI_SETTING. */ 961/* Structure for R92C_CMD_RSSI_SETTING. */
962struct r92c_fw_cmd_rssi { 962struct r92c_fw_cmd_rssi {
963 uint8_t macid; 963 uint8_t macid;
964 uint8_t reserved; 964 uint8_t reserved;
965 uint8_t pwdb; 965 uint8_t pwdb;
966} __packed; 966} __packed;
967 967
968/* Structure for R92C_CMD_MACID_CONFIG. */ 968/* Structure for R92C_CMD_MACID_CONFIG. */
969struct r92c_fw_cmd_macid_cfg { 969struct r92c_fw_cmd_macid_cfg {
970 uint32_t mask; 970 uint32_t mask;
971 uint8_t macid; 971 uint8_t macid;
972#define RTWN_MACID_BSS 0 972#define RTWN_MACID_BSS 0
973#define RTWN_MACID_BC 4 /* Broadcast. */ 973#define RTWN_MACID_BC 4 /* Broadcast. */
974#define RTWN_MACID_VALID 0x80 974#define RTWN_MACID_VALID 0x80
975} __packed; 975} __packed;
976 976
977/* 977/*
978 * RTL8192CU ROM image. 978 * RTL8192CU ROM image.
979 */ 979 */
980struct r92c_rom { 980struct r92c_rom {
981 uint16_t id; /* 0x8129 */ 981 uint16_t id; /* 0x8129 */
982 uint8_t reserved1[5]; 982 uint8_t reserved1[5];
983 uint8_t dbg_sel; 983 uint8_t dbg_sel;
984 uint16_t reserved2; 984 uint16_t reserved2;
985 uint16_t vid; 985 uint16_t vid;
986 uint16_t pid; 986 uint16_t pid;
987 uint8_t usb_opt; 987 uint8_t usb_opt;
988 uint8_t ep_setting; 988 uint8_t ep_setting;
989 uint16_t reserved3; 989 uint16_t reserved3;
990 uint8_t usb_phy; 990 uint8_t usb_phy;
991 uint8_t reserved4[3]; 991 uint8_t reserved4[3];
992 uint8_t macaddr[6]; 992 uint8_t macaddr[6];
993 uint8_t string[61]; /* "Realtek" */ 993 uint8_t string[61]; /* "Realtek" */
994 uint8_t subcustomer_id; 994 uint8_t subcustomer_id;
995 uint8_t cck_tx_pwr[R92C_MAX_CHAINS][3]; 995 uint8_t cck_tx_pwr[R92C_MAX_CHAINS][3];
996 uint8_t ht40_1s_tx_pwr[R92C_MAX_CHAINS][3]; 996 uint8_t ht40_1s_tx_pwr[R92C_MAX_CHAINS][3];
997 uint8_t ht40_2s_tx_pwr_diff[3]; 997 uint8_t ht40_2s_tx_pwr_diff[3];
998 uint8_t ht20_tx_pwr_diff[3]; 998 uint8_t ht20_tx_pwr_diff[3];
999 uint8_t ofdm_tx_pwr_diff[3]; 999 uint8_t ofdm_tx_pwr_diff[3];
1000 uint8_t ht40_max_pwr[3]; 1000 uint8_t ht40_max_pwr[3];
1001 uint8_t ht20_max_pwr[3]; 1001 uint8_t ht20_max_pwr[3];
1002 uint8_t xtal_calib; 1002 uint8_t xtal_calib;
1003 uint8_t tssi[R92C_MAX_CHAINS]; 1003 uint8_t tssi[R92C_MAX_CHAINS];
1004 uint8_t thermal_meter; 1004 uint8_t thermal_meter;
1005 uint8_t rf_opt1; 1005 uint8_t rf_opt1;
1006#define R92C_ROM_RF1_REGULATORY_M 0x07 1006#define R92C_ROM_RF1_REGULATORY_M 0x07
1007#define R92C_ROM_RF1_REGULATORY_S 0 1007#define R92C_ROM_RF1_REGULATORY_S 0
1008#define R92C_ROM_RF1_BOARD_TYPE_M 0xe0 1008#define R92C_ROM_RF1_BOARD_TYPE_M 0xe0
1009#define R92C_ROM_RF1_BOARD_TYPE_S 5 1009#define R92C_ROM_RF1_BOARD_TYPE_S 5
1010#define R92C_BOARD_TYPE_DONGLE 0 1010#define R92C_BOARD_TYPE_DONGLE 0
1011#define R92C_BOARD_TYPE_HIGHPA 1 1011#define R92C_BOARD_TYPE_HIGHPA 1
1012#define R92C_BOARD_TYPE_MINICARD 2 1012#define R92C_BOARD_TYPE_MINICARD 2
1013#define R92C_BOARD_TYPE_SOLO 3 1013#define R92C_BOARD_TYPE_SOLO 3
1014#define R92C_BOARD_TYPE_COMBO 4 1014#define R92C_BOARD_TYPE_COMBO 4
1015 1015
1016 uint8_t rf_opt2; 1016 uint8_t rf_opt2;
1017 uint8_t rf_opt3; 1017 uint8_t rf_opt3;
1018 uint8_t rf_opt4; 1018 uint8_t rf_opt4;
1019 uint8_t channel_plan; 1019 uint8_t channel_plan;
1020 uint8_t version; 1020 uint8_t version;
1021 uint8_t curstomer_id; 1021 uint8_t curstomer_id;
1022} __packed; 1022} __packed;
1023 1023
1024/* Rx MAC descriptor. */ 1024/* Rx MAC descriptor. */
1025struct r92c_rx_desc { 1025struct r92c_rx_desc {
1026 uint32_t rxdw0; 1026 uint32_t rxdw0;
1027#define R92C_RXDW0_PKTLEN_M 0x00003fff 1027#define R92C_RXDW0_PKTLEN_M 0x00003fff
1028#define R92C_RXDW0_PKTLEN_S 0 1028#define R92C_RXDW0_PKTLEN_S 0
1029#define R92C_RXDW0_CRCERR 0x00004000 1029#define R92C_RXDW0_CRCERR 0x00004000
1030#define R92C_RXDW0_ICVERR 0x00008000 1030#define R92C_RXDW0_ICVERR 0x00008000
1031#define R92C_RXDW0_INFOSZ_M 0x000f0000 1031#define R92C_RXDW0_INFOSZ_M 0x000f0000
1032#define R92C_RXDW0_INFOSZ_S 16 1032#define R92C_RXDW0_INFOSZ_S 16
1033#define R92C_RXDW0_QOS 0x00800000 1033#define R92C_RXDW0_QOS 0x00800000
1034#define R92C_RXDW0_SHIFT_M 0x03000000 1034#define R92C_RXDW0_SHIFT_M 0x03000000
1035#define R92C_RXDW0_SHIFT_S 24 1035#define R92C_RXDW0_SHIFT_S 24
1036#define R92C_RXDW0_PHYST 0x04000000 1036#define R92C_RXDW0_PHYST 0x04000000
1037#define R92C_RXDW0_DECRYPTED 0x08000000 1037#define R92C_RXDW0_DECRYPTED 0x08000000
1038#define R92C_RXDW0_LS 0x10000000 1038#define R92C_RXDW0_LS 0x10000000
1039#define R92C_RXDW0_FS 0x20000000 1039#define R92C_RXDW0_FS 0x20000000
1040#define R92C_RXDW0_EOR 0x40000000 1040#define R92C_RXDW0_EOR 0x40000000
1041#define R92C_RXDW0_OWN 0x80000000 1041#define R92C_RXDW0_OWN 0x80000000
1042 1042
1043 uint32_t rxdw1; 1043 uint32_t rxdw1;
1044 uint32_t rxdw2; 1044 uint32_t rxdw2;
1045#define R92C_RXDW2_PKTCNT_M 0x00ff0000 1045#define R92C_RXDW2_PKTCNT_M 0x00ff0000
1046#define R92C_RXDW2_PKTCNT_S 16 1046#define R92C_RXDW2_PKTCNT_S 16
1047 1047
1048 uint32_t rxdw3; 1048 uint32_t rxdw3;
1049#define R92C_RXDW3_RATE_M 0x0000003f 1049#define R92C_RXDW3_RATE_M 0x0000003f
1050#define R92C_RXDW3_RATE_S 0 1050#define R92C_RXDW3_RATE_S 0
1051#define R92C_RXDW3_HT 0x00000040 1051#define R92C_RXDW3_HT 0x00000040
1052#define R92C_RXDW3_HTC 0x00000400 1052#define R92C_RXDW3_HTC 0x00000400
1053 1053
1054 uint32_t rxdw4; 1054 uint32_t rxdw4;
1055 uint32_t rxdw5; 1055 uint32_t rxdw5;
1056 1056
1057 uint32_t rxbufaddr; 1057 uint32_t rxbufaddr;
1058 uint32_t rxbufaddr64; 1058 uint32_t rxbufaddr64;
1059} __packed __attribute__((aligned(4))); 1059} __packed __attribute__((aligned(4)));
1060 1060
1061/* Rx PHY descriptor. */ 1061/* Rx PHY descriptor. */
1062struct r92c_rx_phystat { 1062struct r92c_rx_phystat {
1063 uint32_t phydw0; 1063 uint32_t phydw0;
1064 uint32_t phydw1; 1064 uint32_t phydw1;
1065 uint32_t phydw2; 1065 uint32_t phydw2;
1066 uint32_t phydw3; 1066 uint32_t phydw3;
1067 uint32_t phydw4; 1067 uint32_t phydw4;
1068 uint32_t phydw5; 1068 uint32_t phydw5;
1069 uint32_t phydw6; 1069 uint32_t phydw6;
1070 uint32_t phydw7; 1070 uint32_t phydw7;
1071} __packed __attribute__((aligned(4))); 1071} __packed __attribute__((aligned(4)));
1072 1072
1073/* Rx PHY CCK descriptor. */ 1073/* Rx PHY CCK descriptor. */
1074struct r92c_rx_cck { 1074struct r92c_rx_cck {
1075 uint8_t adc_pwdb[4]; 1075 uint8_t adc_pwdb[4];
1076 uint8_t sq_rpt; 1076 uint8_t sq_rpt;
1077 uint8_t agc_rpt; 1077 uint8_t agc_rpt;
1078} __packed; 1078} __packed;
1079 1079
1080/* Tx MAC descriptor. */ 1080/* Tx MAC descriptor. */
1081struct r92c_tx_desc { 1081struct r92c_tx_desc {
1082 uint32_t txdw0; 1082 uint32_t txdw0;
1083#define R92C_TXDW0_PKTLEN_M 0x0000ffff 1083#define R92C_TXDW0_PKTLEN_M 0x0000ffff
1084#define R92C_TXDW0_PKTLEN_S 0 1084#define R92C_TXDW0_PKTLEN_S 0
1085#define R92C_TXDW0_OFFSET_M 0x00ff0000 1085#define R92C_TXDW0_OFFSET_M 0x00ff0000
1086#define R92C_TXDW0_OFFSET_S 16 1086#define R92C_TXDW0_OFFSET_S 16
1087#define R92C_TXDW0_BMCAST 0x01000000 1087#define R92C_TXDW0_BMCAST 0x01000000
1088#define R92C_TXDW0_LSG 0x04000000 1088#define R92C_TXDW0_LSG 0x04000000
1089#define R92C_TXDW0_FSG 0x08000000 1089#define R92C_TXDW0_FSG 0x08000000
1090#define R92C_TXDW0_OWN 0x80000000 1090#define R92C_TXDW0_OWN 0x80000000
1091 1091
1092 uint32_t txdw1; 1092 uint32_t txdw1;
1093#define R92C_TXDW1_MACID_M 0x0000001f 1093#define R92C_TXDW1_MACID_M 0x0000001f
1094#define R92C_TXDW1_MACID_S 0 1094#define R92C_TXDW1_MACID_S 0
1095#define R92C_TXDW1_AGGEN 0x00000020 1095#define R92C_TXDW1_AGGEN 0x00000020
1096#define R92C_TXDW1_AGGBK 0x00000040 1096#define R92C_TXDW1_AGGBK 0x00000040
1097#define R92C_TXDW1_QSEL_M 0x00001f00 1097#define R92C_TXDW1_QSEL_M 0x00001f00
1098#define R92C_TXDW1_QSEL_S 8 1098#define R92C_TXDW1_QSEL_S 8
1099#define R92C_TXDW1_QSEL_BE 0x00 1099#define R92C_TXDW1_QSEL_BE 0x00
1100#define R92C_TXDW1_QSEL_BK 0x02 1100#define R92C_TXDW1_QSEL_BK 0x02
1101#define R92C_TXDW1_QSEL_VI 0x05 1101#define R92C_TXDW1_QSEL_VI 0x05
1102#define R92C_TXDW1_QSEL_VO 0x07 1102#define R92C_TXDW1_QSEL_VO 0x07
1103#define R92C_TXDW1_QSEL_BEACON 0x10 1103#define R92C_TXDW1_QSEL_BEACON 0x10
1104#define R92C_TXDW1_QSEL_HIGH 0x11 1104#define R92C_TXDW1_QSEL_HIGH 0x11
1105#define R92C_TXDW1_QSEL_MGNT 0x12 1105#define R92C_TXDW1_QSEL_MGNT 0x12
1106#define R92C_TXDW1_QSEL_CMD 0x13 1106#define R92C_TXDW1_QSEL_CMD 0x13
1107#define R92C_TXDW1_RAID_M 0x000f0000 1107#define R92C_TXDW1_RAID_M 0x000f0000
1108#define R92C_TXDW1_RAID_S 16 1108#define R92C_TXDW1_RAID_S 16
1109#define R92C_TXDW1_CIPHER_M 0x00c00000 1109#define R92C_TXDW1_CIPHER_M 0x00c00000
1110#define R92C_TXDW1_CIPHER_S 22 1110#define R92C_TXDW1_CIPHER_S 22
1111#define R92C_TXDW1_CIPHER_NONE 0 1111#define R92C_TXDW1_CIPHER_NONE 0
1112#define R92C_TXDW1_CIPHER_RC4 1 1112#define R92C_TXDW1_CIPHER_RC4 1
1113#define R92C_TXDW1_CIPHER_AES 3 1113#define R92C_TXDW1_CIPHER_AES 3
1114#define R92C_TXDW1_PKTOFF_M 0x7c000000 1114#define R92C_TXDW1_PKTOFF_M 0x7c000000
1115#define R92C_TXDW1_PKTOFF_S 26 1115#define R92C_TXDW1_PKTOFF_S 26
1116 1116
1117 uint32_t txdw2; 1117 uint32_t txdw2;
1118 uint16_t txdw3; 1118 uint16_t txdw3;
1119 uint16_t txdseq; 1119 uint16_t txdseq;
1120 1120
1121 uint32_t txdw4; 1121 uint32_t txdw4;
1122#define R92C_TXDW4_RTSRATE_M 0x0000003f 1122#define R92C_TXDW4_RTSRATE_M 0x0000003f
1123#define R92C_TXDW4_RTSRATE_S 0 1123#define R92C_TXDW4_RTSRATE_S 0
1124#define R92C_TXDW4_QOS 0x00000040 1124#define R92C_TXDW4_QOS 0x00000040
1125#define R92C_TXDW4_HWSEQ 0x00000080 1125#define R92C_TXDW4_HWSEQ 0x00000080
1126#define R92C_TXDW4_DRVRATE 0x00000100 1126#define R92C_TXDW4_DRVRATE 0x00000100
1127#define R92C_TXDW4_CTS2SELF 0x00000800 1127#define R92C_TXDW4_CTS2SELF 0x00000800
1128#define R92C_TXDW4_RTSEN 0x00001000 1128#define R92C_TXDW4_RTSEN 0x00001000
1129#define R92C_TXDW4_HWRTSEN 0x00002000 1129#define R92C_TXDW4_HWRTSEN 0x00002000
1130#define R92C_TXDW4_SCO_M 0x003f0000 1130#define R92C_TXDW4_SCO_M 0x003f0000
1131#define R92C_TXDW4_SCO_S 20 1131#define R92C_TXDW4_SCO_S 20
1132#define R92C_TXDW4_SCO_SCA 1 1132#define R92C_TXDW4_SCO_SCA 1
1133#define R92C_TXDW4_SCO_SCB 2 1133#define R92C_TXDW4_SCO_SCB 2
1134#define R92C_TXDW4_40MHZ 0x02000000 1134#define R92C_TXDW4_40MHZ 0x02000000
1135 1135
1136 uint32_t txdw5; 1136 uint32_t txdw5;
1137#define R92C_TXDW5_DATARATE_M 0x0000003f 1137#define R92C_TXDW5_DATARATE_M 0x0000003f
1138#define R92C_TXDW5_DATARATE_S 0 1138#define R92C_TXDW5_DATARATE_S 0
1139#define R92C_TXDW5_SGI 0x00000040 1139#define R92C_TXDW5_SGI 0x00000040
1140#define R92C_TXDW5_DATARATE_FBLIMIT_M 0x00001f00 1140#define R92C_TXDW5_DATARATE_FBLIMIT_M 0x00001f00
1141#define R92C_TXDW5_DATARATE_FBLIMIT_S 8 1141#define R92C_TXDW5_DATARATE_FBLIMIT_S 8
1142#define R92C_TXDW5_RTSRATE_FBLIMIT_M 0x0001e000 1142#define R92C_TXDW5_RTSRATE_FBLIMIT_M 0x0001e000
1143#define R92C_TXDW5_RTSRATE_FBLIMIT_S 13 1143#define R92C_TXDW5_RTSRATE_FBLIMIT_S 13
1144#define R92C_TXDW5_RETRY_LIMIT_ENABLE 0x00020000 1144#define R92C_TXDW5_RETRY_LIMIT_ENABLE 0x00020000
1145#define R92C_TXDW5_DATA_RETRY_LIMIT_M 0x00fc0000 1145#define R92C_TXDW5_DATA_RETRY_LIMIT_M 0x00fc0000
1146#define R92C_TXDW5_DATA_RETRY_LIMIT_S 18 1146#define R92C_TXDW5_DATA_RETRY_LIMIT_S 18
1147#define R92C_TXDW5_AGGNUM_M 0xff000000 1147#define R92C_TXDW5_AGGNUM_M 0xff000000
1148#define R92C_TXDW5_AGGNUM_S 24 1148#define R92C_TXDW5_AGGNUM_S 24
1149 1149
1150 uint32_t txdw6; 1150 uint32_t txdw6;
1151 1151
1152 uint16_t txbufsize; 1152 uint16_t txbufsize;
1153 uint16_t pad; 1153 uint16_t pad;
1154 1154
1155 uint32_t txbufaddr; 1155 uint32_t txbufaddr;
1156 uint32_t txbufaddr64; 1156 uint32_t txbufaddr64;
1157 1157
1158 uint32_t nextdescaddr; 1158 uint32_t nextdescaddr;
1159 uint32_t nextdescaddr64; 1159 uint32_t nextdescaddr64;
1160 1160
1161 uint32_t reserved[4]; 1161 uint32_t reserved[4];
1162} __packed __attribute__((aligned(4))); 1162} __packed __attribute__((aligned(4)));
1163 1163
1164 1164
1165/* 1165/*
1166 * Driver definitions. 1166 * Driver definitions.
1167 */ 1167 */
1168#define RTWN_NTXQUEUES 9 1168#define RTWN_NTXQUEUES 9
1169#define RTWN_RX_LIST_COUNT 256 1169#define RTWN_RX_LIST_COUNT 256
1170#define RTWN_TX_LIST_COUNT 256 1170#define RTWN_TX_LIST_COUNT 256
1171#define RTWN_HOST_CMD_RING_COUNT 32 1171#define RTWN_HOST_CMD_RING_COUNT 32
1172 1172
1173/* TX queue indices. */ 1173/* TX queue indices. */
1174#define RTWN_BK_QUEUE 0 1174#define RTWN_BK_QUEUE 0
1175#define RTWN_BE_QUEUE 1 1175#define RTWN_BE_QUEUE 1
1176#define RTWN_VI_QUEUE 2 1176#define RTWN_VI_QUEUE 2
1177#define RTWN_VO_QUEUE 3 1177#define RTWN_VO_QUEUE 3
1178#define RTWN_BEACON_QUEUE 4 1178#define RTWN_BEACON_QUEUE 4
1179#define RTWN_TXCMD_QUEUE 5 1179#define RTWN_TXCMD_QUEUE 5
1180#define RTWN_MGNT_QUEUE 6 1180#define RTWN_MGNT_QUEUE 6
1181#define RTWN_HIGH_QUEUE 7 1181#define RTWN_HIGH_QUEUE 7
1182#define RTWN_HCCA_QUEUE 8 1182#define RTWN_HCCA_QUEUE 8
1183 1183
1184/* RX queue indices. */ 1184/* RX queue indices. */
1185#define RTWN_RX_QUEUE 0 1185#define RTWN_RX_QUEUE 0
1186 1186
1187#define RTWN_RXBUFSZ (16 * 1024) 1187#define RTWN_RXBUFSZ (16 * 1024)
1188#define RTWN_TXBUFSZ (sizeof(struct r92c_tx_desc) + IEEE80211_MAX_LEN) 1188#define RTWN_TXBUFSZ (sizeof(struct r92c_tx_desc) + IEEE80211_MAX_LEN)
1189 1189
1190#define RTWN_RIDX_COUNT 28 1190#define RTWN_RIDX_COUNT 28
1191 1191
1192#define RTWN_TX_TIMEOUT 5000 /* ms */ 1192#define RTWN_TX_TIMEOUT 5000 /* ms */
1193 1193
1194#define RTWN_LED_LINK 0 1194#define RTWN_LED_LINK 0
1195#define RTWN_LED_DATA 1 1195#define RTWN_LED_DATA 1
1196 1196
1197struct rtwn_rx_radiotap_header { 1197struct rtwn_rx_radiotap_header {
1198 struct ieee80211_radiotap_header wr_ihdr; 1198 struct ieee80211_radiotap_header wr_ihdr;
1199 uint8_t wr_flags; 1199 uint8_t wr_flags;
1200 uint8_t wr_rate; 1200 uint8_t wr_rate;
1201 uint16_t wr_chan_freq; 1201 uint16_t wr_chan_freq;
1202 uint16_t wr_chan_flags; 1202 uint16_t wr_chan_flags;
1203 uint8_t wr_dbm_antsignal; 1203 uint8_t wr_dbm_antsignal;
1204} __packed; 1204} __packed;
1205 1205
1206#define RTWN_RX_RADIOTAP_PRESENT \ 1206#define RTWN_RX_RADIOTAP_PRESENT \
1207 (1 << IEEE80211_RADIOTAP_FLAGS | \ 1207 (1 << IEEE80211_RADIOTAP_FLAGS | \
1208 1 << IEEE80211_RADIOTAP_RATE | \ 1208 1 << IEEE80211_RADIOTAP_RATE | \
1209 1 << IEEE80211_RADIOTAP_CHANNEL | \ 1209 1 << IEEE80211_RADIOTAP_CHANNEL | \
1210 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) 1210 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL)
1211 1211
1212struct rtwn_tx_radiotap_header { 1212struct rtwn_tx_radiotap_header {
1213 struct ieee80211_radiotap_header wt_ihdr; 1213 struct ieee80211_radiotap_header wt_ihdr;
1214 uint8_t wt_flags; 1214 uint8_t wt_flags;
1215 uint16_t wt_chan_freq; 1215 uint16_t wt_chan_freq;
1216 uint16_t wt_chan_flags; 1216 uint16_t wt_chan_flags;
1217} __packed; 1217} __packed;
1218 1218
1219#define RTWN_TX_RADIOTAP_PRESENT \ 1219#define RTWN_TX_RADIOTAP_PRESENT \
1220 (1 << IEEE80211_RADIOTAP_FLAGS | \ 1220 (1 << IEEE80211_RADIOTAP_FLAGS | \
1221 1 << IEEE80211_RADIOTAP_CHANNEL) 1221 1 << IEEE80211_RADIOTAP_CHANNEL)
1222 1222
1223struct rtwn_softc; 1223struct rtwn_softc;
1224 1224
1225struct rtwn_rx_data { 1225struct rtwn_rx_data {
1226 bus_dmamap_t map; 1226 bus_dmamap_t map;
1227 struct mbuf *m; 1227 struct mbuf *m;
1228}; 1228};
1229 1229
1230struct rtwn_rx_ring { 1230struct rtwn_rx_ring {
1231 struct r92c_rx_desc *desc; 1231 struct r92c_rx_desc *desc;
1232 bus_dmamap_t map; 1232 bus_dmamap_t map;
1233 bus_dma_segment_t seg; 1233 bus_dma_segment_t seg;
1234 int nsegs; 1234 int nsegs;
1235 struct rtwn_rx_data rx_data[RTWN_RX_LIST_COUNT]; 1235 struct rtwn_rx_data rx_data[RTWN_RX_LIST_COUNT];
1236 1236
1237}; 1237};
1238struct rtwn_tx_data { 1238struct rtwn_tx_data {
1239 bus_dmamap_t map; 1239 bus_dmamap_t map;
1240 struct mbuf *m; 1240 struct mbuf *m;
1241 struct ieee80211_node *ni; 1241 struct ieee80211_node *ni;
1242}; 1242};
1243 1243
1244struct rtwn_tx_ring { 1244struct rtwn_tx_ring {
1245 bus_dmamap_t map; 1245 bus_dmamap_t map;
1246 bus_dma_segment_t seg; 1246 bus_dma_segment_t seg;
1247 int nsegs; 1247 int nsegs;
1248 struct r92c_tx_desc *desc; 1248 struct r92c_tx_desc *desc;
1249 struct rtwn_tx_data tx_data[RTWN_TX_LIST_COUNT]; 1249 struct rtwn_tx_data tx_data[RTWN_TX_LIST_COUNT];
1250 int queued; 1250 int queued;
1251 int cur; 1251 int cur;
1252}; 1252};
1253 1253
1254struct rtwn_host_cmd { 1254struct rtwn_host_cmd {
1255 void (*cb)(struct rtwn_softc *, void *); 1255 void (*cb)(struct rtwn_softc *, void *);
1256 uint8_t data[256]; 1256 uint8_t data[256];
1257}; 1257};
1258 1258
1259struct rtwn_cmd_key { 1259struct rtwn_cmd_key {
1260 struct ieee80211_key key; 1260 struct ieee80211_key key;
1261 uint16_t associd; 1261 uint16_t associd;
1262}; 1262};
1263 1263
1264struct rtwn_host_cmd_ring { 1264struct rtwn_host_cmd_ring {
1265 struct rtwn_host_cmd cmd[RTWN_HOST_CMD_RING_COUNT]; 1265 struct rtwn_host_cmd cmd[RTWN_HOST_CMD_RING_COUNT];
1266 int cur; 1266 int cur;
1267 int next; 1267 int next;
1268 int queued; 1268 int queued;
1269}; 1269};
1270 1270
1271struct rtwn_softc { 1271struct rtwn_softc {
1272 device_t sc_dev; 1272 device_t sc_dev;
1273 struct ethercom sc_ec; 1273 struct ethercom sc_ec;
1274 struct ieee80211com sc_ic; 1274 struct ieee80211com sc_ic;
1275 int (*sc_newstate)(struct ieee80211com *, 1275 int (*sc_newstate)(struct ieee80211com *,
1276 enum ieee80211_state, int); 1276 enum ieee80211_state, int);
1277 1277
1278 /* PCI specific goo. */ 1278 /* PCI specific goo. */
1279 bus_dma_tag_t sc_dmat; 1279 bus_dma_tag_t sc_dmat;
1280 pci_chipset_tag_t sc_pc; 1280 pci_chipset_tag_t sc_pc;
1281 pcitag_t sc_tag; 1281 pcitag_t sc_tag;
1282 void *sc_ih; 1282 void *sc_ih;
1283#ifdef __HAVE_PCI_MSI_MSIX 
1284 pci_intr_handle_t *sc_pihp; 1283 pci_intr_handle_t *sc_pihp;
1285#endif 
1286 bus_space_tag_t sc_st; 1284 bus_space_tag_t sc_st;
1287 bus_space_handle_t sc_sh; 1285 bus_space_handle_t sc_sh;
1288 bus_size_t sc_mapsize; 1286 bus_size_t sc_mapsize;
1289 int sc_cap_off; 1287 int sc_cap_off;
1290 1288
1291 1289
1292 struct callout scan_to; 1290 struct callout scan_to;
1293 struct callout calib_to; 1291 struct callout calib_to;
1294 void *init_task; 1292 void *init_task;
1295 int ac2idx[WME_NUM_AC]; 1293 int ac2idx[WME_NUM_AC];
1296 uint32_t sc_flags; 1294 uint32_t sc_flags;
1297#define RTWN_FLAG_FW_LOADED __BIT(0) 1295#define RTWN_FLAG_FW_LOADED __BIT(0)
1298#define RTWN_FLAG_CCK_HIPWR __BIT(1) 1296#define RTWN_FLAG_CCK_HIPWR __BIT(1)
1299 1297
1300 uint32_t chip; 1298 uint32_t chip;
1301#define RTWN_CHIP_88C __BIT(0) 1299#define RTWN_CHIP_88C __BIT(0)
1302#define RTWN_CHIP_92C __BIT(1) 1300#define RTWN_CHIP_92C __BIT(1)
1303#define RTWN_CHIP_92C_1T2R __BIT(2) 1301#define RTWN_CHIP_92C_1T2R __BIT(2)
1304#define RTWN_CHIP_UMC __BIT(3) 1302#define RTWN_CHIP_UMC __BIT(3)
1305#define RTWN_CHIP_UMC_A_CUT __BIT(4) 1303#define RTWN_CHIP_UMC_A_CUT __BIT(4)
1306#define RTWN_CHIP_UMC_B_CUT __BIT(5) 1304#define RTWN_CHIP_UMC_B_CUT __BIT(5)
1307 1305
1308 uint8_t board_type; 1306 uint8_t board_type;
1309 uint8_t regulatory; 1307 uint8_t regulatory;
1310 uint8_t pa_setting; 1308 uint8_t pa_setting;
1311 int avg_pwdb; 1309 int avg_pwdb;
1312 int thcal_state; 1310 int thcal_state;
1313 int thcal_lctemp; 1311 int thcal_lctemp;
1314 int ntxchains; 1312 int ntxchains;
1315 int nrxchains; 1313 int nrxchains;
1316 int ledlink; 1314 int ledlink;
1317 1315
1318 int sc_tx_timer; 1316 int sc_tx_timer;
1319 int fwcur; 1317 int fwcur;
1320 struct rtwn_rx_ring rx_ring; 1318 struct rtwn_rx_ring rx_ring;
1321 struct rtwn_tx_ring tx_ring[RTWN_NTXQUEUES]; 1319 struct rtwn_tx_ring tx_ring[RTWN_NTXQUEUES];
1322 uint32_t qfullmsk; 1320 uint32_t qfullmsk;
1323 struct r92c_rom rom; 1321 struct r92c_rom rom;
1324 1322
1325 uint32_t rf_chnlbw[R92C_MAX_CHAINS]; 1323 uint32_t rf_chnlbw[R92C_MAX_CHAINS];
1326 struct bpf_if *sc_drvbpf; 1324 struct bpf_if *sc_drvbpf;
1327 1325
1328 union { 1326 union {
1329 struct rtwn_rx_radiotap_header th; 1327 struct rtwn_rx_radiotap_header th;
1330 uint8_t pad[64]; 1328 uint8_t pad[64];
1331 } sc_rxtapu; 1329 } sc_rxtapu;
1332#define sc_rxtap sc_rxtapu.th 1330#define sc_rxtap sc_rxtapu.th
1333 int sc_rxtap_len; 1331 int sc_rxtap_len;
1334 1332
1335 union { 1333 union {
1336 struct rtwn_tx_radiotap_header th; 1334 struct rtwn_tx_radiotap_header th;
1337 uint8_t pad[64]; 1335 uint8_t pad[64];
1338 } sc_txtapu; 1336 } sc_txtapu;
1339#define sc_txtap sc_txtapu.th 1337#define sc_txtap sc_txtapu.th
1340 int sc_txtap_len; 1338 int sc_txtap_len;
1341}; 1339};
1342 1340
1343#define sc_if sc_ec.ec_if 1341#define sc_if sc_ec.ec_if
1344#define GET_IFP(sc) (&(sc)->sc_if) 1342#define GET_IFP(sc) (&(sc)->sc_if)
1345#define IC2IFP(ic) ((ic)->ic_ifp) 1343#define IC2IFP(ic) ((ic)->ic_ifp)
1346 1344
1347 1345
1348/* 1346/*
1349 * MAC initialization values. 1347 * MAC initialization values.
1350 */ 1348 */
1351static const struct { 1349static const struct {
1352 uint16_t reg; 1350 uint16_t reg;
1353 uint8_t val; 1351 uint8_t val;
1354} rtl8192ce_mac[] = { 1352} rtl8192ce_mac[] = {
1355 { 0x420, 0x80 }, { 0x423, 0x00 }, { 0x430, 0x00 }, { 0x431, 0x00 }, 1353 { 0x420, 0x80 }, { 0x423, 0x00 }, { 0x430, 0x00 }, { 0x431, 0x00 },
1356 { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 }, 1354 { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 },
1357 { 0x436, 0x06 }, { 0x437, 0x07 }, { 0x438, 0x00 }, { 0x439, 0x00 }, 1355 { 0x436, 0x06 }, { 0x437, 0x07 }, { 0x438, 0x00 }, { 0x439, 0x00 },
1358 { 0x43a, 0x00 }, { 0x43b, 0x01 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, 1356 { 0x43a, 0x00 }, { 0x43b, 0x01 }, { 0x43c, 0x04 }, { 0x43d, 0x05 },
1359 { 0x43e, 0x06 }, { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, 1357 { 0x43e, 0x06 }, { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 },
1360 { 0x442, 0x00 }, { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, 1358 { 0x442, 0x00 }, { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f },
1361 { 0x447, 0x00 }, { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, 1359 { 0x447, 0x00 }, { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 },
1362 { 0x45b, 0xb9 }, { 0x460, 0x88 }, { 0x461, 0x88 }, { 0x462, 0x06 }, 1360 { 0x45b, 0xb9 }, { 0x460, 0x88 }, { 0x461, 0x88 }, { 0x462, 0x06 },
1363 { 0x463, 0x03 }, { 0x4c8, 0x04 }, { 0x4c9, 0x08 }, { 0x4cc, 0x02 }, 1361 { 0x463, 0x03 }, { 0x4c8, 0x04 }, { 0x4c9, 0x08 }, { 0x4cc, 0x02 },
1364 { 0x4cd, 0x28 }, { 0x4ce, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 }, 1362 { 0x4cd, 0x28 }, { 0x4ce, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 },
1365 { 0x502, 0x2f }, { 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 }, 1363 { 0x502, 0x2f }, { 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 },
1366 { 0x506, 0x5e }, { 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 }, 1364 { 0x506, 0x5e }, { 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 },
1367 { 0x50a, 0x5e }, { 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 }, 1365 { 0x50a, 0x5e }, { 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 },
1368 { 0x50e, 0x00 }, { 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a }, 1366 { 0x50e, 0x00 }, { 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a },
1369 { 0x515, 0x10 }, { 0x516, 0x0a }, { 0x517, 0x10 }, { 0x51a, 0x16 }, 1367 { 0x515, 0x10 }, { 0x516, 0x0a }, { 0x517, 0x10 }, { 0x51a, 0x16 },
1370 { 0x524, 0x0f }, { 0x525, 0x4f }, { 0x546, 0x20 }, { 0x547, 0x00 }, 1368 { 0x524, 0x0f }, { 0x525, 0x4f }, { 0x546, 0x20 }, { 0x547, 0x00 },
1371 { 0x559, 0x02 }, { 0x55a, 0x02 }, { 0x55d, 0xff }, { 0x605, 0x30 }, 1369 { 0x559, 0x02 }, { 0x55a, 0x02 }, { 0x55d, 0xff }, { 0x605, 0x30 },
1372 { 0x608, 0x0e }, { 0x609, 0x2a }, { 0x652, 0x20 }, { 0x63c, 0x0a }, 1370 { 0x608, 0x0e }, { 0x609, 0x2a }, { 0x652, 0x20 }, { 0x63c, 0x0a },
1373 { 0x63d, 0x0e }, { 0x700, 0x21 }, { 0x701, 0x43 }, { 0x702, 0x65 }, 1371 { 0x63d, 0x0e }, { 0x700, 0x21 }, { 0x701, 0x43 }, { 0x702, 0x65 },
1374 { 0x703, 0x87 }, { 0x708, 0x21 }, { 0x709, 0x43 }, { 0x70a, 0x65 }, 1372 { 0x703, 0x87 }, { 0x708, 0x21 }, { 0x709, 0x43 }, { 0x70a, 0x65 },
1375 { 0x70b, 0x87 } 1373 { 0x70b, 0x87 }
1376}; 1374};
1377 1375
1378/* 1376/*
1379 * Baseband initialization values. 1377 * Baseband initialization values.
1380 */ 1378 */
1381struct rtwn_bb_prog { 1379struct rtwn_bb_prog {
1382 int count; 1380 int count;
1383 const uint16_t *regs; 1381 const uint16_t *regs;
1384 const uint32_t *vals; 1382 const uint32_t *vals;
1385 int agccount; 1383 int agccount;
1386 const uint32_t *agcvals; 1384 const uint32_t *agcvals;
1387}; 1385};
1388 1386
1389/* 1387/*
1390 * RTL8192CU and RTL8192CE-VAU. 1388 * RTL8192CU and RTL8192CE-VAU.
1391 */ 1389 */
1392static const uint16_t rtl8192ce_bb_regs[] = { 1390static const uint16_t rtl8192ce_bb_regs[] = {
1393 0x024, 0x028, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818, 1391 0x024, 0x028, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818,
1394 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c, 1392 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c,
1395 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 0x860, 1393 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 0x860,
1396 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 0x884, 1394 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 0x884,
1397 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 0x908, 1395 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 0x908,
1398 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 0xa1c, 1396 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 0xa1c,
1399 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, 0xc08, 1397 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, 0xc08,
1400 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 0xc2c, 1398 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 0xc2c,
1401 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 0xc50, 1399 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 0xc50,
1402 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74, 1400 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74,
1403 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 0xc98, 1401 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 0xc98,
1404 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 0xcbc, 1402 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 0xcbc,
1405 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 0xce0, 1403 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 0xce0,
1406 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 0xd14, 1404 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 0xd14,
1407 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 0xd48, 1405 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 0xd48,
1408 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 0xd6c, 1406 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 0xd6c,
1409 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 0xe18, 1407 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 0xe18,
1410 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 0xe48, 1408 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 0xe48,
1411 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 0xe70, 1409 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 0xe70,
1412 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 0xed4, 1410 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 0xed4,
1413 0xed8, 0xedc, 0xee0, 0xeec, 0xf14, 0xf4c, 0xf00 1411 0xed8, 0xedc, 0xee0, 0xeec, 0xf14, 0xf4c, 0xf00
1414}; 1412};
1415 1413
1416static const uint32_t rtl8192ce_bb_vals_2t[] = { 1414static const uint32_t rtl8192ce_bb_vals_2t[] = {
1417 0x0011800f, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 1415 0x0011800f, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00,
1418 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1416 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000,
1419 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, 1417 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727,
1420 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, 1418 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000,
1421 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, 1419 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a,
1422 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, 1420 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27,
1423 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, 1421 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070,
1424 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, 1422 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe,
1425 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1423 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000,
1426 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1424 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f,
1427 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1425 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000,
1428 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1426 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007,
1429 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1427 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000,
1430 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1428 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000,
1431 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1429 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994,
1432 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1430 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f,
1433 0x69543420, 0x43bc0094, 0x69543420, 0x433c0094, 0x00000000, 1431 0x69543420, 0x43bc0094, 0x69543420, 0x433c0094, 0x00000000,
1434 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1432 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db,
1435 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1433 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100,
1436 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1434 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f,
1437 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1435 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000,
1438 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1436 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000,
1439 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1437 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427,
1440 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1438 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c,
1441 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, 1439 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333,
1442 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1440 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000,
1443 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1441 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000,
1444 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1442 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064,
1445 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1443 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e,
1446 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1444 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a,
1447 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1445 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000,
1448 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1446 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00,
1449 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1447 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f,
1450 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, 1448 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4,
1451 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 1449 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4,
1452 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, 1450 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4,
1453 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, 1451 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003,
1454 0x00000000, 0x00000300 1452 0x00000000, 0x00000300
1455}; 1453};
1456 1454
1457static const uint32_t rtl8192ce_bb_vals_1t[] = { 1455static const uint32_t rtl8192ce_bb_vals_1t[] = {
1458 0x0011800f, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 1456 0x0011800f, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00,
1459 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1457 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000,
1460 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 1458 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000,
1461 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 1459 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000,
1462 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 1460 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a,
1463 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 1461 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200,
1464 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 1462 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070,
1465 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 1463 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe,
1466 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1464 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000,
1467 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1465 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f,
1468 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1466 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000,
1469 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1467 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007,
1470 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1468 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000,
1471 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1469 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000,
1472 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1470 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994,
1473 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1471 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f,
1474 0x69543420, 0x43bc0094, 0x69543420, 0x433c0094, 0x00000000, 1472 0x69543420, 0x43bc0094, 0x69543420, 0x433c0094, 0x00000000,
1475 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1473 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db,
1476 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1474 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100,
1477 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1475 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f,
1478 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1476 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000,
1479 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1477 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000,
1480 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1478 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427,
1481 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1479 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c,
1482 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 1480 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333,
1483 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1481 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000,
1484 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1482 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000,
1485 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1483 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064,
1486 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1484 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e,
1487 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1485 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a,
1488 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1486 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000,
1489 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1487 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00,
1490 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1488 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f,
1491 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x631b25a0, 1489 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x631b25a0,
1492 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1490 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0,
1493 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 1491 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0,
1494 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 1492 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003,
1495 0x00000000, 0x00000300, 1493 0x00000000, 0x00000300,
1496}; 1494};
1497 1495
1498static const uint32_t rtl8192ce_agc_vals[] = { 1496static const uint32_t rtl8192ce_agc_vals[] = {
1499 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1497 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001,
1500 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001, 1498 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001,
1501 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001, 1499 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001,
1502 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001, 1500 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001,
1503 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001, 1501 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001,
1504 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001, 1502 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001,
1505 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, 1503 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001,
1506 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1504 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001,
1507 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1505 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001,
1508 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1506 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001,
1509 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1507 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001,
1510 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1508 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001,
1511 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1509 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001,
1512 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1510 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001,
1513 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001, 1511 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001,
1514 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001, 1512 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001,
1515 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001, 1513 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001,
1516 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001, 1514 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001,
1517 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, 1515 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001,
1518 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001, 1516 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001,
1519 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1517 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001,
1520 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1518 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001,
1521 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1519 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001,
1522 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1520 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001,
1523 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1521 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001,
1524 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1522 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e,
1525 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1523 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e,
1526 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1524 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e,
1527 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1525 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e,
1528 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1526 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e,
1529 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1527 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e,
1530 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1528 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e
1531}; 1529};
1532 1530
1533static const struct rtwn_bb_prog rtl8192ce_bb_prog_2t = { 1531static const struct rtwn_bb_prog rtl8192ce_bb_prog_2t = {
1534 __arraycount(rtl8192ce_bb_regs), 1532 __arraycount(rtl8192ce_bb_regs),
1535 rtl8192ce_bb_regs, 1533 rtl8192ce_bb_regs,
1536 rtl8192ce_bb_vals_2t, 1534 rtl8192ce_bb_vals_2t,
1537 __arraycount(rtl8192ce_agc_vals), 1535 __arraycount(rtl8192ce_agc_vals),
1538 rtl8192ce_agc_vals 1536 rtl8192ce_agc_vals
1539}; 1537};
1540 1538
1541static const struct rtwn_bb_prog rtl8192ce_bb_prog_1t = { 1539static const struct rtwn_bb_prog rtl8192ce_bb_prog_1t = {
1542 __arraycount(rtl8192ce_bb_regs), 1540 __arraycount(rtl8192ce_bb_regs),
1543 rtl8192ce_bb_regs, 1541 rtl8192ce_bb_regs,
1544 rtl8192ce_bb_vals_1t, 1542 rtl8192ce_bb_vals_1t,
1545 __arraycount(rtl8192ce_agc_vals), 1543 __arraycount(rtl8192ce_agc_vals),
1546 rtl8192ce_agc_vals 1544 rtl8192ce_agc_vals
1547}; 1545};
1548 1546
1549/* 1547/*
1550 * RTL8188CU. 1548 * RTL8188CU.
1551 */ 1549 */
1552static const uint32_t rtl8192cu_bb_vals[] = { 1550static const uint32_t rtl8192cu_bb_vals[] = {
1553 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 1551 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00,
1554 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1552 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000,
1555 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, 1553 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727,
1556 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, 1554 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000,
1557 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, 1555 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a,
1558 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, 1556 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27,
1559 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, 1557 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070,
1560 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, 1558 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe,
1561 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1559 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000,
1562 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1560 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f,
1563 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1561 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000,
1564 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1562 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007,
1565 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1563 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000,
1566 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1564 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000,
1567 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1565 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994,
1568 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1566 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f,
1569 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1567 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000,
1570 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x0186115b, 1568 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x0186115b,
1571 0x0000001f, 0x00b99612, 0x40000100, 0x20f60000, 0x40000100, 1569 0x0000001f, 0x00b99612, 0x40000100, 0x20f60000, 0x40000100,
1572 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1570 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f,
1573 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1571 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000,
1574 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1572 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000,
1575 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1573 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427,
1576 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1574 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c,
1577 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, 1575 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333,
1578 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1576 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000,
1579 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1577 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000,
1580 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1578 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064,
1581 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1579 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e,
1582 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1580 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a,
1583 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1581 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000,
1584 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1582 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00,
1585 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1583 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f,
1586 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, 1584 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4,
1587 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 1585 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4,
1588 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, 1586 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4,
1589 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, 1587 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003,
1590 0x00000000, 0x00000300 1588 0x00000000, 0x00000300
1591}; 1589};
1592 1590
1593static const struct rtwn_bb_prog rtl8192cu_bb_prog = { 1591static const struct rtwn_bb_prog rtl8192cu_bb_prog = {
1594 __arraycount(rtl8192ce_bb_regs), 1592 __arraycount(rtl8192ce_bb_regs),
1595 rtl8192ce_bb_regs, 1593 rtl8192ce_bb_regs,
1596 rtl8192cu_bb_vals, 1594 rtl8192cu_bb_vals,
1597 __arraycount(rtl8192ce_agc_vals), 1595 __arraycount(rtl8192ce_agc_vals),
1598 rtl8192ce_agc_vals 1596 rtl8192ce_agc_vals
1599}; 1597};
1600 1598
1601/* 1599/*
1602 * RTL8188CE-VAU. 1600 * RTL8188CE-VAU.
1603 */ 1601 */
1604static const uint32_t rtl8188ce_bb_vals[] = { 1602static const uint32_t rtl8188ce_bb_vals[] = {
1605 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 1603 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00,
1606 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1604 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000,
1607 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 1605 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000,
1608 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 1606 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000,
1609 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 1607 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a,
1610 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 1608 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200,
1611 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 1609 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070,
1612 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 1610 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe,
1613 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1611 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000,
1614 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1612 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f,
1615 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1613 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000,
1616 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1614 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007,
1617 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1615 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000,
1618 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1616 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000,
1619 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1617 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994,
1620 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1618 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f,
1621 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1619 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000,
1622 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1620 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db,
1623 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1621 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100,
1624 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1622 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f,
1625 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1623 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000,
1626 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1624 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000,
1627 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1625 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427,
1628 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1626 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c,
1629 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 1627 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333,
1630 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1628 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000,
1631 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1629 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000,
1632 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1630 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064,
1633 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1631 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e,
1634 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1632 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a,
1635 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1633 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000,
1636 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1634 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00,
1637 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1635 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f,
1638 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, 1636 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0,
1639 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1637 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0,
1640 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 1638 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0,
1641 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 1639 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003,
1642 0x00000000, 0x00000300 1640 0x00000000, 0x00000300
1643}; 1641};
1644 1642
1645static const uint32_t rtl8188ce_agc_vals[] = { 1643static const uint32_t rtl8188ce_agc_vals[] = {
1646 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1644 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001,
1647 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001, 1645 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001,
1648 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001, 1646 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001,
1649 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001, 1647 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001,
1650 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001, 1648 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001,
1651 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001, 1649 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001,
1652 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, 1650 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001,
1653 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1651 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001,
1654 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1652 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001,
1655 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1653 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001,
1656 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1654 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001,
1657 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1655 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001,
1658 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1656 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001,
1659 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1657 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001,
1660 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001, 1658 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001,
1661 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001, 1659 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001,
1662 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001, 1660 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001,
1663 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001, 1661 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001,
1664 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, 1662 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001,
1665 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001, 1663 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001,
1666 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1664 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001,
1667 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1665 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001,
1668 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1666 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001,
1669 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1667 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001,
1670 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1668 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001,
1671 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1669 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e,
1672 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1670 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e,
1673 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1671 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e,
1674 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1672 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e,
1675 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1673 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e,
1676 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1674 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e,
1677 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1675 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e
1678}; 1676};
1679 1677
1680static const struct rtwn_bb_prog rtl8188ce_bb_prog = { 1678static const struct rtwn_bb_prog rtl8188ce_bb_prog = {
1681 __arraycount(rtl8192ce_bb_regs), 1679 __arraycount(rtl8192ce_bb_regs),
1682 rtl8192ce_bb_regs, 1680 rtl8192ce_bb_regs,
1683 rtl8188ce_bb_vals, 1681 rtl8188ce_bb_vals,
1684 __arraycount(rtl8188ce_agc_vals), 1682 __arraycount(rtl8188ce_agc_vals),
1685 rtl8188ce_agc_vals 1683 rtl8188ce_agc_vals
1686}; 1684};
1687 1685
1688static const uint32_t rtl8188cu_bb_vals[] = { 1686static const uint32_t rtl8188cu_bb_vals[] = {
1689 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 1687 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00,
1690 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1688 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000,
1691 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 1689 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000,
1692 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 1690 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000,
1693 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 1691 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a,
1694 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 1692 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200,
1695 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 1693 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070,
1696 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 1694 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe,
1697 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1695 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000,
1698 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1696 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f,
1699 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1697 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000,
1700 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1698 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007,
1701 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1699 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000,
1702 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1700 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000,
1703 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1701 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994,
1704 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1702 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f,
1705 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1703 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000,
1706 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1704 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db,
1707 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1705 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100,
1708 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1706 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f,
1709 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1707 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000,
1710 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1708 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000,
1711 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1709 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427,
1712 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1710 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c,
1713 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 1711 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333,
1714 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1712 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000,
1715 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1713 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000,
1716 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1714 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064,
1717 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1715 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e,
1718 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1716 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a,
1719 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1717 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000,
1720 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1718 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00,
1721 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1719 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f,
1722 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, 1720 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0,
1723 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1721 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0,
1724 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 1722 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0,
1725 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 1723 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003,
1726 0x00000000, 0x00000300 1724 0x00000000, 0x00000300
1727}; 1725};
1728 1726
1729static const struct rtwn_bb_prog rtl8188cu_bb_prog = { 1727static const struct rtwn_bb_prog rtl8188cu_bb_prog = {
1730 __arraycount(rtl8192ce_bb_regs), 1728 __arraycount(rtl8192ce_bb_regs),
1731 rtl8192ce_bb_regs, 1729 rtl8192ce_bb_regs,
1732 rtl8188cu_bb_vals, 1730 rtl8188cu_bb_vals,
1733 __arraycount(rtl8188ce_agc_vals), 1731 __arraycount(rtl8188ce_agc_vals),
1734 rtl8188ce_agc_vals 1732 rtl8188ce_agc_vals
1735}; 1733};
1736 1734
1737/* 1735/*
1738 * RTL8188RU. 1736 * RTL8188RU.
1739 */ 1737 */
1740static const uint16_t rtl8188ru_bb_regs[] = { 1738static const uint16_t rtl8188ru_bb_regs[] = {
1741 0x024, 0x028, 0x040, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 1739 0x024, 0x028, 0x040, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814,
1742 0x818, 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 1740 0x818, 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838,
1743 0x83c, 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 1741 0x83c, 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c,
1744 0x860, 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 1742 0x860, 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880,
1745 0x884, 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 1743 0x884, 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904,
1746 0x908, 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 1744 0x908, 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18,
1747 0xa1c, 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, 1745 0xa1c, 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04,
1748 0xc08, 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 1746 0xc08, 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28,
1749 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 1747 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c,
1750 0xc50, 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 1748 0xc50, 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70,
1751 0xc74, 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 1749 0xc74, 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94,
1752 0xc98, 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 1750 0xc98, 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8,
1753 0xcbc, 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 1751 0xcbc, 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc,
1754 0xce0, 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 1752 0xce0, 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10,
1755 0xd14, 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 1753 0xd14, 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44,
1756 0xd48, 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 1754 0xd48, 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68,
1757 0xd6c, 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 1755 0xd6c, 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14,
1758 0xe18, 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 1756 0xe18, 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44,
1759 0xe48, 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 1757 0xe48, 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c,
1760 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 1758 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0,
1761 0xed4, 0xed8, 0xedc, 0xee0, 0xeec, 0xee8, 0xf14, 0xf4c, 0xf00 1759 0xed4, 0xed8, 0xedc, 0xee0, 0xeec, 0xee8, 0xf14, 0xf4c, 0xf00
1762}; 1760};
1763 1761
1764static const uint32_t rtl8188ru_bb_vals[] = { 1762static const uint32_t rtl8188ru_bb_vals[] = {
1765 0x0011800d, 0x00ffdb83, 0x000c0004, 0x80040000, 0x00000001, 1763 0x0011800d, 0x00ffdb83, 0x000c0004, 0x80040000, 0x00000001,
1766 0x0000fc00, 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 1764 0x0000fc00, 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385,
1767 0x00000000, 0x01000100, 0x00390204, 0x00000000, 0x00000000, 1765 0x00000000, 0x01000100, 0x00390204, 0x00000000, 0x00000000,
1768 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010000, 1766 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010000,
1769 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1767 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1770 0x569a569a, 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 1768 0x569a569a, 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000,
1771 0x32323200, 0x03000300, 0x22004000, 0x00000808, 0x00ffc3f1, 1769 0x32323200, 0x03000300, 0x22004000, 0x00000808, 0x00ffc3f1,
1772 0xc0083070, 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 1770 0xc0083070, 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800,
1773 0xfffffffe, 0x40302010, 0x00706050, 0x00000000, 0x00000023, 1771 0xfffffffe, 0x40302010, 0x00706050, 0x00000000, 0x00000023,
1774 0x00000000, 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 1772 0x00000000, 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300,
1775 0x2e68120f, 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 1773 0x2e68120f, 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00,
1776 0x15160000, 0x070b0f12, 0x00000104, 0x00d30000, 0x101fbf00, 1774 0x15160000, 0x070b0f12, 0x00000104, 0x00d30000, 0x101fbf00,
1777 0x00000007, 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 1775 0x00000007, 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c,
1778 0x08800000, 0x40000100, 0x08800000, 0x40000100, 0x00000000, 1776 0x08800000, 0x40000100, 0x08800000, 0x40000100, 0x00000000,
1779 0x00000000, 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 1777 0x00000000, 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf,
1780 0x49795994, 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 1778 0x49795994, 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107,
1781 0x007f037f, 0x6954342e, 0x43bc0094, 0x6954342f, 0x433c0094, 1779 0x007f037f, 0x6954342e, 0x43bc0094, 0x6954342f, 0x433c0094,
1782 0x00000000, 0x5116848b, 0x47c00bff, 0x00000036, 0x2c56000d, 1780 0x00000000, 0x5116848b, 0x47c00bff, 0x00000036, 0x2c56000d,
1783 0x018610db, 0x0000001f, 0x00b91612, 0x24000090, 0x20f60000, 1781 0x018610db, 0x0000001f, 0x00b91612, 0x24000090, 0x20f60000,
1784 0x24000090, 0x20200000, 0x00121820, 0x00000000, 0x00121820, 1782 0x24000090, 0x20200000, 0x00121820, 0x00000000, 0x00121820,
1785 0x00007f7f, 0x00000000, 0x00000080, 0x00000000, 0x00000000, 1783 0x00007f7f, 0x00000000, 0x00000080, 0x00000000, 0x00000000,
1786 0x00000000, 0x00000000, 0x00000000, 0x28000000, 0x00000000, 1784 0x00000000, 0x00000000, 0x00000000, 0x28000000, 0x00000000,
1787 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1785 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1788 0x64b22427, 0x00766932, 0x00222222, 0x00000000, 0x37644302, 1786 0x64b22427, 0x00766932, 0x00222222, 0x00000000, 0x37644302,
1789 0x2f97d40c, 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 1787 0x2f97d40c, 0x00080740, 0x00020401, 0x0000907f, 0x20010201,
1790 0xa0633333, 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 1788 0xa0633333, 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000,
1791 0x80608000, 0x00000000, 0x00027293, 0x00000000, 0x00000000, 1789 0x80608000, 0x00000000, 0x00027293, 0x00000000, 0x00000000,
1792 0x00000000, 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 1790 0x00000000, 0x00000000, 0x6437140a, 0x00000000, 0x00000000,
1793 0x30032064, 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 1791 0x30032064, 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16,
1794 0x1812362e, 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 1792 0x1812362e, 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a,
1795 0x03902a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 1793 0x03902a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a,
1796 0x00000000, 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 1794 0x00000000, 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2,
1797 0x01007c00, 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 1795 0x01007c00, 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f,
1798 0x10008c1f, 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 1796 0x10008c1f, 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4,
1799 0x631b25a0, 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1797 0x631b25a0, 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0,
1800 0x081b25a0, 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 1798 0x081b25a0, 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0,
1801 0x631b25a0, 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 1799 0x631b25a0, 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0,
1802 0x31555448, 0x00000003, 0x00000000, 0x00000300 1800 0x31555448, 0x00000003, 0x00000000, 0x00000300
1803}; 1801};
1804 1802
1805static const uint32_t rtl8188ru_agc_vals[] = { 1803static const uint32_t rtl8188ru_agc_vals[] = {
1806 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1804 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001,
1807 0x7b050001, 0x7b060001, 0x7b070001, 0x7b080001, 0x7a090001, 1805 0x7b050001, 0x7b060001, 0x7b070001, 0x7b080001, 0x7a090001,
1808 0x790a0001, 0x780b0001, 0x770c0001, 0x760d0001, 0x750e0001, 1806 0x790a0001, 0x780b0001, 0x770c0001, 0x760d0001, 0x750e0001,
1809 0x740f0001, 0x73100001, 0x72110001, 0x71120001, 0x70130001, 1807 0x740f0001, 0x73100001, 0x72110001, 0x71120001, 0x70130001,
1810 0x6f140001, 0x6e150001, 0x6d160001, 0x6c170001, 0x6b180001, 1808 0x6f140001, 0x6e150001, 0x6d160001, 0x6c170001, 0x6b180001,
1811 0x6a190001, 0x691a0001, 0x681b0001, 0x671c0001, 0x661d0001, 1809 0x6a190001, 0x691a0001, 0x681b0001, 0x671c0001, 0x661d0001,
1812 0x651e0001, 0x641f0001, 0x63200001, 0x62210001, 0x61220001, 1810 0x651e0001, 0x641f0001, 0x63200001, 0x62210001, 0x61220001,
1813 0x60230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1811 0x60230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001,
1814 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1812 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001,
1815 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1813 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001,
1816 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1814 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001,
1817 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1815 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001,
1818 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1816 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001,
1819 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1817 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001,
1820 0x7b460001, 0x7b470001, 0x7b480001, 0x7a490001, 0x794a0001, 1818 0x7b460001, 0x7b470001, 0x7b480001, 0x7a490001, 0x794a0001,
1821 0x784b0001, 0x774c0001, 0x764d0001, 0x754e0001, 0x744f0001, 1819 0x784b0001, 0x774c0001, 0x764d0001, 0x754e0001, 0x744f0001,
1822 0x73500001, 0x72510001, 0x71520001, 0x70530001, 0x6f540001, 1820 0x73500001, 0x72510001, 0x71520001, 0x70530001, 0x6f540001,
1823 0x6e550001, 0x6d560001, 0x6c570001, 0x6b580001, 0x6a590001, 1821 0x6e550001, 0x6d560001, 0x6c570001, 0x6b580001, 0x6a590001,
1824 0x695a0001, 0x685b0001, 0x675c0001, 0x665d0001, 0x655e0001, 1822 0x695a0001, 0x685b0001, 0x675c0001, 0x665d0001, 0x655e0001,
1825 0x645f0001, 0x63600001, 0x62610001, 0x61620001, 0x60630001, 1823 0x645f0001, 0x63600001, 0x62610001, 0x61620001, 0x60630001,
1826 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1824 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001,
1827 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1825 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001,
1828 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1826 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001,
1829 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1827 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001,
1830 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1828 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001,
1831 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1829 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e,
1832 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1830 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e,
1833 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1831 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e,
1834 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1832 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e,
1835 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1833 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e,
1836 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1834 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e,
1837 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1835 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e
1838}; 1836};
1839 1837
1840static const struct rtwn_bb_prog rtl8188ru_bb_prog = { 1838static const struct rtwn_bb_prog rtl8188ru_bb_prog = {
1841 __arraycount(rtl8188ru_bb_regs), 1839 __arraycount(rtl8188ru_bb_regs),
1842 rtl8188ru_bb_regs, 1840 rtl8188ru_bb_regs,
1843 rtl8188ru_bb_vals, 1841 rtl8188ru_bb_vals,
1844 __arraycount(rtl8188ru_agc_vals), 1842 __arraycount(rtl8188ru_agc_vals),
1845 rtl8188ru_agc_vals 1843 rtl8188ru_agc_vals
1846}; 1844};
1847 1845
1848/* 1846/*
1849 * RF initialization values. 1847 * RF initialization values.
1850 */ 1848 */
1851struct rtwn_rf_prog { 1849struct rtwn_rf_prog {
1852 int count; 1850 int count;
1853 const uint8_t *regs; 1851 const uint8_t *regs;
1854 const uint32_t *vals; 1852 const uint32_t *vals;
1855}; 1853};
1856 1854
1857/* 1855/*
1858 * RTL8192CU and RTL8192CE-VAU. 1856 * RTL8192CU and RTL8192CE-VAU.
1859 */ 1857 */
1860static const uint8_t rtl8192ce_rf1_regs[] = { 1858static const uint8_t rtl8192ce_rf1_regs[] = {
1861 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 1859 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e,
1862 0x0f, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 1860 0x0f, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22,
1863 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2a, 0x2b, 1861 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2a, 0x2b,
1864 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 1862 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b,
1865 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 1863 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b,
1866 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 1864 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a,
1867 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 1865 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c,
1868 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 1866 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b,
1869 0x2c, 0x2a, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 1867 0x2c, 0x2a, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10,
1870 0x11, 0x10, 0x11, 0x10, 0x11, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 1868 0x11, 0x10, 0x11, 0x10, 0x11, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13,
1871 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 1869 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14,
1872 0x14, 0x14, 0x15, 0x15, 0x15, 0x15, 0x16, 0x16, 0x16, 0x16, 0x00, 1870 0x14, 0x14, 0x15, 0x15, 0x15, 0x15, 0x16, 0x16, 0x16, 0x16, 0x00,
1873 0x18, 0xfe, 0xfe, 0x1f, 0xfe, 0xfe, 0x1e, 0x1f, 0x00 1871 0x18, 0xfe, 0xfe, 0x1f, 0xfe, 0xfe, 0x1e, 0x1f, 0x00
1874}; 1872};
1875 1873
1876static const uint32_t rtl8192ce_rf1_vals[] = { 1874static const uint32_t rtl8192ce_rf1_vals[] = {
1877 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1875 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1,
1878 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1876 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255,
1879 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1877 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000,
1880 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0, 1878 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0,
1881 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1879 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808,
1882 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1880 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003,
1883 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1881 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d,
1884 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1882 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333,
1885 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1883 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a,
1886 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1884 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a,
1887 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1885 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d,
1888 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1886 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333,
1889 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1887 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f,
1890 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1888 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500,
1891 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1889 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000,
1892 0x71000, 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, 1890 0x71000, 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f,
1893 0x18493, 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 1891 0x18493, 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c,
1894 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 1892 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424,
1895 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1893 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401,
1896 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1894 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000,
1897 0x30159 1895 0x30159
1898}; 1896};
1899 1897
1900static const uint8_t rtl8192ce_rf2_regs[] = { 1898static const uint8_t rtl8192ce_rf2_regs[] = {
1901 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 1899 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e,
1902 0x0f, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 1900 0x0f, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
1903 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 0x14, 0x14, 0x15, 0x15, 1901 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 0x14, 0x14, 0x15, 0x15,
1904 0x15, 0x15, 0x16, 0x16, 0x16, 0x16 1902 0x15, 0x15, 0x16, 0x16, 0x16, 0x16
1905}; 1903};
1906 1904
1907static const uint32_t rtl8192ce_rf2_vals[] = { 1905static const uint32_t rtl8192ce_rf2_vals[] = {
1908 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1906 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1,
1909 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x32000, 0x71000, 1907 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x32000, 0x71000,
1910 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, 0x18493, 1908 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, 0x18493,
1911 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 0x1944c, 1909 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 0x1944c,
1912 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 0xcf424, 1910 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 0xcf424,
1913 0xe0330, 0xa0330, 0x60330, 0x20330 1911 0xe0330, 0xa0330, 0x60330, 0x20330
1914}; 1912};
1915 1913
1916static const struct rtwn_rf_prog rtl8192ce_rf_prog[] = { 1914static const struct rtwn_rf_prog rtl8192ce_rf_prog[] = {
1917 { 1915 {
1918 __arraycount(rtl8192ce_rf1_regs), 1916 __arraycount(rtl8192ce_rf1_regs),
1919 rtl8192ce_rf1_regs, 1917 rtl8192ce_rf1_regs,
1920 rtl8192ce_rf1_vals 1918 rtl8192ce_rf1_vals
1921 }, 1919 },
1922 { 1920 {
1923 __arraycount(rtl8192ce_rf2_regs), 1921 __arraycount(rtl8192ce_rf2_regs),
1924 rtl8192ce_rf2_regs, 1922 rtl8192ce_rf2_regs,
1925 rtl8192ce_rf2_vals 1923 rtl8192ce_rf2_vals
1926 } 1924 }
1927}; 1925};
1928 1926
1929/* 1927/*
1930 * RTL8188CE-VAU. 1928 * RTL8188CE-VAU.
1931 */ 1929 */
1932static const uint32_t rtl8188ce_rf_vals[] = { 1930static const uint32_t rtl8188ce_rf_vals[] = {
1933 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1931 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1,
1934 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1932 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255,
1935 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1933 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000,
1936 0x00000, 0x01558, 0x00060, 0x00483, 0x4f200, 0xec7d9, 0x577c0, 1934 0x00000, 0x01558, 0x00060, 0x00483, 0x4f200, 0xec7d9, 0x577c0,
1937 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1935 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808,
1938 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1936 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003,
1939 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1937 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d,
1940 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1938 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333,
1941 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1939 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a,
1942 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1940 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a,
1943 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1941 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d,
1944 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1942 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333,
1945 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1943 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f,
1946 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1944 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500,
1947 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1945 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000,
1948 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, 1946 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f,
1949 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, 1947 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020,
1950 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 1948 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424,
1951 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1949 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401,
1952 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1950 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000,
1953 0x30159 1951 0x30159
1954}; 1952};
1955 1953
1956static const struct rtwn_rf_prog rtl8188ce_rf_prog[] = { 1954static const struct rtwn_rf_prog rtl8188ce_rf_prog[] = {
1957 { 1955 {
1958 __arraycount(rtl8192ce_rf1_regs), 1956 __arraycount(rtl8192ce_rf1_regs),
1959 rtl8192ce_rf1_regs, 1957 rtl8192ce_rf1_regs,
1960 rtl8188ce_rf_vals 1958 rtl8188ce_rf_vals
1961 } 1959 }
1962}; 1960};
1963 1961
1964 1962
1965/* 1963/*
1966 * RTL8188CU. 1964 * RTL8188CU.
1967 */ 1965 */
1968static const uint32_t rtl8188cu_rf_vals[] = { 1966static const uint32_t rtl8188cu_rf_vals[] = {
1969 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1967 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1,
1970 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1968 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255,
1971 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1969 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000,
1972 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0, 1970 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0,
1973 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1971 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808,
1974 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1972 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003,
1975 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1973 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d,
1976 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1974 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333,
1977 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1975 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a,
1978 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1976 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a,
1979 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1977 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d,
1980 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1978 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333,
1981 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1979 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f,
1982 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1980 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500,
1983 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1981 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000,
1984 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, 1982 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f,
1985 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, 1983 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020,
1986 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, 1984 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405,
1987 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1985 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401,
1988 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1986 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000,
1989 0x30159 1987 0x30159
1990}; 1988};
1991 1989
1992static const struct rtwn_rf_prog rtl8188cu_rf_prog[] = { 1990static const struct rtwn_rf_prog rtl8188cu_rf_prog[] = {
1993 { 1991 {
1994 __arraycount(rtl8192ce_rf1_regs), 1992 __arraycount(rtl8192ce_rf1_regs),
1995 rtl8192ce_rf1_regs, 1993 rtl8192ce_rf1_regs,
1996 rtl8188cu_rf_vals 1994 rtl8188cu_rf_vals
1997 } 1995 }
1998}; 1996};
1999 1997
2000/* 1998/*
2001 * RTL8188RU. 1999 * RTL8188RU.
2002 */ 2000 */
2003static const uint32_t rtl8188ru_rf_vals[] = { 2001static const uint32_t rtl8188ru_rf_vals[] = {
2004 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb0, 2002 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb0,
2005 0x54867, 0x8992e, 0x0e529, 0x39ce7, 0x00451, 0x00000, 0x00255, 2003 0x54867, 0x8992e, 0x0e529, 0x39ce7, 0x00451, 0x00000, 0x00255,
2006 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 2004 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000,
2007 0x0083c, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x977c0, 2005 0x0083c, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x977c0,
2008 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 2006 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808,
2009 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 2007 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003,
2010 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 2008 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d,
2011 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 2009 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333,
2012 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 2010 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a,
2013 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 2011 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a,
2014 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 2012 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d,
2015 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 2013 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333,
2016 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 2014 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f,
2017 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 2015 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500,
2018 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0xd8000, 2016 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0xd8000,
2019 0x90000, 0x51000, 0x12000, 0x28fb4, 0x24fa8, 0x207a4, 0x1c798, 2017 0x90000, 0x51000, 0x12000, 0x28fb4, 0x24fa8, 0x207a4, 0x1c798,
2020 0x183a4, 0x14398, 0x101a4, 0x0c198, 0x080a4, 0x04098, 0x00014, 2018 0x183a4, 0x14398, 0x101a4, 0x0c198, 0x080a4, 0x04098, 0x00014,
2021 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, 2019 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405,
2022 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 2020 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401,
2023 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 2021 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000,
2024 0x30159 2022 0x30159
2025}; 2023};
2026 2024
2027static const struct rtwn_rf_prog rtl8188ru_rf_prog[] = { 2025static const struct rtwn_rf_prog rtl8188ru_rf_prog[] = {
2028 { 2026 {
2029 __arraycount(rtl8192ce_rf1_regs), 2027 __arraycount(rtl8192ce_rf1_regs),
2030 rtl8192ce_rf1_regs, 2028 rtl8192ce_rf1_regs,
2031 rtl8188ru_rf_vals 2029 rtl8188ru_rf_vals
2032 } 2030 }
2033}; 2031};
2034 2032
2035struct rtwn_txpwr { 2033struct rtwn_txpwr {
2036 uint8_t pwr[3][28]; 2034 uint8_t pwr[3][28];
2037}; 2035};
2038 2036
2039/* 2037/*
2040 * Per RF chain/group/rate Tx gain values. 2038 * Per RF chain/group/rate Tx gain values.
2041 */ 2039 */
2042static const struct rtwn_txpwr rtl8192cu_txagc[] = { 2040static const struct rtwn_txpwr rtl8192cu_txagc[] = {
2043 { { /* Chain 0. */ 2041 { { /* Chain 0. */
2044 { /* Group 0. */ 2042 { /* Group 0. */
2045 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2043 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */
2046 0x0c, 0x0c, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* OFDM6~54. */ 2044 0x0c, 0x0c, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* OFDM6~54. */
2047 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* MCS0~7. */ 2045 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* MCS0~7. */
2048 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02 /* MCS8~15. */ 2046 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02 /* MCS8~15. */
2049 }, 2047 },
2050 { /* Group 1. */ 2048 { /* Group 1. */
2051 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2049 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */
2052 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2050 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */
2053 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2051 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */
2054 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2052 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */
2055 }, 2053 },
2056 { /* Group 2. */ 2054 { /* Group 2. */
2057 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2055 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */
2058 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. */ 2056 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. */
2059 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2057 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */
2060 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2058 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */
2061 } 2059 }
2062 } }, 2060 } },
2063 { { /* Chain 1. */ 2061 { { /* Chain 1. */
2064 { /* Group 0. */ 2062 { /* Group 0. */
2065 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2063 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */
2066 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2064 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */
2067 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2065 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */
2068 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2066 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */
2069 }, 2067 },
2070 { /* Group 1. */ 2068 { /* Group 1. */
2071 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2069 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */
2072 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2070 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */
2073 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2071 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */
2074 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2072 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */
2075 }, 2073 },
2076 { /* Group 2. */ 2074 { /* Group 2. */
2077 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2075 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */
2078 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. */ 2076 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. */
2079 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2077 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */
2080 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2078 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */
2081 } 2079 }
2082 } } 2080 } }
2083}; 2081};
2084 2082
2085static const struct rtwn_txpwr rtl8188ru_txagc[] = { 2083static const struct rtwn_txpwr rtl8188ru_txagc[] = {
2086 { { /* Chain 0. */ 2084 { { /* Chain 0. */
2087 { /* Group 0. */ 2085 { /* Group 0. */
2088 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2086 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */
2089 0x08, 0x08, 0x08, 0x06, 0x06, 0x04, 0x04, 0x00, /* OFDM6~54. */ 2087 0x08, 0x08, 0x08, 0x06, 0x06, 0x04, 0x04, 0x00, /* OFDM6~54. */
2090 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00, /* MCS0~7. */ 2088 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00, /* MCS0~7. */
2091 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00 /* MCS8~15. */ 2089 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00 /* MCS8~15. */
2092 }, 2090 },
2093 { /* Group 1. */ 2091 { /* Group 1. */
2094 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2092 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */
2095 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2093 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */
2096 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2094 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */
2097 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2095 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */
2098 }, 2096 },
2099 { /* Group 2. */ 2097 { /* Group 2. */
2100 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2098 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */
2101 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2099 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */
2102 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2100 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */
2103 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2101 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */
2104 } 2102 }
2105 } } 2103 } }
2106}; 2104};
cvs diff -r1.4 -r1.5 src/sys/dev/pci/rtsx_pci.c (switch to unified diff)

--- src/sys/dev/pci/rtsx_pci.c 2015/09/05 04:56:53 1.4
+++ src/sys/dev/pci/rtsx_pci.c 2015/11/06 14:22:17 1.5
@@ -1,206 +1,190 @@ @@ -1,206 +1,190 @@
1/* $NetBSD: rtsx_pci.c,v 1.4 2015/09/05 04:56:53 nonaka Exp $ */ 1/* $NetBSD: rtsx_pci.c,v 1.5 2015/11/06 14:22:17 nonaka Exp $ */
2/* $OpenBSD: rtsx_pci.c,v 1.7 2014/08/19 17:55:03 phessler Exp $ */ 2/* $OpenBSD: rtsx_pci.c,v 1.7 2014/08/19 17:55:03 phessler Exp $ */
3 3
4 4
5/* 5/*
6 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 6 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
7 * Copyright (c) 2012 Stefan Sperling <stsp@openbsd.org> 7 * Copyright (c) 2012 Stefan Sperling <stsp@openbsd.org>
8 * 8 *
9 * Permission to use, copy, modify, and distribute this software for any 9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above 10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies. 11 * copyright notice and this permission notice appear in all copies.
12 * 12 *
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 */ 20 */
21 21
22#include <sys/cdefs.h> 22#include <sys/cdefs.h>
23__KERNEL_RCSID(0, "$NetBSD: rtsx_pci.c,v 1.4 2015/09/05 04:56:53 nonaka Exp $"); 23__KERNEL_RCSID(0, "$NetBSD: rtsx_pci.c,v 1.5 2015/11/06 14:22:17 nonaka Exp $");
24 24
25#include <sys/param.h> 25#include <sys/param.h>
26#include <sys/device.h> 26#include <sys/device.h>
27#include <sys/systm.h> 27#include <sys/systm.h>
28#include <sys/malloc.h> 28#include <sys/malloc.h>
29#include <sys/pmf.h> 29#include <sys/pmf.h>
30 30
31#include <dev/pci/pcivar.h> 31#include <dev/pci/pcivar.h>
32#include <dev/pci/pcidevs.h> 32#include <dev/pci/pcidevs.h>
33 33
34#include <dev/ic/rtsxreg.h> 34#include <dev/ic/rtsxreg.h>
35#include <dev/ic/rtsxvar.h> 35#include <dev/ic/rtsxvar.h>
36 36
37#include <dev/sdmmc/sdmmcvar.h> 37#include <dev/sdmmc/sdmmcvar.h>
38 38
39#define RTSX_PCI_BAR 0x10 39#define RTSX_PCI_BAR 0x10
40 40
41struct rtsx_pci_softc { 41struct rtsx_pci_softc {
42 struct rtsx_softc sc; 42 struct rtsx_softc sc;
43 pci_chipset_tag_t sc_pc; 43 pci_chipset_tag_t sc_pc;
44 void *sc_ih; 44 void *sc_ih;
45 45
46#ifdef __HAVE_PCI_MSI_MSIX 
47 pci_intr_handle_t *sc_pihp; 46 pci_intr_handle_t *sc_pihp;
48#endif 
49}; 47};
50 48
51static int rtsx_pci_match(device_t , cfdata_t, void *); 49static int rtsx_pci_match(device_t , cfdata_t, void *);
52static void rtsx_pci_attach(device_t, device_t, void *); 50static void rtsx_pci_attach(device_t, device_t, void *);
53static int rtsx_pci_detach(device_t, int); 51static int rtsx_pci_detach(device_t, int);
54 52
55CFATTACH_DECL_NEW(rtsx_pci, sizeof(struct rtsx_pci_softc), 53CFATTACH_DECL_NEW(rtsx_pci, sizeof(struct rtsx_pci_softc),
56 rtsx_pci_match, rtsx_pci_attach, rtsx_pci_detach, NULL); 54 rtsx_pci_match, rtsx_pci_attach, rtsx_pci_detach, NULL);
57 55
58#ifdef RTSX_DEBUG 56#ifdef RTSX_DEBUG
59extern int rtsxdebug; 57extern int rtsxdebug;
60#define DPRINTF(n,s) do { if ((n) <= rtsxdebug) printf s; } while (0) 58#define DPRINTF(n,s) do { if ((n) <= rtsxdebug) printf s; } while (0)
61#else 59#else
62#define DPRINTF(n,s) /**/ 60#define DPRINTF(n,s) /**/
63#endif 61#endif
64 62
65static int 63static int
66rtsx_pci_match(device_t parent, cfdata_t cf, void *aux) 64rtsx_pci_match(device_t parent, cfdata_t cf, void *aux)
67{ 65{
68 struct pci_attach_args *pa = aux; 66 struct pci_attach_args *pa = aux;
69 67
70 /*  68 /*
71 * Explicitly match the UNDEFINED device class only. Some RTS5902 69 * Explicitly match the UNDEFINED device class only. Some RTS5902
72 * devices advertise a SYSTEM/SDHC class in addition to the UNDEFINED 70 * devices advertise a SYSTEM/SDHC class in addition to the UNDEFINED
73 * device class. Let sdhc(4) handle the SYSTEM/SDHC ones. 71 * device class. Let sdhc(4) handle the SYSTEM/SDHC ones.
74 */ 72 */
75 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_REALTEK || 73 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_REALTEK ||
76 PCI_CLASS(pa->pa_class) != PCI_CLASS_UNDEFINED) 74 PCI_CLASS(pa->pa_class) != PCI_CLASS_UNDEFINED)
77 return 0; 75 return 0;
78 76
79 switch (PCI_PRODUCT(pa->pa_id)) { 77 switch (PCI_PRODUCT(pa->pa_id)) {
80 case PCI_PRODUCT_REALTEK_RTS5209: 78 case PCI_PRODUCT_REALTEK_RTS5209:
81 case PCI_PRODUCT_REALTEK_RTS5227: 79 case PCI_PRODUCT_REALTEK_RTS5227:
82 case PCI_PRODUCT_REALTEK_RTS5229: 80 case PCI_PRODUCT_REALTEK_RTS5229:
83 case PCI_PRODUCT_REALTEK_RTL8402: 81 case PCI_PRODUCT_REALTEK_RTL8402:
84 case PCI_PRODUCT_REALTEK_RTL8411: 82 case PCI_PRODUCT_REALTEK_RTL8411:
85 case PCI_PRODUCT_REALTEK_RTL8411B: 83 case PCI_PRODUCT_REALTEK_RTL8411B:
86 return 1; 84 return 1;
87 } 85 }
88 86
89 return 0; 87 return 0;
90} 88}
91 89
92static void 90static void
93rtsx_pci_attach(device_t parent, device_t self, void *aux) 91rtsx_pci_attach(device_t parent, device_t self, void *aux)
94{ 92{
95 struct rtsx_pci_softc *sc = device_private(self); 93 struct rtsx_pci_softc *sc = device_private(self);
96 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 94 struct pci_attach_args *pa = (struct pci_attach_args *)aux;
97 pci_chipset_tag_t pc = pa->pa_pc; 95 pci_chipset_tag_t pc = pa->pa_pc;
98 pcitag_t tag = pa->pa_tag; 96 pcitag_t tag = pa->pa_tag;
99#ifndef __HAVE_PCI_MSI_MSIX 
100 pci_intr_handle_t ih; 
101#endif 
102 pcireg_t reg; 97 pcireg_t reg;
103 char const *intrstr; 98 char const *intrstr;
104 bus_space_tag_t iot; 99 bus_space_tag_t iot;
105 bus_space_handle_t ioh; 100 bus_space_handle_t ioh;
106 bus_size_t size; 101 bus_size_t size;
107 uint32_t flags; 102 uint32_t flags;
108 char intrbuf[PCI_INTRSTR_LEN]; 103 char intrbuf[PCI_INTRSTR_LEN];
109 104
110 sc->sc.sc_dev = self; 105 sc->sc.sc_dev = self;
111 sc->sc_pc = pc; 106 sc->sc_pc = pc;
112 107
113 pci_aprint_devinfo(pa, NULL); 108 pci_aprint_devinfo(pa, NULL);
114 109
115 if ((pci_conf_read(pc, tag, RTSX_CFG_PCI) & RTSX_CFG_ASIC) != 0) { 110 if ((pci_conf_read(pc, tag, RTSX_CFG_PCI) & RTSX_CFG_ASIC) != 0) {
116 aprint_error_dev(self, "no asic\n"); 111 aprint_error_dev(self, "no asic\n");
117 return; 112 return;
118 } 113 }
119 114
120 if (pci_mapreg_map(pa, RTSX_PCI_BAR, PCI_MAPREG_TYPE_MEM, 0, 115 if (pci_mapreg_map(pa, RTSX_PCI_BAR, PCI_MAPREG_TYPE_MEM, 0,
121 &iot, &ioh, NULL, &size)) { 116 &iot, &ioh, NULL, &size)) {
122 aprint_error_dev(self, "couldn't map registers\n"); 117 aprint_error_dev(self, "couldn't map registers\n");
123 return; 118 return;
124 } 119 }
125 120
126#ifdef __HAVE_PCI_MSI_MSIX 
127 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0)) { 121 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0)) {
128 aprint_error_dev(self, "couldn't map interrupt\n"); 122 aprint_error_dev(self, "couldn't map interrupt\n");
129 return; 123 return;
130 } 124 }
131 intrstr = pci_intr_string(pc, sc->sc_pihp[0], intrbuf, sizeof(intrbuf)); 125 intrstr = pci_intr_string(pc, sc->sc_pihp[0], intrbuf, sizeof(intrbuf));
132 sc->sc_ih = pci_intr_establish(pc, sc->sc_pihp[0], IPL_SDMMC, rtsx_intr, 126 sc->sc_ih = pci_intr_establish(pc, sc->sc_pihp[0], IPL_SDMMC, rtsx_intr,
133 &sc->sc); 127 &sc->sc);
134#else /* !__HAVE_PCI_MSI_MSIX */ 
135 if (pci_intr_map(pa, &ih)) { 
136 aprint_error_dev(self, "couldn't map interrupt\n"); 
137 return; 
138 } 
139 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 
140 sc->sc_ih = pci_intr_establish(pc, ih, IPL_SDMMC, rtsx_intr, &sc->sc); 
141#endif /* __HAVE_PCI_MSI_MSIX */ 
142 if (sc->sc_ih == NULL) { 128 if (sc->sc_ih == NULL) {
143 aprint_error_dev(self, "couldn't establish interrupt\n"); 129 aprint_error_dev(self, "couldn't establish interrupt\n");
144 return; 130 return;
145 } 131 }
146 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 132 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
147 133
148 /* Enable the device */ 134 /* Enable the device */
149 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 135 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
150 reg |= PCI_COMMAND_MASTER_ENABLE; 136 reg |= PCI_COMMAND_MASTER_ENABLE;
151 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 137 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg);
152 138
153 /* Power up the device */ 139 /* Power up the device */
154 pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0); 140 pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0);
155 141
156 switch (PCI_PRODUCT(pa->pa_id)) { 142 switch (PCI_PRODUCT(pa->pa_id)) {
157 case PCI_PRODUCT_REALTEK_RTS5209: 143 case PCI_PRODUCT_REALTEK_RTS5209:
158 flags = RTSX_F_5209; 144 flags = RTSX_F_5209;
159 break; 145 break;
160 case PCI_PRODUCT_REALTEK_RTS5227: 146 case PCI_PRODUCT_REALTEK_RTS5227:
161 flags = RTSX_F_5227; 147 flags = RTSX_F_5227;
162 break; 148 break;
163 case PCI_PRODUCT_REALTEK_RTS5229: 149 case PCI_PRODUCT_REALTEK_RTS5229:
164 flags = RTSX_F_5229; 150 flags = RTSX_F_5229;
165 break; 151 break;
166 case PCI_PRODUCT_REALTEK_RTL8402: 152 case PCI_PRODUCT_REALTEK_RTL8402:
167 flags = RTSX_F_8402; 153 flags = RTSX_F_8402;
168 break; 154 break;
169 case PCI_PRODUCT_REALTEK_RTL8411: 155 case PCI_PRODUCT_REALTEK_RTL8411:
170 flags = RTSX_F_8411; 156 flags = RTSX_F_8411;
171 break; 157 break;
172 case PCI_PRODUCT_REALTEK_RTL8411B: 158 case PCI_PRODUCT_REALTEK_RTL8411B:
173 flags = RTSX_F_8411B; 159 flags = RTSX_F_8411B;
174 break; 160 break;
175 default: 161 default:
176 flags = 0; 162 flags = 0;
177 break; 163 break;
178 } 164 }
179 165
180 if (rtsx_attach(&sc->sc, iot, ioh, size, pa->pa_dmat, flags) != 0) { 166 if (rtsx_attach(&sc->sc, iot, ioh, size, pa->pa_dmat, flags) != 0) {
181 aprint_error_dev(self, "couldn't initialize chip\n"); 167 aprint_error_dev(self, "couldn't initialize chip\n");
182 return; 168 return;
183 } 169 }
184 170
185 if (!pmf_device_register1(self, rtsx_suspend, rtsx_resume, 171 if (!pmf_device_register1(self, rtsx_suspend, rtsx_resume,
186 rtsx_shutdown)) 172 rtsx_shutdown))
187 aprint_error_dev(self, "couldn't establish powerhook\n"); 173 aprint_error_dev(self, "couldn't establish powerhook\n");
188} 174}
189 175
190static int 176static int
191rtsx_pci_detach(device_t self, int flags) 177rtsx_pci_detach(device_t self, int flags)
192{ 178{
193 struct rtsx_pci_softc *sc = device_private(self); 179 struct rtsx_pci_softc *sc = device_private(self);
194 int rv; 180 int rv;
195 181
196 rv = rtsx_detach(&sc->sc, flags); 182 rv = rtsx_detach(&sc->sc, flags);
197 if (rv) 183 if (rv)
198 return rv; 184 return rv;
199 185
200 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 186 pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
201#ifdef __HAVE_PCI_MSI_MSIX 
202 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 187 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1);
203#endif /* __HAVE_PCI_MSI_MSIX */ 
204 188
205 return 0; 189 return 0;
206} 190}