Tue Nov 17 00:08:33 2015 UTC ()
Do not clear the PCIe interrupt until we've allowed its cause to become
deasserted.  This halves the PCIe interrupt rate.


(jakllsch)
diff -r1.10 -r1.11 src/sys/arch/arm/nvidia/tegra_pcie.c

cvs diff -r1.10 -r1.11 src/sys/arch/arm/nvidia/tegra_pcie.c (expand / switch to unified diff)

--- src/sys/arch/arm/nvidia/tegra_pcie.c 2015/11/14 03:44:52 1.10
+++ src/sys/arch/arm/nvidia/tegra_pcie.c 2015/11/17 00:08:33 1.11
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: tegra_pcie.c,v 1.10 2015/11/14 03:44:52 jakllsch Exp $ */ 1/* $NetBSD: tegra_pcie.c,v 1.11 2015/11/17 00:08:33 jakllsch Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
@@ -19,27 +19,27 @@ @@ -19,27 +19,27 @@
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE. 26 * SUCH DAMAGE.
27 */ 27 */
28 28
29#include "locators.h" 29#include "locators.h"
30 30
31#include <sys/cdefs.h> 31#include <sys/cdefs.h>
32__KERNEL_RCSID(0, "$NetBSD: tegra_pcie.c,v 1.10 2015/11/14 03:44:52 jakllsch Exp $"); 32__KERNEL_RCSID(0, "$NetBSD: tegra_pcie.c,v 1.11 2015/11/17 00:08:33 jakllsch Exp $");
33 33
34#include <sys/param.h> 34#include <sys/param.h>
35#include <sys/bus.h> 35#include <sys/bus.h>
36#include <sys/device.h> 36#include <sys/device.h>
37#include <sys/intr.h> 37#include <sys/intr.h>
38#include <sys/systm.h> 38#include <sys/systm.h>
39#include <sys/kernel.h> 39#include <sys/kernel.h>
40#include <sys/extent.h> 40#include <sys/extent.h>
41#include <sys/queue.h> 41#include <sys/queue.h>
42#include <sys/mutex.h> 42#include <sys/mutex.h>
43#include <sys/kmem.h> 43#include <sys/kmem.h>
44 44
45#include <arm/cpufunc.h> 45#include <arm/cpufunc.h>
@@ -227,41 +227,47 @@ tegra_pcie_legacy_intr(struct tegra_pcie @@ -227,41 +227,47 @@ tegra_pcie_legacy_intr(struct tegra_pcie
227 msg); 227 msg);
228 } else { 228 } else {
229 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_MSG_REG, msg); 229 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_MSG_REG, msg);
230 rv = 1; 230 rv = 1;
231 } 231 }
232 232
233 return rv; 233 return rv;
234} 234}
235 235
236static int 236static int
237tegra_pcie_intr(void *priv) 237tegra_pcie_intr(void *priv)
238{ 238{
239 struct tegra_pcie_softc *sc = priv; 239 struct tegra_pcie_softc *sc = priv;
 240 int rv;
240 241
241 const uint32_t code = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 242 const uint32_t code = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi,
242 AFI_INTR_CODE_REG); 243 AFI_INTR_CODE_REG);
243 const uint32_t sig = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 244 const uint32_t sig = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi,
244 AFI_INTR_SIGNATURE_REG); 245 AFI_INTR_SIGNATURE_REG);
245 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_INTR_CODE_REG, 0); 
246 246
247 switch (__SHIFTOUT(code, AFI_INTR_CODE_INT_CODE)) { 247 switch (__SHIFTOUT(code, AFI_INTR_CODE_INT_CODE)) {
248 case AFI_INTR_CODE_SM_MSG: 248 case AFI_INTR_CODE_SM_MSG:
249 return tegra_pcie_legacy_intr(sc); 249 rv = tegra_pcie_legacy_intr(sc);
 250 break;
250 default: 251 default:
251 device_printf(sc->sc_dev, "intr: code %#x sig %#x\n", 252 device_printf(sc->sc_dev, "intr: code %#x sig %#x\n",
252 code, sig); 253 code, sig);
253 return 1; 254 rv = 1;
 255 break;
254 } 256 }
 257
 258 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_INTR_CODE_REG, 0);
 259
 260 return rv;
255} 261}
256 262
257static void 263static void
258tegra_pcie_setup(struct tegra_pcie_softc * const sc) 264tegra_pcie_setup(struct tegra_pcie_softc * const sc)
259{ 265{
260 size_t i; 266 size_t i;
261 267
262 /* 268 /*
263 * Map PCI address spaces into ARM address space via 269 * Map PCI address spaces into ARM address space via
264 * HyperTransport-like "FPCI". 270 * HyperTransport-like "FPCI".
265 */ 271 */
266 static const struct { uint32_t size, base, fpci; } pcie_init_table[] = { 272 static const struct { uint32_t size, base, fpci; } pcie_init_table[] = {
267 /* 273 /*