Tue Dec 22 22:10:36 2015 UTC ()

Switch Tegra over to fdt based clocks and reset controls.


(jmcneill)

diff -r1.27 -r1.28 src/sys/arch/arm/nvidia/files.tegra
diff -r1.11 -r1.12 src/sys/arch/arm/nvidia/soc_tegra124.c
diff -r1.11 -r1.12 src/sys/arch/arm/nvidia/tegra_ehci.c
diff -r0 -r1.1 src/sys/arch/arm/nvidia/tegra124_car.c
diff -r0 -r1.1 src/sys/arch/arm/nvidia/tegra124_carreg.h
diff -r0 -r1.1 src/sys/arch/arm/nvidia/tegra_clock.h
diff -r1.8 -r1.9 src/sys/arch/arm/nvidia/tegra_ahcisata.c
diff -r1.8 -r1.9 src/sys/arch/arm/nvidia/tegra_nouveau.c
diff -r1.31 -r0 src/sys/arch/arm/nvidia/tegra_car.c
diff -r1.22 -r0 src/sys/arch/arm/nvidia/tegra_carreg.h
diff -r1.2 -r1.3 src/sys/arch/arm/nvidia/tegra_cec.c
diff -r1.2 -r1.3 src/sys/arch/arm/nvidia/tegra_cpufreq.c
diff -r1.2 -r1.3 src/sys/arch/arm/nvidia/tegra_soctherm.c
diff -r1.2 -r1.3 src/sys/arch/arm/nvidia/tegra_timer.c
diff -r1.4 -r1.5 src/sys/arch/arm/nvidia/tegra_com.c
diff -r1.4 -r1.5 src/sys/arch/arm/nvidia/tegra_drm.c
diff -r1.4 -r1.5 src/sys/arch/arm/nvidia/tegra_usbphy.c
diff -r1.5 -r1.6 src/sys/arch/arm/nvidia/tegra_drm.h
diff -r1.5 -r1.6 src/sys/arch/arm/nvidia/tegra_hdaudio.c
diff -r1.10 -r1.11 src/sys/arch/arm/nvidia/tegra_drm_mode.c
diff -r1.10 -r1.11 src/sys/arch/arm/nvidia/tegra_i2c.c
diff -r1.1 -r1.2 src/sys/arch/arm/nvidia/tegra_fdt.c
diff -r1.1 -r1.2 src/sys/arch/arm/nvidia/tegra_timerreg.h
diff -r1.3 -r1.4 src/sys/arch/arm/nvidia/tegra_fuse.c
diff -r1.14 -r1.15 src/sys/arch/arm/nvidia/tegra_sdhc.c
diff -r1.7 -r1.8 src/sys/arch/arm/nvidia/tegra_soc.c
diff -r1.5 -r1.6 src/sys/arch/evbarm/conf/TEGRA
diff -r1.11 -r1.12 src/sys/arch/evbarm/conf/std.tegra
diff -r1.36 -r1.37 src/sys/arch/evbarm/tegra/tegra_machdep.c

--- src/sys/arch/arm/nvidia/files.tegra 2015/12/13 22:55:05	1.27
+++ src/sys/arch/arm/nvidia/files.tegra 2015/12/22 22:10:36	1.28

 @@ -1,14 +1,14 @@
-#	$NetBSD: files.tegra,v 1.27 2015/12/13 22:55:05 jmcneill Exp $
+#	$NetBSD: files.tegra,v 1.28 2015/12/22 22:10:36 jmcneill Exp $
+#
 # Configuration info for NVIDIA Tegra ARM Peripherals
+#
 include "arch/arm/pic/files.pic"
 include "arch/arm/cortex/files.cortex"
 file	arch/arm/arm32/arm32_boot.c
 file	arch/arm/arm32/arm32_kvminit.c
 file	arch/arm/arm32/arm32_reboot.c
 file	arch/arm/arm32/irq_dispatch.S
 file	arch/arm/arm32/armv7_generic_space.c
 file	arch/arm/arm/bus_space_a4x.S
 @@ -33,29 +33,29 @@ attach	tegramc at fdt with tegra_mc
 file	arch/arm/nvidia/tegra_mc.c		tegra_mc
 # Power management controller
 device	tegrapmc
 attach	tegrapmc at fdt with tegra_pmc
 file	arch/arm/nvidia/tegra_pmc.c		tegra_pmc
 # eFUSE
 device	tegrafuse
 attach	tegrafuse at fdt with tegra_fuse
 file	arch/arm/nvidia/tegra_fuse.c		tegra_fuse
 # Clock and Reset controller
-device	tegracar
+device	tegra124car: clk
-attach	tegracar at fdt with tegra_car
+attach	tegra124car at fdt with tegra124_car
-file	arch/arm/nvidia/tegra_car.c		tegra_car
+file	arch/arm/nvidia/tegra124_car.c		tegra124_car
 # GPIO controller
 device	tegragpio: gpiobus
 attach	tegragpio at fdt with tegra_gpio
 file	arch/arm/nvidia/tegra_gpio.c		tegra_gpio
 # Timers
 device	tegratimer: sysmon_wdog
 attach	tegratimer at fdt with tegra_timer
 file	arch/arm/nvidia/tegra_timer.c		tegra_timer
 # MPIO / Pinmux
 device	tegrampio

--- src/sys/arch/arm/nvidia/soc_tegra124.c 2015/12/01 22:08:13	1.11
+++ src/sys/arch/arm/nvidia/soc_tegra124.c 2015/12/22 22:10:36	1.12

 @@ -1,14 +1,14 @@
-/* $NetBSD: soc_tegra124.c,v 1.11 2015/12/01 22:08:13 jmcneill Exp $ */
+/* $NetBSD: soc_tegra124.c,v 1.12 2015/12/22 22:10:36 jmcneill Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -20,35 +20,39 @@
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include "opt_tegra.h"
 #include "opt_multiprocessor.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: soc_tegra124.c,v 1.11 2015/12/01 22:08:13 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: soc_tegra124.c,v 1.12 2015/12/22 22:10:36 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/cpu.h>
 #include <sys/device.h>
 #include <uvm/uvm_extern.h>
 #include <dev/clk/clk.h>
 #include <dev/i2c/i2cvar.h>
 #include <dev/fdt/fdtvar.h>
 #include <arm/cpufunc.h>
 #include <arm/nvidia/tegra_reg.h>
 #include <arm/nvidia/tegra_pmcreg.h>
 #include <arm/nvidia/tegra_var.h>
 #define EVP_RESET_VECTOR_0_REG	0x100
 #define FUSE_SKU_INFO_REG	0x010
 #define FUSE_CPU_SPEEDO_0_REG	0x014
 #define FUSE_CPU_IDDQ_REG	0x018
 #define FUSE_FT_REV_REG		0x028
 #define FUSE_CPU_SPEEDO_1_REG	0x02c
 @@ -97,39 +101,62 @@ static const u_int tegra124_cpufreq_max[
 };
 static struct tegra124_speedo {
 	u_int cpu_speedo_id;
 	u_int soc_speedo_id;
 	u_int gpu_speedo_id;
 } tegra124_speedo = {
 	.cpu_speedo_id = 0,
 	.soc_speedo_id = 0,
 	.gpu_speedo_id = 0
 };
 static struct clk *tegra124_clk_pllx = NULL;
 void
 tegra124_cpuinit(void)
+{
-	tegra_car_periph_i2c_enable(4, 20400000);
+	const int node = OF_finddevice("/i2c@0,7000d000");
 	if (node == -1) {
 		aprint_error("cpufreq: ERROR: couldn't find i2c@0,7000d000\n");
 		return;
+	}
 	i2c_tag_t ic = fdtbus_get_i2c_tag(node);
 	/* Set VDD_CPU voltage to 1.4V */
 	const u_int target_mv = 1400;
 	const u_int sd0_vsel = (target_mv - 600) / 10;
-	tegra_i2c_dvc_write(0x40, (sd0_vsel << 8) | 00, 2);
+	uint8_t data[2] = { 0x00, sd0_vsel };
 	iic_acquire_bus(ic, I2C_F_POLL);
 	const int error = iic_exec(ic, I2C_OP_WRITE_WITH_STOP, 0x40,
 	    NULL, 0, data, sizeof(data), I2C_F_POLL);
 	iic_release_bus(ic, I2C_F_POLL);
 	if (error) {
 		aprint_error("cpufreq: ERROR: couldn't set VDD_CPU: %d\n",
 		    error);
 		return;
+	}
 	delay(10000);
 	tegra124_speedo_init();
 	tegra124_clk_pllx = clk_get("pll_x");
 	if (tegra124_clk_pllx == NULL) {
 		aprint_error("cpufreq: ERROR: couldn't find pll_x\n");
 		return;
+	}
 	tegra_cpufreq_register(&tegra124_cpufreq_func);
+}
 static void
 tegra124_speedo_init(void)
+{
 	uint32_t sku_id;
 	sku_id = tegra_fuse_read(FUSE_SKU_INFO_REG);
 	tegra124_speedo_init_ids(sku_id);
+}
 static int
 @@ -196,35 +223,33 @@ tegra124_cpufreq_set_rate(u_int rate)
 	if (tegra124_speedo_rate_ok(rate) == false)
 		return EINVAL;
 	for (int i = 0; i < nrates; i++) {
 		if (tegra124_cpufreq_rates[i].rate == rate) {
 			r = &tegra124_cpufreq_rates[i];
 			break;
+		}
+	}
 	if (r == NULL)
 		return EINVAL;
-	tegra_car_pllx_set_rate(r->divm, r->divn, r->divp);
+	return clk_set_rate(tegra124_clk_pllx, r->rate * 1000000);
 	return 0;
+}
 static u_int
 tegra124_cpufreq_get_rate(void)
+{
-	return tegra_car_pllx_rate() / 1000000;
+	return clk_get_rate(tegra124_clk_pllx) / 1000000;
+}
 static size_t
 tegra124_cpufreq_get_available(u_int *pavail, size_t maxavail)
+{
 	const u_int nrates = __arraycount(tegra124_cpufreq_rates);
 	u_int n, cnt;
 	KASSERT(nrates <= maxavail);
 	for (n = 0, cnt = 0; n < nrates; n++) {
 		if (tegra124_speedo_rate_ok(tegra124_cpufreq_rates[n].rate)) {
 			pavail[cnt++] = tegra124_cpufreq_rates[n].rate;

--- src/sys/arch/arm/nvidia/tegra_ehci.c 2015/12/13 17:39:19	1.11
+++ src/sys/arch/arm/nvidia/tegra_ehci.c 2015/12/22 22:10:36	1.12

 @@ -1,14 +1,14 @@
-/* $NetBSD: tegra_ehci.c,v 1.11 2015/12/13 17:39:19 jmcneill Exp $ */
+/* $NetBSD: tegra_ehci.c,v 1.12 2015/12/22 22:10:36 jmcneill Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -17,77 +17,60 @@
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_ehci.c,v 1.11 2015/12/13 17:39:19 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_ehci.c,v 1.12 2015/12/22 22:10:36 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <dev/usb/usb.h>
 #include <dev/usb/usbdi.h>
 #include <dev/usb/usbdivar.h>
 #include <dev/usb/usb_mem.h>
 #include <dev/usb/ehcireg.h>
 #include <dev/usb/ehcivar.h>
 #include <arm/nvidia/tegra_reg.h>
 #include <arm/nvidia/tegra_var.h>
 #include <arm/nvidia/tegra_usbreg.h>
 #include <dev/fdt/fdtvar.h>
 /* XXX */
 static int
 tegra_ehci_addr2port(bus_addr_t addr)
 	switch (addr) {
 	case TEGRA_AHB_A2_BASE + TEGRA_USB1_OFFSET:
 		return 0;
 	case TEGRA_AHB_A2_BASE + TEGRA_USB2_OFFSET:
 		return 1;
 	case TEGRA_AHB_A2_BASE + TEGRA_USB3_OFFSET:
 		return 2;
 	default:
 		return -1;
 #define TEGRA_EHCI_REG_OFFSET	0x100
 static int	tegra_ehci_match(device_t, cfdata_t, void *);
 static void	tegra_ehci_attach(device_t, device_t, void *);
 static void	tegra_ehci_init(struct ehci_softc *);
 struct tegra_ehci_softc {
 	struct ehci_softc	sc;
 	bus_space_tag_t		sc_bst;
 	bus_space_handle_t	sc_bsh;
 	void			*sc_ih;
 	u_int			sc_port;
 };
 static int	tegra_ehci_port_status(struct ehci_softc *sc, uint32_t v,
 		    int i);
 CFATTACH_DECL2_NEW(tegra_ehci, sizeof(struct tegra_ehci_softc),
 	tegra_ehci_match, tegra_ehci_attach, NULL,
 	ehci_activate, NULL, ehci_childdet);
 static int
 tegra_ehci_match(device_t parent, cfdata_t cf, void *aux)
+{
 	const char * const compatible[] = { "nvidia,tegra124-ehci", NULL };
 @@ -102,50 +85,49 @@ tegra_ehci_attach(device_t parent, devic
 	struct tegra_ehci_softc * const sc = device_private(self);
 	struct fdt_attach_args * const faa = aux;
 	char intrstr[128];
 	bus_addr_t addr;
 	bus_size_t size;
 	int error;
 	if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) {
 		aprint_error(": couldn't get registers\n");
 		return;
+	}
 	sc->sc_bst = faa->faa_bst;
 	sc->sc_port = tegra_ehci_addr2port(addr);
 	error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
 	if (error) {
-		aprint_error(": couldn't map USB%d\n", sc->sc_port + 1);
+		aprint_error(": couldn't map USB\n");
 		return;
+	}
 	sc->sc.sc_dev = self;
 	sc->sc.sc_bus.hci_private = &sc->sc;
 	sc->sc.sc_bus.dmatag = faa->faa_dmat;
 	sc->sc.sc_bus.usbrev = USBREV_2_0;
 	sc->sc.sc_ncomp = 0;
 	sc->sc.sc_flags = EHCIF_ETTF;
 	sc->sc.sc_id_vendor = 0x10de;
 	strlcpy(sc->sc.sc_vendor, "Tegra", sizeof(sc->sc.sc_vendor));
 	sc->sc.sc_size = size - TEGRA_EHCI_REG_OFFSET;
 	sc->sc.iot = sc->sc_bst;
 	bus_space_subregion(sc->sc_bst, sc->sc_bsh, TEGRA_EHCI_REG_OFFSET,
 	    sc->sc.sc_size, &sc->sc.ioh);
 	sc->sc.sc_vendor_init = tegra_ehci_init;
 	sc->sc.sc_vendor_port_status = tegra_ehci_port_status;
 	aprint_naive("\n");
-	aprint_normal(": USB%d\n", sc->sc_port + 1);
+	aprint_normal(": USB\n");
 	sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH);
 	if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) {
 		aprint_error_dev(self, "failed to decode interrupt\n");
 		return;
+	}
 	sc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_USB, 0,
 	    ehci_intr, &sc->sc);
 	if (sc->sc_ih == NULL) {
 		aprint_error_dev(self, "couldn't establish interrupt on %s\n",
 		    intrstr);

/* $NetBSD: tegra124_car.c,v 1.1 2015/12/22 22:10:36 jmcneill Exp $ */

/*-
 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: tegra124_car.c,v 1.1 2015/12/22 22:10:36 jmcneill Exp $");

#include <sys/param.h>
#include <sys/bus.h>
#include <sys/device.h>
#include <sys/intr.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/rndpool.h>
#include <sys/rndsource.h>
#include <sys/atomic.h>
#include <sys/kmem.h>

#include <dev/clk/clk_backend.h>

#include <arm/nvidia/tegra_reg.h>
#include <arm/nvidia/tegra124_carreg.h>
#include <arm/nvidia/tegra_clock.h>
#include <arm/nvidia/tegra_pmcreg.h>
#include <arm/nvidia/tegra_var.h>

#include <dev/fdt/fdtvar.h>

static int	tegra124_car_match(device_t, cfdata_t, void *);
static void	tegra124_car_attach(device_t, device_t, void *);

static struct clk *tegra124_car_clock_decode(device_t, const void *, size_t);

static const struct fdtbus_clock_controller_func tegra124_car_fdtclock_funcs = {
	.decode = tegra124_car_clock_decode
};

/* DT clock ID to clock name mappings */
static struct tegra124_car_clock_id {
	u_int		id;
	const char	*name;
} tegra124_car_clock_ids[] = {
	{ 3, "ispb" },
	{ 4, "rtc" },
	{ 5, "timer" },
	{ 6, "uarta" },
	{ 9, "sdmmc2" },
	{ 11, "i2s1" },
	{ 12, "i2c1" },
	{ 14, "sdmmc1" },
	{ 15, "sdmmc4" },
	{ 17, "pwm" },
	{ 18, "i2s2" },
	{ 22, "usbd" },
	{ 23, "isp" },
	{ 26, "disp2" },
	{ 27, "disp1" },
	{ 28, "host1x" },
	{ 29, "vcp" },
	{ 30, "i2s0" },
	{ 32, "mc" },
	{ 34, "apbdma" },
	{ 36, "kbc" },
	{ 40, "kfuse" },
	{ 41, "sbc1" },
	{ 42, "nor" },
	{ 44, "sbc2" },
	{ 46, "sbc3" },
	{ 47, "i2c5" },
	{ 48, "dsia" },
	{ 50, "mipi" },
	{ 51, "hdmi" },
	{ 52, "csi" },
	{ 54, "i2c2" },
	{ 55, "uartc" },
	{ 56, "mipi_cal" },
	{ 57, "emc" },
	{ 58, "usb2" },
	{ 59, "usb3" },
	{ 61, "vde" },
	{ 62, "bsea" },
	{ 63, "bsev" },
	{ 65, "uartd" },
	{ 67, "i2c3" },
	{ 68, "sbc4" },
	{ 69, "sdmmc3" },
	{ 70, "pcie" },
	{ 71, "owr" },
	{ 72, "afi" },
	{ 73, "csite" },
	{ 76, "la" },
	{ 77, "trace" },
	{ 78, "soc_therm" },
	{ 79, "dtv" },
	{ 81, "i2cslow" },
	{ 82, "dsib" },
	{ 83, "tsec" },
	{ 89, "xusb_host" },
	{ 91, "msenc" },
	{ 92, "csus" },
	{ 99, "mselect" },
	{ 100, "tsensor" },
	{ 101, "i2s3" },
	{ 102, "i2s4" },
	{ 103, "i2c4" },
	{ 104, "sbc5" },
	{ 105, "sbc6" },
	{ 106, "d_audio" },
	{ 107, "apbif" },
	{ 108, "dam0" },
	{ 109, "dam1" },
	{ 110, "dam2" },
	{ 111, "hda2codec_2x" },
	{ 113, "audio0_2x" },
	{ 114, "audio1_2x" },
	{ 115, "audio2_2x" },
	{ 116, "audio3_2x" },
	{ 117, "audio4_2x" },
	{ 118, "spdif_2x" },
	{ 119, "actmon" },
	{ 120, "extern1" },
	{ 121, "extern2" },
	{ 122, "extern3" },
	{ 123, "sata_oob" },
	{ 124, "sata" },
	{ 125, "hda" },
	{ 127, "se" },
	{ 128, "hda2hdmi" },
	{ 129, "sata_cold" },
	{ 144, "cilab" },
	{ 145, "cilcd" },
	{ 146, "cile" },
	{ 147, "dsialp" },
	{ 148, "dsiblp" },
	{ 149, "entropy" },
	{ 150, "dds" },
	{ 152, "dp2" },
	{ 153, "amx" },
	{ 154, "adx" },
	{ 156, "xusb_ss" },
	{ 166, "i2c6" },
	{ 171, "vim2_clk" },
	{ 176, "hdmi_audio" },
	{ 177, "clk72mhz" },
	{ 178, "vic03" },
	{ 180, "adx1" },
	{ 181, "dpaux" },
	{ 182, "sor0" },
	{ 184, "gpu" },
	{ 185, "amx1" },
	{ 192, "uartb" },
	{ 193, "vfir" },
	{ 194, "spdif_in" },
	{ 195, "spdif_out" },
	{ 196, "vi" },
	{ 197, "vi_sensor" },
	{ 198, "fuse" },
	{ 199, "fuse_burn" },
	{ 200, "clk_32k" },
	{ 201, "clk_m" },
	{ 202, "clk_m_div2" },
	{ 203, "clk_m_div4" },
	{ 204, "pll_ref" },
	{ 205, "pll_c" },
	{ 206, "pll_c_out1" },
	{ 207, "pll_c2" },
	{ 208, "pll_c3" },
	{ 209, "pll_m" },
	{ 210, "pll_m_out1" },
	{ 211, "pll_p" },
	{ 212, "pll_p_out1" },
	{ 213, "pll_p_out2" },
	{ 214, "pll_p_out3" },
	{ 215, "pll_p_out4" },
	{ 216, "pll_a" },
	{ 217, "pll_a_out0" },
	{ 218, "pll_d" },
	{ 219, "pll_d_out0" },
	{ 220, "pll_d2" },
	{ 221, "pll_d2_out0" },
	{ 222, "pll_u" },
	{ 223, "pll_u_480m" },
	{ 224, "pll_u_60m" },
	{ 225, "pll_u_48m" },
	{ 226, "pll_u_12m" },
	{ 229, "pll_re_vco" },
	{ 230, "pll_re_out" },
	{ 231, "pll_e" },
	{ 232, "spdif_in_sync" },
	{ 233, "i2s0_sync" },
	{ 234, "i2s1_sync" },
	{ 235, "i2s2_sync" },
	{ 236, "i2s3_sync" },
	{ 237, "i2s4_sync" },
	{ 238, "vimclk_sync" },
	{ 239, "audio0" },
	{ 240, "audio1" },
	{ 241, "audio2" },
	{ 242, "audio3" },
	{ 243, "audio4" },
	{ 244, "spdif" },
	{ 245, "clk_out_1" },
	{ 246, "clk_out_2" },
	{ 247, "clk_out_3" },
	{ 248, "blink" },
	{ 252, "xusb_host_src" },
	{ 253, "xusb_falcon_src" },
	{ 254, "xusb_fs_src" },
	{ 255, "xusb_ss_src" },
	{ 256, "xusb_dev_src" },
	{ 257, "xusb_dev" },
	{ 258, "xusb_hs_src" },
	{ 259, "sclk" },
	{ 260, "hclk" },
	{ 261, "pclk" },
	{ 264, "dfll_ref" },
	{ 265, "dfll_soc" },
	{ 266, "vi_sensor2" },
	{ 267, "pll_p_out5" },
	{ 268, "cml0" },
	{ 269, "cml1" },
	{ 270, "pll_c4" },
	{ 271, "pll_dp" },
	{ 272, "pll_e_mux" },
	{ 273, "pll_d_dsi_out" },
	{ 300, "audio0_mux" },
	{ 301, "audio1_mux" },
	{ 302, "audio2_mux" },
	{ 303, "audio3_mux" },
	{ 304, "audio4_mux" },
	{ 305, "spdif_mux" },
	{ 306, "clk_out_1_mux" },
	{ 307, "clk_out_2_mux" },
	{ 308, "clk_out_3_mux" },
	{ 311, "sor0_lvds" },
	{ 312, "xusb_ss_div2" },
	{ 313, "pll_m_ud" },
	{ 314, "pll_c_ud" },
	{ 227, "pll_x" },
	{ 228, "pll_x_out0" },
	{ 262, "cclk_g" },
	{ 263, "cclk_lp" },
	{ 315, "clk_max" },
};

static struct clk *tegra124_car_clock_get(void *, const char *);
static void	tegra124_car_clock_put(void *, struct clk *);
static u_int	tegra124_car_clock_get_rate(void *, struct clk *);
static int	tegra124_car_clock_set_rate(void *, struct clk *, u_int);
static int	tegra124_car_clock_enable(void *, struct clk *);
static int	tegra124_car_clock_disable(void *, struct clk *);
static int	tegra124_car_clock_set_parent(void *, struct clk *,
		    struct clk *);
static struct clk *tegra124_car_clock_get_parent(void *, struct clk *);

static const struct clk_funcs tegra124_car_clock_funcs = {
	.get = tegra124_car_clock_get,
	.put = tegra124_car_clock_put,
	.get_rate = tegra124_car_clock_get_rate,
	.set_rate = tegra124_car_clock_set_rate,
	.enable = tegra124_car_clock_enable,
	.disable = tegra124_car_clock_disable,
	.set_parent = tegra124_car_clock_set_parent,
	.get_parent = tegra124_car_clock_get_parent,
};

#define CLK_FIXED(_name, _rate) {				\
	.base = { .name = (_name) }, .type = TEGRA_CLK_FIXED,	\
	.u = { .fixed = { .rate = (_rate) } }			\
}

#define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) {	\
	.base = { .name = (_name) }, .type = TEGRA_CLK_PLL,	\
	.parent = (_parent),					\
	.u = {							\
		.pll = {					\
			.base_reg = (_base),			\
			.divm_mask = (_divm),			\
			.divn_mask = (_divn),			\
			.divp_mask = (_divp),			\
		}						\
	}							\
}

#define CLK_MUX(_name, _reg, _bits, _p) {			\
	.base = { .name = (_name) }, .type = TEGRA_CLK_MUX,	\
	.u = {							\
		.mux = {					\
			.nparents = __arraycount(_p),		\
			.parents = (_p),			\
			.reg = (_reg),				\
			.bits = (_bits)				\
		}						\
	}							\
}

#define CLK_FIXED_DIV(_name, _parent, _div) {			\
	.base = { .name = (_name) }, .type = TEGRA_CLK_FIXED_DIV, \
	.parent = (_parent),					\
	.u = {							\
		.fixed_div = {					\
			.div = (_div)				\
		}						\
	}							\
}

#define CLK_DIV(_name, _parent, _reg, _bits) {			\
	.base = { .name = (_name) }, .type = TEGRA_CLK_DIV,	\
	.parent = (_parent),					\
	.u = {							\
		.div = {					\
			.reg = (_reg),				\
			.bits = (_bits)				\
		}						\
	}							\
}

#define CLK_GATE(_name, _parent, _set, _clr, _bits) {		\
	.base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \
	.type = TEGRA_CLK_GATE,					\
	.parent = (_parent),					\
	.u = {							\
		.gate = {					\
			.set_reg = (_set),			\
			.clr_reg = (_clr),			\
			.bits = (_bits),			\
		}						\
	}							\
}

#define CLK_GATE_L(_name, _parent, _bits) 			\
	CLK_GATE(_name, _parent,				\
		 CAR_CLK_ENB_L_SET_REG, CAR_CLK_ENB_L_CLR_REG,	\
		 _bits)

#define CLK_GATE_H(_name, _parent, _bits) 			\
	CLK_GATE(_name, _parent,				\
		 CAR_CLK_ENB_H_SET_REG, CAR_CLK_ENB_H_CLR_REG,	\
		 _bits)

#define CLK_GATE_U(_name, _parent, _bits) 			\
	CLK_GATE(_name, _parent,				\
		 CAR_CLK_ENB_U_SET_REG, CAR_CLK_ENB_U_CLR_REG,	\
		 _bits)

#define CLK_GATE_V(_name, _parent, _bits) 			\
	CLK_GATE(_name, _parent,				\
		 CAR_CLK_ENB_V_SET_REG, CAR_CLK_ENB_V_CLR_REG,	\
		 _bits)

#define CLK_GATE_W(_name, _parent, _bits) 			\
	CLK_GATE(_name, _parent,				\
		 CAR_CLK_ENB_W_SET_REG, CAR_CLK_ENB_W_CLR_REG,	\
		 _bits)

#define CLK_GATE_X(_name, _parent, _bits) 			\
	CLK_GATE(_name, _parent,				\
		 CAR_CLK_ENB_X_SET_REG, CAR_CLK_ENB_X_CLR_REG,	\
		 _bits)

#define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits)		\
	CLK_GATE(_name, _parent, _reg, _reg, _bits)

static const char *mux_uart_p[] =
	{ "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0",
	  "pll_m_out0", NULL, "clk_m" };
static const char *mux_sdmmc_p[] =
	{ "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0",
	  "pll_m_out0", "pll_e_out0", "clk_m" };
static const char *mux_i2c_p[] =
	{ "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0",
	  "pll_m_out0", NULL, "clk_m" };
static const char *mux_sata_p[] =
	{ "pll_p_out0", NULL, "pll_c_out0", NULL, "pll_m_out0", NULL, "clk_m" };
static const char *mux_hda_p[] =
	{ "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0",
	  "pll_m_out0", NULL, "clk_m" };
static const char *mux_tsensor_p[] =
	{ "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", "clk_m",
	  NULL, "clk_s" };
static const char *mux_soc_therm_p[] =
	{ "pll_m_out0", "pll_c_out0", "pll_p_out0", "pll_a_out0", "pll_c2_out0",
	  "pll_c3_out0" };
static const char *mux_host1x_p[] =
	{ "pll_m_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0",
	  "pll_p_out0", NULL, "pll_a_out0" };
static const char *mux_disp_p[] =
	{ "pll_p_out0", "pll_m_out0", "pll_d_out0", "pll_a_out0", "pll_c_out0",
	  "pll_d2_out0", "clk_m" };
static const char *mux_hdmi_p[] =
	{ "pll_p_out0", "pll_m_out0", "pll_d_out0", "pll_a_out0", "pll_c_out0",
	  "pll_d2_out0", "clk_m" };

static struct tegra_clk tegra124_car_clocks[] = {
	CLK_FIXED("clk_m", TEGRA_REF_FREQ),

	CLK_PLL("pll_p", "clk_m", CAR_PLLP_BASE_REG,
		CAR_PLLP_BASE_DIVM, CAR_PLLP_BASE_DIVN, CAR_PLLP_BASE_DIVP),
	CLK_PLL("pll_c", "clk_m", CAR_PLLC_BASE_REG,
		CAR_PLLC_BASE_DIVM, CAR_PLLC_BASE_DIVN, CAR_PLLC_BASE_DIVP),
	CLK_PLL("pll_u", "clk_m", CAR_PLLU_BASE_REG,
		CAR_PLLU_BASE_DIVM, CAR_PLLU_BASE_DIVN, CAR_PLLU_BASE_VCO_FREQ),
	CLK_PLL("pll_x", "clk_m", CAR_PLLX_BASE_REG,
		CAR_PLLX_BASE_DIVM, CAR_PLLX_BASE_DIVN, CAR_PLLX_BASE_DIVP),
	CLK_PLL("pll_e", "clk_m", CAR_PLLE_BASE_REG,
		CAR_PLLE_BASE_DIVM, CAR_PLLE_BASE_DIVN, CAR_PLLE_BASE_DIVP_CML),
	CLK_PLL("pll_d", "clk_m", CAR_PLLD_BASE_REG,
		CAR_PLLD_BASE_DIVM, CAR_PLLD_BASE_DIVN, CAR_PLLD_BASE_DIVP),
	CLK_PLL("pll_d2", "clk_m", CAR_PLLD2_BASE_REG,
		CAR_PLLD2_BASE_DIVM, CAR_PLLD2_BASE_DIVN, CAR_PLLD2_BASE_DIVP),

	CLK_FIXED_DIV("pll_p_out0", "pll_p", 1),
	CLK_FIXED_DIV("pll_u_480", "pll_u", 1),
	CLK_FIXED_DIV("pll_u_60", "pll_u", 8),
	CLK_FIXED_DIV("pll_u_48", "pll_u", 10),
	CLK_FIXED_DIV("pll_u_12", "pll_u", 40),
	CLK_FIXED_DIV("pll_d_out", "pll_d", 1),
	CLK_FIXED_DIV("pll_d_out0", "pll_d", 2),
	CLK_FIXED_DIV("pll_d2_out0", "pll_d2", 1),

	CLK_MUX("mux_uarta", CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_SRC,
		mux_uart_p),
	CLK_MUX("mux_uartb", CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_SRC,
		mux_uart_p),
	CLK_MUX("mux_uartc", CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_SRC,
		mux_uart_p),
	CLK_MUX("mux_uartd", CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_SRC,
		mux_uart_p),
	CLK_MUX("mux_sdmmc1", CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_SRC,
	 	mux_sdmmc_p),
	CLK_MUX("mux_sdmmc2", CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_SRC,
	 	mux_sdmmc_p),
	CLK_MUX("mux_sdmmc3", CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_SRC,
	 	mux_sdmmc_p),
	CLK_MUX("mux_sdmmc4", CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_SRC,
	 	mux_sdmmc_p),
	CLK_MUX("mux_i2c1", CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p),
	CLK_MUX("mux_i2c2", CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p),
	CLK_MUX("mux_i2c3", CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p),
	CLK_MUX("mux_i2c4", CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p),
	CLK_MUX("mux_i2c5", CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p),
	CLK_MUX("mux_i2c6", CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p),
	CLK_MUX("mux_sata_oob",
		CAR_CLKSRC_SATA_OOB_REG, CAR_CLKSRC_SATA_OOB_SRC, mux_sata_p),
	CLK_MUX("mux_sata",
		CAR_CLKSRC_SATA_REG, CAR_CLKSRC_SATA_SRC, mux_sata_p),
	CLK_MUX("mux_hda2codec_2x",
		CAR_CLKSRC_HDA2CODEC_2X_REG, CAR_CLKSRC_HDA2CODEC_2X_SRC,
		mux_hda_p),
	CLK_MUX("mux_hda",
		CAR_CLKSRC_HDA_REG, CAR_CLKSRC_HDA_SRC, mux_hda_p),
	CLK_MUX("mux_soc_therm",
		CAR_CLKSRC_SOC_THERM_REG, CAR_CLKSRC_SOC_THERM_SRC,
		mux_soc_therm_p),
	CLK_MUX("mux_tsensor",
		CAR_CLKSRC_TSENSOR_REG, CAR_CLKSRC_TSENSOR_SRC,
		mux_tsensor_p),
	CLK_MUX("mux_host1x",
		CAR_CLKSRC_HOST1X_REG, CAR_CLKSRC_HOST1X_SRC,
		mux_host1x_p),
	CLK_MUX("mux_disp1",
		CAR_CLKSRC_DISP1_REG, CAR_CLKSRC_DISP_SRC,
		mux_disp_p),
	CLK_MUX("mux_disp2",
		CAR_CLKSRC_DISP2_REG, CAR_CLKSRC_DISP_SRC,
		mux_disp_p),
	CLK_MUX("mux_hdmi",
		CAR_CLKSRC_HDMI_REG, CAR_CLKSRC_HDMI_SRC,
		mux_hdmi_p),

	CLK_DIV("div_uarta", "mux_uarta",
		CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_DIV),
	CLK_DIV("div_uartb", "mux_uartb",
		CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_DIV),
	CLK_DIV("div_uartc", "mux_uartc",
		CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_DIV),
	CLK_DIV("div_uartd", "mux_uartd",
		CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_DIV),
	CLK_DIV("div_sdmmc1", "mux_sdmmc1",
		CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_DIV),
	CLK_DIV("div_sdmmc2", "mux_sdmmc2",
		CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_DIV),
	CLK_DIV("div_sdmmc3", "mux_sdmmc3",
		CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_DIV),
	CLK_DIV("div_sdmmc4", "mux_sdmmc4",
		CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_DIV),
	CLK_DIV("div_i2c1", "mux_i2c1", 
		CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_DIV),
	CLK_DIV("div_i2c2", "mux_i2c2", 
		CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_DIV),
	CLK_DIV("div_i2c3", "mux_i2c3", 
		CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_DIV),
	CLK_DIV("div_i2c4", "mux_i2c4", 
		CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_DIV),
	CLK_DIV("div_i2c5", "mux_i2c5", 
		CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_DIV),
	CLK_DIV("div_i2c6", "mux_i2c6", 
		CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_DIV),
	CLK_DIV("div_sata_oob", "mux_sata_oob",
		CAR_CLKSRC_SATA_OOB_REG, CAR_CLKSRC_SATA_OOB_DIV),
	CLK_DIV("div_sata", "mux_sata",
		CAR_CLKSRC_SATA_REG, CAR_CLKSRC_SATA_DIV),
	CLK_DIV("div_hda2codec_2x", "mux_hda2codec_2x",
		CAR_CLKSRC_HDA2CODEC_2X_REG, CAR_CLKSRC_HDA2CODEC_2X_DIV),
	CLK_DIV("div_hda", "mux_hda",
		CAR_CLKSRC_HDA_REG, CAR_CLKSRC_HDA_DIV),
	CLK_DIV("div_soc_therm", "mux_soc_therm",
		CAR_CLKSRC_SOC_THERM_REG, CAR_CLKSRC_SOC_THERM_DIV),
	CLK_DIV("div_tsensor", "mux_tsensor",
		CAR_CLKSRC_TSENSOR_REG, CAR_CLKSRC_TSENSOR_DIV),
	CLK_DIV("div_host1x", "mux_host1x",
		CAR_CLKSRC_HOST1X_REG, CAR_CLKSRC_HOST1X_CLK_DIVISOR),
	CLK_DIV("div_hdmi", "mux_hdmi",
		CAR_CLKSRC_HDMI_REG, CAR_CLKSRC_HDMI_DIV),
	CLK_DIV("div_pll_p_out5", "pll_p",
		CAR_PLLP_OUTC_REG, CAR_PLLP_OUTC_OUT5_RATIO),

	CLK_GATE_L("uarta", "div_uarta", CAR_DEV_L_UARTA),
	CLK_GATE_L("uartb", "div_uartb", CAR_DEV_L_UARTB),
	CLK_GATE_H("uartc", "div_uartc", CAR_DEV_H_UARTC),
	CLK_GATE_U("uartd", "div_uartd", CAR_DEV_U_UARTD),
	CLK_GATE_L("sdmmc1", "div_sdmmc1", CAR_DEV_L_SDMMC1),
	CLK_GATE_L("sdmmc2", "div_sdmmc2", CAR_DEV_L_SDMMC2),
	CLK_GATE_U("sdmmc3", "div_sdmmc3", CAR_DEV_U_SDMMC3),
	CLK_GATE_L("sdmmc4", "div_sdmmc4", CAR_DEV_L_SDMMC4),
	CLK_GATE_L("i2c1", "div_i2c1", CAR_DEV_L_I2C1),
	CLK_GATE_H("i2c2", "div_i2c2", CAR_DEV_H_I2C2),
	CLK_GATE_U("i2c3", "div_i2c3", CAR_DEV_U_I2C3),
	CLK_GATE_V("i2c4", "div_i2c4", CAR_DEV_V_I2C4),
	CLK_GATE_H("i2c5", "div_i2c5", CAR_DEV_H_I2C5),
	CLK_GATE_X("i2c6", "div_i2c6", CAR_DEV_X_I2C6),
	CLK_GATE_L("usbd", "pll_u_480", CAR_DEV_L_USBD),
	CLK_GATE_H("usb2", "pll_u_480", CAR_DEV_H_USB2),
	CLK_GATE_H("usb3", "pll_u_480", CAR_DEV_H_USB3),
	CLK_GATE_V("sata_oob", "div_sata_oob", CAR_DEV_V_SATA_OOB),
	CLK_GATE_V("sata", "div_sata", CAR_DEV_V_SATA),
	CLK_GATE_SIMPLE("cml0", "pll_e",
		CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML0_OEN),
	CLK_GATE_SIMPLE("cml1", "pll_e",
		CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML1_OEN),
	CLK_GATE_V("hda2codec_2x", "div_hda2codec_2x", CAR_DEV_V_HDA2CODEC_2X),
	CLK_GATE_V("hda", "div_hda", CAR_DEV_V_HDA),
	CLK_GATE_W("hda2hdmi", "clk_m", CAR_DEV_W_HDA2HDMICODEC),
	CLK_GATE_H("fuse", "clk_m", CAR_DEV_H_FUSE),
	CLK_GATE_U("soc_therm", "div_soc_therm", CAR_DEV_U_SOC_THERM),
	CLK_GATE_V("tsensor", "div_tsensor", CAR_DEV_V_TSENSOR),
	CLK_GATE_SIMPLE("watchdog", "clk_m", CAR_RST_SOURCE_REG,
		CAR_RST_SOURCE_WDT_EN|CAR_RST_SOURCE_WDT_SYS_RST_EN),
	CLK_GATE_L("host1x", "div_host1x", CAR_DEV_L_HOST1X),
	CLK_GATE_L("disp1", "mux_disp1", CAR_DEV_L_DISP1),
	CLK_GATE_L("disp2", "mux_disp2", CAR_DEV_L_DISP2),
	CLK_GATE_H("hdmi", "div_hdmi", CAR_DEV_H_HDMI),
	CLK_GATE_SIMPLE("pll_p_out5", "div_pllp_out5",
		CAR_PLLP_OUTC_REG, CAR_PLLP_OUTC_OUT5_CLKEN),
};

struct tegra124_car_rst {
	u_int	set_reg;
	u_int	clr_reg;
	u_int	mask;
};

static struct tegra124_car_reset_reg {
	u_int	set_reg;
	u_int	clr_reg;
} tegra124_car_reset_regs[] = {
	{ CAR_RST_DEV_L_SET_REG, CAR_RST_DEV_L_CLR_REG },
	{ CAR_RST_DEV_H_SET_REG, CAR_RST_DEV_H_CLR_REG },
	{ CAR_RST_DEV_U_SET_REG, CAR_RST_DEV_U_CLR_REG },
	{ CAR_RST_DEV_V_SET_REG, CAR_RST_DEV_V_CLR_REG },
	{ CAR_RST_DEV_W_SET_REG, CAR_RST_DEV_W_CLR_REG },
	{ CAR_RST_DEV_X_SET_REG, CAR_RST_DEV_X_CLR_REG },
};

static void *	tegra124_car_reset_acquire(device_t, const void *, size_t);
static void	tegra124_car_reset_release(device_t, void *);
static int	tegra124_car_reset_assert(device_t, void *);
static int	tegra124_car_reset_deassert(device_t, void *);

static const struct fdtbus_reset_controller_func tegra124_car_fdtreset_funcs = {
	.acquire = tegra124_car_reset_acquire,
	.release = tegra124_car_reset_release,
	.reset_assert = tegra124_car_reset_assert,
	.reset_deassert = tegra124_car_reset_deassert,
};

struct tegra124_car_softc {
	device_t		sc_dev;
	bus_space_tag_t		sc_bst;
	bus_space_handle_t	sc_bsh;

	u_int			sc_clock_cells;
	u_int			sc_reset_cells;

	kmutex_t		sc_intr_lock;
	kmutex_t		sc_rnd_lock;
	u_int			sc_bytes_wanted;
	void			*sc_sih;
	krndsource_t		sc_rndsource;
};

static void	tegra124_car_init(struct tegra124_car_softc *);
static void	tegra124_car_utmip_init(struct tegra124_car_softc *);

static void	tegra124_car_rnd_attach(device_t);
static void	tegra124_car_rnd_intr(void *);
static void	tegra124_car_rnd_callback(size_t, void *);

CFATTACH_DECL_NEW(tegra124_car, sizeof(struct tegra124_car_softc),
	tegra124_car_match, tegra124_car_attach, NULL, NULL);

static int
tegra124_car_match(device_t parent, cfdata_t cf, void *aux)
{
	const char * const compatible[] = { "nvidia,tegra124-car", NULL };
	struct fdt_attach_args * const faa = aux;

#if 0
	return of_match_compatible(faa->faa_phandle, compatible);
#else
	if (of_match_compatible(faa->faa_phandle, compatible) == 0)
		return 0;

	return 999;
#endif
}

static void
tegra124_car_attach(device_t parent, device_t self, void *aux)
{
	struct tegra124_car_softc * const sc = device_private(self);
	struct fdt_attach_args * const faa = aux;
	const int phandle = faa->faa_phandle;
	bus_addr_t addr;
	bus_size_t size;
	int error;

	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
		aprint_error(": couldn't get registers\n");
		return;
	}

	sc->sc_dev = self;
	sc->sc_bst = faa->faa_bst;
	error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
	if (error) {
		aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error);
		return;
	}
	if (of_getprop_uint32(phandle, "#clock-cells", &sc->sc_clock_cells))
		sc->sc_clock_cells = 1;
	if (of_getprop_uint32(phandle, "#reset-cells", &sc->sc_reset_cells))
		sc->sc_reset_cells = 1;

	aprint_naive("\n");
	aprint_normal(": CAR\n");

	clk_backend_register("tegra124", &tegra124_car_clock_funcs, sc);

	fdtbus_register_clock_controller(self, phandle,
	    &tegra124_car_fdtclock_funcs);
	fdtbus_register_reset_controller(self, phandle,
	    &tegra124_car_fdtreset_funcs);

	tegra124_car_init(sc);

	config_interrupts(self, tegra124_car_rnd_attach);
}

static void
tegra124_car_init(struct tegra124_car_softc *sc)
{
	tegra124_car_utmip_init(sc);
}

static void
tegra124_car_utmip_init(struct tegra124_car_softc *sc)
{
	bus_space_tag_t bst = sc->sc_bst;
	bus_space_handle_t bsh = sc->sc_bsh;

	const u_int enable_dly_count = 0x02;
	const u_int stable_count = 0x2f;
	const u_int active_dly_count = 0x04;
	const u_int xtal_freq_count = 0x76;

	tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG,
	    __SHIFTIN(stable_count, CAR_UTMIP_PLL_CFG2_STABLE_COUNT) |
	    __SHIFTIN(active_dly_count, CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT),
	    CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN |
	    CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN |
	    CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN |
	    CAR_UTMIP_PLL_CFG2_STABLE_COUNT |
	    CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT);

        tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG,
	    __SHIFTIN(enable_dly_count, CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT) |
	    __SHIFTIN(xtal_freq_count, CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT),
	    CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT |
	    CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT);

	tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG,
	    0,
	    CAR_UTMIP_PLL_CFG1_PLLU_POWERDOWN |
	    CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN);

}

static void
tegra124_car_rnd_attach(device_t self)
{
	struct tegra124_car_softc * const sc = device_private(self);

	mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SERIAL);
	mutex_init(&sc->sc_rnd_lock, MUTEX_DEFAULT, IPL_SERIAL);
	sc->sc_bytes_wanted = 0;
	sc->sc_sih = softint_establish(SOFTINT_SERIAL|SOFTINT_MPSAFE,
	    tegra124_car_rnd_intr, sc);
	if (sc->sc_sih == NULL) {
		aprint_error_dev(sc->sc_dev, "couldn't establish softint\n");
		return;
	}

	rndsource_setcb(&sc->sc_rndsource, tegra124_car_rnd_callback, sc);
	rnd_attach_source(&sc->sc_rndsource, device_xname(sc->sc_dev),
	    RND_TYPE_RNG, RND_FLAG_COLLECT_VALUE|RND_FLAG_HASCB);
}

static void
tegra124_car_rnd_intr(void *priv)
{
	struct tegra124_car_softc * const sc = priv;
	uint16_t buf[512];
	uint32_t cnt;

	mutex_enter(&sc->sc_intr_lock);
	while (sc->sc_bytes_wanted) {
		const u_int nbytes = MIN(sc->sc_bytes_wanted, 1024);
		for (cnt = 0; cnt < sc->sc_bytes_wanted / 2; cnt++) {
			buf[cnt] = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
			    CAR_PLL_LFSR_REG) & 0xffff;
		}
		mutex_exit(&sc->sc_intr_lock);
		mutex_enter(&sc->sc_rnd_lock);
		rnd_add_data(&sc->sc_rndsource, buf, nbytes, nbytes * NBBY);
		mutex_exit(&sc->sc_rnd_lock);
		mutex_enter(&sc->sc_intr_lock);
		sc->sc_bytes_wanted -= MIN(sc->sc_bytes_wanted, nbytes);
	}
	explicit_memset(buf, 0, sizeof(buf));
	mutex_exit(&sc->sc_intr_lock);
}

static void
tegra124_car_rnd_callback(size_t bytes_wanted, void *priv)
{
	struct tegra124_car_softc * const sc = priv;

	mutex_enter(&sc->sc_intr_lock);
	if (sc->sc_bytes_wanted == 0) {
		softint_schedule(sc->sc_sih);
	}
	if (bytes_wanted > (UINT_MAX - sc->sc_bytes_wanted)) {
		sc->sc_bytes_wanted = UINT_MAX;
	} else {
		sc->sc_bytes_wanted += bytes_wanted;
	}
	mutex_exit(&sc->sc_intr_lock);
}

static struct tegra_clk *
tegra124_car_clock_find(const char *name)
{
	u_int n;

	for (n = 0; n < __arraycount(tegra124_car_clocks); n++) {
		if (strcmp(tegra124_car_clocks[n].base.name, name) == 0) {
			return &tegra124_car_clocks[n];
		}
	}

	return NULL;
}

static struct tegra_clk *
tegra124_car_clock_find_by_id(u_int clock_id)
{
	u_int n;

	for (n = 0; n < __arraycount(tegra124_car_clock_ids); n++) {
		if (tegra124_car_clock_ids[n].id == clock_id) {
			const char *name = tegra124_car_clock_ids[n].name;
			return tegra124_car_clock_find(name);
		}
	}

	return NULL;
}

static struct clk *
tegra124_car_clock_decode(device_t dev, const void *data, size_t len)
{
	struct tegra124_car_softc * const sc = device_private(dev);
	struct tegra_clk *tclk;

	if (len != sc->sc_clock_cells * 4) {
		return NULL;
	}

	const u_int clock_id = be32dec(data);

	tclk = tegra124_car_clock_find_by_id(clock_id);
	if (tclk)
		return TEGRA_CLK_BASE(tclk);

	return NULL;
}

static struct clk *
tegra124_car_clock_get(void *priv, const char *name)
{
	struct tegra_clk *tclk;

	tclk = tegra124_car_clock_find(name);
	if (tclk == NULL)
		return NULL;

	atomic_inc_uint(&tclk->refcnt);

	return TEGRA_CLK_BASE(tclk);
}

static void
tegra124_car_clock_put(void *priv, struct clk *clk)
{
	struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);

	KASSERT(tclk->refcnt > 0);

	atomic_dec_uint(&tclk->refcnt);
}

static u_int
tegra124_car_clock_get_rate_pll(struct tegra124_car_softc *sc,
    struct tegra_clk *tclk)
{
	struct tegra_pll_clk *tpll = &tclk->u.pll;
	struct tegra_clk *tclk_parent;
	bus_space_tag_t bst = sc->sc_bst;
	bus_space_handle_t bsh = sc->sc_bsh;
	u_int divm, divn, divp;
	uint64_t rate;

	KASSERT(tclk->type == TEGRA_CLK_PLL);

	tclk_parent = tegra124_car_clock_find(tclk->parent);
	KASSERT(tclk_parent != NULL);

	const u_int rate_parent = tegra124_car_clock_get_rate(sc,
	    TEGRA_CLK_BASE(tclk_parent));

	const uint32_t base = bus_space_read_4(bst, bsh, tpll->base_reg);
	divm = __SHIFTOUT(base, tpll->divm_mask);
	divn = __SHIFTOUT(base, tpll->divn_mask);
	if (tpll->base_reg == CAR_PLLU_BASE_REG) {
		divp = __SHIFTOUT(base, tpll->divp_mask) ? 0 : 1;
	} else {
		divp = __SHIFTOUT(base, tpll->divp_mask);
	}

	rate = (uint64_t)rate_parent * divn;
	return rate / (divm << divp);
}

static int
tegra124_car_clock_set_rate_pll(struct tegra124_car_softc *sc,
    struct tegra_clk *tclk, u_int rate)
{
	struct tegra_pll_clk *tpll = &tclk->u.pll;
	bus_space_tag_t bst = sc->sc_bst;
	bus_space_handle_t bsh = sc->sc_bsh;
	struct clk *clk_parent;
	uint32_t bp, base;

	clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk));
	if (clk_parent == NULL)
		return EIO;
	const u_int rate_parent = tegra124_car_clock_get_rate(sc, clk_parent);
	if (rate_parent == 0)
		return EIO;

	if (tpll->base_reg == CAR_PLLX_BASE_REG) {
		const u_int divm = 1;
		const u_int divn = rate / rate_parent;
		const u_int divp = 0;

		bp = bus_space_read_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG);
		bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE;
		bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE,
				CAR_CCLKG_BURST_POLICY_CPU_STATE);
		bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE;
		bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM,
				CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE);
		bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp);

		base = bus_space_read_4(bst, bsh, CAR_PLLX_BASE_REG);
		base &= ~CAR_PLLX_BASE_DIVM;
		base &= ~CAR_PLLX_BASE_DIVN;
		base &= ~CAR_PLLX_BASE_DIVP;
		base |= __SHIFTIN(divm, CAR_PLLX_BASE_DIVM);
		base |= __SHIFTIN(divn, CAR_PLLX_BASE_DIVN);
		base |= __SHIFTIN(divp, CAR_PLLX_BASE_DIVP);
		bus_space_write_4(bst, bsh, CAR_PLLX_BASE_REG, base);

		tegra_reg_set_clear(bst, bsh, CAR_PLLX_MISC_REG,
		    CAR_PLLX_MISC_LOCK_ENABLE, 0);
		do {
			delay(2);
			base = bus_space_read_4(bst, bsh, tpll->base_reg);
		} while ((base & CAR_PLLX_BASE_LOCK) == 0);
		delay(100);

		bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE;
		bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN,
				CAR_CCLKG_BURST_POLICY_CPU_STATE);
		bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE;
		bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ,
				CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE);
		bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp);

		return 0;
	} else if (tpll->base_reg == CAR_PLLD2_BASE_REG) {
		const u_int divm = 1;
		const u_int pldiv = 1;
		const u_int divn = (rate << pldiv) / rate_parent;

		/* Set frequency */
		tegra_reg_set_clear(bst, bsh, tpll->base_reg,
		    __SHIFTIN(divm, CAR_PLLD2_BASE_DIVM) |
		    __SHIFTIN(divn, CAR_PLLD2_BASE_DIVN) |
		    __SHIFTIN(pldiv, CAR_PLLD2_BASE_DIVP),
		    CAR_PLLD2_BASE_REF_SRC_SEL |
		    CAR_PLLD2_BASE_DIVM |
		    CAR_PLLD2_BASE_DIVN |
		    CAR_PLLD2_BASE_DIVP);

		return 0;
	} else {
		/* TODO */
		return EOPNOTSUPP;
	}
}

static int
tegra124_car_clock_set_parent_mux(struct tegra124_car_softc *sc,
    struct tegra_clk *tclk, struct tegra_clk *tclk_parent)
{
	struct tegra_mux_clk *tmux = &tclk->u.mux;
	bus_space_tag_t bst = sc->sc_bst;
	bus_space_handle_t bsh = sc->sc_bsh;
	uint32_t v;
	u_int src;

	KASSERT(tclk->type == TEGRA_CLK_MUX);

	for (src = 0; src < tmux->nparents; src++) {
		if (tmux->parents[src] == NULL) {
			continue;
		}
		if (strcmp(tmux->parents[src], tclk_parent->base.name) == 0) {
			break;
		}
	}
	if (src == tmux->nparents) {
		return EINVAL;
	}

	if (tmux->reg == CAR_CLKSRC_HDMI_REG &&
	    src == CAR_CLKSRC_HDMI_SRC_PLLD2_OUT0) {
		/* Change IDDQ from 1 to 0 */
		tegra_reg_set_clear(bst, bsh, CAR_PLLD2_BASE_REG,
		    0, CAR_PLLD2_BASE_IDDQ);
		delay(2);

		/* Enable lock */
		tegra_reg_set_clear(bst, bsh, CAR_PLLD2_MISC_REG,
		    CAR_PLLD2_MISC_LOCK_ENABLE, 0);

		/* Enable PLLD2 */
		tegra_reg_set_clear(bst, bsh, CAR_PLLD2_BASE_REG,
		    CAR_PLLD2_BASE_ENABLE, 0);

		/* Wait for lock */
		do {
			delay(2);
			v = bus_space_read_4(bst, bsh, CAR_PLLD2_BASE_REG);
		} while ((v & CAR_PLLD2_BASE_LOCK) == 0);

		delay(200);
	}

	v = bus_space_read_4(bst, bsh, tmux->reg);
	v &= ~tmux->bits;
	v |= __SHIFTIN(src, tmux->bits);
	bus_space_write_4(bst, bsh, tmux->reg, v);

	return 0;
}

static struct tegra_clk *
tegra124_car_clock_get_parent_mux(struct tegra124_car_softc *sc,
    struct tegra_clk *tclk)
{
	struct tegra_mux_clk *tmux = &tclk->u.mux;
	bus_space_tag_t bst = sc->sc_bst;
	bus_space_handle_t bsh = sc->sc_bsh;

	KASSERT(tclk->type == TEGRA_CLK_MUX);

	const uint32_t v = bus_space_read_4(bst, bsh, tmux->reg);
	const u_int src = __SHIFTOUT(v, tmux->bits);

	KASSERT(src < tmux->nparents);

	if (tmux->parents[src] == NULL) {
		return NULL;
	}

	return tegra124_car_clock_find(tmux->parents[src]);
}

static u_int
tegra124_car_clock_get_rate_fixed_div(struct tegra124_car_softc *sc,
    struct tegra_clk *tclk)
{
	struct tegra_fixed_div_clk *tfixed_div = &tclk->u.fixed_div;
	struct clk *clk_parent;

	clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk));
	if (clk_parent == NULL)
		return 0;
	const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent);

	return parent_rate / tfixed_div->div;
}

static u_int
tegra124_car_clock_get_rate_div(struct tegra124_car_softc *sc,
    struct tegra_clk *tclk)
{
	struct tegra_div_clk *tdiv = &tclk->u.div;
	bus_space_tag_t bst = sc->sc_bst;
	bus_space_handle_t bsh = sc->sc_bsh;
	struct clk *clk_parent;
	u_int div;

	KASSERT(tclk->type == TEGRA_CLK_DIV);

	clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk));
	const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent);

	const uint32_t v = bus_space_read_4(bst, bsh, tdiv->reg);
	const u_int raw_div = __SHIFTOUT(v, tdiv->bits);

	switch (tdiv->reg) {
	case CAR_CLKSRC_UARTA_REG:
	case CAR_CLKSRC_UARTB_REG:
	case CAR_CLKSRC_UARTC_REG:
	case CAR_CLKSRC_UARTD_REG:
		if (v & CAR_CLKSRC_UART_DIV_ENB) {
			div = raw_div * 2;
		} else {
			div = 2;
		}
		break;
	default:
		div = raw_div * 2;
		break;
	}

	return (parent_rate * 2) / div;
}

static int
tegra124_car_clock_set_rate_div(struct tegra124_car_softc *sc,
    struct tegra_clk *tclk, u_int rate)
{
	struct tegra_div_clk *tdiv = &tclk->u.div;
	bus_space_tag_t bst = sc->sc_bst;
	bus_space_handle_t bsh = sc->sc_bsh;
	struct clk *clk_parent;
	uint32_t v;

	KASSERT(tclk->type == TEGRA_CLK_DIV);

	clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk));
	if (clk_parent == NULL)
		return EINVAL;
	const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent);

	v = bus_space_read_4(bst, bsh, tdiv->reg);

	switch (tdiv->reg) {
	case CAR_CLKSRC_UARTA_REG:
	case CAR_CLKSRC_UARTB_REG:
	case CAR_CLKSRC_UARTC_REG:
	case CAR_CLKSRC_UARTD_REG:
		if (rate == parent_rate) {
			v &= ~CAR_CLKSRC_UART_DIV_ENB;
		} else {
			v |= CAR_CLKSRC_UART_DIV_ENB;
		}
		break;
	case CAR_CLKSRC_SATA_REG:
		if (rate) {
			tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG,
			    0, CAR_SATA_PLL_CFG0_PADPLL_RESET_SWCTL);
			v |= CAR_CLKSRC_SATA_AUX_CLK_ENB;
		} else {
			v &= ~CAR_CLKSRC_SATA_AUX_CLK_ENB;
		}
		break;
	case CAR_CLKSRC_HDMI_REG:

		break;
	}

	const u_int raw_div = rate ? howmany(parent_rate * 2, rate) - 2 : 0;
	//const u_int raw_div = rate ? (parent_rate * 2) / rate - 2 : 0;

	v &= ~tdiv->bits;
	v |= __SHIFTIN(raw_div, tdiv->bits);

	bus_space_write_4(bst, bsh, tdiv->reg, v);

	return 0;
}

static int
tegra124_car_clock_enable_gate(struct tegra124_car_softc *sc,
    struct tegra_clk *tclk, bool enable)
{
	struct tegra_gate_clk *tgate = &tclk->u.gate;
	bus_space_tag_t bst = sc->sc_bst;
	bus_space_handle_t bsh = sc->sc_bsh;
	bus_size_t reg;

	KASSERT(tclk->type == TEGRA_CLK_GATE);

	if (tgate->set_reg == tgate->clr_reg) {
		uint32_t v = bus_space_read_4(bst, bsh, tgate->set_reg);
		if (enable) {
			v |= tgate->bits;
		} else {
			v &= ~tgate->bits;
		}
		bus_space_write_4(bst, bsh, tgate->set_reg, v);
	} else {
		if (enable) {
			reg = tgate->set_reg;
		} else {
			reg = tgate->clr_reg;
		}

		if (reg == CAR_CLK_ENB_V_SET_REG &&
		    tgate->bits == CAR_DEV_V_SATA) {
			/* De-assert reset to SATA PADPLL */
			tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG,
			    0, CAR_SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE);
			delay(15);
		}
		bus_space_write_4(bst, bsh, reg, tgate->bits);
	}

	return 0;
}

static u_int
tegra124_car_clock_get_rate(void *priv, struct clk *clk)
{
	struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
	struct clk *clk_parent;

	switch (tclk->type) {
	case TEGRA_CLK_FIXED:
		return tclk->u.fixed.rate;
	case TEGRA_CLK_PLL:
		return tegra124_car_clock_get_rate_pll(priv, tclk);
	case TEGRA_CLK_MUX:
	case TEGRA_CLK_GATE:
		clk_parent = tegra124_car_clock_get_parent(priv, clk);
		if (clk_parent == NULL)
			return EINVAL;
		return tegra124_car_clock_get_rate(priv, clk_parent);
	case TEGRA_CLK_FIXED_DIV:
		return tegra124_car_clock_get_rate_fixed_div(priv, tclk);
	case TEGRA_CLK_DIV:
		return tegra124_car_clock_get_rate_div(priv, tclk);
	default:
		panic("tegra124: unknown tclk type %d", tclk->type);
	}
}

static int
tegra124_car_clock_set_rate(void *priv, struct clk *clk, u_int rate)
{
	struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
	struct clk *clk_parent;

	KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0);

	switch (tclk->type) {
	case TEGRA_CLK_FIXED:
	case TEGRA_CLK_MUX:
		return EIO;
	case TEGRA_CLK_FIXED_DIV:
		clk_parent = tegra124_car_clock_get_parent(priv, clk);
		if (clk_parent == NULL)
			return EIO;
		return tegra124_car_clock_set_rate(priv, clk_parent,
		    rate * tclk->u.fixed_div.div);
	case TEGRA_CLK_GATE:
		return EINVAL;
	case TEGRA_CLK_PLL:
		return tegra124_car_clock_set_rate_pll(priv, tclk, rate);
	case TEGRA_CLK_DIV:
		return tegra124_car_clock_set_rate_div(priv, tclk, rate);
	default:
		panic("tegra124: unknown tclk type %d", tclk->type);
	}
}

static int
tegra124_car_clock_enable(void *priv, struct clk *clk)
{
	struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
	struct clk *clk_parent;

	if (tclk->type != TEGRA_CLK_GATE) {
		clk_parent = tegra124_car_clock_get_parent(priv, clk);
		if (clk_parent == NULL)
			return 0;
		return tegra124_car_clock_enable(priv, clk_parent);
	}

	return tegra124_car_clock_enable_gate(priv, tclk, true);
}

static int
tegra124_car_clock_disable(void *priv, struct clk *clk)
{
	struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);

	if (tclk->type != TEGRA_CLK_GATE)
		return EINVAL;

	return tegra124_car_clock_enable_gate(priv, tclk, false);
}

static int
tegra124_car_clock_set_parent(void *priv, struct clk *clk,
    struct clk *clk_parent)
{
	struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
	struct tegra_clk *tclk_parent = TEGRA_CLK_PRIV(clk_parent);
	struct clk *nclk_parent;

	if (tclk->type != TEGRA_CLK_MUX) {
		nclk_parent = tegra124_car_clock_get_parent(priv, clk);
		if (nclk_parent == clk_parent || nclk_parent == NULL)
			return EINVAL;
		return tegra124_car_clock_set_parent(priv, nclk_parent,
		    clk_parent);
	}

	return tegra124_car_clock_set_parent_mux(priv, tclk, tclk_parent);
}

static struct clk *
tegra124_car_clock_get_parent(void *priv, struct clk *clk)
{
	struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
	struct tegra_clk *tclk_parent = NULL;

	switch (tclk->type) {
	case TEGRA_CLK_FIXED:
	case TEGRA_CLK_PLL:
	case TEGRA_CLK_FIXED_DIV:
	case TEGRA_CLK_DIV:
	case TEGRA_CLK_GATE:
		if (tclk->parent) {
			tclk_parent = tegra124_car_clock_find(tclk->parent);
		}
		break;
	case TEGRA_CLK_MUX:
		tclk_parent = tegra124_car_clock_get_parent_mux(priv, tclk);
		break;
	}

	if (tclk_parent == NULL)
		return NULL;

	return TEGRA_CLK_BASE(tclk_parent);
}

static void *
tegra124_car_reset_acquire(device_t dev, const void *data, size_t len)
{
	struct tegra124_car_softc * const sc = device_private(dev);
	struct tegra124_car_rst *rst;

	if (len != sc->sc_reset_cells * 4)
		return NULL;

	const u_int reset_id = be32dec(data);

	if (reset_id > __arraycount(tegra124_car_reset_regs) * 32)
		return NULL;

	const u_int reg = reset_id / 32;

	rst = kmem_alloc(sizeof(*rst), KM_SLEEP);
	rst->set_reg = tegra124_car_reset_regs[reg].set_reg;
	rst->clr_reg = tegra124_car_reset_regs[reg].clr_reg;
	rst->mask = __BIT(reset_id % 32);

	return rst;
}

static void
tegra124_car_reset_release(device_t dev, void *priv)
{
	struct tegra124_car_rst *rst = priv;

	kmem_free(rst, sizeof(*rst));
}

static int
tegra124_car_reset_assert(device_t dev, void *priv)
{
	struct tegra124_car_softc * const sc = device_private(dev);
	struct tegra124_car_rst *rst = priv;

	bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->set_reg, rst->mask);

	return 0;
}

static int
tegra124_car_reset_deassert(device_t dev, void *priv)
{
	struct tegra124_car_softc * const sc = device_private(dev);
	struct tegra124_car_rst *rst = priv;

	bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->clr_reg, rst->mask);

	return 0;
}

/* $NetBSD: tegra124_carreg.h,v 1.1 2015/12/22 22:10:36 jmcneill Exp $ */

/*-
 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#ifndef _ARM_TEGRA124_CARREG_H
#define _ARM_TEGRA124_CARREG_H

#define CAR_RST_SOURCE_REG	0x00
#define CAR_RST_SOURCE_WDT_EN		__BIT(5)
#define CAR_RST_SOURCE_WDT_SEL		__BIT(4)
#define CAR_RST_SOURCE_WDT_SYS_RST_EN	__BIT(2)
#define CAR_RST_SOURCE_WDT_COP_RST_EN	__BIT(1)
#define CAR_RST_SOURCE_WDT_CPU_RST_EN	__BIT(0)

#define CAR_CLK_OUT_ENB_L_REG	0x10
#define CAR_CLK_OUT_ENB_H_REG	0x14
#define CAR_CLK_OUT_ENB_U_REG	0x18

#define CAR_PLL_LFSR_REG	0x54
#define CAR_PLL_LFSR_RND		__BITS(15,0)

#define CAR_PLLP_BASE_REG	0xa0
#define CAR_PLLP_BASE_BYPASS		__BIT(31)
#define CAR_PLLP_BASE_ENABLE		__BIT(30)
#define CAR_PLLP_BASE_REF_DIS		__BIT(29)
#define CAR_PLLP_BASE_OVERRIDE		__BIT(28)
#define CAR_PLLP_BASE_LOCK		__BIT(27)
#define CAR_PLLP_BASE_DIVP		__BITS(22,20)
#define CAR_PLLP_BASE_DIVN		__BITS(17,8)
#define CAR_PLLP_BASE_DIVM		__BITS(4,0)

#define CAR_PLLP_OUTA_REG	0xa4
#define CAR_PLLP_OUTB_REG	0xa8
#define CAR_PLLP_OUTB_OUT4_RATIO	__BITS(31,24)
#define CAR_PLLP_OUTB_OUT4_OVRRIDE	__BIT(18)
#define CAR_PLLP_OUTB_OUT4_CLKEN	__BIT(17)
#define CAR_PLLP_OUTB_OUT4_RSTN		__BIT(16)
#define CAR_PLLP_OUTB_OUT3_RATIO	__BITS(15,8)
#define CAR_PLLP_OUTB_OUT3_OVRRIDE	__BIT(2)
#define CAR_PLLP_OUTB_OUT3_CLKEN	__BIT(1)
#define CAR_PLLP_OUTB_OUT3_RSTN		__BIT(0)
#define CAR_PLLP_OUTC_REG	0x67c
#define CAR_PLLP_OUTC_OUT5_RATIO	__BITS(31,24)
#define CAR_PLLP_OUTC_OUT5_OVERRIDE	__BIT(18)
#define CAR_PLLP_OUTC_OUT5_CLKEN	__BIT(17)
#define CAR_PLLP_OUTC_OUT5_RSTN		__BIT(16)
#define CAR_PLLP_MISC_REG	0xac

#define CAR_PLLC_BASE_REG	0x80
#define CAR_PLLC_BASE_ENABLE		__BIT(30)
#define CAR_PLLC_BASE_REF_DIS		__BIT(29)
#define CAR_PLLC_BASE_LOCK_OVERRIDE	__BIT(28)
#define CAR_PLLC_BASE_LOCK		__BIT(27)
#define CAR_PLLC_BASE_DIVP		__BITS(23,20)
#define CAR_PLLC_BASE_DIVN		__BITS(15,8)
#define CAR_PLLC_BASE_DIVM		__BITS(7,0)

#define CAR_PLLU_BASE_REG	0xc0
#define CAR_PLLU_BASE_BYPASS		__BIT(31)
#define CAR_PLLU_BASE_ENABLE		__BIT(30)
#define CAR_PLLU_BASE_REF_DIS		__BIT(29)
#define CAR_PLLU_BASE_LOCK		__BIT(27)
#define CAR_PLLU_BASE_CLKENABLE_48M	__BIT(25)
#define CAR_PLLU_BASE_OVERRIDE		__BIT(24)
#define CAR_PLLU_BASE_CLKENABLE_ICUSB	__BIT(23)
#define CAR_PLLU_BASE_CLKENABLE_HSIC	__BIT(22)
#define CAR_PLLU_BASE_CLKENABLE_USB	__BIT(21)
#define CAR_PLLU_BASE_VCO_FREQ		__BIT(20)
#define CAR_PLLU_BASE_DIVN		__BITS(17,8)
#define CAR_PLLU_BASE_DIVM		__BITS(4,0)

#define CAR_PLLD_BASE_REG	0xd0
#define CAR_PLLD_BASE_BYPASS		__BIT(31)
#define CAR_PLLD_BASE_ENABLE		__BIT(30)
#define CAR_PLLD_BASE_REF_DIS		__BIT(29)
#define CAR_PLLD_BASE_LOCK		__BIT(27)
#define CAR_PLLD_BASE_CLKENABLE_CSI	__BIT(26)
#define CAR_PLLD_BASE_DSIA_CLK_SRC	__BIT(25)
#define CAR_PLLD_BASE_CSI_CLK_SRC	__BIT(23)
#define CAR_PLLD_BASE_DIVP		__BITS(22,20)
#define CAR_PLLD_BASE_DIVN		__BITS(18,8)
#define CAR_PLLD_BASE_DIVM		__BITS(4,0)

#define CAR_PLLD_MISC_REG	0xdc

#define CAR_PLLX_BASE_REG	0xe0
#define CAR_PLLX_BASE_BYPASS		__BIT(31)
#define CAR_PLLX_BASE_ENABLE		__BIT(30)
#define CAR_PLLX_BASE_REF_DIS		__BIT(29)
#define CAR_PLLX_BASE_LOCK		__BIT(27)
#define CAR_PLLX_BASE_DIVP		__BITS(23,20)
#define CAR_PLLX_BASE_DIVN		__BITS(15,8)
#define CAR_PLLX_BASE_DIVM		__BITS(7,0)

#define CAR_PLLX_MISC_REG	0xe4
#define CAR_PLLX_MISC_FO_LP_DISABLE	__BIT(29)
#define CAR_PLLX_MISC_FO_G_DISABLE	__BIT(28)
#define CAR_PLLX_MISC_PTS		__BITS(23,22)
#define CAR_PLLX_MISC_LOCK_ENABLE	__BIT(18)

#define CAR_PLLE_BASE_REG	0xe8
#define CAR_PLLE_BASE_ENABLE		__BIT(30)
#define CAR_PLLE_BASE_LOCK_OVERRIDE	__BIT(29)
#define CAR_PLLE_BASE_FDIV48		__BIT(28)
#define CAR_PLLE_BASE_DIVP_CML		__BITS(27,24)
#define CAR_PLLE_BASE_EXT_SETUP_23_16	__BITS(23,16)
#define CAR_PLLE_BASE_DIVN		__BITS(15,8)
#define CAR_PLLE_BASE_DIVM		__BITS(7,0)

#define CAR_PLLE_MISC_REG	0xec

#define CAR_PLLD2_BASE_REG	0x4b8
#define CAR_PLLD2_BASE_BYPASS		__BIT(31)
#define CAR_PLLD2_BASE_ENABLE		__BIT(30)
#define CAR_PLLD2_BASE_REF_DIS		__BIT(29)
#define CAR_PLLD2_BASE_FREQLOCK		__BIT(28)
#define CAR_PLLD2_BASE_LOCK		__BIT(27)
#define CAR_PLLD2_BASE_REF_SRC_SEL	__BITS(26,25)
#define CAR_PLLD2_BASE_REF_SRC_SEL_PLL_D	0
#define CAR_PLLD2_BASE_REF_SRC_SEL_PLL_D2	1
#define CAR_PLLD2_BASE_LOCK_OVERRIDE	__BIT(24)
#define CAR_PLLD2_BASE_DIVP		__BITS(23,20)
#define CAR_PLLD2_BASE_IDDQ		__BIT(19)
#define CAR_PLLD2_BASE_PTS		__BIT(16)
#define CAR_PLLD2_BASE_DIVN		__BITS(15,8)
#define CAR_PLLD2_BASE_DIVM		__BITS(7,0)

#define CAR_PLLD2_MISC_REG	0x4bc
#define CAR_PLLD2_MISC_EN_FSTLCK	__BIT(31)
#define CAR_PLLD2_MISC_LOCK_ENABLE	__BIT(30)
#define CAR_PLLD2_MISC_MON_TEST_OUT	__BITS(29,27)
#define CAR_PLLD2_MISC_KCP		__BITS(26,25)
#define CAR_PLLD2_MISC_KVCO		__BIT(24)
#define CAR_PLLD2_MISC_SETUP		__BITS(23,0)

#define CAR_CLKSRC_I2C1_REG		0x124
#define CAR_CLKSRC_I2C2_REG		0x198
#define CAR_CLKSRC_I2C3_REG		0x1b8
#define CAR_CLKSRC_I2C4_REG		0x3c4
#define CAR_CLKSRC_I2C5_REG		0x128
#define CAR_CLKSRC_I2C6_REG		0x65c

#define CAR_CLKSRC_I2C_SRC		__BITS(31,29)
#define CAR_CLKSRC_I2C_SRC_PLLP_OUT0	0
#define CAR_CLKSRC_I2C_SRC_PLLC2_OUT0	1
#define CAR_CLKSRC_I2C_SRC_PLLC_OUT0	2
#define CAR_CLKSRC_I2C_SRC_PLLC3_OUT0	3
#define CAR_CLKSRC_I2C_SRC_PLLM_OUT0	4
#define CAR_CLKSRC_I2C_SRC_CLK_M	6
#define CAR_CLKSRC_I2C_DIV		__BITS(15,0)

#define CAR_CLKSRC_UARTA_REG		0x178
#define CAR_CLKSRC_UARTB_REG		0x17c
#define CAR_CLKSRC_UARTC_REG		0x1a0
#define CAR_CLKSRC_UARTD_REG		0x1c0

#define CAR_CLKSRC_UART_SRC		__BITS(31,29)
#define CAR_CLKSRC_UART_SRC_PLLP_OUT0	0
#define CAR_CLKSRC_UART_SRC_PLLC2_OUT0	1
#define CAR_CLKSRC_UART_SRC_PLLC_OUT0	2
#define CAR_CLKSRC_UART_SRC_PLLC3_OUT0	3
#define CAR_CLKSRC_UART_SRC_PLLM_OUT0	4
#define CAR_CLKSRC_UART_SRC_CLK_M	6
#define CAR_CLKSRC_UART_DIV_ENB		__BIT(24)
#define CAR_CLKSRC_UART_DIV		__BITS(15,0)

#define CAR_CLKSRC_SDMMC1_REG		0x150
#define CAR_CLKSRC_SDMMC2_REG		0x154
#define CAR_CLKSRC_SDMMC4_REG		0x164
#define CAR_CLKSRC_SDMMC3_REG		0x1bc

#define CAR_CLKSRC_SDMMC_SRC		__BITS(31,29)
#define CAR_CLKSRC_SDMMC_SRC_PLLP_OUT0	0
#define CAR_CLKSRC_SDMMC_SRC_PLLC2_OUT0	1
#define CAR_CLKSRC_SDMMC_SRC_PLLC_OUT0	2
#define CAR_CLKSRC_SDMMC_SRC_PLLC3_OUT0	3
#define CAR_CLKSRC_SDMMC_SRC_PLLM_OUT0	4
#define CAR_CLKSRC_SDMMC_SRC_PLLE_OUT0	5
#define CAR_CLKSRC_SDMMC_SRC_CLK_M	6
#define CAR_CLKSRC_SDMMC_DIV		__BITS(7,0)

#define CAR_CLKSRC_HDMI_REG		0x18c
#define CAR_CLKSRC_HDMI_SRC		__BITS(31,29)
#define CAR_CLKSRC_HDMI_SRC_PLLP_OUT0	0
#define CAR_CLKSRC_HDMI_SRC_PLLM_OUT0	1
#define CAR_CLKSRC_HDMI_SRC_PLLD_OUT0	2
#define CAR_CLKSRC_HDMI_SRC_PLLA_OUT0	3
#define CAR_CLKSRC_HDMI_SRC_PLLC_OUT0	4
#define CAR_CLKSRC_HDMI_SRC_PLLD2_OUT0	5
#define CAR_CLKSRC_HDMI_SRC_CLK_M	6
#define CAR_CLKSRC_HDMI_DIV		__BITS(7,0)

#define CAR_CLKSRC_DISP1_REG		0x138
#define CAR_CLKSRC_DISP2_REG		0x13c
#define CAR_CLKSRC_DISP_SRC		__BITS(31,29)
#define CAR_CLKSRC_DISP_SRC_PLLP_OUT0	0
#define CAR_CLKSRC_DISP_SRC_PLLM_OUT0	1
#define CAR_CLKSRC_DISP_SRC_PLLD_OUT0	2
#define CAR_CLKSRC_DISP_SRC_PLLA_OUT0	3
#define CAR_CLKSRC_DISP_SRC_PLLC_OUT0	4
#define CAR_CLKSRC_DISP_SRC_PLLD2_OUT0	5
#define CAR_CLKSRC_DISP_SRC_CLK_M	6

#define CAR_CLKSRC_HOST1X_REG		0x180
#define CAR_CLKSRC_HOST1X_SRC		__BITS(31,29)
#define CAR_CLKSRC_HOST1X_SRC_PLLM_OUT0		0
#define CAR_CLKSRC_HOST1X_SRC_PLLC2_OUT0	1
#define CAR_CLKSRC_HOST1X_SRC_PLLC_OUT0		2
#define CAR_CLKSRC_HOST1X_SRC_PLLC3_OUT0	3
#define CAR_CLKSRC_HOST1X_SRC_PLLP_OUT0		4
#define CAR_CLKSRC_HOST1X_SRC_PLLA_OUT0		6
#define CAR_CLKSRC_HOST1X_IDLE_DIVISOR	__BITS(15,8)
#define CAR_CLKSRC_HOST1X_CLK_DIVISOR	__BITS(7,0)

#define CAR_RST_DEV_L_SET_REG		0x300
#define CAR_RST_DEV_L_CLR_REG		0x304
#define CAR_RST_DEV_H_SET_REG		0x308
#define CAR_RST_DEV_H_CLR_REG		0x30c
#define CAR_RST_DEV_U_SET_REG		0x310
#define CAR_RST_DEV_U_CLR_REG		0x314
#define CAR_RST_DEV_V_SET_REG		0x430
#define CAR_RST_DEV_V_CLR_REG		0x434
#define CAR_RST_DEV_W_SET_REG		0x438
#define CAR_RST_DEV_W_CLR_REG		0x43c
#define CAR_RST_DEV_X_SET_REG		0x290
#define CAR_RST_DEV_X_CLR_REG		0x294

#define CAR_CLK_ENB_L_SET_REG		0x320
#define CAR_CLK_ENB_L_CLR_REG		0x324
#define CAR_CLK_ENB_H_SET_REG		0x328
#define CAR_CLK_ENB_H_CLR_REG		0x32c
#define CAR_CLK_ENB_U_SET_REG		0x330
#define CAR_CLK_ENB_U_CLR_REG		0x334
#define CAR_CLK_ENB_V_SET_REG		0x440
#define CAR_CLK_ENB_V_CLR_REG		0x444
#define CAR_CLK_ENB_W_SET_REG		0x448
#define CAR_CLK_ENB_W_CLR_REG		0x44c
#define CAR_CLK_ENB_X_SET_REG		0x284
#define CAR_CLK_ENB_X_CLR_REG		0x288

#define CAR_DEV_L_CACHE2		__BIT(31)
#define CAR_DEV_L_I2S0			__BIT(30)
#define CAR_DEV_L_VCP			__BIT(29)
#define CAR_DEV_L_HOST1X		__BIT(28)
#define CAR_DEV_L_DISP1			__BIT(27)
#define CAR_DEV_L_DISP2			__BIT(26)
#define CAR_DEV_L_ISP			__BIT(23)
#define CAR_DEV_L_USBD			__BIT(22)
#define CAR_DEV_L_VI			__BIT(20)
#define CAR_DEV_L_I2S2			__BIT(18)
#define CAR_DEV_L_PWM			__BIT(17)
#define CAR_DEV_L_SDMMC4		__BIT(15)
#define CAR_DEV_L_SDMMC1		__BIT(14)
#define CAR_DEV_L_I2C1			__BIT(12)
#define CAR_DEV_L_I2S1			__BIT(11)
#define CAR_DEV_L_SPDIF			__BIT(10)
#define CAR_DEV_L_SDMMC2		__BIT(9)
#define CAR_DEV_L_GPIO			__BIT(8)
#define CAR_DEV_L_UARTB			__BIT(7)
#define CAR_DEV_L_UARTA			__BIT(6)
#define CAR_DEV_L_TMR			__BIT(5
#define CAR_DEV_L_RTC			__BIT(4)
#define CAR_DEV_L_ISPB			__BIT(3)
#define CAR_DEV_L_CPU			__BIT(0)

#define CAR_DEV_U_XUSB_DEV		__BIT(31)
#define CAR_DEV_U_DEV1_OUT		__BIT(30)
#define CAR_DEV_U_DEV2_OUT		__BIT(29)
#define CAR_DEV_U_SUS_OUT		__BIT(28)
#define CAR_DEV_U_MSENC			__BIT(27)
#define CAR_DEV_U_XUSB_HOST		__BIT(25)
#define CAR_DEV_U_CRAM2			__BIT(24)
#define CAR_DEV_U_IRAMD			__BIT(23)
#define CAR_DEV_U_IRAMC			__BIT(22)
#define CAR_DEV_U_IRAMB			__BIT(21)
#define CAR_DEV_U_IRAMA			__BIT(20)
#define CAR_DEV_U_TSEC			__BIT(19)
#define CAR_DEV_U_DSIB			__BIT(18)
#define CAR_DEV_U_I2C_SLOW		__BIT(17)
#define CAR_DEV_U_DTV			__BIT(15)
#define CAR_DEV_U_SOC_THERM		__BIT(14)
#define CAR_DEV_U_TRACECLKIN		__BIT(13)
#define CAR_DEV_U_AVPUCQ		__BIT(11)
#define CAR_DEV_U_CSITE			__BIT(9)
#define CAR_DEV_U_AFI			__BIT(8)
#define CAR_DEV_U_OWR			__BIT(7)
#define CAR_DEV_U_PCIE			__BIT(6)
#define CAR_DEV_U_SDMMC3		__BIT(5)
#define CAR_DEV_U_SPI4			__BIT(4)
#define CAR_DEV_U_I2C3			__BIT(3)
#define CAR_DEV_U_UARTD			__BIT(1)

#define CAR_DEV_H_BSEV			__BIT(31)
#define CAR_DEV_H_BSEA			__BIT(30)
#define CAR_DEV_H_VDE			__BIT(29)
#define CAR_DEV_H_USB3			__BIT(27)
#define CAR_DEV_H_USB2			__BIT(26)
#define CAR_DEV_H_EMC			__BIT(25)
#define CAR_DEV_H_MIPI_CAL		__BIT(24)
#define CAR_DEV_H_UARTC			__BIT(23)
#define CAR_DEV_H_I2C2			__BIT(22)
#define CAR_DEV_H_CSI			__BIT(20)
#define CAR_DEV_H_HDMI			__BIT(19)
#define CAR_DEV_H_HSI			__BIT(18)
#define CAR_DEV_H_DSI			__BIT(16)
#define CAR_DEV_H_I2C5			__BIT(15)
#define CAR_DEV_H_SPI3			__BIT(14)
#define CAR_DEV_H_SPI2			__BIT(12)
#define CAR_DEV_H_JTAG2TBC		__BIT(11)
#define CAR_DEV_H_SNOR			__BIT(10)
#define CAR_DEV_H_SPI1			__BIT(9)
#define CAR_DEV_H_KFUSE			__BIT(8)
#define CAR_DEV_H_FUSE			__BIT(7)
#define CAR_DEV_H_PMC			__BIT(6)
#define CAR_DEV_H_STAT_MON		__BIT(5)
#define CAR_DEV_H_KBC			__BIT(4)
#define CAR_DEV_H_APBDMA		__BIT(2)
#define CAR_DEV_H_AHBDMA		__BIT(1)
#define CAR_DEV_H_MEM			__BIT(0)

#define CAR_DEV_V_HDA			__BIT(29)
#define CAR_DEV_V_SATA			__BIT(28)
#define CAR_DEV_V_SATA_OOB		__BIT(27)
#define CAR_DEV_V_ACTMON		__BIT(23)
#define CAR_DEV_V_ATOMICS		__BIT(16)
#define CAR_DEV_V_HDA2CODEC_2X		__BIT(15)
#define CAR_DEV_V_DAM2			__BIT(14)
#define CAR_DEV_V_DAM1			__BIT(13)
#define CAR_DEV_V_DAM0			__BIT(12)
#define CAR_DEV_V_APBIF			__BIT(11)
#define CAR_DEV_V_AUDIO			__BIT(10)
#define CAR_DEV_V_SPI6			__BIT(9)
#define CAR_DEV_V_SPI5			__BIT(8)
#define CAR_DEV_V_I2C4			__BIT(7)
#define CAR_DEV_V_I2S4			__BIT(6)
#define CAR_DEV_V_I2S3			__BIT(5)
#define CAR_DEV_V_TSENSOR		__BIT(4)
#define CAR_DEV_V_MSELECT		__BIT(3)
#define CAR_DEV_V_CPULP			__BIT(1)
#define CAR_DEV_V_CPUG			__BIT(0)

#define CAR_DEV_W_XUSB_SS		__BIT(28)
#define CAR_DEV_W_DVFS			__BIT(27)
#define CAR_DEV_W_ADX0			__BIT(26)
#define CAR_DEV_W_AMX0			__BIT(25)
#define CAR_DEV_W_ENTROPY		__BIT(21)
#define CAR_DEV_W_XUSB_PADCTL		__BIT(14)
#define CAR_DEV_W_CEC			__BIT(8)
#define CAR_DEV_W_SATACOLD		__BIT(1)
#define CAR_DEV_W_HDA2HDMICODEC		__BIT(0)

#define CAR_DEV_X_AMX1			__BIT(25)
#define CAR_DEV_X_GPU			__BIT(24)
#define CAR_DEV_X_SOR0			__BIT(22)
#define CAR_DEV_X_DPAUX			__BIT(21)
#define CAR_DEV_X_ADX1			__BIT(20)
#define CAR_DEV_X_VIC			__BIT(18)
#define CAR_DEV_X_CLK72MHZ		__BIT(17)
#define CAR_DEV_X_HDMI_AUDIO		__BIT(16)
#define CAR_DEV_X_EMC_DLL		__BIT(14)
#define CAR_DEV_X_VIM2_CLK		__BIT(11)
#define CAR_DEV_X_I2C6			__BIT(6)
#define CAR_DEV_X_CAM_MCLK2		__BIT(5)
#define CAR_DEV_X_CAM_MCLK		__BIT(4)
#define CAR_DEV_X_SPARE			__BIT(0)

#define CAR_CCLKG_BURST_POLICY_REG	0x368
#define CAR_CCLKG_BURST_POLICY_CPU_STATE	__BITS(31,28)
#define CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE			1
#define CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN			2
#define CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE __BITS(3,0)
#define CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM		0
#define CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ	8

#define CAR_CLKSRC_TSENSOR_REG		0x3b8
#define CAR_CLKSRC_TSENSOR_SRC		__BITS(31,29)
#define CAR_CLKSRC_TSENSOR_SRC_CLK_M	4
#define CAR_CLKSRC_TSENSOR_DIV		__BITS(7,0)

#define CAR_CLKSRC_HDA2CODEC_2X_REG	0x3e4
#define CAR_CLKSRC_HDA2CODEC_2X_SRC	__BITS(31,29)
#define CAR_CLKSRC_HDA2CODEC_2X_SRC_PLLP_OUT0	0
#define CAR_CLKSRC_HDA2CODEC_2X_SRC_PLLC2_OUT0	1
#define CAR_CLKSRC_HDA2CODEC_2X_SRC_PLLC_OUT0	2
#define CAR_CLKSRC_HDA2CODEC_2X_SRC_PLLC3_OUT0	3
#define CAR_CLKSRC_HDA2CODEC_2X_SRC_PLLM_OUT0	4
#define CAR_CLKSRC_HDA2CODEC_2X_SRC_CLKM	6
#define CAR_CLKSRC_HDA2CODEC_2X_DIV	__BITS(7,0)

#define CAR_CLKSRC_SATA_OOB_REG		0x420
#define CAR_CLKSRC_SATA_OOB_SRC		__BITS(31,29)
#define CAR_CLKSRC_SATA_OOB_SRC_PLLP_OUT0	0
#define CAR_CLKSRC_SATA_OOB_SRC_PLLC_OUT0	2
#define CAR_CLKSRC_SATA_OOB_SRC_PLLM_OUT0	4
#define CAR_CLKSRC_SATA_OOB_SRC_CLKM		6
#define CAR_CLKSRC_SATA_OOB_DIV		__BITS(7,0)

#define CAR_CLKSRC_SATA_REG		0x424
#define CAR_CLKSRC_SATA_SRC		__BITS(31,29)
#define CAR_CLKSRC_SATA_SRC_PLLP_OUT0		0
#define CAR_CLKSRC_SATA_SRC_PLLC_OUT0		2
#define CAR_CLKSRC_SATA_SRC_PLLM_OUT0		4
#define CAR_CLKSRC_SATA_SRC_CLKM		6
#define CAR_CLKSRC_SATA_AUX_CLK_ENB	__BIT(24)
#define CAR_CLKSRC_SATA_DIV		__BITS(7,0)

#define CAR_CLKSRC_HDA_REG		0x428
#define CAR_CLKSRC_HDA_SRC		__BITS(31,29)
#define CAR_CLKSRC_HDA_SRC_PLLP_OUT0	0
#define CAR_CLKSRC_HDA_SRC_PLLC2_OUT0	1
#define CAR_CLKSRC_HDA_SRC_PLLC_OUT0	2
#define CAR_CLKSRC_HDA_SRC_PLLC3_OUT0	3
#define CAR_CLKSRC_HDA_SRC_PLLM_OUT0	4
#define CAR_CLKSRC_HDA_SRC_CLKM		6
#define CAR_CLKSRC_HDA_DIV		__BITS(7,0)

#define CAR_UTMIP_PLL_CFG0_REG		0x480

#define CAR_UTMIP_PLL_CFG1_REG		0x484
#define CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT	__BITS(31,27)
#define CAR_UTMIP_PLL_CFG1_PLLU_POWERUP		__BIT(17)
#define CAR_UTMIP_PLL_CFG1_PLLU_POWERDOWN	__BIT(16)
#define CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERUP 	__BIT(15)
#define CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN	__BIT(14)
#define CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT	__BITS(11,0)

#define CAR_UTMIP_PLL_CFG2_REG		0x488
#define CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT	__BITS(23,18)
#define CAR_UTMIP_PLL_CFG2_STABLE_COUNT		__BITS(17,6)
#define CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERUP	__BIT(5)
#define CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN	__BIT(4)
#define CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERUP	__BIT(3)
#define CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN	__BIT(2)
#define CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERUP	__BIT(1)
#define CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN	__BIT(0)

#define CAR_PLLE_AUX_REG		0x48c
#define CAR_PLLE_AUX_SS_SEQ_INCLUDE		__BIT(31)
#define CAR_PLLE_AUX_REF_SEL_PLLREFE		__BIT(28)
#define CAR_PLLE_AUX_SEQ_STATE			__BITS(27,26)
#define CAR_PLLE_AUX_SEQ_START_STATE		__BIT(25)
#define CAR_PLLE_AUX_SEQ_ENABLE			__BIT(24)
#define CAR_PLLE_AUX_SS_DLY			__BITS(23,16)
#define CAR_PLLE_AUX_LOCK_DLY			__BITS(15,8)
#define CAR_PLLE_AUX_FAST_PT			__BIT(7)
#define CAR_PLLE_AUX_SS_SWCTL			__BIT(6)
#define CAR_PLLE_AUX_CONFIG_SWCTL		__BIT(5)
#define CAR_PLLE_AUX_ENABLE_SWCTL		__BIT(4)
#define CAR_PLLE_AUX_USE_LOCKDET		__BIT(3)
#define CAR_PLLE_AUX_REF_SRC			__BIT(2)
#define CAR_PLLE_AUX_CML1_OEN			__BIT(1)
#define CAR_PLLE_AUX_CML0_OEN			__BIT(0)

#define CAR_SATA_PLL_CFG0_REG		0x490
#define CAR_SATA_PLL_CFG0_SEQ_STATE		__BITS(27,26)
#define CAR_SATA_PLL_CFG0_SEQ_START_STATE	__BIT(25)
#define CAR_SATA_PLL_CFG0_SEQ_ENABLE		__BIT(24)
#define CAR_SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE __BIT(7)
#define CAR_SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE __BIT(6)
#define CAR_SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE	__BIT(5)
#define CAR_SATA_PLL_CFG0_SEQ_IN_SWCTL		__BIT(4)
#define CAR_SATA_PLL_CFG0_PADPLL_USE_LOCKDET	__BIT(2)
#define CAR_SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE __BIT(1)
#define CAR_SATA_PLL_CFG0_PADPLL_RESET_SWCTL	__BIT(0)

#define CAR_SATA_PLL_CFG1_REG		0x494
#define CAR_SATA_PLL_CFG1_LANE_IDDQ2_PADPLL_RESET_DLY __BITS(31,24)
#define CAR_SATA_PLL_CFG1_PADPLL_IDDQ2LANE_SLUMBER_DLY __BITS(23,16)
#define CAR_SATA_PLL_CFG1_PADPLL_PU_POST_DLY	__BITS(15,8)
#define CAR_SATA_PLL_CFG1_LANE_IDDQ2_PADPLL_IDDQ_DLY __BITS(7,0)

#define CAR_CLKSRC_SOC_THERM_REG	0x644
#define CAR_CLKSRC_SOC_THERM_SRC	__BITS(31,29)
#define CAR_CLKSRC_SOC_THERM_SRC_PLLP_OUT0	2
#define CAR_CLKSRC_SOC_THERM_DIV	__BITS(7,0)

#define CAR_CLKSRC_HDMI_AUDIO_REG	0x668
#define CAR_CLKSRC_HDMI_AUDIO_SRC	__BITS(31,29)
#define CAR_CLKSRC_HDMI_AUDIO_SRC_PLLP_OUT0	0
#define CAR_CLKSRC_HDMI_AUDIO_SRC_PLLC_OUT0	1
#define CAR_CLKSRC_HDMI_AUDIO_SRC_PLLC2_OUT0	2
#define CAR_CLKSRC_HDMI_AUDIO_SRC_CLKM		3
#define CAR_CLKSRC_HDMI_AUDIO_DIV	__BITS(7,0)

#endif /* _ARM_TEGRA124_CARREG_H */

/* $NetBSD: tegra_clock.h,v 1.1 2015/12/22 22:10:36 jmcneill Exp $ */

/*-
 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#ifndef _ARM_TEGRA_CLOCK_H
#define _ARM_TEGRA_CLOCK_H

enum tegra_clk_type {
	TEGRA_CLK_FIXED,
	TEGRA_CLK_PLL,
	TEGRA_CLK_MUX,
	TEGRA_CLK_FIXED_DIV,
	TEGRA_CLK_DIV,
	TEGRA_CLK_GATE
};

struct tegra_fixed_clk {
	u_int rate;
};

struct tegra_fixed_div_clk {
	u_int div;
};

struct tegra_pll_clk {
	u_int base_reg;
	u_int divm_mask;
	u_int divn_mask;
	u_int divp_mask;
};

struct tegra_mux_clk {
	const char **parents;
	u_int nparents;
	u_int reg;
	u_int bits;
};

struct tegra_div_clk {
	u_int reg;
	u_int bits;
};

struct tegra_gate_clk {
	u_int set_reg;
	u_int clr_reg;
	u_int bits;
};

struct tegra_clk {
	struct clk base;		/* must be first */
	u_int id;
	const char *parent;
	enum tegra_clk_type type;
	u_int refcnt;
	union {
		struct tegra_fixed_clk fixed;
		struct tegra_pll_clk pll;
		struct tegra_mux_clk mux;
		struct tegra_fixed_div_clk fixed_div;
		struct tegra_div_clk div;
		struct tegra_gate_clk gate;
	} u;
};

#define TEGRA_CLK_BASE(_tclk)	((_tclk) ? &(_tclk)->base : NULL)
#define TEGRA_CLK_PRIV(_clk)	((struct tegra_clk *)(_clk))

#endif /* _ARM_TEGRA_CLOCK_H */

--- src/sys/arch/arm/nvidia/tegra_ahcisata.c 2015/12/13 17:39:19	1.8
+++ src/sys/arch/arm/nvidia/tegra_ahcisata.c 2015/12/22 22:10:36	1.9

 @@ -1,14 +1,14 @@
-/* $NetBSD: tegra_ahcisata.c,v 1.8 2015/12/13 17:39:19 jmcneill Exp $ */
+/* $NetBSD: tegra_ahcisata.c,v 1.9 2015/12/22 22:10:36 jmcneill Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -17,66 +17,75 @@
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_ahcisata.c,v 1.8 2015/12/13 17:39:19 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_ahcisata.c,v 1.9 2015/12/22 22:10:36 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <dev/ata/atavar.h>
 #include <dev/ic/ahcisatavar.h>
 #include <arm/nvidia/tegra_var.h>
 #include <arm/nvidia/tegra_pmcreg.h>
 #include <arm/nvidia/tegra_ahcisatareg.h>
 #include <dev/fdt/fdtvar.h>
 #define TEGRA_AHCISATA_OFFSET	0x7000
 static int	tegra_ahcisata_match(device_t, cfdata_t, void *);
 static void	tegra_ahcisata_attach(device_t, device_t, void *);
 struct tegra_ahcisata_softc {
 	struct ahci_softc	sc;
 	bus_space_tag_t		sc_bst;
 	bus_space_handle_t	sc_bsh;
 	void			*sc_ih;
 	struct clk		*sc_clk_sata;
 	struct clk		*sc_clk_sata_oob;
 	struct clk		*sc_clk_cml1;
 	struct clk		*sc_clk_pll_e;
 	struct fdtbus_reset	*sc_rst_sata;
 	struct fdtbus_reset	*sc_rst_sata_oob;
 	struct fdtbus_reset	*sc_rst_sata_cold;
 	struct tegra_gpio_pin	*sc_pin_power;
 };
 static const char * const tegra_ahcisata_supplies[] = {
     "hvdd-supply",
     "vddio-supply",
     "avdd-supply",
     "target-5v-supply",
     "target-12v-supply"
 };
 static void	tegra_ahcisata_init(struct tegra_ahcisata_softc *);
 static int	tegra_ahcisata_init_clocks(struct tegra_ahcisata_softc *);
 CFATTACH_DECL_NEW(tegra_ahcisata, sizeof(struct tegra_ahcisata_softc),
 	tegra_ahcisata_match, tegra_ahcisata_attach, NULL, NULL);
 static int
 tegra_ahcisata_match(device_t parent, cfdata_t cf, void *aux)
+{
 	const char * const compatible[] = { "nvidia,tegra124-ahci", NULL };
 	struct fdt_attach_args * const faa = aux;
 	return of_match_compatible(faa->faa_phandle, compatible);
+}
 @@ -90,26 +99,61 @@ tegra_ahcisata_attach(device_t parent, d
 	bus_size_t ahci_size, sata_size;
 	struct fdtbus_regulator *reg;
 	char intrstr[128];
 	int error, n;
 	if (fdtbus_get_reg(phandle, 0, &ahci_addr, &ahci_size) != 0) {
 		aprint_error(": couldn't get ahci registers\n");
 		return;
+	}
 	if (fdtbus_get_reg(phandle, 1, &sata_addr, &sata_size) != 0) {
 		aprint_error(": couldn't get sata registers\n");
 		return;
+	}
 	sc->sc_clk_sata = fdtbus_clock_get(phandle, "sata");
 	if (sc->sc_clk_sata == NULL) {
 		aprint_error(": couldn't get clock sata\n");
 		return;
+	}
 	sc->sc_clk_sata_oob = fdtbus_clock_get(phandle, "sata-oob");
 	if (sc->sc_clk_sata_oob == NULL) {
 		aprint_error(": couldn't get clock sata-oob\n");
 		return;
+	}
 	sc->sc_clk_cml1 = fdtbus_clock_get(phandle, "cml1");
 	if (sc->sc_clk_cml1 == NULL) {
 		aprint_error(": couldn't get clock cml1\n");
 		return;
+	}
 	sc->sc_clk_pll_e = fdtbus_clock_get(phandle, "pll_e");
 	if (sc->sc_clk_pll_e == NULL) {
 		aprint_error(": couldn't get clock pll_e\n");
 		return;
+	}
 	sc->sc_rst_sata = fdtbus_reset_get(phandle, "sata");
 	if (sc->sc_rst_sata == NULL) {
 		aprint_error(": couldn't get reset sata\n");
 		return;
+	}
 	sc->sc_rst_sata_oob = fdtbus_reset_get(phandle, "sata-oob");
 	if (sc->sc_rst_sata_oob == NULL) {
 		aprint_error(": couldn't get reset sata-oob\n");
 		return;
+	}
 	sc->sc_rst_sata_cold = fdtbus_reset_get(phandle, "sata-cold");
 	if(sc->sc_rst_sata_cold == NULL) {
 		aprint_error(": couldn't get reset sata-cold\n");
 		return;
+	}
 	sc->sc_bst = faa->faa_bst;
 	error = bus_space_map(sc->sc_bst, sata_addr, sata_size, 0, &sc->sc_bsh);
 	if (error) {
 		aprint_error(": couldn't map sata registers: %d\n", error);
 		return;
+	}
 	sc->sc.sc_atac.atac_dev = self;
 	sc->sc.sc_dmat = faa->faa_dmat;
 	sc->sc.sc_ahcit = faa->faa_bst;
 	sc->sc.sc_ahcis = ahci_size;
 	error = bus_space_map(sc->sc.sc_ahcit, ahci_addr, ahci_size, 0,
 @@ -126,27 +170,28 @@ tegra_ahcisata_attach(device_t parent, d
 	for (n = 0; n < __arraycount(tegra_ahcisata_supplies); n++) {
 		const char *supply = tegra_ahcisata_supplies[n];
 		reg = fdtbus_regulator_acquire(phandle, supply);
 		if (reg == NULL) {
 			aprint_error_dev(self, "couldn't acquire %s\n", supply);
 			continue;
+		}
 		if (fdtbus_regulator_enable(reg) != 0) {
 			aprint_error_dev(self, "couldn't enable %s\n", supply);
+		}
 		fdtbus_regulator_release(reg);
+	}
-	tegra_car_periph_sata_enable();
+	if (tegra_ahcisata_init_clocks(sc) != 0)
 		return;
 	tegra_xusbpad_sata_enable();
 	tegra_ahcisata_init(sc);
 	if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
 		aprint_error_dev(self, "failed to decode interrupt\n");
 		return;
+	}
 	sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_BIO, 0,
 	    ahci_intr, &sc->sc);
 	if (sc->sc_ih == NULL) {
 @@ -224,13 +269,88 @@ tegra_ahcisata_init(struct tegra_ahcisat
 	    TEGRA_T_SATA0_CFG1_IO_SPACE,
 );
 	/* MMIO setup */
 	bus_space_write_4(bst, bsh, TEGRA_SATA_FPCI_BAR5_REG,
 	    __SHIFTIN(0x10000, TEGRA_SATA_FPCI_BAR_START));
 	bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CFG9_REG,
 	    __SHIFTIN(0x8000, TEGRA_T_SATA0_CFG9_BASE_ADDRESS));
 	/* Enable interrupts */
 	tegra_reg_set_clear(bst, bsh, TEGRA_SATA_INTR_MASK_REG,
 	    TEGRA_SATA_INTR_MASK_IP_INT, 0);
+}
 static int
 tegra_ahcisata_init_clocks(struct tegra_ahcisata_softc *sc)
+{
 	device_t self = sc->sc.sc_atac.atac_dev;
 	struct clk *pll_p_out0;
 	int error;
 	pll_p_out0 = clk_get("pll_p_out0");
 	if (pll_p_out0 == NULL) {
 		aprint_error_dev(self, "couldn't find pll_p_out0\n");
 		return ENOENT;
+	}
 	/* Assert resets */
 	fdtbus_reset_assert(sc->sc_rst_sata);
 	fdtbus_reset_assert(sc->sc_rst_sata_cold);
 	/* Set SATA_OOB clock source to PLLP, 204MHz */
 	error = clk_set_parent(sc->sc_clk_sata_oob, pll_p_out0);
 	if (error) {
 		aprint_error_dev(self, "couldn't set sata-oob parent: %d\n",
 		    error);
 		return error;
+	}
 	error = clk_set_rate(sc->sc_clk_sata_oob, 204000000);
 	if (error) {
 		aprint_error_dev(self, "couldn't set sata-oob rate: %d\n",
 		    error);
 		return error;
+	}
 	/* Set SATA clock source to PLLP, 102MHz */
 	error = clk_set_parent(sc->sc_clk_sata, pll_p_out0);
 	if (error) {
 		aprint_error_dev(self, "couldn't set sata parent: %d\n", error);
 		return error;
+	}
 	error = clk_set_rate(sc->sc_clk_sata, 102000000);
 	if (error) {
 		aprint_error_dev(self, "couldn't set sata rate: %d\n", error);
 		return error;
+	}
 	/* Ungate SAX partition in the PMC */
 	tegra_pmc_power(PMC_PARTID_SAX, true);
 	delay(20);
 	/* Remove clamping from SAX partition in the PMC */
 	tegra_pmc_remove_clamping(PMC_PARTID_SAX);
 	delay(20);
 	/* Un-gate clocks and enable CML clock for SATA */
 	error = clk_enable(sc->sc_clk_sata);
 	if (error) {
 		aprint_error_dev(self, "couldn't enable sata: %d\n", error);
 		return error;
+	}
 	error = clk_enable(sc->sc_clk_sata_oob);
 	if (error) {
 		aprint_error_dev(self, "couldn't enable sata-oob: %d\n", error);
 		return error;
+	}
 	error = clk_enable(sc->sc_clk_cml1);
 	if (error) {
 		aprint_error_dev(self, "couldn't enable cml1: %d\n", error);
 		return error;
+	}
 	/* De-assert resets */
 	fdtbus_reset_deassert(sc->sc_rst_sata);
 	fdtbus_reset_deassert(sc->sc_rst_sata_cold);
 	return 0;
+}

--- src/sys/arch/arm/nvidia/tegra_nouveau.c 2015/12/13 22:05:52	1.8
+++ src/sys/arch/arm/nvidia/tegra_nouveau.c 2015/12/22 22:10:36	1.9

 @@ -1,14 +1,14 @@
-/* $NetBSD: tegra_nouveau.c,v 1.8 2015/12/13 22:05:52 jmcneill Exp $ */
+/* $NetBSD: tegra_nouveau.c,v 1.9 2015/12/22 22:10:36 jmcneill Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -17,56 +17,60 @@
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_nouveau.c,v 1.8 2015/12/13 22:05:52 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_nouveau.c,v 1.9 2015/12/22 22:10:36 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/module.h>
 #include <arm/nvidia/tegra_reg.h>
 #include <arm/nvidia/tegra_pmcreg.h>
 #include <arm/nvidia/tegra_var.h>
 #include <dev/fdt/fdtvar.h>
 #include <drm/drmP.h>
 #include <engine/device.h>
 extern char *nouveau_config;
 extern char *nouveau_debug;
 extern struct drm_driver *const nouveau_drm_driver;
 static int	tegra_nouveau_match(device_t, cfdata_t, void *);
 static void	tegra_nouveau_attach(device_t, device_t, void *);
 struct tegra_nouveau_softc {
 	device_t		sc_dev;
 	bus_space_tag_t		sc_bst;
 	bus_dma_tag_t		sc_dmat;
 	int			sc_phandle;
 	struct clk		*sc_clk_gpu;
 	struct clk		*sc_clk_pwr;
 	struct fdtbus_reset	*sc_rst_gpu;
 	struct drm_device	*sc_drm_dev;
 	struct platform_device	sc_platform_dev;
 	struct nouveau_device	*sc_nv_dev;
 };
 static void	tegra_nouveau_init(device_t);
 static int	tegra_nouveau_get_irq(struct drm_device *);
 static const char *tegra_nouveau_get_name(struct drm_device *);
 static int	tegra_nouveau_set_busid(struct drm_device *,
 					struct drm_master *);
 static int	tegra_nouveau_irq_install(struct drm_device *,
 					  irqreturn_t (*)(void *),
 @@ -99,33 +103,69 @@ tegra_nouveau_match(device_t parent, cfd
 static void
 tegra_nouveau_attach(device_t parent, device_t self, void *aux)
+{
 	struct tegra_nouveau_softc * const sc = device_private(self);
 	struct fdt_attach_args * const faa = aux;
 	prop_dictionary_t prop = device_properties(self);
 	int error;
 	sc->sc_dev = self;
 	sc->sc_bst = faa->faa_bst;
 	sc->sc_dmat = faa->faa_dmat;
 	sc->sc_phandle = faa->faa_phandle;
 	sc->sc_clk_gpu = fdtbus_clock_get(faa->faa_phandle, "gpu");
 	if (sc->sc_clk_gpu == NULL) {
 		aprint_error(": couldn't get clock gpu\n");
 		return;
+	}
 	sc->sc_clk_pwr = fdtbus_clock_get(faa->faa_phandle, "pwr");
 	if (sc->sc_clk_pwr == NULL) {
 		aprint_error(": couldn't get clock pwr\n");
 		return;
+	}
 	sc->sc_rst_gpu = fdtbus_reset_get(faa->faa_phandle, "gpu");
 	if (sc->sc_rst_gpu == NULL) {
 		aprint_error(": couldn't get reset gpu\n");
 		return;
+	}
 	aprint_naive("\n");
 	aprint_normal(": GPU\n");
 	prop_dictionary_get_cstring(prop, "debug", &nouveau_debug);
 	prop_dictionary_get_cstring(prop, "config", &nouveau_config);
-	tegra_car_gpu_enable();
+	fdtbus_reset_assert(sc->sc_rst_gpu);
 	error = clk_set_rate(sc->sc_clk_pwr, 204000000);
 	if (error) {
 		aprint_error_dev(self, "couldn't set clock pwr frequency: %d\n",
 		    error);
 		return;
+	}
 	error = clk_enable(sc->sc_clk_pwr);
 	if (error) {
 		aprint_error_dev(self, "couldn't enable clock pwr: %d\n",
 		    error);
 		return;
+	}
 	error = clk_enable(sc->sc_clk_gpu);
 	if (error) {
 		aprint_error_dev(self, "couldn't enable clock gpu: %d\n",
 		    error);
 		return;
+	}
 	tegra_pmc_remove_clamping(PMC_PARTID_TD);
 	fdtbus_reset_deassert(sc->sc_rst_gpu);
 	error = -nouveau_device_create(&sc->sc_platform_dev,
 	    NOUVEAU_BUS_PLATFORM, -1, device_xname(self),
 	    nouveau_config, nouveau_debug, &sc->sc_nv_dev);
 	if (error) {
 		aprint_error_dev(self, "couldn't create nouveau device: %d\n",
 		    error);
 		return;
+	}
 	config_mountroot(self, tegra_nouveau_init);
+}

--- src/sys/arch/arm/nvidia/tegra_cec.c 2015/12/13 17:39:19	1.2
+++ src/sys/arch/arm/nvidia/tegra_cec.c 2015/12/22 22:10:36	1.3

 @@ -1,14 +1,14 @@
-/* $NetBSD: tegra_cec.c,v 1.2 2015/12/13 17:39:19 jmcneill Exp $ */
+/* $NetBSD: tegra_cec.c,v 1.3 2015/12/22 22:10:36 jmcneill Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -17,27 +17,27 @@
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_cec.c,v 1.2 2015/12/13 17:39:19 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_cec.c,v 1.3 2015/12/22 22:10:36 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/mutex.h>
 #include <sys/condvar.h>
 #include <sys/poll.h>
 #include <sys/select.h>
 #include <dev/hdmicec/hdmicecio.h>
 @@ -51,26 +51,28 @@ __KERNEL_RCSID(0, "$NetBSD: tegra_cec.c,
 #define CEC_VENDORID_NVIDIA	0x00044b
 static int	tegra_cec_match(device_t, cfdata_t, void *);
 static void	tegra_cec_attach(device_t, device_t, void *);
 static int	tegra_cec_intr(void *);
 struct tegra_cec_softc {
 	device_t		sc_dev;
 	bus_space_tag_t		sc_bst;
 	bus_space_handle_t	sc_bsh;
 	void			*sc_ih;
 	struct clk		*sc_clk;
 	struct fdtbus_reset	*sc_rst;
 	kmutex_t		sc_lock;
 	kcondvar_t		sc_cv;
 	const char		*sc_hdmidevname;
 	device_t		sc_cecdev;
 	struct selinfo		sc_selinfo;
 	uint8_t			sc_rxbuf[16];
 	int			sc_rxlen;
 	bool			sc_rxdone;
 @@ -124,26 +126,36 @@ tegra_cec_attach(device_t parent, device
 	struct tegra_cec_softc * const sc = device_private(self);
 	struct fdt_attach_args * const faa = aux;
 	prop_dictionary_t prop = device_properties(self);
 	struct hdmicec_attach_args caa;
 	char intrstr[128];
 	bus_addr_t addr;
 	bus_size_t size;
 	int error;
 	if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) {
 		aprint_error(": couldn't get registers\n");
 		return;
+	}
 	sc->sc_clk = fdtbus_clock_get(faa->faa_phandle, "cec");
 	if (sc->sc_clk == NULL) {
 		aprint_error(": couldn't get clock cec\n");
 		return;
+	}
 	sc->sc_rst = fdtbus_reset_get(faa->faa_phandle, "cec");
 	if (sc->sc_rst == NULL) {
 		aprint_error(": couldn't get reset cec\n");
 		return;
+	}
 	sc->sc_dev = self;
 	sc->sc_bst = faa->faa_bst;
 	error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
 	if (error) {
 		aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error);
 		return;
+	}
 	mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM);
 	cv_init(&sc->sc_cv, "tegracec");
 	selinit(&sc->sc_selinfo);
 	aprint_naive("\n");
 @@ -156,27 +168,33 @@ tegra_cec_attach(device_t parent, device
 	sc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_VM,
 	    FDT_INTR_MPSAFE, tegra_cec_intr, sc);
 	if (sc->sc_ih == NULL) {
 		aprint_error_dev(self, "couldn't establish interrupt on %s\n",
 		    intrstr);
 		return;
+	}
 	aprint_normal_dev(self, "interrupting on %s\n", intrstr);
 	prop_dictionary_get_cstring_nocopy(prop, "hdmi-device",
 	    &sc->sc_hdmidevname);
-	tegra_car_periph_cec_enable();
+	fdtbus_reset_assert(sc->sc_rst);
 	error = clk_enable(sc->sc_clk);
 	if (error) {
 		aprint_error_dev(self, "couldn't enable cec: %d\n", error);
 		return;
+	}
 	fdtbus_reset_deassert(sc->sc_rst);
 	CEC_WRITE(sc, CEC_SW_CONTROL_REG, 0);
 	CEC_WRITE(sc, CEC_INPUT_FILTER_REG, 0);
 	CEC_WRITE(sc, CEC_HW_CONTROL_REG, 0);
 	CEC_WRITE(sc, CEC_INT_MASK_REG, 0);
 	CEC_WRITE(sc, CEC_INT_STAT_REG, 0xffffffff);
 	memset(&caa, 0, sizeof(caa));
 	caa.priv = sc;
 	caa.hwif = &tegra_cec_hw_if;
 	sc->sc_cecdev = config_found(self, &caa, NULL);
+}

--- src/sys/arch/arm/nvidia/tegra_cpufreq.c 2015/11/21 12:09:39	1.2
+++ src/sys/arch/arm/nvidia/tegra_cpufreq.c 2015/12/22 22:10:36	1.3

 @@ -1,14 +1,14 @@
-/* $NetBSD: tegra_cpufreq.c,v 1.2 2015/11/21 12:09:39 jmcneill Exp $ */
+/* $NetBSD: tegra_cpufreq.c,v 1.3 2015/12/22 22:10:36 jmcneill Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -19,48 +19,47 @@
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include "locators.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_cpufreq.c,v 1.2 2015/11/21 12:09:39 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_cpufreq.c,v 1.3 2015/12/22 22:10:36 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/atomic.h>
 #include <sys/kmem.h>
 #include <sys/xcall.h>
 #include <sys/sysctl.h>
 #include <arm/nvidia/tegra_var.h>
 static u_int cpufreq_busy;
 static struct sysctllog *cpufreq_log;
 static int cpufreq_node_target, cpufreq_node_current, cpufreq_node_available;
 static const struct tegra_cpufreq_func *cpufreq_func = NULL;
 static void	tegra_cpufreq_post(void *, void *);
 static int	tegra_cpufreq_freq_helper(SYSCTLFN_PROTO);
 static char 	tegra_cpufreq_available[TEGRA_CPUFREQ_MAX * 5];
 #define cpufreq_set_rate	cpufreq_func->set_rate
 #define cpufreq_get_rate	cpufreq_func->get_rate
 #define cpufreq_get_available	cpufreq_func->get_available
 void
 tegra_cpufreq_register(const struct tegra_cpufreq_func *cf)
+{
 	KASSERT(cpufreq_func == NULL);
 	cpufreq_func = cf;
+}
 @@ -118,66 +117,56 @@ tegra_cpufreq_init(void)
 	    CTL_CREATE, CTL_EOL);
 	if (error)
 		goto sysctl_failed;
 	cpufreq_node_current = node->sysctl_num;
 	error = sysctl_createv(&cpufreq_log, 0, &freqnode, &node,
 , CTLTYPE_STRING, "available", NULL,
 	    NULL, 0, tegra_cpufreq_available, 0,
 	    CTL_CREATE, CTL_EOL);
 	if (error)
 		goto sysctl_failed;
 	cpufreq_node_available = node->sysctl_num;
 	device_printf(curcpu()->ci_dev,
 	    "setting speed to %d MHz\n", availfreq[0]);
 	cpufreq_set_rate(availfreq[0]);
 	tegra_cpufreq_post(NULL, NULL);
 	return;
 sysctl_failed:
 	aprint_error("cpufreq: couldn't create sysctl nodes (%d)\n", error);
 	sysctl_teardown(&cpufreq_log);
+}
 static void
 tegra_cpufreq_post(void *arg1, void *arg2)
 	struct cpu_info *ci = curcpu();
 	ci->ci_data.cpu_cc_freq = cpufreq_get_rate() * 1000000;
 static int
 tegra_cpufreq_freq_helper(SYSCTLFN_ARGS)
+{
 	struct sysctlnode node;
 	int fq, oldfq = 0, error;
 	uint64_t xc;
 	node = *rnode;
 	node.sysctl_data = &fq;
 	fq = cpufreq_get_rate();
 	if (rnode->sysctl_num == cpufreq_node_target)
 		oldfq = fq;
 	error = sysctl_lookup(SYSCTLFN_CALL(&node));
 	if (error || newp == NULL)
 		return error;
 	if (fq == oldfq || rnode->sysctl_num != cpufreq_node_target)
 		return 0;
 	if (atomic_cas_uint(&cpufreq_busy, 0, 1) != 0)
 		return EBUSY;
 	error = cpufreq_set_rate(fq);
 	if (error == 0) {
 		xc = xc_broadcast(0, tegra_cpufreq_post, NULL, NULL);
 		xc_wait(xc);
 		pmf_event_inject(NULL, PMFE_SPEED_CHANGED);
+	}
 	atomic_dec_uint(&cpufreq_busy);
 	return error;
+}

--- src/sys/arch/arm/nvidia/tegra_soctherm.c 2015/12/13 17:39:19	1.2
+++ src/sys/arch/arm/nvidia/tegra_soctherm.c 2015/12/22 22:10:36	1.3

 @@ -1,14 +1,14 @@
-/* $NetBSD: tegra_soctherm.c,v 1.2 2015/12/13 17:39:19 jmcneill Exp $ */
+/* $NetBSD: tegra_soctherm.c,v 1.3 2015/12/22 22:10:36 jmcneill Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -17,27 +17,27 @@
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_soctherm.c,v 1.2 2015/12/13 17:39:19 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_soctherm.c,v 1.3 2015/12/22 22:10:36 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/kmem.h>
 #include <dev/sysmon/sysmonvar.h>
 #include <arm/nvidia/tegra_reg.h>
 #include <arm/nvidia/tegra_socthermreg.h>
 @@ -110,37 +110,41 @@ static const struct tegra_soctherm_senso
 	  .s_fuse_corr_alpha = 1122300, .s_fuse_corr_beta = -5936400 },
 	{ .s_data = { .desc = "MEM1" }, .s_base = 0x160, .s_fuse = 0x15c,
 	  .s_fuse_corr_alpha = 1145700, .s_fuse_corr_beta = -7124600 },
 	{ .s_data = { .desc = "GPU" },  .s_base = 0x180, .s_fuse = 0x154,
 	  .s_fuse_corr_alpha = 1120100, .s_fuse_corr_beta = -6000500 },
 	{ .s_data = { .desc = "PLLX" }, .s_base = 0x1a0, .s_fuse = 0x160,
 	  .s_fuse_corr_alpha = 1106500, .s_fuse_corr_beta = -6729300 },
 };
 struct tegra_soctherm_softc {
 	device_t		sc_dev;
 	bus_space_tag_t		sc_bst;
 	bus_space_handle_t	sc_bsh;
 	struct clk		*sc_clk_tsensor;
 	struct clk		*sc_clk_soctherm;
 	struct fdtbus_reset	*sc_rst_soctherm;
 	struct sysmon_envsys	*sc_sme;
 	struct tegra_soctherm_sensor *sc_sensors;
 	const struct tegra_soctherm_config *sc_config;
 	uint32_t		sc_base_cp;
 	uint32_t		sc_base_ft;
 	int32_t			sc_actual_temp_cp;
 	int32_t			sc_actual_temp_ft;
 };
 static int	tegra_soctherm_init_clocks(struct tegra_soctherm_softc *);
 static void	tegra_soctherm_init_sensors(struct tegra_soctherm_softc *);
 static void	tegra_soctherm_init_sensor(struct tegra_soctherm_softc *,
 		    struct tegra_soctherm_sensor *);
 static void	tegra_soctherm_refresh(struct sysmon_envsys *, envsys_data_t *);
 static int	tegra_soctherm_decodeint(uint32_t, uint32_t);
 static int64_t	tegra_soctherm_divide(int64_t, int64_t);
 CFATTACH_DECL_NEW(tegra_soctherm, sizeof(struct tegra_soctherm_softc),
 	tegra_soctherm_match, tegra_soctherm_attach, NULL, NULL);
 #define SOCTHERM_READ(sc, reg)			\
     bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
 #define SOCTHERM_WRITE(sc, reg, val)		\
 @@ -167,52 +171,133 @@ tegra_soctherm_match(device_t parent, cf
 static void
 tegra_soctherm_attach(device_t parent, device_t self, void *aux)
+{
 	struct tegra_soctherm_softc * const sc = device_private(self);
 	struct fdt_attach_args * const faa = aux;
 	bus_addr_t addr;
 	bus_size_t size;
 	int error;
 	if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) {
 		aprint_error(": couldn't get registers\n");
 		return;
+	}
 	sc->sc_clk_tsensor = fdtbus_clock_get(faa->faa_phandle, "tsensor");
 	if (sc->sc_clk_tsensor == NULL) {
 		aprint_error(": couldn't get clock tsensor\n");
 		return;
+	}
 	sc->sc_clk_soctherm = fdtbus_clock_get(faa->faa_phandle, "soctherm");
 	if (sc->sc_clk_soctherm == NULL) {
 		aprint_error(": couldn't get clock soctherm\n");
 		return;
+	}
 	sc->sc_rst_soctherm = fdtbus_reset_get(faa->faa_phandle, "soctherm");
 	if (sc->sc_rst_soctherm == NULL) {
 		aprint_error(": couldn't get reset soctherm\n");
 		return;
+	}
 	sc->sc_dev = self;
 	sc->sc_bst = faa->faa_bst;
 	error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
 	if (error) {
 		aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error);
 		return;
+	}
 	aprint_naive("\n");
 	aprint_normal(": SOC_THERM\n");
 	if (tegra_chip_id() == CHIP_ID_TEGRA124) {
 		sc->sc_config = &tegra124_soctherm_config;
+	}
 	if (sc->sc_config == NULL) {
 		aprint_error_dev(self, "unsupported chip ID\n");
 		return;
+	}
-	tegra_car_soctherm_enable();
+	if (tegra_soctherm_init_clocks(sc) != 0)
 		return;
 	tegra_soctherm_init_sensors(sc);
+}
 static int
 tegra_soctherm_init_clocks(struct tegra_soctherm_softc *sc)
+{
 	struct clk *pll_p_out0;
 	struct clk *clk_m;
 	int error;
 	pll_p_out0 = clk_get("pll_p_out0");
 	if (pll_p_out0 == NULL) {
 		aprint_error_dev(sc->sc_dev, "couldn't find pll_p_out0\n");
 		return ENOENT;
+	}
 	clk_m = clk_get("clk_m");
 	if (clk_m == NULL) {
 		aprint_error_dev(sc->sc_dev, "couldn't find clk_m\n");
 		return ENOENT;
+	}
 	fdtbus_reset_assert(sc->sc_rst_soctherm);
 	error = clk_set_parent(sc->sc_clk_soctherm, pll_p_out0);
 	if (error) {
 		aprint_error_dev(sc->sc_dev,
 		    "couldn't set soctherm parent: %d\n", error);
 		return error;
+	}
 	error = clk_set_rate(sc->sc_clk_soctherm, 51000000);
 	if (error) {
 		aprint_error_dev(sc->sc_dev,
 		    "couldn't set soctherm rate: %d\n", error);
 		return error;
+	}
 	error = clk_set_parent(sc->sc_clk_tsensor, clk_m);
 	if (error) {
 		aprint_error_dev(sc->sc_dev,
 		    "couldn't set tsensor parent: %d\n", error);
 		return error;
+	}
 	error = clk_set_rate(sc->sc_clk_tsensor, 400000);
 	if (error) {
 		aprint_error_dev(sc->sc_dev,
 		    "couldn't set tsensor rate: %d\n", error);
 		return error;
+	}
 	error = clk_enable(sc->sc_clk_tsensor);
 	if (error) {
 		aprint_error_dev(sc->sc_dev, "couldn't enable tsensor: %d\n",
 		    error);
 		return error;
+	}
 	error = clk_enable(sc->sc_clk_soctherm);
 	if (error) {
 		aprint_error_dev(sc->sc_dev, "couldn't enable soctherm: %d\n",
 		    error);
 		return error;
+	}
 	fdtbus_reset_deassert(sc->sc_rst_soctherm);
 	return 0;
+}
 static void
 tegra_soctherm_init_sensors(struct tegra_soctherm_softc *sc)
+{
 	const struct tegra_soctherm_config *config = sc->sc_config;
 	const u_int nsensors = __arraycount(tegra_soctherm_sensors);
 	const size_t len = sizeof(*sc->sc_sensors) * nsensors;
 	uint32_t val;
 	u_int n;
 	val = tegra_fuse_read(FUSE_TSENSOR8_CALIB_REG);
 	sc->sc_base_cp = __SHIFTOUT(val, FUSE_TSENSOR8_CALIB_CP_TS_BASE);
 	sc->sc_base_ft = __SHIFTOUT(val, FUSE_TSENSOR8_CALIB_FT_TS_BASE);
 	val = tegra_fuse_read(FUSE_SPARE_REALIGNMENT_REG);

--- src/sys/arch/arm/nvidia/tegra_timer.c 2015/12/13 17:39:19	1.2
+++ src/sys/arch/arm/nvidia/tegra_timer.c 2015/12/22 22:10:36	1.3

 @@ -1,14 +1,14 @@
-/* $NetBSD: tegra_timer.c,v 1.2 2015/12/13 17:39:19 jmcneill Exp $ */
+/* $NetBSD: tegra_timer.c,v 1.3 2015/12/22 22:10:36 jmcneill Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -17,53 +17,54 @@
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_timer.c,v 1.2 2015/12/13 17:39:19 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_timer.c,v 1.3 2015/12/22 22:10:36 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/wdog.h>
 #include <dev/sysmon/sysmonvar.h>
 #include <arm/nvidia/tegra_reg.h>
 #include <arm/nvidia/tegra_timerreg.h>
 #include <arm/nvidia/tegra_var.h>
 #include <dev/fdt/fdtvar.h>
 #define TEGRA_TIMER_WDOG_PERIOD_DEFAULT	10
 static int	tegra_timer_match(device_t, cfdata_t, void *);
 static void	tegra_timer_attach(device_t, device_t, void *);
 struct tegra_timer_softc {
 	device_t		sc_dev;
 	bus_space_tag_t		sc_bst;
 	bus_space_handle_t	sc_bsh;
 	struct clk		*sc_clk_watchdog;
 	struct sysmon_wdog	sc_smw;
 };
 static int	tegra_timer_wdt_setmode(struct sysmon_wdog *);
 static int	tegra_timer_wdt_tickle(struct sysmon_wdog *);
 CFATTACH_DECL_NEW(tegra_timer, sizeof(struct tegra_timer_softc),
 	tegra_timer_match, tegra_timer_attach, NULL, NULL);
 #define TIMER_READ(sc, reg)			\
     bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
 #define TIMER_WRITE(sc, reg, val)		\
 @@ -83,73 +84,108 @@ tegra_timer_match(device_t parent, cfdat
 static void
 tegra_timer_attach(device_t parent, device_t self, void *aux)
+{
 	struct tegra_timer_softc * const sc = device_private(self);
 	struct fdt_attach_args * const faa = aux;
 	bus_addr_t addr;
 	bus_size_t size;
 	int error;
 	if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) {
 		aprint_error(": couldn't get registers\n");
 		return;
+	}
 	sc->sc_clk_watchdog = fdtbus_clock_get(faa->faa_phandle, "watchdog");
 	sc->sc_dev = self;
 	sc->sc_bst = faa->faa_bst;
 	error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
 	if (error) {
 		aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error);
 		return;
+	}
 	aprint_naive("\n");
 	aprint_normal(": Timers\n");
-	sc->sc_smw.smw_name = device_xname(self);
+	if (sc->sc_clk_watchdog) {
-	sc->sc_smw.smw_cookie = sc;
+		sc->sc_smw.smw_name = device_xname(self);
-	sc->sc_smw.smw_setmode = tegra_timer_wdt_setmode;
+		sc->sc_smw.smw_cookie = sc;
-	sc->sc_smw.smw_tickle = tegra_timer_wdt_tickle;
+		sc->sc_smw.smw_setmode = tegra_timer_wdt_setmode;
-	sc->sc_smw.smw_period = TEGRA_TIMER_WDOG_PERIOD_DEFAULT;
+		sc->sc_smw.smw_tickle = tegra_timer_wdt_tickle;
 		sc->sc_smw.smw_period = TEGRA_TIMER_WDOG_PERIOD_DEFAULT;
 	aprint_normal_dev(self, "default watchdog period is %u seconds\n",
-	    sc->sc_smw.smw_period);
+		aprint_normal_dev(self,
 		    "default watchdog period is %u seconds\n",
-	if (sysmon_wdog_register(&sc->sc_smw) != 0)
+		    sc->sc_smw.smw_period);
 		aprint_error_dev(self, "couldn't register with sysmon\n");
 		if (sysmon_wdog_register(&sc->sc_smw) != 0) {
 			aprint_error_dev(self,
 			    "couldn't register with sysmon\n");
+		}
+	}
+}
 static int
 tegra_timer_wdt_setmode(struct sysmon_wdog *smw)
+{
 	struct tegra_timer_softc * const sc = smw->smw_cookie;
 	if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) {
 		TIMER_SET_CLEAR(sc, TMR1_PTV_REG, 0, TMR_PTV_EN);
-		tegra_car_wdt_enable(1, false);
+		return clk_disable(sc->sc_clk_watchdog);
 	} else {
 		if (smw->smw_period == WDOG_PERIOD_DEFAULT) {
 			sc->sc_smw.smw_period = TEGRA_TIMER_WDOG_PERIOD_DEFAULT;
 		} else if (smw->smw_period == 0 || smw->smw_period > 1000) {
 			return EINVAL;
 		} else {
 			sc->sc_smw.smw_period = smw->smw_period;
+		}
 		u_int tval = (sc->sc_smw.smw_period * 1000000) / 2;
 		TIMER_WRITE(sc, TMR1_PTV_REG,
 		    TMR_PTV_EN | TMR_PTV_PER | __SHIFTIN(tval, TMR_PTV_VAL));
 		TIMER_WRITE(sc, TMR1_PCR_REG, TMR_PCR_INTR_CLR);
-		tegra_car_wdt_enable(1, true);
+		return clk_enable(sc->sc_clk_watchdog);
+	}
 	return 0;
+}
 static int
 tegra_timer_wdt_tickle(struct sysmon_wdog *smw)
+{
 	struct tegra_timer_softc * const sc = smw->smw_cookie;
 	TIMER_WRITE(sc, TMR1_PCR_REG, TMR_PCR_INTR_CLR);
 	return 0;
+}
 void
 delay(u_int us)
+{
 	static bool timerus_configured = false;
 	bus_space_tag_t bst = &armv7_generic_bs_tag;
 	bus_space_handle_t bsh;
 	bus_space_subregion(bst, tegra_ppsb_bsh, TEGRA_TIMER_OFFSET,
 	    TEGRA_TIMER_SIZE, &bsh);
 	if (__predict_false(timerus_configured == false)) {
 		/* clk_m frequency 12 MHz */
 		bus_space_write_4(bst, bsh, TMRUS_USEC_CFG_REG, 0xb);
 		timerus_configured = true;
+	}
 	u_int nus = 0;
 	u_int us_prev = bus_space_read_4(bst, bsh, TMRUS_CNTR_1US_REG);
 	while (nus < us) {
 		const u_int us_cur = bus_space_read_4(bst, bsh,
 		    TMRUS_CNTR_1US_REG);
 		if (us_cur < us_prev) {
 			nus += (0xffffffff - us_prev) + us_cur;
 		} else {
 			nus += (us_cur - us_prev);
+		}
 		us_prev = us_cur;
+	}
+}

--- src/sys/arch/arm/nvidia/tegra_com.c 2015/12/16 19:46:55	1.4
+++ src/sys/arch/arm/nvidia/tegra_com.c 2015/12/22 22:10:36	1.5

 @@ -1,14 +1,14 @@
-/* $NetBSD: tegra_com.c,v 1.4 2015/12/16 19:46:55 jmcneill Exp $ */
+/* $NetBSD: tegra_com.c,v 1.5 2015/12/22 22:10:36 jmcneill Exp $ */
 /*-
  * Copyright (c) 2013 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Matt Thomas of 3am Software Foundry.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -21,67 +21,52 @@
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: tegra_com.c,v 1.4 2015/12/16 19:46:55 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: tegra_com.c,v 1.5 2015/12/22 22:10:36 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/time.h>
 #include <sys/termios.h>
 #include <arm/nvidia/tegra_reg.h>
 #include <arm/nvidia/tegra_var.h>
 #include <dev/ic/comvar.h>
 #include <dev/fdt/fdtvar.h>
 /* XXX */
 static int
 tegra_com_addr2port(bus_addr_t addr)
 	switch (addr) {
 	case TEGRA_APB_BASE + TEGRA_UARTA_OFFSET:
 		return 0;
 	case TEGRA_APB_BASE + TEGRA_UARTB_OFFSET:
 		return 1;
 	case TEGRA_APB_BASE + TEGRA_UARTC_OFFSET:
 		return 2;
 	case TEGRA_APB_BASE + TEGRA_UARTD_OFFSET:
 		return 3;
 	default:
 		return -1;
 static int tegra_com_match(device_t, cfdata_t, void *);
 static void tegra_com_attach(device_t, device_t, void *);
 struct tegra_com_softc {
 	struct com_softc tsc_sc;
 	void *tsc_ih;
 	struct clk *tsc_clk;
 	struct fdtbus_reset *tsc_rst;
 };
 CFATTACH_DECL_NEW(tegra_com, sizeof(struct tegra_com_softc),
 	tegra_com_match, tegra_com_attach, NULL, NULL);
 static int
 tegra_com_match(device_t parent, cfdata_t cf, void *aux)
+{
 	const char * const compatible[] = { "nvidia,tegra124-uart", NULL };
 	struct fdt_attach_args * const faa = aux;
 	return of_match_compatible(faa->faa_phandle, compatible);
+}
 @@ -112,32 +97,35 @@ tegra_com_attach(device_t parent, device
 		if (reg_shift == 2) {
 			bst = faa->faa_a4x_bst;
 		} else if (reg_shift == 0) {
 			bst = faa->faa_bst;
 		} else {
 			aprint_error(": unsupported reg-shift value %d\n",
 			    reg_shift);
 			return;
+		}
+	}
 	sc->sc_dev = self;
-	/* XXX */
+	tsc->tsc_clk = fdtbus_clock_get_index(faa->faa_phandle, 0);
-	const int port = tegra_com_addr2port(addr);
+	tsc->tsc_rst = fdtbus_reset_get(faa->faa_phandle, "serial");
 	if (port == -1) {
-		panic("unsupported com address %#llx", (uint64_t)addr);
+	if (tsc->tsc_clk == NULL) {
 		aprint_error(": couldn't get frequency\n");
 		return;
+	}
 	sc->sc_frequency = tegra_car_uart_rate(port);
 	sc->sc_frequency = clk_get_rate(tsc->tsc_clk);
 	sc->sc_type = COM_TYPE_TEGRA;
 	error = bus_space_map(bst, addr, size, 0, &bsh);
 	if (error) {
 		aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error);
 		return;
+	}
 	COM_INIT_REGS(sc->sc_regs, bst, bsh, addr);
 	com_attach_subr(sc);
 	aprint_naive("\n");

--- src/sys/arch/arm/nvidia/tegra_drm.c 2015/12/13 17:39:19	1.4
+++ src/sys/arch/arm/nvidia/tegra_drm.c 2015/12/22 22:10:36	1.5

 @@ -1,14 +1,14 @@
-/* $NetBSD: tegra_drm.c,v 1.4 2015/12/13 17:39:19 jmcneill Exp $ */
+/* $NetBSD: tegra_drm.c,v 1.5 2015/12/22 22:10:36 jmcneill Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -17,27 +17,27 @@
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_drm.c,v 1.4 2015/12/13 17:39:19 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_drm.c,v 1.5 2015/12/22 22:10:36 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/conf.h>
 #include <uvm/uvm_extern.h>
 #include <uvm/uvm_device.h>
 #include <drm/drmP.h>
 @@ -111,47 +111,69 @@ tegra_drm_match(device_t parent, cfdata_
 	return of_match_compatible(faa->faa_phandle, compatible);
+}
 static void
 tegra_drm_attach(device_t parent, device_t self, void *aux)
+{
 	struct tegra_drm_softc * const sc = device_private(self);
 	struct fdt_attach_args * const faa = aux;
 	struct drm_driver * const driver = &tegra_drm_driver;
 	prop_dictionary_t prop = device_properties(self);
 	int error, node, hdmi_phandle, ddc_phandle;
 	const char * const hdmi_compat[] = { "nvidia,tegra124-hdmi", NULL };
 	const char * const dc_compat[] = { "nvidia,tegra124-dc", NULL };
 	const char * const hdmi_supplies[] = {
 		"hdmi-supply", "pll-supply", "vdd-supply"
 	};
 	struct fdtbus_regulator *reg;
-	u_int n;
+	struct clk *pll_p_out0;
 	u_int n, ndc;
 	sc->sc_dev = self;
 	sc->sc_dmat = faa->faa_dmat;
 	sc->sc_bst = faa->faa_bst;
 	sc->sc_phandle = faa->faa_phandle;
 	aprint_naive("\n");
 	aprint_normal("\n");
-	tegra_car_host1x_enable();
+	sc->sc_clk_host1x = fdtbus_clock_get_index(faa->faa_phandle, 0);
 	if (sc->sc_clk_host1x == NULL) {
 		aprint_error_dev(self, "couldn't get clock host1x\n");
 		return;
+	}
 	sc->sc_rst_host1x = fdtbus_reset_get(faa->faa_phandle, "host1x");
 	if (sc->sc_clk_host1x == NULL || sc->sc_rst_host1x == NULL) {
 		aprint_error_dev(self, "couldn't get reset host1x\n");
 		return;
+	}
 	ndc = 0;
 	hdmi_phandle = -1;
 	for (node = OF_child(faa->faa_phandle); node; node = OF_peer(node)) {
 		if (of_match_compatible(node, hdmi_compat)) {
 			sc->sc_clk_hdmi = fdtbus_clock_get(node, "hdmi");
 			sc->sc_clk_hdmi_parent = fdtbus_clock_get(node,
 			    "parent");
 			sc->sc_rst_hdmi = fdtbus_reset_get(node, "hdmi");
 			hdmi_phandle = node;
-			break;
+		} else if (of_match_compatible(node, dc_compat) &&
 			   ndc < __arraycount(sc->sc_clk_dc)) {
 			sc->sc_clk_dc[ndc] = fdtbus_clock_get(node, "dc");
 			sc->sc_clk_dc_parent[ndc] = fdtbus_clock_get(node,
 			    "parent");
 			sc->sc_rst_dc[ndc] = fdtbus_reset_get(node, "dc");
 			++ndc;
+		}
+	}
 	if (hdmi_phandle >= 0) {
 		ddc_phandle = fdtbus_get_phandle(hdmi_phandle,
 		    "nvidia,ddc-i2c-bus");
 		if (ddc_phandle >= 0) {
 			sc->sc_ddc = fdtbus_get_i2c_tag(ddc_phandle);
+		}
 		sc->sc_pin_hpd = fdtbus_gpio_acquire(hdmi_phandle,
 		    "nvidia,hpd-gpio", GPIO_PIN_INPUT);
 		for (n = 0; n < __arraycount(hdmi_supplies); n++) {
 @@ -160,26 +182,53 @@ tegra_drm_attach(device_t parent, device
 			if (reg == NULL) {
 				aprint_error_dev(self, "couldn't acquire %s\n",
 				    supply);
 				continue;
+			}
 			if (fdtbus_regulator_enable(reg) != 0) {
 				aprint_error_dev(self, "couldn't enable %s\n",
 				    supply);
+			}
 			fdtbus_regulator_release(reg);
+		}
+	}
 	pll_p_out0 = clk_get("pll_p_out0");
 	if (pll_p_out0 == NULL) {
 		aprint_error_dev(self, "couldn't get clock pll_p_out0\n");
 		return;
+	}
 	fdtbus_reset_assert(sc->sc_rst_host1x);
 	error = clk_set_parent(sc->sc_clk_host1x, pll_p_out0);
 	if (error) {
 		aprint_error_dev(self, "couldn't set host1x clock parent: %d\n",
 		    error);
 		return;
+	}
 	error = clk_set_rate(sc->sc_clk_host1x, 408000000);
 	if (error) {
 		aprint_error_dev(self, "couldn't set host1x frequency: %d\n",
 		    error);
 		return;
+	}
 	error = clk_enable(sc->sc_clk_host1x);
 	if (error) {
 		aprint_error_dev(self, "couldn't enable clock host1x: %d\n",
 		    error);
 		return;
+	}
 	fdtbus_reset_deassert(sc->sc_rst_host1x);
 	clk_put(pll_p_out0);
 	prop_dictionary_get_bool(prop, "force-dvi", &sc->sc_force_dvi);
 	driver->bus = &tegra_drm_bus;
 	sc->sc_ddev = drm_dev_alloc(driver, sc->sc_dev);
 	if (sc->sc_ddev == NULL) {
 		aprint_error_dev(self, "couldn't allocate DRM device\n");
 		return;
+	}
 	sc->sc_ddev->dev_private = sc;
 	error = -drm_dev_register(sc->sc_ddev, 0);
 	if (error) {

--- src/sys/arch/arm/nvidia/tegra_usbphy.c 2015/12/16 19:46:55	1.4
+++ src/sys/arch/arm/nvidia/tegra_usbphy.c 2015/12/22 22:10:36	1.5

 @@ -1,14 +1,14 @@
-/* $NetBSD: tegra_usbphy.c,v 1.4 2015/12/16 19:46:55 jmcneill Exp $ */
+/* $NetBSD: tegra_usbphy.c,v 1.5 2015/12/22 22:10:36 jmcneill Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -17,66 +17,55 @@
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_usbphy.c,v 1.4 2015/12/16 19:46:55 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_usbphy.c,v 1.5 2015/12/22 22:10:36 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/atomic.h>
 #include <arm/nvidia/tegra_reg.h>
 #include <arm/nvidia/tegra_var.h>
 #include <arm/nvidia/tegra_usbreg.h>
 #include <dev/fdt/fdtvar.h>
 /* XXX */
 static int
 tegra_usbphy_addr2port(bus_addr_t addr)
 	switch (addr) {
 	case TEGRA_AHB_A2_BASE + TEGRA_USB1_OFFSET:
 		return 0;
 	case TEGRA_AHB_A2_BASE + TEGRA_USB2_OFFSET:
 		return 1;
 	case TEGRA_AHB_A2_BASE + TEGRA_USB3_OFFSET:
 		return 2;
 	default:
 		return -1;
 static int	tegra_usbphy_match(device_t, cfdata_t, void *);
 static void	tegra_usbphy_attach(device_t, device_t, void *);
 struct tegra_usbphy_softc {
 	device_t		sc_dev;
 	bus_space_tag_t		sc_bst;
 	bus_space_handle_t	sc_bsh;
 	int			sc_phandle;
-	u_int			sc_port;
+	struct clk		*sc_clk_reg;
 	struct clk		*sc_clk_pll;
 	struct clk		*sc_clk_utmip;
 	struct fdtbus_reset	*sc_rst_usb;
 	struct fdtbus_reset	*sc_rst_utmip;
 	struct tegra_gpio_pin	*sc_pin_vbus;
 	uint32_t		sc_hssync_start_delay;
 	uint32_t		sc_idle_wait_delay;
 	uint32_t		sc_elastic_limit;
 	uint32_t		sc_term_range_adj;
 	uint32_t		sc_xcvr_setup;
 	uint32_t		sc_xcvr_lsfslew;
 	uint32_t		sc_xcvr_lsrslew;
 	uint32_t		sc_hssquelch_level;
 	uint32_t		sc_hsdiscon_level;
 	uint32_t		sc_xcvr_hsslew;
 };
 @@ -92,57 +81,88 @@ tegra_usbphy_match(device_t parent, cfda
+{
 	const char * const compatible[] = { "nvidia,tegra124-usb-phy", NULL };
 	struct fdt_attach_args * const faa = aux;
 	return of_match_compatible(faa->faa_phandle, compatible);
+}
 static void
 tegra_usbphy_attach(device_t parent, device_t self, void *aux)
+{
 	struct tegra_usbphy_softc * const sc = device_private(self);
 	struct fdt_attach_args * const faa = aux;
 	struct fdtbus_regulator *reg;
 	const int phandle = faa->faa_phandle;
 	bus_addr_t addr;
 	bus_size_t size;
 	int error;
-	if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) {
+	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
 		aprint_error(": couldn't get registers\n");
 		return;
+	}
 	sc->sc_clk_reg = fdtbus_clock_get(phandle, "reg");
 	if (sc->sc_clk_reg == NULL) {
 		aprint_error(": couldn't get clock reg\n");
 		return;
+	}
 	sc->sc_clk_pll = fdtbus_clock_get(phandle, "pll_u");
 	if (sc->sc_clk_pll == NULL) {
 		aprint_error(": couldn't get clock pll_u\n");
 		return;
+	}
 	sc->sc_clk_utmip = fdtbus_clock_get(phandle, "utmi-pads");
 	if (sc->sc_clk_utmip == NULL) {
 		aprint_error(": couldn't get clock utmi-pads\n");
 		return;
+	}
 	sc->sc_rst_usb = fdtbus_reset_get(phandle, "usb");
 	if (sc->sc_rst_usb == NULL) {
 		aprint_error(": couldn't get reset usb\n");
 		return;
+	}
 	sc->sc_rst_utmip = fdtbus_reset_get(phandle, "utmi-pads");
 	if (sc->sc_rst_utmip == NULL) {
 		aprint_error(": couldn't get reset utmi-pads\n");
 		return;
+	}
 	sc->sc_dev = self;
-	sc->sc_phandle = faa->faa_phandle;
+	sc->sc_phandle = phandle;
 	sc->sc_bst = faa->faa_bst;
 	error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
 	if (error) {
 		aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error);
 		return;
+	}
 	sc->sc_port = tegra_usbphy_addr2port(addr);
 	aprint_naive("\n");
-	aprint_normal(": USB PHY%d\n", sc->sc_port + 1);
+	aprint_normal(": USB PHY\n");
 	if (tegra_usbphy_parse_properties(sc) != 0)
 		return;
-	tegra_car_periph_usb_enable(sc->sc_port);
+	fdtbus_reset_assert(sc->sc_rst_usb);
-	delay(2);
+	error = clk_enable(sc->sc_clk_reg);
 	if (error) {
 		aprint_error_dev(self, "couldn't enable clock reg: %d\n",
 		    error);
 		return;
+	}
 	fdtbus_reset_deassert(sc->sc_rst_usb);
 	tegra_usbphy_utmip_init(sc);
-	reg = fdtbus_regulator_acquire(faa->faa_phandle, "vbus-supply");
+	reg = fdtbus_regulator_acquire(phandle, "vbus-supply");
 	if (reg) {
 		const uint32_t v = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
 		    TEGRA_EHCI_PHY_VBUS_SENSORS_REG);
 		if ((v & TEGRA_EHCI_PHY_VBUS_SENSORS_A_VBUS_VLD_STS) == 0) {
 			fdtbus_regulator_enable(reg);
 		} else {
 			aprint_normal_dev(self, "VBUS input active\n");
+		}
+        }
+}
 static int
 tegra_usbphy_parse_properties(struct tegra_usbphy_softc *sc)
 @@ -162,72 +182,74 @@ tegra_usbphy_parse_properties(struct teg
 	PROPGET("nvidia,xcvr-lsfslew", &sc->sc_xcvr_lsfslew);
 	PROPGET("nvidia,xcvr-lsrslew", &sc->sc_xcvr_lsrslew);
 	PROPGET("nvidia,hssquelch-level", &sc->sc_hssquelch_level);
 	PROPGET("nvidia,hsdiscon-level", &sc->sc_hsdiscon_level);
 	PROPGET("nvidia,xcvr-hsslew", &sc->sc_xcvr_hsslew);
 	return 0;
 #undef PROPGET
+}
 static void
 tegra_usbphy_utmip_init(struct tegra_usbphy_softc *sc)
+{
 	static u_int init_count = 0;
 	bus_space_tag_t bst = sc->sc_bst;
 	bus_space_handle_t bsh = sc->sc_bsh;
 	int retry;
 	/* Put UTMIP PHY into reset before programming UTMIP config registers */
 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_SUSP_CTRL_REG,
 	    TEGRA_EHCI_SUSP_CTRL_UTMIP_RESET, 0);
 	/* Enable UTMIP PHY mode */
 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_SUSP_CTRL_REG,
 	    TEGRA_EHCI_SUSP_CTRL_UTMIP_PHY_ENB, 0);
 	/* Stop crystal clock */
 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_MISC_CFG1_REG,
 , TEGRA_EHCI_UTMIP_MISC_CFG1_PHY_XTAL_CLOCKEN);
 	delay(1);
 	/* Clear session status */
 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_PHY_VBUS_SENSORS_REG,
 ,
 	    TEGRA_EHCI_PHY_VBUS_SENSORS_B_VLD_SW_VALUE |
 	    TEGRA_EHCI_PHY_VBUS_SENSORS_B_VLD_SW_EN);
 	/* PLL configuration */
 	tegra_car_utmip_init();
 	/* Transceiver configuration */
 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG0_REG,
 	    __SHIFTIN(4, TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP) |
 	    __SHIFTIN(3, TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP_MSB) |
 	    __SHIFTIN(sc->sc_xcvr_hsslew,
 		      TEGRA_EHCI_UTMIP_XCVR_CFG0_HSSLEW_MSB),
 	    TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP |
 	    TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP_MSB |
 	    TEGRA_EHCI_UTMIP_XCVR_CFG0_HSSLEW_MSB);
 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG1_REG,
 	    __SHIFTIN(sc->sc_term_range_adj,
 		      TEGRA_EHCI_UTMIP_XCVR_CFG1_TERM_RANGE_ADJ),
 	    TEGRA_EHCI_UTMIP_XCVR_CFG1_TERM_RANGE_ADJ);
-	if (sc->sc_port == 0) {
+	if (atomic_inc_uint_nv(&init_count) == 1) {
 		tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG0_REG,
 		    TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL_MSB |
 		    __SHIFTIN(sc->sc_hsdiscon_level,
 			      TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL),
 		    TEGRA_EHCI_UTMIP_BIAS_CFG0_BIASPD |
 		    TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL);
 		delay(25);
 		tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG1_REG,
 , TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_POWERDOWN);
+	}
 	/* Misc config */
 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_MISC_CFG0_REG,
 ,
 	    TEGRA_EHCI_UTMIP_MISC_CFG0_SUSPEND_EXIT_ON_EDGE);
 	/* BIAS cell power down lag */
 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG1_REG,
 	    __SHIFTIN(5, TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_COUNT),
 	    TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_COUNT);
 	/* Debounce config */
 @@ -255,29 +277,26 @@ tegra_usbphy_utmip_init(struct tegra_usb
 		      TEGRA_EHCI_UTMIP_HSRX_CFG0_ELASTIC_LIMIT),
 	    TEGRA_EHCI_UTMIP_HSRX_CFG0_IDLE_WAIT |
 	    TEGRA_EHCI_UTMIP_HSRX_CFG0_ELASTIC_LIMIT);
 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_HSRX_CFG1_REG,
 	    __SHIFTIN(sc->sc_hssync_start_delay,
 		      TEGRA_EHCI_UTMIP_HSRX_CFG1_SYNC_START_DLY),
 	    TEGRA_EHCI_UTMIP_HSRX_CFG1_SYNC_START_DLY);
 	/* Start crystal clock */
 	delay(1);
 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_MISC_CFG1_REG,
 	    TEGRA_EHCI_UTMIP_MISC_CFG1_PHY_XTAL_CLOCKEN, 0);
 	/* Clear port PLL powerdown status */
 	tegra_car_utmip_enable(sc->sc_port);
 	/* Bring UTMIP PHY out of reset */
 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_SUSP_CTRL_REG,
 , TEGRA_EHCI_SUSP_CTRL_UTMIP_RESET);
 	for (retry = 100000; retry > 0; retry--) {
 		const uint32_t susp = bus_space_read_4(bst, bsh,
 		    TEGRA_EHCI_SUSP_CTRL_REG);
 		if (susp & TEGRA_EHCI_SUSP_CTRL_PHY_CLK_VALID)
 			break;
 		delay(1);
+	}
 	if (retry == 0) {
 		aprint_error_dev(sc->sc_dev, "PHY clock is not valid\n");
 		return;
 @@ -289,22 +308,14 @@ tegra_usbphy_utmip_init(struct tegra_usb
 	    TEGRA_EHCI_ICUSB_CTRL_ENB1);
 	/* Power up UTMPI transceiver */
 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG0_REG,
 ,
 	    TEGRA_EHCI_UTMIP_XCVR_CFG0_PD_POWERDOWN |
 	    TEGRA_EHCI_UTMIP_XCVR_CFG0_PD2_POWERDOWN |
 	    TEGRA_EHCI_UTMIP_XCVR_CFG0_PDZI_POWERDOWN);
 	tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG1_REG,
 ,
 	    TEGRA_EHCI_UTMIP_XCVR_CFG1_PDDISC_POWERDOWN |
 	    TEGRA_EHCI_UTMIP_XCVR_CFG1_PDCHRP_POWERDOWN |
 	    TEGRA_EHCI_UTMIP_XCVR_CFG1_PDDR_POWERDOWN);
 	if (sc->sc_port == 0) {
 		tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG0_REG,
 , TEGRA_EHCI_UTMIP_BIAS_CFG0_BIASPD);
 		delay(25);
 		tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG1_REG,
 , TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_POWERDOWN);
+}

--- src/sys/arch/arm/nvidia/tegra_drm.h 2015/12/13 17:39:19	1.5
+++ src/sys/arch/arm/nvidia/tegra_drm.h 2015/12/22 22:10:36	1.6

 @@ -1,14 +1,14 @@
-/* $NetBSD: tegra_drm.h,v 1.5 2015/12/13 17:39:19 jmcneill Exp $ */
+/* $NetBSD: tegra_drm.h,v 1.6 2015/12/22 22:10:36 jmcneill Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -44,54 +44,63 @@
 struct tegra_framebuffer;
 struct tegra_gem_object;
 struct tegra_drm_softc {
 	device_t		sc_dev;
 	struct drm_device	*sc_ddev;
 	bus_space_tag_t		sc_bst;
 	bus_dma_tag_t		sc_dmat;
 	int			sc_phandle;
 	struct clk		*sc_clk_host1x;
 	struct fdtbus_reset	*sc_rst_host1x;
 	struct clk		*sc_clk_dc[2];
 	struct clk		*sc_clk_dc_parent[2];
 	struct fdtbus_reset	*sc_rst_dc[2];
 	struct clk		*sc_clk_hdmi;
 	struct clk		*sc_clk_hdmi_parent;
 	struct fdtbus_reset	*sc_rst_hdmi;
 	i2c_tag_t		sc_ddc;
 	struct fdtbus_gpio_pin	*sc_pin_hpd;
 	struct tegra_gpio_pin	*sc_pin_pll;
 	struct tegra_gpio_pin	*sc_pin_power;
 	bool			sc_force_dvi;
 	uint32_t		sc_vbl_received[2];
 };
 struct tegra_drmfb_attach_args {
 	struct drm_device	*tfa_drm_dev;
 	struct drm_fb_helper	*tfa_fb_helper;
 	struct drm_fb_helper_surface_size tfa_fb_sizes;
 	bus_space_tag_t		tfa_fb_bst;
 	bus_dma_tag_t		tfa_fb_dmat;
 };
 struct tegra_crtc {
 	struct drm_crtc		base;
 	bus_space_tag_t		bst;
 	bus_space_handle_t	bsh;
 	bus_size_t		size;
 	int			intr;
 	int			index;
 	void			*ih;
 	bool			enabled;
 	struct clk		*clk_parent;
 	struct tegra_gem_object	*cursor_obj;
 	int			cursor_x;
 	int			cursor_y;
 };
 struct tegra_encoder {
 	struct drm_encoder	base;
 	bus_space_tag_t		bst;
 	bus_space_handle_t	bsh;
 	bus_size_t		size;
 };

--- src/sys/arch/arm/nvidia/tegra_hdaudio.c 2015/12/13 17:39:19	1.5
+++ src/sys/arch/arm/nvidia/tegra_hdaudio.c 2015/12/22 22:10:36	1.6

 @@ -1,14 +1,14 @@
-/* $NetBSD: tegra_hdaudio.c,v 1.5 2015/12/13 17:39:19 jmcneill Exp $ */
+/* $NetBSD: tegra_hdaudio.c,v 1.6 2015/12/22 22:10:36 jmcneill Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -17,27 +17,27 @@
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_hdaudio.c,v 1.5 2015/12/13 17:39:19 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_hdaudio.c,v 1.6 2015/12/22 22:10:36 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <dev/hdaudio/hdaudioreg.h>
 #include <dev/hdaudio/hdaudiovar.h>
 #include <arm/nvidia/tegra_var.h>
 #include <arm/nvidia/tegra_pmcreg.h>
 @@ -57,97 +57,212 @@ static int	tegra_hdaudio_match(device_t,
 static void	tegra_hdaudio_attach(device_t, device_t, void *);
 static int	tegra_hdaudio_detach(device_t, int);
 static int	tegra_hdaudio_rescan(device_t, const char *, const int *);
 static void	tegra_hdaudio_childdet(device_t, device_t);
 static int	tegra_hdaudio_intr(void *);
 struct tegra_hdaudio_softc {
 	struct hdaudio_softc	sc;
 	bus_space_tag_t		sc_bst;
 	bus_space_handle_t	sc_bsh;
 	void			*sc_ih;
 	int			sc_phandle;
 	struct clk		*sc_clk_hda;
 	struct clk		*sc_clk_hda2hdmi;
 	struct clk		*sc_clk_hda2codec_2x;
 	struct fdtbus_reset	*sc_rst_hda;
 	struct fdtbus_reset	*sc_rst_hda2hdmi;
 	struct fdtbus_reset	*sc_rst_hda2codec_2x;
 };
 static int	tegra_hdaudio_init_clocks(struct tegra_hdaudio_softc *);
 static void	tegra_hdaudio_init(struct tegra_hdaudio_softc *);
 CFATTACH_DECL2_NEW(tegra_hdaudio, sizeof(struct tegra_hdaudio_softc),
 	tegra_hdaudio_match, tegra_hdaudio_attach, tegra_hdaudio_detach, NULL,
 	tegra_hdaudio_rescan, tegra_hdaudio_childdet);
 static int
 tegra_hdaudio_match(device_t parent, cfdata_t cf, void *aux)
+{
 	const char * const compatible[] = { "nvidia,tegra124-hda", NULL };
 	struct fdt_attach_args * const faa = aux;
 	return of_match_compatible(faa->faa_phandle, compatible);
+}
 static void
 tegra_hdaudio_attach(device_t parent, device_t self, void *aux)
+{
 	struct tegra_hdaudio_softc * const sc = device_private(self);
 	struct fdt_attach_args * const faa = aux;
 	const int phandle = faa->faa_phandle;
 	char intrstr[128];
 	bus_addr_t addr;
 	bus_size_t size;
 	int error;
-	if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) {
+	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
 		aprint_error(": couldn't get registers\n");
 		return;
+	}
 	sc->sc_clk_hda = fdtbus_clock_get(phandle, "hda");
 	if (sc->sc_clk_hda == NULL) {
 		aprint_error(": couldn't get clock hda\n");
 		return;
+	}
 	sc->sc_clk_hda2hdmi = fdtbus_clock_get(phandle, "hda2hdmi");
 	if (sc->sc_clk_hda2hdmi == NULL) {
 		aprint_error(": couldn't get clock hda2hdmi\n");
 		return;
+	}
 	sc->sc_clk_hda2codec_2x = fdtbus_clock_get(phandle, "hda2codec_2x");
 	if (sc->sc_clk_hda2codec_2x == NULL) {
 		aprint_error(": couldn't get clock hda2codec_2x\n");
 		return;
+	}
 	sc->sc_rst_hda = fdtbus_reset_get(phandle, "hda");
 	if (sc->sc_rst_hda == NULL) {
 		aprint_error(": couldn't get reset hda\n");
 		return;
+	}
 	sc->sc_rst_hda2hdmi = fdtbus_reset_get(phandle, "hda2hdmi");
 	if (sc->sc_rst_hda2hdmi == NULL) {
 		aprint_error(": couldn't get reset hda2hdmi\n");
 		return;
+	}
 	sc->sc_rst_hda2codec_2x = fdtbus_reset_get(phandle, "hda2codec_2x");
 	if (sc->sc_rst_hda2codec_2x == NULL) {
 		aprint_error(": couldn't get reset hda2codec_2x\n");
 		return;
+	}
-	sc->sc_phandle = faa->faa_phandle;
+	sc->sc_phandle = phandle;
 	sc->sc_bst = faa->faa_bst;
 	error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
 	if (error) {
 		aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error);
 		return;
+	}
 	sc->sc.sc_dev = self;
 	sc->sc.sc_memt = faa->faa_bst;
 	bus_space_subregion(sc->sc.sc_memt, sc->sc_bsh, TEGRA_HDAUDIO_OFFSET,
 	    size - TEGRA_HDAUDIO_OFFSET, &sc->sc.sc_memh);
 	sc->sc.sc_memvalid = true;
 	sc->sc.sc_dmat = faa->faa_dmat;
 	sc->sc.sc_flags = HDAUDIO_FLAG_NO_STREAM_RESET;
 	aprint_naive("\n");
 	aprint_normal(": HDA\n");
-	if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) {
+	if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
 		aprint_error_dev(self, "failed to decode interrupt\n");
 		return;
+	}
-	sc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_AUDIO, 0,
+	sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_AUDIO, 0,
 	    tegra_hdaudio_intr, sc);
 	if (sc->sc_ih == NULL) {
 		aprint_error_dev(self, "couldn't establish interrupt on %s\n",
 		    intrstr);
 		return;
+	}
 	aprint_normal_dev(self, "interrupting on %s\n", intrstr);
 	tegra_pmc_power(PMC_PARTID_DISB, true);
 	tegra_car_periph_hda_enable();
 	if (tegra_hdaudio_init_clocks(sc) != 0)
 		return;
 	tegra_hdaudio_init(sc);
 	hdaudio_attach(self, &sc->sc);
+}
 static int
 tegra_hdaudio_init_clocks(struct tegra_hdaudio_softc *sc)
+{
 	device_t self = sc->sc.sc_dev;
 	struct clk *pll_p_out0;
 	int error;
 	pll_p_out0 = clk_get("pll_p_out0");
 	if (pll_p_out0 == NULL) {
 		aprint_error_dev(self, "couldn't find pll_p_out0\n");
 		return ENOENT;
+	}
 	/* Assert resets */
 	fdtbus_reset_assert(sc->sc_rst_hda);
 	fdtbus_reset_assert(sc->sc_rst_hda2hdmi);
 	fdtbus_reset_assert(sc->sc_rst_hda2codec_2x);
 	/* Set hda to 48MHz and enable it */
 	error = clk_set_parent(sc->sc_clk_hda, pll_p_out0);
 	if (error) {
 		aprint_error_dev(self, "coulnd't set hda parent: %d\n", error);
 		return error;
+	}
 	error = clk_set_rate(sc->sc_clk_hda, 48000000);
 	if (error) {
 		aprint_error_dev(self, "couldn't set hda frequency: %d\n",
 		    error);
 		return error;
+	}
 	error = clk_enable(sc->sc_clk_hda);
 	if (error) {
 		aprint_error_dev(self, "couldn't enable clock hda: %d\n",
 		    error);
 		return error;
+	}
 	/* Enable hda2hdmi clock */
 	error = clk_enable(sc->sc_clk_hda2hdmi);
 	if (error) {
 		aprint_error_dev(self, "couldn't enable clock hda2hdmi: %d\n",
 		    error);
 		return error;
+	}
 	/* Set hda2codec_2x to 48MHz and enable it */
 	error = clk_set_parent(sc->sc_clk_hda2codec_2x, pll_p_out0);
 	if (error) {
 		aprint_error_dev(self, "couldn't set hda2codec_2x parent: %d\n",
 		    error);
 		return error;
+	}
 	error = clk_set_rate(sc->sc_clk_hda2codec_2x, 48000000);
 	if (error) {
 		aprint_error_dev(self,
 		    "couldn't set clock hda2codec_2x frequency: %d\n", error);
 		return error;
+	}
 	error = clk_enable(sc->sc_clk_hda2codec_2x);
 	if (error) {
 		aprint_error_dev(self,
 		    "couldn't enable clock hda2codec_2x: %d\n", error);
 		return error;
+	}
 	/* De-assert resets */
 	fdtbus_reset_deassert(sc->sc_rst_hda);
 	fdtbus_reset_deassert(sc->sc_rst_hda2hdmi);
 	fdtbus_reset_deassert(sc->sc_rst_hda2codec_2x);
 	return 0;
+}
 static void
 tegra_hdaudio_init(struct tegra_hdaudio_softc *sc)
+{
 	tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, TEGRA_HDA_IFPS_CONFIG_REG,
 	    TEGRA_HDA_IFPS_CONFIG_FPCI_EN, 0);
 	tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, TEGRA_HDA_CFG_CMD_REG,
 	    TEGRA_HDA_CFG_CMD_ENABLE_SERR |
 	    TEGRA_HDA_CFG_CMD_BUS_MASTER |
 	    TEGRA_HDA_CFG_CMD_MEM_SPACE |
 	    TEGRA_HDA_CFG_CMD_IO_SPACE,
 	    TEGRA_HDA_CFG_CMD_DISABLE_INTR);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, TEGRA_HDA_CFG_BAR0_REG,
 xffffffff);

--- src/sys/arch/arm/nvidia/tegra_drm_mode.c 2015/12/13 17:39:19	1.10
+++ src/sys/arch/arm/nvidia/tegra_drm_mode.c 2015/12/22 22:10:36	1.11

 @@ -1,14 +1,14 @@
-/* $NetBSD: tegra_drm_mode.c,v 1.10 2015/12/13 17:39:19 jmcneill Exp $ */
+/* $NetBSD: tegra_drm_mode.c,v 1.11 2015/12/22 22:10:36 jmcneill Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -17,38 +17,39 @@
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_drm_mode.c,v 1.10 2015/12/13 17:39:19 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_drm_mode.c,v 1.11 2015/12/22 22:10:36 jmcneill Exp $");
 #include <drm/drmP.h>
 #include <drm/drm_crtc.h>
 #include <drm/drm_crtc_helper.h>
 #include <drm/drm_edid.h>
 #include <dev/i2c/ddcvar.h>
 #include <arm/nvidia/tegra_reg.h>
 #include <arm/nvidia/tegra_var.h>
 #include <arm/nvidia/tegra_intr.h>
 #include <arm/nvidia/tegra_pmcreg.h>
 #include <arm/nvidia/tegra_dcreg.h>
 #include <arm/nvidia/tegra_hdmireg.h>
 #include <arm/nvidia/tegra_drm.h>
 #include <dev/fdt/fdtvar.h>
 static struct drm_framebuffer *tegra_fb_create(struct drm_device *,
 		    struct drm_file *, struct drm_mode_fb_cmd2 *);
 static const struct drm_mode_config_funcs tegra_mode_config_funcs = {
 	.fb_create = tegra_fb_create
 };
 @@ -273,31 +274,39 @@ tegra_framebuffer_destroy(struct drm_fra
+{
 	struct tegra_framebuffer *tegra_fb = to_tegra_framebuffer(fb);
 	drm_framebuffer_cleanup(fb);
 	drm_gem_object_unreference_unlocked(&tegra_fb->obj->base);
 	kmem_free(tegra_fb, sizeof(*tegra_fb));
+}
 static int
 tegra_crtc_init(struct drm_device *ddev, int index)
+{
 	struct tegra_drm_softc * const sc = tegra_drm_private(ddev);
 	struct tegra_crtc *crtc;
 	struct clk *clk_parent;
 	bus_addr_t offset;
 	bus_size_t size;
 	u_int intr;
 	int error;
 	if (sc->sc_clk_dc[index] == NULL ||
 	    sc->sc_clk_dc_parent[index] == NULL ||
 	    sc->sc_rst_dc[index] == NULL) {
 		DRM_ERROR("no clocks configured for crtc %d\n", index);
 		return -EIO;
+	}
 	switch (index) {
 	case 0:
 		offset = TEGRA_GHOST_BASE + TEGRA_DISPLAYA_OFFSET;
 		size = TEGRA_DISPLAYA_SIZE;
 		intr = TEGRA_INTR_DISPLAYA;
 		break;
 	case 1:
 		offset = TEGRA_GHOST_BASE + TEGRA_DISPLAYB_OFFSET;
 		size = TEGRA_DISPLAYB_SIZE;
 		intr = TEGRA_INTR_DISPLAYB;
 		break;
 	default:
 		return -EINVAL;
 @@ -318,27 +327,58 @@ tegra_crtc_init(struct drm_device *ddev,
 	crtc->intr = intr;
 	crtc->ih = intr_establish(intr, IPL_VM, IST_LEVEL | IST_MPSAFE,
 	    tegra_crtc_intr, crtc);
 	if (crtc->ih == NULL) {
 		DRM_ERROR("failed to establish interrupt for crtc %d\n", index);
+	}
 	const size_t cursor_size = 256 * 256 * 4;
 	crtc->cursor_obj = tegra_drm_obj_alloc(ddev, cursor_size);
 	if (crtc->cursor_obj == NULL) {
 		kmem_free(crtc, sizeof(*crtc));
 		return -ENOMEM;
+	}
-	tegra_car_dc_enable(crtc->index);
+	/* Enter reset */
 	fdtbus_reset_assert(sc->sc_rst_dc[index]);
 	/* Turn on power to display partition */
 	const u_int pmc_partid = index == 0 ? PMC_PARTID_DIS : PMC_PARTID_DISB;
 	tegra_pmc_power(pmc_partid, true);
 	tegra_pmc_remove_clamping(pmc_partid);
 	/* Set parent clock */
 	clk_parent = clk_get("pll_d2_out0");
 	if (clk_parent == NULL) {
 		DRM_ERROR("couldn't find pll_d2_out0\n");
 		return -EIO;
+	}
 	error = clk_set_parent(sc->sc_clk_dc[index], clk_parent);
 	if (error) {
 		DRM_ERROR("failed to set crtc %d clock parent: %d\n",
 		    index, error);
 		return -error;
+	}
 	/* Enable DC clock */
 	error = clk_enable(sc->sc_clk_dc[index]);
 	if (error) {
 		DRM_ERROR("failed to enable crtc %d clock: %d\n", index, error);
 		return -error;
+	}
 	/* Leave reset */
 	fdtbus_reset_deassert(sc->sc_rst_dc[index]);
 	crtc->clk_parent = clk_parent;
 	DC_WRITE(crtc, DC_CMD_INT_ENABLE_REG, DC_CMD_INT_V_BLANK);
 	drm_crtc_init(ddev, &crtc->base, &tegra_crtc_funcs);
 	drm_crtc_helper_add(&crtc->base, &tegra_crtc_helper_funcs);
 	return 0;
+}
 static int
 tegra_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
     uint32_t handle, uint32_t width, uint32_t height)
+{
 @@ -596,28 +636,28 @@ tegra_crtc_mode_set(struct drm_crtc *crt
 	    DC_DISP_DISP_SIGNAL_OPTIONS0_H_PULSE2_ENABLE);
 	DC_WRITE(tegra_crtc, DC_DISP_H_PULSE2_CONTROL_REG,
 	    __SHIFTIN(DC_DISP_H_PULSE2_CONTROL_V_QUAL_VACTIVE,
 		      DC_DISP_H_PULSE2_CONTROL_V_QUAL) |
 	    __SHIFTIN(DC_DISP_H_PULSE2_CONTROL_LAST_END_A,
 		      DC_DISP_H_PULSE2_CONTROL_LAST));
 	const u_int pulse_start = 1 + hspw + hbp - 10;
 	DC_WRITE(tegra_crtc, DC_DISP_H_PULSE2_POSITION_A_REG,
 	    __SHIFTIN(pulse_start, DC_DISP_H_PULSE2_POSITION_A_START) |
 	    __SHIFTIN(pulse_start + 8, DC_DISP_H_PULSE2_POSITION_A_END));
 	/* Pixel clock */
-	const u_int div = (tegra_car_plld2_rate() * 2) /
+	const u_int parent_rate = clk_get_rate(tegra_crtc->clk_parent);
-	    (mode->crtc_clock * 1000) - 2;
+	const u_int div = (parent_rate * 2) / (mode->crtc_clock * 1000) - 2;
 	DC_WRITE(tegra_crtc, DC_DISP_DISP_CLOCK_CONTROL_REG,
 	    __SHIFTIN(0, DC_DISP_DISP_CLOCK_CONTROL_PIXEL_CLK_DIVIDER) |
 	    __SHIFTIN(div, DC_DISP_DISP_CLOCK_CONTROL_SHIFT_CLK_DIVIDER));
 	/* Mode timings */
 	DC_WRITE(tegra_crtc, DC_DISP_REF_TO_SYNC_REG,
 	    __SHIFTIN(1, DC_DISP_REF_TO_SYNC_V) |
 	    __SHIFTIN(1, DC_DISP_REF_TO_SYNC_H));
 	DC_WRITE(tegra_crtc, DC_DISP_SYNC_WIDTH_REG,
 	    __SHIFTIN(vspw, DC_DISP_SYNC_WIDTH_V) |
 	    __SHIFTIN(hspw, DC_DISP_SYNC_WIDTH_H));
 	DC_WRITE(tegra_crtc, DC_DISP_BACK_PORCH_REG,
 	    __SHIFTIN(vbp, DC_DISP_BACK_PORCH_V) |
 @@ -738,43 +778,64 @@ tegra_crtc_commit(struct drm_crtc *crtc)
 	    DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ |
 	    DC_CMD_STATE_CONTROL_WIN_A_ACT_REQ);
 	tegra_crtc->enabled = true;
+}
 static int
 tegra_encoder_init(struct drm_device *ddev)
+{
 	struct tegra_drm_softc * const sc = tegra_drm_private(ddev);
 	struct tegra_encoder *encoder;
 	int error;
 	if (sc->sc_clk_hdmi == NULL ||
 	    sc->sc_clk_hdmi_parent == NULL ||
 	    sc->sc_rst_hdmi == NULL) {
 		DRM_ERROR("no clocks configured for hdmi\n");
 		DRM_ERROR("clk: hdmi %p parent %p\n", sc->sc_clk_hdmi, sc->sc_clk_hdmi_parent);
 		DRM_ERROR("rst: hdmi %p\n", sc->sc_rst_hdmi);
 		return -EIO;
+	}
 	encoder = kmem_zalloc(sizeof(*encoder), KM_SLEEP);
 	if (encoder == NULL)
 		return -ENOMEM;
 	const bus_addr_t offset = TEGRA_GHOST_BASE + TEGRA_HDMI_OFFSET;
 	const bus_size_t size = TEGRA_HDMI_SIZE;
 	encoder->bst = sc->sc_bst;
 	error = bus_space_map(encoder->bst, offset, size, 0, &encoder->bsh);
 	if (error) {
 		kmem_free(encoder, sizeof(*encoder));
 		return -error;
+	}
 	encoder->size = size;
 	tegra_pmc_hdmi_enable();
 	/* Enable parent PLL */
 	error = clk_set_rate(sc->sc_clk_hdmi_parent, 594000000);
 	if (error) {
 		DRM_ERROR("couldn't set hdmi parent PLL rate: %d\n", error);
 		return -error;
+	}
 	error = clk_enable(sc->sc_clk_hdmi_parent);
 	if (error) {
 		DRM_ERROR("couldn't enable hdmi parent PLL: %d\n", error);
 		return -error;
+	}
 	drm_encoder_init(ddev, &encoder->base, &tegra_encoder_funcs,
 	    DRM_MODE_ENCODER_TMDS);
 	drm_encoder_helper_add(&encoder->base, &tegra_encoder_helper_funcs);
 	encoder->base.possible_crtcs = (1 << 0) | (1 << 1);
 	return tegra_connector_init(ddev, &encoder->base);
+}
 static void
 tegra_encoder_destroy(struct drm_encoder *encoder)
+{
 	struct tegra_encoder *tegra_encoder = to_tegra_encoder(encoder);
 @@ -801,41 +862,76 @@ tegra_encoder_dpms(struct drm_encoder *e
 		HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_BLANK_REG,
 		    HDMI_NV_PDISP_SOR_BLANK_OVERRIDE, 0);
 		break;
+	}
+}
 static bool
 tegra_encoder_mode_fixup(struct drm_encoder *encoder,
     const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode)
+{
 	return true;
+}
 static int
 tegra_encoder_hdmi_set_clock(struct drm_encoder *encoder, u_int rate)
+{
 	struct drm_device *ddev = encoder->dev;
 	struct tegra_drm_softc * const sc = tegra_drm_private(ddev);
 	int error;
 	/* Enter reset */
 	fdtbus_reset_assert(sc->sc_rst_hdmi);
 	/* Set HDMI parent clock */
 	error = clk_set_parent(sc->sc_clk_hdmi, sc->sc_clk_hdmi_parent);
 	if (error) {
 		DRM_ERROR("couldn't set hdmi parent: %d\n", error);
 		return -error;
+	}
 	/* Set dot clock frequency */
 	error = clk_set_rate(sc->sc_clk_hdmi, rate);
 	if (error) {
 		DRM_ERROR("couldn't set hdmi clock: %d\n", error);
 		return -error;
+	}
 	error = clk_enable(sc->sc_clk_hdmi);
 	if (error) {
 		DRM_ERROR("couldn't enable hdmi clock: %d\n", error);
 		return -error;
+	}
 	/* Leave reset */
 	fdtbus_reset_deassert(sc->sc_rst_hdmi);
 	return 0;
+}
 static void
 tegra_encoder_mode_set(struct drm_encoder *encoder,
     struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode)
+{
 	struct drm_device *ddev = encoder->dev;
 	struct tegra_encoder *tegra_encoder = to_tegra_encoder(encoder);
 	struct tegra_crtc *tegra_crtc = to_tegra_crtc(encoder->crtc);
 	struct tegra_connector *tegra_connector = NULL;
 	struct drm_connector *connector;
 	const struct tegra_hdmi_tmds_config *tmds = NULL;
 	uint32_t input_ctrl;
 	int retry;
 	u_int i;
-	tegra_car_hdmi_enable(mode->crtc_clock * 1000);
+	tegra_encoder_hdmi_set_clock(encoder, mode->crtc_clock * 1000);
 	/* find the connector for this encoder */
 	list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
 		if (connector->encoder == encoder) {
 			tegra_connector = to_tegra_connector(connector);
 			break;
+		}
+	}
 	for (i = 0; i < __arraycount(tegra_hdmi_tmds_config); i++) {
 		if (tegra_hdmi_tmds_config[i].dot_clock >= mode->crtc_clock) {
 			break;
+		}

--- src/sys/arch/arm/nvidia/tegra_i2c.c 2015/12/16 19:46:55	1.10
+++ src/sys/arch/arm/nvidia/tegra_i2c.c 2015/12/22 22:10:36	1.11

 @@ -1,14 +1,14 @@
-/* $NetBSD: tegra_i2c.c,v 1.10 2015/12/16 19:46:55 jmcneill Exp $ */
+/* $NetBSD: tegra_i2c.c,v 1.11 2015/12/22 22:10:36 jmcneill Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -17,80 +17,60 @@
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_i2c.c,v 1.10 2015/12/16 19:46:55 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_i2c.c,v 1.11 2015/12/22 22:10:36 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <dev/i2c/i2cvar.h>
 #include <arm/nvidia/tegra_reg.h>
 #include <arm/nvidia/tegra_i2creg.h>
 #include <arm/nvidia/tegra_var.h>
 #include <dev/fdt/fdtvar.h>
 /* XXX */
 static int
 tegra_i2c_addr2port(bus_addr_t addr)
 	switch (addr) {
 	case TEGRA_APB_BASE + TEGRA_I2C1_OFFSET:
 		return 0;
 	case TEGRA_APB_BASE + TEGRA_I2C2_OFFSET:
 		return 1;
 	case TEGRA_APB_BASE + TEGRA_I2C3_OFFSET:
 		return 2;
 	case TEGRA_APB_BASE + TEGRA_I2C4_OFFSET:
 		return 3;
 	case TEGRA_APB_BASE + TEGRA_I2C5_OFFSET:
 		return 4;
 	case TEGRA_APB_BASE + TEGRA_I2C6_OFFSET:
 		return 5;
 	default:
 		return -1;
 static int	tegra_i2c_match(device_t, cfdata_t, void *);
 static void	tegra_i2c_attach(device_t, device_t, void *);
 static i2c_tag_t tegra_i2c_get_tag(device_t);
 struct fdtbus_i2c_controller_func tegra_i2c_funcs = {
 	.get_tag = tegra_i2c_get_tag
 };
 struct tegra_i2c_softc {
 	device_t		sc_dev;
 	bus_space_tag_t		sc_bst;
 	bus_space_handle_t	sc_bsh;
 	void *			sc_ih;
-	u_int			sc_port;
+	struct clk *		sc_clk;
 	struct fdtbus_reset *	sc_rst;
 	u_int			sc_cid;
 	struct i2c_controller	sc_ic;
 	kmutex_t		sc_lock;
 	kcondvar_t		sc_cv;
 	device_t		sc_i2cdev;
 };
 static void	tegra_i2c_init(struct tegra_i2c_softc *);
 static int	tegra_i2c_intr(void *);
 static int	tegra_i2c_acquire_bus(void *, int);
 static void	tegra_i2c_release_bus(void *, int);
 static int	tegra_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *,
 @@ -129,60 +109,81 @@ tegra_i2c_attach(device_t parent, device
 	const int phandle = faa->faa_phandle;
 	struct i2cbus_attach_args iba;
 	prop_dictionary_t devs;
 	char intrstr[128];
 	bus_addr_t addr;
 	bus_size_t size;
 	u_int address_cells;
 	int error;
 	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
 		aprint_error(": couldn't get registers\n");
 		return;
+	}
 	sc->sc_clk = fdtbus_clock_get(phandle, "div-clk");
 	if (sc->sc_clk == NULL) {
 		aprint_error(": couldn't get clock div-clk\n");
 		return;
+	}
 	sc->sc_rst = fdtbus_reset_get(phandle, "i2c");
 	if (sc->sc_rst == NULL) {
 		aprint_error(": couldn't get reset i2c\n");
 		return;
+	}
 	sc->sc_dev = self;
 	sc->sc_bst = faa->faa_bst;
 	sc->sc_cid = device_unit(self);
 	error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
 	if (error) {
 		aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error);
 		return;
+	}
 	sc->sc_port = tegra_i2c_addr2port(addr);
 	mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM);
 	cv_init(&sc->sc_cv, device_xname(self));
 	aprint_naive("\n");
-	aprint_normal(": I2C%d\n", sc->sc_port + 1);
+	aprint_normal(": I2C\n");
 	if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
 		aprint_error_dev(self, "failed to decode interrupt\n");
 		return;
+	}
 	sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_VM,
 	    FDT_INTR_MPSAFE, tegra_i2c_intr, sc);
 	if (sc->sc_ih == NULL) {
 		aprint_error_dev(self, "couldn't establish interrupt on %s\n",
 		    intrstr);
 		return;
+	}
 	aprint_normal_dev(self, "interrupting on %s\n", intrstr);
 	/*
 	 * Recommended setting for standard mode is to use an I2C source div
 	 * of 20 (Tegra K1 Technical Reference Manual, Table 137)
 	 */
-	tegra_car_periph_i2c_enable(sc->sc_port, 20400000);
+	fdtbus_reset_assert(sc->sc_rst);
 	error = clk_set_rate(sc->sc_clk, 20400000);
 	if (error) {
 		aprint_error_dev(self, "couldn't set frequency: %d\n", error);
 		return;
+	}
 	error = clk_enable(sc->sc_clk);
 	if (error) {
 		aprint_error_dev(self, "couldn't enable clock: %d\n", error);
 		return;
+	}
 	fdtbus_reset_deassert(sc->sc_rst);
 	tegra_i2c_init(sc);
 	sc->sc_ic.ic_cookie = sc;
 	sc->sc_ic.ic_acquire_bus = tegra_i2c_acquire_bus;
 	sc->sc_ic.ic_release_bus = tegra_i2c_release_bus;
 	sc->sc_ic.ic_exec = tegra_i2c_exec;
 	fdtbus_register_i2c_controller(self, phandle, &tegra_i2c_funcs);
 	devs = prop_dictionary_create();
 	if (of_getprop_uint32(phandle, "#address-cells", &address_cells))
 @@ -385,27 +386,27 @@ tegra_i2c_write(struct tegra_i2c_softc *
+{
 	const uint8_t *p = buf;
 	size_t n, resid = buflen;
 	uint32_t data;
 	int retry;
 	const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG);
 	I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus);
 	/* Generic Header 0 */
 	I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG,
 	    __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ,
 		      I2C_IOPACKET_WORD0_PROTHDRSZ) |
-	    __SHIFTIN(sc->sc_port, I2C_IOPACKET_WORD0_CONTROLLERID) |
+	    __SHIFTIN(sc->sc_cid, I2C_IOPACKET_WORD0_CONTROLLERID) |
 	    __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) |
 	    __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C,
 		      I2C_IOPACKET_WORD0_PROTOCOL) |
 	    __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ,
 		      I2C_IOPACKET_WORD0_PKTTYPE));
 	/* Generic Header 1 */
 	I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG,
 	    __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE));
 	/* I2C Master Transmit Packet Header */
 	I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG,
 	    I2C_IOPACKET_XMITHDR_IE |
 	    (repeat_start ? I2C_IOPACKET_XMITHDR_REPEAT_STARTSTOP : 0) |
 	    __SHIFTIN((addr << 1), I2C_IOPACKET_XMITHDR_SLAVE_ADDR));
 @@ -443,27 +444,27 @@ tegra_i2c_read(struct tegra_i2c_softc *s
+{
 	uint8_t *p = buf;
 	size_t n, resid = buflen;
 	uint32_t data;
 	int retry;
 	const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG);
 	I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus);
 	/* Generic Header 0 */
 	I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG,
 	    __SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ,
 		      I2C_IOPACKET_WORD0_PROTHDRSZ) |
-	    __SHIFTIN(sc->sc_port, I2C_IOPACKET_WORD0_CONTROLLERID) |
+	    __SHIFTIN(sc->sc_cid, I2C_IOPACKET_WORD0_CONTROLLERID) |
 	    __SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) |
 	    __SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C,
 		      I2C_IOPACKET_WORD0_PROTOCOL) |
 	    __SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ,
 		      I2C_IOPACKET_WORD0_PKTTYPE));
 	/* Generic Header 1 */
 	I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG,
 	    __SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE));
 	/* I2C Master Transmit Packet Header */
 	I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG,
 	    I2C_IOPACKET_XMITHDR_IE | I2C_IOPACKET_XMITHDR_READ |
 	    __SHIFTIN((addr << 1) | 1, I2C_IOPACKET_XMITHDR_SLAVE_ADDR));

--- src/sys/arch/arm/nvidia/Attic/tegra_fdt.c 2015/12/13 17:39:19	1.1
+++ src/sys/arch/arm/nvidia/Attic/tegra_fdt.c 2015/12/22 22:10:36	1.2

 @@ -1,14 +1,14 @@
-/* $NetBSD: tegra_fdt.c,v 1.1 2015/12/13 17:39:19 jmcneill Exp $ */
+/* $NetBSD: tegra_fdt.c,v 1.2 2015/12/22 22:10:36 jmcneill Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -19,27 +19,27 @@
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include "opt_tegra.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_fdt.c,v 1.1 2015/12/13 17:39:19 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_fdt.c,v 1.2 2015/12/22 22:10:36 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <machine/cpu.h>
 #include <sys/bus.h>
 #include <arm/mainbus/mainbus.h>
 #include <arm/nvidia/tegra_reg.h>
 #include <arm/nvidia/tegra_var.h>
 #include <dev/fdt/fdtvar.h>
 @@ -60,36 +60,39 @@ tegrafdt_match(device_t parent, cfdata_t
 		return 0;
 	return 1;
+}
 void
 tegrafdt_attach(device_t parent, device_t self, void *aux)
+{
 	const char *tegrafdt_init[] = {
 		"interrupt-controller",
 		"clock",
 		"pinmux",
 		"gpio",
 		"regulators",
 		"fuse",
 		"dma",
 		"pmc",
 		"memory-controller",
 		"i2c",
 		"usb-phy"
 	};
 	tegrafdt_found = true;
 	aprint_naive("\n");
 	aprint_normal("\n");
 	struct fdt_attach_args faa = {
 		.faa_name = "",
 		.faa_bst = &armv7_generic_bs_tag,
 		.faa_a4x_bst = &armv7_generic_a4x_bs_tag,
 		.faa_dmat = &tegra_dma_tag,
 		.faa_phandle = OF_peer(0),
 		.faa_init = tegrafdt_init,
 		.faa_ninit = __arraycount(tegrafdt_init)
 	};
 	config_found(self, &faa, NULL);
 	tegra_cpuinit();
+}

--- src/sys/arch/arm/nvidia/tegra_timerreg.h 2015/05/30 13:25:55	1.1
+++ src/sys/arch/arm/nvidia/tegra_timerreg.h 2015/12/22 22:10:36	1.2

 @@ -1,14 +1,14 @@
-/* $NetBSD: tegra_timerreg.h,v 1.1 2015/05/30 13:25:55 jmcneill Exp $ */
+/* $NetBSD: tegra_timerreg.h,v 1.2 2015/12/22 22:10:36 jmcneill Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -23,26 +23,29 @@
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #ifndef _ARM_TEGRA_TIMERREG_H
 #define _ARM_TEGRA_TIMERREG_H
 #define TMR1_PTV_REG		0x00
 #define TMR1_PCR_REG		0x04
 #define TMR2_PTV_REG		0x08
 #define TMR2_PCR_REG		0x0c
 #define TMRUS_CNTR_1US_REG	0x10
 #define TMRUS_USEC_CFG_REG	0x14
 #define TMRUS_CNTR_FREEZE_REG	0x18
 #define TMR3_PTV_REG		0x50
 #define TMR3_PCR_REG		0x54
 #define TMR4_PTV_REG		0x58
 #define TMR4_PCR_REG		0x5c
 #define TMR5_PTV_REG		0x60
 #define TMR5_PCR_REG		0x64
 #define TMR6_PTV_REG		0x68
 #define TMR6_PCR_REG		0x6c
 #define TMR7_PTV_REG		0x70
 #define TMR7_PCR_REG		0x74
 #define TMR8_PTV_REG		0x78
 #define TMR8_PCR_REG		0x7c
 #define TMR9_PTV_REG		0x80

--- src/sys/arch/arm/nvidia/tegra_fuse.c 2015/12/13 17:39:19	1.3
+++ src/sys/arch/arm/nvidia/tegra_fuse.c 2015/12/22 22:10:36	1.4

 @@ -1,14 +1,14 @@
-/* $NetBSD: tegra_fuse.c,v 1.3 2015/12/13 17:39:19 jmcneill Exp $ */
+/* $NetBSD: tegra_fuse.c,v 1.4 2015/12/22 22:10:36 jmcneill Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -16,50 +16,51 @@
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include "locators.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_fuse.c,v 1.3 2015/12/13 17:39:19 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_fuse.c,v 1.4 2015/12/22 22:10:36 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <arm/nvidia/tegra_reg.h>
 #include <arm/nvidia/tegra_var.h>
 #include <dev/fdt/fdtvar.h>
 static int	tegra_fuse_match(device_t, cfdata_t, void *);
 static void	tegra_fuse_attach(device_t, device_t, void *);
 struct tegra_fuse_softc {
 	device_t		sc_dev;
 	bus_space_tag_t		sc_bst;
 	bus_space_handle_t	sc_bsh;
 	struct clk		*sc_clk;
 	struct fdtbus_reset	*sc_rst;
 };
 static struct tegra_fuse_softc *fuse_softc = NULL;
 CFATTACH_DECL_NEW(tegra_fuse, sizeof(struct tegra_fuse_softc),
 	tegra_fuse_match, tegra_fuse_attach, NULL, NULL);
 static int
 tegra_fuse_match(device_t parent, cfdata_t cf, void *aux)
+{
 	const char * const compatible[] = { "nvidia,tegra124-efuse", NULL };
 	struct fdt_attach_args * const faa = aux;
 @@ -69,50 +70,56 @@ tegra_fuse_match(device_t parent, cfdata
 static void
 tegra_fuse_attach(device_t parent, device_t self, void *aux)
+{
 	struct tegra_fuse_softc * const sc = device_private(self);
 	struct fdt_attach_args * const faa = aux;
 	bus_addr_t addr;
 	bus_size_t size;
 	int error;
 	if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) {
 		aprint_error(": couldn't get registers\n");
 		return;
+	}
 	sc->sc_clk = fdtbus_clock_get(faa->faa_phandle, "fuse");
 	if (sc->sc_clk == NULL) {
 		aprint_error(": couldn't get clock fuse\n");
 		return;
+	}
 	sc->sc_rst = fdtbus_reset_get(faa->faa_phandle, "fuse");
 	if (sc->sc_rst == NULL) {
 		aprint_error(": couldn't get reset fuse\n");
 		return;
+	}
 	sc->sc_dev = self;
 	sc->sc_bst = faa->faa_bst;
 	error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
 	if (error) {
 		aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error);
 		return;
+	}
 	KASSERT(fuse_softc == NULL);
 	fuse_softc = sc;
 	aprint_naive("\n");
 	aprint_normal(": FUSE\n");
+}
 uint32_t
 tegra_fuse_read(u_int offset)
+{
 	bus_space_tag_t bst;
 	bus_space_handle_t bsh;
-	if (fuse_softc) {
+	KASSERT(fuse_softc != NULL);
 		bst = fuse_softc->sc_bst;
-		bsh = fuse_softc->sc_bsh;
+	bst = fuse_softc->sc_bst;
-	} else {
+	bsh = fuse_softc->sc_bsh;
 		bst = &armv7_generic_bs_tag;
 		bus_space_subregion(bst, tegra_apb_bsh,
 		    TEGRA_FUSE_OFFSET, TEGRA_FUSE_SIZE, &bsh);
-	tegra_car_fuse_enable();
+	clk_enable(fuse_softc->sc_clk);
 	const uint32_t v = bus_space_read_4(bst, bsh, 0x100 + offset);
-	tegra_car_fuse_disable();
+	clk_disable(fuse_softc->sc_clk);
 	return v;
+}

--- src/sys/arch/arm/nvidia/tegra_sdhc.c 2015/12/16 19:46:55	1.14
+++ src/sys/arch/arm/nvidia/tegra_sdhc.c 2015/12/22 22:10:36	1.15

 @@ -1,14 +1,14 @@
-/* $NetBSD: tegra_sdhc.c,v 1.14 2015/12/16 19:46:55 jmcneill Exp $ */
+/* $NetBSD: tegra_sdhc.c,v 1.15 2015/12/22 22:10:36 jmcneill Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -19,72 +19,55 @@
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include "locators.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_sdhc.c,v 1.14 2015/12/16 19:46:55 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_sdhc.c,v 1.15 2015/12/22 22:10:36 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <dev/sdmmc/sdhcreg.h>
 #include <dev/sdmmc/sdhcvar.h>
 #include <dev/sdmmc/sdmmcvar.h>
 #include <arm/nvidia/tegra_reg.h>
 #include <arm/nvidia/tegra_var.h>
 #include <dev/fdt/fdtvar.h>
 /* XXX */
 static int
 tegra_sdhc_addr2port(bus_addr_t addr)
 	switch (addr) {
 	case TEGRA_APB_BASE + TEGRA_SDMMC1_OFFSET:
 		return 0;
 	case TEGRA_APB_BASE + TEGRA_SDMMC2_OFFSET:
 		return 1;
 	case TEGRA_APB_BASE + TEGRA_SDMMC3_OFFSET:
 		return 2;
 	case TEGRA_APB_BASE + TEGRA_SDMMC4_OFFSET:
 		return 3;
 	default:
 		return -1;
 static int	tegra_sdhc_match(device_t, cfdata_t, void *);
 static void	tegra_sdhc_attach(device_t, device_t, void *);
 static int	tegra_sdhc_card_detect(struct sdhc_softc *);
 static int	tegra_sdhc_write_protect(struct sdhc_softc *);
 struct tegra_sdhc_softc {
 	struct sdhc_softc	sc;
-	u_int			sc_port;
+	struct clk		*sc_clk;
 	struct fdtbus_reset	*sc_rst;
 	bus_space_tag_t		sc_bst;
 	bus_space_handle_t	sc_bsh;
 	bus_size_t		sc_bsz;
 	struct sdhc_host	*sc_host;
 	void			*sc_ih;
 	struct fdtbus_gpio_pin	*sc_pin_cd;
 	struct fdtbus_gpio_pin	*sc_pin_power;
 	struct fdtbus_gpio_pin	*sc_pin_wp;
 };
 CFATTACH_DECL_NEW(tegra_sdhc, sizeof(struct tegra_sdhc_softc),
 @@ -129,51 +112,73 @@ tegra_sdhc_attach(device_t parent, devic
 			  SDHC_FLAG_USE_ADMA2;
 	if (bus_width == 8) {
 		sc->sc.sc_flags |= SDHC_FLAG_8BIT_MODE;
+	}
 	sc->sc.sc_host = &sc->sc_host;
 	sc->sc_bst = faa->faa_bst;
 	error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
 	if (error) {
 		aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error);
 		return;
+	}
 	sc->sc_bsz = size;
 	sc->sc_port = tegra_sdhc_addr2port(addr);
 	sc->sc_pin_power = fdtbus_gpio_acquire(faa->faa_phandle,
 	    "power-gpios", GPIO_PIN_OUTPUT);
 	if (sc->sc_pin_power)
 		fdtbus_gpio_write(sc->sc_pin_power, 1);
 	sc->sc_pin_cd = fdtbus_gpio_acquire(faa->faa_phandle,
 	    "cd-gpios", GPIO_PIN_INPUT);
 	sc->sc_pin_wp = fdtbus_gpio_acquire(faa->faa_phandle,
 	    "wp-gpios", GPIO_PIN_INPUT);
 	if (sc->sc_pin_cd) {
 		sc->sc.sc_vendor_card_detect = tegra_sdhc_card_detect;
 		sc->sc.sc_flags |= SDHC_FLAG_POLL_CARD_DET;
+	}
 	if (sc->sc_pin_wp) {
 		sc->sc.sc_vendor_write_protect = tegra_sdhc_write_protect;
+	}
-	tegra_car_periph_sdmmc_set_rate(sc->sc_port, 204000000);
+	sc->sc_clk = fdtbus_clock_get_index(faa->faa_phandle, 0);
-	sc->sc.sc_clkbase = tegra_car_periph_sdmmc_rate(sc->sc_port) / 1000;
+	if (sc->sc_clk == NULL) {
 		aprint_error(": couldn't get clock\n");
 		return;
+	}
 	sc->sc_rst = fdtbus_reset_get(faa->faa_phandle, "sdhci");
 	if (sc->sc_rst == NULL) {
 		aprint_error(": couldn't get reset\n");
 		return;
+	}
 	fdtbus_reset_assert(sc->sc_rst);
 	error = clk_set_rate(sc->sc_clk, 204000000);
 	if (error) {
 		aprint_error(": couldn't set frequency: %d\n", error);
 		return;
+	}
 	error = clk_enable(sc->sc_clk);
 	if (error) {
 		aprint_error(": couldn't enable clock: %d\n", error);
 		return;
+	}
 	fdtbus_reset_deassert(sc->sc_rst);
 	sc->sc.sc_clkbase = clk_get_rate(sc->sc_clk) / 1000;
 	aprint_naive("\n");
-	aprint_normal(": SDMMC%d\n", sc->sc_port + 1);
+	aprint_normal(": SDMMC\n");
 	if (sc->sc.sc_clkbase == 0) {
 		aprint_error_dev(self, "couldn't determine frequency\n");
 		return;
+	}
 	if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) {
 		aprint_error_dev(self, "failed to decode interrupt\n");
 		return;
+	}
 	sc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_SDMMC, 0,
 	    sdhc_intr, &sc->sc);

--- src/sys/arch/arm/nvidia/tegra_soc.c 2015/11/19 22:09:16	1.7
+++ src/sys/arch/arm/nvidia/tegra_soc.c 2015/12/22 22:10:36	1.8

 @@ -1,14 +1,14 @@
-/* $NetBSD: tegra_soc.c,v 1.7 2015/11/19 22:09:16 jmcneill Exp $ */
+/* $NetBSD: tegra_soc.c,v 1.8 2015/12/22 22:10:36 jmcneill Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -20,27 +20,27 @@
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include "opt_tegra.h"
 #include "opt_multiprocessor.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_soc.c,v 1.7 2015/11/19 22:09:16 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_soc.c,v 1.8 2015/12/22 22:10:36 jmcneill Exp $");
 #define	_ARM32_BUS_DMA_PRIVATE
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/cpu.h>
 #include <sys/device.h>
 #include <uvm/uvm_extern.h>
 #include <arm/bootconfig.h>
 #include <arm/cpufunc.h>
 #include <arm/nvidia/tegra_reg.h>
 @@ -61,28 +61,26 @@ static void	tegra_mpinit(void);
 void
 tegra_bootstrap(void)
+{
 	if (bus_space_map(&armv7_generic_bs_tag,
 	    TEGRA_PPSB_BASE, TEGRA_PPSB_SIZE, 0,
 	    &tegra_ppsb_bsh) != 0)
 		panic("couldn't map PPSB");
 	if (bus_space_map(&armv7_generic_bs_tag,
 	    TEGRA_APB_BASE, TEGRA_APB_SIZE, 0,
 	    &tegra_apb_bsh) != 0)
 		panic("couldn't map APB");
 	curcpu()->ci_data.cpu_cc_freq = tegra_car_pllx_rate();
 	tegra_mpinit();
+}
 void
 tegra_dma_bootstrap(psize_t psize)
+{
+}
 void
 tegra_cpuinit(void)
+{
 	switch (tegra_chip_id()) {
 #ifdef SOC_TEGRA124

--- src/sys/arch/evbarm/conf/Attic/TEGRA 2015/12/16 12:26:14	1.5
+++ src/sys/arch/evbarm/conf/Attic/TEGRA 2015/12/22 22:10:36	1.6

 @@ -1,15 +1,15 @@
+#
-#	$NetBSD: TEGRA,v 1.5 2015/12/16 12:26:14 jmcneill Exp $
+#	$NetBSD: TEGRA,v 1.6 2015/12/22 22:10:36 jmcneill Exp $
+#
 #	NVIDIA Tegra K1 (T124)
+#
 include	"arch/evbarm/conf/std.tegra"
 include	"arch/evbarm/conf/GENERIC.common"
 options 	CPU_CORTEXA15
 options 	SOC_TEGRA124
 options 	MULTIPROCESSOR
 pseudo-device 	openfirm	# /dev/openfirm
 @@ -45,27 +45,27 @@ gpiokeys*	at fdt?
 tegralic*	at fdt?			# LIC
 gic*		at fdt?			# GIC
 # Memory controller
 tegramc*	at fdt?			# MC
 # FUSE controller
 tegrafuse*	at fdt?			# FUSE
 # Power management controller
 tegrapmc*	at fdt?			# PMC
 # Clock and Reset controller
-tegracar0	at fdt?			# CAR
+tegra124car*	at fdt?			# CAR
 # GPIO controller
 tegragpio*	at fdt?			# GPIO
 gpio*		at gpiobus?
 # Timers
 tegratimer*	at fdt?			# Timers
 # MPIO / Pinmux
 tegrampio*	at fdt?			# MPIO
 # XUSB PADCTL
 tegraxusbpad*	at fdt?			# XUSB PADCTL

--- src/sys/arch/evbarm/conf/Attic/std.tegra 2015/12/16 12:26:14	1.11
+++ src/sys/arch/evbarm/conf/Attic/std.tegra 2015/12/22 22:10:36	1.12

 @@ -1,26 +1,25 @@
-#	$NetBSD: std.tegra,v 1.11 2015/12/16 12:26:14 jmcneill Exp $
+#	$NetBSD: std.tegra,v 1.12 2015/12/22 22:10:36 jmcneill Exp $
+#
 machine	evbarm arm
 include 	"arch/evbarm/conf/std.evbarm"
 include		"arch/evbarm/conf/files.tegra"
 options 	FDT				# Flattened Device Tree support
 options 	MODULAR
 options 	MODULAR_DEFAULT_AUTOLOAD
 options 	__HAVE_CPU_COUNTER
 options 	CORTEX_PMC
 options 	__HAVE_FAST_SOFTINTS		# should be in types.h
 options 	ARM_HAS_VBAR
 #options 	__HAVE_MM_MD_DIRECT_MAPPED_PHYS
 #options 	PMAP_NEED_ALLOC_POOLPAGE
 options 	TPIDRPRW_IS_CURCPU
 options 	KERNEL_BASE_EXT=0x80000000
 options 	FPU_VFP
 options 	PCI_NETBSD_CONFIGURE
 options 	__HAVE_PCI_CONF_HOOK
 options 	__BUS_SPACE_HAS_STREAM_METHODS
 makeoptions	KERNEL_BASE_PHYS="0x81000000"
 makeoptions	KERNEL_BASE_VIRT="0x81000000"

--- src/sys/arch/evbarm/tegra/Attic/tegra_machdep.c 2015/12/16 12:18:02	1.36
+++ src/sys/arch/evbarm/tegra/Attic/tegra_machdep.c 2015/12/22 22:10:36	1.37

 @@ -1,14 +1,14 @@
-/* $NetBSD: tegra_machdep.c,v 1.36 2015/12/16 12:18:02 jmcneill Exp $ */
+/* $NetBSD: tegra_machdep.c,v 1.37 2015/12/22 22:10:36 jmcneill Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -17,27 +17,27 @@
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_machdep.c,v 1.36 2015/12/16 12:18:02 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_machdep.c,v 1.37 2015/12/22 22:10:36 jmcneill Exp $");
 #include "opt_tegra.h"
 #include "opt_machdep.h"
 #include "opt_ddb.h"
 #include "opt_md.h"
 #include "opt_arm_debug.h"
 #include "opt_multiprocessor.h"
 #include "com.h"
 #include "ukbd.h"
 #include "genfb.h"
 #include "ether.h"
 #include "as3722pmic.h"
 @@ -371,27 +371,27 @@ initarm(void *arg)
 #endif
 void
 consinit(void)
+{
 	static bool consinit_called = false;
 	if (consinit_called)
 		return;
 	consinit_called = true;
 #if NCOM > 0
 	const bus_space_tag_t bst = &armv7_generic_a4x_bs_tag;
-	const u_int freq = tegra_car_uart_rate(3);
+	const u_int freq = 408000000;	/* 408MHz PLLP_OUT0 */
 	if (comcnattach(bst, CONSADDR, CONSPEED, freq,
 			COM_TYPE_TEGRA, CONMODE)) {
 		panic("Serial console cannot be initialized.");
+	}
 #else
 #error only COM console is supported
 #endif
+}
 static bool
 tegra_bootconf_match(const char *key, const char *val)
+{
 	char *s;
 @@ -432,30 +432,26 @@ tegra_device_register(device_t self, voi
 	if (device_is_a(self, "armperiph")
 	    && device_is_a(device_parent(self), "mainbus")) {
 		struct mainbus_attach_args * const mb = aux;
 		mb->mb_iot = &armv7_generic_bs_tag;
 		return;
+	}
 	if (device_is_a(self, "armgtmr")) {
                 prop_dictionary_set_uint32(dict, "frequency", TEGRA_REF_FREQ);
 		return;
+	}
 	if (device_is_a(self, "cpu") && device_unit(self) == 0) {
 		tegra_cpuinit();
 	if (device_is_a(self, "tegrafb")
 	    && tegra_bootconf_match("console", "fb")) {
 		prop_dictionary_set_bool(dict, "is_console", true);
 #if NUKBD > 0
 		ukbd_cnattach();
 #endif
+	}
 	if (device_is_a(self, "tegradrm")) {
 		const char *video = tegra_bootconf_strdup("video");
 		if (tegra_bootconf_match("hdmi.forcemode", "dvi")) {
 			prop_dictionary_set_bool(dict, "force-dvi", true);