 @@ -1,14 +1,14 @@
-/*	$NetBSD: exynos_gpio.c,v 1.21 2015/12/27 12:42:14 jmcneill Exp $ */
+/*	$NetBSD: exynos_gpio.c,v 1.22 2015/12/30 04:30:27 marty Exp $ */
 /*-
 * Copyright (c) 2014 The NetBSD Foundation, Inc.
 * All rights reserved.
+*
 * This code is derived from software contributed to The NetBSD Foundation
 * by Reinoud Zandijk
+*
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 @@ -24,78 +24,62 @@
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */
 #include "opt_exynos.h"
 #include "opt_arm_debug.h"
 #include "gpio.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: exynos_gpio.c,v 1.21 2015/12/27 12:42:14 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: exynos_gpio.c,v 1.22 2015/12/30 04:30:27 marty Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/kmem.h>
 #include <sys/gpio.h>
 #include <dev/gpio/gpiovar.h>
 #include <arm/samsung/exynos_reg.h>
 #include <arm/samsung/exynos_var.h>
 #include <arm/samsung/exynos_intr.h>
 #include <arm/samsung/exynos_pinctrl.h>
 #include <dev/fdt/fdtvar.h>
 struct exynos_gpio_pin_cfg {
 	uint32_t cfg;
 	uint32_t pud;
 	uint32_t drv;
 	uint32_t conpwd;
 	uint32_t pudpwd;
 };
 struct exynos_gpio_softc;
 struct exynos_gpio_bank {
 	const char		bank_name[6];
 	device_t		bank_dev;
 	struct gpio_chipset_tag	bank_gc;
 	struct exynos_gpio_softc *bank_sc;
 	gpio_pin_t		bank_pins[8];
 	const bus_addr_t	bank_core_offset;
 	const uint8_t		bank_bits;
 	uint8_t			bank_pin_mask;
 	uint8_t			bank_pin_inuse_mask;
 	bus_space_handle_t	bank_bsh;
 	struct exynos_gpio_pin_cfg bank_cfg;
 	struct exynos_gpio_bank * bank_next;
 };
 struct exynos_gpio_softc {
 	device_t		sc_dev;
 	bus_space_tag_t		sc_bst;
 	bus_space_handle_t	sc_bsh;
 };
 struct exynos_gpio_pin {
 	struct exynos_gpio_softc *pin_sc;
 	int			  pin_no;
 	u_int			  pin_flags;
 	int			  pin_actlo;
 	const struct exynos_gpio_bank   *pin_bank;
 };
 //#define GPIO_REG(v,s,o) (EXYNOS##v##_GPIO_##s##_OFFSET + (o))
 #define GPIO_REG(v,s,o) ((o))
 #define GPIO_GRP(v, s, o, n, b)	\
 	{ \
 @@ -134,42 +118,41 @@ static struct exynos_gpio_bank exynos5_b
 	GPIO_GRP(5, MUXC, 0x00C0, gpg2, 2),
 	GPIO_GRP(5, MUXC, 0x00E0, gpj4, 4),
 	GPIO_GRP(5, MUXD, 0x0000, gpa0, 8),
 	GPIO_GRP(5, MUXD, 0x0020, gpa1, 6),
 	GPIO_GRP(5, MUXD, 0x0040, gpa2, 8),
 	GPIO_GRP(5, MUXD, 0x0060, gpb0, 5),
 	GPIO_GRP(5, MUXD, 0x0080, gpb1, 5),
 	GPIO_GRP(5, MUXD, 0x00A0, gpb2, 4),
 	GPIO_GRP(5, MUXD, 0x00C0, gpb3, 8),
 	GPIO_GRP(5, MUXD, 0x00E0, gpb4, 2),
 	GPIO_GRP(5, MUXD, 0x0100, gph0, 4),
-	GPIO_GRP(5, MUXE, 0x0000, gpz0, 7),
+	GPIO_GRP(5, MUXE, 0x0000, gpz, 7),
 };
 struct exynos_gpio_bank *exynos_gpio_banks = exynos5_banks;
 static int exynos_gpio_pin_read(void *, int);
 static void exynos_gpio_pin_write(void *, int, int);
 static void exynos_gpio_pin_ctl(void *, int, int);
 static void *exynos_gpio_fdt_acquire(device_t, const void *,
 				     size_t, int);
 static void exynos_gpio_fdt_release(device_t, void *);
 static int exynos_gpio_fdt_read(device_t, void *, bool);
 static void exynos_gpio_fdt_write(device_t, void *, int, bool);
 static struct exynos_gpio_bank *exynos_gpio_bank_lookup(const char *);
 static int exynos_gpio_cfprint(void *, const char *);
 struct fdtbus_gpio_controller_func exynos_gpio_funcs = {
 	.acquire = exynos_gpio_fdt_acquire,
 	.release = exynos_gpio_fdt_release,
 	.read = exynos_gpio_fdt_read,
 	.write = exynos_gpio_fdt_write
 };
 #define GPIO_WRITE(bank, reg, val) \
 	bus_space_write_4((bank)->bank_sc->sc_bst, \
 	    (bank)->bank_sc->sc_bsh, \
 	    (bank)->bank_core_offset + (reg), (val))
 #define GPIO_READ(bank, reg) \
 @@ -269,82 +252,112 @@ exynos_gpio_pin_ctl(void *cookie, int pi
 	/* honour i/o */
 	if (flags & GPIO_PIN_INPUT) {
 		ncfg.cfg &= ~(0x0f << shift);
 		ncfg.cfg |= EXYNOS_GPIO_FUNC_INPUT << shift;
 	} else if (flags & GPIO_PIN_OUTPUT) {
 		ncfg.cfg &= ~(0x0f << shift);
 		ncfg.cfg |= EXYNOS_GPIO_FUNC_OUTPUT << shift;
+	}
 	/* update any config registers that changed */
 	exynos_gpio_update_cfg_regs(bank, &ncfg);
+}
-void
+void exynos_gpio_pin_ctl_read(const struct exynos_gpio_bank *bank,
 			      struct exynos_gpio_pin_cfg *cfg)
+{
 	cfg->cfg = GPIO_READ(bank, EXYNOS_GPIO_CON);
 	cfg->pud = GPIO_READ(bank, EXYNOS_GPIO_PUD);
 	cfg->drv = GPIO_READ(bank, EXYNOS_GPIO_DRV);
 	cfg->conpwd = GPIO_READ(bank, EXYNOS_GPIO_CONPWD);
 	cfg->pudpwd = GPIO_READ(bank, EXYNOS_GPIO_PUDPWD);
+}
 void exynos_gpio_pin_ctl_write(const struct exynos_gpio_bank *bank,
 			       const struct exynos_gpio_pin_cfg *cfg)
+{
 		GPIO_WRITE(bank, EXYNOS_GPIO_CON, cfg->cfg);
 		GPIO_WRITE(bank, EXYNOS_GPIO_PUD, cfg->pud);
 		GPIO_WRITE(bank, EXYNOS_GPIO_DRV, cfg->drv);
 		GPIO_WRITE(bank, EXYNOS_GPIO_CONPWD, cfg->conpwd);
 		GPIO_WRITE(bank, EXYNOS_GPIO_PUDPWD, cfg->pudpwd);
+}
 struct exynos_gpio_softc *
 exynos_gpio_bank_config(struct exynos_pinctrl_softc * parent,
 			const struct fdt_attach_args *faa, int node)
+{
 	struct exynos_gpio_bank *bank = kmem_zalloc(sizeof(*bank), KM_SLEEP);
 	struct exynos_gpio_softc *sc = kmem_zalloc(sizeof(*sc), KM_SLEEP);
 	struct gpiobus_attach_args gba;
 	struct gpio_chipset_tag *gc_tag;
 	char result[64];
 	OF_getprop(node, "name", result, sizeof(result));
 	bank = exynos_gpio_bank_lookup(result);
 	if (bank == NULL) {
 		aprint_error_dev(parent->sc_dev, "no bank found for %s\n",
 		    result);
-		return;
+		return NULL;
+	}
 	sc->sc_dev = parent->sc_dev;
 	sc->sc_bst = &armv7_generic_bs_tag;
 	sc->sc_bsh = parent->sc_bsh;
 	sc->sc_bank = bank;
 	gc_tag = &bank->bank_gc;
 	gc_tag->gp_cookie = bank;
 	gc_tag->gp_pin_read  = exynos_gpio_pin_read;
 	gc_tag->gp_pin_write = exynos_gpio_pin_write;
 	gc_tag->gp_pin_ctl   = exynos_gpio_pin_ctl;
 	memset(&gba, 0, sizeof(gba));
 	gba.gba_gc = &bank->bank_gc;
 	gba.gba_pins = bank->bank_pins;
 	gba.gba_npins = bank->bank_bits;
 	bank->bank_sc = sc;
 	bank->bank_dev = config_found_ia(parent->sc_dev, "gpiobus", &gba,
 					 exynos_gpio_cfprint);
 	bank->bank_pin_mask = __BIT(bank->bank_bits) - 1;
 	bank->bank_pin_inuse_mask = 0;
 	/* read in our initial settings */
 	bank->bank_cfg.cfg = GPIO_READ(bank, EXYNOS_GPIO_CON);
 	bank->bank_cfg.pud = GPIO_READ(bank, EXYNOS_GPIO_PUD);
 	bank->bank_cfg.drv = GPIO_READ(bank, EXYNOS_GPIO_DRV);
 	bank->bank_cfg.conpwd = GPIO_READ(bank, EXYNOS_GPIO_CONPWD);
 	bank->bank_cfg.pudpwd = GPIO_READ(bank, EXYNOS_GPIO_PUDPWD);
 	fdtbus_register_gpio_controller(bank->bank_dev, node,
 					&exynos_gpio_funcs);
 	return sc;
+}
-static struct exynos_gpio_bank *
+/*
  * This function is a bit funky.  Given a string that may look like
  * 'gpAN' or 'gpAN-P' it is meant to find a match to the part before
  * the '-', or the four character string if the dash is not present.
  */
 struct exynos_gpio_bank *
 exynos_gpio_bank_lookup(const char *name)
+{
 	struct exynos_gpio_bank *bank;
 	for (u_int n = 0; n < __arraycount(exynos5_banks); n++) {
-		struct exynos_gpio_bank *bank = &exynos_gpio_banks[n];
+		bank = &exynos_gpio_banks[n];
-		if (strncmp(bank->bank_name, name, strlen(name)) == 0) {
+		if (!strncmp(bank->bank_name, name,
 			     strlen(bank->bank_name))) {
 			return bank;
+		}
+	}
 	return NULL;
+}
 #if notyet
 static int
 exynos_gpio_pin_lookup(const char *name)
+{
 	char *p;

 @@ -1,22 +1,19 @@
-/*	$NetBSD: exynos_i2c.c,v 1.8 2015/12/24 21:30:05 marty Exp $ */
+/*	$NetBSD: exynos_i2c.c,v 1.9 2015/12/30 04:30:27 marty Exp $ */
 /*
- * Copyright (c) 2014 The NetBSD Foundation, Inc.
+ * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Reinoud Zandijk.
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 @@ -24,91 +21,116 @@
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
+ *
  */
 #include "opt_exynos.h"
 #include "opt_arm_debug.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: exynos_i2c.c,v 1.8 2015/12/24 21:30:05 marty Exp $");
+__KERNEL_RCSID(0, "$NetBSD: exynos_i2c.c,v 1.9 2015/12/30 04:30:27 marty Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/kmem.h>
 #include <arm/samsung/exynos_reg.h>
 #include <arm/samsung/exynos_var.h>
 #include <arm/samsung/exynos_intr.h>
 #include <sys/gpio.h>
 #include <dev/gpio/gpiovar.h>
 #include <dev/i2c/i2cvar.h>
 #include <dev/i2c/i2c_bitbang.h>
 #include <dev/fdt/fdtvar.h>
 struct exynos_i2c_softc {
 	device_t		sc_dev;
 	bus_space_tag_t		sc_bst;
 	bus_space_handle_t	sc_bsh;
 	void *			sc_ih;
-	u_int			sc_port;
+	struct clk *		sc_clk;
-	struct fdtbus_gpio_pin  *sc_sda;
+	struct fdtbus_pinctrl_pin  *sc_sda;
-	struct fdtbus_gpio_pin  *sc_scl;
+	struct fdtbus_pinctrl_pin  *sc_scl;
 	bool			sc_sda_is_output;
 	struct i2c_controller 	sc_ic;
 	kmutex_t		sc_lock;
 	kcondvar_t		sc_cv;
 	device_t		sc_i2cdev;
 };
 static u_int i2c_port;
 static int	exynos_i2c_intr(void *);
 static int	exynos_i2c_acquire_bus(void *, int);
 static void	exynos_i2c_release_bus(void *, int);
 static int	exynos_i2c_send_start(void *, int);
 static int	exynos_i2c_send_stop(void *, int);
 static int	exynos_i2c_initiate_xfer(void *, i2c_addr_t, int);
 static int	exynos_i2c_read_byte(void *, uint8_t *, int);
 static int	exynos_i2c_write_byte(void *, uint8_t , int);
-static bool exynos_i2c_attach_i2cbus(struct exynos_i2c_softc *,
+static int	exynos_i2c_wait(struct exynos_i2c_softc *, int);
 				     struct i2c_controller *);
 static int exynos_i2c_match(device_t, cfdata_t, void *);
 static void exynos_i2c_attach(device_t, device_t, void *);
 static i2c_tag_t exynos_i2c_get_tag(device_t);
 struct fdtbus_i2c_controller_func exynos_i2c_funcs = {
 	.get_tag = exynos_i2c_get_tag
 };
 CFATTACH_DECL_NEW(exynos_i2c, sizeof(struct exynos_i2c_softc),
     exynos_i2c_match, exynos_i2c_attach, NULL, NULL);
 #define I2C_WRITE(sc, reg, val) \
-    bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
+    bus_space_write_1((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
 #define I2C_READ(sc, reg) \
-    bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
+    bus_space_read_1((sc)->sc_bst, (sc)->sc_bsh, (reg))
-#define IICON 0
+#define IICCON  0x00
-#define IRQPEND (1<<4)
+#define IICSTAT 0x04
 #define IICADD  0x08
 #define IICDS   0x0C
 #define ACKENABLE  (1<<7)
 #define TXPRESCALE (1<<6)
 #define INTENABLE  (1<<5)
 #define IRQPEND    (1<<4)
 #define PRESCALE   (0x0f)
 #define MODESELECT  (3<<6)
 #define BUSYSTART   (1<<5)
 #define BUSENABLE   (1<<4)
 #define ARBITRATION (1<<3)
 #define SLAVESTATUS (1<<2)
 #define ZEROSTATUS  (1<<1)
 #define LASTBIT     (1<<0)
 #define READBIT     (1<<7)
 static int
 exynos_i2c_match(device_t self, cfdata_t cf, void *aux)
+{
 	const char * const compatible[] = { "samsung,s3c2440-i2c", NULL };
 	struct fdt_attach_args * const faa = aux;
 	return of_match_compatible(faa->faa_phandle, compatible);
+}
 static void
 exynos_i2c_attach(device_t parent, device_t self, void *aux)
+{
 @@ -116,44 +138,43 @@ exynos_i2c_attach(device_t parent, devic
 	struct fdt_attach_args * const faa = aux;
 	const int phandle = faa->faa_phandle;
 	struct i2cbus_attach_args iba;
 	char intrstr[128];
 	bus_addr_t addr;
 	bus_size_t size;
 	int error;
 	char result[64];
 	int i2c_handle;
 	int len;
 	int handle;
-	int func /*, pud, drv */;
+	int func, pud, drv;
 	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
 		aprint_error(": couldn't get registers\n");
 		return;
+	}
 	sc->sc_dev  = self;
 	sc->sc_bst = faa->faa_bst;
 	error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
 	if (error) {
 		aprint_error(": couldn't map %#llx: %d", (uint64_t)addr,
 			     error);
 		return;
+	}
 	sc->sc_port = i2c_port++;
 	mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM);
 	cv_init(&sc->sc_cv, device_xname(self));
 	aprint_normal(" @ 0x%08x\n", (uint)addr);
 	if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
 		aprint_error_dev(self, "failed to decode interrupt\n");
 		return;
+	}
 	sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_VM,
 	    FDT_INTR_MPSAFE, exynos_i2c_intr, sc);
 	if (sc->sc_ih == NULL) {
 		aprint_error_dev(self, "couldn't establish interrupt on %s\n",
 @@ -174,191 +195,195 @@ exynos_i2c_attach(device_t parent, devic
 	if (len <= 0) {
 		aprint_error_dev(self, "couldn't get pins.\n");
 		return;
+	}
 	len = OF_getprop(i2c_handle, "samsung,pin-function",
 			 &handle, sizeof(handle));
 	if (len <= 0) {
 		aprint_error_dev(self, "couldn't get pin-function.\n");
 		return;
 	} else
 		func = be32toh(handle);
-	sc->sc_sda = fdtbus_gpio_acquire(phandle, &result[0], func);
+	sc->sc_sda = fdtbus_pinctrl_acquire(phandle, &result[0]);
-	sc->sc_scl = fdtbus_gpio_acquire(phandle, &result[7], func);
+	if (sc->sc_sda == NULL) {
 		printf("could not acquire sda gpio %s\n", &result[0]);
 		return;
+	}
 	sc->sc_scl = fdtbus_pinctrl_acquire(phandle, &result[7]);
 	if (sc->sc_scl == NULL) {
 		printf("could not acquire scl gpio %s\n", &result[7]);
 		return;
+	}
 	/* MJF: Need fdtbus_gpio_configure */
 #if 0
 	len = OF_getprop(i2c_handle, "samsung,pin-pud", &handle,
 			 sizeof(&handle));
 	if (len <= 0) {
 		aprint_error_dev(self, "couldn't get pin-pud.\n");
 		return;
 	} else
 		pud = be32toh(handle);
 	len = OF_getprop(i2c_handle, "samsung,pin-drv", &handle,
 			 sizeof(&handle));
 	if (len <= 0) {
 		aprint_error_dev(self, "couldn't get pin-drv.\n");
 		return;
 	} else
 		drv = be32toh(handle);
-#endif
+	struct exynos_gpio_pin_cfg cfg;
-	if (!exynos_i2c_attach_i2cbus(sc, &sc->sc_ic))
+	cfg.cfg = func;
-		return;
+	cfg.pud = pud;
 	cfg.drv = drv;
 	cfg.conpwd = 0;
 	cfg.pudpwd = 0;
 	fdtbus_pinctrl_set_cfg(sc->sc_scl, &cfg);
 	fdtbus_pinctrl_set_cfg(sc->sc_sda, &cfg);
 	sc->sc_ic.ic_cookie = sc;
 	sc->sc_ic.ic_acquire_bus = exynos_i2c_acquire_bus;
 	sc->sc_ic.ic_release_bus = exynos_i2c_release_bus;
 	sc->sc_ic.ic_send_start  = exynos_i2c_send_start;
 	sc->sc_ic.ic_send_stop   = exynos_i2c_send_stop;
 	sc->sc_ic.ic_initiate_xfer = exynos_i2c_initiate_xfer;
 	sc->sc_ic.ic_read_byte   = exynos_i2c_read_byte;
 	sc->sc_ic.ic_write_byte  = exynos_i2c_write_byte;
 	sc->sc_i2cdev = config_found_ia(self, "i2cbus", &iba, iicbus_print);
+}
-static bool
+static i2c_tag_t
-exynos_i2c_attach_i2cbus(struct exynos_i2c_softc *i2c_sc,
+exynos_i2c_get_tag(device_t dev)
 			 struct i2c_controller *i2c_cntr)
 	i2c_cntr->ic_cookie = i2c_sc;
 	i2c_cntr->ic_acquire_bus = exynos_i2c_acquire_bus;
 	i2c_cntr->ic_release_bus = exynos_i2c_release_bus;
 	i2c_cntr->ic_send_start  = exynos_i2c_send_start;
 	i2c_cntr->ic_send_stop   = exynos_i2c_send_stop;
 	i2c_cntr->ic_initiate_xfer = exynos_i2c_initiate_xfer;
 	i2c_cntr->ic_read_byte   = exynos_i2c_read_byte;
 	i2c_cntr->ic_write_byte  = exynos_i2c_write_byte;
 	return 1;
 #define EXYNOS_I2C_BB_SDA	__BIT(1)
 #define EXYNOS_I2C_BB_SCL	__BIT(2)
 #define EXYNOS_I2C_BB_SDA_OUT	__BIT(3)
 #define EXYNOS_I2C_BB_SDA_IN	0
 static void
 exynos_i2c_bb_set_bits(void *cookie, uint32_t bits)
 	struct exynos_i2c_softc *i2c_sc = cookie;
 	int sda, scl;
 	sda = (bits & EXYNOS_I2C_BB_SDA) ? true : false;
 	scl = (bits & EXYNOS_I2C_BB_SCL) ? true : false;
 	if (i2c_sc->sc_sda_is_output)
 		fdtbus_gpio_write(i2c_sc->sc_sda, sda);
 	fdtbus_gpio_write(i2c_sc->sc_scl, scl);
 static uint32_t
 exynos_i2c_bb_read_bits(void *cookie)
+{
-	struct exynos_i2c_softc *i2c_sc = cookie;
+	struct exynos_i2c_softc * const sc = device_private(dev);
 	int sda, scl;
 	sda = 0;
 	if (!i2c_sc->sc_sda_is_output)
 		sda = fdtbus_gpio_read(i2c_sc->sc_sda);
 	scl = fdtbus_gpio_read(i2c_sc->sc_scl);
-	return (sda ? EXYNOS_I2C_BB_SDA : 0) | (scl ? EXYNOS_I2C_BB_SCL : 0);
+	return &sc->sc_ic;
+}
 static void
 exynos_i2c_bb_set_dir(void *cookie, uint32_t bits)
 	struct exynos_i2c_softc *i2c_sc = cookie;
 	int flags;
 	flags = GPIO_PIN_INPUT | GPIO_PIN_TRISTATE;
 	i2c_sc->sc_sda_is_output = ((bits & EXYNOS_I2C_BB_SDA_OUT) != 0);
 	if (i2c_sc->sc_sda_is_output)
 		flags = GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE;
 	/* MJF: This is wrong but fdtbus has no ctrl operation */
 	fdtbus_gpio_write(i2c_sc->sc_sda, flags);
 static const struct i2c_bitbang_ops exynos_i2c_bbops = {
 	exynos_i2c_bb_set_bits,
 	exynos_i2c_bb_set_dir,
 	exynos_i2c_bb_read_bits,
 		EXYNOS_I2C_BB_SDA,
 		EXYNOS_I2C_BB_SCL,
 		EXYNOS_I2C_BB_SDA_OUT,
 		EXYNOS_I2C_BB_SDA_IN,
 };
 static int
 exynos_i2c_intr(void *priv)
+{
 	struct exynos_i2c_softc * const sc = priv;
-	uint32_t istatus = I2C_READ(sc, IICON);
+	uint8_t istatus = I2C_READ(sc, IICCON);
 	if (!(istatus & IRQPEND))
 		return 0;
 	istatus &= ~IRQPEND;
-	I2C_WRITE(sc, IICON, istatus);
+	I2C_WRITE(sc, IICCON, istatus);
 	mutex_enter(&sc->sc_lock);
 	cv_broadcast(&sc->sc_cv);
 	mutex_exit(&sc->sc_lock);
 	return 1;
+}
 static int
 exynos_i2c_acquire_bus(void *cookie, int flags)
+{
 	struct exynos_i2c_softc *i2c_sc = cookie;
 	/* XXX what to do in polling case? could another cpu help */
 	if (flags & I2C_F_POLL)
 		return 0;
 	mutex_enter(&i2c_sc->sc_lock);
 	return 0;
+}
 static void
 exynos_i2c_release_bus(void *cookie, int flags)
+{
 	struct exynos_i2c_softc *i2c_sc = cookie;
 	/* XXX what to do in polling case? could another cpu help */
 	if (flags & I2C_F_POLL)
 		return;
 	mutex_exit(&i2c_sc->sc_lock);
+}
 static int
 exynos_i2c_wait(struct exynos_i2c_softc *sc, int flags)
+{
 	int error, retry;
 	uint8_t stat = 0;
 	retry = (flags & I2C_F_POLL) ? 100000 : 100;
 	while (--retry > 0) {
 		if ((flags & I2C_F_POLL) == 0) {
 			error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_lock,
 			    max(mstohz(10), 1));
 			if (error) {
 				return error;
+			}
+		}
 		stat = I2C_READ(sc, IICSTAT);
 		if (!(stat & BUSYSTART)) {
 			break;
+		}
 		if (flags & I2C_F_POLL) {
 			delay(10);
+		}
+	}
 	if (retry == 0) {
 		stat = I2C_READ(sc, IICSTAT);
 		device_printf(sc->sc_dev, "timed out, status = %#x\n", stat);
 		return ETIMEDOUT;
+	}
 	return 0;
+}
 static int
 exynos_i2c_send_start(void *cookie, int flags)
+{
-	return i2c_bitbang_send_start(cookie, flags, &exynos_i2c_bbops);
+	struct exynos_i2c_softc *sc = cookie;
 	I2C_WRITE(sc, IICSTAT, 0xF0);
 	return 0;
+}
 static int
 exynos_i2c_send_stop(void *cookie, int flags)
+{
-	return i2c_bitbang_send_stop(cookie, flags, &exynos_i2c_bbops);
+	struct exynos_i2c_softc *sc = cookie;
 	I2C_WRITE(sc, IICSTAT, 0xD0);
 	return 0;
+}
 static int
 exynos_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags)
+{
-	return i2c_bitbang_initiate_xfer(cookie, addr, flags,
+	struct exynos_i2c_softc *sc = cookie;
-					 &exynos_i2c_bbops);
+	uint8_t byte = addr & 0x7f;
 	if (flags & I2C_F_READ)
 		byte |= READBIT;
 	else
 		byte &= ~READBIT;
 	I2C_WRITE(sc, IICADD, addr);
 	exynos_i2c_send_start(cookie, flags);
 	exynos_i2c_write_byte(cookie, byte, flags);
 	return exynos_i2c_wait(cookie, flags);
+}
 static int
 exynos_i2c_read_byte(void *cookie, uint8_t *bytep, int flags)
+{
-	return i2c_bitbang_read_byte(cookie, bytep, flags,
+	struct exynos_i2c_softc *sc = cookie;
-				     &exynos_i2c_bbops);
+	int error = exynos_i2c_wait(sc, flags);
 	if (error)
 		return error;
 	*bytep = I2C_READ(sc, IICDS) & 0xff;
 	if (flags & I2C_F_STOP)
 		exynos_i2c_send_stop(cookie, flags);
 	return 0;
+}
 static int
 exynos_i2c_write_byte(void *cookie, uint8_t byte, int flags)
+{
-	return i2c_bitbang_write_byte(cookie, byte, flags,
+	struct exynos_i2c_softc *sc = cookie;
-				      &exynos_i2c_bbops);
+	int error = exynos_i2c_wait(sc, flags);
 	if (error)
 		return error;
 	I2C_WRITE(sc, IICDS, byte);
 	return 0;
+}

 @@ -1,14 +1,14 @@
-/*	$NetBSD: exynos_pinctrl.c,v 1.7 2015/12/27 12:21:37 jmcneill Exp $ */
+/*	$NetBSD: exynos_pinctrl.c,v 1.8 2015/12/30 04:30:27 marty Exp $ */
 /*-
 * Copyright (c) 2015 The NetBSD Foundation, Inc.
 * All rights reserved.
+*
 * This code is derived from software contributed to The NetBSD Foundation
 * by Marty Fouts
+*
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 @@ -24,66 +24,79 @@
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */
 #include "opt_exynos.h"
 #include "opt_arm_debug.h"
 #include "gpio.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: exynos_pinctrl.c,v 1.7 2015/12/27 12:21:37 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: exynos_pinctrl.c,v 1.8 2015/12/30 04:30:27 marty Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/kmem.h>
 #include <sys/gpio.h>
 #include <dev/gpio/gpiovar.h>
 #include <arm/samsung/exynos_reg.h>
 #include <arm/samsung/exynos_var.h>
 #include <arm/samsung/exynos_intr.h>
 #include <arm/samsung/exynos_pinctrl.h>
 #include <dev/fdt/fdtvar.h>
 static int exynos_pinctrl_match(device_t, cfdata_t, void *);
 static void exynos_pinctrl_attach(device_t, device_t, void *);
 static void *exynos_pinctrl_acquire(device_t, const char *);
 static void  exynos_pinctrl_release(device_t, void *);
 static void  exynos_pinctrl_get_cfg(struct fdtbus_pinctrl_pin *, void *);
 static void  exynos_pinctrl_set_cfg(struct fdtbus_pinctrl_pin *, void *);
 static struct fdtbus_pinctrl_controller_func exynos_pinctrl_controller_func = {
 	.acquire = exynos_pinctrl_acquire,
 	.release = exynos_pinctrl_release,
 	.get     = exynos_pinctrl_get_cfg,
 	.set     = exynos_pinctrl_set_cfg,
 };
 CFATTACH_DECL_NEW(exynos_pinctrl, sizeof(struct exynos_pinctrl_softc),
 	exynos_pinctrl_match, exynos_pinctrl_attach, NULL, NULL);
 static int
 exynos_pinctrl_match(device_t parent, cfdata_t cf, void *aux)
+{
 	const char * const compatible[] = { "samsung,exynos5420-pinctrl",
 					    NULL };
 	struct fdt_attach_args * const faa = aux;
 	return of_match_compatible(faa->faa_phandle, compatible);
+}
 static void
 exynos_pinctrl_attach(device_t parent, device_t self, void *aux)
+{
 	struct exynos_pinctrl_softc * const sc
 		= kmem_zalloc(sizeof(*sc), KM_SLEEP);
 	struct fdt_attach_args * const faa = aux;
 	struct exynos_gpio_softc *child_sc;
 	bus_addr_t addr;
 	bus_size_t size;
 	int error;
 	int child;
 	if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) {
 		aprint_error(": couldn't get registers\n");
 		return;
+	}
 	aprint_normal(" pinctl @ 0x%08x ", (uint)addr);
 	sc->sc_dev = self;
 	sc->sc_bst = faa->faa_bst;
 @@ -91,16 +104,51 @@ exynos_pinctrl_attach(device_t parent, d
 	if (error) {
 		aprint_error(": couldn't map %#llx: %d",
 			     (uint64_t)addr, error);
 		return;
+	}
 	aprint_naive("\n");
 	aprint_normal("\n");
 	for (child = OF_child(faa->faa_phandle); child;
 	     child = OF_peer(child)) {
 		if (of_getprop_bool(child, "gpio-controller") == false)
 			continue;
-		exynos_gpio_bank_config(sc, faa, child);
+		child_sc = exynos_gpio_bank_config(sc, faa, child);
 		fdtbus_register_pinctrl_controller(child_sc->sc_dev, child,
 					    &exynos_pinctrl_controller_func);
+	}
+}
 static void *exynos_pinctrl_acquire(device_t self, const char *name)
+{
 	return exynos_gpio_bank_lookup(name);
+}
 static void exynos_pinctrl_release(device_t self, void *cookie)
+{
+}
 static void exynos_pinctrl_get_cfg(struct fdtbus_pinctrl_pin *pin,
 				   void *cookie)
+{
 	struct exynos_gpio_bank *bank = pin->pp_priv;
 	struct exynos_gpio_pin_cfg *cfg  = cookie;
 	struct exynos_gpio_pin_cfg **cfgp = &cfg;
 	struct exynos_gpio_pin_cfg *newcfg = kmem_zalloc(sizeof(*newcfg),
 							 KM_SLEEP);
 	if (newcfg == NULL)
 		return;
 	exynos_gpio_pin_ctl_read(bank, newcfg);
 	*cfgp = newcfg;
 	return;
+}
 static void exynos_pinctrl_set_cfg(struct fdtbus_pinctrl_pin *pin,
 				   void *cookie)
+{
 	struct exynos_gpio_bank *bank = pin->pp_priv;
 	struct exynos_gpio_pin_cfg *cfg = cookie;
 	exynos_gpio_pin_ctl_write(bank, cfg);
+}

 @@ -1,14 +1,14 @@
-/*	$NetBSD: exynos_var.h,v 1.22 2015/12/24 01:10:51 marty Exp $	*/
+/*	$NetBSD: exynos_var.h,v 1.23 2015/12/30 04:30:27 marty Exp $	*/
 /*-
  * Copyright (c) 2013, 2014 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Matt Thomas of 3am Software Foundry.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Reinoud Zandijk.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
 @@ -94,75 +94,96 @@ struct exyo_attach_args {
 };
 struct exynos_gpio_pinset {
 	char pinset_bank[10];
 	uint8_t pinset_func;
 	uint8_t pinset_mask;
 };
 struct exynos_gpio_pindata {
 	gpio_chipset_tag_t pd_gc;
 	int pd_pin;
 };
 struct exynos_gpio_pin_cfg {
 	uint32_t cfg;
 	uint32_t pud;
 	uint32_t drv;
 	uint32_t conpwd;
 	uint32_t pudpwd;
 };
 struct exynos_gpio_softc {
 	device_t		sc_dev;
 	bus_space_tag_t		sc_bst;
 	bus_space_handle_t	sc_bsh;
 	struct exynos_gpio_bank *sc_bank;
 	int			sc_phandle;
 };
 #define EXYNOS_MAX_IIC_BUSSES 9
 struct i2c_controller;
 extern struct i2c_controller *exynos_i2cbus[EXYNOS_MAX_IIC_BUSSES];
 extern struct bus_space exynos_bs_tag;
 extern struct bus_space exynos_a4x_bs_tag;
 extern struct arm32_bus_dma_tag exynos_bus_dma_tag;
 extern struct arm32_bus_dma_tag exynos_coherent_bus_dma_tag;
 extern struct bus_space armv7_generic_bs_tag;
 extern struct bus_space armv7_generic_a4x_bs_tag;
 extern bus_space_handle_t exynos_core_bsh;
 extern bus_space_handle_t exynos_wdt_bsh;
 extern bus_space_handle_t exynos_pmu_bsh;
 extern bus_space_handle_t exynos_cmu_bsh;
 extern bus_space_handle_t exynos_sysreg_bsh;
 extern void exynos_bootstrap(vaddr_t, vaddr_t);
 extern void exynos_dma_bootstrap(psize_t memsize);
 struct exynos_pinctrl_softc;
 struct exynos_gpio_softc;
 struct fdt_attach_args;
 extern void exynos_gpio_bank_config(struct exynos_pinctrl_softc *,
 extern struct exynos_gpio_softc * exynos_gpio_bank_config(struct exynos_pinctrl_softc *,
 				    const struct fdt_attach_args *, int);
 extern void exynos_wdt_reset(void);
 extern void exynos_init_clkout_for_usb(void);	// board specific
 extern void exynos_clocks_bootstrap(void);
 extern void exynos_sysctl_cpufreq_init(void);
 extern uint64_t exynos_get_cpufreq(void);
 extern void exynos_device_register(device_t self, void *aux);
 extern void exynos_device_register_post_config(device_t self, void *aux);
 extern void exynos_usb_phy_init(bus_space_handle_t usb2phy_bsh);
 extern void exynos_usb_soc_powerup(void);
 extern void exyo_device_register(device_t self, void *aux);
 extern void exyo_device_register_post_config(device_t self, void *aux);
 extern struct exynos_gpio_bank *exynos_gpio_bank_lookup(const char *name);
 extern bool exynos_gpio_pinset_available(const struct exynos_gpio_pinset *);
 extern void exynos_gpio_pinset_acquire(const struct exynos_gpio_pinset *);
 extern void exynos_gpio_pinset_release(const struct exynos_gpio_pinset *);
 extern void exynos_gpio_pinset_to_pindata(const struct exynos_gpio_pinset *,
 	int pinnr, struct exynos_gpio_pindata *);
 extern bool exynos_gpio_pin_reserve(const char *, struct exynos_gpio_pindata *);
 extern void exynos_gpio_pin_ctl_read(const struct exynos_gpio_bank *,
 				     struct exynos_gpio_pin_cfg *);
 extern void exynos_gpio_pin_ctl_write(const struct exynos_gpio_bank *,
 				      const struct exynos_gpio_pin_cfg *);
 static inline void
 exynos_gpio_pindata_write(const struct exynos_gpio_pindata *pd, int value)
+{
         gpiobus_pin_write(pd->pd_gc, pd->pd_pin, value);
+}
 static inline int
 exynos_gpio_pindata_read(const struct exynos_gpio_pindata *pd)
+{
         return gpiobus_pin_read(pd->pd_gc, pd->pd_pin);
+}
 static inline void