 @@ -1292,1999 +1292,2000 @@ static void
 sjlj_emit_dispatch_table (rtx_code_label *dispatch_label, int num_dispatch)
+{
   machine_mode unwind_word_mode = targetm.unwind_word_mode ();
   machine_mode filter_mode = targetm.eh_return_filter_mode ();
   eh_landing_pad lp;
   rtx mem, fc, before, exc_ptr_reg, filter_reg;
   rtx_insn *seq;
   rtx first_reachable_label;
   basic_block bb;
   eh_region r;
   edge e;
   int i, disp_index;
   vec<tree> dispatch_labels = vNULL;
   fc = crtl->eh.sjlj_fc;
   start_sequence ();
   emit_label (dispatch_label);
 #ifndef DONT_USE_BUILTIN_SETJMP
   expand_builtin_setjmp_receiver (dispatch_label);
   /* The caller of expand_builtin_setjmp_receiver is responsible for
      making sure that the label doesn't vanish.  The only other caller
      is the expander for __builtin_setjmp_receiver, which places this
      label on the nonlocal_goto_label list.  Since we're modeling these
      CFG edges more exactly, we can use the forced_labels list instead.  */
   LABEL_PRESERVE_P (dispatch_label) = 1;
   forced_labels
     = gen_rtx_INSN_LIST (VOIDmode, dispatch_label, forced_labels);
 #endif
   /* Load up exc_ptr and filter values from the function context.  */
   mem = adjust_address (fc, unwind_word_mode, sjlj_fc_data_ofs);
   if (unwind_word_mode != ptr_mode)
+    {
 #ifdef POINTERS_EXTEND_UNSIGNED
       mem = convert_memory_address (ptr_mode, mem);
 #else
       mem = convert_to_mode (ptr_mode, mem, 0);
 #endif
+    }
   exc_ptr_reg = force_reg (ptr_mode, mem);
   mem = adjust_address (fc, unwind_word_mode,
 			sjlj_fc_data_ofs + GET_MODE_SIZE (unwind_word_mode));
   if (unwind_word_mode != filter_mode)
     mem = convert_to_mode (filter_mode, mem, 0);
   filter_reg = force_reg (filter_mode, mem);
   /* Jump to one of the directly reachable regions.  */
   disp_index = 0;
   first_reachable_label = NULL;
   /* If there's exactly one call site in the function, don't bother
      generating a switch statement.  */
   if (num_dispatch > 1)
     dispatch_labels.create (num_dispatch);
   for (i = 1; vec_safe_iterate (cfun->eh->lp_array, i, &lp); ++i)
     if (lp && lp->post_landing_pad)
+      {
 	rtx_insn *seq2;
 	rtx label;
 	start_sequence ();
 	lp->landing_pad = dispatch_label;
 	if (num_dispatch > 1)
+	  {
 	    tree t_label, case_elt, t;
 	    t_label = create_artificial_label (UNKNOWN_LOCATION);
 	    t = build_int_cst (integer_type_node, disp_index);
 	    case_elt = build_case_label (t, NULL, t_label);
 	    dispatch_labels.quick_push (case_elt);
 	    label = label_rtx (t_label);
+	  }
 	else
 	  label = gen_label_rtx ();
 	if (disp_index == 0)
 	  first_reachable_label = label;
 	emit_label (label);
 	r = lp->region;
 	if (r->exc_ptr_reg)
 	  emit_move_insn (r->exc_ptr_reg, exc_ptr_reg);
 	if (r->filter_reg)
 	  emit_move_insn (r->filter_reg, filter_reg);
 	seq2 = get_insns ();
 	end_sequence ();
 	before = label_rtx (lp->post_landing_pad);
 	bb = emit_to_new_bb_before (seq2, before);
 	e = make_edge (bb, bb->next_bb, EDGE_FALLTHRU);
 	e->count = bb->count;
 	e->probability = REG_BR_PROB_BASE;
 	if (current_loops)
+	  {
 	    struct loop *loop = bb->next_bb->loop_father;
 	    /* If we created a pre-header block, add the new block to the
 	       outer loop, otherwise to the loop itself.  */
 	    if (bb->next_bb == loop->header)
 	      add_bb_to_loop (bb, loop_outer (loop));
 	    else
 	      add_bb_to_loop (bb, loop);
 	    /* ???  For multiple dispatches we will end up with edges
 	       from the loop tree root into this loop, making it a
 	       multiple-entry loop.  Discard all affected loops.  */
 	    if (num_dispatch > 1)
+	      {
 		for (loop = bb->loop_father;
 		     loop_outer (loop); loop = loop_outer (loop))
 		  mark_loop_for_removal (loop);
+	      }
+	  }
 	disp_index++;
+      }
   gcc_assert (disp_index == num_dispatch);
   if (num_dispatch > 1)
+    {
       rtx disp = adjust_address (fc, TYPE_MODE (integer_type_node),
 				 sjlj_fc_call_site_ofs);
       expand_sjlj_dispatch_table (disp, dispatch_labels);
+    }
   seq = get_insns ();
   end_sequence ();
   bb = emit_to_new_bb_before (seq, first_reachable_label);
   if (num_dispatch == 1)
+    {
       e = make_edge (bb, bb->next_bb, EDGE_FALLTHRU);
       e->count = bb->count;
       e->probability = REG_BR_PROB_BASE;
       if (current_loops)
+	{
 	  struct loop *loop = bb->next_bb->loop_father;
 	  /* If we created a pre-header block, add the new block to the
 	     outer loop, otherwise to the loop itself.  */
 	  if (bb->next_bb == loop->header)
 	    add_bb_to_loop (bb, loop_outer (loop));
 	  else
 	    add_bb_to_loop (bb, loop);
+	}
+    }
   else
+    {
       /* We are not wiring up edges here, but as the dispatcher call
          is at function begin simply associate the block with the
 	 outermost (non-)loop.  */
       if (current_loops)
 	add_bb_to_loop (bb, current_loops->tree_root);
+    }
+}
 static void
 sjlj_build_landing_pads (void)
+{
   int num_dispatch;
   num_dispatch = vec_safe_length (cfun->eh->lp_array);
   if (num_dispatch == 0)
     return;
   sjlj_lp_call_site_index.safe_grow_cleared (num_dispatch);
   num_dispatch = sjlj_assign_call_site_values ();
   if (num_dispatch > 0)
+    {
       rtx_code_label *dispatch_label = gen_label_rtx ();
       int align = STACK_SLOT_ALIGNMENT (sjlj_fc_type_node,
 					TYPE_MODE (sjlj_fc_type_node),
 					TYPE_ALIGN (sjlj_fc_type_node));
       crtl->eh.sjlj_fc
 	= assign_stack_local (TYPE_MODE (sjlj_fc_type_node),
 			      int_size_in_bytes (sjlj_fc_type_node),
 			      align);
       sjlj_mark_call_sites ();
       sjlj_emit_function_enter (dispatch_label);
       sjlj_emit_dispatch_table (dispatch_label, num_dispatch);
       sjlj_emit_function_exit ();
+    }
   /* If we do not have any landing pads, we may still need to register a
      personality routine and (empty) LSDA to handle must-not-throw regions.  */
   else if (function_needs_eh_personality (cfun) != eh_personality_none)
+    {
       int align = STACK_SLOT_ALIGNMENT (sjlj_fc_type_node,
 					TYPE_MODE (sjlj_fc_type_node),
 					TYPE_ALIGN (sjlj_fc_type_node));
       crtl->eh.sjlj_fc
 	= assign_stack_local (TYPE_MODE (sjlj_fc_type_node),
 			      int_size_in_bytes (sjlj_fc_type_node),
 			      align);
       sjlj_mark_call_sites ();
       sjlj_emit_function_enter (NULL);
       sjlj_emit_function_exit ();
+    }
   sjlj_lp_call_site_index.release ();
+}
 /* After initial rtl generation, call back to finish generating
    exception support code.  */
 void
 finish_eh_generation (void)
+{
   basic_block bb;
   /* Construct the landing pads.  */
   if (targetm_common.except_unwind_info (&global_options) == UI_SJLJ)
     sjlj_build_landing_pads ();
   else
     dw2_build_landing_pads ();
   break_superblocks ();
   if (targetm_common.except_unwind_info (&global_options) == UI_SJLJ
       /* Kludge for Alpha (see alpha_gp_save_rtx).  */
       || single_succ_edge (ENTRY_BLOCK_PTR_FOR_FN (cfun))->insns.r)
     commit_edge_insertions ();
   /* Redirect all EH edges from the post_landing_pad to the landing pad.  */
   FOR_EACH_BB_FN (bb, cfun)
+    {
       eh_landing_pad lp;
       edge_iterator ei;
       edge e;
       lp = get_eh_landing_pad_from_rtx (BB_END (bb));
       FOR_EACH_EDGE (e, ei, bb->succs)
 	if (e->flags & EDGE_EH)
 	  break;
       /* We should not have generated any new throwing insns during this
 	 pass, and we should not have lost any EH edges, so we only need
 	 to handle two cases here:
 	 (1) reachable handler and an existing edge to post-landing-pad,
 	 (2) no reachable handler and no edge.  */
       gcc_assert ((lp != NULL) == (e != NULL));
       if (lp != NULL)
+	{
 	  gcc_assert (BB_HEAD (e->dest) == label_rtx (lp->post_landing_pad));
 	  redirect_edge_succ (e, BLOCK_FOR_INSN (lp->landing_pad));
 	  e->flags |= (CALL_P (BB_END (bb))
 		       ? EDGE_ABNORMAL | EDGE_ABNORMAL_CALL
 		       : EDGE_ABNORMAL);
+	}
+    }
+}
 /* This section handles removing dead code for flow.  */
 void
 remove_eh_landing_pad (eh_landing_pad lp)
+{
   eh_landing_pad *pp;
   for (pp = &lp->region->landing_pads; *pp != lp; pp = &(*pp)->next_lp)
     continue;
   *pp = lp->next_lp;
   if (lp->post_landing_pad)
     EH_LANDING_PAD_NR (lp->post_landing_pad) = 0;
   (*cfun->eh->lp_array)[lp->index] = NULL;
+}
 /* Splice the EH region at PP from the region tree.  */
 static void
 remove_eh_handler_splicer (eh_region *pp)
+{
   eh_region region = *pp;
   eh_landing_pad lp;
   for (lp = region->landing_pads; lp ; lp = lp->next_lp)
+    {
       if (lp->post_landing_pad)
 	EH_LANDING_PAD_NR (lp->post_landing_pad) = 0;
       (*cfun->eh->lp_array)[lp->index] = NULL;
+    }
   if (region->inner)
+    {
       eh_region p, outer;
       outer = region->outer;
       *pp = p = region->inner;
       do
+	{
 	  p->outer = outer;
 	  pp = &p->next_peer;
 	  p = *pp;
+	}
       while (p);
+    }
   *pp = region->next_peer;
   (*cfun->eh->region_array)[region->index] = NULL;
+}
 /* Splice a single EH region REGION from the region tree.
    To unlink REGION, we need to find the pointer to it with a relatively
    expensive search in REGION's outer region.  If you are going to
    remove a number of handlers, using remove_unreachable_eh_regions may
    be a better option.  */
 void
 remove_eh_handler (eh_region region)
+{
   eh_region *pp, *pp_start, p, outer;
   outer = region->outer;
   if (outer)
     pp_start = &outer->inner;
   else
     pp_start = &cfun->eh->region_tree;
   for (pp = pp_start, p = *pp; p != region; pp = &p->next_peer, p = *pp)
     continue;
   remove_eh_handler_splicer (pp);
+}
 /* Worker for remove_unreachable_eh_regions.
    PP is a pointer to the region to start a region tree depth-first
    search from.  R_REACHABLE is the set of regions that have to be
    preserved.  */
 static void
 remove_unreachable_eh_regions_worker (eh_region *pp, sbitmap r_reachable)
+{
   while (*pp)
+    {
       eh_region region = *pp;
       remove_unreachable_eh_regions_worker (&region->inner, r_reachable);
       if (!bitmap_bit_p (r_reachable, region->index))
 	remove_eh_handler_splicer (pp);
       else
 	pp = &region->next_peer;
+    }
+}
 /* Splice all EH regions *not* marked in R_REACHABLE from the region tree.
    Do this by traversing the EH tree top-down and splice out regions that
    are not marked.  By removing regions from the leaves, we avoid costly
    searches in the region tree.  */
 void
 remove_unreachable_eh_regions (sbitmap r_reachable)
+{
   remove_unreachable_eh_regions_worker (&cfun->eh->region_tree, r_reachable);
+}
 /* Invokes CALLBACK for every exception handler landing pad label.
    Only used by reload hackery; should not be used by new code.  */
 void
 for_each_eh_label (void (*callback) (rtx))
+{
   eh_landing_pad lp;
   int i;
   for (i = 1; vec_safe_iterate (cfun->eh->lp_array, i, &lp); ++i)
+    {
       if (lp)
+	{
 	  rtx lab = lp->landing_pad;
 	  if (lab && LABEL_P (lab))
 	    (*callback) (lab);
+	}
+    }
+}
 /* Create the REG_EH_REGION note for INSN, given its ECF_FLAGS for a
    call insn.
    At the gimple level, we use LP_NR
        > 0 : The statement transfers to landing pad LP_NR
        = 0 : The statement is outside any EH region
        < 0 : The statement is within MUST_NOT_THROW region -LP_NR.
    At the rtl level, we use LP_NR
        > 0 : The insn transfers to landing pad LP_NR
        = 0 : The insn cannot throw
        < 0 : The insn is within MUST_NOT_THROW region -LP_NR
        = INT_MIN : The insn cannot throw or execute a nonlocal-goto.
        missing note: The insn is outside any EH region.
   ??? This difference probably ought to be avoided.  We could stand
   to record nothrow for arbitrary gimple statements, and so avoid
   some moderately complex lookups in stmt_could_throw_p.  Perhaps
   NOTHROW should be mapped on both sides to INT_MIN.  Perhaps the
   no-nonlocal-goto property should be recorded elsewhere as a bit
   on the call_insn directly.  Perhaps we should make more use of
   attaching the trees to call_insns (reachable via symbol_ref in
   direct call cases) and just pull the data out of the trees.  */
 void
 make_reg_eh_region_note (rtx insn, int ecf_flags, int lp_nr)
+{
   rtx value;
   if (ecf_flags & ECF_NOTHROW)
     value = const0_rtx;
   else if (lp_nr != 0)
     value = GEN_INT (lp_nr);
   else
     return;
   add_reg_note (insn, REG_EH_REGION, value);
+}
 /* Create a REG_EH_REGION note for a CALL_INSN that cannot throw
    nor perform a non-local goto.  Replace the region note if it
    already exists.  */
 void
 make_reg_eh_region_note_nothrow_nononlocal (rtx insn)
+{
   rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
   rtx intmin = GEN_INT (INT_MIN);
   if (note != 0)
     XEXP (note, 0) = intmin;
   else
     add_reg_note (insn, REG_EH_REGION, intmin);
+}
 /* Return true if INSN could throw, assuming no REG_EH_REGION note
    to the contrary.  */
 bool
 insn_could_throw_p (const_rtx insn)
+{
   if (!flag_exceptions)
     return false;
   if (CALL_P (insn))
     return true;
   if (INSN_P (insn) && cfun->can_throw_non_call_exceptions)
     return may_trap_p (PATTERN (insn));
   return false;
+}
 /* Copy an REG_EH_REGION note to each insn that might throw beginning
    at FIRST and ending at LAST.  NOTE_OR_INSN is either the source insn
    to look for a note, or the note itself.  */
 void
 copy_reg_eh_region_note_forward (rtx note_or_insn, rtx_insn *first, rtx last)
+{
   rtx_insn *insn;
   rtx note = note_or_insn;
   if (INSN_P (note_or_insn))
+    {
       note = find_reg_note (note_or_insn, REG_EH_REGION, NULL_RTX);
       if (note == NULL)
 	return;
+    }
   note = XEXP (note, 0);
   for (insn = first; insn != last ; insn = NEXT_INSN (insn))
     if (!find_reg_note (insn, REG_EH_REGION, NULL_RTX)
         && insn_could_throw_p (insn))
       add_reg_note (insn, REG_EH_REGION, note);
+}
 /* Likewise, but iterate backward.  */
 void
 copy_reg_eh_region_note_backward (rtx note_or_insn, rtx_insn *last, rtx first)
+{
   rtx_insn *insn;
   rtx note = note_or_insn;
   if (INSN_P (note_or_insn))
+    {
       note = find_reg_note (note_or_insn, REG_EH_REGION, NULL_RTX);
       if (note == NULL)
 	return;
+    }
   note = XEXP (note, 0);
   for (insn = last; insn != first; insn = PREV_INSN (insn))
     if (insn_could_throw_p (insn))
       add_reg_note (insn, REG_EH_REGION, note);
+}
 /* Extract all EH information from INSN.  Return true if the insn
    was marked NOTHROW.  */
 static bool
 get_eh_region_and_lp_from_rtx (const_rtx insn, eh_region *pr,
 			       eh_landing_pad *plp)
+{
   eh_landing_pad lp = NULL;
   eh_region r = NULL;
   bool ret = false;
   rtx note;
   int lp_nr;
   if (! INSN_P (insn))
     goto egress;
   if (NONJUMP_INSN_P (insn)
       && GET_CODE (PATTERN (insn)) == SEQUENCE)
     insn = XVECEXP (PATTERN (insn), 0, 0);
   note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
   if (!note)
+    {
       ret = !insn_could_throw_p (insn);
       goto egress;
+    }
   lp_nr = INTVAL (XEXP (note, 0));
   if (lp_nr == 0 || lp_nr == INT_MIN)
+    {
       ret = true;
       goto egress;
+    }
   if (lp_nr < 0)
     r = (*cfun->eh->region_array)[-lp_nr];
   else
+    {
       lp = (*cfun->eh->lp_array)[lp_nr];
       r = lp->region;
+    }
  egress:
   *plp = lp;
   *pr = r;
   return ret;
+}
 /* Return the landing pad to which INSN may go, or NULL if it does not
    have a reachable landing pad within this function.  */
 eh_landing_pad
 get_eh_landing_pad_from_rtx (const_rtx insn)
+{
   eh_landing_pad lp;
   eh_region r;
   get_eh_region_and_lp_from_rtx (insn, &r, &lp);
   return lp;
+}
 /* Return the region to which INSN may go, or NULL if it does not
    have a reachable region within this function.  */
 eh_region
 get_eh_region_from_rtx (const_rtx insn)
+{
   eh_landing_pad lp;
   eh_region r;
   get_eh_region_and_lp_from_rtx (insn, &r, &lp);
   return r;
+}
 /* Return true if INSN throws and is caught by something in this function.  */
 bool
 can_throw_internal (const_rtx insn)
+{
   return get_eh_landing_pad_from_rtx (insn) != NULL;
+}
 /* Return true if INSN throws and escapes from the current function.  */
 bool
 can_throw_external (const_rtx insn)
+{
   eh_landing_pad lp;
   eh_region r;
   bool nothrow;
   if (! INSN_P (insn))
     return false;
   if (NONJUMP_INSN_P (insn)
       && GET_CODE (PATTERN (insn)) == SEQUENCE)
+    {
       rtx_sequence *seq = as_a <rtx_sequence *> (PATTERN (insn));
       int i, n = seq->len ();
       for (i = 0; i < n; i++)
 	if (can_throw_external (seq->element (i)))
 	  return true;
       return false;
+    }
   nothrow = get_eh_region_and_lp_from_rtx (insn, &r, &lp);
   /* If we can't throw, we obviously can't throw external.  */
   if (nothrow)
     return false;
   /* If we have an internal landing pad, then we're not external.  */
   if (lp != NULL)
     return false;
   /* If we're not within an EH region, then we are external.  */
   if (r == NULL)
     return true;
   /* The only thing that ought to be left is MUST_NOT_THROW regions,
      which don't always have landing pads.  */
   gcc_assert (r->type == ERT_MUST_NOT_THROW);
   return false;
+}
 /* Return true if INSN cannot throw at all.  */
 bool
 insn_nothrow_p (const_rtx insn)
+{
   eh_landing_pad lp;
   eh_region r;
   if (! INSN_P (insn))
     return true;
   if (NONJUMP_INSN_P (insn)
       && GET_CODE (PATTERN (insn)) == SEQUENCE)
+    {
       rtx_sequence *seq = as_a <rtx_sequence *> (PATTERN (insn));
       int i, n = seq->len ();
       for (i = 0; i < n; i++)
 	if (!insn_nothrow_p (seq->element (i)))
 	  return false;
       return true;
+    }
   return get_eh_region_and_lp_from_rtx (insn, &r, &lp);
+}
 /* Return true if INSN can perform a non-local goto.  */
 /* ??? This test is here in this file because it (ab)uses REG_EH_REGION.  */
 bool
 can_nonlocal_goto (const_rtx insn)
+{
   if (nonlocal_goto_handler_labels && CALL_P (insn))
+    {
       rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
       if (!note || INTVAL (XEXP (note, 0)) != INT_MIN)
 	return true;
+    }
   return false;
+}
 /* Set TREE_NOTHROW and crtl->all_throwers_are_sibcalls.  */
 static unsigned int
 set_nothrow_function_flags (void)
+{
   rtx_insn *insn;
   crtl->nothrow = 1;
   /* Assume crtl->all_throwers_are_sibcalls until we encounter
      something that can throw an exception.  We specifically exempt
      CALL_INSNs that are SIBLING_CALL_P, as these are really jumps,
      and can't throw.  Most CALL_INSNs are not SIBLING_CALL_P, so this
      is optimistic.  */
   crtl->all_throwers_are_sibcalls = 1;
   /* If we don't know that this implementation of the function will
      actually be used, then we must not set TREE_NOTHROW, since
      callers must not assume that this function does not throw.  */
   if (TREE_NOTHROW (current_function_decl))
     return 0;
   if (! flag_exceptions)
     return 0;
   for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
     if (can_throw_external (insn))
+      {
         crtl->nothrow = 0;
 	if (!CALL_P (insn) || !SIBLING_CALL_P (insn))
+	  {
 	    crtl->all_throwers_are_sibcalls = 0;
 	    return 0;
+	  }
+      }
   if (crtl->nothrow
       && (cgraph_node::get (current_function_decl)->get_availability ()
           >= AVAIL_AVAILABLE))
+    {
       struct cgraph_node *node = cgraph_node::get (current_function_decl);
       struct cgraph_edge *e;
       for (e = node->callers; e; e = e->next_caller)
         e->can_throw_external = false;
       node->set_nothrow_flag (true);
       if (dump_file)
 	fprintf (dump_file, "Marking function nothrow: %s\n\n",
 		 current_function_name ());
+    }
   return 0;
+}
 namespace {
 const pass_data pass_data_set_nothrow_function_flags =
+{
   RTL_PASS, /* type */
   "nothrow", /* name */
   OPTGROUP_NONE, /* optinfo_flags */
   TV_NONE, /* tv_id */
 , /* properties_required */
 , /* properties_provided */
 , /* properties_destroyed */
 , /* todo_flags_start */
 , /* todo_flags_finish */
 };
 class pass_set_nothrow_function_flags : public rtl_opt_pass
+{
 public:
   pass_set_nothrow_function_flags (gcc::context *ctxt)
     : rtl_opt_pass (pass_data_set_nothrow_function_flags, ctxt)
   {}
   /* opt_pass methods: */
   virtual unsigned int execute (function *)
+    {
       return set_nothrow_function_flags ();
+    }
 }; // class pass_set_nothrow_function_flags
 } // anon namespace
 rtl_opt_pass *
 make_pass_set_nothrow_function_flags (gcc::context *ctxt)
+{
   return new pass_set_nothrow_function_flags (ctxt);
+}
 /* Various hooks for unwind library.  */
 /* Expand the EH support builtin functions:
    __builtin_eh_pointer and __builtin_eh_filter.  */
 static eh_region
 expand_builtin_eh_common (tree region_nr_t)
+{
   HOST_WIDE_INT region_nr;
   eh_region region;
   gcc_assert (tree_fits_shwi_p (region_nr_t));
   region_nr = tree_to_shwi (region_nr_t);
   region = (*cfun->eh->region_array)[region_nr];
   /* ??? We shouldn't have been able to delete a eh region without
      deleting all the code that depended on it.  */
   gcc_assert (region != NULL);
   return region;
+}
 /* Expand to the exc_ptr value from the given eh region.  */
 rtx
 expand_builtin_eh_pointer (tree exp)
+{
   eh_region region
     = expand_builtin_eh_common (CALL_EXPR_ARG (exp, 0));
   if (region->exc_ptr_reg == NULL)
     region->exc_ptr_reg = gen_reg_rtx (ptr_mode);
   return region->exc_ptr_reg;
+}
 /* Expand to the filter value from the given eh region.  */
 rtx
 expand_builtin_eh_filter (tree exp)
+{
   eh_region region
     = expand_builtin_eh_common (CALL_EXPR_ARG (exp, 0));
   if (region->filter_reg == NULL)
     region->filter_reg = gen_reg_rtx (targetm.eh_return_filter_mode ());
   return region->filter_reg;
+}
 /* Copy the exc_ptr and filter values from one landing pad's registers
    to another.  This is used to inline the resx statement.  */
 rtx
 expand_builtin_eh_copy_values (tree exp)
+{
   eh_region dst
     = expand_builtin_eh_common (CALL_EXPR_ARG (exp, 0));
   eh_region src
     = expand_builtin_eh_common (CALL_EXPR_ARG (exp, 1));
   machine_mode fmode = targetm.eh_return_filter_mode ();
   if (dst->exc_ptr_reg == NULL)
     dst->exc_ptr_reg = gen_reg_rtx (ptr_mode);
   if (src->exc_ptr_reg == NULL)
     src->exc_ptr_reg = gen_reg_rtx (ptr_mode);
   if (dst->filter_reg == NULL)
     dst->filter_reg = gen_reg_rtx (fmode);
   if (src->filter_reg == NULL)
     src->filter_reg = gen_reg_rtx (fmode);
   emit_move_insn (dst->exc_ptr_reg, src->exc_ptr_reg);
   emit_move_insn (dst->filter_reg, src->filter_reg);
   return const0_rtx;
+}
 /* Do any necessary initialization to access arbitrary stack frames.
    On the SPARC, this means flushing the register windows.  */
 void
 expand_builtin_unwind_init (void)
+{
   /* Set this so all the registers get saved in our frame; we need to be
      able to copy the saved values for any registers from frames we unwind.  */
   crtl->saves_all_registers = 1;
 #ifdef SETUP_FRAME_ADDRESSES
   SETUP_FRAME_ADDRESSES ();
 #endif
+}
 /* Map a non-negative number to an eh return data register number; expands
    to -1 if no return data register is associated with the input number.
    At least the inputs 0 and 1 must be mapped; the target may provide more.  */
 rtx
 expand_builtin_eh_return_data_regno (tree exp)
+{
   tree which = CALL_EXPR_ARG (exp, 0);
   unsigned HOST_WIDE_INT iwhich;
   if (TREE_CODE (which) != INTEGER_CST)
+    {
       error ("argument of %<__builtin_eh_return_regno%> must be constant");
       return constm1_rtx;
+    }
   iwhich = tree_to_uhwi (which);
   iwhich = EH_RETURN_DATA_REGNO (iwhich);
   if (iwhich == INVALID_REGNUM)
     return constm1_rtx;
 #ifdef DWARF_FRAME_REGNUM
   iwhich = DWARF_FRAME_REGNUM (iwhich);
 #else
   iwhich = DBX_REGISTER_NUMBER (iwhich);
 #endif
   return GEN_INT (iwhich);
+}
 /* Given a value extracted from the return address register or stack slot,
    return the actual address encoded in that value.  */
 rtx
 expand_builtin_extract_return_addr (tree addr_tree)
+{
   rtx addr = expand_expr (addr_tree, NULL_RTX, Pmode, EXPAND_NORMAL);
   if (GET_MODE (addr) != Pmode
       && GET_MODE (addr) != VOIDmode)
+    {
 #ifdef POINTERS_EXTEND_UNSIGNED
       addr = convert_memory_address (Pmode, addr);
 #else
       addr = convert_to_mode (Pmode, addr, 0);
 #endif
+    }
   /* First mask out any unwanted bits.  */
 #ifdef MASK_RETURN_ADDR
   expand_and (Pmode, addr, MASK_RETURN_ADDR, addr);
 #endif
   /* Then adjust to find the real return address.  */
 #if defined (RETURN_ADDR_OFFSET)
   addr = plus_constant (Pmode, addr, RETURN_ADDR_OFFSET);
 #endif
   return addr;
+}
 /* Given an actual address in addr_tree, do any necessary encoding
    and return the value to be stored in the return address register or
    stack slot so the epilogue will return to that address.  */
 rtx
 expand_builtin_frob_return_addr (tree addr_tree)
+{
   rtx addr = expand_expr (addr_tree, NULL_RTX, ptr_mode, EXPAND_NORMAL);
   addr = convert_memory_address (Pmode, addr);
 #ifdef RETURN_ADDR_OFFSET
   addr = force_reg (Pmode, addr);
   addr = plus_constant (Pmode, addr, -RETURN_ADDR_OFFSET);
 #endif
   return addr;
+}
 /* Set up the epilogue with the magic bits we'll need to return to the
    exception handler.  */
 void
 expand_builtin_eh_return (tree stackadj_tree ATTRIBUTE_UNUSED,
 			  tree handler_tree)
+{
   rtx tmp;
 #ifdef EH_RETURN_STACKADJ_RTX
   tmp = expand_expr (stackadj_tree, crtl->eh.ehr_stackadj,
 		     VOIDmode, EXPAND_NORMAL);
   tmp = convert_memory_address (Pmode, tmp);
   if (!crtl->eh.ehr_stackadj)
     crtl->eh.ehr_stackadj = copy_addr_to_reg (tmp);
   else if (tmp != crtl->eh.ehr_stackadj)
     emit_move_insn (crtl->eh.ehr_stackadj, tmp);
 #endif
   tmp = expand_expr (handler_tree, crtl->eh.ehr_handler,
 		     VOIDmode, EXPAND_NORMAL);
   tmp = convert_memory_address (Pmode, tmp);
   if (!crtl->eh.ehr_handler)
     crtl->eh.ehr_handler = copy_addr_to_reg (tmp);
   else if (tmp != crtl->eh.ehr_handler)
     emit_move_insn (crtl->eh.ehr_handler, tmp);
   if (!crtl->eh.ehr_label)
     crtl->eh.ehr_label = gen_label_rtx ();
   emit_jump (crtl->eh.ehr_label);
+}
 /* Expand __builtin_eh_return.  This exit path from the function loads up
    the eh return data registers, adjusts the stack, and branches to a
    given PC other than the normal return address.  */
 void
 expand_eh_return (void)
+{
   rtx_code_label *around_label;
   if (! crtl->eh.ehr_label)
     return;
   crtl->calls_eh_return = 1;
 #ifdef EH_RETURN_STACKADJ_RTX
   emit_move_insn (EH_RETURN_STACKADJ_RTX, const0_rtx);
 #endif
   around_label = gen_label_rtx ();
   emit_jump (around_label);
   emit_label (crtl->eh.ehr_label);
   clobber_return_register ();
 #ifdef EH_RETURN_STACKADJ_RTX
   emit_move_insn (EH_RETURN_STACKADJ_RTX, crtl->eh.ehr_stackadj);
 #endif
 #ifdef HAVE_eh_return
   if (HAVE_eh_return)
     emit_insn (gen_eh_return (crtl->eh.ehr_handler));
   else
 #endif
+    {
 #ifdef EH_RETURN_HANDLER_RTX
-      emit_move_insn (EH_RETURN_HANDLER_RTX, crtl->eh.ehr_handler);
+      rtx insn = emit_move_insn (EH_RETURN_HANDLER_RTX, crtl->eh.ehr_handler);
       RTX_FRAME_RELATED_P (insn) = 1;
 #else
       error ("__builtin_eh_return not supported on this target");
 #endif
+    }
   emit_label (around_label);
+}
 /* Convert a ptr_mode address ADDR_TREE to a Pmode address controlled by
    POINTERS_EXTEND_UNSIGNED and return it.  */
 rtx
 expand_builtin_extend_pointer (tree addr_tree)
+{
   rtx addr = expand_expr (addr_tree, NULL_RTX, ptr_mode, EXPAND_NORMAL);
   int extend;
 #ifdef POINTERS_EXTEND_UNSIGNED
   extend = POINTERS_EXTEND_UNSIGNED;
 #else
   /* The previous EH code did an unsigned extend by default, so we do this also
      for consistency.  */
   extend = 1;
 #endif
   return convert_modes (targetm.unwind_word_mode (), ptr_mode, addr, extend);
+}
 static int
 add_action_record (action_hash_type *ar_hash, int filter, int next)
+{
   struct action_record **slot, *new_ar, tmp;
   tmp.filter = filter;
   tmp.next = next;
   slot = ar_hash->find_slot (&tmp, INSERT);
   if ((new_ar = *slot) == NULL)
+    {
       new_ar = XNEW (struct action_record);
       new_ar->offset = crtl->eh.action_record_data->length () + 1;
       new_ar->filter = filter;
       new_ar->next = next;
       *slot = new_ar;
       /* The filter value goes in untouched.  The link to the next
 	 record is a "self-relative" byte offset, or zero to indicate
 	 that there is no next record.  So convert the absolute 1 based
 	 indices we've been carrying around into a displacement.  */
       push_sleb128 (&crtl->eh.action_record_data, filter);
       if (next)
 	next -= crtl->eh.action_record_data->length () + 1;
       push_sleb128 (&crtl->eh.action_record_data, next);
+    }
   return new_ar->offset;
+}
 static int
 collect_one_action_chain (action_hash_type *ar_hash, eh_region region)
+{
   int next;
   /* If we've reached the top of the region chain, then we have
      no actions, and require no landing pad.  */
   if (region == NULL)
     return -1;
   switch (region->type)
+    {
     case ERT_CLEANUP:
+      {
 	eh_region r;
 	/* A cleanup adds a zero filter to the beginning of the chain, but
 	   there are special cases to look out for.  If there are *only*
 	   cleanups along a path, then it compresses to a zero action.
 	   Further, if there are multiple cleanups along a path, we only
 	   need to represent one of them, as that is enough to trigger
 	   entry to the landing pad at runtime.  */
 	next = collect_one_action_chain (ar_hash, region->outer);
 	if (next <= 0)
 	  return 0;
 	for (r = region->outer; r ; r = r->outer)
 	  if (r->type == ERT_CLEANUP)
 	    return next;
 	return add_action_record (ar_hash, 0, next);
+      }
     case ERT_TRY:
+      {
 	eh_catch c;
 	/* Process the associated catch regions in reverse order.
 	   If there's a catch-all handler, then we don't need to
 	   search outer regions.  Use a magic -3 value to record
 	   that we haven't done the outer search.  */
 	next = -3;
 	for (c = region->u.eh_try.last_catch; c ; c = c->prev_catch)
+	  {
 	    if (c->type_list == NULL)
+	      {
 		/* Retrieve the filter from the head of the filter list
 		   where we have stored it (see assign_filter_values).  */
 		int filter = TREE_INT_CST_LOW (TREE_VALUE (c->filter_list));
 		next = add_action_record (ar_hash, filter, 0);
+	      }
 	    else
+	      {
 		/* Once the outer search is done, trigger an action record for
 		   each filter we have.  */
 		tree flt_node;
 		if (next == -3)
+		  {
 		    next = collect_one_action_chain (ar_hash, region->outer);
 		    /* If there is no next action, terminate the chain.  */
 		    if (next == -1)
 		      next = 0;
 		    /* If all outer actions are cleanups or must_not_throw,
 		       we'll have no action record for it, since we had wanted
 		       to encode these states in the call-site record directly.
 		       Add a cleanup action to the chain to catch these.  */
 		    else if (next <= 0)
 		      next = add_action_record (ar_hash, 0, 0);
+		  }
 		flt_node = c->filter_list;
 		for (; flt_node; flt_node = TREE_CHAIN (flt_node))
+		  {
 		    int filter = TREE_INT_CST_LOW (TREE_VALUE (flt_node));
 		    next = add_action_record (ar_hash, filter, next);
+		  }
+	      }
+	  }
 	return next;
+      }
     case ERT_ALLOWED_EXCEPTIONS:
       /* An exception specification adds its filter to the
 	 beginning of the chain.  */
       next = collect_one_action_chain (ar_hash, region->outer);
       /* If there is no next action, terminate the chain.  */
       if (next == -1)
 	next = 0;
       /* If all outer actions are cleanups or must_not_throw,
 	 we'll have no action record for it, since we had wanted
 	 to encode these states in the call-site record directly.
 	 Add a cleanup action to the chain to catch these.  */
       else if (next <= 0)
 	next = add_action_record (ar_hash, 0, 0);
       return add_action_record (ar_hash, region->u.allowed.filter, next);
     case ERT_MUST_NOT_THROW:
       /* A must-not-throw region with no inner handlers or cleanups
 	 requires no call-site entry.  Note that this differs from
 	 the no handler or cleanup case in that we do require an lsda
 	 to be generated.  Return a magic -2 value to record this.  */
       return -2;
+    }
   gcc_unreachable ();
+}
 static int
 add_call_site (rtx landing_pad, int action, int section)
+{
   call_site_record record;
   record = ggc_alloc<call_site_record_d> ();
   record->landing_pad = landing_pad;
   record->action = action;
   vec_safe_push (crtl->eh.call_site_record_v[section], record);
   return call_site_base + crtl->eh.call_site_record_v[section]->length () - 1;
+}
 static rtx_note *
 emit_note_eh_region_end (rtx_insn *insn)
+{
   rtx_insn *next = NEXT_INSN (insn);
   /* Make sure we do not split a call and its corresponding
      CALL_ARG_LOCATION note.  */
   if (next && NOTE_P (next)
       && NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION)
     insn = next;
   return emit_note_after (NOTE_INSN_EH_REGION_END, insn);
+}
 /* Turn REG_EH_REGION notes back into NOTE_INSN_EH_REGION notes.
    The new note numbers will not refer to region numbers, but
    instead to call site entries.  */
 static unsigned int
 convert_to_eh_region_ranges (void)
+{
   rtx insn;
   rtx_insn *iter;
   rtx_note *note;
   action_hash_type ar_hash (31);
   int last_action = -3;
   rtx_insn *last_action_insn = NULL;
   rtx last_landing_pad = NULL_RTX;
   rtx_insn *first_no_action_insn = NULL;
   int call_site = 0;
   int cur_sec = 0;
   rtx section_switch_note = NULL_RTX;
   rtx_insn *first_no_action_insn_before_switch = NULL;
   rtx_insn *last_no_action_insn_before_switch = NULL;
   int saved_call_site_base = call_site_base;
   vec_alloc (crtl->eh.action_record_data, 64);
   for (iter = get_insns (); iter ; iter = NEXT_INSN (iter))
     if (INSN_P (iter))
+      {
 	eh_landing_pad lp;
 	eh_region region;
 	bool nothrow;
 	int this_action;
 	rtx this_landing_pad;
 	insn = iter;
 	if (NONJUMP_INSN_P (insn)
 	    && GET_CODE (PATTERN (insn)) == SEQUENCE)
 	  insn = XVECEXP (PATTERN (insn), 0, 0);
 	nothrow = get_eh_region_and_lp_from_rtx (insn, &region, &lp);
 	if (nothrow)
 	  continue;
 	if (region)
 	  this_action = collect_one_action_chain (&ar_hash, region);
 	else
 	  this_action = -1;
 	/* Existence of catch handlers, or must-not-throw regions
 	   implies that an lsda is needed (even if empty).  */
 	if (this_action != -1)
 	  crtl->uses_eh_lsda = 1;
 	/* Delay creation of region notes for no-action regions
 	   until we're sure that an lsda will be required.  */
 	else if (last_action == -3)
+	  {
 	    first_no_action_insn = iter;
 	    last_action = -1;
+	  }
 	if (this_action >= 0)
 	  this_landing_pad = lp->landing_pad;
 	else
 	  this_landing_pad = NULL_RTX;
 	/* Differing actions or landing pads implies a change in call-site
 	   info, which implies some EH_REGION note should be emitted.  */
 	if (last_action != this_action
 	    || last_landing_pad != this_landing_pad)
+	  {
 	    /* If there is a queued no-action region in the other section
 	       with hot/cold partitioning, emit it now.  */
 	    if (first_no_action_insn_before_switch)
+	      {
 		gcc_assert (this_action != -1
 			    && last_action == (first_no_action_insn
 					       ? -1 : -3));
 		call_site = add_call_site (NULL_RTX, 0, 0);
 		note = emit_note_before (NOTE_INSN_EH_REGION_BEG,
 					 first_no_action_insn_before_switch);
 		NOTE_EH_HANDLER (note) = call_site;
 		note
 		  = emit_note_eh_region_end (last_no_action_insn_before_switch);
 		NOTE_EH_HANDLER (note) = call_site;
 		gcc_assert (last_action != -3
 			    || (last_action_insn
 				== last_no_action_insn_before_switch));
 		first_no_action_insn_before_switch = NULL;
 		last_no_action_insn_before_switch = NULL;
 		call_site_base++;
+	      }
 	    /* If we'd not seen a previous action (-3) or the previous
 	       action was must-not-throw (-2), then we do not need an
 	       end note.  */
 	    if (last_action >= -1)
+	      {
 		/* If we delayed the creation of the begin, do it now.  */
 		if (first_no_action_insn)
+		  {
 		    call_site = add_call_site (NULL_RTX, 0, cur_sec);
 		    note = emit_note_before (NOTE_INSN_EH_REGION_BEG,
 					     first_no_action_insn);
 		    NOTE_EH_HANDLER (note) = call_site;
 		    first_no_action_insn = NULL;
+		  }
 		note = emit_note_eh_region_end (last_action_insn);
 		NOTE_EH_HANDLER (note) = call_site;
+	      }
 	    /* If the new action is must-not-throw, then no region notes
 	       are created.  */
 	    if (this_action >= -1)
+	      {
 		call_site = add_call_site (this_landing_pad,
 					   this_action < 0 ? 0 : this_action,
 					   cur_sec);
 		note = emit_note_before (NOTE_INSN_EH_REGION_BEG, iter);
 		NOTE_EH_HANDLER (note) = call_site;
+	      }
 	    last_action = this_action;
 	    last_landing_pad = this_landing_pad;
+	  }
 	last_action_insn = iter;
+      }
     else if (NOTE_P (iter)
 	     && NOTE_KIND (iter) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
+      {
 	gcc_assert (section_switch_note == NULL_RTX);
 	gcc_assert (flag_reorder_blocks_and_partition);
 	section_switch_note = iter;
 	if (first_no_action_insn)
+	  {
 	    first_no_action_insn_before_switch = first_no_action_insn;
 	    last_no_action_insn_before_switch = last_action_insn;
 	    first_no_action_insn = NULL;
 	    gcc_assert (last_action == -1);
 	    last_action = -3;
+	  }
 	/* Force closing of current EH region before section switch and
 	   opening a new one afterwards.  */
 	else if (last_action != -3)
 	  last_landing_pad = pc_rtx;
 	if (crtl->eh.call_site_record_v[cur_sec])
 	  call_site_base += crtl->eh.call_site_record_v[cur_sec]->length ();
 	cur_sec++;
 	gcc_assert (crtl->eh.call_site_record_v[cur_sec] == NULL);
 	vec_alloc (crtl->eh.call_site_record_v[cur_sec], 10);
+      }
   if (last_action >= -1 && ! first_no_action_insn)
+    {
       note = emit_note_eh_region_end (last_action_insn);
       NOTE_EH_HANDLER (note) = call_site;
+    }
   call_site_base = saved_call_site_base;
   return 0;
+}
 namespace {
 const pass_data pass_data_convert_to_eh_region_ranges =
+{
   RTL_PASS, /* type */
   "eh_ranges", /* name */
   OPTGROUP_NONE, /* optinfo_flags */
   TV_NONE, /* tv_id */
 , /* properties_required */
 , /* properties_provided */
 , /* properties_destroyed */
 , /* todo_flags_start */
 , /* todo_flags_finish */
 };
 class pass_convert_to_eh_region_ranges : public rtl_opt_pass
+{
 public:
   pass_convert_to_eh_region_ranges (gcc::context *ctxt)
     : rtl_opt_pass (pass_data_convert_to_eh_region_ranges, ctxt)
   {}
   /* opt_pass methods: */
   virtual bool gate (function *);
   virtual unsigned int execute (function *)
+    {
       return convert_to_eh_region_ranges ();
+    }
 }; // class pass_convert_to_eh_region_ranges
 bool
 pass_convert_to_eh_region_ranges::gate (function *)
+{
   /* Nothing to do for SJLJ exceptions or if no regions created.  */
   if (cfun->eh->region_tree == NULL)
     return false;
   if (targetm_common.except_unwind_info (&global_options) == UI_SJLJ)
     return false;
   return true;
+}
 } // anon namespace
 rtl_opt_pass *
 make_pass_convert_to_eh_region_ranges (gcc::context *ctxt)
+{
   return new pass_convert_to_eh_region_ranges (ctxt);
+}
 static void
 push_uleb128 (vec<uchar, va_gc> **data_area, unsigned int value)
+{
   do
+    {
       unsigned char byte = value & 0x7f;
       value >>= 7;
       if (value)
 	byte |= 0x80;
       vec_safe_push (*data_area, byte);
+    }
   while (value);
+}
 static void
 push_sleb128 (vec<uchar, va_gc> **data_area, int value)
+{
   unsigned char byte;
   int more;
   do
+    {
       byte = value & 0x7f;
       value >>= 7;
       more = ! ((value == 0 && (byte & 0x40) == 0)
 		|| (value == -1 && (byte & 0x40) != 0));
       if (more)
 	byte |= 0x80;
       vec_safe_push (*data_area, byte);
+    }
   while (more);
+}
 #ifndef HAVE_AS_LEB128
 static int
 dw2_size_of_call_site_table (int section)
+{
   int n = vec_safe_length (crtl->eh.call_site_record_v[section]);
   int size = n * (4 + 4 + 4);
   int i;
   for (i = 0; i < n; ++i)
+    {
       struct call_site_record_d *cs =
 	(*crtl->eh.call_site_record_v[section])[i];
       size += size_of_uleb128 (cs->action);
+    }
   return size;
+}
 static int
 sjlj_size_of_call_site_table (void)
+{
   int n = vec_safe_length (crtl->eh.call_site_record_v[0]);
   int size = 0;
   int i;
   for (i = 0; i < n; ++i)
+    {
       struct call_site_record_d *cs =
 	(*crtl->eh.call_site_record_v[0])[i];
       size += size_of_uleb128 (INTVAL (cs->landing_pad));
       size += size_of_uleb128 (cs->action);
+    }
   return size;
+}
 #endif
 static void
 dw2_output_call_site_table (int cs_format, int section)
+{
   int n = vec_safe_length (crtl->eh.call_site_record_v[section]);
   int i;
   const char *begin;
   if (section == 0)
     begin = current_function_func_begin_label;
   else if (first_function_block_is_cold)
     begin = crtl->subsections.hot_section_label;
   else
     begin = crtl->subsections.cold_section_label;
   for (i = 0; i < n; ++i)
+    {
       struct call_site_record_d *cs = (*crtl->eh.call_site_record_v[section])[i];
       char reg_start_lab[32];
       char reg_end_lab[32];
       char landing_pad_lab[32];
       ASM_GENERATE_INTERNAL_LABEL (reg_start_lab, "LEHB", call_site_base + i);
       ASM_GENERATE_INTERNAL_LABEL (reg_end_lab, "LEHE", call_site_base + i);
       if (cs->landing_pad)
 	ASM_GENERATE_INTERNAL_LABEL (landing_pad_lab, "L",
 				     CODE_LABEL_NUMBER (cs->landing_pad));
       /* ??? Perhaps use insn length scaling if the assembler supports
 	 generic arithmetic.  */
       /* ??? Perhaps use attr_length to choose data1 or data2 instead of
 	 data4 if the function is small enough.  */
       if (cs_format == DW_EH_PE_uleb128)
+	{
 	  dw2_asm_output_delta_uleb128 (reg_start_lab, begin,
 					"region %d start", i);
 	  dw2_asm_output_delta_uleb128 (reg_end_lab, reg_start_lab,
 					"length");
 	  if (cs->landing_pad)
 	    dw2_asm_output_delta_uleb128 (landing_pad_lab, begin,
 					  "landing pad");
 	  else
 	    dw2_asm_output_data_uleb128 (0, "landing pad");
+	}
       else
+	{
 	  dw2_asm_output_delta (4, reg_start_lab, begin,
 				"region %d start", i);
 	  dw2_asm_output_delta (4, reg_end_lab, reg_start_lab, "length");
 	  if (cs->landing_pad)
 	    dw2_asm_output_delta (4, landing_pad_lab, begin,
 				  "landing pad");
 	  else
 	    dw2_asm_output_data (4, 0, "landing pad");
+	}
       dw2_asm_output_data_uleb128 (cs->action, "action");
+    }
   call_site_base += n;
+}
 static void
 sjlj_output_call_site_table (void)
+{
   int n = vec_safe_length (crtl->eh.call_site_record_v[0]);
   int i;
   for (i = 0; i < n; ++i)
+    {
       struct call_site_record_d *cs = (*crtl->eh.call_site_record_v[0])[i];
       dw2_asm_output_data_uleb128 (INTVAL (cs->landing_pad),
 				   "region %d landing pad", i);
       dw2_asm_output_data_uleb128 (cs->action, "action");
+    }
   call_site_base += n;
+}
 /* Switch to the section that should be used for exception tables.  */
 static void
 switch_to_exception_section (const char * ARG_UNUSED (fnname))
+{
   section *s;
   if (exception_section)
     s = exception_section;
   else
+    {
       /* Compute the section and cache it into exception_section,
 	 unless it depends on the function name.  */
       if (targetm_common.have_named_sections)
+	{
 	  int flags;
 	  if (EH_TABLES_CAN_BE_READ_ONLY)
+	    {
 	      int tt_format =
 		ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/0, /*global=*/1);
 	      flags = ((! flag_pic
 			|| ((tt_format & 0x70) != DW_EH_PE_absptr
 			    && (tt_format & 0x70) != DW_EH_PE_aligned))
 		       ? 0 : SECTION_WRITE);
+	    }
 	  else
 	    flags = SECTION_WRITE;
 #ifdef HAVE_LD_EH_GC_SECTIONS
 	  if (flag_function_sections
 	      || (DECL_COMDAT_GROUP (current_function_decl) && HAVE_COMDAT_GROUP))
+	    {
 	      char *section_name = XNEWVEC (char, strlen (fnname) + 32);
 	      /* The EH table must match the code section, so only mark
 		 it linkonce if we have COMDAT groups to tie them together.  */
 	      if (DECL_COMDAT_GROUP (current_function_decl) && HAVE_COMDAT_GROUP)
 		flags |= SECTION_LINKONCE;
 	      sprintf (section_name, ".gcc_except_table.%s", fnname);
 	      s = get_section (section_name, flags, current_function_decl);
 	      free (section_name);
+	    }
 	  else
 #endif
 	    exception_section
 	      = s = get_section (".gcc_except_table", flags, NULL);
+	}
       else
 	exception_section
 	  = s = flag_pic ? data_section : readonly_data_section;
+    }
   switch_to_section (s);
+}
 /* Output a reference from an exception table to the type_info object TYPE.
    TT_FORMAT and TT_FORMAT_SIZE describe the DWARF encoding method used for
    the value.  */
 static void
 output_ttype (tree type, int tt_format, int tt_format_size)
+{
   rtx value;
   bool is_public = true;
   if (type == NULL_TREE)
     value = const0_rtx;
   else
+    {
       /* FIXME lto.  pass_ipa_free_lang_data changes all types to
 	 runtime types so TYPE should already be a runtime type
 	 reference.  When pass_ipa_free_lang data is made a default
 	 pass, we can then remove the call to lookup_type_for_runtime
 	 below.  */
       if (TYPE_P (type))
 	type = lookup_type_for_runtime (type);
       value = expand_expr (type, NULL_RTX, VOIDmode, EXPAND_INITIALIZER);
       /* Let cgraph know that the rtti decl is used.  Not all of the
 	 paths below go through assemble_integer, which would take
 	 care of this for us.  */
       STRIP_NOPS (type);
       if (TREE_CODE (type) == ADDR_EXPR)
+	{
 	  type = TREE_OPERAND (type, 0);
 	  if (TREE_CODE (type) == VAR_DECL)
 	    is_public = TREE_PUBLIC (type);
+	}
       else
 	gcc_assert (TREE_CODE (type) == INTEGER_CST);
+    }
   /* Allow the target to override the type table entry format.  */
   if (targetm.asm_out.ttype (value))
     return;
   if (tt_format == DW_EH_PE_absptr || tt_format == DW_EH_PE_aligned)
     assemble_integer (value, tt_format_size,
 		      tt_format_size * BITS_PER_UNIT, 1);
   else
     dw2_asm_output_encoded_addr_rtx (tt_format, value, is_public, NULL);
+}
 static void
 output_one_function_exception_table (int section)
+{
   int tt_format, cs_format, lp_format, i;
 #ifdef HAVE_AS_LEB128
   char ttype_label[32];
   char cs_after_size_label[32];
   char cs_end_label[32];
 #else
   int call_site_len;
 #endif
   int have_tt_data;
   int tt_format_size = 0;
   have_tt_data = (vec_safe_length (cfun->eh->ttype_data)
 		  || (targetm.arm_eabi_unwinder
 		      ? vec_safe_length (cfun->eh->ehspec_data.arm_eabi)
 		      : vec_safe_length (cfun->eh->ehspec_data.other)));
   /* Indicate the format of the @TType entries.  */
   if (! have_tt_data)
     tt_format = DW_EH_PE_omit;
   else
+    {
       tt_format = ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/0, /*global=*/1);
 #ifdef HAVE_AS_LEB128
       ASM_GENERATE_INTERNAL_LABEL (ttype_label,
 				   section ? "LLSDATTC" : "LLSDATT",
 				   current_function_funcdef_no);
 #endif
       tt_format_size = size_of_encoded_value (tt_format);
       assemble_align (tt_format_size * BITS_PER_UNIT);
+    }
   targetm.asm_out.internal_label (asm_out_file, section ? "LLSDAC" : "LLSDA",
 				  current_function_funcdef_no);
   /* The LSDA header.  */
   /* Indicate the format of the landing pad start pointer.  An omitted
      field implies @LPStart == @Start.  */
   /* Currently we always put @LPStart == @Start.  This field would
      be most useful in moving the landing pads completely out of
      line to another section, but it could also be used to minimize
      the size of uleb128 landing pad offsets.  */
   lp_format = DW_EH_PE_omit;
   dw2_asm_output_data (1, lp_format, "@LPStart format (%s)",
 		       eh_data_format_name (lp_format));
   /* @LPStart pointer would go here.  */
   dw2_asm_output_data (1, tt_format, "@TType format (%s)",
 		       eh_data_format_name (tt_format));
 #ifndef HAVE_AS_LEB128
   if (targetm_common.except_unwind_info (&global_options) == UI_SJLJ)
     call_site_len = sjlj_size_of_call_site_table ();
   else
     call_site_len = dw2_size_of_call_site_table (section);
 #endif
   /* A pc-relative 4-byte displacement to the @TType data.  */
   if (have_tt_data)
+    {
 #ifdef HAVE_AS_LEB128
       char ttype_after_disp_label[32];
       ASM_GENERATE_INTERNAL_LABEL (ttype_after_disp_label,
 				   section ? "LLSDATTDC" : "LLSDATTD",
 				   current_function_funcdef_no);
       dw2_asm_output_delta_uleb128 (ttype_label, ttype_after_disp_label,
 				    "@TType base offset");
       ASM_OUTPUT_LABEL (asm_out_file, ttype_after_disp_label);
 #else
       /* Ug.  Alignment queers things.  */
       unsigned int before_disp, after_disp, last_disp, disp;
       before_disp = 1 + 1;
       after_disp = (1 + size_of_uleb128 (call_site_len)
 		    + call_site_len
 		    + vec_safe_length (crtl->eh.action_record_data)
 		    + (vec_safe_length (cfun->eh->ttype_data)
 		       * tt_format_size));
       disp = after_disp;
       do
+	{
 	  unsigned int disp_size, pad;
 	  last_disp = disp;
 	  disp_size = size_of_uleb128 (disp);
 	  pad = before_disp + disp_size + after_disp;
 	  if (pad % tt_format_size)
 	    pad = tt_format_size - (pad % tt_format_size);
 	  else
 	    pad = 0;
 	  disp = after_disp + pad;
+	}
       while (disp != last_disp);
       dw2_asm_output_data_uleb128 (disp, "@TType base offset");
 #endif
+    }
   /* Indicate the format of the call-site offsets.  */
 #ifdef HAVE_AS_LEB128
   cs_format = DW_EH_PE_uleb128;
 #else
   cs_format = DW_EH_PE_udata4;
 #endif
   dw2_asm_output_data (1, cs_format, "call-site format (%s)",
 		       eh_data_format_name (cs_format));
 #ifdef HAVE_AS_LEB128
   ASM_GENERATE_INTERNAL_LABEL (cs_after_size_label,
 			       section ? "LLSDACSBC" : "LLSDACSB",
 			       current_function_funcdef_no);
   ASM_GENERATE_INTERNAL_LABEL (cs_end_label,
 			       section ? "LLSDACSEC" : "LLSDACSE",
 			       current_function_funcdef_no);
   dw2_asm_output_delta_uleb128 (cs_end_label, cs_after_size_label,
 				"Call-site table length");
   ASM_OUTPUT_LABEL (asm_out_file, cs_after_size_label);
   if (targetm_common.except_unwind_info (&global_options) == UI_SJLJ)
     sjlj_output_call_site_table ();
   else
     dw2_output_call_site_table (cs_format, section);
   ASM_OUTPUT_LABEL (asm_out_file, cs_end_label);
 #else
   dw2_asm_output_data_uleb128 (call_site_len, "Call-site table length");
   if (targetm_common.except_unwind_info (&global_options) == UI_SJLJ)
     sjlj_output_call_site_table ();
   else
     dw2_output_call_site_table (cs_format, section);
 #endif
   /* ??? Decode and interpret the data for flag_debug_asm.  */
+  {
     uchar uc;
     FOR_EACH_VEC_ELT (*crtl->eh.action_record_data, i, uc)
       dw2_asm_output_data (1, uc, i ? NULL : "Action record table");
+  }
   if (have_tt_data)
     assemble_align (tt_format_size * BITS_PER_UNIT);
   i = vec_safe_length (cfun->eh->ttype_data);
   while (i-- > 0)
+    {
       tree type = (*cfun->eh->ttype_data)[i];
       output_ttype (type, tt_format, tt_format_size);
+    }
 #ifdef HAVE_AS_LEB128
   if (have_tt_data)
       ASM_OUTPUT_LABEL (asm_out_file, ttype_label);
 #endif
   /* ??? Decode and interpret the data for flag_debug_asm.  */
   if (targetm.arm_eabi_unwinder)
+    {
       tree type;
       for (i = 0;
 	   vec_safe_iterate (cfun->eh->ehspec_data.arm_eabi, i, &type); ++i)
 	output_ttype (type, tt_format, tt_format_size);
+    }
   else
+    {
       uchar uc;
       for (i = 0;
 	   vec_safe_iterate (cfun->eh->ehspec_data.other, i, &uc); ++i)
 	dw2_asm_output_data (1, uc,
 			     i ? NULL : "Exception specification table");
+    }
+}
 void
 output_function_exception_table (const char *fnname)
+{
   rtx personality = get_personality_function (current_function_decl);
   /* Not all functions need anything.  */
   if (! crtl->uses_eh_lsda)
     return;
   if (personality)
+    {
       assemble_external_libcall (personality);
       if (targetm.asm_out.emit_except_personality)
 	targetm.asm_out.emit_except_personality (personality);
+    }
   switch_to_exception_section (fnname);
   /* If the target wants a label to begin the table, emit it here.  */
   targetm.asm_out.emit_except_table_label (asm_out_file);
   output_one_function_exception_table (0);
   if (crtl->eh.call_site_record_v[1])
     output_one_function_exception_table (1);
   switch_to_section (current_function_section ());
+}
 void
 set_eh_throw_stmt_table (function *fun, hash_map<gimple, int> *table)
+{
   fun->eh->throw_stmt_table = table;
+}
 hash_map<gimple, int> *
 get_eh_throw_stmt_table (struct function *fun)
+{
   return fun->eh->throw_stmt_table;
+}
 /* Determine if the function needs an EH personality function.  */
 enum eh_personality_kind
 function_needs_eh_personality (struct function *fn)
+{
   enum eh_personality_kind kind = eh_personality_none;
   eh_region i;
   FOR_ALL_EH_REGION_FN (i, fn)
+    {
       switch (i->type)
+	{
 	case ERT_CLEANUP:
 	  /* Can do with any personality including the generic C one.  */
 	  kind = eh_personality_any;
 	  break;
 	case ERT_TRY:
 	case ERT_ALLOWED_EXCEPTIONS:
 	  /* Always needs a EH personality function.  The generic C
 	     personality doesn't handle these even for empty type lists.  */
 	  return eh_personality_lang;
 	case ERT_MUST_NOT_THROW:
 	  /* Always needs a EH personality function.  The language may specify
 	     what abort routine that must be used, e.g. std::terminate.  */
 	  return eh_personality_lang;
+	}
+    }
   return kind;
+}
 /* Dump EH information to OUT.  */
 void
 dump_eh_tree (FILE * out, struct function *fun)
+{
   eh_region i;
   int depth = 0;
   static const char *const type_name[] = {
     "cleanup", "try", "allowed_exceptions", "must_not_throw"
   };
   i = fun->eh->region_tree;
   if (!i)
     return;
   fprintf (out, "Eh tree:\n");
   while (1)
+    {
       fprintf (out, "  %*s %i %s", depth * 2, "",
 	       i->index, type_name[(int) i->type]);
       if (i->landing_pads)
+	{
 	  eh_landing_pad lp;
 	  fprintf (out, " land:");
 	  if (current_ir_type () == IR_GIMPLE)
+	    {
 	      for (lp = i->landing_pads; lp ; lp = lp->next_lp)
+		{
 		  fprintf (out, "{%i,", lp->index);
 		  print_generic_expr (out, lp->post_landing_pad, 0);
 		  fputc ('}', out);
 		  if (lp->next_lp)
 		    fputc (',', out);
+		}
+	    }
 	  else
+	    {
 	      for (lp = i->landing_pads; lp ; lp = lp->next_lp)
+		{
 		  fprintf (out, "{%i,", lp->index);
 		  if (lp->landing_pad)
 		    fprintf (out, "%i%s,", INSN_UID (lp->landing_pad),
 			     NOTE_P (lp->landing_pad) ? "(del)" : "");
 		  else
 		    fprintf (out, "(nil),");
 		  if (lp->post_landing_pad)
+		    {
 		      rtx lab = label_rtx (lp->post_landing_pad);
 		      fprintf (out, "%i%s}", INSN_UID (lab),
 			       NOTE_P (lab) ? "(del)" : "");
+		    }
 		  else
 		    fprintf (out, "(nil)}");
 		  if (lp->next_lp)
 		    fputc (',', out);
+		}
+	    }
+	}
       switch (i->type)
+	{
 	case ERT_CLEANUP:
 	case ERT_MUST_NOT_THROW:
 	  break;
 	case ERT_TRY:
+	  {
 	    eh_catch c;
 	    fprintf (out, " catch:");
 	    for (c = i->u.eh_try.first_catch; c; c = c->next_catch)
+	      {
 		fputc ('{', out);
 		if (c->label)
+		  {
 		    fprintf (out, "lab:");
 		    print_generic_expr (out, c->label, 0);
 		    fputc (';', out);
+		  }
 		print_generic_expr (out, c->type_list, 0);
 		fputc ('}', out);
 		if (c->next_catch)
 		  fputc (',', out);
+	      }
+	  }
 	  break;

 @@ -1,1197 +1,1198 @@
 /* Subroutines for insn-output.c for VAX.
    Copyright (C) 1987-2015 Free Software Foundation, Inc.
 This file is part of GCC.
 GCC is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 3, or (at your option)
 any later version.
 GCC is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 You should have received a copy of the GNU General Public License
 along with GCC; see the file COPYING3.  If not see
 <http://www.gnu.org/licenses/>.  */
 #include "config.h"
 #include "system.h"
 #include "coretypes.h"
 #include "tm.h"
 #include "rtl.h"
 #include "dominance.h"
 #include "cfg.h"
 #include "cfgrtl.h"
 #include "cfganal.h"
 #include "lcm.h"
 #include "cfgbuild.h"
 #include "cfgcleanup.h"
 #include "predict.h"
 #include "basic-block.h"
 #include "df.h"
 #include "hash-set.h"
 #include "machmode.h"
 #include "vec.h"
 #include "double-int.h"
 #include "input.h"
 #include "alias.h"
 #include "symtab.h"
 #include "wide-int.h"
 #include "inchash.h"
 #include "tree.h"
 #include "calls.h"
 #include "varasm.h"
 #include "regs.h"
 #include "hard-reg-set.h"
 #include "insn-config.h"
 #include "conditions.h"
 #include "function.h"
 #include "output.h"
 #include "insn-attr.h"
 #include "recog.h"
 #include "hashtab.h"
 #include "flags.h"
 #include "statistics.h"
 #include "real.h"
 #include "fixed-value.h"
 #include "expmed.h"
 #include "dojump.h"
 #include "explow.h"
 #include "emit-rtl.h"
 #include "stmt.h"
 #include "expr.h"
 #include "insn-codes.h"
 #include "optabs.h"
 #include "debug.h"
 #include "diagnostic-core.h"
 #include "reload.h"
 #include "tm-preds.h"
 #include "tm-constrs.h"
 #include "tm_p.h"
 #include "target.h"
 #include "target-def.h"
 #include "builtins.h"
 static void vax_option_override (void);
 static bool vax_legitimate_address_p (machine_mode, rtx, bool);
 static void vax_file_start (void);
 static void vax_init_libfuncs (void);
 static void vax_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
 				 HOST_WIDE_INT, tree);
 static int vax_address_cost_1 (rtx);
 static int vax_address_cost (rtx, machine_mode, addr_space_t, bool);
 static bool vax_rtx_costs (rtx, int, int, int, int *, bool);
 static rtx vax_function_arg (cumulative_args_t, machine_mode,
 			     const_tree, bool);
 static void vax_function_arg_advance (cumulative_args_t, machine_mode,
 				      const_tree, bool);
 static rtx vax_struct_value_rtx (tree, int);
 static rtx vax_builtin_setjmp_frame_value (void);
 static void vax_asm_trampoline_template (FILE *);
 static void vax_trampoline_init (rtx, tree, rtx);
 static int vax_return_pops_args (tree, tree, int);
 static bool vax_mode_dependent_address_p (const_rtx, addr_space_t);
 /* Initialize the GCC target structure.  */
 #undef TARGET_ASM_ALIGNED_HI_OP
 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
 #undef TARGET_ASM_FILE_START
 #define TARGET_ASM_FILE_START vax_file_start
 #undef TARGET_ASM_FILE_START_APP_OFF
 #define TARGET_ASM_FILE_START_APP_OFF true
 #undef TARGET_INIT_LIBFUNCS
 #define TARGET_INIT_LIBFUNCS vax_init_libfuncs
 #undef TARGET_ASM_OUTPUT_MI_THUNK
 #define TARGET_ASM_OUTPUT_MI_THUNK vax_output_mi_thunk
 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
 #undef TARGET_RTX_COSTS
 #define TARGET_RTX_COSTS vax_rtx_costs
 #undef TARGET_ADDRESS_COST
 #define TARGET_ADDRESS_COST vax_address_cost
 #undef TARGET_PROMOTE_PROTOTYPES
 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
 #undef TARGET_FUNCTION_ARG
 #define TARGET_FUNCTION_ARG vax_function_arg
 #undef TARGET_FUNCTION_ARG_ADVANCE
 #define TARGET_FUNCTION_ARG_ADVANCE vax_function_arg_advance
 #undef TARGET_STRUCT_VALUE_RTX
 #define TARGET_STRUCT_VALUE_RTX vax_struct_value_rtx
 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE vax_builtin_setjmp_frame_value
 #undef TARGET_LEGITIMATE_ADDRESS_P
 #define TARGET_LEGITIMATE_ADDRESS_P vax_legitimate_address_p
 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
 #define TARGET_MODE_DEPENDENT_ADDRESS_P vax_mode_dependent_address_p
 #undef TARGET_FRAME_POINTER_REQUIRED
 #define TARGET_FRAME_POINTER_REQUIRED hook_bool_void_true
 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
 #define TARGET_ASM_TRAMPOLINE_TEMPLATE vax_asm_trampoline_template
 #undef TARGET_TRAMPOLINE_INIT
 #define TARGET_TRAMPOLINE_INIT vax_trampoline_init
 #undef TARGET_RETURN_POPS_ARGS
 #define TARGET_RETURN_POPS_ARGS vax_return_pops_args
 #undef TARGET_OPTION_OVERRIDE
 #define TARGET_OPTION_OVERRIDE vax_option_override
 struct gcc_target targetm = TARGET_INITIALIZER;
 /* Set global variables as needed for the options enabled.  */
 static void
 vax_option_override (void)
+{
   /* We're VAX floating point, not IEEE floating point.  */
   if (TARGET_G_FLOAT)
     REAL_MODE_FORMAT (DFmode) = &vax_g_format;
 #ifdef SUBTARGET_OVERRIDE_OPTIONS
   SUBTARGET_OVERRIDE_OPTIONS;
 #endif
+}
 static void
 vax_add_reg_cfa_offset (rtx insn, int offset, rtx src)
+{
   rtx x;
   x = plus_constant (Pmode, frame_pointer_rtx, offset);
   x = gen_rtx_MEM (SImode, x);
   x = gen_rtx_SET (VOIDmode, x, src);
   add_reg_note (insn, REG_CFA_OFFSET, x);
+}
 /* Generate the assembly code for function entry.  FILE is a stdio
    stream to output the code to.  SIZE is an int: how many units of
    temporary storage to allocate.
    Refer to the array `regs_ever_live' to determine which registers to
    save; `regs_ever_live[I]' is nonzero if register number I is ever
    used in the function.  This function is responsible for knowing
    which registers should not be saved even if used.  */
 void
 vax_expand_prologue (void)
+{
   int regno, offset;
   int mask = 0;
   HOST_WIDE_INT size;
   rtx insn;
   offset = 20;
   for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
-    if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
+    if ((df_regs_ever_live_p (regno) && !call_used_regs[regno])
 	|| (crtl->calls_eh_return && regno >= 2 && regno < 4))
+      {
         mask |= 1 << regno;
         offset += 4;
+      }
   insn = emit_insn (gen_procedure_entry_mask (GEN_INT (mask)));
   RTX_FRAME_RELATED_P (insn) = 1;
   /* The layout of the CALLG/S stack frame is follows:
 		<- CFA, AP
 	r11
 	r10
 	...	Registers saved as specified by MASK
 	r3
 	r2
 	return-addr
 	old fp
 	old ap
 	old psw
 	zero
 		<- FP, SP
      The rest of the prologue will adjust the SP for the local frame.  */
   add_reg_note (insn, REG_CFA_DEF_CFA,
                 plus_constant (Pmode, frame_pointer_rtx, offset));
   insn = emit_insn (gen_blockage ());
   RTX_FRAME_RELATED_P (insn) = 1;
   vax_add_reg_cfa_offset (insn, 4, gen_rtx_REG (Pmode, PSW_REGNUM));
   vax_add_reg_cfa_offset (insn, 8, arg_pointer_rtx);
   vax_add_reg_cfa_offset (insn, 12, frame_pointer_rtx);
   vax_add_reg_cfa_offset (insn, 16, pc_rtx);
   offset = 20;
   for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
     if (mask & (1 << regno))
+      {
 	vax_add_reg_cfa_offset (insn, offset, gen_rtx_REG (SImode, regno));
 	offset += 4;
+      }
   /* Allocate the local stack frame.  */
   size = get_frame_size ();
   size -= STARTING_FRAME_OFFSET;
   emit_insn (gen_addsi3 (stack_pointer_rtx,
 			 stack_pointer_rtx, GEN_INT (-size)));
   /* Do not allow instructions referencing local stack memory to be
      scheduled before the frame is allocated.  This is more pedantic
      than anything else, given that VAX does not currently have a
      scheduling description.  */
   emit_insn (gen_blockage ());
+}
 /* When debugging with stabs, we want to output an extra dummy label
    so that gas can distinguish between D_float and G_float prior to
    processing the .stabs directive identifying type double.  */
 static void
 vax_file_start (void)
+{
   default_file_start ();
   if (write_symbols == DBX_DEBUG)
     fprintf (asm_out_file, "___vax_%c_doubles:\n", ASM_DOUBLE_CHAR);
+}
 /* We can use the BSD C library routines for the libgcc calls that are
    still generated, since that's what they boil down to anyways.  When
    ELF, avoid the user's namespace.  */
 static void
 vax_init_libfuncs (void)
+{
   if (TARGET_BSD_DIVMOD)
+    {
       set_optab_libfunc (udiv_optab, SImode, TARGET_ELF ? "*__udiv" : "*udiv");
       set_optab_libfunc (umod_optab, SImode, TARGET_ELF ? "*__urem" : "*urem");
+    }
+}
 /* This is like nonimmediate_operand with a restriction on the type of MEM.  */
 static void
 split_quadword_operands (rtx insn, enum rtx_code code, rtx * operands,
 			 rtx * low, int n)
+{
   int i;
   for (i = 0; i < n; i++)
     low[i] = 0;
   for (i = 0; i < n; i++)
+    {
       if (MEM_P (operands[i])
 	  && (GET_CODE (XEXP (operands[i], 0)) == PRE_DEC
 	      || GET_CODE (XEXP (operands[i], 0)) == POST_INC))
+	{
 	  rtx addr = XEXP (operands[i], 0);
 	  operands[i] = low[i] = gen_rtx_MEM (SImode, addr);
+	}
       else if (optimize_size && MEM_P (operands[i])
 	       && REG_P (XEXP (operands[i], 0))
 	       && (code != MINUS || operands[1] != const0_rtx)
 	       && find_regno_note (insn, REG_DEAD,
 				   REGNO (XEXP (operands[i], 0))))
+	{
 	  low[i] = gen_rtx_MEM (SImode,
 				gen_rtx_POST_INC (Pmode,
 						  XEXP (operands[i], 0)));
 	  operands[i] = gen_rtx_MEM (SImode, XEXP (operands[i], 0));
+	}
       else
+	{
 	  low[i] = operand_subword (operands[i], 0, 0, DImode);
 	  operands[i] = operand_subword (operands[i], 1, 0, DImode);
+	}
+    }
+}
 void
 print_operand_address (FILE * file, rtx addr)
+{
   rtx orig = addr;
   rtx reg1, breg, ireg;
   rtx offset;
  retry:
   switch (GET_CODE (addr))
+    {
     case MEM:
       fprintf (file, "*");
       addr = XEXP (addr, 0);
       goto retry;
     case REG:
       fprintf (file, "(%s)", reg_names[REGNO (addr)]);
       break;
     case PRE_DEC:
       fprintf (file, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]);
       break;
     case POST_INC:
       fprintf (file, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]);
       break;
     case PLUS:
       /* There can be either two or three things added here.  One must be a
 	 REG.  One can be either a REG or a MULT of a REG and an appropriate
 	 constant, and the third can only be a constant or a MEM.
 	 We get these two or three things and put the constant or MEM in
 	 OFFSET, the MULT or REG in IREG, and the REG in BREG.  If we have
 	 a register and can't tell yet if it is a base or index register,
 	 put it into REG1.  */
       reg1 = 0; ireg = 0; breg = 0; offset = 0;
       if (CONSTANT_ADDRESS_P (XEXP (addr, 0))
 	  || MEM_P (XEXP (addr, 0)))
+	{
 	  offset = XEXP (addr, 0);
 	  addr = XEXP (addr, 1);
+	}
       else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))
 	       || MEM_P (XEXP (addr, 1)))
+	{
 	  offset = XEXP (addr, 1);
 	  addr = XEXP (addr, 0);
+	}
       else if (GET_CODE (XEXP (addr, 1)) == MULT)
+	{
 	  ireg = XEXP (addr, 1);
 	  addr = XEXP (addr, 0);
+	}
       else if (GET_CODE (XEXP (addr, 0)) == MULT)
+	{
 	  ireg = XEXP (addr, 0);
 	  addr = XEXP (addr, 1);
+	}
       else if (REG_P (XEXP (addr, 1)))
+	{
 	  reg1 = XEXP (addr, 1);
 	  addr = XEXP (addr, 0);
+	}
       else if (REG_P (XEXP (addr, 0)))
+	{
 	  reg1 = XEXP (addr, 0);
 	  addr = XEXP (addr, 1);
+	}
       else
+	{
 	   debug_rtx (orig);
 	   gcc_unreachable ();
+	}
       if (REG_P (addr))
+	{
 	  if (reg1)
 	    ireg = addr;
 	  else
 	    reg1 = addr;
+	}
       else if (GET_CODE (addr) == MULT)
 	ireg = addr;
       else if (GET_CODE (addr) == PLUS)
+	{
 	  if (CONSTANT_ADDRESS_P (XEXP (addr, 0))
 	      || MEM_P (XEXP (addr, 0)))
+	    {
 	      if (offset)
+		{
 		  if (CONST_INT_P (offset))
 		    offset = plus_constant (Pmode, XEXP (addr, 0),
 		                            INTVAL (offset));
 		  else
+		    {
 		      gcc_assert (CONST_INT_P (XEXP (addr, 0)));
 		      offset = plus_constant (Pmode, offset,
 					      INTVAL (XEXP (addr, 0)));
+		    }
+		}
 	      offset = XEXP (addr, 0);
+	    }
 	  else if (REG_P (XEXP (addr, 0)))
+	    {
 	      if (reg1)
 		ireg = reg1, breg = XEXP (addr, 0), reg1 = 0;
 	      else
 		reg1 = XEXP (addr, 0);
+	    }
 	  else if (GET_CODE (XEXP (addr, 0)) == MULT && !ireg)
+	    {
 	      ireg = XEXP (addr, 0);
+	    }
 	  else
+	    {
 	      debug_rtx (orig);
 	      gcc_unreachable ();
+	    }
 	  if (CONSTANT_ADDRESS_P (XEXP (addr, 1))
 	      || MEM_P (XEXP (addr, 1)))
+	    {
 	      if (offset)
+		{
 		  if (CONST_INT_P (offset))
 		    offset = plus_constant (Pmode, XEXP (addr, 1),
 					    INTVAL (offset));
 		  else
+		    {
 		      gcc_assert (CONST_INT_P (XEXP (addr, 1)));
 		      offset = plus_constant (Pmode, offset,
 					      INTVAL (XEXP (addr, 1)));
+		    }
+		}
 	      offset = XEXP (addr, 1);
+	    }
 	  else if (REG_P (XEXP (addr, 1)))
+	    {
 	      if (reg1)
 		ireg = reg1, breg = XEXP (addr, 1), reg1 = 0;
 	      else
 		reg1 = XEXP (addr, 1);
+	    }
 	  else if (GET_CODE (XEXP (addr, 1)) == MULT && !ireg)
+	    {
 	      ireg = XEXP (addr, 1);
+	    }
 	  else
+	    {
 	      debug_rtx (orig);
 	      gcc_unreachable ();
+	    }
+	}
       else
+	{
 	  debug_rtx (orig);
 	  gcc_unreachable ();
+	}
       /* If REG1 is nonzero, figure out if it is a base or index register.  */
       if (reg1)
+	{
 	  if (breg
 	      || (flag_pic && GET_CODE (addr) == SYMBOL_REF)
 	      || (offset
 		  && (MEM_P (offset)
 		      || (flag_pic && symbolic_operand (offset, SImode)))))
+	    {
 	      if (ireg)
+		{
 		  debug_rtx (orig);
 		  gcc_unreachable ();
+		}
 	      ireg = reg1;
+	    }
 	  else
 	    breg = reg1;
+	}
       if (offset != 0)
+	{
 	  if (flag_pic && symbolic_operand (offset, SImode))
+	    {
 	      if (breg && ireg)
+		{
 		  debug_rtx (orig);
 		  output_operand_lossage ("symbol used with both base and indexed registers");
+		}
 #ifdef NO_EXTERNAL_INDIRECT_ADDRESS
 	      if (flag_pic > 1 && GET_CODE (offset) == CONST
 		  && GET_CODE (XEXP (XEXP (offset, 0), 0)) == SYMBOL_REF
 		  && !SYMBOL_REF_LOCAL_P (XEXP (XEXP (offset, 0), 0)))
+		{
 		  debug_rtx (orig);
 		  output_operand_lossage ("symbol with offset used in PIC mode");
+		}
 #endif
 	      /* symbol(reg) isn't PIC, but symbol[reg] is.  */
 	      if (breg)
+		{
 		  ireg = breg;
 		  breg = 0;
+		}
+	    }
 	  output_address (offset);
+	}
       if (breg != 0)
 	fprintf (file, "(%s)", reg_names[REGNO (breg)]);
       if (ireg != 0)
+	{
 	  if (GET_CODE (ireg) == MULT)
 	    ireg = XEXP (ireg, 0);
 	  if (! REG_P (ireg))
+	    {
 	      debug_rtx (orig);
 	      output_operand_lossage ("non-register index expression");
+	    }
 	  fprintf (file, "[%s]", reg_names[REGNO (ireg)]);
+	}
       break;
     default:
       gcc_assert (! REG_P(addr));
       output_addr_const (file, addr);
+    }
+}
 void
 print_operand (FILE *file, rtx x, int code)
+{
   if (code == '#')
     fputc (ASM_DOUBLE_CHAR, file);
   else if (code == '|')
     fputs (REGISTER_PREFIX, file);
   else if (code == 'c')
     fputs (cond_name (x), file);
   else if (code == 'C')
     fputs (rev_cond_name (x), file);
   else if (code == 'D' && CONST_INT_P (x) && INTVAL (x) < 0)
     fprintf (file, "$" NEG_HWI_PRINT_HEX16, INTVAL (x));
   else if (code == 'P' && CONST_INT_P (x))
     fprintf (file, "$" HOST_WIDE_INT_PRINT_DEC, INTVAL (x) + 1);
   else if (code == 'N' && CONST_INT_P (x))
     fprintf (file, "$" HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
   /* rotl instruction cannot deal with negative arguments.  */
   else if (code == 'R' && CONST_INT_P (x))
     fprintf (file, "$" HOST_WIDE_INT_PRINT_DEC, 32 - INTVAL (x));
   else if (code == 'H' && CONST_INT_P (x))
     fprintf (file, "$%d", (int) (0xffff & ~ INTVAL (x)));
   else if (code == 'h' && CONST_INT_P (x))
     fprintf (file, "$%d", (short) - INTVAL (x));
   else if (code == 'B' && CONST_INT_P (x))
     fprintf (file, "$%d", (int) (0xff & ~ INTVAL (x)));
   else if (code == 'b' && CONST_INT_P (x))
     fprintf (file, "$%d", (int) (0xff & - INTVAL (x)));
   else if (code == 'M' && CONST_INT_P (x))
     fprintf (file, "$%d", ~((1 << INTVAL (x)) - 1));
   else if (code == 'x' && CONST_INT_P (x))
     fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
   else if (REG_P (x))
     fprintf (file, "%s", reg_names[REGNO (x)]);
   else if (MEM_P (x))
     output_address (XEXP (x, 0));
   else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
+    {
       char dstr[30];
       real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x),
 		       sizeof (dstr), 0, 1);
       fprintf (file, "$0f%s", dstr);
+    }
   else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
+    {
       char dstr[30];
       real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x),
 		       sizeof (dstr), 0, 1);
       fprintf (file, "$0%c%s", ASM_DOUBLE_CHAR, dstr);
+    }
   else if (GET_CODE (x) == SUBREG)
+    {
       debug_rtx (x);
       output_operand_lossage ("SUBREG operand");
+    }
   else
+    {
       if (flag_pic > 1 && symbolic_operand (x, SImode))
+	{
 	  debug_rtx (x);
 	  output_operand_lossage ("symbol used as immediate operand");
+	}
       putc ('$', file);
       output_addr_const (file, x);
+    }
+}
 const char *
 cond_name (rtx op)
+{
   switch (GET_CODE (op))
+    {
     case NE:
       return "neq";
     case EQ:
       return "eql";
     case GE:
       return "geq";
     case GT:
       return "gtr";
     case LE:
       return "leq";
     case LT:
       return "lss";
     case GEU:
       return "gequ";
     case GTU:
       return "gtru";
     case LEU:
       return "lequ";
     case LTU:
       return "lssu";
     default:
       gcc_unreachable ();
+    }
+}
 const char *
 rev_cond_name (rtx op)
+{
   switch (GET_CODE (op))
+    {
     case EQ:
       return "neq";
     case NE:
       return "eql";
     case LT:
       return "geq";
     case LE:
       return "gtr";
     case GT:
       return "leq";
     case GE:
       return "lss";
     case LTU:
       return "gequ";
     case LEU:
       return "gtru";
     case GTU:
       return "lequ";
     case GEU:
       return "lssu";
     default:
       gcc_unreachable ();
+    }
+}
 static bool
 vax_float_literal (rtx c)
+{
   machine_mode mode;
   REAL_VALUE_TYPE r, s;
   int i;
   if (GET_CODE (c) != CONST_DOUBLE)
     return false;
   mode = GET_MODE (c);
   if (c == const_tiny_rtx[(int) mode][0]
       || c == const_tiny_rtx[(int) mode][1]
       || c == const_tiny_rtx[(int) mode][2])
     return true;
   REAL_VALUE_FROM_CONST_DOUBLE (r, c);
   for (i = 0; i < 7; i++)
+    {
       int x = 1 << i;
       bool ok;
       real_from_integer (&s, mode, x, SIGNED);
       if (REAL_VALUES_EQUAL (r, s))
 	return true;
       ok = exact_real_inverse (mode, &s);
       gcc_assert (ok);
       if (REAL_VALUES_EQUAL (r, s))
 	return true;
+    }
   return false;
+}
 /* Return the cost in cycles of a memory address, relative to register
    indirect.
    Each of the following adds the indicated number of cycles:
 - symbolic address
 - pre-decrement
 - indexing and/or offset(register)
 - indirect */
 static int
 vax_address_cost_1 (rtx addr)
+{
   int reg = 0, indexed = 0, indir = 0, offset = 0, predec = 0;
   rtx plus_op0 = 0, plus_op1 = 0;
  restart:
   switch (GET_CODE (addr))
+    {
     case PRE_DEC:
       predec = 1;
     case REG:
     case SUBREG:
     case POST_INC:
       reg = 1;
       break;
     case MULT:
       indexed = 1;	/* 2 on VAX 2 */
       break;
     case CONST_INT:
       /* byte offsets cost nothing (on a VAX 2, they cost 1 cycle) */
       if (offset == 0)
 	offset = (unsigned HOST_WIDE_INT)(INTVAL(addr)+128) > 256;
       break;
     case CONST:
     case SYMBOL_REF:
       offset = 1;	/* 2 on VAX 2 */
       break;
     case LABEL_REF:	/* this is probably a byte offset from the pc */
       if (offset == 0)
 	offset = 1;
       break;
     case PLUS:
       if (plus_op0)
 	plus_op1 = XEXP (addr, 0);
       else
 	plus_op0 = XEXP (addr, 0);
       addr = XEXP (addr, 1);
       goto restart;
     case MEM:
       indir = 2;	/* 3 on VAX 2 */
       addr = XEXP (addr, 0);
       goto restart;
     default:
       break;
+    }
   /* Up to 3 things can be added in an address.  They are stored in
      plus_op0, plus_op1, and addr.  */
   if (plus_op0)
+    {
       addr = plus_op0;
       plus_op0 = 0;
       goto restart;
+    }
   if (plus_op1)
+    {
       addr = plus_op1;
       plus_op1 = 0;
       goto restart;
+    }
   /* Indexing and register+offset can both be used (except on a VAX 2)
      without increasing execution time over either one alone.  */
   if (reg && indexed && offset)
     return reg + indir + offset + predec;
   return reg + indexed + indir + offset + predec;
+}
 static int
 vax_address_cost (rtx x, machine_mode mode ATTRIBUTE_UNUSED,
 		  addr_space_t as ATTRIBUTE_UNUSED,
 		  bool speed ATTRIBUTE_UNUSED)
+{
   return (1 + (REG_P (x) ? 0 : vax_address_cost_1 (x)));
+}
 /* Cost of an expression on a VAX.  This version has costs tuned for the
    CVAX chip (found in the VAX 3 series) with comments for variations on
    other models.
    FIXME: The costs need review, particularly for TRUNCATE, FLOAT_EXTEND
    and FLOAT_TRUNCATE.  We need a -mcpu option to allow provision of
    costs on a per cpu basis.  */
 static bool
 vax_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
 	       int *total, bool speed ATTRIBUTE_UNUSED)
+{
   machine_mode mode = GET_MODE (x);
   int i = 0;				   /* may be modified in switch */
   const char *fmt = GET_RTX_FORMAT (code); /* may be modified in switch */
   switch (code)
+    {
       /* On a VAX, constants from 0..63 are cheap because they can use the
 byte literal constant format.  Compare to -1 should be made cheap
 	 so that decrement-and-branch insns can be formed more easily (if
 	 the value -1 is copied to a register some decrement-and-branch
 	 patterns will not match).  */
     case CONST_INT:
       if (INTVAL (x) == 0)
+	{
 	  *total = 0;
 	  return true;
+	}
       if (outer_code == AND)
+	{
 	  *total = ((unsigned HOST_WIDE_INT) ~INTVAL (x) <= 077) ? 1 : 2;
 	  return true;
+	}
       if ((unsigned HOST_WIDE_INT) INTVAL (x) <= 077
 	  || (outer_code == COMPARE
 	      && INTVAL (x) == -1)
 	  || ((outer_code == PLUS || outer_code == MINUS)
 	      && (unsigned HOST_WIDE_INT) -INTVAL (x) <= 077))
+	{
 	  *total = 1;
 	  return true;
+	}
       /* FALLTHRU */
     case CONST:
     case LABEL_REF:
     case SYMBOL_REF:
       *total = 3;
       return true;
     case CONST_DOUBLE:
       if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
 	*total = vax_float_literal (x) ? 5 : 8;
       else
 	*total = ((CONST_DOUBLE_HIGH (x) == 0
 		   && (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (x) < 64)
 		  || (outer_code == PLUS
 		      && CONST_DOUBLE_HIGH (x) == -1
 		      && (unsigned HOST_WIDE_INT)-CONST_DOUBLE_LOW (x) < 64))
 		 ? 2 : 5;
       return true;
     case POST_INC:
       *total = 2;
       return true;		/* Implies register operand.  */
     case PRE_DEC:
       *total = 3;
       return true;		/* Implies register operand.  */
     case MULT:
       switch (mode)
+	{
 	case DFmode:
 	  *total = 16;		/* 4 on VAX 9000 */
 	  break;
 	case SFmode:
 	  *total = 9;		/* 4 on VAX 9000, 12 on VAX 2 */
 	  break;
 	case DImode:
 	  *total = 16;		/* 6 on VAX 9000, 28 on VAX 2 */
 	  break;
 	case SImode:
 	case HImode:
 	case QImode:
 	  *total = 10;		/* 3-4 on VAX 9000, 20-28 on VAX 2 */
 	  break;
 	default:
 	  *total = MAX_COST;	/* Mode is not supported.  */
 	  return true;
+	}
       break;
     case UDIV:
       if (mode != SImode)
+	{
 	  *total = MAX_COST;	/* Mode is not supported.  */
 	  return true;
+	}
       *total = 17;
       break;
     case DIV:
       if (mode == DImode)
 	*total = 30;		/* Highly variable.  */
       else if (mode == DFmode)
 	/* divide takes 28 cycles if the result is not zero, 13 otherwise */
 	*total = 24;
       else
 	*total = 11;		/* 25 on VAX 2 */
       break;
     case MOD:
       *total = 23;
       break;
     case UMOD:
       if (mode != SImode)
+	{
 	  *total = MAX_COST;	/* Mode is not supported.  */
 	  return true;
+	}
       *total = 29;
       break;
     case FLOAT:
       *total = (6		/* 4 on VAX 9000 */
 		+ (mode == DFmode) + (GET_MODE (XEXP (x, 0)) != SImode));
       break;
     case FIX:
       *total = 7;		/* 17 on VAX 2 */
       break;
     case ASHIFT:
     case LSHIFTRT:
     case ASHIFTRT:
       if (mode == DImode)
 	*total = 12;
       else
 	*total = 10;		/* 6 on VAX 9000 */
       break;
     case ROTATE:
     case ROTATERT:
       *total = 6;		/* 5 on VAX 2, 4 on VAX 9000 */
       if (CONST_INT_P (XEXP (x, 1)))
 	fmt = "e"; 		/* all constant rotate counts are short */
       break;
     case PLUS:
     case MINUS:
       *total = (mode == DFmode) ? 13 : 8; /* 6/8 on VAX 9000, 16/15 on VAX 2 */
       /* Small integer operands can use subl2 and addl2.  */
       if ((CONST_INT_P (XEXP (x, 1)))
 	  && (unsigned HOST_WIDE_INT)(INTVAL (XEXP (x, 1)) + 63) < 127)
 	fmt = "e";
       break;
     case IOR:
     case XOR:
       *total = 3;
       break;
     case AND:
       /* AND is special because the first operand is complemented.  */
       *total = 3;
       if (CONST_INT_P (XEXP (x, 0)))
+	{
 	  if ((unsigned HOST_WIDE_INT)~INTVAL (XEXP (x, 0)) > 63)
 	    *total = 4;
 	  fmt = "e";
 	  i = 1;
+	}
       break;
     case NEG:
       if (mode == DFmode)
 	*total = 9;
       else if (mode == SFmode)
 	*total = 6;
       else if (mode == DImode)
 	*total = 4;
       else
 	*total = 2;
       break;
     case NOT:
       *total = 2;
       break;
     case ZERO_EXTRACT:
     case SIGN_EXTRACT:
       *total = 15;
       break;
     case MEM:
       if (mode == DImode || mode == DFmode)
 	*total = 5;		/* 7 on VAX 2 */
       else
 	*total = 3;		/* 4 on VAX 2 */
       x = XEXP (x, 0);
       if (!REG_P (x) && GET_CODE (x) != POST_INC)
 	*total += vax_address_cost_1 (x);
       return true;
     case FLOAT_EXTEND:
     case FLOAT_TRUNCATE:
     case TRUNCATE:
       *total = 3;		/* FIXME: Costs need to be checked  */
       break;
     default:
       return false;
+    }
   /* Now look inside the expression.  Operands which are not registers or
      short constants add to the cost.
      FMT and I may have been adjusted in the switch above for instructions
      which require special handling.  */
   while (*fmt++ == 'e')
+    {
       rtx op = XEXP (x, i);
       i += 1;
       code = GET_CODE (op);
       /* A NOT is likely to be found as the first operand of an AND
 	 (in which case the relevant cost is of the operand inside
 	 the not) and not likely to be found anywhere else.  */
       if (code == NOT)
 	op = XEXP (op, 0), code = GET_CODE (op);
       switch (code)
+	{
 	case CONST_INT:
 	  if ((unsigned HOST_WIDE_INT)INTVAL (op) > 63
 	      && GET_MODE (x) != QImode)
 	    *total += 1;	/* 2 on VAX 2 */
 	  break;
 	case CONST:
 	case LABEL_REF:
 	case SYMBOL_REF:
 	  *total += 1;		/* 2 on VAX 2 */
 	  break;
 	case CONST_DOUBLE:
 	  if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT)
+	    {
 	      /* Registers are faster than floating point constants -- even
 		 those constants which can be encoded in a single byte.  */
 	      if (vax_float_literal (op))
 		*total += 1;
 	      else
 		*total += (GET_MODE (x) == DFmode) ? 3 : 2;
+	    }
 	  else
+	    {
 	      if (CONST_DOUBLE_HIGH (op) != 0
 		  || (unsigned HOST_WIDE_INT)CONST_DOUBLE_LOW (op) > 63)
 		*total += 2;
+	    }
 	  break;
 	case MEM:
 	  *total += 1;		/* 2 on VAX 2 */
 	  if (!REG_P (XEXP (op, 0)))
 	    *total += vax_address_cost_1 (XEXP (op, 0));
 	  break;
 	case REG:
 	case SUBREG:
 	  break;
 	default:
 	  *total += 1;
 	  break;
+	}
+    }
   return true;
+}
 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
    Used for C++ multiple inheritance.
 	.mask	^m<r2,r3,r4,r5,r6,r7,r8,r9,r10,r11>  #conservative entry mask
 	addl2	$DELTA, 4(ap)	#adjust first argument
 	jmp	FUNCTION+2	#jump beyond FUNCTION's entry mask
 */
 static void
 vax_output_mi_thunk (FILE * file,
 		     tree thunk ATTRIBUTE_UNUSED,
 		     HOST_WIDE_INT delta,
 		     HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
 		     tree function)
+{
   fprintf (file, "\t.word 0x0ffc\n\taddl2 $" HOST_WIDE_INT_PRINT_DEC, delta);
   asm_fprintf (file, ",4(%Rap)\n");
   fprintf (file, "\tjmp ");
   assemble_name (file,  XSTR (XEXP (DECL_RTL (function), 0), 0));
   fprintf (file, "+2\n");
+}
 static rtx
 vax_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
 		      int incoming ATTRIBUTE_UNUSED)
+{
   return gen_rtx_REG (Pmode, VAX_STRUCT_VALUE_REGNUM);
+}
 static rtx
 vax_builtin_setjmp_frame_value (void)
+{
   return hard_frame_pointer_rtx;
+}
 /* Worker function for NOTICE_UPDATE_CC.  */
 void
 vax_notice_update_cc (rtx exp, rtx insn ATTRIBUTE_UNUSED)
+{
   if (GET_CODE (exp) == SET)
+    {
       if (GET_CODE (SET_SRC (exp)) == CALL)
 	CC_STATUS_INIT;
       else if (GET_CODE (SET_DEST (exp)) != ZERO_EXTRACT
 	       && GET_CODE (SET_DEST (exp)) != PC)
+	{
 	  cc_status.flags = 0;
 	  /* The integer operations below don't set carry or
 	     set it in an incompatible way.  That's ok though
 	     as the Z bit is all we need when doing unsigned
 	     comparisons on the result of these insns (since
 	     they're always with 0).  Set CC_NO_OVERFLOW to
 	     generate the correct unsigned branches.  */
 	  switch (GET_CODE (SET_SRC (exp)))
+	    {
 	    case NEG:
 	      if (GET_MODE_CLASS (GET_MODE (exp)) == MODE_FLOAT)
 		break;
 	    case AND:
 	    case IOR:
 	    case XOR:
 	    case NOT:
 	    case CTZ:
 	    case MEM:
 	    case REG:
 	      cc_status.flags = CC_NO_OVERFLOW;
 	      break;
 	    default:
 	      break;
+	    }
 	  cc_status.value1 = SET_DEST (exp);
 	  cc_status.value2 = SET_SRC (exp);
+	}
+    }
   else if (GET_CODE (exp) == PARALLEL
 	   && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
+    {
       if (GET_CODE (SET_SRC (XVECEXP (exp, 0, 0))) == CALL)
 	CC_STATUS_INIT;
       else if (GET_CODE (SET_DEST (XVECEXP (exp, 0, 0))) != PC)
+	{
 	  cc_status.flags = 0;
 	  cc_status.value1 = SET_DEST (XVECEXP (exp, 0, 0));
 	  cc_status.value2 = SET_SRC (XVECEXP (exp, 0, 0));
+	}
       else
 	/* PARALLELs whose first element sets the PC are aob,
 	   sob insns.  They do change the cc's.  */
 	CC_STATUS_INIT;
+    }
   else
     CC_STATUS_INIT;
   if (cc_status.value1 && REG_P (cc_status.value1)
       && cc_status.value2
       && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
     cc_status.value2 = 0;
   if (cc_status.value1 && MEM_P (cc_status.value1)
       && cc_status.value2
       && MEM_P (cc_status.value2))
     cc_status.value2 = 0;
   /* Actual condition, one line up, should be that value2's address
      depends on value1, but that is too much of a pain.  */
+}
 /* Output integer move instructions.  */
 const char *
 vax_output_int_move (rtx insn ATTRIBUTE_UNUSED, rtx *operands,
 		     machine_mode mode)

 @@ -1,716 +1,716 @@
 /* Definitions of target machine for GNU compiler.  VAX version.
    Copyright (C) 1987-2015 Free Software Foundation, Inc.
 This file is part of GCC.
 GCC is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 3, or (at your option)
 any later version.
 GCC is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 You should have received a copy of the GNU General Public License
 along with GCC; see the file COPYING3.  If not see
 <http://www.gnu.org/licenses/>.  */
 #include "vax-protos.h"
 /* Target CPU builtins.  */
 #define TARGET_CPU_CPP_BUILTINS()		\
   do						\
     {						\
       builtin_define ("__vax__");		\
       builtin_assert ("cpu=vax");		\
       builtin_assert ("machine=vax");		\
       if (TARGET_G_FLOAT)			\
 	{					\
 	  builtin_define ("__GFLOAT");		\
 	  builtin_define ("__GFLOAT__");	\
 	}					\
     }						\
   while (0)
 /* Use -J option for long branch support with Unix assembler.  */
 #define ASM_SPEC "-J"
 /* Choose proper libraries depending on float format.
    Note that there are no profiling libraries for g-format.
    Also use -lg for the sake of dbx.  */
 #define LIB_SPEC "%{g:-lg}\
  %{mg:%{lm:-lmg} -lcg \
   %{p:%eprofiling not supported with -mg\n}\
   %{pg:%eprofiling not supported with -mg\n}}\
  %{!mg:%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}}"
 /* Run-time compilation parameters selecting different hardware subsets.  */
 /* Nonzero if ELF.  Redefined by vax/elf.h.  */
 #define TARGET_ELF 0
 /* Use BSD names for udiv and umod libgcc calls.  */
 #define TARGET_BSD_DIVMOD 1
 /* Default target_flags if no switches specified.  */
 #ifndef TARGET_DEFAULT
 #define TARGET_DEFAULT (MASK_UNIX_ASM)
 #endif
 /* Target machine storage layout */
 /* Define this if most significant bit is lowest numbered
    in instructions that operate on numbered bit-fields.
    This is not true on the VAX.  */
 #define BITS_BIG_ENDIAN 0
 /* Define this if most significant byte of a word is the lowest numbered.  */
 /* That is not true on the VAX.  */
 #define BYTES_BIG_ENDIAN 0
 /* Define this if most significant word of a multiword number is the lowest
    numbered.  */
 /* This is not true on the VAX.  */
 #define WORDS_BIG_ENDIAN 0
 /* Width of a word, in units (bytes).  */
 #define UNITS_PER_WORD 4
 /* Allocation boundary (in *bits*) for storing arguments in argument list.  */
 #define PARM_BOUNDARY 32
 /* Allocation boundary (in *bits*) for the code of a function.  */
 #define FUNCTION_BOUNDARY 16
 /* Alignment of field after `int : 0' in a structure.  */
 #define EMPTY_FIELD_BOUNDARY (TARGET_VAXC_ALIGNMENT ? 8 : 32)
 /* Every structure's size must be a multiple of this.  */
 #define STRUCTURE_SIZE_BOUNDARY 8
 /* A bit-field declared as `int' forces `int' alignment for the struct.  */
 #define PCC_BITFIELD_TYPE_MATTERS (! TARGET_VAXC_ALIGNMENT)
 /* No data type wants to be aligned rounder than this.  */
 #define BIGGEST_ALIGNMENT 32
 /* No structure field wants to be aligned rounder than this.  */
 #define BIGGEST_FIELD_ALIGNMENT (TARGET_VAXC_ALIGNMENT ? 8 : 32)
 /* Set this nonzero if move instructions will actually fail to work
    when given unaligned data.  */
 #define STRICT_ALIGNMENT 0
 /* Let's keep the stack somewhat aligned.  */
 #define STACK_BOUNDARY 32
 /* The table of an ADDR_DIFF_VEC must be contiguous with the case
    opcode, it is part of the case instruction.  */
 #define ADDR_VEC_ALIGN(ADDR_VEC) 0
 /* Standard register usage.  */
 /* Number of actual hardware registers.
    The hardware registers are assigned numbers for the compiler
    from 0 to just below FIRST_PSEUDO_REGISTER.
    All registers that the compiler knows about must be given numbers,
    even those that are not normally considered general registers.  */
 #define FIRST_PSEUDO_REGISTER 16
 /* 1 for registers that have pervasive standard uses
    and are not available for the register allocator.
    On the VAX, these are the AP, FP, SP and PC.  */
 #define FIXED_REGISTERS {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1}
 /* 1 for registers not available across function calls.
    These must include the FIXED_REGISTERS and also any
    registers that can be used without being saved.
    The latter must include the registers where values are returned
    and the register where structure-value addresses are passed.
    Aside from that, you can include as many other registers as you like.  */
 #define CALL_USED_REGISTERS {1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1}
 /* Return number of consecutive hard regs needed starting at reg REGNO
    to hold something of mode MODE.
    This is ordinarily the length in words of a value of mode MODE
    but can be less for certain modes in special long registers.
    On the VAX, all registers are one word long.  */
 #define HARD_REGNO_NREGS(REGNO, MODE)	\
   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
    On the VAX, all registers can hold all modes.  */
 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
 /* Value is 1 if it is a good idea to tie two pseudo registers
    when one has mode MODE1 and one has mode MODE2.
    If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
    for any hard reg, then this must be 0 for correct output.  */
 #define MODES_TIEABLE_P(MODE1, MODE2)  1
 /* Specify the registers used for certain standard purposes.
    The values of these macros are register numbers.  */
 /* VAX PSW for DWARF-2 */
 #define PSW_REGNUM VAX_PSW_REGNUM
 /* VAX pc is overloaded on a register.  */
 #define PC_REGNUM VAX_PC_REGNUM
 /* Register to use for pushing function arguments.  */
 #define STACK_POINTER_REGNUM VAX_SP_REGNUM
 /* Base register for access to local variables of the function.  */
 #define FRAME_POINTER_REGNUM VAX_FP_REGNUM
 /* Offset from the frame pointer register value to the top of stack.  */
 #define FRAME_POINTER_CFA_OFFSET(FNDECL) 0
 /* Base register for access to arguments of the function.  */
 #define ARG_POINTER_REGNUM VAX_AP_REGNUM
 /* Offset from the argument pointer register value to the CFA.  */
 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
 /* Register in which static-chain is passed to a function.  */
 #define STATIC_CHAIN_REGNUM 0
 /* Register in which address to store a structure value
    is passed to a function.  */
 #define VAX_STRUCT_VALUE_REGNUM 1
 /* Define the classes of registers for register constraints in the
    machine description.  Also define ranges of constants.
    One of the classes must always be named ALL_REGS and include all hard regs.
    If there is more than one class, another class must be named NO_REGS
    and contain no registers.
    The name GENERAL_REGS must be the name of a class (or an alias for
    another name such as ALL_REGS).  This is the class of registers
    that is allowed by "g" or "r" in a register constraint.
    Also, registers outside this class are allocated only when
    instructions express preferences for them.
    The classes must be numbered in nondecreasing order; that is,
    a larger-numbered class must never be contained completely
    in a smaller-numbered class.
    For any two classes, it is very desirable that there be another
    class that represents their union.  */
 /* The VAX has only one kind of registers, so NO_REGS and ALL_REGS
    are the only classes.  */
 enum reg_class { NO_REGS, ALL_REGS, LIM_REG_CLASSES };
 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 /* Since GENERAL_REGS is the same class as ALL_REGS,
    don't give it a different class number; just make it an alias.  */
 #define GENERAL_REGS ALL_REGS
 /* Give names of register classes as strings for dump file.  */
 #define REG_CLASS_NAMES	\
   { "NO_REGS", "ALL_REGS" }
 /* Define which registers fit in which classes.
    This is an initializer for a vector of HARD_REG_SET
    of length N_REG_CLASSES.  */
 #define REG_CLASS_CONTENTS {{0}, {0xffff}}
 /* The same information, inverted:
    Return the class number of the smallest class containing
    reg number REGNO.  This could be a conditional expression
    or could index an array.  */
 #define REGNO_REG_CLASS(REGNO) ALL_REGS
 /* The class value for index registers, and the one for base regs.  */
 #define INDEX_REG_CLASS ALL_REGS
 #define BASE_REG_CLASS ALL_REGS
 /* Stack layout; function entry, exit and calling.  */
 /* Define this if pushing a word on the stack
    makes the stack pointer a smaller address.  */
 #define STACK_GROWS_DOWNWARD
 /* Define this to nonzero if the nominal address of the stack frame
    is at the high-address end of the local variables;
    that is, each additional local variable allocated
    goes at a more negative offset in the frame.  */
 #define FRAME_GROWS_DOWNWARD 1
 /* Offset within stack frame to start allocating local variables at.
    If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
    first local allocated.  Otherwise, it is the offset to the BEGINNING
    of the first local allocated.  */
 #define STARTING_FRAME_OFFSET 0
 /* Given an rtx for the address of a frame,
    return an rtx for the address of the word in the frame
    that holds the dynamic chain--the previous frame's address.  */
 #define DYNAMIC_CHAIN_ADDRESS(FRAME) plus_constant (Pmode, (FRAME), 12)
 /* If we generate an insn to push BYTES bytes,
    this says how many the stack pointer really advances by.
    On the VAX, -(sp) pushes only the bytes of the operands.  */
 #define PUSH_ROUNDING(BYTES) (BYTES)
 /* Offset of first parameter from the argument pointer register value.  */
 #define FIRST_PARM_OFFSET(FNDECL) 4
 /* Define how to find the value returned by a function.
    VALTYPE is the data type of the value (as a tree).
    If the precise function being called is known, FUNC is its FUNCTION_DECL;
    otherwise, FUNC is 0.  */
 /* On the VAX the return value is in R0 regardless.  */
 #define FUNCTION_VALUE(VALTYPE, FUNC)	\
   gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
 /* Define how to find the value returned by a library function
    assuming the value has mode MODE.  */
 /* On the VAX the return value is in R0 regardless.  */
 #define LIBCALL_VALUE(MODE)  gen_rtx_REG (MODE, 0)
 /* Define this if PCC uses the nonreentrant convention for returning
    structure and union values.  */
 #define PCC_STATIC_STRUCT_RETURN
 /* 1 if N is a possible register number for a function value.
    On the VAX, R0 is the only register thus used.  */
 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
 /* 1 if N is a possible register number for function argument passing.
    On the VAX, no registers are used in this way.  */
 #define FUNCTION_ARG_REGNO_P(N) ((void) (N), 0)
 /* Define a data type for recording info about an argument list
    during the scan of that argument list.  This data type should
    hold all necessary information about the function itself
    and about the args processed so far, enough to enable macros
    such as FUNCTION_ARG to determine where the next arg should go.
    On the VAX, this is a single integer, which is a number of bytes
    of arguments scanned so far.  */
 #define CUMULATIVE_ARGS int
 /* Initialize a variable CUM of type CUMULATIVE_ARGS
    for a call to a function whose data type is FNTYPE.
    For a library call, FNTYPE is 0.
    On the VAX, the offset starts at 0.  */
 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
  ((CUM) = 0)
 /* Output assembler code to FILE to increment profiler label # LABELNO
    for profiling a function entry.  */
 #define VAX_FUNCTION_PROFILER_NAME "mcount"
 #define FUNCTION_PROFILER(FILE, LABELNO)			\
   do								\
     {								\
       char label[256];						\
       ASM_GENERATE_INTERNAL_LABEL (label, "LP", (LABELNO));	\
       fprintf (FILE, "\tmovab ");				\
       assemble_name (FILE, label);				\
       asm_fprintf (FILE, ",%Rr0\n\tjsb %s\n",			\
 		   VAX_FUNCTION_PROFILER_NAME);			\
     }								\
   while (0)
 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
    the stack pointer does not matter.  The value is tested only in
    functions that have frame pointers.
    No definition is equivalent to always zero.  */
 #define EXIT_IGNORE_STACK 1
 /* Store in the variable DEPTH the initial difference between the
    frame pointer reg contents and the stack pointer reg contents,
    as of the start of the function body.  This depends on the layout
    of the fixed parts of the stack frame and on how registers are saved.
    On the VAX, FRAME_POINTER_REQUIRED is always 1, so the definition of this
    macro doesn't matter.  But it must be defined.  */
 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = 0;
 /* Length in units of the trampoline for entering a nested function.  */
 #define TRAMPOLINE_SIZE 15
 /* Byte offset of return address in a stack frame.  The "saved PC" field
    is in element [4] when treating the frame as an array of longwords.  */
 #define RETURN_ADDRESS_OFFSET	(4 * UNITS_PER_WORD)	/* 16 */
 /* A C expression whose value is RTL representing the value of the return
    address for the frame COUNT steps up from the current frame.
    FRAMEADDR is already the frame pointer of the COUNT frame, so we
    can ignore COUNT.  */
 #define RETURN_ADDR_RTX(COUNT, FRAME)					\
   ((COUNT == 0)								\
    ? gen_rtx_MEM (Pmode, plus_constant (Pmode, FRAME,			\
 					RETURN_ADDRESS_OFFSET))		\
    : (rtx) 0)
 /* A C expression that is nonzero if X is a legitimate immediate operand
    on the target machine when generating position independent code.  */
 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
 /* Addressing modes, and classification of registers for them.  */
 #define HAVE_POST_INCREMENT 1
 #define HAVE_PRE_DECREMENT 1
 /* Macros to check register numbers against specific register classes.  */
 /* These assume that REGNO is a hard or pseudo reg number.
    They give nonzero only if REGNO is a hard reg of the suitable class
    or a pseudo reg currently allocated to a suitable hard reg.
    Since they use reg_renumber, they are safe only once reg_renumber
    has been allocated, which happens in reginfo.c during register
    allocation.  */
 #define REGNO_OK_FOR_INDEX_P(regno)	\
   ((regno) < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0)
 #define REGNO_OK_FOR_BASE_P(regno)	\
   ((regno) < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0)
 /* Maximum number of registers that can appear in a valid memory address.  */
 #define MAX_REGS_PER_ADDRESS 2
 /* 1 if X is an rtx for a constant that is a valid address.  */
 #define CONSTANT_ADDRESS_P(X) legitimate_constant_address_p (X)
 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
    and check its validity for a certain class.
    We have two alternate definitions for each of them.
    The usual definition accepts all pseudo regs; the other rejects
    them unless they have been allocated suitable hard regs.
    The symbol REG_OK_STRICT causes the latter definition to be used.
    Most source files want to accept pseudo regs in the hope that
    they will get allocated to the class that the insn wants them to be in.
    Source files for reload pass need to be strict.
    After reload, it makes no difference, since pseudo regs have
    been eliminated by then.  */
 #ifndef REG_OK_STRICT
 /* Nonzero if X is a hard reg that can be used as an index
    or if it is a pseudo reg.  */
 #define REG_OK_FOR_INDEX_P(X) 1
 /* Nonzero if X is a hard reg that can be used as a base reg
    or if it is a pseudo reg.  */
 #define REG_OK_FOR_BASE_P(X) 1
 #else
 /* Nonzero if X is a hard reg that can be used as an index.  */
 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
 /* Nonzero if X is a hard reg that can be used as a base reg.  */
 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
 #endif
 /* Specify the machine mode that this machine uses
    for the index in the tablejump instruction.  */
 #define CASE_VECTOR_MODE HImode
 /* Define as C expression which evaluates to nonzero if the tablejump
    instruction expects the table to contain offsets from the address of the
    table.
    Do not define this if the table should contain absolute addresses.  */
 #define CASE_VECTOR_PC_RELATIVE 1
 /* Indicate that jump tables go in the text section.  This is
    necessary when compiling PIC code.  */
 #define JUMP_TABLES_IN_TEXT_SECTION 1
 /* Define this as 1 if `char' should by default be signed; else as 0.  */
 #define DEFAULT_SIGNED_CHAR 1
 /* Max number of bytes we can move from memory to memory
    in one reasonably fast instruction.  */
 #define MOVE_MAX 8
 /* If a memory-to-memory move would take MOVE_RATIO or more simple
    move-instruction pairs, we will do a movmem or libcall instead.  */
 #define MOVE_RATIO(speed) ((speed) ? 6 : 3)
 #define CLEAR_RATIO(speed) ((speed) ? 6 : 2)
 /* Nonzero if access to memory by bytes is slow and undesirable.  */
 #define SLOW_BYTE_ACCESS 0
 /* Define if shifts truncate the shift count
    which implies one can omit a sign-extension or zero-extension
    of a shift count.  */
 /* #define SHIFT_COUNT_TRUNCATED */
 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
    is done just by pretending it is already truncated.  */
 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
 /* Specify the machine mode that pointers have.
    After generation of rtl, the compiler makes no further distinction
    between pointers and any other objects of this machine mode.  */
 #define Pmode SImode
 /* A function address in a call instruction
    is a byte address (for indexing purposes)
    so give the MEM rtx a byte's mode.  */
 #define FUNCTION_MODE QImode
 /* Specify the cost of a branch insn; roughly the number of extra insns that
    should be added to avoid a branch.
    Branches are extremely cheap on the VAX while the shift insns often
    used to replace branches can be expensive.  */
 #define BRANCH_COST(speed_p, predictable_p) 0
 /* Tell final.c how to eliminate redundant test instructions.  */
 /* Here we define machine-dependent flags and fields in cc_status
    (see `conditions.h').  No extra ones are needed for the VAX.  */
 /* Store in cc_status the expressions
    that the condition codes will describe
    after execution of an instruction whose pattern is EXP.
    Do not alter them if the instruction would not alter the cc's.  */
 #define NOTICE_UPDATE_CC(EXP, INSN)	\
   vax_notice_update_cc ((EXP), (INSN))
 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV)	\
   { if (cc_status.flags & CC_NO_OVERFLOW)	\
       return NO_OV;				\
     return NORMAL;				\
+  }
 /* Control the assembler format that we output.  */
 /* A C string constant describing how to begin a comment in the target
    assembler language.  The compiler assumes that the comment will end at
    the end of the line.  */
 #define ASM_COMMENT_START "#"
 /* Output to assembler file text saying following lines
    may contain character constants, extra white space, comments, etc.  */
 #define ASM_APP_ON "#APP\n"
 /* Output to assembler file text saying following lines
    no longer contain unusual constructs.  */
 #define ASM_APP_OFF "#NO_APP\n"
 /* Output before read-only data.  */
 #define TEXT_SECTION_ASM_OP "\t.text"
 /* Output before writable data.  */
 #define DATA_SECTION_ASM_OP "\t.data"
 /* How to refer to registers in assembler output.
    This sequence is indexed by compiler's hard-register-number (see above).
    The register names will be prefixed by REGISTER_PREFIX, if any.  */
 #define REGISTER_PREFIX ""
 #define REGISTER_NAMES					\
   { "r0", "r1",  "r2",  "r3", "r4", "r5", "r6", "r7",	\
     "r8", "r9", "r10", "r11", "ap", "fp", "sp", "pc", }
 /* This is BSD, so it wants DBX format.  */
 #define DBX_DEBUGGING_INFO 1
 /* Do not break .stabs pseudos into continuations.  */
 #define DBX_CONTIN_LENGTH 0
 /* This is the char to use for continuation (in case we need to turn
    continuation back on).  */
 #define DBX_CONTIN_CHAR '?'
 /* Don't use the `xsfoo;' construct in DBX output; this system
    doesn't support it.  */
 #define DBX_NO_XREFS
 /* Output the .stabs for a C `static' variable in the data section.  */
 #define DBX_STATIC_STAB_DATA_SECTION
 /* VAX specific: which type character is used for type double?  */
 #define ASM_DOUBLE_CHAR (TARGET_G_FLOAT ? 'g' : 'd')
 /* This is how to output a command to make the user-level label named NAME
    defined for reference from other files.  */
 /* Globalizing directive for a label.  */
 #define GLOBAL_ASM_OP ".globl "
 /* The prefix to add to user-visible assembler symbols.  */
 #define USER_LABEL_PREFIX "_"
 /* This is how to store into the string LABEL
    the symbol_ref name of an internal numbered label where
    PREFIX is the class of label and NUM is the number within the class.
    This is suitable for output with `assemble_name'.  */
 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
   sprintf (LABEL, "*%s%ld", PREFIX, (long)(NUM))
 /* This is how to output an insn to push a register on the stack.
    It need not be very fast code.  */
 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
   fprintf (FILE, "\tpushl %s\n", reg_names[REGNO])
 /* This is how to output an insn to pop a register from the stack.
    It need not be very fast code.  */
 #define ASM_OUTPUT_REG_POP(FILE,REGNO)					\
   fprintf (FILE, "\tmovl (%s)+,%s\n", reg_names[STACK_POINTER_REGNUM],	\
 	   reg_names[REGNO])
 /* This is how to output an element of a case-vector that is absolute.
    (The VAX does not use such vectors,
    but we must define this macro anyway.)  */
 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)		\
   do							\
     {							\
       char label[256];					\
       ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE));\
       fprintf (FILE, "\t.long ");			\
       assemble_name (FILE, label);			\
       fprintf (FILE, "\n");				\
     }							\
   while (0)
 /* This is how to output an element of a case-vector that is relative.  */
 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)	\
   do								\
     {								\
       char label[256];						\
       ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE));	\
       fprintf (FILE, "\t.word ");				\
       assemble_name (FILE, label);				\
       ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL));		\
       fprintf (FILE, "-");					\
       assemble_name (FILE, label);				\
       fprintf (FILE, "\n");					\
     }								\
   while (0)
 /* This is how to output an assembler line
    that says to advance the location counter
    to a multiple of 2**LOG bytes.  */
 #define ASM_OUTPUT_ALIGN(FILE,LOG)  \
   fprintf (FILE, "\t.align %d\n", (LOG))
 /* This is how to output an assembler line
    that says to advance the location counter by SIZE bytes.  */
 #define ASM_OUTPUT_SKIP(FILE,SIZE)  \
   fprintf (FILE, "\t.space %u\n", (int)(SIZE))
 /* This says how to output an assembler line
    to define a global common symbol.  */
 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)	\
   ( fputs (".comm ", (FILE)),				\
     assemble_name ((FILE), (NAME)),			\
     fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
 /* This says how to output an assembler line
    to define a local common symbol.  */
 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)	\
   ( fputs (".lcomm ", (FILE)),				\
     assemble_name ((FILE), (NAME)),			\
     fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
 /* Print an instruction operand X on file FILE.
    CODE is the code from the %-spec that requested printing this operand;
    if `%z3' was used to print operand 3, then CODE is 'z'.
 VAX operand formatting codes:
  letter	   print
    c	direct branch condition
    C	reverse branch condition
    D	64-bit immediate operand
    B	the low 8 bits of the complement of a constant operand
    H	the low 16 bits of the complement of a constant operand
    M	a mask for the N highest bits of a word
    N	the complement of a constant integer operand
    P	constant operand plus 1
    R	32 - constant operand
    b	the low 8 bits of a negated constant operand
    h	the low 16 bits of a negated constant operand
    #	'd' or 'g' depending on whether dfloat or gfloat is used
    |	register prefix  */
 /* The purpose of D is to get around a quirk or bug in VAX assembler
    whereby -1 in a 64-bit immediate operand means 0x00000000ffffffff,
    which is not a 64-bit minus one.  As a workaround, we output negative
    values in hex.  */
 #if HOST_BITS_PER_WIDE_INT == 64
 #  define NEG_HWI_PRINT_HEX16 HOST_WIDE_INT_PRINT_HEX
 #else
 #  define NEG_HWI_PRINT_HEX16 "0xffffffff%08lx"
 #endif
 #define PRINT_OPERAND_PUNCT_VALID_P(CODE)  \
   ((CODE) == '#' || (CODE) == '|')
 #define PRINT_OPERAND(FILE, X, CODE)  \
   print_operand (FILE, X, CODE)
 /* Print a memory operand whose address is X, on file FILE.
    This uses a function in output-vax.c.  */
 #define PRINT_OPERAND_ADDRESS(FILE, ADDR)  \
   print_operand_address (FILE, ADDR)
 /* This is a blatent lie.  However, it's good enough, since we don't
    actually have any code whatsoever for which this isn't overridden
    by the proper FDE definition.  */
 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, PC_REGNUM)

 @@ -1,1728 +1,1700 @@
 ;; Machine description for GNU compiler, VAX Version
 ;; Copyright (C) 1987-2015 Free Software Foundation, Inc.
 ;; This file is part of GCC.
 ;; GCC is free software; you can redistribute it and/or modify
 ;; it under the terms of the GNU General Public License as published by
 ;; the Free Software Foundation; either version 3, or (at your option)
 ;; any later version.
 ;; GCC is distributed in the hope that it will be useful,
 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ;; GNU General Public License for more details.
 ;; You should have received a copy of the GNU General Public License
 ;; along with GCC; see the file COPYING3.  If not see
 ;; <http://www.gnu.org/licenses/>.
 ;; Note that operand 1 is total size of args, in bytes,
 ;; and what the call insn wants is the number of words.
 ;; It is used in the call instruction as a byte, but in the addl2 as
 ;; a word.  Since the only time we actually use it in the call instruction
 ;; is when it is a constant, SImode (for addl2) is the proper mode.
 ;;- Instruction patterns.  When multiple patterns apply,
 ;;- the first one in the file is chosen.
 ;;-
 ;;- See file "rtl.def" for documentation on define_insn, match_*, et al.
 ;;-
 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
 ;;- updates for most instructions.
 ;; UNSPEC_VOLATILE usage:
 (define_c_enum "unspecv" [
   VUNSPEC_BLOCKAGE 	    ; 'blockage' insn to prevent scheduling across an
 			    ; insn in the code.
   VUNSPEC_SYNC_ISTREAM      ; sequence of insns to sync the I-stream
   VUNSPEC_PEM		    ; 'procedure_entry_mask' insn.
 ])
 (define_constants
   [(VAX_AP_REGNUM 12)	    ; Register 12 contains the argument pointer
    (VAX_FP_REGNUM 13)	    ; Register 13 contains the frame pointer
    (VAX_SP_REGNUM 14)	    ; Register 14 contains the stack pointer
    (VAX_PC_REGNUM 15)	    ; Register 15 contains the program counter
    (VAX_PSW_REGNUM 16)	    ; Program Status Word
+  ]
+)
 ;; Integer modes supported on VAX, with a mapping from machine mode
 ;; to mnemonic suffix.  DImode is always a special case.
 (define_mode_iterator VAXint [QI HI SI])
 (define_mode_iterator VAXintQH [QI HI])
 (define_mode_iterator VAXintQHSD [QI HI SI DI])
 (define_mode_attr  isfx [(QI "b") (HI "w") (SI "l") (DI "q")])
 ;; Similar for float modes supported on VAX.
 (define_mode_iterator VAXfp [SF DF])
 (define_mode_attr  fsfx [(SF "f") (DF "%#")])
 ;; Some output patterns want integer immediates with a prefix...
 (define_mode_attr  iprefx [(QI "B") (HI "H") (SI "N")])
 ;;
 (include "constraints.md")
 (include "predicates.md")
 (define_insn "*cmp<mode>"
   [(set (cc0)
 	(compare (match_operand:VAXint 0 "nonimmediate_operand" "nrmT,nrmT")
 		 (match_operand:VAXint 1 "general_operand" "I,nrmT")))]
   ""
   "@
    tst<VAXint:isfx> %0
    cmp<VAXint:isfx> %0,%1")
 (define_insn "*cmp<mode>"
   [(set (cc0)
 	(compare (match_operand:VAXfp 0 "general_operand" "gF,gF")
 		 (match_operand:VAXfp 1 "general_operand" "G,gF")))]
   ""
   "@
    tst<VAXfp:fsfx> %0
    cmp<VAXfp:fsfx> %0,%1")
 (define_insn "*bit<mode>"
   [(set (cc0)
 	(compare (and:VAXint (match_operand:VAXint 0 "general_operand" "nrmT")
 			     (match_operand:VAXint 1 "general_operand" "nrmT"))
 		 (const_int 0)))]
   ""
   "bit<VAXint:isfx> %0,%1")
 ;; The VAX has no sCOND insns.  It does have add/subtract with carry
 ;; which could be used to implement the sltu and sgeu patterns.  However,
 ;; to do this properly requires a complete rewrite of the compare insns
 ;; to keep them together with the sltu/sgeu insns until after the
 ;; reload pass is complete.  The previous implementation didn't do this
 ;; and has been deleted.
 (define_insn "mov<mode>"
   [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
 	(match_operand:VAXfp 1 "general_operand" "G,gF"))]
   ""
   "@
    clr<VAXfp:fsfx> %0
    mov<VAXfp:fsfx> %1,%0")
 ;; Some VAXen don't support this instruction.
 ;;(define_insn "movti"
 ;;  [(set (match_operand:TI 0 "general_operand" "=g")
 ;;	(match_operand:TI 1 "general_operand" "g"))]
 ;;  ""
 ;;  "movh %1,%0")
 (define_insn "movdi"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
 	(match_operand:DI 1 "general_operand" "g"))]
   ""
   "* return vax_output_int_move (insn, operands, DImode);")
 ;; The VAX move instructions have space-time tradeoffs.  On a MicroVAX
 ;; register-register mov instructions take 3 bytes and 2 CPU cycles.  clrl
 ;; takes 2 bytes and 3 cycles.  mov from constant to register takes 2 cycles
 ;; if the constant is smaller than 4 bytes, 3 cycles for a longword
 ;; constant.  movz, mneg, and mcom are as fast as mov, so movzwl is faster
 ;; than movl for positive constants that fit in 16 bits but not 6 bits.  cvt
 ;; instructions take 4 cycles.  inc takes 3 cycles.  The machine description
 ;; is willing to trade 1 byte for 1 cycle (clrl instead of movl $0; cvtwl
 ;; instead of movl).
 ;; Cycle counts for other models may vary (on a VAX 750 they are similar,
 ;; but on a VAX 9000 most move and add instructions with one constant
 ;; operand take 1 cycle).
 ;;  Loads of constants between 64 and 128 used to be done with
 ;; "addl3 $63,#,dst" but this is slower than movzbl and takes as much space.
 (define_expand "movsi"
   [(set (match_operand:SI 0 "nonimmediate_operand" "")
 	(match_operand:SI 1 "general_operand" ""))]
   ""
+  "
+{
 #ifdef NO_EXTERNAL_INDIRECT_ADDRESS
   if (flag_pic
       && GET_CODE (operands[1]) == CONST
       && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF
       && !SYMBOL_REF_LOCAL_P (XEXP (XEXP (operands[1], 0), 0)))
+    {
       rtx symbol_ref = XEXP (XEXP (operands[1], 0), 0);
       rtx const_int = XEXP (XEXP (operands[1], 0), 1);
       rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
       emit_move_insn (temp, symbol_ref);
       emit_move_insn (operands[0], gen_rtx_PLUS (SImode, temp, const_int));
       DONE;
+    }
 #endif
 }")
 (define_insn "movsi_2"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 	(match_operand:SI 1 "nonsymbolic_operand" "nrmT"))]
   ""
   "* return vax_output_int_move (insn, operands, SImode);")
 (define_insn "mov<mode>"
   [(set (match_operand:VAXintQH 0 "nonimmediate_operand" "=g")
 	(match_operand:VAXintQH 1 "general_operand" "g"))]
   ""
   "* return vax_output_int_move (insn, operands, <MODE>mode);")
 (define_insn "movstricthi"
   [(set (strict_low_part (match_operand:HI 0 "register_operand" "+g"))
 	(match_operand:HI 1 "general_operand" "g"))]
   ""
   "*
+{
   if (CONST_INT_P (operands[1]))
+    {
       int i = INTVAL (operands[1]);
       if (i == 0)
 	return \"clrw %0\";
       else if ((unsigned int)i < 64)
 	return \"movw %1,%0\";
       else if ((unsigned int)~i < 64)
 	return \"mcomw %H1,%0\";
       else if ((unsigned int)i < 256)
 	return \"movzbw %1,%0\";
+    }
   return \"movw %1,%0\";
 }")
 (define_insn "movstrictqi"
   [(set (strict_low_part (match_operand:QI 0 "register_operand" "+g"))
 	(match_operand:QI 1 "general_operand" "g"))]
   ""
   "*
+{
   if (CONST_INT_P (operands[1]))
+    {
       int i = INTVAL (operands[1]);
       if (i == 0)
 	return \"clrb %0\";
       else if ((unsigned int)~i < 64)
 	return \"mcomb %B1,%0\";
+    }
   return \"movb %1,%0\";
 }")
 ;; This is here to accept 4 arguments and pass the first 3 along
 ;; to the movmemhi1 pattern that really does the work.
 (define_expand "movmemhi"
   [(set (match_operand:BLK 0 "general_operand" "=g")
 	(match_operand:BLK 1 "general_operand" "g"))
    (use (match_operand:HI 2 "general_operand" "g"))
    (match_operand 3 "" "")]
   ""
+  "
+{
   if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) <= 48)
+    {
       emit_insn (gen_movmemsi1_2 (operands[0], operands[1], operands[2]));
       DONE;
+    }
   emit_insn (gen_movmemhi1 (operands[0], operands[1], operands[2]));
   DONE;
 }")
 ;; The definition of this insn does not really explain what it does,
 ;; but it should suffice
 ;; that anything generated as this insn will be recognized as one
 ;; and that it won't successfully combine with anything.
 (define_insn "movmemsi1_2"
   [(set (match_operand:BLK 0 "memory_operand" "=B")
 	(match_operand:BLK 1 "memory_operand" "B"))
    (use (match_operand:SI 2 "const_int_operand" "g"))]
   "INTVAL (operands[2]) <= 48"
   "* return vax_output_movmemsi (insn, operands);")
 (define_insn "movmemhi1"
   [(set (match_operand:BLK 0 "memory_operand" "=o")
 	(match_operand:BLK 1 "memory_operand" "o"))
    (use (match_operand:HI 2 "general_operand" "g"))
    (clobber (reg:SI 0))
    (clobber (reg:SI 1))
    (clobber (reg:SI 2))
    (clobber (reg:SI 3))
    (clobber (reg:SI 4))
    (clobber (reg:SI 5))]
   ""
   "movc3 %2,%1,%0")
 ;; Extension and truncation insns.
 (define_insn "truncsiqi2"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
 	(truncate:QI (match_operand:SI 1 "nonimmediate_operand" "nrmT")))]
   ""
   "cvtlb %1,%0")
 (define_insn "truncsihi2"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
 	(truncate:HI (match_operand:SI 1 "nonimmediate_operand" "nrmT")))]
   ""
   "cvtlw %1,%0")
 (define_insn "trunchiqi2"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
 	(truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))]
   ""
   "cvtwb %1,%0")
 (define_insn "extendhisi2"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 	(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
   ""
   "cvtwl %1,%0")
 (define_insn "extendqihi2"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
 	(sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
   ""
   "cvtbw %1,%0")
 (define_insn "extendqisi2"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
   ""
   "cvtbl %1,%0")
 (define_insn "extendsfdf2"
   [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
 	(float_extend:DF (match_operand:SF 1 "general_operand" "gF")))]
   ""
   "cvtf%# %1,%0")
 (define_insn "truncdfsf2"
   [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
 	(float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))]
   ""
   "cvt%#f %1,%0")
 (define_insn "zero_extendhisi2"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
   ""
   "movzwl %1,%0")
 (define_insn "zero_extendqihi2"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
 	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
   ""
   "movzbw %1,%0")
 (define_insn "zero_extendqisi2"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
   ""
   "movzbl %1,%0")
 ;; Fix-to-float conversion insns.
 (define_insn "float<VAXint:mode><VAXfp:mode>2"
   [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g")
 	(float:VAXfp (match_operand:VAXint 1 "nonimmediate_operand" "g")))]
   ""
   "cvt<VAXint:isfx><VAXfp:fsfx> %1,%0")
 ;; Float-to-fix conversion insns.
 (define_insn "fix_trunc<VAXfp:mode><VAXint:mode>2"
   [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
 	(fix:VAXint (match_operand:VAXfp 1 "general_operand" "gF")))]
   ""
   "cvt<VAXfp:fsfx><VAXint:isfx> %1,%0")
 (define_expand "fixuns_trunc<VAXfp:mode><VAXint:mode>2"
   [(set (match_operand:VAXint 0 "nonimmediate_operand" "")
 	(fix:VAXint (match_operand:VAXfp 1 "general_operand")))]
   "")
 ;;- All kinds of add instructions.
 (define_insn "add<mode>3"
   [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g")
 	(plus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF")
 		    (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))]
   ""
   "@
    add<VAXfp:fsfx>2 %2,%0
    add<VAXfp:fsfx>2 %1,%0
    add<VAXfp:fsfx>3 %1,%2,%0")
 (define_insn "pushlclsymreg"
   [(set (match_operand:SI 0 "push_operand" "=g")
 	(plus:SI (match_operand:SI 1 "register_operand" "%r")
 		 (match_operand:SI 2 "local_symbolic_operand" "i")))]
   "flag_pic"
   "pushab %a2[%1]")
 (define_insn "pushextsymreg"
   [(set (match_operand:SI 0 "push_operand" "=g")
 	(plus:SI (match_operand:SI 1 "register_operand" "%r")
 		 (match_operand:SI 2 "external_symbolic_operand" "i")))]
   "flag_pic"
   "pushab %a2[%1]")
 (define_insn "movlclsymreg"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 	(plus:SI (match_operand:SI 1 "register_operand" "%r")
 		 (match_operand:SI 2 "local_symbolic_operand" "i")))]
   "flag_pic"
   "movab %a2[%1],%0")
 (define_insn "movextsymreg"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 	(plus:SI (match_operand:SI 1 "register_operand" "%r")
 		 (match_operand:SI 2 "external_symbolic_operand" "i")))]
   "flag_pic"
   "movab %a2[%1],%0")
 (define_insn "add<mode>3"
   [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
 	(plus:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")
 		     (match_operand:VAXint 2 "general_operand" "nrmT")))]
   ""
   "* return vax_output_int_add (insn, operands, <MODE>mode);")
 (define_expand "adddi3"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
 	(plus:DI (match_operand:DI 1 "general_operand" "g")
 		 (match_operand:DI 2 "general_operand" "g")))]
   "!reload_in_progress"
   "vax_expand_addsub_di_operands (operands, PLUS); DONE;")
 (define_insn "adcdi3"
   [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr")
 	(plus:DI (match_operand:DI 1 "general_addsub_di_operand" "%0")
 		 (match_operand:DI 2 "general_addsub_di_operand" "nRr")))]
   "TARGET_QMATH"
   "* return vax_output_int_add (insn, operands, DImode);")
 ;; The add-with-carry (adwc) instruction only accepts two operands.
 (define_insn "adddi3_old"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=ro>,ro>")
 	(plus:DI (match_operand:DI 1 "general_operand" "%0,ro>")
 		 (match_operand:DI 2 "general_operand" "Fsro,Fs")))]
   "!TARGET_QMATH"
   "* return vax_output_int_add (insn, operands, DImode);")
 ;;- All kinds of subtract instructions.
 (define_insn "sub<mode>3"
   [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
 	(minus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF")
 		     (match_operand:VAXfp 2 "general_operand" "gF,gF")))]
   ""
   "@
    sub<VAXfp:fsfx>2 %2,%0
    sub<VAXfp:fsfx>3 %2,%1,%0")
 (define_insn "sub<mode>3"
   [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
 	(minus:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
 		      (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))]
   ""
   "@
    sub<VAXint:isfx>2 %2,%0
    sub<VAXint:isfx>3 %2,%1,%0")
 (define_expand "subdi3"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
 	(minus:DI (match_operand:DI 1 "general_operand" "g")
 		  (match_operand:DI 2 "general_operand" "g")))]
   "!reload_in_progress"
   "vax_expand_addsub_di_operands (operands, MINUS); DONE;")
 (define_insn "sbcdi3"
   [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr,Rr")
 	(minus:DI (match_operand:DI 1 "general_addsub_di_operand" "0,I")
 		  (match_operand:DI 2 "general_addsub_di_operand" "nRr,Rr")))]
   "TARGET_QMATH"
   "* return vax_output_int_subtract (insn, operands, DImode);")
 ;; The subtract-with-carry (sbwc) instruction only takes two operands.
 (define_insn "subdi3_old"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=or>,or>")
 	(minus:DI (match_operand:DI 1 "general_operand" "0,or>")
 		  (match_operand:DI 2 "general_operand" "Fsor,Fs")))]
   "!TARGET_QMATH"
   "* return vax_output_int_subtract (insn, operands, DImode);")
 ;;- Multiply instructions.
 (define_insn "mul<mode>3"
   [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g")
 	(mult:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF")
 		    (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))]
   ""
   "@
    mul<VAXfp:fsfx>2 %2,%0
    mul<VAXfp:fsfx>2 %1,%0
    mul<VAXfp:fsfx>3 %1,%2,%0")
 (define_insn "mul<mode>3"
   [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
 	(mult:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
 		     (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))]
   ""
   "@
    mul<VAXint:isfx>2 %2,%0
    mul<VAXint:isfx>2 %1,%0
    mul<VAXint:isfx>3 %1,%2,%0")
 (define_insn "mulsidi3"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
 	(mult:DI (sign_extend:DI
 		  (match_operand:SI 1 "nonimmediate_operand" "nrmT"))
 		 (sign_extend:DI
 		  (match_operand:SI 2 "nonimmediate_operand" "nrmT"))))]
   ""
   "emul %1,%2,$0,%0")
 (define_insn ""
   [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
 	(plus:DI
 	 (mult:DI (sign_extend:DI
 		   (match_operand:SI 1 "nonimmediate_operand" "nrmT"))
 		  (sign_extend:DI
 		   (match_operand:SI 2 "nonimmediate_operand" "nrmT")))
 	 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "g"))))]
   ""
   "emul %1,%2,%3,%0")
 ;; 'F' constraint means type CONST_DOUBLE
 (define_insn ""
   [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
 	(plus:DI
 	 (mult:DI (sign_extend:DI
 		   (match_operand:SI 1 "nonimmediate_operand" "nrmT"))
 		  (sign_extend:DI
 		   (match_operand:SI 2 "nonimmediate_operand" "nrmT")))
 	 (match_operand:DI 3 "immediate_operand" "F")))]
   "GET_CODE (operands[3]) == CONST_DOUBLE
     && CONST_DOUBLE_HIGH (operands[3]) == (CONST_DOUBLE_LOW (operands[3]) >> 31)"
   "*
+{
   if (CONST_DOUBLE_HIGH (operands[3]))
     operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[3]));
   return \"emul %1,%2,%3,%0\";
 }")
 ;;- Divide instructions.
 (define_insn "div<mode>3"
   [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
 	(div:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF")
 		   (match_operand:VAXfp 2 "general_operand" "gF,gF")))]
   ""
   "@
    div<VAXfp:fsfx>2 %2,%0
    div<VAXfp:fsfx>3 %2,%1,%0")
 (define_insn "div<mode>3"
   [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
 	(div:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
 		    (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))]
   ""
   "@
    div<VAXint:isfx>2 %2,%0
    div<VAXint:isfx>3 %2,%1,%0")
 ;This is left out because it is very slow;
 ;we are better off programming around the "lack" of this insn.
 ;(define_insn "divmoddisi4"
 ;  [(set (match_operand:SI 0 "general_operand" "=g")
 ;	(div:SI (match_operand:DI 1 "general_operand" "g")
 ;		(match_operand:SI 2 "general_operand" "g")))
 ;   (set (match_operand:SI 3 "general_operand" "=g")
 ;	(mod:SI (match_operand:DI 1 "general_operand" "g")
 ;		(match_operand:SI 2 "general_operand" "g")))]
 ;  ""
 ;  "ediv %2,%1,%0,%3")
 ;; Bit-and on the VAX is done with a clear-bits insn.
 (define_expand "and<mode>3"
   [(set (match_operand:VAXint 0 "nonimmediate_operand" "")
 	(and:VAXint (not:VAXint (match_operand:VAXint 1 "general_operand" ""))
 		    (match_operand:VAXint 2 "general_operand" "")))]
   ""
+  "
+{
   rtx op1 = operands[1];
   /* If there is a constant argument, complement that one.  */
   if (CONST_INT_P (operands[2]) && ! CONST_INT_P (op1))
+    {
       operands[1] = operands[2];
       operands[2] = op1;
       op1 = operands[1];
+    }
   if (CONST_INT_P (op1))
     operands[1] = GEN_INT (~INTVAL (op1));
   else
     operands[1] = expand_unop (<MODE>mode, one_cmpl_optab, op1, 0, 1);
 }")
 (define_insn "*and<mode>"
   [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
 	(and:VAXint (not:VAXint (match_operand:VAXint 1 "general_operand" "nrmT,nrmT"))
 		    (match_operand:VAXint 2 "general_operand" "0,nrmT")))]
   ""
   "@
    bic<VAXint:isfx>2 %1,%0
    bic<VAXint:isfx>3 %1,%2,%0")
 ;; The following used to be needed because constant propagation can
 ;; create them starting from the bic insn patterns above.  This is no
 ;; longer a problem.  However, having these patterns allows optimization
 ;; opportunities in combine.c.
 (define_insn "*and<mode>_const_int"
   [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
 	(and:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
 		    (match_operand:VAXint 2 "const_int_operand" "n,n")))]
   ""
   "@
    bic<VAXint:isfx>2 %<VAXint:iprefx>2,%0
    bic<VAXint:isfx>3 %<VAXint:iprefx>2,%1,%0")
 ;;- Bit set instructions.
 (define_insn "ior<mode>3"
   [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
 	(ior:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
 		    (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))]
   ""
   "@
    bis<VAXint:isfx>2 %2,%0
    bis<VAXint:isfx>2 %1,%0
    bis<VAXint:isfx>3 %2,%1,%0")
 ;;- xor instructions.
 (define_insn "xor<mode>3"
   [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
 	(xor:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
 		    (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))]
   ""
   "@
    xor<VAXint:isfx>2 %2,%0
    xor<VAXint:isfx>2 %1,%0
    xor<VAXint:isfx>3 %2,%1,%0")
 (define_insn "neg<mode>2"
   [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g")
 	(neg:VAXfp (match_operand:VAXfp 1 "general_operand" "gF")))]
   ""
   "mneg<VAXfp:fsfx> %1,%0")
 (define_insn "neg<mode>2"
   [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
 	(neg:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")))]
   ""
   "mneg<VAXint:isfx> %1,%0")
 (define_insn "one_cmpl<mode>2"
   [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
 	(not:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")))]
   ""
   "mcom<VAXint:isfx> %1,%0")
 ;; Arithmetic right shift on the VAX works by negating the shift count,
 ;; then emitting a right shift with the shift count negated.  This means
 ;; that all actual shift counts in the RTL will be positive.  This
 ;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
 ;; which isn't valid.
 (define_expand "ashrsi3"
   [(set (match_operand:SI 0 "general_operand" "=g")
 	(ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
 		     (match_operand:QI 2 "general_operand" "g")))]
   ""
+  "
+{
   if (! CONST_INT_P (operands[2]))
     operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
 }")
 (define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 	(ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
 		     (match_operand:QI 2 "const_int_operand" "n")))]
   ""
   "ashl $%n2,%1,%0")
 (define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 	(ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
 		     (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
   ""
   "ashl %2,%1,%0")
 (define_insn "ashlsi3"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 	(ashift:SI (match_operand:SI 1 "general_operand" "nrmT")
 		   (match_operand:QI 2 "general_operand" "g")))]
   ""
   "*
+{
   if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1]))
     return \"addl2 %0,%0\";
   if (REG_P (operands[1]) && CONST_INT_P (operands[2]))
+    {
       int i = INTVAL (operands[2]);
       if (i == 1)
 	return \"addl3 %1,%1,%0\";
       if (i == 2 && !optimize_size)
+	{
 	  if (push_operand (operands[0], SImode))
 	    return \"pushal 0[%1]\";
 	  return \"moval 0[%1],%0\";
+	}
       if (i == 3 && !optimize_size)
+	{
 	  if (push_operand (operands[0], SImode))
 	    return \"pushaq 0[%1]\";
 	  return \"movaq 0[%1],%0\";
+	}
+    }
   return \"ashl %2,%1,%0\";
 }")
 ;; Arithmetic right shift on the VAX works by negating the shift count.
 (define_expand "ashrdi3"
   [(set (match_operand:DI 0 "general_operand" "=g")
 	(ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
 		     (match_operand:QI 2 "general_operand" "g")))]
   ""
+  "
+{
   operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
 }")
 (define_insn "ashldi3"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
 	(ashift:DI (match_operand:DI 1 "general_operand" "g")
 		   (match_operand:QI 2 "general_operand" "g")))]
   ""
   "ashq %2,%D1,%0")
 (define_insn ""
   [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
 	(ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
 		     (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
   ""
   "ashq %2,%D1,%0")
 ;; We used to have expand_shift handle logical right shifts by using extzv,
 ;; but this make it very difficult to do lshrdi3.  Since the VAX is the
 ;; only machine with this kludge, it's better to just do this with a
 ;; define_expand and remove that case from expand_shift.
 (define_expand "lshrsi3"
   [(set (match_dup 3)
 	(minus:QI (const_int 32)
 		  (match_dup 4)))
    (set (match_operand:SI 0 "nonimmediate_operand" "=g")
 	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
 			 (match_dup 3)
 			 (match_operand:SI 2 "register_operand" "g")))]
   ""
+  "
+{
   operands[3] = gen_reg_rtx (QImode);
   operands[4] = gen_lowpart (QImode, operands[2]);
 }")
 ;; Rotate right on the VAX works by negating the shift count.
 (define_expand "rotrsi3"
   [(set (match_operand:SI 0 "general_operand" "=g")
 	(rotatert:SI (match_operand:SI 1 "general_operand" "g")
 		     (match_operand:QI 2 "general_operand" "g")))]
   ""
+  "
+{
   if (! CONST_INT_P (operands[2]))
     operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
 }")
 (define_insn "rotlsi3"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 	(rotate:SI (match_operand:SI 1 "general_operand" "nrmT")
 		   (match_operand:QI 2 "general_operand" "g")))]
   ""
   "rotl %2,%1,%0")
 (define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 	(rotatert:SI (match_operand:SI 1 "general_operand" "nrmT")
 		     (match_operand:QI 2 "const_int_operand" "n")))]
   ""
   "rotl %R2,%1,%0")
 (define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 	(rotatert:SI (match_operand:SI 1 "general_operand" "nrmT")
 		     (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
   ""
   "rotl %2,%1,%0")
 ;This insn is probably slower than a multiply and an add.
 ;(define_insn ""
 ;  [(set (match_operand:SI 0 "general_operand" "=g")
 ;	(mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g")
 ;			  (match_operand:SI 2 "general_operand" "g"))
 ;		 (match_operand:SI 3 "general_operand" "g")))]
 ;  ""
 ;  "index %1,$0x80000000,$0x7fffffff,%3,%2,%0")
 ;; Special cases of bit-field insns which we should
 ;; recognize in preference to the general case.
 ;; These handle aligned 8-bit and 16-bit fields,
 ;; which can usually be done with move instructions.
 ;; netbsd changed this to REG_P (operands[0]) || (MEM_P (operands[0]) && ...
 ;; but gcc made it just !MEM_P (operands[0]) || ...
 (define_insn ""
   [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+ro")
 			 (match_operand:QI 1 "const_int_operand" "n")
 			 (match_operand:SI 2 "const_int_operand" "n"))
 	(match_operand:SI 3 "general_operand" "g"))]
    "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
    && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
    && (REG_P (operands[0])
        || (MEM_P (operands[0])
           && ! mode_dependent_address_p (XEXP (operands[0], 0),
 				       MEM_ADDR_SPACE (operands[0]))))"
   "*
+{
   if (REG_P (operands[0]))
+    {
       if (INTVAL (operands[2]) != 0)
 	return \"insv %3,%2,%1,%0\";
+    }
   else
     operands[0]
       = adjust_address (operands[0],
 			INTVAL (operands[1]) == 8 ? QImode : HImode,
 			INTVAL (operands[2]) / 8);
   CC_STATUS_INIT;
   if (INTVAL (operands[1]) == 8)
     return \"movb %3,%0\";
   return \"movw %3,%0\";
 }")
 (define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand" "=&g")
 	(zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
 			 (match_operand:QI 2 "const_int_operand" "n")
 			 (match_operand:SI 3 "const_int_operand" "n")))]
   "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
    && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
    && (REG_P (operands[1])
        || (MEM_P (operands[1])
           && ! mode_dependent_address_p (XEXP (operands[1], 0),
 				      MEM_ADDR_SPACE (operands[1]))))"
   "*
+{
   if (REG_P (operands[1]))
+    {
       if (INTVAL (operands[3]) != 0)
 	return \"extzv %3,%2,%1,%0\";
+    }
   else
     operands[1]
       = adjust_address (operands[1],
 			INTVAL (operands[2]) == 8 ? QImode : HImode,
 			INTVAL (operands[3]) / 8);
   if (INTVAL (operands[2]) == 8)
     return \"movzbl %1,%0\";
   return \"movzwl %1,%0\";
 }")
 (define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 	(sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
 			 (match_operand:QI 2 "const_int_operand" "n")
 			 (match_operand:SI 3 "const_int_operand" "n")))]
   "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
    && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
    && (REG_P (operands[1])
        || (MEM_P (operands[1])
           && ! mode_dependent_address_p (XEXP (operands[1], 0),
 				      MEM_ADDR_SPACE (operands[1]))))"
   "*
+{
   if (REG_P (operands[1]))
+    {
       if (INTVAL (operands[3]) != 0)
 	return \"extv %3,%2,%1,%0\";
+    }
   else
     operands[1]
       = adjust_address (operands[1],
 			INTVAL (operands[2]) == 8 ? QImode : HImode,
 			INTVAL (operands[3]) / 8);
   if (INTVAL (operands[2]) == 8)
     return \"cvtbl %1,%0\";
   return \"cvtwl %1,%0\";
 }")
 ;; Register-only SImode cases of bit-field insns.
 (define_insn ""
   [(set (cc0)
 	(compare
 	 (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
 			  (match_operand:QI 1 "general_operand" "g")
 			  (match_operand:SI 2 "general_operand" "nrmT"))
 	 (match_operand:SI 3 "general_operand" "nrmT")))]
   ""
   "cmpv %2,%1,%0,%3")
 (define_insn ""
   [(set (cc0)
 	(compare
 	 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
 			  (match_operand:QI 1 "general_operand" "g")
 			  (match_operand:SI 2 "general_operand" "nrmT"))
 	 (match_operand:SI 3 "general_operand" "nrmT")))]
   ""
   "cmpzv %2,%1,%0,%3")
 ;; When the field position and size are constant and the destination
 ;; is a register, extv and extzv are much slower than a rotate followed
 ;; by a bicl or sign extension.  Because we might end up choosing ext[z]v
 ;; anyway, we can't allow immediate values for the primary source operand.
 (define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 	(sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
 			 (match_operand:QI 2 "general_operand" "g")
 			 (match_operand:SI 3 "general_operand" "nrmT")))]
   ""
   "*
+{
   if (! CONST_INT_P (operands[3]) || ! CONST_INT_P (operands[2])
       || ! REG_P (operands[0])
       || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16))
     return \"extv %3,%2,%1,%0\";
   if (INTVAL (operands[2]) == 8)
     return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
   return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
 }")
 (define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 	(zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
 			 (match_operand:QI 2 "general_operand" "g")
 			 (match_operand:SI 3 "general_operand" "nrmT")))]
   ""
   "*
+{
   if (! CONST_INT_P (operands[3]) || ! CONST_INT_P (operands[2])
       || ! REG_P (operands[0]))
     return \"extzv %3,%2,%1,%0\";
   if (INTVAL (operands[2]) == 8)
     return \"rotl %R3,%1,%0\;movzbl %0,%0\";
   if (INTVAL (operands[2]) == 16)
     return \"rotl %R3,%1,%0\;movzwl %0,%0\";
   if (INTVAL (operands[3]) & 31)
     return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
   if (rtx_equal_p (operands[0], operands[1]))
     return \"bicl2 %M2,%0\";
   return \"bicl3 %M2,%1,%0\";
 }")
 ;; Non-register cases.
 ;; nonimmediate_operand is used to make sure that mode-ambiguous cases
 ;; don't match these (and therefore match the cases above instead).
 (define_insn ""
   [(set (cc0)
 	(compare
 	 (sign_extract:SI (match_operand:QI 0 "memory_operand" "m")
 			  (match_operand:QI 1 "general_operand" "g")
 			  (match_operand:SI 2 "general_operand" "nrmT"))
 	 (match_operand:SI 3 "general_operand" "nrmT")))]
   ""
   "cmpv %2,%1,%0,%3")
 (define_insn ""
   [(set (cc0)
 	(compare
 	 (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
 			  (match_operand:QI 1 "general_operand" "g")
 			  (match_operand:SI 2 "general_operand" "nrmT"))
 	 (match_operand:SI 3 "general_operand" "nrmT")))]
   ""
   "cmpzv %2,%1,%0,%3")
 (define_insn "extv"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 	(sign_extract:SI (match_operand:QI 1 "memory_operand" "m")
 			 (match_operand:QI 2 "general_operand" "g")
 			 (match_operand:SI 3 "general_operand" "nrmT")))]
   ""
   "*
+{
   if (! REG_P (operands[0]) || ! CONST_INT_P (operands[2])
       || ! CONST_INT_P (operands[3])
       || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)
       || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
       || side_effects_p (operands[1])
       || (MEM_P (operands[1])
 	  && mode_dependent_address_p (XEXP (operands[1], 0),
 				       MEM_ADDR_SPACE (operands[1]))))
     return \"extv %3,%2,%1,%0\";
   if (INTVAL (operands[2]) == 8)
     return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
   return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
 }")
 (define_expand "extzv"
   [(set (match_operand:SI 0 "general_operand" "")
 	(zero_extract:SI (match_operand:SI 1 "general_operand" "")
 			 (match_operand:QI 2 "general_operand" "")
 			 (match_operand:SI 3 "general_operand" "")))]
   ""
   "")
 (define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 	(zero_extract:SI (match_operand:QI 1 "memory_operand" "m")
 			 (match_operand:QI 2 "general_operand" "g")
 			 (match_operand:SI 3 "general_operand" "nrmT")))]
   ""
   "*
+{
   if (! REG_P (operands[0]) || ! CONST_INT_P (operands[2])
       || ! CONST_INT_P (operands[3])
       || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
       || side_effects_p (operands[1])
       || (MEM_P (operands[1])
 	  && mode_dependent_address_p (XEXP (operands[1], 0),
 				       MEM_ADDR_SPACE (operands[1]))))
     return \"extzv %3,%2,%1,%0\";
   if (INTVAL (operands[2]) == 8)
     return \"rotl %R3,%1,%0\;movzbl %0,%0\";
   if (INTVAL (operands[2]) == 16)
     return \"rotl %R3,%1,%0\;movzwl %0,%0\";
   if (MEM_P (operands[1])
       && GET_CODE (XEXP (operands[1], 0)) == PLUS
       && REG_P (XEXP (XEXP (operands[1], 0), 0))
       && CONST_INT_P (XEXP (XEXP (operands[1], 0), 1))
       && CONST_INT_P (operands[2])
       && CONST_INT_P (operands[3]))
+    {
       HOST_WIDE_INT o = INTVAL (XEXP (XEXP (operands[1], 0), 1));
       HOST_WIDE_INT l = INTVAL (operands[2]);
       HOST_WIDE_INT v = INTVAL (operands[3]);
       if ((o & 3) && (o & 3) * 8 + v + l <= 32)
+	{
 	  rtx tmp;
 	  tmp = XEXP (XEXP (operands[1], 0), 0);
 	  if (o & ~3)
 	    tmp = gen_rtx_PLUS (SImode, tmp, GEN_INT (o & ~3));
 	  operands[1] = gen_rtx_MEM (QImode, tmp);
 	  operands[3] = GEN_INT (v + (o & 3) * 8);
+	}
       if (optimize_size)
 	return \"extzv %3,%2,%1,%0\";
+    }
   return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
 }")
 (define_expand "insv"
   [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
 			 (match_operand:QI 1 "general_operand" "")
 			 (match_operand:SI 2 "general_operand" ""))
 	(match_operand:SI 3 "general_operand" ""))]
   ""
   "")
 (define_insn ""
   [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+g")
 			 (match_operand:QI 1 "general_operand" "g")
 			 (match_operand:SI 2 "general_operand" "nrmT"))
 	(match_operand:SI 3 "general_operand" "nrmT"))]
   ""
   "*
+{
   if (MEM_P (operands[0])
       && GET_CODE (XEXP (operands[0], 0)) == PLUS
       && REG_P (XEXP (XEXP (operands[0], 0), 0))
       && CONST_INT_P (XEXP (XEXP (operands[0], 0), 1))
       && CONST_INT_P (operands[1])
       && CONST_INT_P (operands[2]))
+    {
       HOST_WIDE_INT o = INTVAL (XEXP (XEXP (operands[0], 0), 1));
       HOST_WIDE_INT v = INTVAL (operands[2]);
       HOST_WIDE_INT l = INTVAL (operands[1]);
       if ((o & 3) && (o & 3) * 8 + v + l <= 32)
+	{
 	  rtx tmp;
 	  tmp = XEXP (XEXP (operands[0], 0), 0);
 	  if (o & ~3)
 	    tmp = gen_rtx_PLUS (SImode, tmp, GEN_INT (o & ~3));
 	  operands[0] = gen_rtx_MEM (QImode, tmp);
 	  operands[2] = GEN_INT (v + (o & 3) * 8);
+	}
+    }
   return \"insv %3,%2,%1,%0\";
 }")
 (define_insn ""
   [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
 			 (match_operand:QI 1 "general_operand" "g")
 			 (match_operand:SI 2 "general_operand" "nrmT"))
 	(match_operand:SI 3 "general_operand" "nrmT"))]
   ""
   "insv %3,%2,%1,%0")
 ;; Unconditional jump
 (define_insn "jump"
   [(set (pc)
 	(label_ref (match_operand 0 "" "")))]
   ""
   "jbr %l0")
 ;; Conditional jumps
 (define_expand "cbranch<mode>4"
   [(set (cc0)
         (compare (match_operand:VAXint 1 "nonimmediate_operand" "")
                  (match_operand:VAXint 2 "general_operand" "")))
    (set (pc)
         (if_then_else
               (match_operator 0 "ordered_comparison_operator" [(cc0)
                                                                (const_int 0)])
               (label_ref (match_operand 3 "" ""))
               (pc)))]
  "")
 (define_expand "cbranch<mode>4"
   [(set (cc0)
         (compare (match_operand:VAXfp 1 "general_operand" "")
                  (match_operand:VAXfp 2 "general_operand" "")))
    (set (pc)
         (if_then_else
               (match_operator 0 "ordered_comparison_operator" [(cc0)
                                                                (const_int 0)])
               (label_ref (match_operand 3 "" ""))
               (pc)))]
  "")
 (define_insn "*branch"
   [(set (pc)
 	(if_then_else (match_operator 0 "ordered_comparison_operator"
 				      [(cc0)
 				       (const_int 0)])
 		      (label_ref (match_operand 1 "" ""))
 		      (pc)))]
   ""
   "j%c0 %l1")
 ;; Recognize reversed jumps.
 (define_insn "*branch_reversed"
   [(set (pc)
 	(if_then_else (match_operator 0 "ordered_comparison_operator"
 				      [(cc0)
 				       (const_int 0)])
 		      (pc)
 		      (label_ref (match_operand 1 "" ""))))]
   ""
   "j%C0 %l1") ; %C0 negates condition
 ;; Recognize jbs, jlbs, jbc and jlbc instructions.  Note that the operand
 ;; of jlbs and jlbc insns are SImode in the hardware.  However, if it is
 ;; memory, we use QImode in the insn.  So we can't use those instructions
 ;; for mode-dependent addresses.
 (define_insn ""
   [(set (pc)
 	(if_then_else
 	 (ne (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
 			      (const_int 1)
 			      (match_operand:SI 1 "general_operand" "I,nrmT"))
 	     (const_int 0))
 	 (label_ref (match_operand 2 "" ""))
 	 (pc)))]
   ""
   "@
    jlbs %0,%l2
    jbs %1,%0,%l2")
 (define_insn ""
   [(set (pc)
 	(if_then_else
 	 (eq (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
 			      (const_int 1)
 			      (match_operand:SI 1 "general_operand" "I,nrmT"))
 	     (const_int 0))
 	 (label_ref (match_operand 2 "" ""))
 	 (pc)))]
   ""
   "@
    jlbc %0,%l2
    jbc %1,%0,%l2")
 (define_insn ""
   [(set (pc)
 	(if_then_else
 	 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
 			      (const_int 1)
 			      (match_operand:SI 1 "general_operand" "I,nrmT"))
 	     (const_int 0))
 	 (label_ref (match_operand 2 "" ""))
 	 (pc)))]
   ""
   "@
    jlbs %0,%l2
    jbs %1,%0,%l2")
 (define_insn ""
   [(set (pc)
 	(if_then_else
 	 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
 			      (const_int 1)
 			      (match_operand:SI 1 "general_operand" "I,nrmT"))
 	     (const_int 0))
 	 (label_ref (match_operand 2 "" ""))
 	 (pc)))]
   ""
   "@
    jlbc %0,%l2
    jbc %1,%0,%l2")
 ;; Subtract-and-jump and Add-and-jump insns.
 ;; These are not used when output is for the Unix assembler
 ;; because it does not know how to modify them to reach far.
 ;; Normal sob insns.
 (define_insn ""
   [(set (pc)
 	(if_then_else
 	 (gt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
 		      (const_int -1))
 	     (const_int 0))
 	 (label_ref (match_operand 1 "" ""))
 	 (pc)))
    (set (match_dup 0)
 	(plus:SI (match_dup 0)
 		 (const_int -1)))]
   "!TARGET_UNIX_ASM"
   "jsobgtr %0,%l1")
 (define_insn ""
   [(set (pc)
 	(if_then_else
 	 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
 		      (const_int -1))
 	     (const_int 0))
 	 (label_ref (match_operand 1 "" ""))
 	 (pc)))
    (set (match_dup 0)
 	(plus:SI (match_dup 0)
 		 (const_int -1)))]
   "!TARGET_UNIX_ASM"
   "jsobgeq %0,%l1")
 ;; Normal aob insns.  Define a version for when operands[1] is a constant.
 (define_insn ""
   [(set (pc)
 	(if_then_else
 	 (lt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
 		      (const_int 1))
 	     (match_operand:SI 1 "general_operand" "nrmT"))
 	 (label_ref (match_operand 2 "" ""))
 	 (pc)))
    (set (match_dup 0)
 	(plus:SI (match_dup 0)
 		 (const_int 1)))]
   "!TARGET_UNIX_ASM"
   "jaoblss %1,%0,%l2")
 (define_insn ""
   [(set (pc)
 	(if_then_else
 	 (lt (match_operand:SI 0 "nonimmediate_operand" "+g")
 	     (match_operand:SI 1 "general_operand" "nrmT"))
 	 (label_ref (match_operand 2 "" ""))
 	 (pc)))
    (set (match_dup 0)
 	(plus:SI (match_dup 0)
 		 (const_int 1)))]
   "!TARGET_UNIX_ASM && CONST_INT_P (operands[1])"
   "jaoblss %P1,%0,%l2")
 (define_insn ""
   [(set (pc)
 	(if_then_else
 	 (le (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
 		      (const_int 1))
 	     (match_operand:SI 1 "general_operand" "nrmT"))
 	 (label_ref (match_operand 2 "" ""))
 	 (pc)))
    (set (match_dup 0)
 	(plus:SI (match_dup 0)
 		 (const_int 1)))]
   "!TARGET_UNIX_ASM"
   "jaobleq %1,%0,%l2")
 (define_insn ""
   [(set (pc)
 	(if_then_else
 	 (le (match_operand:SI 0 "nonimmediate_operand" "+g")
 	     (match_operand:SI 1 "general_operand" "nrmT"))
 	 (label_ref (match_operand 2 "" ""))
 	 (pc)))
    (set (match_dup 0)
 	(plus:SI (match_dup 0)
 		 (const_int 1)))]
   "!TARGET_UNIX_ASM && CONST_INT_P (operands[1])"
   "jaobleq %P1,%0,%l2")
 ;; Something like a sob insn, but compares against -1.
 ;; This finds `while (foo--)' which was changed to `while (--foo != -1)'.
 (define_insn ""
   [(set (pc)
 	(if_then_else
 	 (ne (match_operand:SI 0 "nonimmediate_operand" "+g")
 	     (const_int 0))
 	 (label_ref (match_operand 1 "" ""))
 	 (pc)))
    (set (match_dup 0)
 	(plus:SI (match_dup 0)
 		 (const_int -1)))]
   ""
   "decl %0\;jgequ %l1")
 ;; Note that operand 1 is total size of args, in bytes,
 ;; and what the call insn wants is the number of words.
 ;; It is used in the call instruction as a byte, but in the addl2 as
 ;; a word.  Since the only time we actually use it in the call instruction
 ;; is when it is a constant, SImode (for addl2) is the proper mode.
 (define_expand "call_pop"
   [(parallel [(call (match_operand:QI 0 "memory_operand" "")
 		    (match_operand:SI 1 "const_int_operand" ""))
 	      (set (reg:SI VAX_SP_REGNUM)
 		   (plus:SI (reg:SI VAX_SP_REGNUM)
 			    (match_operand:SI 3 "immediate_operand" "")))])]
   ""
+{
-  gcc_assert (INTVAL (operands[3]) <= 255 * 4 && INTVAL (operands[3]) % 4 == 0);
+  gcc_assert (INTVAL (operands[1]) <= 255 * 4);
   operands[1] = GEN_INT ((INTVAL (operands[1]) + 3) / 4);
   /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size
      during EH unwinding.  We must include the argument count pushed by
      the calls instruction.  */
   operands[1] = GEN_INT (INTVAL (operands[3]) + 4);
 })
 (define_insn "*call_pop"
   [(call (match_operand:QI 0 "memory_operand" "m")
 	 (match_operand:SI 1 "const_int_operand" "n"))
    (set (reg:SI VAX_SP_REGNUM) (plus:SI (reg:SI VAX_SP_REGNUM)
-					(match_operand:SI 2 "immediate_operand" "i")))]
+			     (match_operand:SI 2 "immediate_operand" "i")))]
   ""
   "calls %1,%0")
   operands[1] = GEN_INT ((INTVAL (operands[1]) - 4) / 4);
   return "calls %1,%0";
 })
 (define_expand "call_value_pop"
   [(parallel [(set (match_operand 0 "" "")
 		   (call (match_operand:QI 1 "memory_operand" "")
 			 (match_operand:SI 2 "const_int_operand" "")))
 	      (set (reg:SI VAX_SP_REGNUM)
 		   (plus:SI (reg:SI VAX_SP_REGNUM)
 			    (match_operand:SI 4 "immediate_operand" "")))])]
   ""
+{
-  gcc_assert (INTVAL (operands[4]) <= 255 * 4 && INTVAL (operands[4]) % 4 == 0);
+  gcc_assert (INTVAL (operands[2]) <= 255 * 4);
   operands[2] = GEN_INT ((INTVAL (operands[2]) + 3) / 4);
   /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size
      during EH unwinding.  We must include the argument count pushed by
      the calls instruction.  */
   operands[2] = GEN_INT (INTVAL (operands[4]) + 4);
 })
 (define_insn "*call_value_pop"
   [(set (match_operand 0 "" "")
 	(call (match_operand:QI 1 "memory_operand" "m")
 	      (match_operand:SI 2 "const_int_operand" "n")))
    (set (reg:SI VAX_SP_REGNUM) (plus:SI (reg:SI VAX_SP_REGNUM)
 					(match_operand:SI 3 "immediate_operand" "i")))]
   ""
-  "*
+  "calls %2,%1")
   operands[2] = GEN_INT ((INTVAL (operands[2]) - 4) / 4);
   return \"calls %2,%1\";
 }")
-(define_expand "call"
+;; Define another set of these for the case of functions with no operands.
-  [(call (match_operand:QI 0 "memory_operand" "")
+;; These will allow the optimizers to do a slightly better job.
-      (match_operand:SI 1 "const_int_operand" ""))]
+(define_insn "call"
-  ""
+  [(call (match_operand:QI 0 "memory_operand" "m")
 	 (const_int 0))]
   /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size
      during EH unwinding.  We must include the argument count pushed by
      the calls instruction.  */
   operands[1] = GEN_INT (INTVAL (operands[1]) + 4);
 }")
 (define_insn "*call"
    [(call (match_operand:QI 0 "memory_operand" "m")
 	  (match_operand:SI 1 "const_int_operand" ""))]
   ""
   "calls $0,%0")
-(define_expand "call_value"
+(define_insn "call_value"
   [(set (match_operand 0 "" "")
       (call (match_operand:QI 1 "memory_operand" "")
 	    (match_operand:SI 2 "const_int_operand" "")))]
   ""
   /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size
      during EH unwinding.  We must include the argument count pushed by
      the calls instruction.  */
   operands[2] = GEN_INT (INTVAL (operands[2]) + 4);
 }")
 (define_insn "*call_value"
   [(set (match_operand 0 "" "")
 	(call (match_operand:QI 1 "memory_operand" "m")
-	      (match_operand:SI 2 "const_int_operand" "")))]
+	      (const_int 0)))]
   ""
   "calls $0,%1")
 ;; Call subroutine returning any type.
 (define_expand "untyped_call"
   [(parallel [(call (match_operand 0 "" "")
 	      (const_int 0))
 	      (match_operand 1 "" "")
 	      (match_operand 2 "" "")])]
   ""
+  "
+{
   int i;
   emit_call_insn (gen_call_pop (operands[0], const0_rtx, NULL, const0_rtx));
   for (i = 0; i < XVECLEN (operands[2], 0); i++)
+    {
       rtx set = XVECEXP (operands[2], 0, i);
       emit_move_insn (SET_DEST (set), SET_SRC (set));
+    }
   /* The optimizer does not know that the call sets the function value
      registers we stored in the result block.  We avoid problems by
      claiming that all hard registers are used and clobbered at this
      point.  */
   emit_insn (gen_blockage ());
   DONE;
 }")
 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
 ;; all of memory.  This blocks insns from being moved across this point.
 (define_insn "blockage"
   [(unspec_volatile [(const_int 0)] VUNSPEC_BLOCKAGE)]
   ""
   "")
 (define_insn "procedure_entry_mask"
   [(unspec_volatile [(match_operand 0 "const_int_operand")] VUNSPEC_PEM)]
   ""
   ".word %x0")
 (define_insn "return"
   [(return)]
   ""
   "ret")
 (define_expand "prologue"
   [(const_int 0)]
   ""
+{
   vax_expand_prologue ();
   DONE;
 })
 (define_expand "epilogue"
   [(return)]
   ""
+  "
+{
   emit_jump_insn (gen_return ());
   DONE;
 }")
 (define_insn "nop"
   [(const_int 0)]
   ""
   "nop")
 ;; This had a wider constraint once, and it had trouble.
 ;; If you are tempted to try `g', please don't--it's not worth
 ;; the risk we will reopen the same bug.
 (define_insn "indirect_jump"
   [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
   ""
   "jmp (%0)")
 ;; This is here to accept 5 arguments (as passed by expand_end_case)
 ;; and pass the first 4 along to the casesi1 pattern that really does
 ;; the actual casesi work.  We emit a jump here to the default label
 ;; _before_ the casesi so that we can be sure that the casesi never
 ;; drops through.
 ;; This is suboptimal perhaps, but so is much of the rest of this
 ;; machine description.  For what it's worth, HPPA uses the same trick.
 ;;
 ;; operand 0 is index
 ;; operand 1 is the minimum bound (a const_int)
 ;; operand 2 is the maximum bound - minimum bound + 1 (also a const_int)
 ;; operand 3 is CODE_LABEL for the table;
 ;; operand 4 is the CODE_LABEL to go to if index out of range (ie. default).
 ;;
 ;; We emit:
 ;;	i = index - minimum_bound
 ;;	if (i > (maximum_bound - minimum_bound + 1) goto default;
 ;;	casesi (i, 0, table);
 ;;
 (define_expand "casesi"
   [(match_operand:SI 0 "general_operand" "")
    (match_operand:SI 1 "general_operand" "")
    (match_operand:SI 2 "general_operand" "")
    (match_operand 3 "" "")
    (match_operand 4 "" "")]
   ""
+{
   rtx test;
   /* i = index - minimum_bound;
      But only if the lower bound is not already zero.  */
   if (operands[1] != const0_rtx)
+    {
       rtx index = gen_reg_rtx (SImode);
       emit_insn (gen_addsi3 (index,
 			     operands[0],
 			     GEN_INT (-INTVAL (operands[1]))));
       operands[0] = index;
+    }
   /* if (i > (maximum_bound - minimum_bound + 1)) goto default;  */
   test = gen_rtx_fmt_ee (GTU, VOIDmode, operands[0], operands[2]);
   emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2], operands[4]));
   /* casesi (i, 0, table);  */
   emit_jump_insn (gen_casesi1 (operands[0], operands[2], operands[3]));
   DONE;
 })
 ;; This insn is a bit of a lier.  It actually falls through if no case
 ;; matches.  But, we prevent that from ever happening by emitting a jump
 ;; before this, see the define_expand above.
 (define_insn "casesi1"
   [(match_operand:SI 1 "const_int_operand" "n")
    (set (pc)
 	(plus:SI (sign_extend:SI
 		  (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "general_operand" "nrmT")
 					    (const_int 2))
 			  (pc))))
 		 (label_ref:SI (match_operand 2 "" ""))))]
   ""
   "casel %0,$0,%1")
 (define_insn "pushextsym"
   [(set (match_operand:SI 0 "push_operand" "=g")
 	(match_operand:SI 1 "external_symbolic_operand" "i"))]
   ""
   "pushab %a1")
 (define_insn "movextsym"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 	(match_operand:SI 1 "external_symbolic_operand" "i"))]
   ""
   "movab %a1,%0")
 (define_insn "pushlclsym"
   [(set (match_operand:SI 0 "push_operand" "=g")
 	(match_operand:SI 1 "local_symbolic_operand" "i"))]
   ""
   "pushab %a1")
 (define_insn "movlclsym"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 	(match_operand:SI 1 "local_symbolic_operand" "i"))]
   ""
   "movab %a1,%0")
 ;;- load or push effective address
 ;; These come after the move and add/sub patterns
 ;; because we don't want pushl $1 turned into pushad 1.
 ;; or addl3 r1,r2,r3 turned into movab 0(r1)[r2],r3.
 ;; It does not work to use constraints to distinguish pushes from moves,
 ;; because < matches any autodecrement, not just a push.
 (define_insn "pushaddr<mode>"
   [(set (match_operand:SI 0 "push_operand" "=g")
 	(match_operand:VAXintQHSD 1 "address_operand" "p"))]
   ""
   "pusha<VAXintQHSD:isfx> %a1")
 (define_insn "movaddr<mode>"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 	(match_operand:VAXintQHSD 1 "address_operand" "p"))]
   ""
   "mova<VAXintQHSD:isfx> %a1,%0")
 (define_insn "pushaddr<mode>"
   [(set (match_operand:SI 0 "push_operand" "=g")
 	(match_operand:VAXfp 1 "address_operand" "p"))]
   ""
   "pusha<VAXfp:fsfx> %a1")
 (define_insn "movaddr<mode>"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 	(match_operand:VAXfp 1 "address_operand" "p"))]
   ""
   "mova<VAXfp:fsfx> %a1,%0")
 ;; These used to be peepholes, but it is more straightforward to do them
 ;; as single insns.  However, we must force the output to be a register
 ;; if it is not an offsettable address so that we know that we can assign
 ;; to it twice.
 ;; If we had a good way of evaluating the relative costs, these could be
 ;; machine-independent.
 ;; Optimize   extzv ...,z;    andl2 ...,z
 ;; or	      ashl ...,z;     andl2 ...,z
 ;; with other operands constant.  This is what the combiner converts the
 ;; above sequences to before attempting to recognize the new insn.
 (define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
 	(and:SI (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
 			     (match_operand:QI 2 "const_int_operand" "n"))
 		(match_operand:SI 3 "const_int_operand" "n")))]
   "(INTVAL (operands[3]) & ~((1 << (32 - INTVAL (operands[2]))) - 1)) == 0"
   "*
+{
   unsigned long mask1 = INTVAL (operands[3]);
   unsigned long mask2 = (1 << (32 - INTVAL (operands[2]))) - 1;
   if ((mask1 & mask2) != mask1)
     operands[3] = GEN_INT (mask1 & mask2);
   return \"rotl %R2,%1,%0\;bicl2 %N3,%0\";
 }")
 ;; left-shift and mask
 ;; The only case where `ashl' is better is if the mask only turns off
 ;; bits that the ashl would anyways, in which case it should have been
 ;; optimized away.
 (define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
 	(and:SI (ashift:SI (match_operand:SI 1 "general_operand" "nrmT")
 			   (match_operand:QI 2 "const_int_operand" "n"))
 		(match_operand:SI 3 "const_int_operand" "n")))]
   ""
   "*
+{
   operands[3]
     = GEN_INT (INTVAL (operands[3]) & ~((1 << INTVAL (operands[2])) - 1));
   return \"rotl %2,%1,%0\;bicl2 %N3,%0\";
 }")
 ;; Instruction sequence to sync the VAX instruction stream.
 (define_insn "sync_istream"
   [(unspec_volatile [(const_int 0)] VUNSPEC_SYNC_ISTREAM)]
   ""
   "movpsl -(%|sp)\;pushal 1(%|pc)\;rei")
 (define_expand "nonlocal_goto"
   [(use (match_operand 0 "general_operand" ""))
    (use (match_operand 1 "general_operand" ""))
    (use (match_operand 2 "general_operand" ""))
    (use (match_operand 3 "general_operand" ""))]
   ""
+{
   rtx lab = operands[1];
   rtx stack = operands[2];
   rtx fp = operands[3];
   emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
   emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
   emit_move_insn (hard_frame_pointer_rtx, fp);
   emit_stack_restore (SAVE_NONLOCAL, stack);
   emit_use (hard_frame_pointer_rtx);
   emit_use (stack_pointer_rtx);
   /* We'll convert this to direct jump via a peephole optimization.  */
   emit_indirect_jump (copy_to_reg (lab));
   emit_barrier ();
   DONE;
 })
 (include "builtins.md")
 (define_peephole2
   [(set (match_operand:SI 0 "push_operand" "")
         (const_int 0))
    (set (match_dup 0)
         (match_operand:SI 1 "const_int_operand" ""))]
   "INTVAL (operands[1]) >= 0"
   [(set (match_dup 0)
         (match_dup 1))]
   "operands[0] = gen_rtx_MEM(DImode, XEXP (operands[0], 0));")
 (define_peephole2
   [(set (match_operand:SI 0 "push_operand" "")
         (match_operand:SI 1 "general_operand" ""))
    (set (match_dup 0)
         (match_operand:SI 2 "general_operand" ""))]
   "vax_decomposed_dimode_operand_p (operands[2], operands[1])"
   [(set (match_dup 0)
         (match_dup 2))]
   "{
     operands[0] = gen_rtx_MEM(DImode, XEXP (operands[0], 0));
     operands[2] = REG_P (operands[2])
       ? gen_rtx_REG(DImode, REGNO (operands[2]))
       : gen_rtx_MEM(DImode, XEXP (operands[2], 0));
 }")
 ; Leave this commented out until we can determine whether the second move
 ; precedes a jump which relies on the CC flags being set correctly.
 (define_peephole2
   [(set (match_operand:SI 0 "nonimmediate_operand" "")
         (match_operand:SI 1 "general_operand" ""))
    (set (match_operand:SI 2 "nonimmediate_operand" "")
         (match_operand:SI 3 "general_operand" ""))]
   "0 && vax_decomposed_dimode_operand_p (operands[1], operands[3])
    && vax_decomposed_dimode_operand_p (operands[0], operands[2])"
   [(set (match_dup 0)
         (match_dup 1))]
   "{
     operands[0] = REG_P (operands[0])
       ? gen_rtx_REG(DImode, REGNO (operands[0]))
       : gen_rtx_MEM(DImode, XEXP (operands[0], 0));
     operands[1] = REG_P (operands[1])
       ? gen_rtx_REG(DImode, REGNO (operands[1]))
       : gen_rtx_MEM(DImode, XEXP (operands[1], 0));
 }")

 @@ -1,112 +1,98 @@
 /* Target definitions for GNU compiler for VAX using ELF
    Copyright (C) 2002-2015 Free Software Foundation, Inc.
    Contributed by Matt Thomas <matt@3am-software.com>
 This file is part of GCC.
 GCC is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 3, or (at your option)
 any later version.
 GCC is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 You should have received a copy of the GNU General Public License
 along with GCC; see the file COPYING3.  If not see
 <http://www.gnu.org/licenses/>.  */
 #undef TARGET_ELF
 #define TARGET_ELF 1
 #undef REGISTER_PREFIX
 #undef REGISTER_NAMES
 #define REGISTER_PREFIX "%"
 #define REGISTER_NAMES \
   { "%r0", "%r1",  "%r2",  "%r3", "%r4", "%r5", "%r6", "%r7", \
     "%r8", "%r9", "%r10", "%r11", "%ap", "%fp", "%sp", "%pc", }
 #undef SIZE_TYPE
 #define SIZE_TYPE "long unsigned int"
 #undef PTRDIFF_TYPE
 #define PTRDIFF_TYPE "long int"
 /* Profiling routine.  */
 #undef VAX_FUNCTION_PROFILER_NAME
 #define VAX_FUNCTION_PROFILER_NAME "__mcount"
 /*  Let's be re-entrant.  */
 #undef PCC_STATIC_STRUCT_RETURN
 /* Before the prologue, the top of the frame is below the argument
    count pushed by the CALLS and before the start of the saved registers.  */
 #define INCOMING_FRAME_SP_OFFSET 0
-/* Offset from the frame pointer register value to the top of the stack.  */
+/* We use R2-R3 (call-clobbered) registers for exceptions.  */
-#define FRAME_POINTER_CFA_OFFSET(FNDECL) 0
+#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) + 2 : INVALID_REGNUM)
 /* We use R2-R5 (call-clobbered) registers for exceptions.  */
 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 2 : INVALID_REGNUM)
 /* Place the top of the stack for the DWARF2 EH stackadj value.  */
 #define EH_RETURN_STACKADJ_RTX						\
   gen_rtx_MEM (SImode,							\
 	       plus_constant (Pmode,					\
 			      gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM),\
 			      -4))
 /* Simple store the return handler into the call frame.  */
 #define EH_RETURN_HANDLER_RTX						\
   gen_rtx_MEM (Pmode,							\
 	       plus_constant (Pmode,					\
 			      gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM),\
 ))
 /* Reserve the top of the stack for exception handler stackadj value.  */
 #undef STARTING_FRAME_OFFSET
 #define STARTING_FRAME_OFFSET -4
 /* The VAX wants no space between the case instruction and the jump table.  */
 #undef  ASM_OUTPUT_BEFORE_CASE_LABEL
 #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE)
 #undef SUBTARGET_OVERRIDE_OPTIONS
 #define SUBTARGET_OVERRIDE_OPTIONS			\
   do							\
     {							\
       /* Turn off function CSE if we're doing PIC.  */	\
       if (flag_pic)					\
 	flag_no_function_cse = 1;			\
     }							\
   while (0)
 /* Don't allow *foo which foo is non-local */
 #define NO_EXTERNAL_INDIRECT_ADDRESS
 #undef VAX_CC1_AND_CC1PLUS_SPEC
 #define VAX_CC1_AND_CC1PLUS_SPEC \
   "%{!fno-pic: \
      %{!fpic: \
        %{!fPIC:-fPIC}}}"
 /* VAX ELF is always gas; override the generic VAX ASM_SPEC.  */
 #undef ASM_SPEC
 #define ASM_SPEC "%{!fno-pic: %{!mno-asm-pic:-k}}"
 /*  We want PCREL dwarf output.  */
 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL)	\
   ((GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4)
 /* Emit a PC-relative relocation.  */
 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL)	\
   do {							\
     fputs (integer_asm_op (SIZE, FALSE), FILE);		\
     fprintf (FILE, "%%pcrel%d(", SIZE * 8);		\
     assemble_name (FILE, LABEL);			\
     fprintf (FILE, "%+d)", SIZE);			\
   } while (0)