 @@ -1,1701 +1,1701 @@
-/*	$NetBSD: ohci.c,v 1.254.2.66 2016/04/01 14:13:29 skrll Exp $	*/
+/*	$NetBSD: ohci.c,v 1.254.2.67 2016/04/01 14:17:24 skrll Exp $	*/
 /*
  * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Lennart Augustsson (lennart@augustsson.net) at
  * Carlstedt Research & Technology, Jared D. McNeill (jmcneill@invisible.ca)
  * and Matthew R. Green (mrg@eterna.com.au).
  * This code is derived from software contributed to The NetBSD Foundation
  * by Charles M. Hannum.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * USB Open Host Controller driver.
+ *
  * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html
  * USB spec: http://www.usb.org/developers/docs/
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.254.2.66 2016/04/01 14:13:29 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.254.2.67 2016/04/01 14:17:24 skrll Exp $");
 #include "opt_usb.h"
 #include <sys/param.h>
 #include <sys/cpu.h>
 #include <sys/device.h>
 #include <sys/kernel.h>
 #include <sys/kmem.h>
 #include <sys/proc.h>
 #include <sys/queue.h>
 #include <sys/select.h>
 #include <sys/sysctl.h>
 #include <sys/systm.h>
 #include <machine/endian.h>
 #include <dev/usb/usb.h>
 #include <dev/usb/usbdi.h>
 #include <dev/usb/usbdivar.h>
 #include <dev/usb/usb_mem.h>
 #include <dev/usb/usb_quirks.h>
 #include <dev/usb/ohcireg.h>
 #include <dev/usb/ohcivar.h>
 #include <dev/usb/usbroothub.h>
 #include <dev/usb/usbhist.h>
 #ifdef USB_DEBUG
 #ifndef OHCI_DEBUG
 #define ohcidebug 0
 #else
 static int ohcidebug = 10;
 SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup")
+{
 	int err;
 	const struct sysctlnode *rnode;
 	const struct sysctlnode *cnode;
 	err = sysctl_createv(clog, 0, NULL, &rnode,
 	    CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci",
 	    SYSCTL_DESCR("ohci global controls"),
 	    NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
 	if (err)
 		goto fail;
 	/* control debugging printfs */
 	err = sysctl_createv(clog, 0, &rnode, &cnode,
 	    CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
 	    "debug", SYSCTL_DESCR("Enable debugging output"),
 	    NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL);
 	if (err)
 		goto fail;
 	return;
 fail:
 	aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err);
+}
 #endif /* OHCI_DEBUG */
 #endif /* USB_DEBUG */
 #define	DPRINTF(FMT,A,B,C,D)	USBHIST_LOG(ohcidebug,FMT,A,B,C,D)
 #define	DPRINTFN(N,FMT,A,B,C,D)	USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D)
 #define	OHCIHIST_FUNC()		USBHIST_FUNC()
 #define	OHCIHIST_CALLED(name)	USBHIST_CALLED(ohcidebug)
 #if BYTE_ORDER == BIG_ENDIAN
 #define	SWAP_ENDIAN	OHCI_LITTLE_ENDIAN
 #else
 #define	SWAP_ENDIAN	OHCI_BIG_ENDIAN
 #endif
 #define	O16TOH(val)	(sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val)
 #define	O32TOH(val)	(sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val)
 #define	HTOO16(val)	O16TOH(val)
 #define	HTOO32(val)	O32TOH(val)
 struct ohci_pipe;
 Static ohci_soft_ed_t  *ohci_alloc_sed(ohci_softc_t *);
 Static void		ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *);
 Static ohci_soft_td_t  *ohci_alloc_std(ohci_softc_t *);
 Static void		ohci_free_std(ohci_softc_t *, ohci_soft_td_t *);
 Static void		ohci_free_std_locked(ohci_softc_t *, ohci_soft_td_t *);
 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *);
 Static void		ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *);
 Static void		ohci_free_sitd_locked(ohci_softc_t *,
 			    ohci_soft_itd_t *);
 Static usbd_status	ohci_alloc_std_chain(ohci_softc_t *, struct usbd_xfer *,
 			    int, int);
 Static void		ohci_free_stds(ohci_softc_t *, struct ohci_xfer *);
 Static void		ohci_reset_std_chain(ohci_softc_t *, struct usbd_xfer *,
 			    int, int, ohci_soft_td_t *, ohci_soft_td_t **);
 Static usbd_status	ohci_open(struct usbd_pipe *);
 Static void		ohci_poll(struct usbd_bus *);
 Static void		ohci_softintr(void *);
 Static void		ohci_waitintr(ohci_softc_t *, struct usbd_xfer *);
 Static void		ohci_rhsc(ohci_softc_t *, struct usbd_xfer *);
 Static void		ohci_rhsc_softint(void *);
 Static void		ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *,
 			    ohci_soft_ed_t *);
 Static void		ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *,
 				    ohci_soft_ed_t *);
 Static void		ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *);
 Static void		ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *);
 Static ohci_soft_td_t  *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t);
 Static void		ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *);
 Static void		ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *);
 Static ohci_soft_itd_t  *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t);
 Static usbd_status	ohci_setup_isoc(struct usbd_pipe *);
 Static void		ohci_device_isoc_enter(struct usbd_xfer *);
 Static struct usbd_xfer *
 			ohci_allocx(struct usbd_bus *, unsigned int);
 Static void		ohci_freex(struct usbd_bus *, struct usbd_xfer *);
 Static void		ohci_get_lock(struct usbd_bus *, kmutex_t **);
 Static int		ohci_roothub_ctrl(struct usbd_bus *,
 			    usb_device_request_t *, void *, int);
 Static usbd_status	ohci_root_intr_transfer(struct usbd_xfer *);
 Static usbd_status	ohci_root_intr_start(struct usbd_xfer *);
 Static void		ohci_root_intr_abort(struct usbd_xfer *);
 Static void		ohci_root_intr_close(struct usbd_pipe *);
 Static void		ohci_root_intr_done(struct usbd_xfer *);
 Static int		ohci_device_ctrl_init(struct usbd_xfer *);
 Static void		ohci_device_ctrl_fini(struct usbd_xfer *);
 Static usbd_status	ohci_device_ctrl_transfer(struct usbd_xfer *);
 Static usbd_status	ohci_device_ctrl_start(struct usbd_xfer *);
 Static void		ohci_device_ctrl_abort(struct usbd_xfer *);
 Static void		ohci_device_ctrl_close(struct usbd_pipe *);
 Static void		ohci_device_ctrl_done(struct usbd_xfer *);
 Static int		ohci_device_bulk_init(struct usbd_xfer *);
 Static void		ohci_device_bulk_fini(struct usbd_xfer *);
 Static usbd_status	ohci_device_bulk_transfer(struct usbd_xfer *);
 Static usbd_status	ohci_device_bulk_start(struct usbd_xfer *);
 Static void		ohci_device_bulk_abort(struct usbd_xfer *);
 Static void		ohci_device_bulk_close(struct usbd_pipe *);
 Static void		ohci_device_bulk_done(struct usbd_xfer *);
 Static int		ohci_device_intr_init(struct usbd_xfer *);
 Static void		ohci_device_intr_fini(struct usbd_xfer *);
 Static usbd_status	ohci_device_intr_transfer(struct usbd_xfer *);
 Static usbd_status	ohci_device_intr_start(struct usbd_xfer *);
 Static void		ohci_device_intr_abort(struct usbd_xfer *);
 Static void		ohci_device_intr_close(struct usbd_pipe *);
 Static void		ohci_device_intr_done(struct usbd_xfer *);
 Static int		ohci_device_isoc_init(struct usbd_xfer *);
 Static void		ohci_device_isoc_fini(struct usbd_xfer *);
 Static usbd_status	ohci_device_isoc_transfer(struct usbd_xfer *);
 Static void		ohci_device_isoc_abort(struct usbd_xfer *);
 Static void		ohci_device_isoc_close(struct usbd_pipe *);
 Static void		ohci_device_isoc_done(struct usbd_xfer *);
 Static usbd_status	ohci_device_setintr(ohci_softc_t *,
 			    struct ohci_pipe *, int);
 Static void		ohci_timeout(void *);
 Static void		ohci_timeout_task(void *);
 Static void		ohci_rhsc_enable(void *);
 Static void		ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *);
 Static void		ohci_abort_xfer(struct usbd_xfer *, usbd_status);
 Static void		ohci_device_clear_toggle(struct usbd_pipe *);
 Static void		ohci_noop(struct usbd_pipe *);
 #ifdef OHCI_DEBUG
 Static void		ohci_dumpregs(ohci_softc_t *);
 Static void		ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *);
 Static void		ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *);
 Static void		ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *);
 Static void		ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *);
 Static void		ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *);
 #endif
 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \
 			BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
 #define OWRITE1(sc, r, x) \
  do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0)
 #define OWRITE2(sc, r, x) \
  do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0)
 #define OWRITE4(sc, r, x) \
  do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0)
 static __inline uint32_t
 OREAD4(ohci_softc_t *sc, bus_size_t r)
+{
 	OBARR(sc);
 	return bus_space_read_4(sc->iot, sc->ioh, r);
+}
 /* Reverse the bits in a value 0 .. 31 */
 Static uint8_t revbits[OHCI_NO_INTRS] =
   { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c,
 x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e,
 x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d,
 x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f };
 struct ohci_pipe {
 	struct usbd_pipe pipe;
 	ohci_soft_ed_t *sed;
 	union {
 		ohci_soft_td_t *td;
 		ohci_soft_itd_t *itd;
 	} tail;
 	/* Info needed for different pipe kinds. */
 	union {
 		/* Control pipe */
 		struct {
 			usb_dma_t reqdma;
 		} ctrl;
 		/* Interrupt pipe */
 		struct {
 			int nslots;
 			int pos;
 		} intr;
 		/* Isochronous pipe */
 		struct isoc {
 			int next, inuse;
 		} isoc;
 	};
 };
 Static const struct usbd_bus_methods ohci_bus_methods = {
 	.ubm_open =	ohci_open,
 	.ubm_softint =	ohci_softintr,
 	.ubm_dopoll =	ohci_poll,
 	.ubm_allocx =	ohci_allocx,
 	.ubm_freex =	ohci_freex,
 	.ubm_getlock =	ohci_get_lock,
 	.ubm_rhctrl =	ohci_roothub_ctrl,
 };
 Static const struct usbd_pipe_methods ohci_root_intr_methods = {
 	.upm_transfer =	ohci_root_intr_transfer,
 	.upm_start =	ohci_root_intr_start,
 	.upm_abort =	ohci_root_intr_abort,
 	.upm_close =	ohci_root_intr_close,
 	.upm_cleartoggle =	ohci_noop,
 	.upm_done =	ohci_root_intr_done,
 };
 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = {
 	.upm_init =	ohci_device_ctrl_init,
 	.upm_fini =	ohci_device_ctrl_fini,
 	.upm_transfer =	ohci_device_ctrl_transfer,
 	.upm_start =	ohci_device_ctrl_start,
 	.upm_abort =	ohci_device_ctrl_abort,
 	.upm_close =	ohci_device_ctrl_close,
 	.upm_cleartoggle =	ohci_noop,
 	.upm_done =	ohci_device_ctrl_done,
 };
 Static const struct usbd_pipe_methods ohci_device_intr_methods = {
 	.upm_init =	ohci_device_intr_init,
 	.upm_fini =	ohci_device_intr_fini,
 	.upm_transfer =	ohci_device_intr_transfer,
 	.upm_start =	ohci_device_intr_start,
 	.upm_abort =	ohci_device_intr_abort,
 	.upm_close =	ohci_device_intr_close,
 	.upm_cleartoggle =	ohci_device_clear_toggle,
 	.upm_done =	ohci_device_intr_done,
 };
 Static const struct usbd_pipe_methods ohci_device_bulk_methods = {
 	.upm_init =	ohci_device_bulk_init,
 	.upm_fini =	ohci_device_bulk_fini,
 	.upm_transfer =	ohci_device_bulk_transfer,
 	.upm_start =	ohci_device_bulk_start,
 	.upm_abort =	ohci_device_bulk_abort,
 	.upm_close =	ohci_device_bulk_close,
 	.upm_cleartoggle =	ohci_device_clear_toggle,
 	.upm_done =	ohci_device_bulk_done,
 };
 Static const struct usbd_pipe_methods ohci_device_isoc_methods = {
 	.upm_init =	ohci_device_isoc_init,
 	.upm_fini =	ohci_device_isoc_fini,
 	.upm_transfer =	ohci_device_isoc_transfer,
 	.upm_abort =	ohci_device_isoc_abort,
 	.upm_close =	ohci_device_isoc_close,
 	.upm_cleartoggle =	ohci_noop,
 	.upm_done =	ohci_device_isoc_done,
 };
 int
 ohci_activate(device_t self, enum devact act)
+{
 	struct ohci_softc *sc = device_private(self);
 	switch (act) {
 	case DVACT_DEACTIVATE:
 		sc->sc_dying = 1;
 		return 0;
 	default:
 		return EOPNOTSUPP;
+	}
+}
 void
 ohci_childdet(device_t self, device_t child)
+{
 	struct ohci_softc *sc = device_private(self);
 	KASSERT(sc->sc_child == child);
 	sc->sc_child = NULL;
+}
 int
 ohci_detach(struct ohci_softc *sc, int flags)
+{
 	int rv = 0;
 	if (sc->sc_child != NULL)
 		rv = config_detach(sc->sc_child, flags);
 	if (rv != 0)
 		return rv;
 	callout_halt(&sc->sc_tmo_rhsc, &sc->sc_lock);
 	usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */
 	callout_destroy(&sc->sc_tmo_rhsc);
 	softint_disestablish(sc->sc_rhsc_si);
 	cv_destroy(&sc->sc_softwake_cv);
 	mutex_destroy(&sc->sc_lock);
 	mutex_destroy(&sc->sc_intr_lock);
 	if (sc->sc_hcca != NULL)
 		usb_freemem(&sc->sc_bus, &sc->sc_hccadma);
 	pool_cache_destroy(sc->sc_xferpool);
 	return rv;
+}
 ohci_soft_ed_t *
 ohci_alloc_sed(ohci_softc_t *sc)
+{
 	ohci_soft_ed_t *sed;
 	usbd_status err;
 	int i, offs;
 	usb_dma_t dma;
 	OHCIHIST_FUNC(); OHCIHIST_CALLED();
 	mutex_enter(&sc->sc_lock);
 	if (sc->sc_freeeds == NULL) {
 		DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
 		mutex_exit(&sc->sc_lock);
 		err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK,
 			  OHCI_ED_ALIGN, &dma);
 		if (err)
 			return 0;
 		mutex_enter(&sc->sc_lock);
 		for (i = 0; i < OHCI_SED_CHUNK; i++) {
 			offs = i * OHCI_SED_SIZE;
 			sed = KERNADDR(&dma, offs);
 			sed->physaddr = DMAADDR(&dma, offs);
 			sed->dma = dma;
 			sed->offs = offs;
 			sed->next = sc->sc_freeeds;
 			sc->sc_freeeds = sed;
+		}
+	}
 	sed = sc->sc_freeeds;
 	sc->sc_freeeds = sed->next;
 	mutex_exit(&sc->sc_lock);
 	memset(&sed->ed, 0, sizeof(ohci_ed_t));
 	sed->next = 0;
 	return sed;
+}
 static inline void
 ohci_free_sed_locked(ohci_softc_t *sc, ohci_soft_ed_t *sed)
+{
 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
 	sed->next = sc->sc_freeeds;
 	sc->sc_freeeds = sed;
+}
 void
 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed)
+{
 	mutex_enter(&sc->sc_lock);
 	ohci_free_sed_locked(sc, sed);
 	mutex_exit(&sc->sc_lock);
+}
 ohci_soft_td_t *
 ohci_alloc_std(ohci_softc_t *sc)
+{
 	ohci_soft_td_t *std;
 	usbd_status err;
 	int i, offs;
 	usb_dma_t dma;
 	OHCIHIST_FUNC(); OHCIHIST_CALLED();
 	mutex_enter(&sc->sc_lock);
 	if (sc->sc_freetds == NULL) {
 		DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
 		mutex_exit(&sc->sc_lock);
 		err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK,
 			  OHCI_TD_ALIGN, &dma);
 		if (err)
 			return NULL;
 		mutex_enter(&sc->sc_lock);
 		for (i = 0; i < OHCI_STD_CHUNK; i++) {
 			offs = i * OHCI_STD_SIZE;
 			std = KERNADDR(&dma, offs);
 			std->physaddr = DMAADDR(&dma, offs);
 			std->dma = dma;
 			std->offs = offs;
 			std->nexttd = sc->sc_freetds;
 			sc->sc_freetds = std;
+		}
+	}
 	std = sc->sc_freetds;
 	sc->sc_freetds = std->nexttd;
 	mutex_exit(&sc->sc_lock);
 	memset(&std->td, 0, sizeof(ohci_td_t));
 	std->nexttd = NULL;
 	std->xfer = NULL;
 	return std;
+}
 void
 ohci_free_std_locked(ohci_softc_t *sc, ohci_soft_td_t *std)
+{
 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
 	std->nexttd = sc->sc_freetds;
 	sc->sc_freetds = std;
+}
 void
 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std)
+{
 	mutex_enter(&sc->sc_lock);
 	ohci_free_std_locked(sc, std);
 	mutex_exit(&sc->sc_lock);
+}
 Static usbd_status
 ohci_alloc_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, int alen, int rd)
+{
 	struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
 	struct usbd_pipe *pipe = xfer->ux_pipe;
 	ohci_soft_td_t *next, *cur;
 	ohci_physaddr_t dataphys, dataphysend;
 	int len = alen;
 	int curlen;
 	usb_dma_t *dma = &xfer->ux_dmabuf;
 	uint16_t flags = xfer->ux_flags;
 	OHCIHIST_FUNC(); OHCIHIST_CALLED();
 	DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d",
 	    pipe->up_dev->ud_addr,
 	    UE_GET_ADDR(pipe->up_endpoint->ue_edesc->bEndpointAddress),
 	    alen, pipe->up_dev->ud_speed);
 	ASSERT_SLEEPABLE();
 	size_t nstd = (flags & USBD_FORCE_SHORT_XFER) ? 1 : 0;
 	nstd += ((len + OHCI_PAGE_SIZE - 1) / OHCI_PAGE_SIZE);
 	ox->ox_stds = kmem_zalloc(sizeof(ohci_soft_td_t *) * nstd,
 	    KM_SLEEP);
 	ox->ox_nstd = nstd;
 	int mps = UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize);
 	DPRINTFN(8, "xfer %p nstd %d mps %d", xfer, nstd, mps, 0);
 	len = alen;
 	cur = ohci_alloc_std(sc);
 	if (cur == NULL)
 		goto nomem;
 	dataphys = DMAADDR(dma, 0);
 	dataphysend = OHCI_PAGE(dataphys + len - 1);
 	const uint32_t tdflags = HTOO32(
 	    (rd ? OHCI_TD_IN : OHCI_TD_OUT) |
 	    OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR);
 	for (size_t j = 0;;) {
 		ox->ox_stds[j++] = cur;
 		next = ohci_alloc_std(sc);
 		if (next == NULL)
 			goto nomem;
 		/* The OHCI hardware can handle at most one page crossing. */
 		if (OHCI_PAGE(dataphys) == dataphysend ||
 		    OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) {
 			/* we can handle it in this TD */
 			curlen = len;
 		} else {
 			/* must use multiple TDs, fill as much as possible. */
 			curlen = 2 * OHCI_PAGE_SIZE -
 			    (dataphys & (OHCI_PAGE_SIZE - 1));
 			/* the length must be a multiple of the max size */
 			curlen -= curlen % mps;
 			KASSERT(curlen != 0);
+		}
 		DPRINTFN(4, "dataphys=0x%08x dataphysend=0x%08x "
 		    "len=%d curlen=%d", dataphys, dataphysend, len, curlen);
 		len -= curlen;
 		cur->td.td_flags = tdflags;
 		cur->td.td_cbp = HTOO32(dataphys);
 		cur->td.td_nexttd = HTOO32(next->physaddr);
 		cur->td.td_be = HTOO32(dataphys + curlen - 1);
 		cur->nexttd = next;
 		cur->len = curlen;
 		cur->flags = OHCI_ADD_LEN;
 		cur->xfer = xfer;
 		DPRINTFN(10, "cbp=0x%08x be=0x%08x", dataphys,
 		    dataphys + curlen - 1, 0, 0);
 		if (len == 0)
 			break;
 		DPRINTFN(10, "extend chain", 0, 0, 0, 0);
 		dataphys += curlen;
 		cur = next;
+	}
 	if (!rd && (flags & USBD_FORCE_SHORT_XFER) &&
 	    alen % mps == 0) {
 		/* Force a 0 length transfer at the end. */
 		cur = next;
 		next = ohci_alloc_std(sc);
 		if (next == NULL)
 			goto nomem;
 		cur->td.td_flags = tdflags;
 		cur->td.td_cbp = 0; /* indicate 0 length packet */
 		cur->td.td_nexttd = HTOO32(next->physaddr);
 		cur->td.td_be = ~0;
 		cur->nexttd = next;
 		cur->len = 0;
 		cur->flags = 0;
 		cur->xfer = xfer;
 		DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0);
+	}
 	return USBD_NORMAL_COMPLETION;
  nomem:
 	ohci_free_stds(sc, ox);
 	return USBD_NOMEM;
+}
 Static void
 ohci_free_stds(ohci_softc_t *sc, struct ohci_xfer *ox)
+{
 	OHCIHIST_FUNC(); OHCIHIST_CALLED();
 	DPRINTF("ox=%p", ox, 0, 0, 0);
 	mutex_enter(&sc->sc_lock);
 	for (size_t i = 0; i < ox->ox_nstd; i++) {
 		ohci_soft_td_t *std = ox->ox_stds[i];
 		if (std == NULL)
 			break;
 		ohci_free_std_locked(sc, std);
+	}
 	mutex_exit(&sc->sc_lock);
+}
 void
 ohci_reset_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer,
     int alen, int rd, ohci_soft_td_t *sp, ohci_soft_td_t **ep)
+{
 	struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
 	ohci_soft_td_t *next, *cur;
 	ohci_physaddr_t dataphys, dataphysend;
 	int len, curlen;
 	usb_dma_t *dma = &xfer->ux_dmabuf;
 	uint16_t flags = xfer->ux_flags;
 	OHCIHIST_FUNC(); OHCIHIST_CALLED();
 	DPRINTF("start len=%d", alen, 0, 0, 0);
 	KASSERT(mutex_owned(&sc->sc_lock));
 	DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d",
 	    xfer->ux_pipe->up_dev->ud_addr,
 	    UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress),
 	    alen, xfer->ux_pipe->up_dev->ud_speed);
 	KASSERT(sp);
 	int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize);
 	len = alen;
 	cur = sp;
 	dataphys = DMAADDR(dma, 0);
 	dataphysend = OHCI_PAGE(dataphys + len - 1);
 	usb_syncmem(dma, 0, len,
 	    rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
 	const uint32_t tdflags = HTOO32(
 	    (rd ? OHCI_TD_IN : OHCI_TD_OUT) |
 	    OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR);
 	for (size_t j = 1;;) {
 		if (j == ox->ox_nstd)
 			next = NULL;
 		else
 			next = ox->ox_stds[j++];
 		KASSERT(next != cur);
 		/* The OHCI hardware can handle at most one page crossing. */
 		if (OHCI_PAGE(dataphys) == dataphysend ||
 		    OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) {
 			/* we can handle it in this TD */
 			curlen = len;
 		} else {
 			/* must use multiple TDs, fill as much as possible. */
 			curlen = 2 * OHCI_PAGE_SIZE -
 			    (dataphys & (OHCI_PAGE_SIZE - 1));
 			/* the length must be a multiple of the max size */
 			curlen -= curlen % mps;
 			KASSERT(curlen != 0);
+		}
 		DPRINTFN(4, "dataphys=0x%08x dataphysend=0x%08x "
-		    "len=%d curlen=%d",  dataphys, dataphysend, len, curlen);
+		    "len=%d curlen=%d", dataphys, dataphysend, len, curlen);
 		len -= curlen;
 		cur->td.td_flags = tdflags;
 		cur->td.td_cbp = HTOO32(dataphys);
 		cur->td.td_be = HTOO32(dataphys + curlen - 1);
 		cur->td.td_nexttd = (next != NULL) ? HTOO32(next->physaddr) : 0;
 		cur->nexttd = next;
 		cur->len = curlen;
 		cur->flags = OHCI_ADD_LEN;
 		cur->xfer = xfer;
 	 	ohci_hash_add_td(sc, cur);
 		usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td),
 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
 		DPRINTFN(10, "cbp=0x%08x be=0x%08x", dataphys,
 		    dataphys + curlen - 1, 0, 0);
 		if (len == 0)
 			break;
 		KASSERT(next != NULL);
 		DPRINTFN(10, "extend chain", 0, 0, 0, 0);
 		dataphys += curlen;
 		cur = next;
+	}
 	cur->td.td_flags |=
 	    (xfer->ux_flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0);
 	if (!rd &&
 	    (flags & USBD_FORCE_SHORT_XFER) &&
 	    alen % mps == 0) {
 		/* Force a 0 length transfer at the end. */
 		KASSERT(next != NULL);
 		cur = next;
 		cur->td.td_flags = tdflags;
 		cur->td.td_cbp = 0; /* indicate 0 length packet */
 		cur->td.td_nexttd = HTOO32(next->physaddr);
 		cur->td.td_be = ~0;
 		cur->nexttd = NULL;
 		cur->len = 0;
 		cur->flags = 0;
 		cur->xfer = xfer;
 	 	ohci_hash_add_td(sc, cur);
 		usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td),
 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
 		DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0);
+	}
 	*ep = cur;
+}
 ohci_soft_itd_t *
 ohci_alloc_sitd(ohci_softc_t *sc)
+{
 	ohci_soft_itd_t *sitd;
 	usbd_status err;
 	int i, offs;
 	usb_dma_t dma;
 	OHCIHIST_FUNC(); OHCIHIST_CALLED();
 	mutex_enter(&sc->sc_lock);
 	if (sc->sc_freeitds == NULL) {
 		DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
 		mutex_exit(&sc->sc_lock);
 		err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK,
 			  OHCI_ITD_ALIGN, &dma);
 		if (err)
 			return NULL;
 		mutex_enter(&sc->sc_lock);
 		for (i = 0; i < OHCI_SITD_CHUNK; i++) {
 			offs = i * OHCI_SITD_SIZE;
 			sitd = KERNADDR(&dma, offs);
 			sitd->physaddr = DMAADDR(&dma, offs);
 			sitd->dma = dma;
 			sitd->offs = offs;
 			sitd->nextitd = sc->sc_freeitds;
 			sc->sc_freeitds = sitd;
+		}
+	}
 	sitd = sc->sc_freeitds;
 	sc->sc_freeitds = sitd->nextitd;
 	mutex_exit(&sc->sc_lock);
 	memset(&sitd->itd, 0, sizeof(ohci_itd_t));
 	sitd->nextitd = NULL;
 	sitd->xfer = NULL;
 #ifdef DIAGNOSTIC
 	sitd->isdone = true;
 #endif
 	return sitd;
+}
 Static void
 ohci_free_sitd_locked(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
+{
 	OHCIHIST_FUNC(); OHCIHIST_CALLED();
 	DPRINTFN(10, "sitd=%p", sitd, 0, 0, 0);
 	KASSERT(sitd->isdone);
 #ifdef DIAGNOSTIC
 	/* Warn double free */
 	sitd->isdone = false;
 #endif
 	sitd->nextitd = sc->sc_freeitds;
 	sc->sc_freeitds = sitd;
+}
 void
 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
+{
 	OHCIHIST_FUNC(); OHCIHIST_CALLED();
 	mutex_enter(&sc->sc_lock);
 	ohci_free_sitd_locked(sc, sitd);
 	mutex_exit(&sc->sc_lock);
+}
 int
 ohci_init(ohci_softc_t *sc)
+{
 	ohci_soft_ed_t *sed, *psed;
 	usbd_status err;
 	int i;
 	uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */;
 	OHCIHIST_FUNC(); OHCIHIST_CALLED();
 	aprint_normal_dev(sc->sc_dev, "");
 	sc->sc_hcca = NULL;
 	callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE);
 	mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
 	mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB);
 	cv_init(&sc->sc_softwake_cv, "ohciab");
 	sc->sc_rhsc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE,
 	    ohci_rhsc_softint, sc);
 	for (i = 0; i < OHCI_HASH_SIZE; i++)
 		LIST_INIT(&sc->sc_hash_tds[i]);
 	for (i = 0; i < OHCI_HASH_SIZE; i++)
 		LIST_INIT(&sc->sc_hash_itds[i]);
 	sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0,
 	    "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL);
 	rev = OREAD4(sc, OHCI_REVISION);
 	aprint_normal("OHCI version %d.%d%s\n",
 	    OHCI_REV_HI(rev), OHCI_REV_LO(rev),
 	    OHCI_REV_LEGACY(rev) ? ", legacy support" : "");
 	if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) {
 		aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n");
 		sc->sc_bus.ub_revision = USBREV_UNKNOWN;
 		return -1;
+	}
 	sc->sc_bus.ub_revision = USBREV_1_0;
 	sc->sc_bus.ub_usedma = true;
 	/* XXX determine alignment by R/W */
 	/* Allocate the HCCA area. */
 	err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE,
 			 OHCI_HCCA_ALIGN, &sc->sc_hccadma);
 	if (err) {
 		sc->sc_hcca = NULL;
 		return err;
+	}
 	sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0);
 	memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE);
 	sc->sc_eintrs = OHCI_NORMAL_INTRS;
 	/* Allocate dummy ED that starts the control list. */
 	sc->sc_ctrl_head = ohci_alloc_sed(sc);
 	if (sc->sc_ctrl_head == NULL) {
 		err = ENOMEM;
 		goto bad1;
+	}
 	sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
 	/* Allocate dummy ED that starts the bulk list. */
 	sc->sc_bulk_head = ohci_alloc_sed(sc);
 	if (sc->sc_bulk_head == NULL) {
 		err = ENOMEM;
 		goto bad2;
+	}
 	sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
 	usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs,
 	    sizeof(sc->sc_bulk_head->ed),
 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
 	/* Allocate dummy ED that starts the isochronous list. */
 	sc->sc_isoc_head = ohci_alloc_sed(sc);
 	if (sc->sc_isoc_head == NULL) {
 		err = ENOMEM;
 		goto bad3;
+	}
 	sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
 	usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs,
 	    sizeof(sc->sc_isoc_head->ed),
 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
 	/* Allocate all the dummy EDs that make up the interrupt tree. */
 	for (i = 0; i < OHCI_NO_EDS; i++) {
 		sed = ohci_alloc_sed(sc);
 		if (sed == NULL) {
 			while (--i >= 0)
 				ohci_free_sed(sc, sc->sc_eds[i]);
 			err = ENOMEM;
 			goto bad4;
+		}
 		/* All ED fields are set to 0. */
 		sc->sc_eds[i] = sed;
 		sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
 		if (i != 0)
 			psed = sc->sc_eds[(i-1) / 2];
 		else
 			psed= sc->sc_isoc_head;
 		sed->next = psed;
 		sed->ed.ed_nexted = HTOO32(psed->physaddr);
 		usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
+	}
 	/*
 	 * Fill HCCA interrupt table.  The bit reversal is to get
 	 * the tree set up properly to spread the interrupts.
 	 */
 	for (i = 0; i < OHCI_NO_INTRS; i++)
 		sc->sc_hcca->hcca_interrupt_table[revbits[i]] =
 		    HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr);
 	usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE,
 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
 #ifdef OHCI_DEBUG
 	DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0);
 	if (ohcidebug >= 15) {
 		for (i = 0; i < OHCI_NO_EDS; i++) {
 			DPRINTFN(15, "ed#%d ", i, 0, 0, 0);
 			ohci_dump_ed(sc, sc->sc_eds[i]);
+		}
 		DPRINTFN(15, "iso", 0, 0, 0 ,0);
 		ohci_dump_ed(sc, sc->sc_isoc_head);
+	}
 	DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0);
 #endif
 	/* Preserve values programmed by SMM/BIOS but lost over reset. */
 	ctl = OREAD4(sc, OHCI_CONTROL);
 	rwc = ctl & OHCI_RWC;
 	fm = OREAD4(sc, OHCI_FM_INTERVAL);
 	desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A);
 	/* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */
 	/* Determine in what context we are running. */
 	if (ctl & OHCI_IR) {
 		/* SMM active, request change */
 		DPRINTF("SMM active, request owner change", 0, 0, 0, 0);
 		if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) ==
 		    (OHCI_OC | OHCI_MIE))
 			OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE);
 		s = OREAD4(sc, OHCI_COMMAND_STATUS);
 		OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR);
 		for (i = 0; i < 100 && (ctl & OHCI_IR); i++) {
 			usb_delay_ms(&sc->sc_bus, 1);
 			ctl = OREAD4(sc, OHCI_CONTROL);
+		}
 		OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE);
 		if ((ctl & OHCI_IR) == 0) {
 			aprint_error_dev(sc->sc_dev,
 			    "SMM does not respond, resetting\n");
 			OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc);
 			goto reset;
+		}
 #if 0
 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */
 	} else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) {
 		/* BIOS started controller. */
 		DPRINTF("BIOS active", 0, 0, 0, 0);
 		if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) {
 			OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc);
 			usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY);
+		}
 #endif
 	} else {
 		DPRINTF("cold started", 0 ,0 ,0 ,0);
 	reset:
 		/* Controller was cold started. */
 		usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY);
+	}
 	/*
 	 * This reset should not be necessary according to the OHCI spec, but
 	 * without it some controllers do not start.
 	 */
 	DPRINTF("sc %p: resetting", sc, 0, 0, 0);
 	OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc);
 	usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY);
 	/* We now own the host controller and the bus has been reset. */
 	OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */
 	/* Nominal time for a reset is 10 us. */
 	for (i = 0; i < 10; i++) {
 		delay(10);
 		hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR;
 		if (!hcr)
 			break;
+	}
 	if (hcr) {
 		aprint_error_dev(sc->sc_dev, "reset timeout\n");
 		err = EIO;
 		goto bad5;
+	}
 #ifdef OHCI_DEBUG
 	if (ohcidebug >= 15)
 		ohci_dumpregs(sc);
 #endif
 	/* The controller is now in SUSPEND state, we have 2ms to finish. */
 	/* Set up HC registers. */
 	OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0));
 	OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr);
 	OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr);
 	/* disable all interrupts and then switch on all desired interrupts */
 	OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
 	/* switch on desired functional features */
 	ctl = OREAD4(sc, OHCI_CONTROL);
 	ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR);
 	ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE |
 		OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc;
 	/* And finally start it! */
 	OWRITE4(sc, OHCI_CONTROL, ctl);
 	/*
 	 * The controller is now OPERATIONAL.  Set a some final
 	 * registers that should be set earlier, but that the
 	 * controller ignores when in the SUSPEND state.
 	 */
 	ival = OHCI_GET_IVAL(fm);
 	fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT;
 	fm |= OHCI_FSMPS(ival) | ival;
 	OWRITE4(sc, OHCI_FM_INTERVAL, fm);
 	per = OHCI_PERIODIC(ival); /* 90% periodic */
 	OWRITE4(sc, OHCI_PERIODIC_START, per);
 	if (sc->sc_flags & OHCIF_SUPERIO) {
 		/* no overcurrent protection */
 		desca |= OHCI_NOCP;
 		/*
 		 * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning
 		 * that
 		 *  - ports are always power switched
 		 *  - don't wait for powered root hub port
 		 */
 		desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS);
+	}
 	/* Fiddle the No OverCurrent Protection bit to avoid chip bug. */
 	OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP);
 	OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */
 	usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY);
 	OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca);
 	/*
 	 * The AMD756 requires a delay before re-reading the register,
 	 * otherwise it will occasionally report 0 ports.
 	 */
 	sc->sc_noport = 0;
 	for (i = 0; i < 10 && sc->sc_noport == 0; i++) {
 		usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY);
 		sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A));
+	}
 #ifdef OHCI_DEBUG
 	if (ohcidebug >= 5)
 		ohci_dumpregs(sc);
 #endif
 	/* Set up the bus struct. */
 	sc->sc_bus.ub_methods = &ohci_bus_methods;
 	sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe);
 	sc->sc_control = sc->sc_intre = 0;
 	/* Finally, turn on interrupts. */
 	DPRINTF("enabling %#x", sc->sc_eintrs | OHCI_MIE, 0, 0, 0);
 	OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE);
 	return 0;
  bad5:
 	for (i = 0; i < OHCI_NO_EDS; i++)
 		ohci_free_sed(sc, sc->sc_eds[i]);
  bad4:
 	ohci_free_sed(sc, sc->sc_isoc_head);
  bad3:
 	ohci_free_sed(sc, sc->sc_bulk_head);
  bad2:
 	ohci_free_sed(sc, sc->sc_ctrl_head);
  bad1:
 	usb_freemem(&sc->sc_bus, &sc->sc_hccadma);
 	sc->sc_hcca = NULL;
 	return err;
+}
 struct usbd_xfer *
 ohci_allocx(struct usbd_bus *bus, unsigned int nframes)
+{
 	ohci_softc_t *sc = OHCI_BUS2SC(bus);
 	struct usbd_xfer *xfer;
 	xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT);
 	if (xfer != NULL) {
 		memset(xfer, 0, sizeof(struct ohci_xfer));
 #ifdef DIAGNOSTIC
 		xfer->ux_state = XFER_BUSY;
 #endif
+	}
 	return xfer;
+}
 void
 ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer)
+{
 	ohci_softc_t *sc = OHCI_BUS2SC(bus);
 	KASSERTMSG(xfer->ux_state == XFER_BUSY,
 	    "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state);
 #ifdef DIAGNOSTIC
 	xfer->ux_state = XFER_FREE;
 #endif
 	pool_cache_put(sc->sc_xferpool, xfer);
+}
 Static void
 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock)
+{
 	ohci_softc_t *sc = OHCI_BUS2SC(bus);
 	*lock = &sc->sc_lock;
+}
 /*
  * Shut down the controller when the system is going down.
  */
 bool
 ohci_shutdown(device_t self, int flags)
+{
 	ohci_softc_t *sc = device_private(self);
 	OHCIHIST_FUNC(); OHCIHIST_CALLED();
 	DPRINTF("stopping the HC", 0, 0, 0, 0);
 	OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
 	return true;
+}
 bool
 ohci_resume(device_t dv, const pmf_qual_t *qual)
+{
 	ohci_softc_t *sc = device_private(dv);
 	uint32_t ctl;
 	mutex_spin_enter(&sc->sc_intr_lock);
 	sc->sc_bus.ub_usepolling++;
 	mutex_spin_exit(&sc->sc_intr_lock);
 	/* Some broken BIOSes do not recover these values */
 	OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0));
 	OWRITE4(sc, OHCI_CONTROL_HEAD_ED,
 	    sc->sc_ctrl_head->physaddr);
 	OWRITE4(sc, OHCI_BULK_HEAD_ED,
 	    sc->sc_bulk_head->physaddr);
 	if (sc->sc_intre)
 		OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre &
 		    (OHCI_ALL_INTRS | OHCI_MIE));
 	if (sc->sc_control)
 		ctl = sc->sc_control;
 	else
 		ctl = OREAD4(sc, OHCI_CONTROL);
 	ctl |= OHCI_HCFS_RESUME;
 	OWRITE4(sc, OHCI_CONTROL, ctl);
 	usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY);
 	ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL;
 	OWRITE4(sc, OHCI_CONTROL, ctl);
 	usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY);
 	sc->sc_control = sc->sc_intre = 0;
 	mutex_spin_enter(&sc->sc_intr_lock);
 	sc->sc_bus.ub_usepolling--;
 	mutex_spin_exit(&sc->sc_intr_lock);
 	return true;
+}
 bool
 ohci_suspend(device_t dv, const pmf_qual_t *qual)
+{
 	ohci_softc_t *sc = device_private(dv);
 	uint32_t ctl;
 	mutex_spin_enter(&sc->sc_intr_lock);
 	sc->sc_bus.ub_usepolling++;
 	mutex_spin_exit(&sc->sc_intr_lock);
 	ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK;
 	if (sc->sc_control == 0) {
 		/*
 		 * Preserve register values, in case that BIOS
 		 * does not recover them.
 		 */
 		sc->sc_control = ctl;
 		sc->sc_intre = OREAD4(sc,
 		    OHCI_INTERRUPT_ENABLE);
+	}
 	ctl |= OHCI_HCFS_SUSPEND;
 	OWRITE4(sc, OHCI_CONTROL, ctl);
 	usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT);
 	mutex_spin_enter(&sc->sc_intr_lock);
 	sc->sc_bus.ub_usepolling--;
 	mutex_spin_exit(&sc->sc_intr_lock);
 	return true;
+}
 #ifdef OHCI_DEBUG
 void
 ohci_dumpregs(ohci_softc_t *sc)
+{
 	OHCIHIST_FUNC(); OHCIHIST_CALLED();
 	DPRINTF("rev=0x%08x control=0x%08x command=0x%08x",
 		 OREAD4(sc, OHCI_REVISION),
 		 OREAD4(sc, OHCI_CONTROL),
 		 OREAD4(sc, OHCI_COMMAND_STATUS), 0);
 	DPRINTF("               intrstat=0x%08x intre=0x%08x intrd=0x%08x",
 		 OREAD4(sc, OHCI_INTERRUPT_STATUS),
 		 OREAD4(sc, OHCI_INTERRUPT_ENABLE),
 		 OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0);
 	DPRINTF("               hcca=0x%08x percur=0x%08x ctrlhd=0x%08x",
 		 OREAD4(sc, OHCI_HCCA),
 		 OREAD4(sc, OHCI_PERIOD_CURRENT_ED),
 		 OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0);
 	DPRINTF("               ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x",
 		 OREAD4(sc, OHCI_CONTROL_CURRENT_ED),
 		 OREAD4(sc, OHCI_BULK_HEAD_ED),
 		 OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0);
 	DPRINTF("               done=0x%08x fmival=0x%08x fmrem=0x%08x",
 		 OREAD4(sc, OHCI_DONE_HEAD),
 		 OREAD4(sc, OHCI_FM_INTERVAL),
 		 OREAD4(sc, OHCI_FM_REMAINING), 0);
 	DPRINTF("               fmnum=0x%08x perst=0x%08x lsthrs=0x%08x",
 		 OREAD4(sc, OHCI_FM_NUMBER),
 		 OREAD4(sc, OHCI_PERIODIC_START),
 		 OREAD4(sc, OHCI_LS_THRESHOLD), 0);
 	DPRINTF("               desca=0x%08x descb=0x%08x stat=0x%08x",
 		 OREAD4(sc, OHCI_RH_DESCRIPTOR_A),
 		 OREAD4(sc, OHCI_RH_DESCRIPTOR_B),
 		 OREAD4(sc, OHCI_RH_STATUS), 0);
 	DPRINTF("               port1=0x%08x port2=0x%08x",
 		 OREAD4(sc, OHCI_RH_PORT_STATUS(1)),
 		 OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0);
 	DPRINTF("         HCCA: frame_number=0x%04x done_head=0x%08x",
 		 O32TOH(sc->sc_hcca->hcca_frame_number),
 		 O32TOH(sc->sc_hcca->hcca_done_head), 0, 0);
+}
 #endif
 Static int ohci_intr1(ohci_softc_t *);
 int
 ohci_intr(void *p)
+{
 	ohci_softc_t *sc = p;
 	int ret = 0;
 	OHCIHIST_FUNC(); OHCIHIST_CALLED();
 	if (sc == NULL)
 		return 0;
 	mutex_spin_enter(&sc->sc_intr_lock);
 	if (sc->sc_dying || !device_has_power(sc->sc_dev))
 		goto done;
 	/* If we get an interrupt while polling, then just ignore it. */
 	if (sc->sc_bus.ub_usepolling) {
 		DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0);
 		/* for level triggered intrs, should do something to ack */
 		OWRITE4(sc, OHCI_INTERRUPT_STATUS,
 			OREAD4(sc, OHCI_INTERRUPT_STATUS));
 		goto done;
+	}
 	ret = ohci_intr1(sc);
 done:
 	mutex_spin_exit(&sc->sc_intr_lock);
 	return ret;
+}
 Static int
 ohci_intr1(ohci_softc_t *sc)
+{
 	uint32_t intrs, eintrs;
 	OHCIHIST_FUNC(); OHCIHIST_CALLED();
 	/* In case the interrupt occurs before initialization has completed. */
 	if (sc == NULL || sc->sc_hcca == NULL) {
 #ifdef DIAGNOSTIC
 		printf("ohci_intr: sc->sc_hcca == NULL\n");
 #endif
 		return 0;
+	}
 	KASSERT(mutex_owned(&sc->sc_intr_lock));
 	intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS);
 	if (!intrs)
 		return 0;
 	/* Acknowledge */
 	OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH));
 	eintrs = intrs & sc->sc_eintrs;
 	DPRINTFN(7, "sc=%p", sc, 0, 0, 0);
 	DPRINTFN(7, "intrs=%#x(%#x) eintrs=%#x(%#x)",
 	    intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs,
 	    sc->sc_eintrs);
 	if (!eintrs) {
 		return 0;
+	}
 	if (eintrs & OHCI_SO) {
 		sc->sc_overrun_cnt++;
 		if (usbd_ratecheck(&sc->sc_overrun_ntc)) {
 			printf("%s: %u scheduling overruns\n",
 			    device_xname(sc->sc_dev), sc->sc_overrun_cnt);
 			sc->sc_overrun_cnt = 0;
+		}
 		/* XXX do what */
 		eintrs &= ~OHCI_SO;
+	}
 	if (eintrs & OHCI_WDH) {
 		/*
 		 * We block the interrupt below, and reenable it later from
 		 * ohci_softintr().
 		 */
 		usb_schedsoftintr(&sc->sc_bus);
+	}
 	if (eintrs & OHCI_RD) {
 		DPRINTFN(5, "resume detect", sc, 0, 0, 0);
 		printf("%s: resume detect\n", device_xname(sc->sc_dev));
 		/* XXX process resume detect */
+	}
 	if (eintrs & OHCI_UE) {
 		DPRINTFN(5, "unrecoverable error", sc, 0, 0, 0);
 		printf("%s: unrecoverable error, controller halted\n",
 		       device_xname(sc->sc_dev));
 		OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
 		/* XXX what else */
+	}
 	if (eintrs & OHCI_RHSC) {
 		/*
 		 * We block the interrupt below, and reenable it later from
 		 * a timeout.
 		 */
 		softint_schedule(sc->sc_rhsc_si);
+	}
 	if (eintrs != 0) {
 		/* Block unprocessed interrupts. */
 		OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs);
 		sc->sc_eintrs &= ~eintrs;
 		DPRINTF("sc %p blocking intrs 0x%x", sc, eintrs, 0, 0);
+	}
 	return 1;
+}
 void
 ohci_rhsc_enable(void *v_sc)
+{
 	ohci_softc_t *sc = v_sc;
 	OHCIHIST_FUNC(); OHCIHIST_CALLED();
 	DPRINTF("sc %p", sc, 0, 0, 0);
 	mutex_spin_enter(&sc->sc_intr_lock);
 	sc->sc_eintrs |= OHCI_RHSC;
 	OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC);
 	mutex_spin_exit(&sc->sc_intr_lock);
+}
 #ifdef OHCI_DEBUG
 const char *ohci_cc_strs[] = {
 	"NO_ERROR",
 	"CRC",
 	"BIT_STUFFING",
 	"DATA_TOGGLE_MISMATCH",
 	"STALL",
 	"DEVICE_NOT_RESPONDING",
 	"PID_CHECK_FAILURE",
 	"UNEXPECTED_PID",
 	"DATA_OVERRUN",
 	"DATA_UNDERRUN",
 	"BUFFER_OVERRUN",
 	"BUFFER_UNDERRUN",
 	"reserved",
 	"reserved",
 	"NOT_ACCESSED",
 	"NOT_ACCESSED",
 };
 #endif
 void
 ohci_softintr(void *v)
+{
 	struct usbd_bus *bus = v;
 	ohci_softc_t *sc = OHCI_BUS2SC(bus);
 	ohci_soft_itd_t *sitd, *sidone, *sitdnext;
 	ohci_soft_td_t  *std,  *sdone,  *stdnext;
 	struct usbd_xfer *xfer;
 	struct ohci_pipe *opipe;
 	int len, cc;
 	int i, j, actlen, iframes, uedir;
 	ohci_physaddr_t done;
 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
 	OHCIHIST_FUNC(); OHCIHIST_CALLED();
 	usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head),
 	    sizeof(sc->sc_hcca->hcca_done_head),
 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
 	done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS;
 	sc->sc_hcca->hcca_done_head = 0;
 	usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head),
 	    sizeof(sc->sc_hcca->hcca_done_head),
 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
 	OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH);
 	sc->sc_eintrs |= OHCI_WDH;
 	OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH);
 	/* Reverse the done list. */
 	for (sdone = NULL, sidone = NULL; done != 0; ) {
 		std = ohci_hash_find_td(sc, done);
 		if (std != NULL) {
 			usb_syncmem(&std->dma, std->offs, sizeof(std->td),
 			    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
 			std->dnext = sdone;
 			done = O32TOH(std->td.td_nexttd);
 			sdone = std;
 			DPRINTFN(10, "add TD %p", std, 0, 0, 0);
 			continue;
+		}
 		sitd = ohci_hash_find_itd(sc, done);
 		if (sitd != NULL) {
 			usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
 			    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
 			sitd->dnext = sidone;
 			done = O32TOH(sitd->itd.itd_nextitd);
 			sidone = sitd;
 			DPRINTFN(5, "add ITD %p", sitd, 0, 0, 0);
 			continue;
+		}
 		DPRINTFN(10, "addr %p not found", done, 0, 0, 0);
 		device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n",
 		    (u_long)done);
 		break;
+	}
 	DPRINTFN(10, "sdone=%p sidone=%p", sdone, sidone, 0, 0);
 	DPRINTFN(10, "--- TD dump start ---", 0, 0, 0, 0);
 #ifdef OHCI_DEBUG
 	if (ohcidebug >= 10) {
 		for (std = sdone; std; std = std->dnext)
 			ohci_dump_td(sc, std);
+	}
 #endif
 	DPRINTFN(10, "--- TD dump end ---", 0, 0, 0, 0);
 	for (std = sdone; std; std = stdnext) {
 		xfer = std->xfer;
 		stdnext = std->dnext;
 		DPRINTFN(10, "std=%p xfer=%p hcpriv=%p", std, xfer,
 		    xfer ? xfer->ux_hcpriv : 0, 0);
 		if (xfer == NULL) {
 			/*
 			 * xfer == NULL: There seems to be no xfer associated
 			 * with this TD. It is tailp that happened to end up on
 			 * the done queue.
 			 * Shouldn't happen, but some chips are broken(?).
 			 */
 			continue;
+		}
 		if (xfer->ux_status == USBD_CANCELLED ||
 		    xfer->ux_status == USBD_TIMEOUT) {
 			DPRINTF("cancel/timeout %p", xfer, 0, 0, 0);
 			/* Handled by abort routine. */
 			continue;
+		}
 		callout_stop(&xfer->ux_callout);
 		len = std->len;
 		if (std->td.td_cbp != 0)
 			len -= O32TOH(std->td.td_be) -
 			       O32TOH(std->td.td_cbp) + 1;
 		DPRINTFN(10, "len=%d, flags=0x%x", len, std->flags, 0, 0);
 		if (std->flags & OHCI_ADD_LEN)
 			xfer->ux_actlen += len;
 		cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags));
 		if (cc == OHCI_CC_NO_ERROR) {
 			ohci_hash_rem_td(sc, std);
 			if (std->flags & OHCI_CALL_DONE) {
 				xfer->ux_status = USBD_NORMAL_COMPLETION;
 				usb_transfer_complete(xfer);
+			}
 		} else {
 			/*
 			 * Endpoint is halted.  First unlink all the TDs
 			 * belonging to the failed transfer, and then restart
 			 * the endpoint.
 			 */
 			ohci_soft_td_t *p, *n;
 			opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
 			DPRINTFN(10, "error cc=%d", cc, 0, 0, 0);
 			/* remove xfer's TDs from the hash */
 			for (p = std; p->xfer == xfer; p = n) {
 				n = p->nexttd;
 				ohci_hash_rem_td(sc, p);
+			}
 			ohci_soft_ed_t *sed = opipe->sed;
 			/* clear halt and TD chain */
 			sed->ed.ed_headp = HTOO32(p->physaddr);
 			usb_syncmem(&sed->dma,
 			    sed->offs + offsetof(ohci_ed_t, ed_headp),
 			    sizeof(sed->ed.ed_headp),
 			    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
 			OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF);
 			if (cc == OHCI_CC_DATA_UNDERRUN)
 				xfer->ux_status = USBD_NORMAL_COMPLETION;
 			else if (cc == OHCI_CC_STALL)
 				xfer->ux_status = USBD_STALLED;
 			else
 				xfer->ux_status = USBD_IOERROR;
 			usb_transfer_complete(xfer);
+		}
+	}
 	DPRINTFN(10, "--- ITD dump start ---", 0, 0, 0, 0);
 #ifdef OHCI_DEBUG
 	if (ohcidebug >= 10) {
 		for (sitd = sidone; sitd; sitd = sitd->dnext)
 			ohci_dump_itd(sc, sitd);
+	}
 #endif
 	DPRINTFN(10, "--- ITD dump end ---", 0, 0, 0, 0);
 	for (sitd = sidone; sitd != NULL; sitd = sitdnext) {
 		xfer = sitd->xfer;
 		sitdnext = sitd->dnext;
 		DPRINTFN(1, "sitd=%p xfer=%p hcpriv=%p", sitd, xfer,
 		    xfer ? xfer->ux_hcpriv : 0, 0);
 		if (xfer == NULL)
 			continue;
 		if (xfer->ux_status == USBD_CANCELLED ||
 		    xfer->ux_status == USBD_TIMEOUT) {
 			DPRINTF("cancel/timeout %p", xfer, 0, 0, 0);
 			/* Handled by abort routine. */
 			continue;
+		}
 		KASSERT(!sitd->isdone);
 #ifdef DIAGNOSTIC
 		sitd->isdone = true;
 #endif
 		if (sitd->flags & OHCI_CALL_DONE) {
 			ohci_soft_itd_t *next;
 			opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
 			opipe->isoc.inuse -= xfer->ux_nframes;
 			uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->
 			    bEndpointAddress);
 			xfer->ux_status = USBD_NORMAL_COMPLETION;
 			actlen = 0;
 			for (i = 0, sitd = xfer->ux_hcpriv;;
 			    sitd = next) {
 				next = sitd->nextitd;
 				if (OHCI_ITD_GET_CC(O32TOH(sitd->
 				    itd.itd_flags)) != OHCI_CC_NO_ERROR)
 					xfer->ux_status = USBD_IOERROR;
 				/* For input, update frlengths with actual */
 				/* XXX anything necessary for output? */
 				if (uedir == UE_DIR_IN &&
 				    xfer->ux_status == USBD_NORMAL_COMPLETION) {
 					iframes = OHCI_ITD_GET_FC(O32TOH(
 					    sitd->itd.itd_flags));
 					for (j = 0; j < iframes; i++, j++) {
 						len = O16TOH(sitd->
 						    itd.itd_offset[j]);
 						if ((OHCI_ITD_PSW_GET_CC(len) &
 						    OHCI_CC_NOT_ACCESSED_MASK)
 						    == OHCI_CC_NOT_ACCESSED)
 							len = 0;
 						else
 							len = OHCI_ITD_PSW_LENGTH(len);
 						xfer->ux_frlengths[i] = len;
 						actlen += len;
+					}
+				}
 				if (sitd->flags & OHCI_CALL_DONE)
 					break;
 				ohci_hash_rem_itd(sc, sitd);
+			}
 			ohci_hash_rem_itd(sc, sitd);
 			if (uedir == UE_DIR_IN &&
 			    xfer->ux_status == USBD_NORMAL_COMPLETION)
 				xfer->ux_actlen = actlen;
 			xfer->ux_hcpriv = NULL;
 			usb_transfer_complete(xfer);
+		}
+	}
 	if (sc->sc_softwake) {
 		sc->sc_softwake = 0;
 		cv_broadcast(&sc->sc_softwake_cv);
+	}
 	DPRINTFN(10, "done", 0, 0, 0, 0);
+}
 void
 ohci_device_ctrl_done(struct usbd_xfer *xfer)
+{
 	struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
 	ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
 	int len = UGETW(xfer->ux_request.wLength);
 	int isread = (xfer->ux_request.bmRequestType & UT_READ);
 	OHCIHIST_FUNC(); OHCIHIST_CALLED();
 	DPRINTFN(10, "xfer=%p", xfer, 0, 0, 0);
 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
 	KASSERT(xfer->ux_rqflags & URQ_REQUEST);
 	if (len)
 		usb_syncmem(&xfer->ux_dmabuf, 0, len,
 		    isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
 	usb_syncmem(&opipe->ctrl.reqdma, 0,
 	    sizeof(usb_device_request_t),  BUS_DMASYNC_POSTWRITE);
+}
 void
 ohci_device_intr_done(struct usbd_xfer *xfer)
+{
 	ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
 	int isread =
 	    (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN);
 	OHCIHIST_FUNC(); OHCIHIST_CALLED();
 	DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0);
 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
 	usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
 	    isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
+}
 void
 ohci_device_bulk_done(struct usbd_xfer *xfer)
+{
 	ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
 	int isread =
 	    (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN);
 	KASSERT(mutex_owned(&sc->sc_lock));