 @@ -1,14 +1,14 @@
-/* $NetBSD: dwc_gmac.c,v 1.28.2.3 2016/03/19 11:30:09 skrll Exp $ */
+/* $NetBSD: dwc_gmac.c,v 1.28.2.4 2016/06/12 07:18:52 skrll Exp $ */
 /*-
  * Copyright (c) 2013, 2014 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Matt Thomas of 3am Software Foundry and Martin Husemann.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -31,31 +31,34 @@
 /*
  * This driver supports the Synopsis Designware GMAC core, as found
  * on Allwinner A20 cores and others.
+ *
  * Real documentation seems to not be available, the marketing product
  * documents could be found here:
+ *
  *  http://www.synopsys.com/dw/ipdir.php?ds=dwc_ether_mac10_100_1000_unive
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: dwc_gmac.c,v 1.28.2.3 2016/03/19 11:30:09 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: dwc_gmac.c,v 1.28.2.4 2016/06/12 07:18:52 skrll Exp $");
 /* #define	DWC_GMAC_DEBUG	1 */
 #ifdef _KERNEL_OPT
 #include "opt_inet.h"
 #include "opt_net_mpsafe.h"
 #endif
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/sockio.h>
 #include <sys/cprng.h>
 #include <net/if.h>
 #include <net/if_ether.h>
 #include <net/if_media.h>
 #include <net/bpf.h>
 @@ -75,28 +78,31 @@ static void dwc_gmac_miibus_statchg(stru
 static int dwc_gmac_reset(struct dwc_gmac_softc *sc);
 static void dwc_gmac_write_hwaddr(struct dwc_gmac_softc *sc,
 			 uint8_t enaddr[ETHER_ADDR_LEN]);
 static int dwc_gmac_alloc_dma_rings(struct dwc_gmac_softc *sc);
 static void dwc_gmac_free_dma_rings(struct dwc_gmac_softc *sc);
 static int dwc_gmac_alloc_rx_ring(struct dwc_gmac_softc *sc, struct dwc_gmac_rx_ring *);
 static void dwc_gmac_reset_rx_ring(struct dwc_gmac_softc *sc, struct dwc_gmac_rx_ring *);
 static void dwc_gmac_free_rx_ring(struct dwc_gmac_softc *sc, struct dwc_gmac_rx_ring *);
 static int dwc_gmac_alloc_tx_ring(struct dwc_gmac_softc *sc, struct dwc_gmac_tx_ring *);
 static void dwc_gmac_reset_tx_ring(struct dwc_gmac_softc *sc, struct dwc_gmac_tx_ring *);
 static void dwc_gmac_free_tx_ring(struct dwc_gmac_softc *sc, struct dwc_gmac_tx_ring *);
 static void dwc_gmac_txdesc_sync(struct dwc_gmac_softc *sc, int start, int end, int ops);
 static int dwc_gmac_init(struct ifnet *ifp);
 static int dwc_gmac_init_locked(struct ifnet *ifp);
 static void dwc_gmac_stop(struct ifnet *ifp, int disable);
 static void dwc_gmac_stop_locked(struct ifnet *ifp, int disable);
 static void dwc_gmac_start(struct ifnet *ifp);
 static void dwc_gmac_start_locked(struct ifnet *ifp);
 static int dwc_gmac_queue(struct dwc_gmac_softc *sc, struct mbuf *m0);
 static int dwc_gmac_ioctl(struct ifnet *, u_long, void *);
 static void dwc_gmac_tx_intr(struct dwc_gmac_softc *sc);
 static void dwc_gmac_rx_intr(struct dwc_gmac_softc *sc);
 static void dwc_gmac_setmulti(struct dwc_gmac_softc *sc);
 static int dwc_gmac_ifflags_cb(struct ethercom *);
 static uint32_t	bitrev32(uint32_t x);
 #define	TX_DESC_OFFSET(N)	((AWGE_RX_RING_COUNT+(N)) \
 				    *sizeof(struct dwc_gmac_dev_dmadesc))
 #define	TX_NEXT(N)		(((N)+1) & (AWGE_TX_RING_COUNT-1))
 #define RX_DESC_OFFSET(N)	((N)*sizeof(struct dwc_gmac_dev_dmadesc))
 @@ -118,35 +124,38 @@ static uint32_t	bitrev32(uint32_t x);
 	(AWIN_GMAC_MAC_INT_TSI | AWIN_GMAC_MAC_INT_ANEG |	\
 	AWIN_GMAC_MAC_INT_LINKCHG | AWIN_GMAC_MAC_INT_RGSMII)
 #ifdef DWC_GMAC_DEBUG
 static void dwc_gmac_dump_dma(struct dwc_gmac_softc *sc);
 static void dwc_gmac_dump_tx_desc(struct dwc_gmac_softc *sc);
 static void dwc_gmac_dump_rx_desc(struct dwc_gmac_softc *sc);
 static void dwc_dump_and_abort(struct dwc_gmac_softc *sc, const char *msg);
 static void dwc_dump_status(struct dwc_gmac_softc *sc);
 static void dwc_gmac_dump_ffilt(struct dwc_gmac_softc *sc, uint32_t ffilt);
 #endif
 #ifdef NET_MPSAFE
 #define DWCGMAC_MPSAFE	1
 #endif
 void
 dwc_gmac_attach(struct dwc_gmac_softc *sc, uint32_t mii_clk)
+{
 	uint8_t enaddr[ETHER_ADDR_LEN];
 	uint32_t maclo, machi;
 	struct mii_data * const mii = &sc->sc_mii;
 	struct ifnet * const ifp = &sc->sc_ec.ec_if;
 	prop_dictionary_t dict;
 	int s;
 	mutex_init(&sc->sc_mdio_lock, MUTEX_DEFAULT, IPL_NET);
 	sc->sc_mii_clk = mii_clk & 7;
 	dict = device_properties(sc->sc_dev);
 	prop_data_t ea = dict ? prop_dictionary_get(dict, "mac-address") : NULL;
 	if (ea != NULL) {
 		/*
 		 * If the MAC address is overriden by a device property,
 		 * use that.
 		 */
 		KASSERT(prop_object_type(ea) == PROP_TYPE_DATA);
 		KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN);
 @@ -188,32 +197,35 @@ dwc_gmac_attach(struct dwc_gmac_softc *s
 	/*
 	 * Allocate Tx and Rx rings
 	 */
 	if (dwc_gmac_alloc_dma_rings(sc) != 0) {
 		aprint_error_dev(sc->sc_dev, "could not allocate DMA rings\n");
 		goto fail;
+	}
 	if (dwc_gmac_alloc_tx_ring(sc, &sc->sc_txq) != 0) {
 		aprint_error_dev(sc->sc_dev, "could not allocate Tx ring\n");
 		goto fail;
+	}
 	mutex_init(&sc->sc_rxq.r_mtx, MUTEX_DEFAULT, IPL_NET);
 	if (dwc_gmac_alloc_rx_ring(sc, &sc->sc_rxq) != 0) {
 		aprint_error_dev(sc->sc_dev, "could not allocate Rx ring\n");
 		goto fail;
+	}
 	sc->sc_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
 	mutex_init(&sc->sc_txq.t_mtx, MUTEX_DEFAULT, IPL_NET);
 	mutex_init(&sc->sc_rxq.r_mtx, MUTEX_DEFAULT, IPL_NET);
 	/*
 	 * Prepare interface data
 	 */
 	ifp->if_softc = sc;
 	strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 	ifp->if_ioctl = dwc_gmac_ioctl;
 	ifp->if_start = dwc_gmac_start;
 	ifp->if_init = dwc_gmac_init;
 	ifp->if_stop = dwc_gmac_stop;
 	IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
 	IFQ_SET_READY(&ifp->if_snd);
 @@ -235,39 +247,42 @@ dwc_gmac_attach(struct dwc_gmac_softc *s
                 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_MANUAL);
         } else {
                 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO);
+        }
 	/*
 	 * We can support 802.1Q VLAN-sized frames.
 	 */
 	sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU;
 	/*
 	 * Ready, attach interface
 	 */
-	if_attach(ifp);
+	/* Attach the interface. */
 	if_initialize(ifp);
 	sc->sc_ipq = if_percpuq_create(&sc->sc_ec.ec_if);
 	ether_ifattach(ifp, enaddr);
 	ether_set_ifflags_cb(&sc->sc_ec, dwc_gmac_ifflags_cb);
 	if_register(ifp);
 	/*
 	 * Enable interrupts
 	 */
-	s = splnet();
+	mutex_enter(sc->sc_lock);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_INTMASK,
 	    AWIN_DEF_MAC_INTRMASK);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_INTENABLE,
 	    GMAC_DEF_DMA_INT_MASK);
-	splx(s);
+	mutex_exit(sc->sc_lock);
 	return;
 fail:
 	dwc_gmac_free_rx_ring(sc, &sc->sc_rxq);
 	dwc_gmac_free_tx_ring(sc, &sc->sc_txq);
+}
 static int
 dwc_gmac_reset(struct dwc_gmac_softc *sc)
+{
 @@ -429,42 +444,44 @@ dwc_gmac_alloc_rx_ring(struct dwc_gmac_s
 fail:
 	dwc_gmac_free_rx_ring(sc, ring);
 	return error;
+}
 static void
 dwc_gmac_reset_rx_ring(struct dwc_gmac_softc *sc,
 	struct dwc_gmac_rx_ring *ring)
+{
 	struct dwc_gmac_dev_dmadesc *desc;
 	int i;
 	mutex_enter(&ring->r_mtx);
 	for (i = 0; i < AWGE_RX_RING_COUNT; i++) {
 		desc = &sc->sc_rxq.r_desc[i];
 		desc->ddesc_cntl = htole32(
 		    __SHIFTIN(AWGE_MAX_PACKET,DDESC_CNTL_SIZE1MASK) |
 		    DDESC_CNTL_RXCHAIN);
 		desc->ddesc_status = htole32(DDESC_STATUS_OWNEDBYDEV);
+	}
 	bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map, 0,
 	    AWGE_RX_RING_COUNT*sizeof(struct dwc_gmac_dev_dmadesc),
 	    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 	ring->r_cur = ring->r_next = 0;
 	/* reset DMA address to start of ring */
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_RX_ADDR,
 	    sc->sc_rxq.r_physaddr);
 	mutex_exit(&ring->r_mtx);
+}
 static int
 dwc_gmac_alloc_dma_rings(struct dwc_gmac_softc *sc)
+{
 	const size_t descsize = AWGE_TOTAL_RING_COUNT *
 		sizeof(struct dwc_gmac_dev_dmadesc);
 	int error, nsegs;
 	void *rings;
 	error = bus_dmamap_create(sc->sc_dmat, descsize, 1, descsize, 0,
 	    BUS_DMA_NOWAIT, &sc->sc_dma_ring_map);
 	if (error != 0) {
 @@ -608,48 +625,50 @@ dwc_gmac_txdesc_sync(struct dwc_gmac_sof
 	/* sync from start of ring to 'end' */
 	bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map,
 	    TX_DESC_OFFSET(0),
 	    TX_DESC_OFFSET(end)-TX_DESC_OFFSET(0),
 	    ops);
+}
 static void
 dwc_gmac_reset_tx_ring(struct dwc_gmac_softc *sc,
 	struct dwc_gmac_tx_ring *ring)
+{
 	int i;
 	mutex_enter(&ring->t_mtx);
 	for (i = 0; i < AWGE_TX_RING_COUNT; i++) {
 		struct dwc_gmac_tx_data *data = &ring->t_data[i];
 		if (data->td_m != NULL) {
 			bus_dmamap_sync(sc->sc_dmat, data->td_active,
 , data->td_active->dm_mapsize,
 			    BUS_DMASYNC_POSTWRITE);
 			bus_dmamap_unload(sc->sc_dmat, data->td_active);
 			m_freem(data->td_m);
 			data->td_m = NULL;
+		}
+	}
 	bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map,
 	    TX_DESC_OFFSET(0),
 	    AWGE_TX_RING_COUNT*sizeof(struct dwc_gmac_dev_dmadesc),
 	    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_TX_ADDR,
 	    sc->sc_txq.t_physaddr);
 	ring->t_queued = 0;
 	ring->t_cur = ring->t_next = 0;
 	mutex_exit(&ring->t_mtx);
+}
 static void
 dwc_gmac_free_tx_ring(struct dwc_gmac_softc *sc,
 	struct dwc_gmac_tx_ring *ring)
+{
 	int i;
 	/* unload the maps */
 	for (i = 0; i < AWGE_TX_RING_COUNT; i++) {
 		struct dwc_gmac_tx_data *data = &ring->t_data[i];
 		if (data->td_m != NULL) {
 @@ -719,26 +738,38 @@ dwc_gmac_miibus_statchg(struct ifnet *if
 #ifdef DWC_GMAC_DEBUG
 	aprint_normal_dev(sc->sc_dev,
 	    "setting MAC conf register: %08x\n", conf);
 #endif
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh,
 	    AWIN_GMAC_MAC_CONF, conf);
+}
 static int
 dwc_gmac_init(struct ifnet *ifp)
+{
 	struct dwc_gmac_softc *sc = ifp->if_softc;
 	mutex_enter(sc->sc_lock);
 	int ret = dwc_gmac_init_locked(ifp);
 	mutex_exit(sc->sc_lock);
 	return ret;
+}
 static int
 dwc_gmac_init_locked(struct ifnet *ifp)
+{
 	struct dwc_gmac_softc *sc = ifp->if_softc;
 	uint32_t ffilt;
 	if (ifp->if_flags & IFF_RUNNING)
 		return 0;
 	dwc_gmac_stop(ifp, 0);
 	/*
 	 * Configure DMA burst/transfer mode and RX/TX priorities.
 	 * XXX - the GMAC_BUSMODE_PRIORXTX bits are undocumented.
 	 */
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_BUSMODE,
 	    GMAC_BUSMODE_FIXEDBURST | GMAC_BUSMODE_4PBL |
 @@ -771,36 +802,52 @@ dwc_gmac_init(struct ifnet *ifp)
 	 */
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_RX_ADDR,
 	    sc->sc_rxq.r_physaddr);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_TX_ADDR,
 	    sc->sc_txq.t_physaddr);
 	/*
 	 * Start RX/TX part
 	 */
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh,
 	    AWIN_GMAC_DMA_OPMODE, GMAC_DMA_OP_RXSTART | GMAC_DMA_OP_TXSTART |
 	    GMAC_DMA_OP_RXSTOREFORWARD | GMAC_DMA_OP_TXSTOREFORWARD);
 	sc->sc_stopping = false;
 	ifp->if_flags |= IFF_RUNNING;
 	ifp->if_flags &= ~IFF_OACTIVE;
 	return 0;
+}
 static void
 dwc_gmac_start(struct ifnet *ifp)
+{
 	struct dwc_gmac_softc *sc = ifp->if_softc;
 	mutex_enter(sc->sc_lock);
 	if (!sc->sc_stopping) {
 		mutex_enter(&sc->sc_txq.t_mtx);
 		dwc_gmac_start_locked(ifp);
 		mutex_exit(&sc->sc_txq.t_mtx);
+	}
 	mutex_exit(sc->sc_lock);
+}
 static void
 dwc_gmac_start_locked(struct ifnet *ifp)
+{
 	struct dwc_gmac_softc *sc = ifp->if_softc;
 	int old = sc->sc_txq.t_queued;
 	int start = sc->sc_txq.t_cur;
 	struct mbuf *m0;
 	if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
 		return;
 	for (;;) {
 		IFQ_POLL(&ifp->if_snd, m0);
 		if (m0 == NULL)
 			break;
 		if (dwc_gmac_queue(sc, m0) != 0) {
 			ifp->if_flags |= IFF_OACTIVE;
 @@ -822,26 +869,38 @@ dwc_gmac_start(struct ifnet *ifp)
 		bus_space_write_4(sc->sc_bst, sc->sc_bsh,
 		    AWIN_GMAC_DMA_TXPOLL, ~0U);
 #ifdef DWC_GMAC_DEBUG
 		dwc_dump_status(sc);
 #endif
+	}
+}
 static void
 dwc_gmac_stop(struct ifnet *ifp, int disable)
+{
 	struct dwc_gmac_softc *sc = ifp->if_softc;
 	mutex_enter(sc->sc_lock);
 	dwc_gmac_stop_locked(ifp, disable);
 	mutex_exit(sc->sc_lock);
+}
 static void
 dwc_gmac_stop_locked(struct ifnet *ifp, int disable)
+{
 	struct dwc_gmac_softc *sc = ifp->if_softc;
 	sc->sc_stopping = true;
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh,
 	    AWIN_GMAC_DMA_OPMODE,
 	    bus_space_read_4(sc->sc_bst, sc->sc_bsh,
 	        AWIN_GMAC_DMA_OPMODE)
 		& ~(GMAC_DMA_OP_TXSTART|GMAC_DMA_OP_RXSTART));
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh,
 	    AWIN_GMAC_DMA_OPMODE,
 	    bus_space_read_4(sc->sc_bst, sc->sc_bsh,
 	        AWIN_GMAC_DMA_OPMODE) | GMAC_DMA_OP_FLUSHTX);
 	mii_down(&sc->sc_mii);
 	dwc_gmac_reset_tx_ring(sc, &sc->sc_txq);
 	dwc_gmac_reset_rx_ring(sc, &sc->sc_rxq);
 @@ -930,69 +989,85 @@ dwc_gmac_queue(struct dwc_gmac_softc *sc
  * If the interface is up and running, only modify the receive
  * filter when setting promiscuous or debug mode.  Otherwise fall
  * through to ether_ioctl, which will reset the chip.
  */
 static int
 dwc_gmac_ifflags_cb(struct ethercom *ec)
+{
 	struct ifnet *ifp = &ec->ec_if;
 	struct dwc_gmac_softc *sc = ifp->if_softc;
 	int change = ifp->if_flags ^ sc->sc_if_flags;
 	if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0)
 		return ENETRESET;
-	if ((change & IFF_PROMISC) != 0)
+	if ((change & IFF_PROMISC) != 0) {
 		mutex_enter(sc->sc_lock);
 		dwc_gmac_setmulti(sc);
 		mutex_exit(sc->sc_lock);
+	}
 	return 0;
+}
 static int
 dwc_gmac_ioctl(struct ifnet *ifp, u_long cmd, void *data)
+{
 	struct dwc_gmac_softc *sc = ifp->if_softc;
-	int s, error = 0;
+	int error = 0;
-	s = splnet();
+	int s = splnet();
 	error = ether_ioctl(ifp, cmd, data);
-	if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) {
+#ifdef DWCGMAC_MPSAFE
 	splx(s);
 #endif
 	if (error == ENETRESET) {
 		error = 0;
 		if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI)
+			;
 		else if (ifp->if_flags & IFF_RUNNING) {
 			/*
 			 * Multicast list has changed; set the hardware filter
 			 * accordingly.
 			 */
 			mutex_enter(sc->sc_lock);
 			dwc_gmac_setmulti(sc);
 			mutex_exit(sc->sc_lock);
+		}
+	}
 	/* Try to get things going again */
 	if (ifp->if_flags & IFF_UP)
 		dwc_gmac_start(ifp);
 	sc->sc_if_flags = sc->sc_ec.ec_if.if_flags;
 #ifndef DWCGMAC_MPSAFE
 	splx(s);
 #endif
 	return error;
+}
 static void
 dwc_gmac_tx_intr(struct dwc_gmac_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_ec.ec_if;
 	struct dwc_gmac_tx_data *data;
 	struct dwc_gmac_dev_dmadesc *desc;
 	uint32_t status;
 	int i, nsegs;
 	mutex_enter(&sc->sc_txq.t_mtx);
 	for (i = sc->sc_txq.t_next; sc->sc_txq.t_queued > 0; i = TX_NEXT(i)) {
 #ifdef DWC_GMAC_DEBUG
 		aprint_normal_dev(sc->sc_dev,
 		    "dwc_gmac_tx_intr: checking desc #%d (t_queued: %d)\n",
 		    i, sc->sc_txq.t_queued);
 #endif
 		/*
 		 * i+1 does not need to be a valid descriptor,
 		 * this is just a special notion to just sync
 		 * a single tx descriptor (i)
 		 */
 		dwc_gmac_txdesc_sync(sc, i, i+1,
 @@ -1020,39 +1095,41 @@ dwc_gmac_tx_intr(struct dwc_gmac_softc *
 #endif
 		m_freem(data->td_m);
 		data->td_m = NULL;
 		sc->sc_txq.t_queued -= nsegs;
+	}
 	sc->sc_txq.t_next = i;
 	if (sc->sc_txq.t_queued < AWGE_TX_RING_COUNT) {
 		ifp->if_flags &= ~IFF_OACTIVE;
+	}
 	mutex_exit(&sc->sc_txq.t_mtx);
+}
 static void
 dwc_gmac_rx_intr(struct dwc_gmac_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_ec.ec_if;
 	struct dwc_gmac_dev_dmadesc *desc;
 	struct dwc_gmac_rx_data *data;
 	bus_addr_t physaddr;
 	uint32_t status;
 	struct mbuf *m, *mnew;
 	int i, len, error;
 	mutex_enter(&sc->sc_rxq.r_mtx);
 	for (i = sc->sc_rxq.r_cur; ; i = RX_NEXT(i)) {
 		bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map,
 		    RX_DESC_OFFSET(i), sizeof(*desc),
 		    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
 		desc = &sc->sc_rxq.r_desc[i];
 		data = &sc->sc_rxq.r_data[i];
 		status = le32toh(desc->ddesc_status);
 		if (status & DDESC_STATUS_OWNEDBYDEV)
 			break;
 		if (status & (DDESC_STATUS_RXERROR|DDESC_STATUS_RXTRUNCATED)) {
 #ifdef DWC_GMAC_DEBUG
 @@ -1088,99 +1165,105 @@ dwc_gmac_rx_intr(struct dwc_gmac_softc *
 			ifp->if_ierrors++;
 			goto skip;
+		}
 		/* unload old DMA map */
 		bus_dmamap_sync(sc->sc_dmat, data->rd_map, 0,
 		    data->rd_map->dm_mapsize, BUS_DMASYNC_POSTREAD);
 		bus_dmamap_unload(sc->sc_dmat, data->rd_map);
 		/* and reload with new mbuf */
 		error = bus_dmamap_load(sc->sc_dmat, data->rd_map,
 		    mtod(mnew, void*), MCLBYTES, NULL,
 		    BUS_DMA_READ | BUS_DMA_NOWAIT);
-		if (error != 0) {
+		    if (error != 0) {
 			m_freem(mnew);
 			/* try to reload old mbuf */
 			error = bus_dmamap_load(sc->sc_dmat, data->rd_map,
 			    mtod(data->rd_m, void*), MCLBYTES, NULL,
 			    BUS_DMA_READ | BUS_DMA_NOWAIT);
 			if (error != 0) {
 				panic("%s: could not load old rx mbuf",
 				    device_xname(sc->sc_dev));
+			}
 			ifp->if_ierrors++;
 			goto skip;
+		}
 		physaddr = data->rd_map->dm_segs[0].ds_addr;
 		/*
 		 * New mbuf loaded, update RX ring and continue
 		 */
 		m = data->rd_m;
 		data->rd_m = mnew;
 		desc->ddesc_data = htole32(physaddr);
 		/* finalize mbuf */
 		m->m_pkthdr.len = m->m_len = len;
 		m->m_pkthdr.rcvif = ifp;
 		m->m_flags |= M_HASFCS;
 		bpf_mtap(ifp, m);
 		ifp->if_ipackets++;
 		mutex_exit(&sc->sc_rxq.r_mtx);
 		bpf_mtap(ifp, m);
 		if_percpuq_enqueue(ifp->if_percpuq, m);
 		mutex_enter(&sc->sc_rxq.r_mtx);
 skip:
 		bus_dmamap_sync(sc->sc_dmat, data->rd_map, 0,
 		    data->rd_map->dm_mapsize, BUS_DMASYNC_PREREAD);
 		desc->ddesc_cntl = htole32(
 		    __SHIFTIN(AWGE_MAX_PACKET,DDESC_CNTL_SIZE1MASK) |
 		    DDESC_CNTL_RXCHAIN);
 		desc->ddesc_status = htole32(DDESC_STATUS_OWNEDBYDEV);
 		bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map,
 		    RX_DESC_OFFSET(i), sizeof(*desc),
 		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+	}
 	/* update RX pointer */
 	sc->sc_rxq.r_cur = i;
 	mutex_exit(&sc->sc_rxq.r_mtx);
+}
 /*
  * Reverse order of bits - http://aggregate.org/MAGIC/#Bit%20Reversal
  */
 static uint32_t
 bitrev32(uint32_t x)
+{
 	x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1));
 	x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2));
 	x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4));
 	x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8));
 	return (x >> 16) | (x << 16);
+}
 static void
 dwc_gmac_setmulti(struct dwc_gmac_softc *sc)
+{
 	struct ifnet * const ifp = &sc->sc_ec.ec_if;
 	struct ether_multi *enm;
 	struct ether_multistep step;
 	uint32_t hashes[2] = { 0, 0 };
 	uint32_t ffilt, h;
-	int mcnt, s;
+	int mcnt;
-	s = splnet();
+	KASSERT(mutex_owned(sc->sc_lock));
 	ffilt = bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_FFILT);
 	if (ifp->if_flags & IFF_PROMISC) {
 		ffilt |= AWIN_GMAC_MAC_FFILT_PR;
 		goto special_filter;
+	}
 	ifp->if_flags &= ~IFF_ALLMULTI;
 	ffilt &= ~(AWIN_GMAC_MAC_FFILT_PM|AWIN_GMAC_MAC_FFILT_PR);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_HTLOW, 0);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_HTHIGH, 0);
 @@ -1206,54 +1289,54 @@ dwc_gmac_setmulti(struct dwc_gmac_softc
 	if (mcnt)
 		ffilt |= AWIN_GMAC_MAC_FFILT_HMC;
 	else
 		ffilt &= ~AWIN_GMAC_MAC_FFILT_HMC;
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_FFILT, ffilt);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_HTLOW,
 	    hashes[0]);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_HTHIGH,
 	    hashes[1]);
 	sc->sc_if_flags = sc->sc_ec.ec_if.if_flags;
 	splx(s);
 #ifdef DWC_GMAC_DEBUG
 	dwc_gmac_dump_ffilt(sc, ffilt);
 #endif
 	return;
 special_filter:
 #ifdef DWC_GMAC_DEBUG
 	dwc_gmac_dump_ffilt(sc, ffilt);
 #endif
 	/* no MAC hashes, ALLMULTI or PROMISC */
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_FFILT,
 	    ffilt);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_HTLOW,
 xffffffff);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_HTHIGH,
 xffffffff);
 	sc->sc_if_flags = sc->sc_ec.ec_if.if_flags;
 	splx(s);
+}
 int
 dwc_gmac_intr(struct dwc_gmac_softc *sc)
+{
 	uint32_t status, dma_status;
 	int rv = 0;
 	if (sc->sc_stopping)
 		return 0;
 	status = bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_INTR);
 	if (status & AWIN_GMAC_MII_IRQ) {
 		(void)bus_space_read_4(sc->sc_bst, sc->sc_bsh,
 		    AWIN_GMAC_MII_STATUS);
 		rv = 1;
 		mii_pollstat(&sc->sc_mii);
+	}
 	dma_status = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
 	    AWIN_GMAC_DMA_STATUS);
 	if (dma_status & (GMAC_DMA_INT_NIE|GMAC_DMA_INT_AIE))
 		rv = 1;

 @@ -24,27 +24,27 @@
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include "locators.h"
 #include "axp806pm.h"
 #include "axp809pm.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: awin_gige.c,v 1.19.2.1 2015/04/06 15:17:51 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_gige.c,v 1.19.2.2 2016/06/12 07:18:52 skrll Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <arm/allwinner/awin_reg.h>
 #include <arm/allwinner/awin_var.h>
 #if NAXP806PM > 0
 #include <dev/i2c/axp806.h>
 #endif
 @@ -143,27 +143,31 @@ awin_gige_attach(device_t parent, device
 	sc->sc_core.sc_bst = aio->aio_core_bst;
 	sc->sc_core.sc_dmat = aio->aio_dmat;
 	bus_space_subregion(sc->sc_core.sc_bst, bsh,
 	    loc->loc_offset, loc->loc_size, &sc->sc_core.sc_bsh);
 	aprint_naive("\n");
 	aprint_normal(": Gigabit Ethernet Controller\n");
 	awin_gige_pmu_init(self);
 	/*
 	 * Interrupt handler
 	 */
-	sc->sc_ih = intr_establish(loc->loc_intr, IPL_NET, IST_LEVEL,
+	int mpsafe = 0;
 #ifdef NET_MPSAFE
 	mpsafe |= IST_MPSAFE;
 #endif
 	sc->sc_ih = intr_establish(loc->loc_intr, IPL_NET, IST_LEVEL | mpsafe,
 	    awin_gige_intr, sc);
 	if (sc->sc_ih == NULL) {
 		aprint_error_dev(self, "failed to establish interrupt %d\n",
 		     loc->loc_intr);
 		return;
+	}
 	aprint_normal_dev(self, "interrupting on irq %d\n",
 	     loc->loc_intr);
 	if (prop_dictionary_get_cstring_nocopy(cfg, "phy-power", &pin_name)) {
 		if (awin_gpio_pin_reserve(pin_name, &sc->sc_power_pin)) {
 			awin_gpio_pindata_write(&sc->sc_power_pin, 1);
 		} else {

 @@ -1,14 +1,14 @@
-/* $NetBSD: dwc_gmac_var.h,v 1.6 2014/11/22 18:31:03 jmcneill Exp $ */
+/* $NetBSD: dwc_gmac_var.h,v 1.6.2.1 2016/06/12 07:18:52 skrll Exp $ */
 /*-
  * Copyright (c) 2013, 2014 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Matt Thomas of 3am Software Foundry and Martin Husemann.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -54,41 +54,47 @@ struct dwc_gmac_rx_data {
 };
 struct dwc_gmac_tx_data {
 	bus_dmamap_t	td_map;
 	bus_dmamap_t	td_active;
 	struct mbuf	*td_m;
 };
 struct dwc_gmac_tx_ring {
 	bus_addr_t			t_physaddr; /* PA of TX ring start */
 	struct dwc_gmac_dev_dmadesc	*t_desc;    /* VA of TX ring start */
 	struct dwc_gmac_tx_data	t_data[AWGE_TX_RING_COUNT];
 	int				t_cur, t_next, t_queued;
 	kmutex_t			t_mtx;
 };
 struct dwc_gmac_rx_ring {
 	bus_addr_t			r_physaddr; /* PA of RX ring start */
 	struct dwc_gmac_dev_dmadesc	*r_desc;    /* VA of RX ring start */
 	struct dwc_gmac_rx_data	r_data[AWGE_RX_RING_COUNT];
 	int				r_cur, r_next;
 	kmutex_t			r_mtx;
 };
 struct dwc_gmac_softc {
 	device_t sc_dev;
 	bus_space_tag_t sc_bst;
 	bus_space_handle_t sc_bsh;
 	bus_dma_tag_t sc_dmat;
 	struct ethercom sc_ec;
 	struct mii_data sc_mii;
 	kmutex_t sc_mdio_lock;
 	bus_dmamap_t sc_dma_ring_map;		/* common dma memory for RX */
 	bus_dma_segment_t sc_dma_ring_seg;	/* and TX ring */
 	struct dwc_gmac_rx_ring sc_rxq;
 	struct dwc_gmac_tx_ring sc_txq;
 	short sc_if_flags;			/* shadow of ether flags */
 	uint16_t sc_mii_clk;
 	bool sc_stopping;
 	kmutex_t *sc_lock;			/* lock for softc operations */
 	struct if_percpuq *sc_ipq;		/* softint-based input queues */
 };
 void dwc_gmac_attach(struct dwc_gmac_softc*, uint32_t /*mii_clk*/);
 int dwc_gmac_intr(struct dwc_gmac_softc*);