| @@ -1,1055 +1,1055 @@ | | | @@ -1,1055 +1,1055 @@ |
1 | /* $NetBSD: ehci.c,v 1.253 2016/08/14 14:42:22 skrll Exp $ */ | | 1 | /* $NetBSD: ehci.c,v 1.254 2016/10/03 00:32:37 dholland Exp $ */ |
2 | | | 2 | |
3 | /* | | 3 | /* |
4 | * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. | | 4 | * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. |
5 | * All rights reserved. | | 5 | * All rights reserved. |
6 | * | | 6 | * |
7 | * This code is derived from software contributed to The NetBSD Foundation | | 7 | * This code is derived from software contributed to The NetBSD Foundation |
8 | * by Lennart Augustsson (lennart@augustsson.net), Charles M. Hannum, | | 8 | * by Lennart Augustsson (lennart@augustsson.net), Charles M. Hannum, |
9 | * Jeremy Morse (jeremy.morse@gmail.com), Jared D. McNeill | | 9 | * Jeremy Morse (jeremy.morse@gmail.com), Jared D. McNeill |
10 | * (jmcneill@invisible.ca) and Matthew R. Green (mrg@eterna.com.au). | | 10 | * (jmcneill@invisible.ca) and Matthew R. Green (mrg@eterna.com.au). |
11 | * | | 11 | * |
12 | * Redistribution and use in source and binary forms, with or without | | 12 | * Redistribution and use in source and binary forms, with or without |
13 | * modification, are permitted provided that the following conditions | | 13 | * modification, are permitted provided that the following conditions |
14 | * are met: | | 14 | * are met: |
15 | * 1. Redistributions of source code must retain the above copyright | | 15 | * 1. Redistributions of source code must retain the above copyright |
16 | * notice, this list of conditions and the following disclaimer. | | 16 | * notice, this list of conditions and the following disclaimer. |
17 | * 2. Redistributions in binary form must reproduce the above copyright | | 17 | * 2. Redistributions in binary form must reproduce the above copyright |
18 | * notice, this list of conditions and the following disclaimer in the | | 18 | * notice, this list of conditions and the following disclaimer in the |
19 | * documentation and/or other materials provided with the distribution. | | 19 | * documentation and/or other materials provided with the distribution. |
20 | * | | 20 | * |
21 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS | | 21 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
22 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED | | 22 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
23 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | | 23 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
24 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS | | 24 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
25 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | | 25 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
26 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | | 26 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
27 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | | 27 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
28 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | | 28 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
29 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | | 29 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
30 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | | 30 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
31 | * POSSIBILITY OF SUCH DAMAGE. | | 31 | * POSSIBILITY OF SUCH DAMAGE. |
32 | */ | | 32 | */ |
33 | | | 33 | |
34 | /* | | 34 | /* |
35 | * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. | | 35 | * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. |
36 | * | | 36 | * |
37 | * The EHCI 1.0 spec can be found at | | 37 | * The EHCI 1.0 spec can be found at |
38 | * http://www.intel.com/technology/usb/spec.htm | | 38 | * http://www.intel.com/technology/usb/spec.htm |
39 | * and the USB 2.0 spec at | | 39 | * and the USB 2.0 spec at |
40 | * http://www.usb.org/developers/docs/ | | 40 | * http://www.usb.org/developers/docs/ |
41 | * | | 41 | * |
42 | */ | | 42 | */ |
43 | | | 43 | |
44 | /* | | 44 | /* |
45 | * TODO: | | 45 | * TODO: |
46 | * 1) hold off explorations by companion controllers until ehci has started. | | 46 | * 1) hold off explorations by companion controllers until ehci has started. |
47 | * | | 47 | * |
48 | * 2) The hub driver needs to handle and schedule the transaction translator, | | 48 | * 2) The hub driver needs to handle and schedule the transaction translator, |
49 | * to assign place in frame where different devices get to go. See chapter | | 49 | * to assign place in frame where different devices get to go. See chapter |
50 | * on hubs in USB 2.0 for details. | | 50 | * on hubs in USB 2.0 for details. |
51 | * | | 51 | * |
52 | * 3) Command failures are not recovered correctly. | | 52 | * 3) Command failures are not recovered correctly. |
53 | */ | | 53 | */ |
54 | | | 54 | |
55 | #include <sys/cdefs.h> | | 55 | #include <sys/cdefs.h> |
56 | __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.253 2016/08/14 14:42:22 skrll Exp $"); | | 56 | __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.254 2016/10/03 00:32:37 dholland Exp $"); |
57 | | | 57 | |
58 | #include "ohci.h" | | 58 | #include "ohci.h" |
59 | #include "uhci.h" | | 59 | #include "uhci.h" |
60 | | | 60 | |
61 | #ifdef _KERNEL_OPT | | 61 | #ifdef _KERNEL_OPT |
62 | #include "opt_usb.h" | | 62 | #include "opt_usb.h" |
63 | #endif | | 63 | #endif |
64 | | | 64 | |
65 | #include <sys/param.h> | | 65 | #include <sys/param.h> |
66 | | | 66 | |
67 | #include <sys/bus.h> | | 67 | #include <sys/bus.h> |
68 | #include <sys/cpu.h> | | 68 | #include <sys/cpu.h> |
69 | #include <sys/device.h> | | 69 | #include <sys/device.h> |
70 | #include <sys/kernel.h> | | 70 | #include <sys/kernel.h> |
71 | #include <sys/kmem.h> | | 71 | #include <sys/kmem.h> |
72 | #include <sys/mutex.h> | | 72 | #include <sys/mutex.h> |
73 | #include <sys/proc.h> | | 73 | #include <sys/proc.h> |
74 | #include <sys/queue.h> | | 74 | #include <sys/queue.h> |
75 | #include <sys/select.h> | | 75 | #include <sys/select.h> |
76 | #include <sys/sysctl.h> | | 76 | #include <sys/sysctl.h> |
77 | #include <sys/systm.h> | | 77 | #include <sys/systm.h> |
78 | | | 78 | |
79 | #include <machine/endian.h> | | 79 | #include <machine/endian.h> |
80 | | | 80 | |
81 | #include <dev/usb/usb.h> | | 81 | #include <dev/usb/usb.h> |
82 | #include <dev/usb/usbdi.h> | | 82 | #include <dev/usb/usbdi.h> |
83 | #include <dev/usb/usbdivar.h> | | 83 | #include <dev/usb/usbdivar.h> |
84 | #include <dev/usb/usbhist.h> | | 84 | #include <dev/usb/usbhist.h> |
85 | #include <dev/usb/usb_mem.h> | | 85 | #include <dev/usb/usb_mem.h> |
86 | #include <dev/usb/usb_quirks.h> | | 86 | #include <dev/usb/usb_quirks.h> |
87 | | | 87 | |
88 | #include <dev/usb/ehcireg.h> | | 88 | #include <dev/usb/ehcireg.h> |
89 | #include <dev/usb/ehcivar.h> | | 89 | #include <dev/usb/ehcivar.h> |
90 | #include <dev/usb/usbroothub.h> | | 90 | #include <dev/usb/usbroothub.h> |
91 | | | 91 | |
92 | | | 92 | |
93 | #ifdef USB_DEBUG | | 93 | #ifdef USB_DEBUG |
94 | #ifndef EHCI_DEBUG | | 94 | #ifndef EHCI_DEBUG |
95 | #define ehcidebug 0 | | 95 | #define ehcidebug 0 |
96 | #else | | 96 | #else |
97 | static int ehcidebug = 0; | | 97 | static int ehcidebug = 0; |
98 | | | 98 | |
99 | SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") | | 99 | SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") |
100 | { | | 100 | { |
101 | int err; | | 101 | int err; |
102 | const struct sysctlnode *rnode; | | 102 | const struct sysctlnode *rnode; |
103 | const struct sysctlnode *cnode; | | 103 | const struct sysctlnode *cnode; |
104 | | | 104 | |
105 | err = sysctl_createv(clog, 0, NULL, &rnode, | | 105 | err = sysctl_createv(clog, 0, NULL, &rnode, |
106 | CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", | | 106 | CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", |
107 | SYSCTL_DESCR("ehci global controls"), | | 107 | SYSCTL_DESCR("ehci global controls"), |
108 | NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); | | 108 | NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); |
109 | | | 109 | |
110 | if (err) | | 110 | if (err) |
111 | goto fail; | | 111 | goto fail; |
112 | | | 112 | |
113 | /* control debugging printfs */ | | 113 | /* control debugging printfs */ |
114 | err = sysctl_createv(clog, 0, &rnode, &cnode, | | 114 | err = sysctl_createv(clog, 0, &rnode, &cnode, |
115 | CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, | | 115 | CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, |
116 | "debug", SYSCTL_DESCR("Enable debugging output"), | | 116 | "debug", SYSCTL_DESCR("Enable debugging output"), |
117 | NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); | | 117 | NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); |
118 | if (err) | | 118 | if (err) |
119 | goto fail; | | 119 | goto fail; |
120 | | | 120 | |
121 | return; | | 121 | return; |
122 | fail: | | 122 | fail: |
123 | aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); | | 123 | aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); |
124 | } | | 124 | } |
125 | | | 125 | |
126 | #endif /* EHCI_DEBUG */ | | 126 | #endif /* EHCI_DEBUG */ |
127 | #endif /* USB_DEBUG */ | | 127 | #endif /* USB_DEBUG */ |
128 | | | 128 | |
129 | #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D) | | 129 | #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D) |
130 | #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D) | | 130 | #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D) |
131 | #define EHCIHIST_FUNC() USBHIST_FUNC() | | 131 | #define EHCIHIST_FUNC() USBHIST_FUNC() |
132 | #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug) | | 132 | #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug) |
133 | | | 133 | |
134 | struct ehci_pipe { | | 134 | struct ehci_pipe { |
135 | struct usbd_pipe pipe; | | 135 | struct usbd_pipe pipe; |
136 | int nexttoggle; | | 136 | int nexttoggle; |
137 | | | 137 | |
138 | ehci_soft_qh_t *sqh; | | 138 | ehci_soft_qh_t *sqh; |
139 | union { | | 139 | union { |
140 | /* Control pipe */ | | 140 | /* Control pipe */ |
141 | struct { | | 141 | struct { |
142 | usb_dma_t reqdma; | | 142 | usb_dma_t reqdma; |
143 | } ctrl; | | 143 | } ctrl; |
144 | /* Interrupt pipe */ | | 144 | /* Interrupt pipe */ |
145 | struct { | | 145 | struct { |
146 | u_int length; | | 146 | u_int length; |
147 | } intr; | | 147 | } intr; |
148 | /* Iso pipe */ | | 148 | /* Iso pipe */ |
149 | struct { | | 149 | struct { |
150 | u_int next_frame; | | 150 | u_int next_frame; |
151 | u_int cur_xfers; | | 151 | u_int cur_xfers; |
152 | } isoc; | | 152 | } isoc; |
153 | }; | | 153 | }; |
154 | }; | | 154 | }; |
155 | | | 155 | |
156 | typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; | | 156 | typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; |
157 | | | 157 | |
158 | Static usbd_status ehci_open(struct usbd_pipe *); | | 158 | Static usbd_status ehci_open(struct usbd_pipe *); |
159 | Static void ehci_poll(struct usbd_bus *); | | 159 | Static void ehci_poll(struct usbd_bus *); |
160 | Static void ehci_softintr(void *); | | 160 | Static void ehci_softintr(void *); |
161 | Static int ehci_intr1(ehci_softc_t *); | | 161 | Static int ehci_intr1(ehci_softc_t *); |
162 | Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, | | 162 | Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, |
163 | ex_completeq_t *); | | 163 | ex_completeq_t *); |
164 | Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, | | 164 | Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, |
165 | ex_completeq_t *); | | 165 | ex_completeq_t *); |
166 | Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, | | 166 | Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, |
167 | ex_completeq_t *); | | 167 | ex_completeq_t *); |
168 | Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); | | 168 | Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); |
169 | Static void ehci_timeout(void *); | | 169 | Static void ehci_timeout(void *); |
170 | Static void ehci_timeout_task(void *); | | 170 | Static void ehci_timeout_task(void *); |
171 | Static void ehci_intrlist_timeout(void *); | | 171 | Static void ehci_intrlist_timeout(void *); |
172 | Static void ehci_doorbell(void *); | | 172 | Static void ehci_doorbell(void *); |
173 | Static void ehci_pcd(void *); | | 173 | Static void ehci_pcd(void *); |
174 | | | 174 | |
175 | Static struct usbd_xfer * | | 175 | Static struct usbd_xfer * |
176 | ehci_allocx(struct usbd_bus *, unsigned int); | | 176 | ehci_allocx(struct usbd_bus *, unsigned int); |
177 | Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); | | 177 | Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); |
178 | | | 178 | |
179 | Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); | | 179 | Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); |
180 | Static int ehci_roothub_ctrl(struct usbd_bus *, | | 180 | Static int ehci_roothub_ctrl(struct usbd_bus *, |
181 | usb_device_request_t *, void *, int); | | 181 | usb_device_request_t *, void *, int); |
182 | | | 182 | |
183 | Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); | | 183 | Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); |
184 | Static usbd_status ehci_root_intr_start(struct usbd_xfer *); | | 184 | Static usbd_status ehci_root_intr_start(struct usbd_xfer *); |
185 | Static void ehci_root_intr_abort(struct usbd_xfer *); | | 185 | Static void ehci_root_intr_abort(struct usbd_xfer *); |
186 | Static void ehci_root_intr_close(struct usbd_pipe *); | | 186 | Static void ehci_root_intr_close(struct usbd_pipe *); |
187 | Static void ehci_root_intr_done(struct usbd_xfer *); | | 187 | Static void ehci_root_intr_done(struct usbd_xfer *); |
188 | | | 188 | |
189 | Static int ehci_device_ctrl_init(struct usbd_xfer *); | | 189 | Static int ehci_device_ctrl_init(struct usbd_xfer *); |
190 | Static void ehci_device_ctrl_fini(struct usbd_xfer *); | | 190 | Static void ehci_device_ctrl_fini(struct usbd_xfer *); |
191 | Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); | | 191 | Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); |
192 | Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); | | 192 | Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); |
193 | Static void ehci_device_ctrl_abort(struct usbd_xfer *); | | 193 | Static void ehci_device_ctrl_abort(struct usbd_xfer *); |
194 | Static void ehci_device_ctrl_close(struct usbd_pipe *); | | 194 | Static void ehci_device_ctrl_close(struct usbd_pipe *); |
195 | Static void ehci_device_ctrl_done(struct usbd_xfer *); | | 195 | Static void ehci_device_ctrl_done(struct usbd_xfer *); |
196 | | | 196 | |
197 | Static int ehci_device_bulk_init(struct usbd_xfer *); | | 197 | Static int ehci_device_bulk_init(struct usbd_xfer *); |
198 | Static void ehci_device_bulk_fini(struct usbd_xfer *); | | 198 | Static void ehci_device_bulk_fini(struct usbd_xfer *); |
199 | Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); | | 199 | Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); |
200 | Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); | | 200 | Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); |
201 | Static void ehci_device_bulk_abort(struct usbd_xfer *); | | 201 | Static void ehci_device_bulk_abort(struct usbd_xfer *); |
202 | Static void ehci_device_bulk_close(struct usbd_pipe *); | | 202 | Static void ehci_device_bulk_close(struct usbd_pipe *); |
203 | Static void ehci_device_bulk_done(struct usbd_xfer *); | | 203 | Static void ehci_device_bulk_done(struct usbd_xfer *); |
204 | | | 204 | |
205 | Static int ehci_device_intr_init(struct usbd_xfer *); | | 205 | Static int ehci_device_intr_init(struct usbd_xfer *); |
206 | Static void ehci_device_intr_fini(struct usbd_xfer *); | | 206 | Static void ehci_device_intr_fini(struct usbd_xfer *); |
207 | Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); | | 207 | Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); |
208 | Static usbd_status ehci_device_intr_start(struct usbd_xfer *); | | 208 | Static usbd_status ehci_device_intr_start(struct usbd_xfer *); |
209 | Static void ehci_device_intr_abort(struct usbd_xfer *); | | 209 | Static void ehci_device_intr_abort(struct usbd_xfer *); |
210 | Static void ehci_device_intr_close(struct usbd_pipe *); | | 210 | Static void ehci_device_intr_close(struct usbd_pipe *); |
211 | Static void ehci_device_intr_done(struct usbd_xfer *); | | 211 | Static void ehci_device_intr_done(struct usbd_xfer *); |
212 | | | 212 | |
213 | Static int ehci_device_isoc_init(struct usbd_xfer *); | | 213 | Static int ehci_device_isoc_init(struct usbd_xfer *); |
214 | Static void ehci_device_isoc_fini(struct usbd_xfer *); | | 214 | Static void ehci_device_isoc_fini(struct usbd_xfer *); |
215 | Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); | | 215 | Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); |
216 | Static void ehci_device_isoc_abort(struct usbd_xfer *); | | 216 | Static void ehci_device_isoc_abort(struct usbd_xfer *); |
217 | Static void ehci_device_isoc_close(struct usbd_pipe *); | | 217 | Static void ehci_device_isoc_close(struct usbd_pipe *); |
218 | Static void ehci_device_isoc_done(struct usbd_xfer *); | | 218 | Static void ehci_device_isoc_done(struct usbd_xfer *); |
219 | | | 219 | |
220 | Static int ehci_device_fs_isoc_init(struct usbd_xfer *); | | 220 | Static int ehci_device_fs_isoc_init(struct usbd_xfer *); |
221 | Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); | | 221 | Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); |
222 | Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); | | 222 | Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); |
223 | Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); | | 223 | Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); |
224 | Static void ehci_device_fs_isoc_close(struct usbd_pipe *); | | 224 | Static void ehci_device_fs_isoc_close(struct usbd_pipe *); |
225 | Static void ehci_device_fs_isoc_done(struct usbd_xfer *); | | 225 | Static void ehci_device_fs_isoc_done(struct usbd_xfer *); |
226 | | | 226 | |
227 | Static void ehci_device_clear_toggle(struct usbd_pipe *); | | 227 | Static void ehci_device_clear_toggle(struct usbd_pipe *); |
228 | Static void ehci_noop(struct usbd_pipe *); | | 228 | Static void ehci_noop(struct usbd_pipe *); |
229 | | | 229 | |
230 | Static void ehci_disown(ehci_softc_t *, int, int); | | 230 | Static void ehci_disown(ehci_softc_t *, int, int); |
231 | | | 231 | |
232 | Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); | | 232 | Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); |
233 | Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); | | 233 | Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); |
234 | | | 234 | |
235 | Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); | | 235 | Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); |
236 | Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); | | 236 | Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); |
237 | Static int ehci_alloc_sqtd_chain(ehci_softc_t *, | | 237 | Static int ehci_alloc_sqtd_chain(ehci_softc_t *, |
238 | struct usbd_xfer *, int, int, ehci_soft_qtd_t **); | | 238 | struct usbd_xfer *, int, int, ehci_soft_qtd_t **); |
239 | Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); | | 239 | Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); |
240 | | | 240 | |
241 | Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, | | 241 | Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, |
242 | int, int, int *, ehci_soft_qtd_t **); | | 242 | int, int, int *, ehci_soft_qtd_t **); |
243 | Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *); | | 243 | Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *); |
244 | | | 244 | |
245 | Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); | | 245 | Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); |
246 | Static ehci_soft_sitd_t * | | 246 | Static ehci_soft_sitd_t * |
247 | ehci_alloc_sitd(ehci_softc_t *); | | 247 | ehci_alloc_sitd(ehci_softc_t *); |
248 | | | 248 | |
249 | Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); | | 249 | Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); |
250 | Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); | | 250 | Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); |
251 | Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); | | 251 | Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); |
252 | Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); | | 252 | Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); |
253 | | | 253 | |
254 | static inline void | | 254 | static inline void |
255 | ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) | | 255 | ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) |
256 | { | | 256 | { |
257 | | | 257 | |
258 | LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); | | 258 | LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); |
259 | } | | 259 | } |
260 | | | 260 | |
261 | static inline void | | 261 | static inline void |
262 | ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) | | 262 | ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) |
263 | { | | 263 | { |
264 | | | 264 | |
265 | LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); | | 265 | LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); |
266 | } | | 266 | } |
267 | | | 267 | |
268 | Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); | | 268 | Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); |
269 | | | 269 | |
270 | Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, | | 270 | Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, |
271 | int); | | 271 | int); |
272 | | | 272 | |
273 | Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, | | 273 | Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, |
274 | ehci_soft_qh_t *); | | 274 | ehci_soft_qh_t *); |
275 | Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, | | 275 | Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, |
276 | ehci_soft_qh_t *); | | 276 | ehci_soft_qh_t *); |
277 | Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); | | 277 | Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); |
278 | Static void ehci_sync_hc(ehci_softc_t *); | | 278 | Static void ehci_sync_hc(ehci_softc_t *); |
279 | | | 279 | |
280 | Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); | | 280 | Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); |
281 | Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); | | 281 | Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); |
282 | | | 282 | |
283 | #ifdef EHCI_DEBUG | | 283 | #ifdef EHCI_DEBUG |
284 | Static ehci_softc_t *theehci; | | 284 | Static ehci_softc_t *theehci; |
285 | void ehci_dump(void); | | 285 | void ehci_dump(void); |
286 | #endif | | 286 | #endif |
287 | | | 287 | |
288 | #ifdef EHCI_DEBUG | | 288 | #ifdef EHCI_DEBUG |
289 | Static void ehci_dump_regs(ehci_softc_t *); | | 289 | Static void ehci_dump_regs(ehci_softc_t *); |
290 | Static void ehci_dump_sqtds(ehci_soft_qtd_t *); | | 290 | Static void ehci_dump_sqtds(ehci_soft_qtd_t *); |
291 | Static void ehci_dump_sqtd(ehci_soft_qtd_t *); | | 291 | Static void ehci_dump_sqtd(ehci_soft_qtd_t *); |
292 | Static void ehci_dump_qtd(ehci_qtd_t *); | | 292 | Static void ehci_dump_qtd(ehci_qtd_t *); |
293 | Static void ehci_dump_sqh(ehci_soft_qh_t *); | | 293 | Static void ehci_dump_sqh(ehci_soft_qh_t *); |
294 | Static void ehci_dump_sitd(struct ehci_soft_itd *); | | 294 | Static void ehci_dump_sitd(struct ehci_soft_itd *); |
295 | Static void ehci_dump_itds(ehci_soft_itd_t *); | | 295 | Static void ehci_dump_itds(ehci_soft_itd_t *); |
296 | Static void ehci_dump_itd(struct ehci_soft_itd *); | | 296 | Static void ehci_dump_itd(struct ehci_soft_itd *); |
297 | Static void ehci_dump_exfer(struct ehci_xfer *); | | 297 | Static void ehci_dump_exfer(struct ehci_xfer *); |
298 | #endif | | 298 | #endif |
299 | | | 299 | |
300 | #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) | | 300 | #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) |
301 | | | 301 | |
302 | static inline void | | 302 | static inline void |
303 | ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) | | 303 | ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) |
304 | { | | 304 | { |
305 | | | 305 | |
306 | TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); | | 306 | TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); |
307 | } | | 307 | } |
308 | | | 308 | |
309 | static inline void | | 309 | static inline void |
310 | ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) | | 310 | ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) |
311 | { | | 311 | { |
312 | | | 312 | |
313 | TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); | | 313 | TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); |
314 | } | | 314 | } |
315 | | | 315 | |
316 | Static const struct usbd_bus_methods ehci_bus_methods = { | | 316 | Static const struct usbd_bus_methods ehci_bus_methods = { |
317 | .ubm_open = ehci_open, | | 317 | .ubm_open = ehci_open, |
318 | .ubm_softint = ehci_softintr, | | 318 | .ubm_softint = ehci_softintr, |
319 | .ubm_dopoll = ehci_poll, | | 319 | .ubm_dopoll = ehci_poll, |
320 | .ubm_allocx = ehci_allocx, | | 320 | .ubm_allocx = ehci_allocx, |
321 | .ubm_freex = ehci_freex, | | 321 | .ubm_freex = ehci_freex, |
322 | .ubm_getlock = ehci_get_lock, | | 322 | .ubm_getlock = ehci_get_lock, |
323 | .ubm_rhctrl = ehci_roothub_ctrl, | | 323 | .ubm_rhctrl = ehci_roothub_ctrl, |
324 | }; | | 324 | }; |
325 | | | 325 | |
326 | Static const struct usbd_pipe_methods ehci_root_intr_methods = { | | 326 | Static const struct usbd_pipe_methods ehci_root_intr_methods = { |
327 | .upm_transfer = ehci_root_intr_transfer, | | 327 | .upm_transfer = ehci_root_intr_transfer, |
328 | .upm_start = ehci_root_intr_start, | | 328 | .upm_start = ehci_root_intr_start, |
329 | .upm_abort = ehci_root_intr_abort, | | 329 | .upm_abort = ehci_root_intr_abort, |
330 | .upm_close = ehci_root_intr_close, | | 330 | .upm_close = ehci_root_intr_close, |
331 | .upm_cleartoggle = ehci_noop, | | 331 | .upm_cleartoggle = ehci_noop, |
332 | .upm_done = ehci_root_intr_done, | | 332 | .upm_done = ehci_root_intr_done, |
333 | }; | | 333 | }; |
334 | | | 334 | |
335 | Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { | | 335 | Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { |
336 | .upm_init = ehci_device_ctrl_init, | | 336 | .upm_init = ehci_device_ctrl_init, |
337 | .upm_fini = ehci_device_ctrl_fini, | | 337 | .upm_fini = ehci_device_ctrl_fini, |
338 | .upm_transfer = ehci_device_ctrl_transfer, | | 338 | .upm_transfer = ehci_device_ctrl_transfer, |
339 | .upm_start = ehci_device_ctrl_start, | | 339 | .upm_start = ehci_device_ctrl_start, |
340 | .upm_abort = ehci_device_ctrl_abort, | | 340 | .upm_abort = ehci_device_ctrl_abort, |
341 | .upm_close = ehci_device_ctrl_close, | | 341 | .upm_close = ehci_device_ctrl_close, |
342 | .upm_cleartoggle = ehci_noop, | | 342 | .upm_cleartoggle = ehci_noop, |
343 | .upm_done = ehci_device_ctrl_done, | | 343 | .upm_done = ehci_device_ctrl_done, |
344 | }; | | 344 | }; |
345 | | | 345 | |
346 | Static const struct usbd_pipe_methods ehci_device_intr_methods = { | | 346 | Static const struct usbd_pipe_methods ehci_device_intr_methods = { |
347 | .upm_init = ehci_device_intr_init, | | 347 | .upm_init = ehci_device_intr_init, |
348 | .upm_fini = ehci_device_intr_fini, | | 348 | .upm_fini = ehci_device_intr_fini, |
349 | .upm_transfer = ehci_device_intr_transfer, | | 349 | .upm_transfer = ehci_device_intr_transfer, |
350 | .upm_start = ehci_device_intr_start, | | 350 | .upm_start = ehci_device_intr_start, |
351 | .upm_abort = ehci_device_intr_abort, | | 351 | .upm_abort = ehci_device_intr_abort, |
352 | .upm_close = ehci_device_intr_close, | | 352 | .upm_close = ehci_device_intr_close, |
353 | .upm_cleartoggle = ehci_device_clear_toggle, | | 353 | .upm_cleartoggle = ehci_device_clear_toggle, |
354 | .upm_done = ehci_device_intr_done, | | 354 | .upm_done = ehci_device_intr_done, |
355 | }; | | 355 | }; |
356 | | | 356 | |
357 | Static const struct usbd_pipe_methods ehci_device_bulk_methods = { | | 357 | Static const struct usbd_pipe_methods ehci_device_bulk_methods = { |
358 | .upm_init = ehci_device_bulk_init, | | 358 | .upm_init = ehci_device_bulk_init, |
359 | .upm_fini = ehci_device_bulk_fini, | | 359 | .upm_fini = ehci_device_bulk_fini, |
360 | .upm_transfer = ehci_device_bulk_transfer, | | 360 | .upm_transfer = ehci_device_bulk_transfer, |
361 | .upm_start = ehci_device_bulk_start, | | 361 | .upm_start = ehci_device_bulk_start, |
362 | .upm_abort = ehci_device_bulk_abort, | | 362 | .upm_abort = ehci_device_bulk_abort, |
363 | .upm_close = ehci_device_bulk_close, | | 363 | .upm_close = ehci_device_bulk_close, |
364 | .upm_cleartoggle = ehci_device_clear_toggle, | | 364 | .upm_cleartoggle = ehci_device_clear_toggle, |
365 | .upm_done = ehci_device_bulk_done, | | 365 | .upm_done = ehci_device_bulk_done, |
366 | }; | | 366 | }; |
367 | | | 367 | |
368 | Static const struct usbd_pipe_methods ehci_device_isoc_methods = { | | 368 | Static const struct usbd_pipe_methods ehci_device_isoc_methods = { |
369 | .upm_init = ehci_device_isoc_init, | | 369 | .upm_init = ehci_device_isoc_init, |
370 | .upm_fini = ehci_device_isoc_fini, | | 370 | .upm_fini = ehci_device_isoc_fini, |
371 | .upm_transfer = ehci_device_isoc_transfer, | | 371 | .upm_transfer = ehci_device_isoc_transfer, |
372 | .upm_abort = ehci_device_isoc_abort, | | 372 | .upm_abort = ehci_device_isoc_abort, |
373 | .upm_close = ehci_device_isoc_close, | | 373 | .upm_close = ehci_device_isoc_close, |
374 | .upm_cleartoggle = ehci_noop, | | 374 | .upm_cleartoggle = ehci_noop, |
375 | .upm_done = ehci_device_isoc_done, | | 375 | .upm_done = ehci_device_isoc_done, |
376 | }; | | 376 | }; |
377 | | | 377 | |
378 | Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { | | 378 | Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { |
379 | .upm_init = ehci_device_fs_isoc_init, | | 379 | .upm_init = ehci_device_fs_isoc_init, |
380 | .upm_fini = ehci_device_fs_isoc_fini, | | 380 | .upm_fini = ehci_device_fs_isoc_fini, |
381 | .upm_transfer = ehci_device_fs_isoc_transfer, | | 381 | .upm_transfer = ehci_device_fs_isoc_transfer, |
382 | .upm_abort = ehci_device_fs_isoc_abort, | | 382 | .upm_abort = ehci_device_fs_isoc_abort, |
383 | .upm_close = ehci_device_fs_isoc_close, | | 383 | .upm_close = ehci_device_fs_isoc_close, |
384 | .upm_cleartoggle = ehci_noop, | | 384 | .upm_cleartoggle = ehci_noop, |
385 | .upm_done = ehci_device_fs_isoc_done, | | 385 | .upm_done = ehci_device_fs_isoc_done, |
386 | }; | | 386 | }; |
387 | | | 387 | |
388 | static const uint8_t revbits[EHCI_MAX_POLLRATE] = { | | 388 | static const uint8_t revbits[EHCI_MAX_POLLRATE] = { |
389 | 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, | | 389 | 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, |
390 | 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, | | 390 | 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, |
391 | 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, | | 391 | 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, |
392 | 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, | | 392 | 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, |
393 | 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, | | 393 | 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, |
394 | 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, | | 394 | 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, |
395 | 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, | | 395 | 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, |
396 | 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, | | 396 | 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, |
397 | }; | | 397 | }; |
398 | | | 398 | |
399 | int | | 399 | int |
400 | ehci_init(ehci_softc_t *sc) | | 400 | ehci_init(ehci_softc_t *sc) |
401 | { | | 401 | { |
402 | uint32_t vers, sparams, cparams, hcr; | | 402 | uint32_t vers, sparams, cparams, hcr; |
403 | u_int i; | | 403 | u_int i; |
404 | usbd_status err; | | 404 | usbd_status err; |
405 | ehci_soft_qh_t *sqh; | | 405 | ehci_soft_qh_t *sqh; |
406 | u_int ncomp; | | 406 | u_int ncomp; |
407 | | | 407 | |
408 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 408 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
409 | #ifdef EHCI_DEBUG | | 409 | #ifdef EHCI_DEBUG |
410 | theehci = sc; | | 410 | theehci = sc; |
411 | #endif | | 411 | #endif |
412 | | | 412 | |
413 | mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); | | 413 | mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); |
414 | mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); | | 414 | mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); |
415 | cv_init(&sc->sc_softwake_cv, "ehciab"); | | 415 | cv_init(&sc->sc_softwake_cv, "ehciab"); |
416 | cv_init(&sc->sc_doorbell, "ehcidi"); | | 416 | cv_init(&sc->sc_doorbell, "ehcidi"); |
417 | | | 417 | |
418 | sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, | | 418 | sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, |
419 | "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); | | 419 | "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); |
420 | | | 420 | |
421 | sc->sc_doorbell_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, | | 421 | sc->sc_doorbell_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, |
422 | ehci_doorbell, sc); | | 422 | ehci_doorbell, sc); |
423 | KASSERT(sc->sc_doorbell_si != NULL); | | 423 | KASSERT(sc->sc_doorbell_si != NULL); |
424 | sc->sc_pcd_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, | | 424 | sc->sc_pcd_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, |
425 | ehci_pcd, sc); | | 425 | ehci_pcd, sc); |
426 | KASSERT(sc->sc_pcd_si != NULL); | | 426 | KASSERT(sc->sc_pcd_si != NULL); |
427 | | | 427 | |
428 | sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); | | 428 | sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); |
429 | | | 429 | |
430 | vers = EREAD2(sc, EHCI_HCIVERSION); | | 430 | vers = EREAD2(sc, EHCI_HCIVERSION); |
431 | aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), | | 431 | aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), |
432 | vers >> 8, vers & 0xff); | | 432 | vers >> 8, vers & 0xff); |
433 | | | 433 | |
434 | sparams = EREAD4(sc, EHCI_HCSPARAMS); | | 434 | sparams = EREAD4(sc, EHCI_HCSPARAMS); |
435 | DPRINTF("sparams=%#x", sparams, 0, 0, 0); | | 435 | DPRINTF("sparams=%#x", sparams, 0, 0, 0); |
436 | sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); | | 436 | sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); |
437 | ncomp = EHCI_HCS_N_CC(sparams); | | 437 | ncomp = EHCI_HCS_N_CC(sparams); |
438 | if (ncomp != sc->sc_ncomp) { | | 438 | if (ncomp != sc->sc_ncomp) { |
439 | aprint_verbose("%s: wrong number of companions (%d != %d)\n", | | 439 | aprint_verbose("%s: wrong number of companions (%d != %d)\n", |
440 | device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); | | 440 | device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); |
441 | #if NOHCI == 0 || NUHCI == 0 | | 441 | #if NOHCI == 0 || NUHCI == 0 |
442 | aprint_error("%s: ohci or uhci probably not configured\n", | | 442 | aprint_error("%s: ohci or uhci probably not configured\n", |
443 | device_xname(sc->sc_dev)); | | 443 | device_xname(sc->sc_dev)); |
444 | #endif | | 444 | #endif |
445 | if (ncomp < sc->sc_ncomp) | | 445 | if (ncomp < sc->sc_ncomp) |
446 | sc->sc_ncomp = ncomp; | | 446 | sc->sc_ncomp = ncomp; |
447 | } | | 447 | } |
448 | if (sc->sc_ncomp > 0) { | | 448 | if (sc->sc_ncomp > 0) { |
449 | KASSERT(!(sc->sc_flags & EHCIF_ETTF)); | | 449 | KASSERT(!(sc->sc_flags & EHCIF_ETTF)); |
450 | aprint_normal("%s: companion controller%s, %d port%s each:", | | 450 | aprint_normal("%s: companion controller%s, %d port%s each:", |
451 | device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", | | 451 | device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", |
452 | EHCI_HCS_N_PCC(sparams), | | 452 | EHCI_HCS_N_PCC(sparams), |
453 | EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); | | 453 | EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); |
454 | for (i = 0; i < sc->sc_ncomp; i++) | | 454 | for (i = 0; i < sc->sc_ncomp; i++) |
455 | aprint_normal(" %s", device_xname(sc->sc_comps[i])); | | 455 | aprint_normal(" %s", device_xname(sc->sc_comps[i])); |
456 | aprint_normal("\n"); | | 456 | aprint_normal("\n"); |
457 | } | | 457 | } |
458 | sc->sc_noport = EHCI_HCS_N_PORTS(sparams); | | 458 | sc->sc_noport = EHCI_HCS_N_PORTS(sparams); |
459 | sc->sc_hasppc = EHCI_HCS_PPC(sparams); | | 459 | sc->sc_hasppc = EHCI_HCS_PPC(sparams); |
460 | | | 460 | |
461 | cparams = EREAD4(sc, EHCI_HCCPARAMS); | | 461 | cparams = EREAD4(sc, EHCI_HCCPARAMS); |
462 | DPRINTF("cparams=%#x", cparams, 0, 0, 0); | | 462 | DPRINTF("cparams=%#x", cparams, 0, 0, 0); |
463 | | | 463 | |
464 | if (EHCI_HCC_64BIT(cparams)) { | | 464 | if (EHCI_HCC_64BIT(cparams)) { |
465 | /* MUST clear segment register if 64 bit capable. */ | | 465 | /* MUST clear segment register if 64 bit capable. */ |
466 | EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); | | 466 | EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); |
467 | } | | 467 | } |
468 | | | 468 | |
469 | if (cparams & EHCI_HCC_IST_FULLFRAME) { | | 469 | if (cparams & EHCI_HCC_IST_FULLFRAME) { |
470 | sc->sc_istthreshold = 0; | | 470 | sc->sc_istthreshold = 0; |
471 | } else { | | 471 | } else { |
472 | sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(cparams); | | 472 | sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(cparams); |
473 | } | | 473 | } |
474 | | | 474 | |
475 | sc->sc_bus.ub_revision = USBREV_2_0; | | 475 | sc->sc_bus.ub_revision = USBREV_2_0; |
476 | sc->sc_bus.ub_usedma = true; | | 476 | sc->sc_bus.ub_usedma = true; |
477 | sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; | | 477 | sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; |
478 | | | 478 | |
479 | /* Reset the controller */ | | 479 | /* Reset the controller */ |
480 | DPRINTF("resetting", 0, 0, 0, 0); | | 480 | DPRINTF("resetting", 0, 0, 0, 0); |
481 | EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ | | 481 | EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ |
482 | usb_delay_ms(&sc->sc_bus, 1); | | 482 | usb_delay_ms(&sc->sc_bus, 1); |
483 | EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); | | 483 | EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); |
484 | for (i = 0; i < 100; i++) { | | 484 | for (i = 0; i < 100; i++) { |
485 | usb_delay_ms(&sc->sc_bus, 1); | | 485 | usb_delay_ms(&sc->sc_bus, 1); |
486 | hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; | | 486 | hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; |
487 | if (!hcr) | | 487 | if (!hcr) |
488 | break; | | 488 | break; |
489 | } | | 489 | } |
490 | if (hcr) { | | 490 | if (hcr) { |
491 | aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); | | 491 | aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); |
492 | return EIO; | | 492 | return EIO; |
493 | } | | 493 | } |
494 | if (sc->sc_vendor_init) | | 494 | if (sc->sc_vendor_init) |
495 | sc->sc_vendor_init(sc); | | 495 | sc->sc_vendor_init(sc); |
496 | | | 496 | |
497 | /* XXX need proper intr scheduling */ | | 497 | /* XXX need proper intr scheduling */ |
498 | sc->sc_rand = 96; | | 498 | sc->sc_rand = 96; |
499 | | | 499 | |
500 | /* frame list size at default, read back what we got and use that */ | | 500 | /* frame list size at default, read back what we got and use that */ |
501 | switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { | | 501 | switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { |
502 | case 0: sc->sc_flsize = 1024; break; | | 502 | case 0: sc->sc_flsize = 1024; break; |
503 | case 1: sc->sc_flsize = 512; break; | | 503 | case 1: sc->sc_flsize = 512; break; |
504 | case 2: sc->sc_flsize = 256; break; | | 504 | case 2: sc->sc_flsize = 256; break; |
505 | case 3: return EIO; | | 505 | case 3: return EIO; |
506 | } | | 506 | } |
507 | err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), | | 507 | err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), |
508 | EHCI_FLALIGN_ALIGN, &sc->sc_fldma); | | 508 | EHCI_FLALIGN_ALIGN, &sc->sc_fldma); |
509 | if (err) | | 509 | if (err) |
510 | return err; | | 510 | return err; |
511 | DPRINTF("flsize=%d", sc->sc_flsize, 0, 0, 0); | | 511 | DPRINTF("flsize=%d", sc->sc_flsize, 0, 0, 0); |
512 | sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); | | 512 | sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); |
513 | | | 513 | |
514 | for (i = 0; i < sc->sc_flsize; i++) { | | 514 | for (i = 0; i < sc->sc_flsize; i++) { |
515 | sc->sc_flist[i] = EHCI_NULL; | | 515 | sc->sc_flist[i] = EHCI_NULL; |
516 | } | | 516 | } |
517 | | | 517 | |
518 | EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); | | 518 | EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); |
519 | | | 519 | |
520 | sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), | | 520 | sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), |
521 | KM_SLEEP); | | 521 | KM_SLEEP); |
522 | if (sc->sc_softitds == NULL) | | 522 | if (sc->sc_softitds == NULL) |
523 | return ENOMEM; | | 523 | return ENOMEM; |
524 | LIST_INIT(&sc->sc_freeitds); | | 524 | LIST_INIT(&sc->sc_freeitds); |
525 | LIST_INIT(&sc->sc_freesitds); | | 525 | LIST_INIT(&sc->sc_freesitds); |
526 | TAILQ_INIT(&sc->sc_intrhead); | | 526 | TAILQ_INIT(&sc->sc_intrhead); |
527 | | | 527 | |
528 | /* Set up the bus struct. */ | | 528 | /* Set up the bus struct. */ |
529 | sc->sc_bus.ub_methods = &ehci_bus_methods; | | 529 | sc->sc_bus.ub_methods = &ehci_bus_methods; |
530 | sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); | | 530 | sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); |
531 | | | 531 | |
532 | sc->sc_eintrs = EHCI_NORMAL_INTRS; | | 532 | sc->sc_eintrs = EHCI_NORMAL_INTRS; |
533 | | | 533 | |
534 | /* | | 534 | /* |
535 | * Allocate the interrupt dummy QHs. These are arranged to give poll | | 535 | * Allocate the interrupt dummy QHs. These are arranged to give poll |
536 | * intervals that are powers of 2 times 1ms. | | 536 | * intervals that are powers of 2 times 1ms. |
537 | */ | | 537 | */ |
538 | for (i = 0; i < EHCI_INTRQHS; i++) { | | 538 | for (i = 0; i < EHCI_INTRQHS; i++) { |
539 | sqh = ehci_alloc_sqh(sc); | | 539 | sqh = ehci_alloc_sqh(sc); |
540 | if (sqh == NULL) { | | 540 | if (sqh == NULL) { |
541 | err = ENOMEM; | | 541 | err = ENOMEM; |
542 | goto bad1; | | 542 | goto bad1; |
543 | } | | 543 | } |
544 | sc->sc_islots[i].sqh = sqh; | | 544 | sc->sc_islots[i].sqh = sqh; |
545 | } | | 545 | } |
546 | for (i = 0; i < EHCI_INTRQHS; i++) { | | 546 | for (i = 0; i < EHCI_INTRQHS; i++) { |
547 | sqh = sc->sc_islots[i].sqh; | | 547 | sqh = sc->sc_islots[i].sqh; |
548 | if (i == 0) { | | 548 | if (i == 0) { |
549 | /* The last (1ms) QH terminates. */ | | 549 | /* The last (1ms) QH terminates. */ |
550 | sqh->qh.qh_link = EHCI_NULL; | | 550 | sqh->qh.qh_link = EHCI_NULL; |
551 | sqh->next = NULL; | | 551 | sqh->next = NULL; |
552 | } else { | | 552 | } else { |
553 | /* Otherwise the next QH has half the poll interval */ | | 553 | /* Otherwise the next QH has half the poll interval */ |
554 | sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; | | 554 | sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; |
555 | sqh->qh.qh_link = htole32(sqh->next->physaddr | | | 555 | sqh->qh.qh_link = htole32(sqh->next->physaddr | |
556 | EHCI_LINK_QH); | | 556 | EHCI_LINK_QH); |
557 | } | | 557 | } |
558 | sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); | | 558 | sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); |
559 | sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); | | 559 | sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); |
560 | sqh->qh.qh_curqtd = EHCI_NULL; | | 560 | sqh->qh.qh_curqtd = EHCI_NULL; |
561 | sqh->qh.qh_qtd.qtd_next = EHCI_NULL; | | 561 | sqh->qh.qh_qtd.qtd_next = EHCI_NULL; |
562 | sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; | | 562 | sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; |
563 | sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); | | 563 | sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); |
564 | sqh->sqtd = NULL; | | 564 | sqh->sqtd = NULL; |
565 | usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), | | 565 | usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), |
566 | BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); | | 566 | BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); |
567 | } | | 567 | } |
568 | /* Point the frame list at the last level (128ms). */ | | 568 | /* Point the frame list at the last level (128ms). */ |
569 | for (i = 0; i < sc->sc_flsize; i++) { | | 569 | for (i = 0; i < sc->sc_flsize; i++) { |
570 | int j; | | 570 | int j; |
571 | | | 571 | |
572 | j = (i & ~(EHCI_MAX_POLLRATE-1)) | | | 572 | j = (i & ~(EHCI_MAX_POLLRATE-1)) | |
573 | revbits[i & (EHCI_MAX_POLLRATE-1)]; | | 573 | revbits[i & (EHCI_MAX_POLLRATE-1)]; |
574 | sc->sc_flist[j] = htole32(EHCI_LINK_QH | | | 574 | sc->sc_flist[j] = htole32(EHCI_LINK_QH | |
575 | sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, | | 575 | sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, |
576 | i)].sqh->physaddr); | | 576 | i)].sqh->physaddr); |
577 | } | | 577 | } |
578 | usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), | | 578 | usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), |
579 | BUS_DMASYNC_PREWRITE); | | 579 | BUS_DMASYNC_PREWRITE); |
580 | | | 580 | |
581 | /* Allocate dummy QH that starts the async list. */ | | 581 | /* Allocate dummy QH that starts the async list. */ |
582 | sqh = ehci_alloc_sqh(sc); | | 582 | sqh = ehci_alloc_sqh(sc); |
583 | if (sqh == NULL) { | | 583 | if (sqh == NULL) { |
584 | err = ENOMEM; | | 584 | err = ENOMEM; |
585 | goto bad1; | | 585 | goto bad1; |
586 | } | | 586 | } |
587 | /* Fill the QH */ | | 587 | /* Fill the QH */ |
588 | sqh->qh.qh_endp = | | 588 | sqh->qh.qh_endp = |
589 | htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); | | 589 | htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); |
590 | sqh->qh.qh_link = | | 590 | sqh->qh.qh_link = |
591 | htole32(sqh->physaddr | EHCI_LINK_QH); | | 591 | htole32(sqh->physaddr | EHCI_LINK_QH); |
592 | sqh->qh.qh_curqtd = EHCI_NULL; | | 592 | sqh->qh.qh_curqtd = EHCI_NULL; |
593 | sqh->next = NULL; | | 593 | sqh->next = NULL; |
594 | /* Fill the overlay qTD */ | | 594 | /* Fill the overlay qTD */ |
595 | sqh->qh.qh_qtd.qtd_next = EHCI_NULL; | | 595 | sqh->qh.qh_qtd.qtd_next = EHCI_NULL; |
596 | sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; | | 596 | sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; |
597 | sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); | | 597 | sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); |
598 | sqh->sqtd = NULL; | | 598 | sqh->sqtd = NULL; |
599 | usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), | | 599 | usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), |
600 | BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); | | 600 | BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); |
601 | #ifdef EHCI_DEBUG | | 601 | #ifdef EHCI_DEBUG |
602 | DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); | | 602 | DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); |
603 | ehci_dump_sqh(sqh); | | 603 | ehci_dump_sqh(sqh); |
604 | DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); | | 604 | DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); |
605 | #endif | | 605 | #endif |
606 | | | 606 | |
607 | /* Point to async list */ | | 607 | /* Point to async list */ |
608 | sc->sc_async_head = sqh; | | 608 | sc->sc_async_head = sqh; |
609 | EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); | | 609 | EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); |
610 | | | 610 | |
611 | callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); | | 611 | callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); |
612 | | | 612 | |
613 | /* Turn on controller */ | | 613 | /* Turn on controller */ |
614 | EOWRITE4(sc, EHCI_USBCMD, | | 614 | EOWRITE4(sc, EHCI_USBCMD, |
615 | EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ | | 615 | EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ |
616 | (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | | | 616 | (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | |
617 | EHCI_CMD_ASE | | | 617 | EHCI_CMD_ASE | |
618 | EHCI_CMD_PSE | | | 618 | EHCI_CMD_PSE | |
619 | EHCI_CMD_RS); | | 619 | EHCI_CMD_RS); |
620 | | | 620 | |
621 | /* Take over port ownership */ | | 621 | /* Take over port ownership */ |
622 | EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); | | 622 | EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); |
623 | | | 623 | |
624 | for (i = 0; i < 100; i++) { | | 624 | for (i = 0; i < 100; i++) { |
625 | usb_delay_ms(&sc->sc_bus, 1); | | 625 | usb_delay_ms(&sc->sc_bus, 1); |
626 | hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; | | 626 | hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; |
627 | if (!hcr) | | 627 | if (!hcr) |
628 | break; | | 628 | break; |
629 | } | | 629 | } |
630 | if (hcr) { | | 630 | if (hcr) { |
631 | aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); | | 631 | aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); |
632 | return EIO; | | 632 | return EIO; |
633 | } | | 633 | } |
634 | | | 634 | |
635 | /* Enable interrupts */ | | 635 | /* Enable interrupts */ |
636 | DPRINTF("enabling interupts", 0, 0, 0, 0); | | 636 | DPRINTF("enabling interupts", 0, 0, 0, 0); |
637 | EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); | | 637 | EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); |
638 | | | 638 | |
639 | return 0; | | 639 | return 0; |
640 | | | 640 | |
641 | #if 0 | | 641 | #if 0 |
642 | bad2: | | 642 | bad2: |
643 | ehci_free_sqh(sc, sc->sc_async_head); | | 643 | ehci_free_sqh(sc, sc->sc_async_head); |
644 | #endif | | 644 | #endif |
645 | bad1: | | 645 | bad1: |
646 | usb_freemem(&sc->sc_bus, &sc->sc_fldma); | | 646 | usb_freemem(&sc->sc_bus, &sc->sc_fldma); |
647 | return err; | | 647 | return err; |
648 | } | | 648 | } |
649 | | | 649 | |
650 | int | | 650 | int |
651 | ehci_intr(void *v) | | 651 | ehci_intr(void *v) |
652 | { | | 652 | { |
653 | ehci_softc_t *sc = v; | | 653 | ehci_softc_t *sc = v; |
654 | int ret = 0; | | 654 | int ret = 0; |
655 | | | 655 | |
656 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 656 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
657 | | | 657 | |
658 | if (sc == NULL) | | 658 | if (sc == NULL) |
659 | return 0; | | 659 | return 0; |
660 | | | 660 | |
661 | mutex_spin_enter(&sc->sc_intr_lock); | | 661 | mutex_spin_enter(&sc->sc_intr_lock); |
662 | | | 662 | |
663 | if (sc->sc_dying || !device_has_power(sc->sc_dev)) | | 663 | if (sc->sc_dying || !device_has_power(sc->sc_dev)) |
664 | goto done; | | 664 | goto done; |
665 | | | 665 | |
666 | /* If we get an interrupt while polling, then just ignore it. */ | | 666 | /* If we get an interrupt while polling, then just ignore it. */ |
667 | if (sc->sc_bus.ub_usepolling) { | | 667 | if (sc->sc_bus.ub_usepolling) { |
668 | uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); | | 668 | uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); |
669 | | | 669 | |
670 | if (intrs) | | 670 | if (intrs) |
671 | EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ | | 671 | EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ |
672 | DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); | | 672 | DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); |
673 | goto done; | | 673 | goto done; |
674 | } | | 674 | } |
675 | | | 675 | |
676 | ret = ehci_intr1(sc); | | 676 | ret = ehci_intr1(sc); |
677 | | | 677 | |
678 | done: | | 678 | done: |
679 | mutex_spin_exit(&sc->sc_intr_lock); | | 679 | mutex_spin_exit(&sc->sc_intr_lock); |
680 | return ret; | | 680 | return ret; |
681 | } | | 681 | } |
682 | | | 682 | |
683 | Static int | | 683 | Static int |
684 | ehci_intr1(ehci_softc_t *sc) | | 684 | ehci_intr1(ehci_softc_t *sc) |
685 | { | | 685 | { |
686 | uint32_t intrs, eintrs; | | 686 | uint32_t intrs, eintrs; |
687 | | | 687 | |
688 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 688 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
689 | | | 689 | |
690 | /* In case the interrupt occurs before initialization has completed. */ | | 690 | /* In case the interrupt occurs before initialization has completed. */ |
691 | if (sc == NULL) { | | 691 | if (sc == NULL) { |
692 | #ifdef DIAGNOSTIC | | 692 | #ifdef DIAGNOSTIC |
693 | printf("ehci_intr1: sc == NULL\n"); | | 693 | printf("ehci_intr1: sc == NULL\n"); |
694 | #endif | | 694 | #endif |
695 | return 0; | | 695 | return 0; |
696 | } | | 696 | } |
697 | | | 697 | |
698 | KASSERT(mutex_owned(&sc->sc_intr_lock)); | | 698 | KASSERT(mutex_owned(&sc->sc_intr_lock)); |
699 | | | 699 | |
700 | intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); | | 700 | intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); |
701 | if (!intrs) | | 701 | if (!intrs) |
702 | return 0; | | 702 | return 0; |
703 | | | 703 | |
704 | eintrs = intrs & sc->sc_eintrs; | | 704 | eintrs = intrs & sc->sc_eintrs; |
705 | DPRINTF("sc=%p intrs=%#x(%#x) eintrs=%#x", sc, intrs, | | 705 | DPRINTF("sc=%p intrs=%#x(%#x) eintrs=%#x", sc, intrs, |
706 | EOREAD4(sc, EHCI_USBSTS), eintrs); | | 706 | EOREAD4(sc, EHCI_USBSTS), eintrs); |
707 | if (!eintrs) | | 707 | if (!eintrs) |
708 | return 0; | | 708 | return 0; |
709 | | | 709 | |
710 | EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ | | 710 | EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ |
711 | if (eintrs & EHCI_STS_IAA) { | | 711 | if (eintrs & EHCI_STS_IAA) { |
712 | DPRINTF("door bell", 0, 0, 0, 0); | | 712 | DPRINTF("door bell", 0, 0, 0, 0); |
713 | kpreempt_disable(); | | 713 | kpreempt_disable(); |
714 | KASSERT(sc->sc_doorbell_si != NULL); | | 714 | KASSERT(sc->sc_doorbell_si != NULL); |
715 | softint_schedule(sc->sc_doorbell_si); | | 715 | softint_schedule(sc->sc_doorbell_si); |
716 | kpreempt_enable(); | | 716 | kpreempt_enable(); |
717 | eintrs &= ~EHCI_STS_IAA; | | 717 | eintrs &= ~EHCI_STS_IAA; |
718 | } | | 718 | } |
719 | if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { | | 719 | if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { |
720 | DPRINTF("INT=%d ERRINT=%d", | | 720 | DPRINTF("INT=%d ERRINT=%d", |
721 | eintrs & EHCI_STS_INT ? 1 : 0, | | 721 | eintrs & EHCI_STS_INT ? 1 : 0, |
722 | eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); | | 722 | eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); |
723 | usb_schedsoftintr(&sc->sc_bus); | | 723 | usb_schedsoftintr(&sc->sc_bus); |
724 | eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); | | 724 | eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); |
725 | } | | 725 | } |
726 | if (eintrs & EHCI_STS_HSE) { | | 726 | if (eintrs & EHCI_STS_HSE) { |
727 | printf("%s: unrecoverable error, controller halted\n", | | 727 | printf("%s: unrecoverable error, controller halted\n", |
728 | device_xname(sc->sc_dev)); | | 728 | device_xname(sc->sc_dev)); |
729 | /* XXX what else */ | | 729 | /* XXX what else */ |
730 | } | | 730 | } |
731 | if (eintrs & EHCI_STS_PCD) { | | 731 | if (eintrs & EHCI_STS_PCD) { |
732 | kpreempt_disable(); | | 732 | kpreempt_disable(); |
733 | KASSERT(sc->sc_pcd_si != NULL); | | 733 | KASSERT(sc->sc_pcd_si != NULL); |
734 | softint_schedule(sc->sc_pcd_si); | | 734 | softint_schedule(sc->sc_pcd_si); |
735 | kpreempt_enable(); | | 735 | kpreempt_enable(); |
736 | eintrs &= ~EHCI_STS_PCD; | | 736 | eintrs &= ~EHCI_STS_PCD; |
737 | } | | 737 | } |
738 | | | 738 | |
739 | if (eintrs != 0) { | | 739 | if (eintrs != 0) { |
740 | /* Block unprocessed interrupts. */ | | 740 | /* Block unprocessed interrupts. */ |
741 | sc->sc_eintrs &= ~eintrs; | | 741 | sc->sc_eintrs &= ~eintrs; |
742 | EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); | | 742 | EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); |
743 | printf("%s: blocking intrs 0x%x\n", | | 743 | printf("%s: blocking intrs 0x%x\n", |
744 | device_xname(sc->sc_dev), eintrs); | | 744 | device_xname(sc->sc_dev), eintrs); |
745 | } | | 745 | } |
746 | | | 746 | |
747 | return 1; | | 747 | return 1; |
748 | } | | 748 | } |
749 | | | 749 | |
750 | Static void | | 750 | Static void |
751 | ehci_doorbell(void *addr) | | 751 | ehci_doorbell(void *addr) |
752 | { | | 752 | { |
753 | ehci_softc_t *sc = addr; | | 753 | ehci_softc_t *sc = addr; |
754 | | | 754 | |
755 | mutex_enter(&sc->sc_lock); | | 755 | mutex_enter(&sc->sc_lock); |
756 | cv_broadcast(&sc->sc_doorbell); | | 756 | cv_broadcast(&sc->sc_doorbell); |
757 | mutex_exit(&sc->sc_lock); | | 757 | mutex_exit(&sc->sc_lock); |
758 | } | | 758 | } |
759 | | | 759 | |
760 | Static void | | 760 | Static void |
761 | ehci_pcd(void *addr) | | 761 | ehci_pcd(void *addr) |
762 | { | | 762 | { |
763 | ehci_softc_t *sc = addr; | | 763 | ehci_softc_t *sc = addr; |
764 | struct usbd_xfer *xfer; | | 764 | struct usbd_xfer *xfer; |
765 | u_char *p; | | 765 | u_char *p; |
766 | int i, m; | | 766 | int i, m; |
767 | | | 767 | |
768 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 768 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
769 | | | 769 | |
770 | mutex_enter(&sc->sc_lock); | | 770 | mutex_enter(&sc->sc_lock); |
771 | xfer = sc->sc_intrxfer; | | 771 | xfer = sc->sc_intrxfer; |
772 | | | 772 | |
773 | if (xfer == NULL) { | | 773 | if (xfer == NULL) { |
774 | /* Just ignore the change. */ | | 774 | /* Just ignore the change. */ |
775 | goto done; | | 775 | goto done; |
776 | } | | 776 | } |
777 | | | 777 | |
778 | p = xfer->ux_buf; | | 778 | p = xfer->ux_buf; |
779 | m = min(sc->sc_noport, xfer->ux_length * 8 - 1); | | 779 | m = min(sc->sc_noport, xfer->ux_length * 8 - 1); |
780 | memset(p, 0, xfer->ux_length); | | 780 | memset(p, 0, xfer->ux_length); |
781 | for (i = 1; i <= m; i++) { | | 781 | for (i = 1; i <= m; i++) { |
782 | /* Pick out CHANGE bits from the status reg. */ | | 782 | /* Pick out CHANGE bits from the status reg. */ |
783 | if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) | | 783 | if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) |
784 | p[i/8] |= 1 << (i%8); | | 784 | p[i/8] |= 1 << (i%8); |
785 | if (i % 8 == 7) | | 785 | if (i % 8 == 7) |
786 | DPRINTF("change(%d)=0x%02x", i / 8, p[i/8], 0, 0); | | 786 | DPRINTF("change(%d)=0x%02x", i / 8, p[i/8], 0, 0); |
787 | } | | 787 | } |
788 | xfer->ux_actlen = xfer->ux_length; | | 788 | xfer->ux_actlen = xfer->ux_length; |
789 | xfer->ux_status = USBD_NORMAL_COMPLETION; | | 789 | xfer->ux_status = USBD_NORMAL_COMPLETION; |
790 | | | 790 | |
791 | usb_transfer_complete(xfer); | | 791 | usb_transfer_complete(xfer); |
792 | | | 792 | |
793 | done: | | 793 | done: |
794 | mutex_exit(&sc->sc_lock); | | 794 | mutex_exit(&sc->sc_lock); |
795 | } | | 795 | } |
796 | | | 796 | |
797 | Static void | | 797 | Static void |
798 | ehci_softintr(void *v) | | 798 | ehci_softintr(void *v) |
799 | { | | 799 | { |
800 | struct usbd_bus *bus = v; | | 800 | struct usbd_bus *bus = v; |
801 | ehci_softc_t *sc = EHCI_BUS2SC(bus); | | 801 | ehci_softc_t *sc = EHCI_BUS2SC(bus); |
802 | struct ehci_xfer *ex, *nextex; | | 802 | struct ehci_xfer *ex, *nextex; |
803 | | | 803 | |
804 | KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); | | 804 | KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); |
805 | | | 805 | |
806 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 806 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
807 | | | 807 | |
808 | ex_completeq_t cq; | | 808 | ex_completeq_t cq; |
809 | TAILQ_INIT(&cq); | | 809 | TAILQ_INIT(&cq); |
810 | | | 810 | |
811 | /* | | 811 | /* |
812 | * The only explanation I can think of for why EHCI is as brain dead | | 812 | * The only explanation I can think of for why EHCI is as brain dead |
813 | * as UHCI interrupt-wise is that Intel was involved in both. | | 813 | * as UHCI interrupt-wise is that Intel was involved in both. |
814 | * An interrupt just tells us that something is done, we have no | | 814 | * An interrupt just tells us that something is done, we have no |
815 | * clue what, so we need to scan through all active transfers. :-( | | 815 | * clue what, so we need to scan through all active transfers. :-( |
816 | */ | | 816 | */ |
817 | | | 817 | |
818 | /* | | 818 | /* |
819 | * ehci_idone will remove transfer from sc->sc_intrhead if it's | | 819 | * ehci_idone will remove transfer from sc->sc_intrhead if it's |
820 | * complete and add to our cq list | | 820 | * complete and add to our cq list |
821 | * | | 821 | * |
822 | */ | | 822 | */ |
823 | TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { | | 823 | TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { |
824 | switch (ex->ex_type) { | | 824 | switch (ex->ex_type) { |
825 | case EX_CTRL: | | 825 | case EX_CTRL: |
826 | case EX_BULK: | | 826 | case EX_BULK: |
827 | case EX_INTR: | | 827 | case EX_INTR: |
828 | ehci_check_qh_intr(sc, ex, &cq); | | 828 | ehci_check_qh_intr(sc, ex, &cq); |
829 | break; | | 829 | break; |
830 | case EX_ISOC: | | 830 | case EX_ISOC: |
831 | ehci_check_itd_intr(sc, ex, &cq); | | 831 | ehci_check_itd_intr(sc, ex, &cq); |
832 | break; | | 832 | break; |
833 | case EX_FS_ISOC: | | 833 | case EX_FS_ISOC: |
834 | ehci_check_sitd_intr(sc, ex, &cq); | | 834 | ehci_check_sitd_intr(sc, ex, &cq); |
835 | break; | | 835 | break; |
836 | default: | | 836 | default: |
837 | KASSERT(false); | | 837 | KASSERT(false); |
838 | } | | 838 | } |
839 | | | 839 | |
840 | } | | 840 | } |
841 | | | 841 | |
842 | /* | | 842 | /* |
843 | * We abuse ex_next for the interrupt and complete lists and | | 843 | * We abuse ex_next for the interrupt and complete lists and |
844 | * interrupt transfers will get re-added here so use | | 844 | * interrupt transfers will get re-added here so use |
845 | * the _SAFE version of TAILQ_FOREACH. | | 845 | * the _SAFE version of TAILQ_FOREACH. |
846 | */ | | 846 | */ |
847 | TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { | | 847 | TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { |
848 | usb_transfer_complete(&ex->ex_xfer); | | 848 | usb_transfer_complete(&ex->ex_xfer); |
849 | } | | 849 | } |
850 | | | 850 | |
851 | /* Schedule a callout to catch any dropped transactions. */ | | 851 | /* Schedule a callout to catch any dropped transactions. */ |
852 | if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && | | 852 | if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && |
853 | !TAILQ_EMPTY(&sc->sc_intrhead)) | | 853 | !TAILQ_EMPTY(&sc->sc_intrhead)) |
854 | callout_reset(&sc->sc_tmo_intrlist, | | 854 | callout_reset(&sc->sc_tmo_intrlist, |
855 | hz, ehci_intrlist_timeout, sc); | | 855 | hz, ehci_intrlist_timeout, sc); |
856 | | | 856 | |
857 | if (sc->sc_softwake) { | | 857 | if (sc->sc_softwake) { |
858 | sc->sc_softwake = 0; | | 858 | sc->sc_softwake = 0; |
859 | cv_broadcast(&sc->sc_softwake_cv); | | 859 | cv_broadcast(&sc->sc_softwake_cv); |
860 | } | | 860 | } |
861 | } | | 861 | } |
862 | | | 862 | |
863 | Static void | | 863 | Static void |
864 | ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) | | 864 | ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) |
865 | { | | 865 | { |
866 | ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; | | 866 | ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; |
867 | uint32_t status; | | 867 | uint32_t status; |
868 | | | 868 | |
869 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 869 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
870 | | | 870 | |
871 | KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); | | 871 | KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); |
872 | | | 872 | |
873 | if (ex->ex_type == EX_CTRL) { | | 873 | if (ex->ex_type == EX_CTRL) { |
874 | fsqtd = ex->ex_setup; | | 874 | fsqtd = ex->ex_setup; |
875 | lsqtd = ex->ex_status; | | 875 | lsqtd = ex->ex_status; |
876 | } else { | | 876 | } else { |
877 | fsqtd = ex->ex_sqtdstart; | | 877 | fsqtd = ex->ex_sqtdstart; |
878 | lsqtd = ex->ex_sqtdend; | | 878 | lsqtd = ex->ex_sqtdend; |
879 | } | | 879 | } |
880 | KASSERTMSG(fsqtd != NULL && lsqtd != NULL, | | 880 | KASSERTMSG(fsqtd != NULL && lsqtd != NULL, |
881 | "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); | | 881 | "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); |
882 | | | 882 | |
883 | /* | | 883 | /* |
884 | * If the last TD is still active we need to check whether there | | 884 | * If the last TD is still active we need to check whether there |
885 | * is an error somewhere in the middle, or whether there was a | | 885 | * is an error somewhere in the middle, or whether there was a |
886 | * short packet (SPD and not ACTIVE). | | 886 | * short packet (SPD and not ACTIVE). |
887 | */ | | 887 | */ |
888 | usb_syncmem(&lsqtd->dma, | | 888 | usb_syncmem(&lsqtd->dma, |
889 | lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), | | 889 | lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), |
890 | sizeof(lsqtd->qtd.qtd_status), | | 890 | sizeof(lsqtd->qtd.qtd_status), |
891 | BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); | | 891 | BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); |
892 | status = le32toh(lsqtd->qtd.qtd_status); | | 892 | status = le32toh(lsqtd->qtd.qtd_status); |
893 | usb_syncmem(&lsqtd->dma, | | 893 | usb_syncmem(&lsqtd->dma, |
894 | lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), | | 894 | lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), |
895 | sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); | | 895 | sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); |
896 | if (status & EHCI_QTD_ACTIVE) { | | 896 | if (status & EHCI_QTD_ACTIVE) { |
897 | DPRINTFN(10, "active ex=%p", ex, 0, 0, 0); | | 897 | DPRINTFN(10, "active ex=%p", ex, 0, 0, 0); |
898 | | | 898 | |
899 | /* last qTD has already been checked */ | | 899 | /* last qTD has already been checked */ |
900 | for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { | | 900 | for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { |
901 | usb_syncmem(&sqtd->dma, | | 901 | usb_syncmem(&sqtd->dma, |
902 | sqtd->offs + offsetof(ehci_qtd_t, qtd_status), | | 902 | sqtd->offs + offsetof(ehci_qtd_t, qtd_status), |
903 | sizeof(sqtd->qtd.qtd_status), | | 903 | sizeof(sqtd->qtd.qtd_status), |
904 | BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); | | 904 | BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); |
905 | status = le32toh(sqtd->qtd.qtd_status); | | 905 | status = le32toh(sqtd->qtd.qtd_status); |
906 | usb_syncmem(&sqtd->dma, | | 906 | usb_syncmem(&sqtd->dma, |
907 | sqtd->offs + offsetof(ehci_qtd_t, qtd_status), | | 907 | sqtd->offs + offsetof(ehci_qtd_t, qtd_status), |
908 | sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); | | 908 | sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); |
909 | /* If there's an active QTD the xfer isn't done. */ | | 909 | /* If there's an active QTD the xfer isn't done. */ |
910 | if (status & EHCI_QTD_ACTIVE) | | 910 | if (status & EHCI_QTD_ACTIVE) |
911 | break; | | 911 | break; |
912 | /* Any kind of error makes the xfer done. */ | | 912 | /* Any kind of error makes the xfer done. */ |
913 | if (status & EHCI_QTD_HALTED) | | 913 | if (status & EHCI_QTD_HALTED) |
914 | goto done; | | 914 | goto done; |
915 | /* Handle short packets */ | | 915 | /* Handle short packets */ |
916 | if (EHCI_QTD_GET_BYTES(status) != 0) { | | 916 | if (EHCI_QTD_GET_BYTES(status) != 0) { |
917 | /* | | 917 | /* |
918 | * If we get here for a control transfer then | | 918 | * If we get here for a control transfer then |
919 | * we need to let the hardware complete the | | 919 | * we need to let the hardware complete the |
920 | * status phase. That is, we're not done | | 920 | * status phase. That is, we're not done |
921 | * quite yet. | | 921 | * quite yet. |
922 | * | | 922 | * |
923 | * Otherwise, we're done. | | 923 | * Otherwise, we're done. |
924 | */ | | 924 | */ |
925 | if (ex->ex_type == EX_CTRL) { | | 925 | if (ex->ex_type == EX_CTRL) { |
926 | break; | | 926 | break; |
927 | } | | 927 | } |
928 | goto done; | | 928 | goto done; |
929 | } | | 929 | } |
930 | } | | 930 | } |
931 | DPRINTFN(10, "ex=%p std=%p still active", ex, ex->ex_sqtdstart, | | 931 | DPRINTFN(10, "ex=%p std=%p still active", ex, ex->ex_sqtdstart, |
932 | 0, 0); | | 932 | 0, 0); |
933 | #ifdef EHCI_DEBUG | | 933 | #ifdef EHCI_DEBUG |
934 | DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0); | | 934 | DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0); |
935 | ehci_dump_sqtds(ex->ex_sqtdstart); | | 935 | ehci_dump_sqtds(ex->ex_sqtdstart); |
936 | DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0); | | 936 | DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0); |
937 | #endif | | 937 | #endif |
938 | return; | | 938 | return; |
939 | } | | 939 | } |
940 | done: | | 940 | done: |
941 | DPRINTFN(10, "ex=%p done", ex, 0, 0, 0); | | 941 | DPRINTFN(10, "ex=%p done", ex, 0, 0, 0); |
942 | callout_stop(&ex->ex_xfer.ux_callout); | | 942 | callout_stop(&ex->ex_xfer.ux_callout); |
943 | ehci_idone(ex, cq); | | 943 | ehci_idone(ex, cq); |
944 | } | | 944 | } |
945 | | | 945 | |
946 | Static void | | 946 | Static void |
947 | ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) | | 947 | ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) |
948 | { | | 948 | { |
949 | ehci_soft_itd_t *itd; | | 949 | ehci_soft_itd_t *itd; |
950 | int i; | | 950 | int i; |
951 | | | 951 | |
952 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 952 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
953 | | | 953 | |
954 | KASSERT(mutex_owned(&sc->sc_lock)); | | 954 | KASSERT(mutex_owned(&sc->sc_lock)); |
955 | | | 955 | |
956 | if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) | | 956 | if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) |
957 | return; | | 957 | return; |
958 | | | 958 | |
959 | KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, | | 959 | KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, |
960 | "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); | | 960 | "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); |
961 | | | 961 | |
962 | itd = ex->ex_itdend; | | 962 | itd = ex->ex_itdend; |
963 | | | 963 | |
964 | /* | | 964 | /* |
965 | * check no active transfers in last itd, meaning we're finished | | 965 | * check no active transfers in last itd, meaning we're finished |
966 | */ | | 966 | */ |
967 | | | 967 | |
968 | usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), | | 968 | usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), |
969 | sizeof(itd->itd.itd_ctl), | | 969 | sizeof(itd->itd.itd_ctl), |
970 | BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); | | 970 | BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); |
971 | | | 971 | |
972 | for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { | | 972 | for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { |
973 | if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) | | 973 | if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) |
974 | break; | | 974 | break; |
975 | } | | 975 | } |
976 | | | 976 | |
977 | if (i == EHCI_ITD_NUFRAMES) { | | 977 | if (i == EHCI_ITD_NUFRAMES) { |
978 | goto done; /* All 8 descriptors inactive, it's done */ | | 978 | goto done; /* All 8 descriptors inactive, it's done */ |
979 | } | | 979 | } |
980 | | | 980 | |
981 | usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), | | 981 | usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), |
982 | sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); | | 982 | sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); |
983 | | | 983 | |
984 | DPRINTFN(10, "ex %p itd %p still active", ex, ex->ex_itdstart, 0, 0); | | 984 | DPRINTFN(10, "ex %p itd %p still active", ex, ex->ex_itdstart, 0, 0); |
985 | return; | | 985 | return; |
986 | done: | | 986 | done: |
987 | DPRINTF("ex %p done", ex, 0, 0, 0); | | 987 | DPRINTF("ex %p done", ex, 0, 0, 0); |
988 | callout_stop(&ex->ex_xfer.ux_callout); | | 988 | callout_stop(&ex->ex_xfer.ux_callout); |
989 | ehci_idone(ex, cq); | | 989 | ehci_idone(ex, cq); |
990 | } | | 990 | } |
991 | | | 991 | |
992 | void | | 992 | void |
993 | ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) | | 993 | ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) |
994 | { | | 994 | { |
995 | ehci_soft_sitd_t *sitd; | | 995 | ehci_soft_sitd_t *sitd; |
996 | | | 996 | |
997 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 997 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
998 | | | 998 | |
999 | KASSERT(mutex_owned(&sc->sc_lock)); | | 999 | KASSERT(mutex_owned(&sc->sc_lock)); |
1000 | | | 1000 | |
1001 | if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) | | 1001 | if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) |
1002 | return; | | 1002 | return; |
1003 | | | 1003 | |
1004 | KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, | | 1004 | KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, |
1005 | "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); | | 1005 | "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); |
1006 | | | 1006 | |
1007 | sitd = ex->ex_sitdend; | | 1007 | sitd = ex->ex_sitdend; |
1008 | | | 1008 | |
1009 | /* | | 1009 | /* |
1010 | * check no active transfers in last sitd, meaning we're finished | | 1010 | * check no active transfers in last sitd, meaning we're finished |
1011 | */ | | 1011 | */ |
1012 | | | 1012 | |
1013 | usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), | | 1013 | usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), |
1014 | sizeof(sitd->sitd.sitd_trans), | | 1014 | sizeof(sitd->sitd.sitd_trans), |
1015 | BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); | | 1015 | BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); |
1016 | | | 1016 | |
1017 | bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); | | 1017 | bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); |
1018 | | | 1018 | |
1019 | usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), | | 1019 | usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), |
1020 | sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); | | 1020 | sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); |
1021 | | | 1021 | |
1022 | if (active) | | 1022 | if (active) |
1023 | return; | | 1023 | return; |
1024 | | | 1024 | |
1025 | DPRINTFN(10, "ex=%p done", ex, 0, 0, 0); | | 1025 | DPRINTFN(10, "ex=%p done", ex, 0, 0, 0); |
1026 | callout_stop(&(ex->ex_xfer.ux_callout)); | | 1026 | callout_stop(&(ex->ex_xfer.ux_callout)); |
1027 | ehci_idone(ex, cq); | | 1027 | ehci_idone(ex, cq); |
1028 | } | | 1028 | } |
1029 | | | 1029 | |
1030 | | | 1030 | |
1031 | Static void | | 1031 | Static void |
1032 | ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) | | 1032 | ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) |
1033 | { | | 1033 | { |
1034 | struct usbd_xfer *xfer = &ex->ex_xfer; | | 1034 | struct usbd_xfer *xfer = &ex->ex_xfer; |
1035 | struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); | | 1035 | struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); |
1036 | struct ehci_softc *sc = EHCI_XFER2SC(xfer); | | 1036 | struct ehci_softc *sc = EHCI_XFER2SC(xfer); |
1037 | ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; | | 1037 | ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; |
1038 | uint32_t status = 0, nstatus = 0; | | 1038 | uint32_t status = 0, nstatus = 0; |
1039 | int actlen = 0; | | 1039 | int actlen = 0; |
1040 | | | 1040 | |
1041 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 1041 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
1042 | | | 1042 | |
1043 | KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); | | 1043 | KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); |
1044 | | | 1044 | |
1045 | DPRINTF("ex=%p", ex, 0, 0, 0); | | 1045 | DPRINTF("ex=%p", ex, 0, 0, 0); |
1046 | | | 1046 | |
1047 | if (xfer->ux_status == USBD_CANCELLED || | | 1047 | if (xfer->ux_status == USBD_CANCELLED || |
1048 | xfer->ux_status == USBD_TIMEOUT) { | | 1048 | xfer->ux_status == USBD_TIMEOUT) { |
1049 | DPRINTF("aborted xfer=%p", xfer, 0, 0, 0); | | 1049 | DPRINTF("aborted xfer=%p", xfer, 0, 0, 0); |
1050 | return; | | 1050 | return; |
1051 | } | | 1051 | } |
1052 | | | 1052 | |
1053 | #ifdef DIAGNOSTIC | | 1053 | #ifdef DIAGNOSTIC |
1054 | #ifdef EHCI_DEBUG | | 1054 | #ifdef EHCI_DEBUG |
1055 | if (ex->ex_isdone) { | | 1055 | if (ex->ex_isdone) { |
| @@ -1172,2000 +1172,2003 @@ ehci_idone(struct ehci_xfer *ex, ex_comp | | | @@ -1172,2000 +1172,2003 @@ ehci_idone(struct ehci_xfer *ex, ex_comp |
1172 | goto end; | | 1172 | goto end; |
1173 | } | | 1173 | } |
1174 | KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || | | 1174 | KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || |
1175 | ex->ex_type == EX_BULK); | | 1175 | ex->ex_type == EX_BULK); |
1176 | | | 1176 | |
1177 | /* Continue processing xfers using queue heads */ | | 1177 | /* Continue processing xfers using queue heads */ |
1178 | if (ex->ex_type == EX_CTRL) { | | 1178 | if (ex->ex_type == EX_CTRL) { |
1179 | fsqtd = ex->ex_setup; | | 1179 | fsqtd = ex->ex_setup; |
1180 | lsqtd = ex->ex_status; | | 1180 | lsqtd = ex->ex_status; |
1181 | } else { | | 1181 | } else { |
1182 | fsqtd = ex->ex_sqtdstart; | | 1182 | fsqtd = ex->ex_sqtdstart; |
1183 | lsqtd = ex->ex_sqtdend; | | 1183 | lsqtd = ex->ex_sqtdend; |
1184 | } | | 1184 | } |
1185 | #ifdef EHCI_DEBUG | | 1185 | #ifdef EHCI_DEBUG |
1186 | DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); | | 1186 | DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); |
1187 | ehci_dump_sqtds(fsqtd); | | 1187 | ehci_dump_sqtds(fsqtd); |
1188 | DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); | | 1188 | DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); |
1189 | #endif | | 1189 | #endif |
1190 | | | 1190 | |
1191 | for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { | | 1191 | for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { |
1192 | usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), | | 1192 | usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), |
1193 | BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); | | 1193 | BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); |
1194 | nstatus = le32toh(sqtd->qtd.qtd_status); | | 1194 | nstatus = le32toh(sqtd->qtd.qtd_status); |
1195 | usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), | | 1195 | usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), |
1196 | BUS_DMASYNC_PREREAD); | | 1196 | BUS_DMASYNC_PREREAD); |
1197 | if (nstatus & EHCI_QTD_ACTIVE) | | 1197 | if (nstatus & EHCI_QTD_ACTIVE) |
1198 | break; | | 1198 | break; |
1199 | | | 1199 | |
1200 | status = nstatus; | | 1200 | status = nstatus; |
1201 | if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) | | 1201 | if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) |
1202 | actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); | | 1202 | actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); |
1203 | } | | 1203 | } |
1204 | | | 1204 | |
1205 | /* | | 1205 | /* |
1206 | * If there are left over TDs we need to update the toggle. | | 1206 | * If there are left over TDs we need to update the toggle. |
1207 | * The default pipe doesn't need it since control transfers | | 1207 | * The default pipe doesn't need it since control transfers |
1208 | * start the toggle at 0 every time. | | 1208 | * start the toggle at 0 every time. |
1209 | * For a short transfer we need to update the toggle for the missing | | 1209 | * For a short transfer we need to update the toggle for the missing |
1210 | * packets within the qTD. | | 1210 | * packets within the qTD. |
1211 | */ | | 1211 | */ |
1212 | if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && | | 1212 | if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && |
1213 | xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { | | 1213 | xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { |
1214 | DPRINTF("toggle update status=0x%08x nstatus=0x%08x", | | 1214 | DPRINTF("toggle update status=0x%08x nstatus=0x%08x", |
1215 | status, nstatus, 0, 0); | | 1215 | status, nstatus, 0, 0); |
1216 | #if 0 | | 1216 | #if 0 |
1217 | ehci_dump_sqh(epipe->sqh); | | 1217 | ehci_dump_sqh(epipe->sqh); |
1218 | ehci_dump_sqtds(ex->ex_sqtdstart); | | 1218 | ehci_dump_sqtds(ex->ex_sqtdstart); |
1219 | #endif | | 1219 | #endif |
1220 | epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); | | 1220 | epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); |
1221 | } | | 1221 | } |
1222 | | | 1222 | |
1223 | DPRINTF("len=%d actlen=%d status=0x%08x", xfer->ux_length, actlen, | | 1223 | DPRINTF("len=%d actlen=%d status=0x%08x", xfer->ux_length, actlen, |
1224 | status, 0); | | 1224 | status, 0); |
1225 | xfer->ux_actlen = actlen; | | 1225 | xfer->ux_actlen = actlen; |
1226 | if (status & EHCI_QTD_HALTED) { | | 1226 | if (status & EHCI_QTD_HALTED) { |
1227 | #ifdef EHCI_DEBUG | | 1227 | #ifdef EHCI_DEBUG |
1228 | DPRINTF("halted addr=%d endpt=0x%02x", | | 1228 | DPRINTF("halted addr=%d endpt=0x%02x", |
1229 | xfer->ux_pipe->up_dev->ud_addr, | | 1229 | xfer->ux_pipe->up_dev->ud_addr, |
1230 | xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, | | 1230 | xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, |
1231 | 0, 0); | | 1231 | 0, 0); |
1232 | DPRINTF("cerr=%d pid=%d", | | 1232 | DPRINTF("cerr=%d pid=%d", |
1233 | EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), | | 1233 | EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), |
1234 | 0, 0); | | 1234 | 0, 0); |
1235 | DPRINTF("active =%d halted=%d buferr=%d babble=%d", | | 1235 | DPRINTF("active =%d halted=%d buferr=%d babble=%d", |
1236 | status & EHCI_QTD_ACTIVE ? 1 : 0, | | 1236 | status & EHCI_QTD_ACTIVE ? 1 : 0, |
1237 | status & EHCI_QTD_HALTED ? 1 : 0, | | 1237 | status & EHCI_QTD_HALTED ? 1 : 0, |
1238 | status & EHCI_QTD_BUFERR ? 1 : 0, | | 1238 | status & EHCI_QTD_BUFERR ? 1 : 0, |
1239 | status & EHCI_QTD_BABBLE ? 1 : 0); | | 1239 | status & EHCI_QTD_BABBLE ? 1 : 0); |
1240 | | | 1240 | |
1241 | DPRINTF("xacterr=%d missed=%d split =%d ping =%d", | | 1241 | DPRINTF("xacterr=%d missed=%d split =%d ping =%d", |
1242 | status & EHCI_QTD_XACTERR ? 1 : 0, | | 1242 | status & EHCI_QTD_XACTERR ? 1 : 0, |
1243 | status & EHCI_QTD_MISSEDMICRO ? 1 : 0, | | 1243 | status & EHCI_QTD_MISSEDMICRO ? 1 : 0, |
1244 | status & EHCI_QTD_SPLITXSTATE ? 1 : 0, | | 1244 | status & EHCI_QTD_SPLITXSTATE ? 1 : 0, |
1245 | status & EHCI_QTD_PINGSTATE ? 1 : 0); | | 1245 | status & EHCI_QTD_PINGSTATE ? 1 : 0); |
1246 | | | 1246 | |
1247 | DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); | | 1247 | DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); |
1248 | ehci_dump_sqh(epipe->sqh); | | 1248 | ehci_dump_sqh(epipe->sqh); |
1249 | ehci_dump_sqtds(ex->ex_sqtdstart); | | 1249 | ehci_dump_sqtds(ex->ex_sqtdstart); |
1250 | DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); | | 1250 | DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); |
1251 | #endif | | 1251 | #endif |
1252 | /* low&full speed has an extra error flag */ | | 1252 | /* low&full speed has an extra error flag */ |
1253 | if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != | | 1253 | if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != |
1254 | EHCI_QH_SPEED_HIGH) | | 1254 | EHCI_QH_SPEED_HIGH) |
1255 | status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; | | 1255 | status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; |
1256 | else | | 1256 | else |
1257 | status &= EHCI_QTD_STATERRS; | | 1257 | status &= EHCI_QTD_STATERRS; |
1258 | if (status == 0) /* no other errors means a stall */ { | | 1258 | if (status == 0) /* no other errors means a stall */ { |
1259 | xfer->ux_status = USBD_STALLED; | | 1259 | xfer->ux_status = USBD_STALLED; |
1260 | } else { | | 1260 | } else { |
1261 | xfer->ux_status = USBD_IOERROR; /* more info XXX */ | | 1261 | xfer->ux_status = USBD_IOERROR; /* more info XXX */ |
1262 | } | | 1262 | } |
1263 | /* XXX need to reset TT on missed microframe */ | | 1263 | /* XXX need to reset TT on missed microframe */ |
1264 | if (status & EHCI_QTD_MISSEDMICRO) { | | 1264 | if (status & EHCI_QTD_MISSEDMICRO) { |
1265 | printf("%s: missed microframe, TT reset not " | | 1265 | printf("%s: missed microframe, TT reset not " |
1266 | "implemented, hub might be inoperational\n", | | 1266 | "implemented, hub might be inoperational\n", |
1267 | device_xname(sc->sc_dev)); | | 1267 | device_xname(sc->sc_dev)); |
1268 | } | | 1268 | } |
1269 | } else { | | 1269 | } else { |
1270 | xfer->ux_status = USBD_NORMAL_COMPLETION; | | 1270 | xfer->ux_status = USBD_NORMAL_COMPLETION; |
1271 | } | | 1271 | } |
1272 | | | 1272 | |
1273 | end: | | 1273 | end: |
1274 | | | 1274 | |
1275 | ehci_del_intr_list(sc, ex); | | 1275 | ehci_del_intr_list(sc, ex); |
1276 | TAILQ_INSERT_TAIL(cq, ex, ex_next); | | 1276 | TAILQ_INSERT_TAIL(cq, ex, ex_next); |
1277 | | | 1277 | |
1278 | DPRINTF("ex=%p done", ex, 0, 0, 0); | | 1278 | DPRINTF("ex=%p done", ex, 0, 0, 0); |
1279 | } | | 1279 | } |
1280 | | | 1280 | |
1281 | Static void | | 1281 | Static void |
1282 | ehci_poll(struct usbd_bus *bus) | | 1282 | ehci_poll(struct usbd_bus *bus) |
1283 | { | | 1283 | { |
1284 | ehci_softc_t *sc = EHCI_BUS2SC(bus); | | 1284 | ehci_softc_t *sc = EHCI_BUS2SC(bus); |
1285 | | | 1285 | |
1286 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 1286 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
1287 | | | 1287 | |
1288 | #ifdef EHCI_DEBUG | | 1288 | #ifdef EHCI_DEBUG |
1289 | static int last; | | 1289 | static int last; |
1290 | int new; | | 1290 | int new; |
1291 | new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); | | 1291 | new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); |
1292 | if (new != last) { | | 1292 | if (new != last) { |
1293 | DPRINTF("intrs=0x%04x", new, 0, 0, 0); | | 1293 | DPRINTF("intrs=0x%04x", new, 0, 0, 0); |
1294 | last = new; | | 1294 | last = new; |
1295 | } | | 1295 | } |
1296 | #endif | | 1296 | #endif |
1297 | | | 1297 | |
1298 | if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { | | 1298 | if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { |
1299 | mutex_spin_enter(&sc->sc_intr_lock); | | 1299 | mutex_spin_enter(&sc->sc_intr_lock); |
1300 | ehci_intr1(sc); | | 1300 | ehci_intr1(sc); |
1301 | mutex_spin_exit(&sc->sc_intr_lock); | | 1301 | mutex_spin_exit(&sc->sc_intr_lock); |
1302 | } | | 1302 | } |
1303 | } | | 1303 | } |
1304 | | | 1304 | |
1305 | void | | 1305 | void |
1306 | ehci_childdet(device_t self, device_t child) | | 1306 | ehci_childdet(device_t self, device_t child) |
1307 | { | | 1307 | { |
1308 | struct ehci_softc *sc = device_private(self); | | 1308 | struct ehci_softc *sc = device_private(self); |
1309 | | | 1309 | |
1310 | KASSERT(sc->sc_child == child); | | 1310 | KASSERT(sc->sc_child == child); |
1311 | sc->sc_child = NULL; | | 1311 | sc->sc_child = NULL; |
1312 | } | | 1312 | } |
1313 | | | 1313 | |
1314 | int | | 1314 | int |
1315 | ehci_detach(struct ehci_softc *sc, int flags) | | 1315 | ehci_detach(struct ehci_softc *sc, int flags) |
1316 | { | | 1316 | { |
1317 | int rv = 0; | | 1317 | int rv = 0; |
1318 | | | 1318 | |
1319 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 1319 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
1320 | | | 1320 | |
1321 | if (sc->sc_child != NULL) | | 1321 | if (sc->sc_child != NULL) |
1322 | rv = config_detach(sc->sc_child, flags); | | 1322 | rv = config_detach(sc->sc_child, flags); |
1323 | | | 1323 | |
1324 | if (rv != 0) | | 1324 | if (rv != 0) |
1325 | return rv; | | 1325 | return rv; |
1326 | | | 1326 | |
1327 | callout_halt(&sc->sc_tmo_intrlist, NULL); | | 1327 | callout_halt(&sc->sc_tmo_intrlist, NULL); |
1328 | callout_destroy(&sc->sc_tmo_intrlist); | | 1328 | callout_destroy(&sc->sc_tmo_intrlist); |
1329 | | | 1329 | |
1330 | /* XXX free other data structures XXX */ | | 1330 | /* XXX free other data structures XXX */ |
1331 | if (sc->sc_softitds) | | 1331 | if (sc->sc_softitds) |
1332 | kmem_free(sc->sc_softitds, | | 1332 | kmem_free(sc->sc_softitds, |
1333 | sc->sc_flsize * sizeof(ehci_soft_itd_t *)); | | 1333 | sc->sc_flsize * sizeof(ehci_soft_itd_t *)); |
1334 | cv_destroy(&sc->sc_doorbell); | | 1334 | cv_destroy(&sc->sc_doorbell); |
1335 | cv_destroy(&sc->sc_softwake_cv); | | 1335 | cv_destroy(&sc->sc_softwake_cv); |
1336 | | | 1336 | |
1337 | #if 0 | | 1337 | #if 0 |
1338 | /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ | | 1338 | /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ |
1339 | | | 1339 | |
1340 | softint_disestablish(sc->sc_doorbell_si); | | 1340 | softint_disestablish(sc->sc_doorbell_si); |
1341 | softint_disestablish(sc->sc_pcd_si); | | 1341 | softint_disestablish(sc->sc_pcd_si); |
1342 | | | 1342 | |
1343 | mutex_destroy(&sc->sc_lock); | | 1343 | mutex_destroy(&sc->sc_lock); |
1344 | mutex_destroy(&sc->sc_intr_lock); | | 1344 | mutex_destroy(&sc->sc_intr_lock); |
1345 | #endif | | 1345 | #endif |
1346 | | | 1346 | |
1347 | pool_cache_destroy(sc->sc_xferpool); | | 1347 | pool_cache_destroy(sc->sc_xferpool); |
1348 | | | 1348 | |
1349 | EOWRITE4(sc, EHCI_CONFIGFLAG, 0); | | 1349 | EOWRITE4(sc, EHCI_CONFIGFLAG, 0); |
1350 | | | 1350 | |
1351 | return rv; | | 1351 | return rv; |
1352 | } | | 1352 | } |
1353 | | | 1353 | |
1354 | | | 1354 | |
1355 | int | | 1355 | int |
1356 | ehci_activate(device_t self, enum devact act) | | 1356 | ehci_activate(device_t self, enum devact act) |
1357 | { | | 1357 | { |
1358 | struct ehci_softc *sc = device_private(self); | | 1358 | struct ehci_softc *sc = device_private(self); |
1359 | | | 1359 | |
1360 | switch (act) { | | 1360 | switch (act) { |
1361 | case DVACT_DEACTIVATE: | | 1361 | case DVACT_DEACTIVATE: |
1362 | sc->sc_dying = 1; | | 1362 | sc->sc_dying = 1; |
1363 | return 0; | | 1363 | return 0; |
1364 | default: | | 1364 | default: |
1365 | return EOPNOTSUPP; | | 1365 | return EOPNOTSUPP; |
1366 | } | | 1366 | } |
1367 | } | | 1367 | } |
1368 | | | 1368 | |
1369 | /* | | 1369 | /* |
1370 | * Handle suspend/resume. | | 1370 | * Handle suspend/resume. |
1371 | * | | 1371 | * |
1372 | * We need to switch to polling mode here, because this routine is | | 1372 | * We need to switch to polling mode here, because this routine is |
1373 | * called from an interrupt context. This is all right since we | | 1373 | * called from an interrupt context. This is all right since we |
1374 | * are almost suspended anyway. | | 1374 | * are almost suspended anyway. |
1375 | * | | 1375 | * |
1376 | * Note that this power handler isn't to be registered directly; the | | 1376 | * Note that this power handler isn't to be registered directly; the |
1377 | * bus glue needs to call out to it. | | 1377 | * bus glue needs to call out to it. |
1378 | */ | | 1378 | */ |
1379 | bool | | 1379 | bool |
1380 | ehci_suspend(device_t dv, const pmf_qual_t *qual) | | 1380 | ehci_suspend(device_t dv, const pmf_qual_t *qual) |
1381 | { | | 1381 | { |
1382 | ehci_softc_t *sc = device_private(dv); | | 1382 | ehci_softc_t *sc = device_private(dv); |
1383 | int i; | | 1383 | int i; |
1384 | uint32_t cmd, hcr; | | 1384 | uint32_t cmd, hcr; |
1385 | | | 1385 | |
1386 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 1386 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
1387 | | | 1387 | |
1388 | mutex_spin_enter(&sc->sc_intr_lock); | | 1388 | mutex_spin_enter(&sc->sc_intr_lock); |
1389 | sc->sc_bus.ub_usepolling++; | | 1389 | sc->sc_bus.ub_usepolling++; |
1390 | mutex_spin_exit(&sc->sc_intr_lock); | | 1390 | mutex_spin_exit(&sc->sc_intr_lock); |
1391 | | | 1391 | |
1392 | for (i = 1; i <= sc->sc_noport; i++) { | | 1392 | for (i = 1; i <= sc->sc_noport; i++) { |
1393 | cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; | | 1393 | cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; |
1394 | if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) | | 1394 | if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) |
1395 | EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); | | 1395 | EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); |
1396 | } | | 1396 | } |
1397 | | | 1397 | |
1398 | sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); | | 1398 | sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); |
1399 | | | 1399 | |
1400 | cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); | | 1400 | cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); |
1401 | EOWRITE4(sc, EHCI_USBCMD, cmd); | | 1401 | EOWRITE4(sc, EHCI_USBCMD, cmd); |
1402 | | | 1402 | |
1403 | for (i = 0; i < 100; i++) { | | 1403 | for (i = 0; i < 100; i++) { |
1404 | hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); | | 1404 | hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); |
1405 | if (hcr == 0) | | 1405 | if (hcr == 0) |
1406 | break; | | 1406 | break; |
1407 | | | 1407 | |
1408 | usb_delay_ms(&sc->sc_bus, 1); | | 1408 | usb_delay_ms(&sc->sc_bus, 1); |
1409 | } | | 1409 | } |
1410 | if (hcr != 0) | | 1410 | if (hcr != 0) |
1411 | printf("%s: reset timeout\n", device_xname(dv)); | | 1411 | printf("%s: reset timeout\n", device_xname(dv)); |
1412 | | | 1412 | |
1413 | cmd &= ~EHCI_CMD_RS; | | 1413 | cmd &= ~EHCI_CMD_RS; |
1414 | EOWRITE4(sc, EHCI_USBCMD, cmd); | | 1414 | EOWRITE4(sc, EHCI_USBCMD, cmd); |
1415 | | | 1415 | |
1416 | for (i = 0; i < 100; i++) { | | 1416 | for (i = 0; i < 100; i++) { |
1417 | hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; | | 1417 | hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; |
1418 | if (hcr == EHCI_STS_HCH) | | 1418 | if (hcr == EHCI_STS_HCH) |
1419 | break; | | 1419 | break; |
1420 | | | 1420 | |
1421 | usb_delay_ms(&sc->sc_bus, 1); | | 1421 | usb_delay_ms(&sc->sc_bus, 1); |
1422 | } | | 1422 | } |
1423 | if (hcr != EHCI_STS_HCH) | | 1423 | if (hcr != EHCI_STS_HCH) |
1424 | printf("%s: config timeout\n", device_xname(dv)); | | 1424 | printf("%s: config timeout\n", device_xname(dv)); |
1425 | | | 1425 | |
1426 | mutex_spin_enter(&sc->sc_intr_lock); | | 1426 | mutex_spin_enter(&sc->sc_intr_lock); |
1427 | sc->sc_bus.ub_usepolling--; | | 1427 | sc->sc_bus.ub_usepolling--; |
1428 | mutex_spin_exit(&sc->sc_intr_lock); | | 1428 | mutex_spin_exit(&sc->sc_intr_lock); |
1429 | | | 1429 | |
1430 | return true; | | 1430 | return true; |
1431 | } | | 1431 | } |
1432 | | | 1432 | |
1433 | bool | | 1433 | bool |
1434 | ehci_resume(device_t dv, const pmf_qual_t *qual) | | 1434 | ehci_resume(device_t dv, const pmf_qual_t *qual) |
1435 | { | | 1435 | { |
1436 | ehci_softc_t *sc = device_private(dv); | | 1436 | ehci_softc_t *sc = device_private(dv); |
1437 | int i; | | 1437 | int i; |
1438 | uint32_t cmd, hcr; | | 1438 | uint32_t cmd, hcr; |
1439 | | | 1439 | |
1440 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 1440 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
1441 | | | 1441 | |
1442 | /* restore things in case the bios sucks */ | | 1442 | /* restore things in case the bios sucks */ |
1443 | EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); | | 1443 | EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); |
1444 | EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); | | 1444 | EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); |
1445 | EOWRITE4(sc, EHCI_ASYNCLISTADDR, | | 1445 | EOWRITE4(sc, EHCI_ASYNCLISTADDR, |
1446 | sc->sc_async_head->physaddr | EHCI_LINK_QH); | | 1446 | sc->sc_async_head->physaddr | EHCI_LINK_QH); |
1447 | | | 1447 | |
1448 | EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); | | 1448 | EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); |
1449 | | | 1449 | |
1450 | EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); | | 1450 | EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); |
1451 | | | 1451 | |
1452 | hcr = 0; | | 1452 | hcr = 0; |
1453 | for (i = 1; i <= sc->sc_noport; i++) { | | 1453 | for (i = 1; i <= sc->sc_noport; i++) { |
1454 | cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; | | 1454 | cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; |
1455 | if ((cmd & EHCI_PS_PO) == 0 && | | 1455 | if ((cmd & EHCI_PS_PO) == 0 && |
1456 | (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { | | 1456 | (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { |
1457 | EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); | | 1457 | EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); |
1458 | hcr = 1; | | 1458 | hcr = 1; |
1459 | } | | 1459 | } |
1460 | } | | 1460 | } |
1461 | | | 1461 | |
1462 | if (hcr) { | | 1462 | if (hcr) { |
1463 | usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); | | 1463 | usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); |
1464 | | | 1464 | |
1465 | for (i = 1; i <= sc->sc_noport; i++) { | | 1465 | for (i = 1; i <= sc->sc_noport; i++) { |
1466 | cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; | | 1466 | cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; |
1467 | if ((cmd & EHCI_PS_PO) == 0 && | | 1467 | if ((cmd & EHCI_PS_PO) == 0 && |
1468 | (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) | | 1468 | (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) |
1469 | EOWRITE4(sc, EHCI_PORTSC(i), | | 1469 | EOWRITE4(sc, EHCI_PORTSC(i), |
1470 | cmd & ~EHCI_PS_FPR); | | 1470 | cmd & ~EHCI_PS_FPR); |
1471 | } | | 1471 | } |
1472 | } | | 1472 | } |
1473 | | | 1473 | |
1474 | EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); | | 1474 | EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); |
1475 | EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); | | 1475 | EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); |
1476 | | | 1476 | |
1477 | for (i = 0; i < 100; i++) { | | 1477 | for (i = 0; i < 100; i++) { |
1478 | hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; | | 1478 | hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; |
1479 | if (hcr != EHCI_STS_HCH) | | 1479 | if (hcr != EHCI_STS_HCH) |
1480 | break; | | 1480 | break; |
1481 | | | 1481 | |
1482 | usb_delay_ms(&sc->sc_bus, 1); | | 1482 | usb_delay_ms(&sc->sc_bus, 1); |
1483 | } | | 1483 | } |
1484 | if (hcr == EHCI_STS_HCH) | | 1484 | if (hcr == EHCI_STS_HCH) |
1485 | printf("%s: config timeout\n", device_xname(dv)); | | 1485 | printf("%s: config timeout\n", device_xname(dv)); |
1486 | | | 1486 | |
1487 | return true; | | 1487 | return true; |
1488 | } | | 1488 | } |
1489 | | | 1489 | |
1490 | /* | | 1490 | /* |
1491 | * Shut down the controller when the system is going down. | | 1491 | * Shut down the controller when the system is going down. |
1492 | */ | | 1492 | */ |
1493 | bool | | 1493 | bool |
1494 | ehci_shutdown(device_t self, int flags) | | 1494 | ehci_shutdown(device_t self, int flags) |
1495 | { | | 1495 | { |
1496 | ehci_softc_t *sc = device_private(self); | | 1496 | ehci_softc_t *sc = device_private(self); |
1497 | | | 1497 | |
1498 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 1498 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
1499 | | | 1499 | |
1500 | EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ | | 1500 | EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ |
1501 | EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); | | 1501 | EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); |
1502 | return true; | | 1502 | return true; |
1503 | } | | 1503 | } |
1504 | | | 1504 | |
1505 | Static struct usbd_xfer * | | 1505 | Static struct usbd_xfer * |
1506 | ehci_allocx(struct usbd_bus *bus, unsigned int nframes) | | 1506 | ehci_allocx(struct usbd_bus *bus, unsigned int nframes) |
1507 | { | | 1507 | { |
1508 | struct ehci_softc *sc = EHCI_BUS2SC(bus); | | 1508 | struct ehci_softc *sc = EHCI_BUS2SC(bus); |
1509 | struct usbd_xfer *xfer; | | 1509 | struct usbd_xfer *xfer; |
1510 | | | 1510 | |
1511 | xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); | | 1511 | xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); |
1512 | if (xfer != NULL) { | | 1512 | if (xfer != NULL) { |
1513 | memset(xfer, 0, sizeof(struct ehci_xfer)); | | 1513 | memset(xfer, 0, sizeof(struct ehci_xfer)); |
1514 | #ifdef DIAGNOSTIC | | 1514 | #ifdef DIAGNOSTIC |
1515 | struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); | | 1515 | struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); |
1516 | ex->ex_isdone = true; | | 1516 | ex->ex_isdone = true; |
1517 | xfer->ux_state = XFER_BUSY; | | 1517 | xfer->ux_state = XFER_BUSY; |
1518 | #endif | | 1518 | #endif |
1519 | } | | 1519 | } |
1520 | return xfer; | | 1520 | return xfer; |
1521 | } | | 1521 | } |
1522 | | | 1522 | |
1523 | Static void | | 1523 | Static void |
1524 | ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) | | 1524 | ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) |
1525 | { | | 1525 | { |
1526 | struct ehci_softc *sc = EHCI_BUS2SC(bus); | | 1526 | struct ehci_softc *sc = EHCI_BUS2SC(bus); |
1527 | struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); | | 1527 | struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); |
1528 | | | 1528 | |
1529 | KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, | | 1529 | KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, |
1530 | xfer->ux_state); | | 1530 | xfer->ux_state); |
1531 | KASSERT(ex->ex_isdone); | | 1531 | KASSERT(ex->ex_isdone); |
1532 | | | 1532 | |
1533 | #ifdef DIAGNOSTIC | | 1533 | #ifdef DIAGNOSTIC |
1534 | xfer->ux_state = XFER_FREE; | | 1534 | xfer->ux_state = XFER_FREE; |
1535 | #endif | | 1535 | #endif |
1536 | | | 1536 | |
1537 | pool_cache_put(sc->sc_xferpool, xfer); | | 1537 | pool_cache_put(sc->sc_xferpool, xfer); |
1538 | } | | 1538 | } |
1539 | | | 1539 | |
1540 | Static void | | 1540 | Static void |
1541 | ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) | | 1541 | ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) |
1542 | { | | 1542 | { |
1543 | struct ehci_softc *sc = EHCI_BUS2SC(bus); | | 1543 | struct ehci_softc *sc = EHCI_BUS2SC(bus); |
1544 | | | 1544 | |
1545 | *lock = &sc->sc_lock; | | 1545 | *lock = &sc->sc_lock; |
1546 | } | | 1546 | } |
1547 | | | 1547 | |
1548 | Static void | | 1548 | Static void |
1549 | ehci_device_clear_toggle(struct usbd_pipe *pipe) | | 1549 | ehci_device_clear_toggle(struct usbd_pipe *pipe) |
1550 | { | | 1550 | { |
1551 | struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); | | 1551 | struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); |
1552 | | | 1552 | |
1553 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 1553 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
1554 | | | 1554 | |
1555 | DPRINTF("epipe=%p status=0x%08x", epipe, | | 1555 | DPRINTF("epipe=%p status=0x%08x", epipe, |
1556 | epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); | | 1556 | epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); |
1557 | #ifdef EHCI_DEBUG | | 1557 | #ifdef EHCI_DEBUG |
1558 | if (ehcidebug) | | 1558 | if (ehcidebug) |
1559 | usbd_dump_pipe(pipe); | | 1559 | usbd_dump_pipe(pipe); |
1560 | #endif | | 1560 | #endif |
1561 | epipe->nexttoggle = 0; | | 1561 | epipe->nexttoggle = 0; |
1562 | } | | 1562 | } |
1563 | | | 1563 | |
1564 | Static void | | 1564 | Static void |
1565 | ehci_noop(struct usbd_pipe *pipe) | | 1565 | ehci_noop(struct usbd_pipe *pipe) |
1566 | { | | 1566 | { |
1567 | } | | 1567 | } |
1568 | | | 1568 | |
1569 | #ifdef EHCI_DEBUG | | 1569 | #ifdef EHCI_DEBUG |
1570 | /* | | 1570 | /* |
1571 | * Unused function - this is meant to be called from a kernel | | 1571 | * Unused function - this is meant to be called from a kernel |
1572 | * debugger. | | 1572 | * debugger. |
1573 | */ | | 1573 | */ |
1574 | void | | 1574 | void |
1575 | ehci_dump(void) | | 1575 | ehci_dump(void) |
1576 | { | | 1576 | { |
1577 | ehci_softc_t *sc = theehci; | | 1577 | ehci_softc_t *sc = theehci; |
1578 | int i; | | 1578 | int i; |
1579 | printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", | | 1579 | printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", |
1580 | EOREAD4(sc, EHCI_USBCMD), | | 1580 | EOREAD4(sc, EHCI_USBCMD), |
1581 | EOREAD4(sc, EHCI_USBSTS), | | 1581 | EOREAD4(sc, EHCI_USBSTS), |
1582 | EOREAD4(sc, EHCI_USBINTR)); | | 1582 | EOREAD4(sc, EHCI_USBINTR)); |
1583 | printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", | | 1583 | printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", |
1584 | EOREAD4(sc, EHCI_FRINDEX), | | 1584 | EOREAD4(sc, EHCI_FRINDEX), |
1585 | EOREAD4(sc, EHCI_CTRLDSSEGMENT), | | 1585 | EOREAD4(sc, EHCI_CTRLDSSEGMENT), |
1586 | EOREAD4(sc, EHCI_PERIODICLISTBASE), | | 1586 | EOREAD4(sc, EHCI_PERIODICLISTBASE), |
1587 | EOREAD4(sc, EHCI_ASYNCLISTADDR)); | | 1587 | EOREAD4(sc, EHCI_ASYNCLISTADDR)); |
1588 | for (i = 1; i <= sc->sc_noport; i++) | | 1588 | for (i = 1; i <= sc->sc_noport; i++) |
1589 | printf("port %d status=0x%08x\n", i, | | 1589 | printf("port %d status=0x%08x\n", i, |
1590 | EOREAD4(sc, EHCI_PORTSC(i))); | | 1590 | EOREAD4(sc, EHCI_PORTSC(i))); |
1591 | } | | 1591 | } |
1592 | | | 1592 | |
1593 | Static void | | 1593 | Static void |
1594 | ehci_dump_regs(ehci_softc_t *sc) | | 1594 | ehci_dump_regs(ehci_softc_t *sc) |
1595 | { | | 1595 | { |
1596 | int i; | | 1596 | int i; |
1597 | | | 1597 | |
1598 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 1598 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
1599 | | | 1599 | |
1600 | DPRINTF("cmd = 0x%08x sts = 0x%08x ien = 0x%08x", | | 1600 | DPRINTF("cmd = 0x%08x sts = 0x%08x ien = 0x%08x", |
1601 | EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), | | 1601 | EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), |
1602 | EOREAD4(sc, EHCI_USBINTR), 0); | | 1602 | EOREAD4(sc, EHCI_USBINTR), 0); |
1603 | DPRINTF("frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " | | 1603 | DPRINTF("frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " |
1604 | "async = 0x%08x", | | 1604 | "async = 0x%08x", |
1605 | EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), | | 1605 | EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), |
1606 | EOREAD4(sc, EHCI_PERIODICLISTBASE), | | 1606 | EOREAD4(sc, EHCI_PERIODICLISTBASE), |
1607 | EOREAD4(sc, EHCI_ASYNCLISTADDR)); | | 1607 | EOREAD4(sc, EHCI_ASYNCLISTADDR)); |
1608 | for (i = 1; i <= sc->sc_noport; i += 2) { | | 1608 | for (i = 1; i <= sc->sc_noport; i += 2) { |
1609 | if (i == sc->sc_noport) { | | 1609 | if (i == sc->sc_noport) { |
1610 | DPRINTF("port %d status = 0x%08x", i, | | 1610 | DPRINTF("port %d status = 0x%08x", i, |
1611 | EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); | | 1611 | EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); |
1612 | } else { | | 1612 | } else { |
1613 | DPRINTF( | | 1613 | DPRINTF( |
1614 | "port %d status = 0x%08x port %d status = 0x%08x", | | 1614 | "port %d status = 0x%08x port %d status = 0x%08x", |
1615 | i, EOREAD4(sc, EHCI_PORTSC(i)), | | 1615 | i, EOREAD4(sc, EHCI_PORTSC(i)), |
1616 | i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); | | 1616 | i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); |
1617 | } | | 1617 | } |
1618 | } | | 1618 | } |
1619 | } | | 1619 | } |
1620 | | | 1620 | |
1621 | #define ehci_dump_link(link, type) do { \ | | 1621 | #define ehci_dump_link(link, type) do { \ |
1622 | DPRINTF(" link 0x%08x (T = %d):", \ | | 1622 | DPRINTF(" link 0x%08x (T = %d):", \ |
1623 | link, \ | | 1623 | link, \ |
1624 | link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ | | 1624 | link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ |
1625 | if (type) { \ | | 1625 | if (type) { \ |
1626 | DPRINTF( \ | | 1626 | DPRINTF( \ |
1627 | " ITD = %d QH = %d SITD = %d FSTN = %d",\ | | 1627 | " ITD = %d QH = %d SITD = %d FSTN = %d",\ |
1628 | EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ | | 1628 | EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ |
1629 | EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ | | 1629 | EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ |
1630 | EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ | | 1630 | EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ |
1631 | EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ | | 1631 | EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ |
1632 | } \ | | 1632 | } \ |
1633 | } while(0) | | 1633 | } while(0) |
1634 | | | 1634 | |
1635 | Static void | | 1635 | Static void |
1636 | ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) | | 1636 | ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) |
1637 | { | | 1637 | { |
1638 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 1638 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
1639 | int i; | | 1639 | int i; |
1640 | uint32_t stop = 0; | | 1640 | uint32_t stop = 0; |
1641 | | | 1641 | |
1642 | for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { | | 1642 | for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { |
1643 | ehci_dump_sqtd(sqtd); | | 1643 | ehci_dump_sqtd(sqtd); |
1644 | usb_syncmem(&sqtd->dma, | | 1644 | usb_syncmem(&sqtd->dma, |
1645 | sqtd->offs + offsetof(ehci_qtd_t, qtd_next), | | 1645 | sqtd->offs + offsetof(ehci_qtd_t, qtd_next), |
1646 | sizeof(sqtd->qtd), | | 1646 | sizeof(sqtd->qtd), |
1647 | BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); | | 1647 | BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); |
1648 | stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); | | 1648 | stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); |
1649 | usb_syncmem(&sqtd->dma, | | 1649 | usb_syncmem(&sqtd->dma, |
1650 | sqtd->offs + offsetof(ehci_qtd_t, qtd_next), | | 1650 | sqtd->offs + offsetof(ehci_qtd_t, qtd_next), |
1651 | sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); | | 1651 | sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); |
1652 | } | | 1652 | } |
1653 | if (!stop) | | 1653 | if (!stop) |
1654 | DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); | | 1654 | DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); |
1655 | } | | 1655 | } |
1656 | | | 1656 | |
1657 | Static void | | 1657 | Static void |
1658 | ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) | | 1658 | ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) |
1659 | { | | 1659 | { |
1660 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 1660 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
1661 | | | 1661 | |
1662 | usb_syncmem(&sqtd->dma, sqtd->offs, | | 1662 | usb_syncmem(&sqtd->dma, sqtd->offs, |
1663 | sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); | | 1663 | sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); |
1664 | | | 1664 | |
1665 | DPRINTFN(10, "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); | | 1665 | DPRINTFN(10, "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); |
1666 | ehci_dump_qtd(&sqtd->qtd); | | 1666 | ehci_dump_qtd(&sqtd->qtd); |
1667 | | | 1667 | |
1668 | usb_syncmem(&sqtd->dma, sqtd->offs, | | 1668 | usb_syncmem(&sqtd->dma, sqtd->offs, |
1669 | sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); | | 1669 | sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); |
1670 | } | | 1670 | } |
1671 | | | 1671 | |
1672 | Static void | | 1672 | Static void |
1673 | ehci_dump_qtd(ehci_qtd_t *qtd) | | 1673 | ehci_dump_qtd(ehci_qtd_t *qtd) |
1674 | { | | 1674 | { |
1675 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 1675 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
1676 | uint32_t s = le32toh(qtd->qtd_status); | | 1676 | uint32_t s = le32toh(qtd->qtd_status); |
1677 | | | 1677 | |
1678 | DPRINTFN(10, | | 1678 | DPRINTFN(10, |
1679 | " next = 0x%08x altnext = 0x%08x status = 0x%08x", | | 1679 | " next = 0x%08x altnext = 0x%08x status = 0x%08x", |
1680 | qtd->qtd_next, qtd->qtd_altnext, s, 0); | | 1680 | qtd->qtd_next, qtd->qtd_altnext, s, 0); |
1681 | DPRINTFN(10, | | 1681 | DPRINTFN(10, |
1682 | " toggle = %d ioc = %d bytes = %#x " | | 1682 | " toggle = %d ioc = %d bytes = %#x " |
1683 | "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), | | 1683 | "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), |
1684 | EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); | | 1684 | EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); |
1685 | DPRINTFN(10, | | 1685 | DPRINTFN(10, |
1686 | " cerr = %d pid = %d stat = %x", | | 1686 | " cerr = %d pid = %d stat = %x", |
1687 | EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), | | 1687 | EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), |
1688 | 0); | | 1688 | 0); |
1689 | DPRINTFN(10, | | 1689 | DPRINTFN(10, |
1690 | "active =%d halted=%d buferr=%d babble=%d", | | 1690 | "active =%d halted=%d buferr=%d babble=%d", |
1691 | s & EHCI_QTD_ACTIVE ? 1 : 0, | | 1691 | s & EHCI_QTD_ACTIVE ? 1 : 0, |
1692 | s & EHCI_QTD_HALTED ? 1 : 0, | | 1692 | s & EHCI_QTD_HALTED ? 1 : 0, |
1693 | s & EHCI_QTD_BUFERR ? 1 : 0, | | 1693 | s & EHCI_QTD_BUFERR ? 1 : 0, |
1694 | s & EHCI_QTD_BABBLE ? 1 : 0); | | 1694 | s & EHCI_QTD_BABBLE ? 1 : 0); |
1695 | DPRINTFN(10, | | 1695 | DPRINTFN(10, |
1696 | "xacterr=%d missed=%d split =%d ping =%d", | | 1696 | "xacterr=%d missed=%d split =%d ping =%d", |
1697 | s & EHCI_QTD_XACTERR ? 1 : 0, | | 1697 | s & EHCI_QTD_XACTERR ? 1 : 0, |
1698 | s & EHCI_QTD_MISSEDMICRO ? 1 : 0, | | 1698 | s & EHCI_QTD_MISSEDMICRO ? 1 : 0, |
1699 | s & EHCI_QTD_SPLITXSTATE ? 1 : 0, | | 1699 | s & EHCI_QTD_SPLITXSTATE ? 1 : 0, |
1700 | s & EHCI_QTD_PINGSTATE ? 1 : 0); | | 1700 | s & EHCI_QTD_PINGSTATE ? 1 : 0); |
1701 | DPRINTFN(10, | | 1701 | DPRINTFN(10, |
1702 | "buffer[0] = %#x buffer[1] = %#x " | | 1702 | "buffer[0] = %#x buffer[1] = %#x " |
1703 | "buffer[2] = %#x buffer[3] = %#x", | | 1703 | "buffer[2] = %#x buffer[3] = %#x", |
1704 | le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), | | 1704 | le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), |
1705 | le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); | | 1705 | le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); |
1706 | DPRINTFN(10, | | 1706 | DPRINTFN(10, |
1707 | "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); | | 1707 | "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); |
1708 | } | | 1708 | } |
1709 | | | 1709 | |
1710 | Static void | | 1710 | Static void |
1711 | ehci_dump_sqh(ehci_soft_qh_t *sqh) | | 1711 | ehci_dump_sqh(ehci_soft_qh_t *sqh) |
1712 | { | | 1712 | { |
1713 | ehci_qh_t *qh = &sqh->qh; | | 1713 | ehci_qh_t *qh = &sqh->qh; |
1714 | ehci_link_t link; | | 1714 | ehci_link_t link; |
1715 | uint32_t endp, endphub; | | 1715 | uint32_t endp, endphub; |
1716 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 1716 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
1717 | | | 1717 | |
1718 | usb_syncmem(&sqh->dma, sqh->offs, | | 1718 | usb_syncmem(&sqh->dma, sqh->offs, |
1719 | sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); | | 1719 | sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); |
1720 | | | 1720 | |
1721 | DPRINTFN(10, "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); | | 1721 | DPRINTFN(10, "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); |
1722 | link = le32toh(qh->qh_link); | | 1722 | link = le32toh(qh->qh_link); |
1723 | ehci_dump_link(link, true); | | 1723 | ehci_dump_link(link, true); |
1724 | | | 1724 | |
1725 | endp = le32toh(qh->qh_endp); | | 1725 | endp = le32toh(qh->qh_endp); |
1726 | DPRINTFN(10, " endp = %#x", endp, 0, 0, 0); | | 1726 | DPRINTFN(10, " endp = %#x", endp, 0, 0, 0); |
1727 | DPRINTFN(10, " addr = 0x%02x inact = %d endpt = %d eps = %d", | | 1727 | DPRINTFN(10, " addr = 0x%02x inact = %d endpt = %d eps = %d", |
1728 | EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), | | 1728 | EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), |
1729 | EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); | | 1729 | EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); |
1730 | DPRINTFN(10, " dtc = %d hrecl = %d", | | 1730 | DPRINTFN(10, " dtc = %d hrecl = %d", |
1731 | EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); | | 1731 | EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); |
1732 | DPRINTFN(10, " ctl = %d nrl = %d mpl = %#x(%d)", | | 1732 | DPRINTFN(10, " ctl = %d nrl = %d mpl = %#x(%d)", |
1733 | EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), | | 1733 | EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), |
1734 | EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); | | 1734 | EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); |
1735 | | | 1735 | |
1736 | endphub = le32toh(qh->qh_endphub); | | 1736 | endphub = le32toh(qh->qh_endphub); |
1737 | DPRINTFN(10, " endphub = %#x", endphub, 0, 0, 0); | | 1737 | DPRINTFN(10, " endphub = %#x", endphub, 0, 0, 0); |
1738 | DPRINTFN(10, " smask = 0x%02x cmask = 0x%02x", | | 1738 | DPRINTFN(10, " smask = 0x%02x cmask = 0x%02x", |
1739 | EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); | | 1739 | EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); |
1740 | DPRINTFN(10, " huba = 0x%02x port = %d mult = %d", | | 1740 | DPRINTFN(10, " huba = 0x%02x port = %d mult = %d", |
1741 | EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), | | 1741 | EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), |
1742 | EHCI_QH_GET_MULT(endphub), 0); | | 1742 | EHCI_QH_GET_MULT(endphub), 0); |
1743 | | | 1743 | |
1744 | link = le32toh(qh->qh_curqtd); | | 1744 | link = le32toh(qh->qh_curqtd); |
1745 | ehci_dump_link(link, false); | | 1745 | ehci_dump_link(link, false); |
1746 | DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0); | | 1746 | DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0); |
1747 | ehci_dump_qtd(&qh->qh_qtd); | | 1747 | ehci_dump_qtd(&qh->qh_qtd); |
1748 | | | 1748 | |
1749 | usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), | | 1749 | usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), |
1750 | BUS_DMASYNC_PREREAD); | | 1750 | BUS_DMASYNC_PREREAD); |
1751 | } | | 1751 | } |
1752 | | | 1752 | |
1753 | Static void | | 1753 | Static void |
1754 | ehci_dump_itds(ehci_soft_itd_t *itd) | | 1754 | ehci_dump_itds(ehci_soft_itd_t *itd) |
1755 | { | | 1755 | { |
1756 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 1756 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
1757 | int i; | | 1757 | int i; |
1758 | uint32_t stop = 0; | | 1758 | uint32_t stop = 0; |
1759 | | | 1759 | |
1760 | for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { | | 1760 | for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { |
1761 | ehci_dump_itd(itd); | | 1761 | ehci_dump_itd(itd); |
1762 | usb_syncmem(&itd->dma, | | 1762 | usb_syncmem(&itd->dma, |
1763 | itd->offs + offsetof(ehci_itd_t, itd_next), | | 1763 | itd->offs + offsetof(ehci_itd_t, itd_next), |
1764 | sizeof(itd->itd), | | 1764 | sizeof(itd->itd), |
1765 | BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); | | 1765 | BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); |
1766 | stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); | | 1766 | stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); |
1767 | usb_syncmem(&itd->dma, | | 1767 | usb_syncmem(&itd->dma, |
1768 | itd->offs + offsetof(ehci_itd_t, itd_next), | | 1768 | itd->offs + offsetof(ehci_itd_t, itd_next), |
1769 | sizeof(itd->itd), BUS_DMASYNC_PREREAD); | | 1769 | sizeof(itd->itd), BUS_DMASYNC_PREREAD); |
1770 | } | | 1770 | } |
1771 | if (!stop) | | 1771 | if (!stop) |
1772 | DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); | | 1772 | DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); |
1773 | } | | 1773 | } |
1774 | | | 1774 | |
1775 | Static void | | 1775 | Static void |
1776 | ehci_dump_itd(struct ehci_soft_itd *itd) | | 1776 | ehci_dump_itd(struct ehci_soft_itd *itd) |
1777 | { | | 1777 | { |
1778 | ehci_isoc_trans_t t; | | 1778 | ehci_isoc_trans_t t; |
1779 | ehci_isoc_bufr_ptr_t b, b2, b3; | | 1779 | ehci_isoc_bufr_ptr_t b, b2, b3; |
1780 | int i; | | 1780 | int i; |
1781 | | | 1781 | |
1782 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 1782 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
1783 | | | 1783 | |
1784 | DPRINTF("ITD: next phys = %#x", itd->itd.itd_next, 0, 0, 0); | | 1784 | DPRINTF("ITD: next phys = %#x", itd->itd.itd_next, 0, 0, 0); |
1785 | | | 1785 | |
1786 | for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { | | 1786 | for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { |
1787 | t = le32toh(itd->itd.itd_ctl[i]); | | 1787 | t = le32toh(itd->itd.itd_ctl[i]); |
1788 | DPRINTF("ITDctl %d: stat = %x len = %x", | | 1788 | DPRINTF("ITDctl %d: stat = %x len = %x", |
1789 | i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); | | 1789 | i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); |
1790 | DPRINTF(" ioc = %x pg = %x offs = %x", | | 1790 | DPRINTF(" ioc = %x pg = %x offs = %x", |
1791 | EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), | | 1791 | EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), |
1792 | EHCI_ITD_GET_OFFS(t), 0); | | 1792 | EHCI_ITD_GET_OFFS(t), 0); |
1793 | } | | 1793 | } |
1794 | DPRINTF("ITDbufr: ", 0, 0, 0, 0); | | 1794 | DPRINTF("ITDbufr: ", 0, 0, 0, 0); |
1795 | for (i = 0; i < EHCI_ITD_NBUFFERS; i++) | | 1795 | for (i = 0; i < EHCI_ITD_NBUFFERS; i++) |
1796 | DPRINTF(" %x", | | 1796 | DPRINTF(" %x", |
1797 | EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); | | 1797 | EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); |
1798 | | | 1798 | |
1799 | b = le32toh(itd->itd.itd_bufr[0]); | | 1799 | b = le32toh(itd->itd.itd_bufr[0]); |
1800 | b2 = le32toh(itd->itd.itd_bufr[1]); | | 1800 | b2 = le32toh(itd->itd.itd_bufr[1]); |
1801 | b3 = le32toh(itd->itd.itd_bufr[2]); | | 1801 | b3 = le32toh(itd->itd.itd_bufr[2]); |
1802 | DPRINTF(" ep = %x daddr = %x dir = %d", | | 1802 | DPRINTF(" ep = %x daddr = %x dir = %d", |
1803 | EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); | | 1803 | EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); |
1804 | DPRINTF(" maxpkt = %x multi = %x", | | 1804 | DPRINTF(" maxpkt = %x multi = %x", |
1805 | EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); | | 1805 | EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); |
1806 | } | | 1806 | } |
1807 | | | 1807 | |
1808 | Static void | | 1808 | Static void |
1809 | ehci_dump_sitd(struct ehci_soft_itd *itd) | | 1809 | ehci_dump_sitd(struct ehci_soft_itd *itd) |
1810 | { | | 1810 | { |
1811 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 1811 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
1812 | | | 1812 | |
1813 | DPRINTF("SITD %p next = %p prev = %p", | | 1813 | DPRINTF("SITD %p next = %p prev = %p", |
1814 | itd, itd->frame_list.next, itd->frame_list.prev, 0); | | 1814 | itd, itd->frame_list.next, itd->frame_list.prev, 0); |
1815 | DPRINTF(" xfernext=%p physaddr=%X slot=%d", | | 1815 | DPRINTF(" xfernext=%p physaddr=%X slot=%d", |
1816 | itd->xfer_next, itd->physaddr, itd->slot, 0); | | 1816 | itd->xfer_next, itd->physaddr, itd->slot, 0); |
1817 | } | | 1817 | } |
1818 | | | 1818 | |
1819 | Static void | | 1819 | Static void |
1820 | ehci_dump_exfer(struct ehci_xfer *ex) | | 1820 | ehci_dump_exfer(struct ehci_xfer *ex) |
1821 | { | | 1821 | { |
1822 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 1822 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
1823 | | | 1823 | |
1824 | DPRINTF("ex = %p type %d isdone", ex, ex->ex_type, | | 1824 | DPRINTF("ex = %p type %d isdone", ex, ex->ex_type, |
1825 | ex->ex_isdone, 0); | | 1825 | ex->ex_isdone, 0); |
1826 | | | 1826 | |
1827 | switch (ex->ex_type) { | | 1827 | switch (ex->ex_type) { |
1828 | case EX_CTRL: | | 1828 | case EX_CTRL: |
1829 | DPRINTF(" setup = %p data = %p status = %p", | | 1829 | DPRINTF(" setup = %p data = %p status = %p", |
1830 | ex->ex_setup, ex->ex_data, ex->ex_status, 0); | | 1830 | ex->ex_setup, ex->ex_data, ex->ex_status, 0); |
1831 | break; | | 1831 | break; |
1832 | case EX_BULK: | | 1832 | case EX_BULK: |
1833 | case EX_INTR: | | 1833 | case EX_INTR: |
1834 | DPRINTF(" qtdstart = %p qtdend = %p", | | 1834 | DPRINTF(" qtdstart = %p qtdend = %p", |
1835 | ex->ex_sqtdstart, ex->ex_sqtdend, 0, 0); | | 1835 | ex->ex_sqtdstart, ex->ex_sqtdend, 0, 0); |
1836 | break; | | 1836 | break; |
1837 | case EX_ISOC: | | 1837 | case EX_ISOC: |
1838 | DPRINTF(" itdstart = %p itdend = %p", | | 1838 | DPRINTF(" itdstart = %p itdend = %p", |
1839 | ex->ex_itdstart, ex->ex_itdend, 0, 0); | | 1839 | ex->ex_itdstart, ex->ex_itdend, 0, 0); |
1840 | break; | | 1840 | break; |
1841 | case EX_FS_ISOC: | | 1841 | case EX_FS_ISOC: |
1842 | DPRINTF(" sitdstart = %p sitdend = %p", | | 1842 | DPRINTF(" sitdstart = %p sitdend = %p", |
1843 | ex->ex_sitdstart, ex->ex_sitdend, 0, 0); | | 1843 | ex->ex_sitdstart, ex->ex_sitdend, 0, 0); |
1844 | break; | | 1844 | break; |
1845 | default: | | 1845 | default: |
1846 | DPRINTF(" unknown type", 0, 0, 0, 0); | | 1846 | DPRINTF(" unknown type", 0, 0, 0, 0); |
1847 | } | | 1847 | } |
1848 | } | | 1848 | } |
1849 | #endif | | 1849 | #endif |
1850 | | | 1850 | |
1851 | Static usbd_status | | 1851 | Static usbd_status |
1852 | ehci_open(struct usbd_pipe *pipe) | | 1852 | ehci_open(struct usbd_pipe *pipe) |
1853 | { | | 1853 | { |
1854 | struct usbd_device *dev = pipe->up_dev; | | 1854 | struct usbd_device *dev = pipe->up_dev; |
1855 | ehci_softc_t *sc = EHCI_PIPE2SC(pipe); | | 1855 | ehci_softc_t *sc = EHCI_PIPE2SC(pipe); |
1856 | usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; | | 1856 | usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; |
1857 | uint8_t rhaddr = dev->ud_bus->ub_rhaddr; | | 1857 | uint8_t rhaddr = dev->ud_bus->ub_rhaddr; |
1858 | uint8_t addr = dev->ud_addr; | | 1858 | uint8_t addr = dev->ud_addr; |
1859 | uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); | | 1859 | uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); |
1860 | struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); | | 1860 | struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); |
1861 | ehci_soft_qh_t *sqh; | | 1861 | ehci_soft_qh_t *sqh; |
1862 | usbd_status err; | | 1862 | usbd_status err; |
1863 | int ival, speed, naks; | | 1863 | int ival, speed, naks; |
1864 | int hshubaddr, hshubport; | | 1864 | int hshubaddr, hshubport; |
1865 | | | 1865 | |
1866 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 1866 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
1867 | | | 1867 | |
1868 | DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)", pipe, addr, | | 1868 | DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)", pipe, addr, |
1869 | ed->bEndpointAddress, rhaddr); | | 1869 | ed->bEndpointAddress, rhaddr); |
1870 | | | 1870 | |
1871 | if (dev->ud_myhsport) { | | 1871 | if (dev->ud_myhsport) { |
1872 | /* | | 1872 | /* |
1873 | * When directly attached FS/LS device while doing embedded | | 1873 | * When directly attached FS/LS device while doing embedded |
1874 | * transaction translations and we are the hub, set the hub | | 1874 | * transaction translations and we are the hub, set the hub |
1875 | * address to 0 (us). | | 1875 | * address to 0 (us). |
1876 | */ | | 1876 | */ |
1877 | if (!(sc->sc_flags & EHCIF_ETTF) | | 1877 | if (!(sc->sc_flags & EHCIF_ETTF) |
1878 | || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { | | 1878 | || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { |
1879 | hshubaddr = dev->ud_myhsport->up_parent->ud_addr; | | 1879 | hshubaddr = dev->ud_myhsport->up_parent->ud_addr; |
1880 | } else { | | 1880 | } else { |
1881 | hshubaddr = 0; | | 1881 | hshubaddr = 0; |
1882 | } | | 1882 | } |
1883 | hshubport = dev->ud_myhsport->up_portno; | | 1883 | hshubport = dev->ud_myhsport->up_portno; |
1884 | } else { | | 1884 | } else { |
1885 | hshubaddr = 0; | | 1885 | hshubaddr = 0; |
1886 | hshubport = 0; | | 1886 | hshubport = 0; |
1887 | } | | 1887 | } |
1888 | | | 1888 | |
1889 | if (sc->sc_dying) | | 1889 | if (sc->sc_dying) |
1890 | return USBD_IOERROR; | | 1890 | return USBD_IOERROR; |
1891 | | | 1891 | |
1892 | /* toggle state needed for bulk endpoints */ | | 1892 | /* toggle state needed for bulk endpoints */ |
1893 | epipe->nexttoggle = pipe->up_endpoint->ue_toggle; | | 1893 | epipe->nexttoggle = pipe->up_endpoint->ue_toggle; |
1894 | | | 1894 | |
1895 | if (addr == rhaddr) { | | 1895 | if (addr == rhaddr) { |
1896 | switch (ed->bEndpointAddress) { | | 1896 | switch (ed->bEndpointAddress) { |
1897 | case USB_CONTROL_ENDPOINT: | | 1897 | case USB_CONTROL_ENDPOINT: |
1898 | pipe->up_methods = &roothub_ctrl_methods; | | 1898 | pipe->up_methods = &roothub_ctrl_methods; |
1899 | break; | | 1899 | break; |
1900 | case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: | | 1900 | case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: |
1901 | pipe->up_methods = &ehci_root_intr_methods; | | 1901 | pipe->up_methods = &ehci_root_intr_methods; |
1902 | break; | | 1902 | break; |
1903 | default: | | 1903 | default: |
1904 | DPRINTF("bad bEndpointAddress 0x%02x", | | 1904 | DPRINTF("bad bEndpointAddress 0x%02x", |
1905 | ed->bEndpointAddress, 0, 0, 0); | | 1905 | ed->bEndpointAddress, 0, 0, 0); |
1906 | return USBD_INVAL; | | 1906 | return USBD_INVAL; |
1907 | } | | 1907 | } |
1908 | return USBD_NORMAL_COMPLETION; | | 1908 | return USBD_NORMAL_COMPLETION; |
1909 | } | | 1909 | } |
1910 | | | 1910 | |
1911 | /* XXX All this stuff is only valid for async. */ | | 1911 | /* XXX All this stuff is only valid for async. */ |
1912 | switch (dev->ud_speed) { | | 1912 | switch (dev->ud_speed) { |
1913 | case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; | | 1913 | case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; |
1914 | case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; | | 1914 | case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; |
1915 | case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; | | 1915 | case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; |
1916 | default: panic("ehci_open: bad device speed %d", dev->ud_speed); | | 1916 | default: panic("ehci_open: bad device speed %d", dev->ud_speed); |
1917 | } | | 1917 | } |
1918 | if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { | | 1918 | if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { |
1919 | DPRINTF("hshubaddr=%d hshubport=%d", hshubaddr, hshubport, 0, | | 1919 | DPRINTF("hshubaddr=%d hshubport=%d", hshubaddr, hshubport, 0, |
1920 | 0); | | 1920 | 0); |
1921 | return USBD_INVAL; | | 1921 | return USBD_INVAL; |
1922 | } | | 1922 | } |
1923 | | | 1923 | |
1924 | /* | | 1924 | /* |
1925 | * For interrupt transfer, nak throttling must be disabled, but for | | 1925 | * For interrupt transfer, nak throttling must be disabled, but for |
1926 | * the other transfer type, nak throttling should be enabled from the | | 1926 | * the other transfer type, nak throttling should be enabled from the |
1927 | * viewpoint that avoids the memory thrashing. | | 1927 | * viewpoint that avoids the memory thrashing. |
1928 | */ | | 1928 | */ |
1929 | naks = (xfertype == UE_INTERRUPT) ? 0 | | 1929 | naks = (xfertype == UE_INTERRUPT) ? 0 |
1930 | : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); | | 1930 | : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); |
1931 | | | 1931 | |
1932 | /* Allocate sqh for everything, save isoc xfers */ | | 1932 | /* Allocate sqh for everything, save isoc xfers */ |
1933 | if (xfertype != UE_ISOCHRONOUS) { | | 1933 | if (xfertype != UE_ISOCHRONOUS) { |
1934 | sqh = ehci_alloc_sqh(sc); | | 1934 | sqh = ehci_alloc_sqh(sc); |
1935 | if (sqh == NULL) | | 1935 | if (sqh == NULL) |
1936 | return USBD_NOMEM; | | 1936 | return USBD_NOMEM; |
1937 | /* qh_link filled when the QH is added */ | | 1937 | /* qh_link filled when the QH is added */ |
1938 | sqh->qh.qh_endp = htole32( | | 1938 | sqh->qh.qh_endp = htole32( |
1939 | EHCI_QH_SET_ADDR(addr) | | | 1939 | EHCI_QH_SET_ADDR(addr) | |
1940 | EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | | | 1940 | EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | |
1941 | EHCI_QH_SET_EPS(speed) | | | 1941 | EHCI_QH_SET_EPS(speed) | |
1942 | EHCI_QH_DTC | | | 1942 | EHCI_QH_DTC | |
1943 | EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | | | 1943 | EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | |
1944 | (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? | | 1944 | (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? |
1945 | EHCI_QH_CTL : 0) | | | 1945 | EHCI_QH_CTL : 0) | |
1946 | EHCI_QH_SET_NRL(naks) | | 1946 | EHCI_QH_SET_NRL(naks) |
1947 | ); | | 1947 | ); |
1948 | sqh->qh.qh_endphub = htole32( | | 1948 | sqh->qh.qh_endphub = htole32( |
1949 | EHCI_QH_SET_MULT(1) | | | 1949 | EHCI_QH_SET_MULT(1) | |
1950 | EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) | | 1950 | EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) |
1951 | ); | | 1951 | ); |
1952 | if (speed != EHCI_QH_SPEED_HIGH) | | 1952 | if (speed != EHCI_QH_SPEED_HIGH) |
1953 | sqh->qh.qh_endphub |= htole32( | | 1953 | sqh->qh.qh_endphub |= htole32( |
1954 | EHCI_QH_SET_PORT(hshubport) | | | 1954 | EHCI_QH_SET_PORT(hshubport) | |
1955 | EHCI_QH_SET_HUBA(hshubaddr) | | | 1955 | EHCI_QH_SET_HUBA(hshubaddr) | |
1956 | (xfertype == UE_INTERRUPT ? | | 1956 | (xfertype == UE_INTERRUPT ? |
1957 | EHCI_QH_SET_CMASK(0x08) : 0) | | 1957 | EHCI_QH_SET_CMASK(0x08) : 0) |
1958 | ); | | 1958 | ); |
1959 | sqh->qh.qh_curqtd = EHCI_NULL; | | 1959 | sqh->qh.qh_curqtd = EHCI_NULL; |
1960 | /* Fill the overlay qTD */ | | 1960 | /* Fill the overlay qTD */ |
1961 | sqh->qh.qh_qtd.qtd_next = EHCI_NULL; | | 1961 | sqh->qh.qh_qtd.qtd_next = EHCI_NULL; |
1962 | sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; | | 1962 | sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; |
1963 | sqh->qh.qh_qtd.qtd_status = htole32(0); | | 1963 | sqh->qh.qh_qtd.qtd_status = htole32(0); |
1964 | | | 1964 | |
1965 | usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), | | 1965 | usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), |
1966 | BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); | | 1966 | BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); |
1967 | epipe->sqh = sqh; | | 1967 | epipe->sqh = sqh; |
1968 | } else { | | 1968 | } else { |
1969 | sqh = NULL; | | 1969 | sqh = NULL; |
1970 | } /*xfertype == UE_ISOC*/ | | 1970 | } /*xfertype == UE_ISOC*/ |
1971 | | | 1971 | |
1972 | switch (xfertype) { | | 1972 | switch (xfertype) { |
1973 | case UE_CONTROL: | | 1973 | case UE_CONTROL: |
1974 | err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), | | 1974 | err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), |
1975 | 0, &epipe->ctrl.reqdma); | | 1975 | 0, &epipe->ctrl.reqdma); |
1976 | #ifdef EHCI_DEBUG | | 1976 | #ifdef EHCI_DEBUG |
1977 | if (err) | | 1977 | if (err) |
1978 | printf("ehci_open: usb_allocmem()=%d\n", err); | | 1978 | printf("ehci_open: usb_allocmem()=%d\n", err); |
1979 | #endif | | 1979 | #endif |
1980 | if (err) | | 1980 | if (err) |
1981 | goto bad; | | 1981 | goto bad; |
1982 | pipe->up_methods = &ehci_device_ctrl_methods; | | 1982 | pipe->up_methods = &ehci_device_ctrl_methods; |
1983 | mutex_enter(&sc->sc_lock); | | 1983 | mutex_enter(&sc->sc_lock); |
1984 | ehci_add_qh(sc, sqh, sc->sc_async_head); | | 1984 | ehci_add_qh(sc, sqh, sc->sc_async_head); |
1985 | mutex_exit(&sc->sc_lock); | | 1985 | mutex_exit(&sc->sc_lock); |
1986 | break; | | 1986 | break; |
1987 | case UE_BULK: | | 1987 | case UE_BULK: |
1988 | pipe->up_methods = &ehci_device_bulk_methods; | | 1988 | pipe->up_methods = &ehci_device_bulk_methods; |
1989 | mutex_enter(&sc->sc_lock); | | 1989 | mutex_enter(&sc->sc_lock); |
1990 | ehci_add_qh(sc, sqh, sc->sc_async_head); | | 1990 | ehci_add_qh(sc, sqh, sc->sc_async_head); |
1991 | mutex_exit(&sc->sc_lock); | | 1991 | mutex_exit(&sc->sc_lock); |
1992 | break; | | 1992 | break; |
1993 | case UE_INTERRUPT: | | 1993 | case UE_INTERRUPT: |
1994 | pipe->up_methods = &ehci_device_intr_methods; | | 1994 | pipe->up_methods = &ehci_device_intr_methods; |
1995 | ival = pipe->up_interval; | | 1995 | ival = pipe->up_interval; |
1996 | if (ival == USBD_DEFAULT_INTERVAL) { | | 1996 | if (ival == USBD_DEFAULT_INTERVAL) { |
1997 | if (speed == EHCI_QH_SPEED_HIGH) { | | 1997 | if (speed == EHCI_QH_SPEED_HIGH) { |
1998 | if (ed->bInterval > 16) { | | 1998 | if (ed->bInterval > 16) { |
1999 | /* | | 1999 | /* |
2000 | * illegal with high-speed, but there | | 2000 | * illegal with high-speed, but there |
2001 | * were documentation bugs in the spec, | | 2001 | * were documentation bugs in the spec, |
2002 | * so be generous | | 2002 | * so be generous |
2003 | */ | | 2003 | */ |
2004 | ival = 256; | | 2004 | ival = 256; |
2005 | } else | | 2005 | } else |
2006 | ival = (1 << (ed->bInterval - 1)) / 8; | | 2006 | ival = (1 << (ed->bInterval - 1)) / 8; |
2007 | } else | | 2007 | } else |
2008 | ival = ed->bInterval; | | 2008 | ival = ed->bInterval; |
2009 | } | | 2009 | } |
2010 | err = ehci_device_setintr(sc, sqh, ival); | | 2010 | err = ehci_device_setintr(sc, sqh, ival); |
2011 | if (err) | | 2011 | if (err) |
2012 | goto bad; | | 2012 | goto bad; |
2013 | break; | | 2013 | break; |
2014 | case UE_ISOCHRONOUS: | | 2014 | case UE_ISOCHRONOUS: |
2015 | pipe->up_serialise = false; | | 2015 | pipe->up_serialise = false; |
2016 | if (speed == EHCI_QH_SPEED_HIGH) | | 2016 | if (speed == EHCI_QH_SPEED_HIGH) |
2017 | pipe->up_methods = &ehci_device_isoc_methods; | | 2017 | pipe->up_methods = &ehci_device_isoc_methods; |
2018 | else | | 2018 | else |
2019 | pipe->up_methods = &ehci_device_fs_isoc_methods; | | 2019 | pipe->up_methods = &ehci_device_fs_isoc_methods; |
2020 | if (ed->bInterval == 0 || ed->bInterval > 16) { | | 2020 | if (ed->bInterval == 0 || ed->bInterval > 16) { |
2021 | printf("ehci: opening pipe with invalid bInterval\n"); | | 2021 | printf("ehci: opening pipe with invalid bInterval\n"); |
2022 | err = USBD_INVAL; | | 2022 | err = USBD_INVAL; |
2023 | goto bad; | | 2023 | goto bad; |
2024 | } | | 2024 | } |
2025 | if (UGETW(ed->wMaxPacketSize) == 0) { | | 2025 | if (UGETW(ed->wMaxPacketSize) == 0) { |
2026 | printf("ehci: zero length endpoint open request\n"); | | 2026 | printf("ehci: zero length endpoint open request\n"); |
2027 | err = USBD_INVAL; | | 2027 | err = USBD_INVAL; |
2028 | goto bad; | | 2028 | goto bad; |
2029 | } | | 2029 | } |
2030 | epipe->isoc.next_frame = 0; | | 2030 | epipe->isoc.next_frame = 0; |
2031 | epipe->isoc.cur_xfers = 0; | | 2031 | epipe->isoc.cur_xfers = 0; |
2032 | break; | | 2032 | break; |
2033 | default: | | 2033 | default: |
2034 | DPRINTF("bad xfer type %d", xfertype, 0, 0, 0); | | 2034 | DPRINTF("bad xfer type %d", xfertype, 0, 0, 0); |
2035 | err = USBD_INVAL; | | 2035 | err = USBD_INVAL; |
2036 | goto bad; | | 2036 | goto bad; |
2037 | } | | 2037 | } |
2038 | return USBD_NORMAL_COMPLETION; | | 2038 | return USBD_NORMAL_COMPLETION; |
2039 | | | 2039 | |
2040 | bad: | | 2040 | bad: |
2041 | if (sqh != NULL) { | | 2041 | if (sqh != NULL) { |
2042 | mutex_enter(&sc->sc_lock); | | 2042 | mutex_enter(&sc->sc_lock); |
2043 | ehci_free_sqh(sc, sqh); | | 2043 | ehci_free_sqh(sc, sqh); |
2044 | mutex_exit(&sc->sc_lock); | | 2044 | mutex_exit(&sc->sc_lock); |
2045 | } | | 2045 | } |
2046 | return err; | | 2046 | return err; |
2047 | } | | 2047 | } |
2048 | | | 2048 | |
2049 | /* | | 2049 | /* |
2050 | * Add an ED to the schedule. Called with USB lock held. | | 2050 | * Add an ED to the schedule. Called with USB lock held. |
2051 | */ | | 2051 | */ |
2052 | Static void | | 2052 | Static void |
2053 | ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) | | 2053 | ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) |
2054 | { | | 2054 | { |
2055 | | | 2055 | |
2056 | KASSERT(mutex_owned(&sc->sc_lock)); | | 2056 | KASSERT(mutex_owned(&sc->sc_lock)); |
2057 | | | 2057 | |
2058 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 2058 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
2059 | | | 2059 | |
2060 | usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), | | 2060 | usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), |
2061 | sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); | | 2061 | sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); |
2062 | | | 2062 | |
2063 | sqh->next = head->next; | | 2063 | sqh->next = head->next; |
2064 | sqh->qh.qh_link = head->qh.qh_link; | | 2064 | sqh->qh.qh_link = head->qh.qh_link; |
2065 | | | 2065 | |
2066 | usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), | | 2066 | usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), |
2067 | sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); | | 2067 | sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); |
2068 | | | 2068 | |
2069 | head->next = sqh; | | 2069 | head->next = sqh; |
2070 | head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); | | 2070 | head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); |
2071 | | | 2071 | |
2072 | usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), | | 2072 | usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), |
2073 | sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); | | 2073 | sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); |
2074 | | | 2074 | |
2075 | #ifdef EHCI_DEBUG | | 2075 | #ifdef EHCI_DEBUG |
2076 | DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); | | 2076 | DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); |
2077 | ehci_dump_sqh(sqh); | | 2077 | ehci_dump_sqh(sqh); |
2078 | DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); | | 2078 | DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); |
2079 | #endif | | 2079 | #endif |
2080 | } | | 2080 | } |
2081 | | | 2081 | |
2082 | /* | | 2082 | /* |
2083 | * Remove an ED from the schedule. Called with USB lock held. | | 2083 | * Remove an ED from the schedule. Called with USB lock held. |
2084 | */ | | 2084 | */ |
2085 | Static void | | 2085 | Static void |
2086 | ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) | | 2086 | ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) |
2087 | { | | 2087 | { |
2088 | ehci_soft_qh_t *p; | | 2088 | ehci_soft_qh_t *p; |
2089 | | | 2089 | |
2090 | KASSERT(mutex_owned(&sc->sc_lock)); | | 2090 | KASSERT(mutex_owned(&sc->sc_lock)); |
2091 | | | 2091 | |
2092 | /* XXX */ | | 2092 | /* XXX */ |
2093 | for (p = head; p != NULL && p->next != sqh; p = p->next) | | 2093 | for (p = head; p != NULL && p->next != sqh; p = p->next) |
2094 | ; | | 2094 | ; |
2095 | if (p == NULL) | | 2095 | if (p == NULL) |
2096 | panic("ehci_rem_qh: ED not found"); | | 2096 | panic("ehci_rem_qh: ED not found"); |
2097 | usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), | | 2097 | usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), |
2098 | sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); | | 2098 | sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); |
2099 | p->next = sqh->next; | | 2099 | p->next = sqh->next; |
2100 | p->qh.qh_link = sqh->qh.qh_link; | | 2100 | p->qh.qh_link = sqh->qh.qh_link; |
2101 | usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), | | 2101 | usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), |
2102 | sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); | | 2102 | sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); |
2103 | | | 2103 | |
2104 | ehci_sync_hc(sc); | | 2104 | ehci_sync_hc(sc); |
2105 | } | | 2105 | } |
2106 | | | 2106 | |
2107 | Static void | | 2107 | Static void |
2108 | ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) | | 2108 | ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) |
2109 | { | | 2109 | { |
2110 | int i; | | 2110 | int i; |
2111 | uint32_t status; | | 2111 | uint32_t status; |
2112 | | | 2112 | |
2113 | /* Save toggle bit and ping status. */ | | 2113 | /* Save toggle bit and ping status. */ |
2114 | usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), | | 2114 | usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), |
2115 | BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); | | 2115 | BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); |
2116 | status = sqh->qh.qh_qtd.qtd_status & | | 2116 | status = sqh->qh.qh_qtd.qtd_status & |
2117 | htole32(EHCI_QTD_TOGGLE_MASK | | | 2117 | htole32(EHCI_QTD_TOGGLE_MASK | |
2118 | EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); | | 2118 | EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); |
2119 | /* Set HALTED to make hw leave it alone. */ | | 2119 | /* Set HALTED to make hw leave it alone. */ |
2120 | sqh->qh.qh_qtd.qtd_status = | | 2120 | sqh->qh.qh_qtd.qtd_status = |
2121 | htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); | | 2121 | htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); |
2122 | usb_syncmem(&sqh->dma, | | 2122 | usb_syncmem(&sqh->dma, |
2123 | sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), | | 2123 | sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), |
2124 | sizeof(sqh->qh.qh_qtd.qtd_status), | | 2124 | sizeof(sqh->qh.qh_qtd.qtd_status), |
2125 | BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); | | 2125 | BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); |
2126 | sqh->qh.qh_curqtd = 0; | | 2126 | sqh->qh.qh_curqtd = 0; |
2127 | sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); | | 2127 | sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); |
2128 | sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; | | 2128 | sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; |
2129 | for (i = 0; i < EHCI_QTD_NBUFFERS; i++) | | 2129 | for (i = 0; i < EHCI_QTD_NBUFFERS; i++) |
2130 | sqh->qh.qh_qtd.qtd_buffer[i] = 0; | | 2130 | sqh->qh.qh_qtd.qtd_buffer[i] = 0; |
2131 | sqh->sqtd = sqtd; | | 2131 | sqh->sqtd = sqtd; |
2132 | usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), | | 2132 | usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), |
2133 | BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); | | 2133 | BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); |
2134 | /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ | | 2134 | /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ |
2135 | sqh->qh.qh_qtd.qtd_status = status; | | 2135 | sqh->qh.qh_qtd.qtd_status = status; |
2136 | usb_syncmem(&sqh->dma, | | 2136 | usb_syncmem(&sqh->dma, |
2137 | sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), | | 2137 | sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), |
2138 | sizeof(sqh->qh.qh_qtd.qtd_status), | | 2138 | sizeof(sqh->qh.qh_qtd.qtd_status), |
2139 | BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); | | 2139 | BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); |
2140 | } | | 2140 | } |
2141 | | | 2141 | |
2142 | /* | | 2142 | /* |
2143 | * Ensure that the HC has released all references to the QH. We do this | | 2143 | * Ensure that the HC has released all references to the QH. We do this |
2144 | * by asking for a Async Advance Doorbell interrupt and then we wait for | | 2144 | * by asking for a Async Advance Doorbell interrupt and then we wait for |
2145 | * the interrupt. | | 2145 | * the interrupt. |
2146 | * To make this easier we first obtain exclusive use of the doorbell. | | 2146 | * To make this easier we first obtain exclusive use of the doorbell. |
2147 | */ | | 2147 | */ |
2148 | Static void | | 2148 | Static void |
2149 | ehci_sync_hc(ehci_softc_t *sc) | | 2149 | ehci_sync_hc(ehci_softc_t *sc) |
2150 | { | | 2150 | { |
2151 | int error __diagused; | | 2151 | int error __diagused; |
2152 | | | 2152 | |
2153 | KASSERT(mutex_owned(&sc->sc_lock)); | | 2153 | KASSERT(mutex_owned(&sc->sc_lock)); |
2154 | | | 2154 | |
2155 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 2155 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
2156 | | | 2156 | |
2157 | if (sc->sc_dying) { | | 2157 | if (sc->sc_dying) { |
2158 | DPRINTF("dying", 0, 0, 0, 0); | | 2158 | DPRINTF("dying", 0, 0, 0, 0); |
2159 | return; | | 2159 | return; |
2160 | } | | 2160 | } |
2161 | /* ask for doorbell */ | | 2161 | /* ask for doorbell */ |
2162 | EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); | | 2162 | EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); |
2163 | DPRINTF("cmd = 0x%08x sts = 0x%08x", | | 2163 | DPRINTF("cmd = 0x%08x sts = 0x%08x", |
2164 | EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); | | 2164 | EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); |
2165 | | | 2165 | |
2166 | error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ | | 2166 | error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ |
2167 | | | 2167 | |
2168 | DPRINTF("cmd = 0x%08x sts = 0x%08x ... done", | | 2168 | DPRINTF("cmd = 0x%08x sts = 0x%08x ... done", |
2169 | EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); | | 2169 | EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); |
2170 | #ifdef DIAGNOSTIC | | 2170 | #ifdef DIAGNOSTIC |
2171 | if (error) | | 2171 | if (error == EWOULDBLOCK) { |
2172 | printf("ehci_sync_hc: cv_timedwait() = %d\n", error); | | 2172 | printf("ehci_sync_hc: timed out\n"); |
| | | 2173 | } else if (error) { |
| | | 2174 | printf("ehci_sync_hc: cv_timedwait: error %d\n", error); |
| | | 2175 | } |
2173 | #endif | | 2176 | #endif |
2174 | } | | 2177 | } |
2175 | | | 2178 | |
2176 | Static void | | 2179 | Static void |
2177 | ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) | | 2180 | ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) |
2178 | { | | 2181 | { |
2179 | | | 2182 | |
2180 | KASSERT(mutex_owned(&sc->sc_lock)); | | 2183 | KASSERT(mutex_owned(&sc->sc_lock)); |
2181 | | | 2184 | |
2182 | for (; itd != NULL; itd = itd->xfer_next) { | | 2185 | for (; itd != NULL; itd = itd->xfer_next) { |
2183 | struct ehci_soft_itd *prev = itd->frame_list.prev; | | 2186 | struct ehci_soft_itd *prev = itd->frame_list.prev; |
2184 | | | 2187 | |
2185 | /* Unlink itd from hardware chain, or frame array */ | | 2188 | /* Unlink itd from hardware chain, or frame array */ |
2186 | if (prev == NULL) { /* We're at the table head */ | | 2189 | if (prev == NULL) { /* We're at the table head */ |
2187 | sc->sc_softitds[itd->slot] = itd->frame_list.next; | | 2190 | sc->sc_softitds[itd->slot] = itd->frame_list.next; |
2188 | sc->sc_flist[itd->slot] = itd->itd.itd_next; | | 2191 | sc->sc_flist[itd->slot] = itd->itd.itd_next; |
2189 | usb_syncmem(&sc->sc_fldma, | | 2192 | usb_syncmem(&sc->sc_fldma, |
2190 | sizeof(ehci_link_t) * itd->slot, | | 2193 | sizeof(ehci_link_t) * itd->slot, |
2191 | sizeof(ehci_link_t), | | 2194 | sizeof(ehci_link_t), |
2192 | BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); | | 2195 | BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); |
2193 | | | 2196 | |
2194 | if (itd->frame_list.next != NULL) | | 2197 | if (itd->frame_list.next != NULL) |
2195 | itd->frame_list.next->frame_list.prev = NULL; | | 2198 | itd->frame_list.next->frame_list.prev = NULL; |
2196 | } else { | | 2199 | } else { |
2197 | /* XXX this part is untested... */ | | 2200 | /* XXX this part is untested... */ |
2198 | prev->itd.itd_next = itd->itd.itd_next; | | 2201 | prev->itd.itd_next = itd->itd.itd_next; |
2199 | usb_syncmem(&itd->dma, | | 2202 | usb_syncmem(&itd->dma, |
2200 | itd->offs + offsetof(ehci_itd_t, itd_next), | | 2203 | itd->offs + offsetof(ehci_itd_t, itd_next), |
2201 | sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); | | 2204 | sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); |
2202 | | | 2205 | |
2203 | prev->frame_list.next = itd->frame_list.next; | | 2206 | prev->frame_list.next = itd->frame_list.next; |
2204 | if (itd->frame_list.next != NULL) | | 2207 | if (itd->frame_list.next != NULL) |
2205 | itd->frame_list.next->frame_list.prev = prev; | | 2208 | itd->frame_list.next->frame_list.prev = prev; |
2206 | } | | 2209 | } |
2207 | } | | 2210 | } |
2208 | } | | 2211 | } |
2209 | | | 2212 | |
2210 | Static void | | 2213 | Static void |
2211 | ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) | | 2214 | ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) |
2212 | { | | 2215 | { |
2213 | struct ehci_soft_itd *next; | | 2216 | struct ehci_soft_itd *next; |
2214 | | | 2217 | |
2215 | mutex_enter(&sc->sc_lock); | | 2218 | mutex_enter(&sc->sc_lock); |
2216 | next = NULL; | | 2219 | next = NULL; |
2217 | for (; itd != NULL; itd = next) { | | 2220 | for (; itd != NULL; itd = next) { |
2218 | next = itd->xfer_next; | | 2221 | next = itd->xfer_next; |
2219 | ehci_free_itd_locked(sc, itd); | | 2222 | ehci_free_itd_locked(sc, itd); |
2220 | } | | 2223 | } |
2221 | mutex_exit(&sc->sc_lock); | | 2224 | mutex_exit(&sc->sc_lock); |
2222 | } | | 2225 | } |
2223 | | | 2226 | |
2224 | Static void | | 2227 | Static void |
2225 | ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) | | 2228 | ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) |
2226 | { | | 2229 | { |
2227 | | | 2230 | |
2228 | KASSERT(mutex_owned(&sc->sc_lock)); | | 2231 | KASSERT(mutex_owned(&sc->sc_lock)); |
2229 | | | 2232 | |
2230 | for (; sitd != NULL; sitd = sitd->xfer_next) { | | 2233 | for (; sitd != NULL; sitd = sitd->xfer_next) { |
2231 | struct ehci_soft_sitd *prev = sitd->frame_list.prev; | | 2234 | struct ehci_soft_sitd *prev = sitd->frame_list.prev; |
2232 | | | 2235 | |
2233 | /* Unlink sitd from hardware chain, or frame array */ | | 2236 | /* Unlink sitd from hardware chain, or frame array */ |
2234 | if (prev == NULL) { /* We're at the table head */ | | 2237 | if (prev == NULL) { /* We're at the table head */ |
2235 | sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; | | 2238 | sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; |
2236 | sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; | | 2239 | sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; |
2237 | usb_syncmem(&sc->sc_fldma, | | 2240 | usb_syncmem(&sc->sc_fldma, |
2238 | sizeof(ehci_link_t) * sitd->slot, | | 2241 | sizeof(ehci_link_t) * sitd->slot, |
2239 | sizeof(ehci_link_t), | | 2242 | sizeof(ehci_link_t), |
2240 | BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); | | 2243 | BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); |
2241 | | | 2244 | |
2242 | if (sitd->frame_list.next != NULL) | | 2245 | if (sitd->frame_list.next != NULL) |
2243 | sitd->frame_list.next->frame_list.prev = NULL; | | 2246 | sitd->frame_list.next->frame_list.prev = NULL; |
2244 | } else { | | 2247 | } else { |
2245 | /* XXX this part is untested... */ | | 2248 | /* XXX this part is untested... */ |
2246 | prev->sitd.sitd_next = sitd->sitd.sitd_next; | | 2249 | prev->sitd.sitd_next = sitd->sitd.sitd_next; |
2247 | usb_syncmem(&sitd->dma, | | 2250 | usb_syncmem(&sitd->dma, |
2248 | sitd->offs + offsetof(ehci_sitd_t, sitd_next), | | 2251 | sitd->offs + offsetof(ehci_sitd_t, sitd_next), |
2249 | sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); | | 2252 | sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); |
2250 | | | 2253 | |
2251 | prev->frame_list.next = sitd->frame_list.next; | | 2254 | prev->frame_list.next = sitd->frame_list.next; |
2252 | if (sitd->frame_list.next != NULL) | | 2255 | if (sitd->frame_list.next != NULL) |
2253 | sitd->frame_list.next->frame_list.prev = prev; | | 2256 | sitd->frame_list.next->frame_list.prev = prev; |
2254 | } | | 2257 | } |
2255 | } | | 2258 | } |
2256 | } | | 2259 | } |
2257 | | | 2260 | |
2258 | Static void | | 2261 | Static void |
2259 | ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) | | 2262 | ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) |
2260 | { | | 2263 | { |
2261 | | | 2264 | |
2262 | mutex_enter(&sc->sc_lock); | | 2265 | mutex_enter(&sc->sc_lock); |
2263 | struct ehci_soft_sitd *next = NULL; | | 2266 | struct ehci_soft_sitd *next = NULL; |
2264 | for (; sitd != NULL; sitd = next) { | | 2267 | for (; sitd != NULL; sitd = next) { |
2265 | next = sitd->xfer_next; | | 2268 | next = sitd->xfer_next; |
2266 | ehci_free_sitd_locked(sc, sitd); | | 2269 | ehci_free_sitd_locked(sc, sitd); |
2267 | } | | 2270 | } |
2268 | mutex_exit(&sc->sc_lock); | | 2271 | mutex_exit(&sc->sc_lock); |
2269 | } | | 2272 | } |
2270 | | | 2273 | |
2271 | /***********/ | | 2274 | /***********/ |
2272 | | | 2275 | |
2273 | Static int | | 2276 | Static int |
2274 | ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, | | 2277 | ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, |
2275 | void *buf, int buflen) | | 2278 | void *buf, int buflen) |
2276 | { | | 2279 | { |
2277 | ehci_softc_t *sc = EHCI_BUS2SC(bus); | | 2280 | ehci_softc_t *sc = EHCI_BUS2SC(bus); |
2278 | usb_hub_descriptor_t hubd; | | 2281 | usb_hub_descriptor_t hubd; |
2279 | usb_port_status_t ps; | | 2282 | usb_port_status_t ps; |
2280 | uint16_t len, value, index; | | 2283 | uint16_t len, value, index; |
2281 | int l, totlen = 0; | | 2284 | int l, totlen = 0; |
2282 | int port, i; | | 2285 | int port, i; |
2283 | uint32_t v; | | 2286 | uint32_t v; |
2284 | | | 2287 | |
2285 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 2288 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
2286 | | | 2289 | |
2287 | if (sc->sc_dying) | | 2290 | if (sc->sc_dying) |
2288 | return -1; | | 2291 | return -1; |
2289 | | | 2292 | |
2290 | DPRINTF("type=0x%02x request=%02x", req->bmRequestType, req->bRequest, | | 2293 | DPRINTF("type=0x%02x request=%02x", req->bmRequestType, req->bRequest, |
2291 | 0, 0); | | 2294 | 0, 0); |
2292 | | | 2295 | |
2293 | len = UGETW(req->wLength); | | 2296 | len = UGETW(req->wLength); |
2294 | value = UGETW(req->wValue); | | 2297 | value = UGETW(req->wValue); |
2295 | index = UGETW(req->wIndex); | | 2298 | index = UGETW(req->wIndex); |
2296 | | | 2299 | |
2297 | #define C(x,y) ((x) | ((y) << 8)) | | 2300 | #define C(x,y) ((x) | ((y) << 8)) |
2298 | switch (C(req->bRequest, req->bmRequestType)) { | | 2301 | switch (C(req->bRequest, req->bmRequestType)) { |
2299 | case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): | | 2302 | case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): |
2300 | if (len == 0) | | 2303 | if (len == 0) |
2301 | break; | | 2304 | break; |
2302 | switch (value) { | | 2305 | switch (value) { |
2303 | case C(0, UDESC_DEVICE): { | | 2306 | case C(0, UDESC_DEVICE): { |
2304 | usb_device_descriptor_t devd; | | 2307 | usb_device_descriptor_t devd; |
2305 | totlen = min(buflen, sizeof(devd)); | | 2308 | totlen = min(buflen, sizeof(devd)); |
2306 | memcpy(&devd, buf, totlen); | | 2309 | memcpy(&devd, buf, totlen); |
2307 | USETW(devd.idVendor, sc->sc_id_vendor); | | 2310 | USETW(devd.idVendor, sc->sc_id_vendor); |
2308 | memcpy(buf, &devd, totlen); | | 2311 | memcpy(buf, &devd, totlen); |
2309 | break; | | 2312 | break; |
2310 | | | 2313 | |
2311 | } | | 2314 | } |
2312 | #define sd ((usb_string_descriptor_t *)buf) | | 2315 | #define sd ((usb_string_descriptor_t *)buf) |
2313 | case C(1, UDESC_STRING): | | 2316 | case C(1, UDESC_STRING): |
2314 | /* Vendor */ | | 2317 | /* Vendor */ |
2315 | totlen = usb_makestrdesc(sd, len, sc->sc_vendor); | | 2318 | totlen = usb_makestrdesc(sd, len, sc->sc_vendor); |
2316 | break; | | 2319 | break; |
2317 | case C(2, UDESC_STRING): | | 2320 | case C(2, UDESC_STRING): |
2318 | /* Product */ | | 2321 | /* Product */ |
2319 | totlen = usb_makestrdesc(sd, len, "EHCI root hub"); | | 2322 | totlen = usb_makestrdesc(sd, len, "EHCI root hub"); |
2320 | break; | | 2323 | break; |
2321 | #undef sd | | 2324 | #undef sd |
2322 | default: | | 2325 | default: |
2323 | /* default from usbroothub */ | | 2326 | /* default from usbroothub */ |
2324 | return buflen; | | 2327 | return buflen; |
2325 | } | | 2328 | } |
2326 | break; | | 2329 | break; |
2327 | | | 2330 | |
2328 | /* Hub requests */ | | 2331 | /* Hub requests */ |
2329 | case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): | | 2332 | case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): |
2330 | break; | | 2333 | break; |
2331 | case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): | | 2334 | case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): |
2332 | DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, | | 2335 | DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, |
2333 | value, 0, 0); | | 2336 | value, 0, 0); |
2334 | if (index < 1 || index > sc->sc_noport) { | | 2337 | if (index < 1 || index > sc->sc_noport) { |
2335 | return -1; | | 2338 | return -1; |
2336 | } | | 2339 | } |
2337 | port = EHCI_PORTSC(index); | | 2340 | port = EHCI_PORTSC(index); |
2338 | v = EOREAD4(sc, port); | | 2341 | v = EOREAD4(sc, port); |
2339 | DPRINTF("portsc=0x%08x", v, 0, 0, 0); | | 2342 | DPRINTF("portsc=0x%08x", v, 0, 0, 0); |
2340 | v &= ~EHCI_PS_CLEAR; | | 2343 | v &= ~EHCI_PS_CLEAR; |
2341 | switch (value) { | | 2344 | switch (value) { |
2342 | case UHF_PORT_ENABLE: | | 2345 | case UHF_PORT_ENABLE: |
2343 | EOWRITE4(sc, port, v &~ EHCI_PS_PE); | | 2346 | EOWRITE4(sc, port, v &~ EHCI_PS_PE); |
2344 | break; | | 2347 | break; |
2345 | case UHF_PORT_SUSPEND: | | 2348 | case UHF_PORT_SUSPEND: |
2346 | if (!(v & EHCI_PS_SUSP)) /* not suspended */ | | 2349 | if (!(v & EHCI_PS_SUSP)) /* not suspended */ |
2347 | break; | | 2350 | break; |
2348 | v &= ~EHCI_PS_SUSP; | | 2351 | v &= ~EHCI_PS_SUSP; |
2349 | EOWRITE4(sc, port, v | EHCI_PS_FPR); | | 2352 | EOWRITE4(sc, port, v | EHCI_PS_FPR); |
2350 | /* see USB2 spec ch. 7.1.7.7 */ | | 2353 | /* see USB2 spec ch. 7.1.7.7 */ |
2351 | usb_delay_ms(&sc->sc_bus, 20); | | 2354 | usb_delay_ms(&sc->sc_bus, 20); |
2352 | EOWRITE4(sc, port, v); | | 2355 | EOWRITE4(sc, port, v); |
2353 | usb_delay_ms(&sc->sc_bus, 2); | | 2356 | usb_delay_ms(&sc->sc_bus, 2); |
2354 | #ifdef DEBUG | | 2357 | #ifdef DEBUG |
2355 | v = EOREAD4(sc, port); | | 2358 | v = EOREAD4(sc, port); |
2356 | if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) | | 2359 | if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) |
2357 | printf("ehci: resume failed: %x\n", v); | | 2360 | printf("ehci: resume failed: %x\n", v); |
2358 | #endif | | 2361 | #endif |
2359 | break; | | 2362 | break; |
2360 | case UHF_PORT_POWER: | | 2363 | case UHF_PORT_POWER: |
2361 | if (sc->sc_hasppc) | | 2364 | if (sc->sc_hasppc) |
2362 | EOWRITE4(sc, port, v &~ EHCI_PS_PP); | | 2365 | EOWRITE4(sc, port, v &~ EHCI_PS_PP); |
2363 | break; | | 2366 | break; |
2364 | case UHF_PORT_TEST: | | 2367 | case UHF_PORT_TEST: |
2365 | DPRINTF("clear port test %d", index, 0, 0, 0); | | 2368 | DPRINTF("clear port test %d", index, 0, 0, 0); |
2366 | break; | | 2369 | break; |
2367 | case UHF_PORT_INDICATOR: | | 2370 | case UHF_PORT_INDICATOR: |
2368 | DPRINTF("clear port ind %d", index, 0, 0, 0); | | 2371 | DPRINTF("clear port ind %d", index, 0, 0, 0); |
2369 | EOWRITE4(sc, port, v &~ EHCI_PS_PIC); | | 2372 | EOWRITE4(sc, port, v &~ EHCI_PS_PIC); |
2370 | break; | | 2373 | break; |
2371 | case UHF_C_PORT_CONNECTION: | | 2374 | case UHF_C_PORT_CONNECTION: |
2372 | EOWRITE4(sc, port, v | EHCI_PS_CSC); | | 2375 | EOWRITE4(sc, port, v | EHCI_PS_CSC); |
2373 | break; | | 2376 | break; |
2374 | case UHF_C_PORT_ENABLE: | | 2377 | case UHF_C_PORT_ENABLE: |
2375 | EOWRITE4(sc, port, v | EHCI_PS_PEC); | | 2378 | EOWRITE4(sc, port, v | EHCI_PS_PEC); |
2376 | break; | | 2379 | break; |
2377 | case UHF_C_PORT_SUSPEND: | | 2380 | case UHF_C_PORT_SUSPEND: |
2378 | /* how? */ | | 2381 | /* how? */ |
2379 | break; | | 2382 | break; |
2380 | case UHF_C_PORT_OVER_CURRENT: | | 2383 | case UHF_C_PORT_OVER_CURRENT: |
2381 | EOWRITE4(sc, port, v | EHCI_PS_OCC); | | 2384 | EOWRITE4(sc, port, v | EHCI_PS_OCC); |
2382 | break; | | 2385 | break; |
2383 | case UHF_C_PORT_RESET: | | 2386 | case UHF_C_PORT_RESET: |
2384 | sc->sc_isreset[index] = 0; | | 2387 | sc->sc_isreset[index] = 0; |
2385 | break; | | 2388 | break; |
2386 | default: | | 2389 | default: |
2387 | return -1; | | 2390 | return -1; |
2388 | } | | 2391 | } |
2389 | #if 0 | | 2392 | #if 0 |
2390 | switch(value) { | | 2393 | switch(value) { |
2391 | case UHF_C_PORT_CONNECTION: | | 2394 | case UHF_C_PORT_CONNECTION: |
2392 | case UHF_C_PORT_ENABLE: | | 2395 | case UHF_C_PORT_ENABLE: |
2393 | case UHF_C_PORT_SUSPEND: | | 2396 | case UHF_C_PORT_SUSPEND: |
2394 | case UHF_C_PORT_OVER_CURRENT: | | 2397 | case UHF_C_PORT_OVER_CURRENT: |
2395 | case UHF_C_PORT_RESET: | | 2398 | case UHF_C_PORT_RESET: |
2396 | default: | | 2399 | default: |
2397 | break; | | 2400 | break; |
2398 | } | | 2401 | } |
2399 | #endif | | 2402 | #endif |
2400 | break; | | 2403 | break; |
2401 | case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): | | 2404 | case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): |
2402 | if (len == 0) | | 2405 | if (len == 0) |
2403 | break; | | 2406 | break; |
2404 | if ((value & 0xff) != 0) { | | 2407 | if ((value & 0xff) != 0) { |
2405 | return -1; | | 2408 | return -1; |
2406 | } | | 2409 | } |
2407 | totlen = min(buflen, sizeof(hubd)); | | 2410 | totlen = min(buflen, sizeof(hubd)); |
2408 | memcpy(&hubd, buf, totlen); | | 2411 | memcpy(&hubd, buf, totlen); |
2409 | hubd.bNbrPorts = sc->sc_noport; | | 2412 | hubd.bNbrPorts = sc->sc_noport; |
2410 | v = EOREAD4(sc, EHCI_HCSPARAMS); | | 2413 | v = EOREAD4(sc, EHCI_HCSPARAMS); |
2411 | USETW(hubd.wHubCharacteristics, | | 2414 | USETW(hubd.wHubCharacteristics, |
2412 | EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | | | 2415 | EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | |
2413 | EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) | | 2416 | EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) |
2414 | ? UHD_PORT_IND : 0); | | 2417 | ? UHD_PORT_IND : 0); |
2415 | hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ | | 2418 | hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ |
2416 | for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) | | 2419 | for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) |
2417 | hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ | | 2420 | hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ |
2418 | hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; | | 2421 | hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; |
2419 | totlen = min(totlen, hubd.bDescLength); | | 2422 | totlen = min(totlen, hubd.bDescLength); |
2420 | memcpy(buf, &hubd, totlen); | | 2423 | memcpy(buf, &hubd, totlen); |
2421 | break; | | 2424 | break; |
2422 | case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): | | 2425 | case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): |
2423 | if (len != 4) { | | 2426 | if (len != 4) { |
2424 | return -1; | | 2427 | return -1; |
2425 | } | | 2428 | } |
2426 | memset(buf, 0, len); /* ? XXX */ | | 2429 | memset(buf, 0, len); /* ? XXX */ |
2427 | totlen = len; | | 2430 | totlen = len; |
2428 | break; | | 2431 | break; |
2429 | case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): | | 2432 | case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): |
2430 | DPRINTF("get port status i=%d", index, 0, 0, 0); | | 2433 | DPRINTF("get port status i=%d", index, 0, 0, 0); |
2431 | if (index < 1 || index > sc->sc_noport) { | | 2434 | if (index < 1 || index > sc->sc_noport) { |
2432 | return -1; | | 2435 | return -1; |
2433 | } | | 2436 | } |
2434 | if (len != 4) { | | 2437 | if (len != 4) { |
2435 | return -1; | | 2438 | return -1; |
2436 | } | | 2439 | } |
2437 | v = EOREAD4(sc, EHCI_PORTSC(index)); | | 2440 | v = EOREAD4(sc, EHCI_PORTSC(index)); |
2438 | DPRINTF("port status=0x%04x", v, 0, 0, 0); | | 2441 | DPRINTF("port status=0x%04x", v, 0, 0, 0); |
2439 | | | 2442 | |
2440 | i = UPS_HIGH_SPEED; | | 2443 | i = UPS_HIGH_SPEED; |
2441 | if (sc->sc_flags & EHCIF_ETTF) { | | 2444 | if (sc->sc_flags & EHCIF_ETTF) { |
2442 | /* | | 2445 | /* |
2443 | * If we are doing embedded transaction translation, | | 2446 | * If we are doing embedded transaction translation, |
2444 | * then directly attached LS/FS devices are reset by | | 2447 | * then directly attached LS/FS devices are reset by |
2445 | * the EHCI controller itself. PSPD is encoded | | 2448 | * the EHCI controller itself. PSPD is encoded |
2446 | * the same way as in USBSTATUS. | | 2449 | * the same way as in USBSTATUS. |
2447 | */ | | 2450 | */ |
2448 | i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; | | 2451 | i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; |
2449 | } | | 2452 | } |
2450 | if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; | | 2453 | if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; |
2451 | if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; | | 2454 | if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; |
2452 | if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; | | 2455 | if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; |
2453 | if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; | | 2456 | if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; |
2454 | if (v & EHCI_PS_PR) i |= UPS_RESET; | | 2457 | if (v & EHCI_PS_PR) i |= UPS_RESET; |
2455 | if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; | | 2458 | if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; |
2456 | if (sc->sc_vendor_port_status) | | 2459 | if (sc->sc_vendor_port_status) |
2457 | i = sc->sc_vendor_port_status(sc, v, i); | | 2460 | i = sc->sc_vendor_port_status(sc, v, i); |
2458 | USETW(ps.wPortStatus, i); | | 2461 | USETW(ps.wPortStatus, i); |
2459 | i = 0; | | 2462 | i = 0; |
2460 | if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; | | 2463 | if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; |
2461 | if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; | | 2464 | if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; |
2462 | if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; | | 2465 | if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; |
2463 | if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; | | 2466 | if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; |
2464 | USETW(ps.wPortChange, i); | | 2467 | USETW(ps.wPortChange, i); |
2465 | totlen = min(len, sizeof(ps)); | | 2468 | totlen = min(len, sizeof(ps)); |
2466 | memcpy(buf, &ps, totlen); | | 2469 | memcpy(buf, &ps, totlen); |
2467 | break; | | 2470 | break; |
2468 | case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): | | 2471 | case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): |
2469 | return -1; | | 2472 | return -1; |
2470 | case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): | | 2473 | case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): |
2471 | break; | | 2474 | break; |
2472 | case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): | | 2475 | case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): |
2473 | if (index < 1 || index > sc->sc_noport) { | | 2476 | if (index < 1 || index > sc->sc_noport) { |
2474 | return -1; | | 2477 | return -1; |
2475 | } | | 2478 | } |
2476 | port = EHCI_PORTSC(index); | | 2479 | port = EHCI_PORTSC(index); |
2477 | v = EOREAD4(sc, port); | | 2480 | v = EOREAD4(sc, port); |
2478 | DPRINTF("portsc=0x%08x", v, 0, 0, 0); | | 2481 | DPRINTF("portsc=0x%08x", v, 0, 0, 0); |
2479 | v &= ~EHCI_PS_CLEAR; | | 2482 | v &= ~EHCI_PS_CLEAR; |
2480 | switch(value) { | | 2483 | switch(value) { |
2481 | case UHF_PORT_ENABLE: | | 2484 | case UHF_PORT_ENABLE: |
2482 | EOWRITE4(sc, port, v | EHCI_PS_PE); | | 2485 | EOWRITE4(sc, port, v | EHCI_PS_PE); |
2483 | break; | | 2486 | break; |
2484 | case UHF_PORT_SUSPEND: | | 2487 | case UHF_PORT_SUSPEND: |
2485 | EOWRITE4(sc, port, v | EHCI_PS_SUSP); | | 2488 | EOWRITE4(sc, port, v | EHCI_PS_SUSP); |
2486 | break; | | 2489 | break; |
2487 | case UHF_PORT_RESET: | | 2490 | case UHF_PORT_RESET: |
2488 | DPRINTF("reset port %d", index, 0, 0, 0); | | 2491 | DPRINTF("reset port %d", index, 0, 0, 0); |
2489 | if (EHCI_PS_IS_LOWSPEED(v) | | 2492 | if (EHCI_PS_IS_LOWSPEED(v) |
2490 | && sc->sc_ncomp > 0 | | 2493 | && sc->sc_ncomp > 0 |
2491 | && !(sc->sc_flags & EHCIF_ETTF)) { | | 2494 | && !(sc->sc_flags & EHCIF_ETTF)) { |
2492 | /* | | 2495 | /* |
2493 | * Low speed device on non-ETTF controller or | | 2496 | * Low speed device on non-ETTF controller or |
2494 | * unaccompanied controller, give up ownership. | | 2497 | * unaccompanied controller, give up ownership. |
2495 | */ | | 2498 | */ |
2496 | ehci_disown(sc, index, 1); | | 2499 | ehci_disown(sc, index, 1); |
2497 | break; | | 2500 | break; |
2498 | } | | 2501 | } |
2499 | /* Start reset sequence. */ | | 2502 | /* Start reset sequence. */ |
2500 | v &= ~ (EHCI_PS_PE | EHCI_PS_PR); | | 2503 | v &= ~ (EHCI_PS_PE | EHCI_PS_PR); |
2501 | EOWRITE4(sc, port, v | EHCI_PS_PR); | | 2504 | EOWRITE4(sc, port, v | EHCI_PS_PR); |
2502 | /* Wait for reset to complete. */ | | 2505 | /* Wait for reset to complete. */ |
2503 | usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); | | 2506 | usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); |
2504 | if (sc->sc_dying) { | | 2507 | if (sc->sc_dying) { |
2505 | return -1; | | 2508 | return -1; |
2506 | } | | 2509 | } |
2507 | /* | | 2510 | /* |
2508 | * An embedded transaction translator will automatically | | 2511 | * An embedded transaction translator will automatically |
2509 | * terminate the reset sequence so there's no need to | | 2512 | * terminate the reset sequence so there's no need to |
2510 | * it. | | 2513 | * it. |
2511 | */ | | 2514 | */ |
2512 | v = EOREAD4(sc, port); | | 2515 | v = EOREAD4(sc, port); |
2513 | if (v & EHCI_PS_PR) { | | 2516 | if (v & EHCI_PS_PR) { |
2514 | /* Terminate reset sequence. */ | | 2517 | /* Terminate reset sequence. */ |
2515 | EOWRITE4(sc, port, v & ~EHCI_PS_PR); | | 2518 | EOWRITE4(sc, port, v & ~EHCI_PS_PR); |
2516 | /* Wait for HC to complete reset. */ | | 2519 | /* Wait for HC to complete reset. */ |
2517 | usb_delay_ms(&sc->sc_bus, | | 2520 | usb_delay_ms(&sc->sc_bus, |
2518 | EHCI_PORT_RESET_COMPLETE); | | 2521 | EHCI_PORT_RESET_COMPLETE); |
2519 | if (sc->sc_dying) { | | 2522 | if (sc->sc_dying) { |
2520 | return -1; | | 2523 | return -1; |
2521 | } | | 2524 | } |
2522 | } | | 2525 | } |
2523 | | | 2526 | |
2524 | v = EOREAD4(sc, port); | | 2527 | v = EOREAD4(sc, port); |
2525 | DPRINTF("ehci after reset, status=0x%08x", v, 0, 0, 0); | | 2528 | DPRINTF("ehci after reset, status=0x%08x", v, 0, 0, 0); |
2526 | if (v & EHCI_PS_PR) { | | 2529 | if (v & EHCI_PS_PR) { |
2527 | printf("%s: port reset timeout\n", | | 2530 | printf("%s: port reset timeout\n", |
2528 | device_xname(sc->sc_dev)); | | 2531 | device_xname(sc->sc_dev)); |
2529 | return USBD_TIMEOUT; | | 2532 | return USBD_TIMEOUT; |
2530 | } | | 2533 | } |
2531 | if (!(v & EHCI_PS_PE)) { | | 2534 | if (!(v & EHCI_PS_PE)) { |
2532 | /* Not a high speed device, give up ownership.*/ | | 2535 | /* Not a high speed device, give up ownership.*/ |
2533 | ehci_disown(sc, index, 0); | | 2536 | ehci_disown(sc, index, 0); |
2534 | break; | | 2537 | break; |
2535 | } | | 2538 | } |
2536 | sc->sc_isreset[index] = 1; | | 2539 | sc->sc_isreset[index] = 1; |
2537 | DPRINTF("ehci port %d reset, status = 0x%08x", index, | | 2540 | DPRINTF("ehci port %d reset, status = 0x%08x", index, |
2538 | v, 0, 0); | | 2541 | v, 0, 0); |
2539 | break; | | 2542 | break; |
2540 | case UHF_PORT_POWER: | | 2543 | case UHF_PORT_POWER: |
2541 | DPRINTF("set port power %d (has PPC = %d)", index, | | 2544 | DPRINTF("set port power %d (has PPC = %d)", index, |
2542 | sc->sc_hasppc, 0, 0); | | 2545 | sc->sc_hasppc, 0, 0); |
2543 | if (sc->sc_hasppc) | | 2546 | if (sc->sc_hasppc) |
2544 | EOWRITE4(sc, port, v | EHCI_PS_PP); | | 2547 | EOWRITE4(sc, port, v | EHCI_PS_PP); |
2545 | break; | | 2548 | break; |
2546 | case UHF_PORT_TEST: | | 2549 | case UHF_PORT_TEST: |
2547 | DPRINTF("set port test %d", index, 0, 0, 0); | | 2550 | DPRINTF("set port test %d", index, 0, 0, 0); |
2548 | break; | | 2551 | break; |
2549 | case UHF_PORT_INDICATOR: | | 2552 | case UHF_PORT_INDICATOR: |
2550 | DPRINTF("set port ind %d", index, 0, 0, 0); | | 2553 | DPRINTF("set port ind %d", index, 0, 0, 0); |
2551 | EOWRITE4(sc, port, v | EHCI_PS_PIC); | | 2554 | EOWRITE4(sc, port, v | EHCI_PS_PIC); |
2552 | break; | | 2555 | break; |
2553 | default: | | 2556 | default: |
2554 | return -1; | | 2557 | return -1; |
2555 | } | | 2558 | } |
2556 | break; | | 2559 | break; |
2557 | case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): | | 2560 | case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): |
2558 | case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): | | 2561 | case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): |
2559 | case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): | | 2562 | case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): |
2560 | case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): | | 2563 | case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): |
2561 | break; | | 2564 | break; |
2562 | default: | | 2565 | default: |
2563 | /* default from usbroothub */ | | 2566 | /* default from usbroothub */ |
2564 | DPRINTF("returning %d (usbroothub default)", buflen, 0, 0, 0); | | 2567 | DPRINTF("returning %d (usbroothub default)", buflen, 0, 0, 0); |
2565 | | | 2568 | |
2566 | return buflen; | | 2569 | return buflen; |
2567 | } | | 2570 | } |
2568 | | | 2571 | |
2569 | DPRINTF("returning %d", totlen, 0, 0, 0); | | 2572 | DPRINTF("returning %d", totlen, 0, 0, 0); |
2570 | | | 2573 | |
2571 | return totlen; | | 2574 | return totlen; |
2572 | } | | 2575 | } |
2573 | | | 2576 | |
2574 | Static void | | 2577 | Static void |
2575 | ehci_disown(ehci_softc_t *sc, int index, int lowspeed) | | 2578 | ehci_disown(ehci_softc_t *sc, int index, int lowspeed) |
2576 | { | | 2579 | { |
2577 | int port; | | 2580 | int port; |
2578 | uint32_t v; | | 2581 | uint32_t v; |
2579 | | | 2582 | |
2580 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 2583 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
2581 | | | 2584 | |
2582 | DPRINTF("index=%d lowspeed=%d", index, lowspeed, 0, 0); | | 2585 | DPRINTF("index=%d lowspeed=%d", index, lowspeed, 0, 0); |
2583 | #ifdef DIAGNOSTIC | | 2586 | #ifdef DIAGNOSTIC |
2584 | if (sc->sc_npcomp != 0) { | | 2587 | if (sc->sc_npcomp != 0) { |
2585 | int i = (index-1) / sc->sc_npcomp; | | 2588 | int i = (index-1) / sc->sc_npcomp; |
2586 | if (i >= sc->sc_ncomp) | | 2589 | if (i >= sc->sc_ncomp) |
2587 | printf("%s: strange port\n", | | 2590 | printf("%s: strange port\n", |
2588 | device_xname(sc->sc_dev)); | | 2591 | device_xname(sc->sc_dev)); |
2589 | else | | 2592 | else |
2590 | printf("%s: handing over %s speed device on " | | 2593 | printf("%s: handing over %s speed device on " |
2591 | "port %d to %s\n", | | 2594 | "port %d to %s\n", |
2592 | device_xname(sc->sc_dev), | | 2595 | device_xname(sc->sc_dev), |
2593 | lowspeed ? "low" : "full", | | 2596 | lowspeed ? "low" : "full", |
2594 | index, device_xname(sc->sc_comps[i])); | | 2597 | index, device_xname(sc->sc_comps[i])); |
2595 | } else { | | 2598 | } else { |
2596 | printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); | | 2599 | printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); |
2597 | } | | 2600 | } |
2598 | #endif | | 2601 | #endif |
2599 | port = EHCI_PORTSC(index); | | 2602 | port = EHCI_PORTSC(index); |
2600 | v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; | | 2603 | v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; |
2601 | EOWRITE4(sc, port, v | EHCI_PS_PO); | | 2604 | EOWRITE4(sc, port, v | EHCI_PS_PO); |
2602 | } | | 2605 | } |
2603 | | | 2606 | |
2604 | Static usbd_status | | 2607 | Static usbd_status |
2605 | ehci_root_intr_transfer(struct usbd_xfer *xfer) | | 2608 | ehci_root_intr_transfer(struct usbd_xfer *xfer) |
2606 | { | | 2609 | { |
2607 | ehci_softc_t *sc = EHCI_XFER2SC(xfer); | | 2610 | ehci_softc_t *sc = EHCI_XFER2SC(xfer); |
2608 | usbd_status err; | | 2611 | usbd_status err; |
2609 | | | 2612 | |
2610 | /* Insert last in queue. */ | | 2613 | /* Insert last in queue. */ |
2611 | mutex_enter(&sc->sc_lock); | | 2614 | mutex_enter(&sc->sc_lock); |
2612 | err = usb_insert_transfer(xfer); | | 2615 | err = usb_insert_transfer(xfer); |
2613 | mutex_exit(&sc->sc_lock); | | 2616 | mutex_exit(&sc->sc_lock); |
2614 | if (err) | | 2617 | if (err) |
2615 | return err; | | 2618 | return err; |
2616 | | | 2619 | |
2617 | /* Pipe isn't running, start first */ | | 2620 | /* Pipe isn't running, start first */ |
2618 | return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); | | 2621 | return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); |
2619 | } | | 2622 | } |
2620 | | | 2623 | |
2621 | Static usbd_status | | 2624 | Static usbd_status |
2622 | ehci_root_intr_start(struct usbd_xfer *xfer) | | 2625 | ehci_root_intr_start(struct usbd_xfer *xfer) |
2623 | { | | 2626 | { |
2624 | ehci_softc_t *sc = EHCI_XFER2SC(xfer); | | 2627 | ehci_softc_t *sc = EHCI_XFER2SC(xfer); |
2625 | | | 2628 | |
2626 | if (sc->sc_dying) | | 2629 | if (sc->sc_dying) |
2627 | return USBD_IOERROR; | | 2630 | return USBD_IOERROR; |
2628 | | | 2631 | |
2629 | mutex_enter(&sc->sc_lock); | | 2632 | mutex_enter(&sc->sc_lock); |
2630 | sc->sc_intrxfer = xfer; | | 2633 | sc->sc_intrxfer = xfer; |
2631 | mutex_exit(&sc->sc_lock); | | 2634 | mutex_exit(&sc->sc_lock); |
2632 | | | 2635 | |
2633 | return USBD_IN_PROGRESS; | | 2636 | return USBD_IN_PROGRESS; |
2634 | } | | 2637 | } |
2635 | | | 2638 | |
2636 | /* Abort a root interrupt request. */ | | 2639 | /* Abort a root interrupt request. */ |
2637 | Static void | | 2640 | Static void |
2638 | ehci_root_intr_abort(struct usbd_xfer *xfer) | | 2641 | ehci_root_intr_abort(struct usbd_xfer *xfer) |
2639 | { | | 2642 | { |
2640 | ehci_softc_t *sc = EHCI_XFER2SC(xfer); | | 2643 | ehci_softc_t *sc = EHCI_XFER2SC(xfer); |
2641 | | | 2644 | |
2642 | KASSERT(mutex_owned(&sc->sc_lock)); | | 2645 | KASSERT(mutex_owned(&sc->sc_lock)); |
2643 | KASSERT(xfer->ux_pipe->up_intrxfer == xfer); | | 2646 | KASSERT(xfer->ux_pipe->up_intrxfer == xfer); |
2644 | | | 2647 | |
2645 | sc->sc_intrxfer = NULL; | | 2648 | sc->sc_intrxfer = NULL; |
2646 | | | 2649 | |
2647 | xfer->ux_status = USBD_CANCELLED; | | 2650 | xfer->ux_status = USBD_CANCELLED; |
2648 | usb_transfer_complete(xfer); | | 2651 | usb_transfer_complete(xfer); |
2649 | } | | 2652 | } |
2650 | | | 2653 | |
2651 | /* Close the root pipe. */ | | 2654 | /* Close the root pipe. */ |
2652 | Static void | | 2655 | Static void |
2653 | ehci_root_intr_close(struct usbd_pipe *pipe) | | 2656 | ehci_root_intr_close(struct usbd_pipe *pipe) |
2654 | { | | 2657 | { |
2655 | ehci_softc_t *sc = EHCI_PIPE2SC(pipe); | | 2658 | ehci_softc_t *sc = EHCI_PIPE2SC(pipe); |
2656 | | | 2659 | |
2657 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 2660 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
2658 | | | 2661 | |
2659 | KASSERT(mutex_owned(&sc->sc_lock)); | | 2662 | KASSERT(mutex_owned(&sc->sc_lock)); |
2660 | | | 2663 | |
2661 | sc->sc_intrxfer = NULL; | | 2664 | sc->sc_intrxfer = NULL; |
2662 | } | | 2665 | } |
2663 | | | 2666 | |
2664 | Static void | | 2667 | Static void |
2665 | ehci_root_intr_done(struct usbd_xfer *xfer) | | 2668 | ehci_root_intr_done(struct usbd_xfer *xfer) |
2666 | { | | 2669 | { |
2667 | } | | 2670 | } |
2668 | | | 2671 | |
2669 | /************************/ | | 2672 | /************************/ |
2670 | | | 2673 | |
2671 | Static ehci_soft_qh_t * | | 2674 | Static ehci_soft_qh_t * |
2672 | ehci_alloc_sqh(ehci_softc_t *sc) | | 2675 | ehci_alloc_sqh(ehci_softc_t *sc) |
2673 | { | | 2676 | { |
2674 | ehci_soft_qh_t *sqh; | | 2677 | ehci_soft_qh_t *sqh; |
2675 | usbd_status err; | | 2678 | usbd_status err; |
2676 | int i, offs; | | 2679 | int i, offs; |
2677 | usb_dma_t dma; | | 2680 | usb_dma_t dma; |
2678 | | | 2681 | |
2679 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 2682 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
2680 | | | 2683 | |
2681 | mutex_enter(&sc->sc_lock); | | 2684 | mutex_enter(&sc->sc_lock); |
2682 | if (sc->sc_freeqhs == NULL) { | | 2685 | if (sc->sc_freeqhs == NULL) { |
2683 | DPRINTF("allocating chunk", 0, 0, 0, 0); | | 2686 | DPRINTF("allocating chunk", 0, 0, 0, 0); |
2684 | mutex_exit(&sc->sc_lock); | | 2687 | mutex_exit(&sc->sc_lock); |
2685 | | | 2688 | |
2686 | err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, | | 2689 | err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, |
2687 | EHCI_PAGE_SIZE, &dma); | | 2690 | EHCI_PAGE_SIZE, &dma); |
2688 | #ifdef EHCI_DEBUG | | 2691 | #ifdef EHCI_DEBUG |
2689 | if (err) | | 2692 | if (err) |
2690 | printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); | | 2693 | printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); |
2691 | #endif | | 2694 | #endif |
2692 | if (err) | | 2695 | if (err) |
2693 | return NULL; | | 2696 | return NULL; |
2694 | | | 2697 | |
2695 | mutex_enter(&sc->sc_lock); | | 2698 | mutex_enter(&sc->sc_lock); |
2696 | for (i = 0; i < EHCI_SQH_CHUNK; i++) { | | 2699 | for (i = 0; i < EHCI_SQH_CHUNK; i++) { |
2697 | offs = i * EHCI_SQH_SIZE; | | 2700 | offs = i * EHCI_SQH_SIZE; |
2698 | sqh = KERNADDR(&dma, offs); | | 2701 | sqh = KERNADDR(&dma, offs); |
2699 | sqh->physaddr = DMAADDR(&dma, offs); | | 2702 | sqh->physaddr = DMAADDR(&dma, offs); |
2700 | sqh->dma = dma; | | 2703 | sqh->dma = dma; |
2701 | sqh->offs = offs; | | 2704 | sqh->offs = offs; |
2702 | sqh->next = sc->sc_freeqhs; | | 2705 | sqh->next = sc->sc_freeqhs; |
2703 | sc->sc_freeqhs = sqh; | | 2706 | sc->sc_freeqhs = sqh; |
2704 | } | | 2707 | } |
2705 | } | | 2708 | } |
2706 | sqh = sc->sc_freeqhs; | | 2709 | sqh = sc->sc_freeqhs; |
2707 | sc->sc_freeqhs = sqh->next; | | 2710 | sc->sc_freeqhs = sqh->next; |
2708 | mutex_exit(&sc->sc_lock); | | 2711 | mutex_exit(&sc->sc_lock); |
2709 | | | 2712 | |
2710 | memset(&sqh->qh, 0, sizeof(ehci_qh_t)); | | 2713 | memset(&sqh->qh, 0, sizeof(ehci_qh_t)); |
2711 | sqh->next = NULL; | | 2714 | sqh->next = NULL; |
2712 | return sqh; | | 2715 | return sqh; |
2713 | } | | 2716 | } |
2714 | | | 2717 | |
2715 | Static void | | 2718 | Static void |
2716 | ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) | | 2719 | ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) |
2717 | { | | 2720 | { |
2718 | KASSERT(mutex_owned(&sc->sc_lock)); | | 2721 | KASSERT(mutex_owned(&sc->sc_lock)); |
2719 | | | 2722 | |
2720 | sqh->next = sc->sc_freeqhs; | | 2723 | sqh->next = sc->sc_freeqhs; |
2721 | sc->sc_freeqhs = sqh; | | 2724 | sc->sc_freeqhs = sqh; |
2722 | } | | 2725 | } |
2723 | | | 2726 | |
2724 | Static ehci_soft_qtd_t * | | 2727 | Static ehci_soft_qtd_t * |
2725 | ehci_alloc_sqtd(ehci_softc_t *sc) | | 2728 | ehci_alloc_sqtd(ehci_softc_t *sc) |
2726 | { | | 2729 | { |
2727 | ehci_soft_qtd_t *sqtd = NULL; | | 2730 | ehci_soft_qtd_t *sqtd = NULL; |
2728 | usbd_status err; | | 2731 | usbd_status err; |
2729 | int i, offs; | | 2732 | int i, offs; |
2730 | usb_dma_t dma; | | 2733 | usb_dma_t dma; |
2731 | | | 2734 | |
2732 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 2735 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
2733 | | | 2736 | |
2734 | mutex_enter(&sc->sc_lock); | | 2737 | mutex_enter(&sc->sc_lock); |
2735 | if (sc->sc_freeqtds == NULL) { | | 2738 | if (sc->sc_freeqtds == NULL) { |
2736 | DPRINTF("allocating chunk", 0, 0, 0, 0); | | 2739 | DPRINTF("allocating chunk", 0, 0, 0, 0); |
2737 | mutex_exit(&sc->sc_lock); | | 2740 | mutex_exit(&sc->sc_lock); |
2738 | | | 2741 | |
2739 | err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, | | 2742 | err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, |
2740 | EHCI_PAGE_SIZE, &dma); | | 2743 | EHCI_PAGE_SIZE, &dma); |
2741 | #ifdef EHCI_DEBUG | | 2744 | #ifdef EHCI_DEBUG |
2742 | if (err) | | 2745 | if (err) |
2743 | printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); | | 2746 | printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); |
2744 | #endif | | 2747 | #endif |
2745 | if (err) | | 2748 | if (err) |
2746 | goto done; | | 2749 | goto done; |
2747 | | | 2750 | |
2748 | mutex_enter(&sc->sc_lock); | | 2751 | mutex_enter(&sc->sc_lock); |
2749 | for (i = 0; i < EHCI_SQTD_CHUNK; i++) { | | 2752 | for (i = 0; i < EHCI_SQTD_CHUNK; i++) { |
2750 | offs = i * EHCI_SQTD_SIZE; | | 2753 | offs = i * EHCI_SQTD_SIZE; |
2751 | sqtd = KERNADDR(&dma, offs); | | 2754 | sqtd = KERNADDR(&dma, offs); |
2752 | sqtd->physaddr = DMAADDR(&dma, offs); | | 2755 | sqtd->physaddr = DMAADDR(&dma, offs); |
2753 | sqtd->dma = dma; | | 2756 | sqtd->dma = dma; |
2754 | sqtd->offs = offs; | | 2757 | sqtd->offs = offs; |
2755 | | | 2758 | |
2756 | sqtd->nextqtd = sc->sc_freeqtds; | | 2759 | sqtd->nextqtd = sc->sc_freeqtds; |
2757 | sc->sc_freeqtds = sqtd; | | 2760 | sc->sc_freeqtds = sqtd; |
2758 | } | | 2761 | } |
2759 | } | | 2762 | } |
2760 | | | 2763 | |
2761 | sqtd = sc->sc_freeqtds; | | 2764 | sqtd = sc->sc_freeqtds; |
2762 | sc->sc_freeqtds = sqtd->nextqtd; | | 2765 | sc->sc_freeqtds = sqtd->nextqtd; |
2763 | mutex_exit(&sc->sc_lock); | | 2766 | mutex_exit(&sc->sc_lock); |
2764 | | | 2767 | |
2765 | memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); | | 2768 | memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); |
2766 | sqtd->nextqtd = NULL; | | 2769 | sqtd->nextqtd = NULL; |
2767 | sqtd->xfer = NULL; | | 2770 | sqtd->xfer = NULL; |
2768 | | | 2771 | |
2769 | done: | | 2772 | done: |
2770 | return sqtd; | | 2773 | return sqtd; |
2771 | } | | 2774 | } |
2772 | | | 2775 | |
2773 | Static void | | 2776 | Static void |
2774 | ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) | | 2777 | ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) |
2775 | { | | 2778 | { |
2776 | | | 2779 | |
2777 | mutex_enter(&sc->sc_lock); | | 2780 | mutex_enter(&sc->sc_lock); |
2778 | sqtd->nextqtd = sc->sc_freeqtds; | | 2781 | sqtd->nextqtd = sc->sc_freeqtds; |
2779 | sc->sc_freeqtds = sqtd; | | 2782 | sc->sc_freeqtds = sqtd; |
2780 | mutex_exit(&sc->sc_lock); | | 2783 | mutex_exit(&sc->sc_lock); |
2781 | } | | 2784 | } |
2782 | | | 2785 | |
2783 | Static int | | 2786 | Static int |
2784 | ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, | | 2787 | ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, |
2785 | int alen, int rd, ehci_soft_qtd_t **sp) | | 2788 | int alen, int rd, ehci_soft_qtd_t **sp) |
2786 | { | | 2789 | { |
2787 | struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); | | 2790 | struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); |
2788 | uint16_t flags = xfer->ux_flags; | | 2791 | uint16_t flags = xfer->ux_flags; |
2789 | | | 2792 | |
2790 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 2793 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
2791 | | | 2794 | |
2792 | ASSERT_SLEEPABLE(); | | 2795 | ASSERT_SLEEPABLE(); |
2793 | KASSERT(sp); | | 2796 | KASSERT(sp); |
2794 | KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); | | 2797 | KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); |
2795 | | | 2798 | |
2796 | size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; | | 2799 | size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; |
2797 | nsqtd += ((alen + EHCI_PAGE_SIZE - 1) / EHCI_PAGE_SIZE); | | 2800 | nsqtd += ((alen + EHCI_PAGE_SIZE - 1) / EHCI_PAGE_SIZE); |
2798 | exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, | | 2801 | exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, |
2799 | KM_SLEEP); | | 2802 | KM_SLEEP); |
2800 | exfer->ex_nsqtd = nsqtd; | | 2803 | exfer->ex_nsqtd = nsqtd; |
2801 | | | 2804 | |
2802 | DPRINTF("xfer %p len %d nsqtd %d flags %x", xfer, alen, nsqtd, flags); | | 2805 | DPRINTF("xfer %p len %d nsqtd %d flags %x", xfer, alen, nsqtd, flags); |
2803 | | | 2806 | |
2804 | for (size_t j = 0; j < exfer->ex_nsqtd;) { | | 2807 | for (size_t j = 0; j < exfer->ex_nsqtd;) { |
2805 | ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc); | | 2808 | ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc); |
2806 | if (cur == NULL) | | 2809 | if (cur == NULL) |
2807 | goto nomem; | | 2810 | goto nomem; |
2808 | exfer->ex_sqtds[j++] = cur; | | 2811 | exfer->ex_sqtds[j++] = cur; |
2809 | | | 2812 | |
2810 | cur->xfer = xfer; | | 2813 | cur->xfer = xfer; |
2811 | cur->len = 0; | | 2814 | cur->len = 0; |
2812 | | | 2815 | |
2813 | } | | 2816 | } |
2814 | | | 2817 | |
2815 | *sp = exfer->ex_sqtds[0]; | | 2818 | *sp = exfer->ex_sqtds[0]; |
2816 | DPRINTF("return sqtd=%p", *sp, 0, 0, 0); | | 2819 | DPRINTF("return sqtd=%p", *sp, 0, 0, 0); |
2817 | | | 2820 | |
2818 | return 0; | | 2821 | return 0; |
2819 | | | 2822 | |
2820 | nomem: | | 2823 | nomem: |
2821 | ehci_free_sqtds(sc, exfer); | | 2824 | ehci_free_sqtds(sc, exfer); |
2822 | kmem_free(exfer->ex_sqtds, sizeof(ehci_soft_qtd_t *) * nsqtd); | | 2825 | kmem_free(exfer->ex_sqtds, sizeof(ehci_soft_qtd_t *) * nsqtd); |
2823 | DPRINTF("no memory", 0, 0, 0, 0); | | 2826 | DPRINTF("no memory", 0, 0, 0, 0); |
2824 | return ENOMEM; | | 2827 | return ENOMEM; |
2825 | } | | 2828 | } |
2826 | | | 2829 | |
2827 | Static void | | 2830 | Static void |
2828 | ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) | | 2831 | ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) |
2829 | { | | 2832 | { |
2830 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 2833 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
2831 | DPRINTF("exfer=%p", exfer, 0, 0, 0); | | 2834 | DPRINTF("exfer=%p", exfer, 0, 0, 0); |
2832 | | | 2835 | |
2833 | mutex_enter(&sc->sc_lock); | | 2836 | mutex_enter(&sc->sc_lock); |
2834 | for (size_t i = 0; i < exfer->ex_nsqtd; i++) { | | 2837 | for (size_t i = 0; i < exfer->ex_nsqtd; i++) { |
2835 | ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; | | 2838 | ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; |
2836 | | | 2839 | |
2837 | if (sqtd == NULL) | | 2840 | if (sqtd == NULL) |
2838 | break; | | 2841 | break; |
2839 | | | 2842 | |
2840 | sqtd->nextqtd = sc->sc_freeqtds; | | 2843 | sqtd->nextqtd = sc->sc_freeqtds; |
2841 | sc->sc_freeqtds = sqtd; | | 2844 | sc->sc_freeqtds = sqtd; |
2842 | } | | 2845 | } |
2843 | mutex_exit(&sc->sc_lock); | | 2846 | mutex_exit(&sc->sc_lock); |
2844 | } | | 2847 | } |
2845 | | | 2848 | |
2846 | Static void | | 2849 | Static void |
2847 | ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev) | | 2850 | ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev) |
2848 | { | | 2851 | { |
2849 | if (prev) { | | 2852 | if (prev) { |
2850 | prev->nextqtd = sqtd; | | 2853 | prev->nextqtd = sqtd; |
2851 | prev->qtd.qtd_next = htole32(sqtd->physaddr); | | 2854 | prev->qtd.qtd_next = htole32(sqtd->physaddr); |
2852 | prev->qtd.qtd_altnext = prev->qtd.qtd_next; | | 2855 | prev->qtd.qtd_altnext = prev->qtd.qtd_next; |
2853 | usb_syncmem(&prev->dma, prev->offs, sizeof(prev->qtd), | | 2856 | usb_syncmem(&prev->dma, prev->offs, sizeof(prev->qtd), |
2854 | BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); | | 2857 | BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); |
2855 | } | | 2858 | } |
2856 | } | | 2859 | } |
2857 | | | 2860 | |
2858 | Static void | | 2861 | Static void |
2859 | ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, | | 2862 | ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, |
2860 | int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) | | 2863 | int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) |
2861 | { | | 2864 | { |
2862 | struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); | | 2865 | struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); |
2863 | usb_dma_t *dma = &xfer->ux_dmabuf; | | 2866 | usb_dma_t *dma = &xfer->ux_dmabuf; |
2864 | uint16_t flags = xfer->ux_flags; | | 2867 | uint16_t flags = xfer->ux_flags; |
2865 | ehci_soft_qtd_t *sqtd, *prev; | | 2868 | ehci_soft_qtd_t *sqtd, *prev; |
2866 | int tog = *toggle; | | 2869 | int tog = *toggle; |
2867 | int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); | | 2870 | int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); |
2868 | int len = length; | | 2871 | int len = length; |
2869 | | | 2872 | |
2870 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 2873 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
2871 | DPRINTF("xfer=%p len %d isread %d toggle %d", xfer, len, isread, tog); | | 2874 | DPRINTF("xfer=%p len %d isread %d toggle %d", xfer, len, isread, tog); |
2872 | DPRINTF(" VA %p", KERNADDR(&xfer->ux_dmabuf, 0), 0, 0, 0); | | 2875 | DPRINTF(" VA %p", KERNADDR(&xfer->ux_dmabuf, 0), 0, 0, 0); |
2873 | | | 2876 | |
2874 | KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); | | 2877 | KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); |
2875 | | | 2878 | |
2876 | const uint32_t qtdstatus = EHCI_QTD_ACTIVE | | | 2879 | const uint32_t qtdstatus = EHCI_QTD_ACTIVE | |
2877 | EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | | | 2880 | EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | |
2878 | EHCI_QTD_SET_CERR(3) | | 2881 | EHCI_QTD_SET_CERR(3) |
2879 | ; | | 2882 | ; |
2880 | | | 2883 | |
2881 | sqtd = prev = NULL; | | 2884 | sqtd = prev = NULL; |
2882 | size_t curoffs = 0; | | 2885 | size_t curoffs = 0; |
2883 | size_t j = 0; | | 2886 | size_t j = 0; |
2884 | for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) { | | 2887 | for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) { |
2885 | sqtd = exfer->ex_sqtds[j++]; | | 2888 | sqtd = exfer->ex_sqtds[j++]; |
2886 | DPRINTF("sqtd[%d]=%p prev %p", j, sqtd, prev, 0); | | 2889 | DPRINTF("sqtd[%d]=%p prev %p", j, sqtd, prev, 0); |
2887 | | | 2890 | |
2888 | /* | | 2891 | /* |
2889 | * The EHCI hardware can handle at most 5 pages and they do | | 2892 | * The EHCI hardware can handle at most 5 pages and they do |
2890 | * not have to be contiguous | | 2893 | * not have to be contiguous |
2891 | */ | | 2894 | */ |
2892 | vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs); | | 2895 | vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs); |
2893 | vaddr_t va_offs = EHCI_PAGE_OFFSET(va); | | 2896 | vaddr_t va_offs = EHCI_PAGE_OFFSET(va); |
2894 | size_t curlen = len; | | 2897 | size_t curlen = len; |
2895 | if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) { | | 2898 | if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) { |
2896 | /* must use multiple TDs, fill as much as possible. */ | | 2899 | /* must use multiple TDs, fill as much as possible. */ |
2897 | curlen = EHCI_QTD_MAXTRANSFER - va_offs; | | 2900 | curlen = EHCI_QTD_MAXTRANSFER - va_offs; |
2898 | | | 2901 | |
2899 | /* the length must be a multiple of the max size */ | | 2902 | /* the length must be a multiple of the max size */ |
2900 | curlen -= curlen % mps; | | 2903 | curlen -= curlen % mps; |
2901 | } | | 2904 | } |
2902 | KASSERT(curlen != 0); | | 2905 | KASSERT(curlen != 0); |
2903 | DPRINTF(" len=%d curlen=%d curoffs=%zu", len, curlen, | | 2906 | DPRINTF(" len=%d curlen=%d curoffs=%zu", len, curlen, |
2904 | curoffs, 0); | | 2907 | curoffs, 0); |
2905 | | | 2908 | |
2906 | /* Fill the qTD */ | | 2909 | /* Fill the qTD */ |
2907 | sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; | | 2910 | sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; |
2908 | sqtd->qtd.qtd_status = htole32( | | 2911 | sqtd->qtd.qtd_status = htole32( |
2909 | qtdstatus | | | 2912 | qtdstatus | |
2910 | EHCI_QTD_SET_BYTES(curlen) | | | 2913 | EHCI_QTD_SET_BYTES(curlen) | |
2911 | EHCI_QTD_SET_TOGGLE(tog)); | | 2914 | EHCI_QTD_SET_TOGGLE(tog)); |
2912 | | | 2915 | |
2913 | /* Find number of pages we'll be using, insert dma addresses */ | | 2916 | /* Find number of pages we'll be using, insert dma addresses */ |
2914 | size_t pages = EHCI_NPAGES(curlen); | | 2917 | size_t pages = EHCI_NPAGES(curlen); |
2915 | KASSERT(pages <= EHCI_QTD_NBUFFERS); | | 2918 | KASSERT(pages <= EHCI_QTD_NBUFFERS); |
2916 | size_t pageoffs = EHCI_PAGE(curoffs); | | 2919 | size_t pageoffs = EHCI_PAGE(curoffs); |
2917 | for (size_t i = 0; i < pages; i++) { | | 2920 | for (size_t i = 0; i < pages; i++) { |
2918 | paddr_t a = DMAADDR(dma, | | 2921 | paddr_t a = DMAADDR(dma, |
2919 | pageoffs + i * EHCI_PAGE_SIZE); | | 2922 | pageoffs + i * EHCI_PAGE_SIZE); |
2920 | sqtd->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); | | 2923 | sqtd->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); |
2921 | /* Cast up to avoid compiler warnings */ | | 2924 | /* Cast up to avoid compiler warnings */ |
2922 | sqtd->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); | | 2925 | sqtd->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); |
2923 | DPRINTF(" buffer[%d/%d] 0x%08x 0x%08x", i, pages, | | 2926 | DPRINTF(" buffer[%d/%d] 0x%08x 0x%08x", i, pages, |
2924 | le32toh(sqtd->qtd.qtd_buffer_hi[i]), | | 2927 | le32toh(sqtd->qtd.qtd_buffer_hi[i]), |
2925 | le32toh(sqtd->qtd.qtd_buffer[i])); | | 2928 | le32toh(sqtd->qtd.qtd_buffer[i])); |
2926 | } | | 2929 | } |
2927 | /* First buffer pointer requires a page offset to start at */ | | 2930 | /* First buffer pointer requires a page offset to start at */ |
2928 | sqtd->qtd.qtd_buffer[0] |= htole32(va_offs); | | 2931 | sqtd->qtd.qtd_buffer[0] |= htole32(va_offs); |
2929 | | | 2932 | |
2930 | usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), | | 2933 | usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), |
2931 | BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); | | 2934 | BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); |
2932 | | | 2935 | |
2933 | sqtd->len = curlen; | | 2936 | sqtd->len = curlen; |
2934 | | | 2937 | |
2935 | DPRINTF(" va %p pa %p len %d", va, | | 2938 | DPRINTF(" va %p pa %p len %d", va, |
2936 | DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0); | | 2939 | DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0); |
2937 | | | 2940 | |
2938 | ehci_append_sqtd(sqtd, prev); | | 2941 | ehci_append_sqtd(sqtd, prev); |
2939 | | | 2942 | |
2940 | if (((curlen + mps - 1) / mps) & 1) { | | 2943 | if (((curlen + mps - 1) / mps) & 1) { |
2941 | tog ^= 1; | | 2944 | tog ^= 1; |
2942 | } | | 2945 | } |
2943 | | | 2946 | |
2944 | curoffs += curlen; | | 2947 | curoffs += curlen; |
2945 | len -= curlen; | | 2948 | len -= curlen; |
2946 | } | | 2949 | } |
2947 | KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu", | | 2950 | KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu", |
2948 | xfer, length, len, mps, exfer->ex_nsqtd, j); | | 2951 | xfer, length, len, mps, exfer->ex_nsqtd, j); |
2949 | | | 2952 | |
2950 | if (!isread && | | 2953 | if (!isread && |
2951 | (flags & USBD_FORCE_SHORT_XFER) && | | 2954 | (flags & USBD_FORCE_SHORT_XFER) && |
2952 | length % mps == 0) { | | 2955 | length % mps == 0) { |
2953 | /* Force a 0 length transfer at the end. */ | | 2956 | /* Force a 0 length transfer at the end. */ |
2954 | | | 2957 | |
2955 | KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j, | | 2958 | KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j, |
2956 | exfer->ex_nsqtd); | | 2959 | exfer->ex_nsqtd); |
2957 | prev = sqtd; | | 2960 | prev = sqtd; |
2958 | sqtd = exfer->ex_sqtds[j++]; | | 2961 | sqtd = exfer->ex_sqtds[j++]; |
2959 | memset(&sqtd->qtd, 0, sizeof(sqtd->qtd)); | | 2962 | memset(&sqtd->qtd, 0, sizeof(sqtd->qtd)); |
2960 | sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; | | 2963 | sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; |
2961 | sqtd->qtd.qtd_status = htole32( | | 2964 | sqtd->qtd.qtd_status = htole32( |
2962 | qtdstatus | | | 2965 | qtdstatus | |
2963 | EHCI_QTD_SET_BYTES(0) | | | 2966 | EHCI_QTD_SET_BYTES(0) | |
2964 | EHCI_QTD_SET_TOGGLE(tog)); | | 2967 | EHCI_QTD_SET_TOGGLE(tog)); |
2965 | | | 2968 | |
2966 | usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), | | 2969 | usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), |
2967 | BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); | | 2970 | BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); |
2968 | | | 2971 | |
2969 | ehci_append_sqtd(sqtd, prev); | | 2972 | ehci_append_sqtd(sqtd, prev); |
2970 | tog ^= 1; | | 2973 | tog ^= 1; |
2971 | } | | 2974 | } |
2972 | | | 2975 | |
2973 | *lsqtd = sqtd; | | 2976 | *lsqtd = sqtd; |
2974 | *toggle = tog; | | 2977 | *toggle = tog; |
2975 | } | | 2978 | } |
2976 | | | 2979 | |
2977 | Static ehci_soft_itd_t * | | 2980 | Static ehci_soft_itd_t * |
2978 | ehci_alloc_itd(ehci_softc_t *sc) | | 2981 | ehci_alloc_itd(ehci_softc_t *sc) |
2979 | { | | 2982 | { |
2980 | struct ehci_soft_itd *itd, *freeitd; | | 2983 | struct ehci_soft_itd *itd, *freeitd; |
2981 | usbd_status err; | | 2984 | usbd_status err; |
2982 | usb_dma_t dma; | | 2985 | usb_dma_t dma; |
2983 | | | 2986 | |
2984 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 2987 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
2985 | | | 2988 | |
2986 | mutex_enter(&sc->sc_lock); | | 2989 | mutex_enter(&sc->sc_lock); |
2987 | | | 2990 | |
2988 | freeitd = LIST_FIRST(&sc->sc_freeitds); | | 2991 | freeitd = LIST_FIRST(&sc->sc_freeitds); |
2989 | if (freeitd == NULL) { | | 2992 | if (freeitd == NULL) { |
2990 | DPRINTF("allocating chunk", 0, 0, 0, 0); | | 2993 | DPRINTF("allocating chunk", 0, 0, 0, 0); |
2991 | mutex_exit(&sc->sc_lock); | | 2994 | mutex_exit(&sc->sc_lock); |
2992 | err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, | | 2995 | err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, |
2993 | EHCI_PAGE_SIZE, &dma); | | 2996 | EHCI_PAGE_SIZE, &dma); |
2994 | | | 2997 | |
2995 | if (err) { | | 2998 | if (err) { |
2996 | DPRINTF("alloc returned %d", err, 0, 0, 0); | | 2999 | DPRINTF("alloc returned %d", err, 0, 0, 0); |
2997 | return NULL; | | 3000 | return NULL; |
2998 | } | | 3001 | } |
2999 | mutex_enter(&sc->sc_lock); | | 3002 | mutex_enter(&sc->sc_lock); |
3000 | | | 3003 | |
3001 | for (int i = 0; i < EHCI_ITD_CHUNK; i++) { | | 3004 | for (int i = 0; i < EHCI_ITD_CHUNK; i++) { |
3002 | int offs = i * EHCI_ITD_SIZE; | | 3005 | int offs = i * EHCI_ITD_SIZE; |
3003 | itd = KERNADDR(&dma, offs); | | 3006 | itd = KERNADDR(&dma, offs); |
3004 | itd->physaddr = DMAADDR(&dma, offs); | | 3007 | itd->physaddr = DMAADDR(&dma, offs); |
3005 | itd->dma = dma; | | 3008 | itd->dma = dma; |
3006 | itd->offs = offs; | | 3009 | itd->offs = offs; |
3007 | LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); | | 3010 | LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); |
3008 | } | | 3011 | } |
3009 | freeitd = LIST_FIRST(&sc->sc_freeitds); | | 3012 | freeitd = LIST_FIRST(&sc->sc_freeitds); |
3010 | } | | 3013 | } |
3011 | | | 3014 | |
3012 | itd = freeitd; | | 3015 | itd = freeitd; |
3013 | LIST_REMOVE(itd, free_list); | | 3016 | LIST_REMOVE(itd, free_list); |
3014 | mutex_exit(&sc->sc_lock); | | 3017 | mutex_exit(&sc->sc_lock); |
3015 | memset(&itd->itd, 0, sizeof(ehci_itd_t)); | | 3018 | memset(&itd->itd, 0, sizeof(ehci_itd_t)); |
3016 | | | 3019 | |
3017 | itd->frame_list.next = NULL; | | 3020 | itd->frame_list.next = NULL; |
3018 | itd->frame_list.prev = NULL; | | 3021 | itd->frame_list.prev = NULL; |
3019 | itd->xfer_next = NULL; | | 3022 | itd->xfer_next = NULL; |
3020 | itd->slot = 0; | | 3023 | itd->slot = 0; |
3021 | | | 3024 | |
3022 | return itd; | | 3025 | return itd; |
3023 | } | | 3026 | } |
3024 | | | 3027 | |
3025 | Static ehci_soft_sitd_t * | | 3028 | Static ehci_soft_sitd_t * |
3026 | ehci_alloc_sitd(ehci_softc_t *sc) | | 3029 | ehci_alloc_sitd(ehci_softc_t *sc) |
3027 | { | | 3030 | { |
3028 | struct ehci_soft_sitd *sitd, *freesitd; | | 3031 | struct ehci_soft_sitd *sitd, *freesitd; |
3029 | usbd_status err; | | 3032 | usbd_status err; |
3030 | int i, offs; | | 3033 | int i, offs; |
3031 | usb_dma_t dma; | | 3034 | usb_dma_t dma; |
3032 | | | 3035 | |
3033 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 3036 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
3034 | | | 3037 | |
3035 | mutex_enter(&sc->sc_lock); | | 3038 | mutex_enter(&sc->sc_lock); |
3036 | freesitd = LIST_FIRST(&sc->sc_freesitds); | | 3039 | freesitd = LIST_FIRST(&sc->sc_freesitds); |
3037 | if (freesitd == NULL) { | | 3040 | if (freesitd == NULL) { |
3038 | DPRINTF("allocating chunk", 0, 0, 0, 0); | | 3041 | DPRINTF("allocating chunk", 0, 0, 0, 0); |
3039 | mutex_exit(&sc->sc_lock); | | 3042 | mutex_exit(&sc->sc_lock); |
3040 | err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, | | 3043 | err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, |
3041 | EHCI_PAGE_SIZE, &dma); | | 3044 | EHCI_PAGE_SIZE, &dma); |
3042 | | | 3045 | |
3043 | if (err) { | | 3046 | if (err) { |
3044 | DPRINTF("alloc returned %d", err, 0, 0, | | 3047 | DPRINTF("alloc returned %d", err, 0, 0, |
3045 | 0); | | 3048 | 0); |
3046 | return NULL; | | 3049 | return NULL; |
3047 | } | | 3050 | } |
3048 | | | 3051 | |
3049 | mutex_enter(&sc->sc_lock); | | 3052 | mutex_enter(&sc->sc_lock); |
3050 | for (i = 0; i < EHCI_SITD_CHUNK; i++) { | | 3053 | for (i = 0; i < EHCI_SITD_CHUNK; i++) { |
3051 | offs = i * EHCI_SITD_SIZE; | | 3054 | offs = i * EHCI_SITD_SIZE; |
3052 | sitd = KERNADDR(&dma, offs); | | 3055 | sitd = KERNADDR(&dma, offs); |
3053 | sitd->physaddr = DMAADDR(&dma, offs); | | 3056 | sitd->physaddr = DMAADDR(&dma, offs); |
3054 | sitd->dma = dma; | | 3057 | sitd->dma = dma; |
3055 | sitd->offs = offs; | | 3058 | sitd->offs = offs; |
3056 | LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); | | 3059 | LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); |
3057 | } | | 3060 | } |
3058 | freesitd = LIST_FIRST(&sc->sc_freesitds); | | 3061 | freesitd = LIST_FIRST(&sc->sc_freesitds); |
3059 | } | | 3062 | } |
3060 | | | 3063 | |
3061 | sitd = freesitd; | | 3064 | sitd = freesitd; |
3062 | LIST_REMOVE(sitd, free_list); | | 3065 | LIST_REMOVE(sitd, free_list); |
3063 | mutex_exit(&sc->sc_lock); | | 3066 | mutex_exit(&sc->sc_lock); |
3064 | | | 3067 | |
3065 | memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); | | 3068 | memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); |
3066 | | | 3069 | |
3067 | sitd->frame_list.next = NULL; | | 3070 | sitd->frame_list.next = NULL; |
3068 | sitd->frame_list.prev = NULL; | | 3071 | sitd->frame_list.prev = NULL; |
3069 | sitd->xfer_next = NULL; | | 3072 | sitd->xfer_next = NULL; |
3070 | sitd->slot = 0; | | 3073 | sitd->slot = 0; |
3071 | | | 3074 | |
3072 | return sitd; | | 3075 | return sitd; |
3073 | } | | 3076 | } |
3074 | | | 3077 | |
3075 | /****************/ | | 3078 | /****************/ |
3076 | | | 3079 | |
3077 | /* | | 3080 | /* |
3078 | * Close a reqular pipe. | | 3081 | * Close a reqular pipe. |
3079 | * Assumes that there are no pending transactions. | | 3082 | * Assumes that there are no pending transactions. |
3080 | */ | | 3083 | */ |
3081 | Static void | | 3084 | Static void |
3082 | ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) | | 3085 | ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) |
3083 | { | | 3086 | { |
3084 | struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); | | 3087 | struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); |
3085 | ehci_softc_t *sc = EHCI_PIPE2SC(pipe); | | 3088 | ehci_softc_t *sc = EHCI_PIPE2SC(pipe); |
3086 | ehci_soft_qh_t *sqh = epipe->sqh; | | 3089 | ehci_soft_qh_t *sqh = epipe->sqh; |
3087 | | | 3090 | |
3088 | KASSERT(mutex_owned(&sc->sc_lock)); | | 3091 | KASSERT(mutex_owned(&sc->sc_lock)); |
3089 | | | 3092 | |
3090 | ehci_rem_qh(sc, sqh, head); | | 3093 | ehci_rem_qh(sc, sqh, head); |
3091 | ehci_free_sqh(sc, epipe->sqh); | | 3094 | ehci_free_sqh(sc, epipe->sqh); |
3092 | } | | 3095 | } |
3093 | | | 3096 | |
3094 | /* | | 3097 | /* |
3095 | * Abort a device request. | | 3098 | * Abort a device request. |
3096 | * If this routine is called at splusb() it guarantees that the request | | 3099 | * If this routine is called at splusb() it guarantees that the request |
3097 | * will be removed from the hardware scheduling and that the callback | | 3100 | * will be removed from the hardware scheduling and that the callback |
3098 | * for it will be called with USBD_CANCELLED status. | | 3101 | * for it will be called with USBD_CANCELLED status. |
3099 | * It's impossible to guarantee that the requested transfer will not | | 3102 | * It's impossible to guarantee that the requested transfer will not |
3100 | * have happened since the hardware runs concurrently. | | 3103 | * have happened since the hardware runs concurrently. |
3101 | * If the transaction has already happened we rely on the ordinary | | 3104 | * If the transaction has already happened we rely on the ordinary |
3102 | * interrupt processing to process it. | | 3105 | * interrupt processing to process it. |
3103 | * XXX This is most probably wrong. | | 3106 | * XXX This is most probably wrong. |
3104 | * XXXMRG this doesn't make sense anymore. | | 3107 | * XXXMRG this doesn't make sense anymore. |
3105 | */ | | 3108 | */ |
3106 | Static void | | 3109 | Static void |
3107 | ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) | | 3110 | ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) |
3108 | { | | 3111 | { |
3109 | struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); | | 3112 | struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); |
3110 | struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); | | 3113 | struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); |
3111 | ehci_softc_t *sc = EHCI_XFER2SC(xfer); | | 3114 | ehci_softc_t *sc = EHCI_XFER2SC(xfer); |
3112 | ehci_soft_qh_t *sqh = epipe->sqh; | | 3115 | ehci_soft_qh_t *sqh = epipe->sqh; |
3113 | ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; | | 3116 | ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; |
3114 | ehci_physaddr_t cur; | | 3117 | ehci_physaddr_t cur; |
3115 | uint32_t qhstatus; | | 3118 | uint32_t qhstatus; |
3116 | int hit; | | 3119 | int hit; |
3117 | int wake; | | 3120 | int wake; |
3118 | | | 3121 | |
3119 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); | | 3122 | EHCIHIST_FUNC(); EHCIHIST_CALLED(); |
3120 | | | 3123 | |
3121 | DPRINTF("xfer=%p pipe=%p", xfer, epipe, 0, 0); | | 3124 | DPRINTF("xfer=%p pipe=%p", xfer, epipe, 0, 0); |
3122 | | | 3125 | |
3123 | KASSERT(mutex_owned(&sc->sc_lock)); | | 3126 | KASSERT(mutex_owned(&sc->sc_lock)); |
3124 | ASSERT_SLEEPABLE(); | | 3127 | ASSERT_SLEEPABLE(); |
3125 | | | 3128 | |
3126 | if (sc->sc_dying) { | | 3129 | if (sc->sc_dying) { |
3127 | /* If we're dying, just do the software part. */ | | 3130 | /* If we're dying, just do the software part. */ |
3128 | xfer->ux_status = status; /* make software ignore it */ | | 3131 | xfer->ux_status = status; /* make software ignore it */ |
3129 | callout_stop(&xfer->ux_callout); | | 3132 | callout_stop(&xfer->ux_callout); |
3130 | usb_transfer_complete(xfer); | | 3133 | usb_transfer_complete(xfer); |
3131 | return; | | 3134 | return; |
3132 | } | | 3135 | } |
3133 | | | 3136 | |
3134 | /* | | 3137 | /* |
3135 | * If an abort is already in progress then just wait for it to | | 3138 | * If an abort is already in progress then just wait for it to |
3136 | * complete and return. | | 3139 | * complete and return. |
3137 | */ | | 3140 | */ |
3138 | if (xfer->ux_hcflags & UXFER_ABORTING) { | | 3141 | if (xfer->ux_hcflags & UXFER_ABORTING) { |
3139 | DPRINTF("already aborting", 0, 0, 0, 0); | | 3142 | DPRINTF("already aborting", 0, 0, 0, 0); |
3140 | #ifdef DIAGNOSTIC | | 3143 | #ifdef DIAGNOSTIC |
3141 | if (status == USBD_TIMEOUT) | | 3144 | if (status == USBD_TIMEOUT) |
3142 | printf("ehci_abort_xfer: TIMEOUT while aborting\n"); | | 3145 | printf("ehci_abort_xfer: TIMEOUT while aborting\n"); |
3143 | #endif | | 3146 | #endif |
3144 | /* Override the status which might be USBD_TIMEOUT. */ | | 3147 | /* Override the status which might be USBD_TIMEOUT. */ |
3145 | xfer->ux_status = status; | | 3148 | xfer->ux_status = status; |
3146 | DPRINTF("waiting for abort to finish", 0, 0, 0, 0); | | 3149 | DPRINTF("waiting for abort to finish", 0, 0, 0, 0); |
3147 | xfer->ux_hcflags |= UXFER_ABORTWAIT; | | 3150 | xfer->ux_hcflags |= UXFER_ABORTWAIT; |
3148 | while (xfer->ux_hcflags & UXFER_ABORTING) | | 3151 | while (xfer->ux_hcflags & UXFER_ABORTING) |
3149 | cv_wait(&xfer->ux_hccv, &sc->sc_lock); | | 3152 | cv_wait(&xfer->ux_hccv, &sc->sc_lock); |
3150 | return; | | 3153 | return; |
3151 | } | | 3154 | } |
3152 | xfer->ux_hcflags |= UXFER_ABORTING; | | 3155 | xfer->ux_hcflags |= UXFER_ABORTING; |
3153 | | | 3156 | |
3154 | /* | | 3157 | /* |
3155 | * Step 1: Make interrupt routine and hardware ignore xfer. | | 3158 | * Step 1: Make interrupt routine and hardware ignore xfer. |
3156 | */ | | 3159 | */ |
3157 | xfer->ux_status = status; /* make software ignore it */ | | 3160 | xfer->ux_status = status; /* make software ignore it */ |
3158 | callout_stop(&xfer->ux_callout); | | 3161 | callout_stop(&xfer->ux_callout); |
3159 | ehci_del_intr_list(sc, exfer); | | 3162 | ehci_del_intr_list(sc, exfer); |
3160 | | | 3163 | |
3161 | usb_syncmem(&sqh->dma, | | 3164 | usb_syncmem(&sqh->dma, |
3162 | sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), | | 3165 | sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), |
3163 | sizeof(sqh->qh.qh_qtd.qtd_status), | | 3166 | sizeof(sqh->qh.qh_qtd.qtd_status), |
3164 | BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); | | 3167 | BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); |
3165 | qhstatus = sqh->qh.qh_qtd.qtd_status; | | 3168 | qhstatus = sqh->qh.qh_qtd.qtd_status; |
3166 | sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); | | 3169 | sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); |
3167 | usb_syncmem(&sqh->dma, | | 3170 | usb_syncmem(&sqh->dma, |
3168 | sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), | | 3171 | sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), |
3169 | sizeof(sqh->qh.qh_qtd.qtd_status), | | 3172 | sizeof(sqh->qh.qh_qtd.qtd_status), |
3170 | BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); | | 3173 | BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); |
3171 | | | 3174 | |