Wed Oct 5 13:25:25 2016 UTC ()
Comment-out don't matched sdhc.  omap's sdhc not support TI_DM37XX now. However Overo FireSTORM(DM3730) work fine with OVERO(OMAP_3530 only).


(kiyohara)
diff -r1.21 -r1.22 src/sys/arch/evbarm/conf/BEAGLEBOARDXM
cvs diff -r1.21 -r1.22 src/sys/arch/evbarm/conf/Attic/BEAGLEBOARDXM (expand / switch to unified diff)

--- src/sys/arch/evbarm/conf/Attic/BEAGLEBOARDXM 2016/06/24 12:22:09 1.21
+++ src/sys/arch/evbarm/conf/Attic/BEAGLEBOARDXM 2016/10/05 13:25:25 1.22
@@ -1,15 +1,15 @@ @@ -1,15 +1,15 @@
1# 1#
2# $NetBSD: BEAGLEBOARDXM,v 1.21 2016/06/24 12:22:09 skrll Exp $ 2# $NetBSD: BEAGLEBOARDXM,v 1.22 2016/10/05 13:25:25 kiyohara Exp $
3# 3#
4# BEAGLEBOARD -- TI OMAP 3530 Eval Board Kernel 4# BEAGLEBOARD -- TI OMAP 3530 Eval Board Kernel
5# 5#
6 6
7include "arch/evbarm/conf/std.beagle" 7include "arch/evbarm/conf/std.beagle"
8 8
9# estimated number of users 9# estimated number of users
10 10
11maxusers 32 11maxusers 32
12 12
13# Standard system options 13# Standard system options
14 14
15options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT 15options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT
@@ -166,31 +166,31 @@ options MEMSIZE=512 @@ -166,31 +166,31 @@ options MEMSIZE=512
166# L3 Interconnect 166# L3 Interconnect
167L3i0 at mainbus? 167L3i0 at mainbus?
168 168
169# OBIO 169# OBIO
170obio0 at mainbus? base 0x48000000 size 0x1000000 # L4 CORE 170obio0 at mainbus? base 0x48000000 size 0x1000000 # L4 CORE
171obio1 at mainbus? base 0x48300000 size 0x0100000 # L4 WAKEUP 171obio1 at mainbus? base 0x48300000 size 0x0100000 # L4 WAKEUP
172obio2 at mainbus? base 0x49000000 size 0x1000000 # L4 PERIPHERAL 172obio2 at mainbus? base 0x49000000 size 0x1000000 # L4 PERIPHERAL
173#obio3 at mainbus? base 0x54000000 size 0x0800000 # L4 EMUL 173#obio3 at mainbus? base 0x54000000 size 0x0800000 # L4 EMUL
174 174
175# General Purpose Memory Controller 175# General Purpose Memory Controller
176gpmc0 at mainbus? base 0x6e000000 176gpmc0 at mainbus? base 0x6e000000
177 177
178# SDHC controllers 178# SDHC controllers
179sdhc0 at obio0 addr 0x4809C000 size 0x0400 intr 83 179#sdhc0 at obio0 addr 0x4809C000 size 0x0400 intr 83
180#sdhc1 at obio0 addr 0x480B4000 size 0x0400 intr 86 180#sdhc1 at obio0 addr 0x480B4000 size 0x0400 intr 86
181#sdhc2 at obio0 addr 0x480AD000 size 0x0400 intr 94 181#sdhc2 at obio0 addr 0x480AD000 size 0x0400 intr 94
182sdmmc* at sdhc? # SD/MMC bus 182#sdmmc* at sdhc? # SD/MMC bus
183ld* at sdmmc? 183#ld* at sdmmc?
184 184
185# Interrupt Controller 185# Interrupt Controller
186omapicu0 at obio0 addr 0x48200000 size 0x1000 intrbase 0 186omapicu0 at obio0 addr 0x48200000 size 0x1000 intrbase 0
187omapgpio0 at obio1 addr 0x48310000 size 0x0400 intrbase 96 intr 29 187omapgpio0 at obio1 addr 0x48310000 size 0x0400 intrbase 96 intr 29
188#omapgpio1 at obio2 addr 0x49050000 size 0x0400 intrbase 128 intr 30 188#omapgpio1 at obio2 addr 0x49050000 size 0x0400 intrbase 128 intr 30
189#omapgpio2 at obio2 addr 0x49052000 size 0x0400 intrbase 160 intr 31 189#omapgpio2 at obio2 addr 0x49052000 size 0x0400 intrbase 160 intr 31
190#omapgpio3 at obio2 addr 0x49054000 size 0x0400 intrbase 192 intr 32 190#omapgpio3 at obio2 addr 0x49054000 size 0x0400 intrbase 192 intr 32
191omapgpio4 at obio2 addr 0x49056000 size 0x0400 intrbase 224 intr 33 191omapgpio4 at obio2 addr 0x49056000 size 0x0400 intrbase 224 intr 33
192#omapgpio5 at obio2 addr 0x49058000 size 0x0400 intrbase 256 intr 34 192#omapgpio5 at obio2 addr 0x49058000 size 0x0400 intrbase 256 intr 34
193 193
194gpio* at omapgpio? 194gpio* at omapgpio?
195 195
196# # I2C Controller 196# # I2C Controller