Sat Oct 8 08:19:22 2016 UTC ()

Sign extend VA for cache operations.

OK matt@


(skrll)

diff -r1.18 -r1.19 src/sys/arch/mips/mips/mips_fixup.c

--- src/sys/arch/mips/mips/mips_fixup.c 2016/08/18 19:25:34	1.18
+++ src/sys/arch/mips/mips/mips_fixup.c 2016/10/08 08:19:22	1.19

 @@ -1,14 +1,14 @@
-/*	$NetBSD: mips_fixup.c,v 1.18 2016/08/18 19:25:34 skrll Exp $	*/
+/*	$NetBSD: mips_fixup.c,v 1.19 2016/10/08 08:19:22 skrll Exp $	*/
 /*-
  * Copyright (c) 2010 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Matt Thomas of 3am Software Foundry.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -20,27 +20,27 @@
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mips_fixup.c,v 1.18 2016/08/18 19:25:34 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_fixup.c,v 1.19 2016/10/08 08:19:22 skrll Exp $");
 #include "opt_mips3_wired.h"
 #include "opt_multiprocessor.h"
 #include <sys/param.h>
 #include <uvm/uvm_extern.h>
 #include <mips/locore.h>
 #include <mips/cache.h>
 #include <mips/mips3_pte.h>
 #include <mips/regnum.h>
 #include <mips/mips_opcode.h>
 @@ -147,27 +147,27 @@ mips_fixup_exceptions(mips_fixup_callbac
+			}
 		} else if (INSN_LOAD_P(insn)) {
 			/*
 			 * If we are loading the register used in the LUI,
 			 * then that LUI is meaningless now.
 			 */
 			size_t rt = (insn >> 16) & 31;
 			if (lui_reg == rt)
 				lui_insn = 0;
+		}
+	}
 	if (fixed)
-		mips_icache_sync_range((vaddr_t)start,
+		mips_icache_sync_range((intptr_t)start,
 		   sizeof(start[0]) * (end - start));
 	return fixed;
+}
 #ifdef MIPS3_PLUS
 bool
 mips_fixup_zero_relative(int32_t load_addr, uint32_t new_insns[2], void *arg)
+{
 	struct cpu_info * const ci = curcpu();
 	struct pmap_tlb_info * const ti = ci->ci_tlb_info;
 	KASSERT(MIPS_KSEG0_P(load_addr));
 @@ -481,27 +481,27 @@ mips_fixup_stubs(uint32_t *start, uint32
 		    .jfi_stub = fixup_addr2offset(stubp),
 		    .jfi_real = fixup_addr2offset(real_addr),
 		};
 		fixup_mips_jump(insnp, &fixup);
 #ifdef DEBUG
 		fixups_done++;
 #endif
+	}
 	if (sizeof(uint32_t [end - start]) > mips_cache_info.mci_picache_size)
 		mips_icache_sync_all();
 	else
-		mips_icache_sync_range((vaddr_t)start,
+		mips_icache_sync_range((intptr_t)start,
 		    sizeof(uint32_t [end - start]));
 #ifdef DEBUG
 #if (MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0
 	if (CPUISMIPS3)
 		cycles = mips3_cp0_count_read() - cycles;
 #endif
 	printf("%s: %zu fixup%s done in %u cycles\n", __func__,
 	    fixups_done, fixups_done == 1 ? "" : "s",
 	    cycles);
 #endif
+}