Mon Oct 10 07:37:17 2016 UTC ()

vaddr_t -> register_t in range cache ops


(skrll)

diff -r1.17 -r1.18 src/sys/arch/mips/mips/cache_r5k.c

--- src/sys/arch/mips/mips/cache_r5k.c 2016/10/08 00:39:53	1.17
+++ src/sys/arch/mips/mips/cache_r5k.c 2016/10/10 07:37:17	1.18

 @@ -1,14 +1,14 @@
-/*	$NetBSD: cache_r5k.c,v 1.17 2016/10/08 00:39:53 macallan Exp $	*/
+/*	$NetBSD: cache_r5k.c,v 1.18 2016/10/10 07:37:17 skrll Exp $	*/
 /*
  * Copyright 2001 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
 @@ -26,27 +26,27 @@
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache_r5k.c,v 1.17 2016/10/08 00:39:53 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache_r5k.c,v 1.18 2016/10/10 07:37:17 skrll Exp $");
 #include <sys/param.h>
 #include <mips/cache.h>
 #include <mips/cache_r4k.h>
 #include <mips/cache_r5k.h>
 #include <mips/locore.h>
 /*
  * Cache operations for R5000-style caches:
+ *
  *	- 2-way set-associative
  *	- Write-back
 @@ -277,53 +277,53 @@ vr4131v1_pdcache_wbinv_range_16(register
 		cache_r4k_op_32lines_16(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
+	}
 	for (; va < eva; va += 16) {
 		cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
 		cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
+	}
+}
 void
 r4600v1_pdcache_inv_range_32(register_t va, vsize_t size)
+{
-	const vaddr_t eva = round_line32(va + size);
+	const register_t eva = round_line32(va + size);
 	/*
 	 * This is pathetically slow, but the chip bug is pretty
 	 * nasty, and we hope that not too many v1.x R4600s are
 	 * around.
 	 */
 	va = trunc_line32(va);
 	const uint32_t ostatus = mips_cp0_status_read();
 	mips_cp0_status_write(ostatus & ~MIPS_SR_INT_IE);
 	for (; va < eva; va += 32) {
 		__asm volatile("nop; nop; nop; nop;");
 		cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
+	}
 	mips_cp0_status_write(ostatus);
+}
 void
 r4600v2_pdcache_inv_range_32(register_t va, vsize_t size)
+{
-	const vaddr_t eva = round_line32(va + size);
+	const register_t eva = round_line32(va + size);
 	va = trunc_line32(va);
 	const uint32_t ostatus = mips_cp0_status_read();
 	mips_cp0_status_write(ostatus & ~MIPS_SR_INT_IE);
 	/*
 	 * Between blasts of big cache chunks, give interrupts
 	 * a chance to get though.
 	 */
 	for (; (eva - va) >= (32 * 32); va += (32 * 32)) {
 		(void) *(volatile int *)MIPS_PHYS_TO_KSEG1(0);