Thu Oct 13 18:58:00 2016 UTC ()
include locore.h for MIPS3_PLUS, while there annotate some #else and #endif


(macallan)
diff -r1.206 -r1.207 src/sys/arch/mips/mips/locore.S
cvs diff -r1.206 -r1.207 src/sys/arch/mips/mips/locore.S (expand / switch to unified diff)

--- src/sys/arch/mips/mips/locore.S 2016/08/19 10:05:35 1.206
+++ src/sys/arch/mips/mips/locore.S 2016/10/13 18:58:00 1.207
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: locore.S,v 1.206 2016/08/19 10:05:35 skrll Exp $ */ 1/* $NetBSD: locore.S,v 1.207 2016/10/13 18:58:00 macallan Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 1992, 1993 4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved. 5 * The Regents of the University of California. All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to Berkeley by 7 * This code is derived from software contributed to Berkeley by
8 * Digital Equipment Corporation and Ralph Campbell. 8 * Digital Equipment Corporation and Ralph Campbell.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -51,28 +51,29 @@ @@ -51,28 +51,29 @@
51 51
52#include "opt_cputype.h" /* which mips CPU levels do we support? */ 52#include "opt_cputype.h" /* which mips CPU levels do we support? */
53#include "opt_ddb.h" 53#include "opt_ddb.h"
54#include "opt_kgdb.h" 54#include "opt_kgdb.h"
55#include "opt_lockdebug.h" 55#include "opt_lockdebug.h"
56#include "opt_multiprocessor.h" 56#include "opt_multiprocessor.h"
57 57
58#include <sys/cdefs.h> 58#include <sys/cdefs.h>
59#include <sys/errno.h> 59#include <sys/errno.h>
60 60
61#include <mips/asm.h> 61#include <mips/asm.h>
62#include <mips/cpuregs.h> 62#include <mips/cpuregs.h>
63#include <mips/trap.h> 63#include <mips/trap.h>
 64#include <mips/locore.h>
64 65
65RCSID("$NetBSD: locore.S,v 1.206 2016/08/19 10:05:35 skrll Exp $") 66RCSID("$NetBSD: locore.S,v 1.207 2016/10/13 18:58:00 macallan Exp $")
66 67
67#include "assym.h" 68#include "assym.h"
68 69
69#if defined(MIPS1) || defined(MIPS2) || defined(MIPS3) 70#if defined(MIPS1) || defined(MIPS2) || defined(MIPS3)
70#define MFC0_HAZARD nop 71#define MFC0_HAZARD nop
71#else 72#else
72#define MFC0_HAZARD /* nothing */ 73#define MFC0_HAZARD /* nothing */
73#endif 74#endif
74 75
75 .set noreorder 76 .set noreorder
76 77
77 .globl start 78 .globl start
78 .globl _C_LABEL(kernel_text) # libkvm refers this 79 .globl _C_LABEL(kernel_text) # libkvm refers this
@@ -133,39 +134,39 @@ _C_LABEL(kernel_text): @@ -133,39 +134,39 @@ _C_LABEL(kernel_text):
1332: 1342:
134#ifdef __GP_SUPPORT__ 135#ifdef __GP_SUPPORT__
135 PTR_LA gp, _C_LABEL(_gp) 136 PTR_LA gp, _C_LABEL(_gp)
136#endif 137#endif
137 138
138#ifdef NOFPU /* No FPU; avoid touching FPU registers */ 139#ifdef NOFPU /* No FPU; avoid touching FPU registers */
139#if !defined(emips) /* XXX??? we have already disabled interrupts! */ 140#if !defined(emips) /* XXX??? we have already disabled interrupts! */
140#ifdef __mips_n32 141#ifdef __mips_n32
141 li t0, MIPS_SR_KX # turn on XKSEG and XKPHYS 142 li t0, MIPS_SR_KX # turn on XKSEG and XKPHYS
142#elif defined(_LP64) 143#elif defined(_LP64)
143 li t0, MIPS_SR_KX | MIPS_SR_UX # turn on XKSEG and XKPHYS 144 li t0, MIPS_SR_KX | MIPS_SR_UX # turn on XKSEG and XKPHYS
144#else 145#else
145 li t0, 0 # Disable interrupts and 146 li t0, 0 # Disable interrupts and
146#endif 147#endif /* n32 */
147 mtc0 t0, MIPS_COP_0_STATUS # the fp coprocessor 148 mtc0 t0, MIPS_COP_0_STATUS # the fp coprocessor
148 COP0_SYNC 149 COP0_SYNC
149#endif 150#endif /* !emips */
150#ifdef HPCMIPS_L1CACHE_DISABLE 151#ifdef HPCMIPS_L1CACHE_DISABLE
151 mfc0 t0, MIPS_COP_0_CONFIG 152 mfc0 t0, MIPS_COP_0_CONFIG
152 li t1, 0xfffffff8 153 li t1, 0xfffffff8
153 and t0, t0, t1 154 and t0, t0, t1
154 or t0, 0x00000002 # XXX, KSEG0 is uncached 155 or t0, 0x00000002 # XXX, KSEG0 is uncached
155 mtc0 t0, MIPS_COP_0_CONFIG 156 mtc0 t0, MIPS_COP_0_CONFIG
156 COP0_SYNC 157 COP0_SYNC
157#endif /* HPCMIPS_L1CACHE_DISABLE */ 158#endif /* HPCMIPS_L1CACHE_DISABLE */
158#else 159#else /* NOFPU */
159 mfc0 t0, MIPS_COP_0_STATUS 160 mfc0 t0, MIPS_COP_0_STATUS
160 MFC0_HAZARD 161 MFC0_HAZARD
161#if defined(_LP64) || defined(__mips_n32) 162#if defined(_LP64) || defined(__mips_n32)
162 or t0, MIPS_SR_KX # turn on XKSEG and XKPHYS 163 or t0, MIPS_SR_KX # turn on XKSEG and XKPHYS
163#endif 164#endif
164 or t0, MIPS_SR_COP_1_BIT # Disable interrupts, and 165 or t0, MIPS_SR_COP_1_BIT # Disable interrupts, and
165 mtc0 t0, MIPS_COP_0_STATUS # enable the fp coprocessor 166 mtc0 t0, MIPS_COP_0_STATUS # enable the fp coprocessor
166 COP0_HAZARD_FPUENABLE 167 COP0_HAZARD_FPUENABLE
167#endif 168#endif
168 mfc0 t0, MIPS_COP_0_PRID # read product revision ID 169 mfc0 t0, MIPS_COP_0_PRID # read product revision ID
169 COP0_SYNC 170 COP0_SYNC
170 nop 171 nop
171#ifdef NOFPU /* No FPU; avoid touching FPU registers */ 172#ifdef NOFPU /* No FPU; avoid touching FPU registers */