Sat Oct 15 09:50:27 2016 UTC ()
Instead of setting the TPR to the value that was in the data segment, set
zero directly. On amd64, the data version of lapic_tpr is not explicitly
initialized.


(maxv)
diff -r1.52 -r1.53 src/sys/arch/x86/x86/lapic.c
cvs diff -r1.52 -r1.53 src/sys/arch/x86/x86/lapic.c (expand / switch to unified diff)

--- src/sys/arch/x86/x86/lapic.c 2016/07/25 12:11:40 1.52
+++ src/sys/arch/x86/x86/lapic.c 2016/10/15 09:50:27 1.53
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: lapic.c,v 1.52 2016/07/25 12:11:40 maxv Exp $ */ 1/* $NetBSD: lapic.c,v 1.53 2016/10/15 09:50:27 maxv Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2000, 2008 The NetBSD Foundation, Inc. 4 * Copyright (c) 2000, 2008 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by RedBack Networks Inc. 8 * by RedBack Networks Inc.
9 * 9 *
10 * Author: Bill Sommerfeld 10 * Author: Bill Sommerfeld
11 * 11 *
12 * Redistribution and use in source and binary forms, with or without 12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions 13 * modification, are permitted provided that the following conditions
14 * are met: 14 * are met:
@@ -22,27 +22,27 @@ @@ -22,27 +22,27 @@
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE. 31 * POSSIBILITY OF SUCH DAMAGE.
32 */ 32 */
33 33
34#include <sys/cdefs.h> 34#include <sys/cdefs.h>
35__KERNEL_RCSID(0, "$NetBSD: lapic.c,v 1.52 2016/07/25 12:11:40 maxv Exp $"); 35__KERNEL_RCSID(0, "$NetBSD: lapic.c,v 1.53 2016/10/15 09:50:27 maxv Exp $");
36 36
37#include "opt_ddb.h" 37#include "opt_ddb.h"
38#include "opt_mpbios.h" /* for MPDEBUG */ 38#include "opt_mpbios.h" /* for MPDEBUG */
39#include "opt_multiprocessor.h" 39#include "opt_multiprocessor.h"
40#include "opt_ntp.h" 40#include "opt_ntp.h"
41 41
42#include <sys/param.h> 42#include <sys/param.h>
43#include <sys/proc.h> 43#include <sys/proc.h>
44#include <sys/systm.h> 44#include <sys/systm.h>
45#include <sys/device.h> 45#include <sys/device.h>
46#include <sys/timetc.h> 46#include <sys/timetc.h>
47 47
48#include <uvm/uvm_extern.h> 48#include <uvm/uvm_extern.h>
@@ -82,67 +82,65 @@ void lapic_dump(void); @@ -82,67 +82,65 @@ void lapic_dump(void);
82struct pic local_pic = { 82struct pic local_pic = {
83 .pic_name = "lapic", 83 .pic_name = "lapic",
84 .pic_type = PIC_LAPIC, 84 .pic_type = PIC_LAPIC,
85 .pic_lock = __SIMPLELOCK_UNLOCKED, 85 .pic_lock = __SIMPLELOCK_UNLOCKED,
86 .pic_hwmask = lapic_hwmask, 86 .pic_hwmask = lapic_hwmask,
87 .pic_hwunmask = lapic_hwunmask, 87 .pic_hwunmask = lapic_hwunmask,
88 .pic_addroute =lapic_setup, 88 .pic_addroute =lapic_setup,
89 .pic_delroute = lapic_setup, 89 .pic_delroute = lapic_setup,
90}; 90};
91 91
92static void 92static void
93lapic_map(paddr_t lapic_base) 93lapic_map(paddr_t lapic_base)
94{ 94{
95 int s; 
96 pt_entry_t *pte; 95 pt_entry_t *pte;
97 vaddr_t va = (vaddr_t)&local_apic; 96 vaddr_t va = (vaddr_t)&local_apic;
98 97
99 /* 98 /*
100 * If the CPU has an APIC MSR, use it and ignore the supplied value: 99 * If the CPU has an APIC MSR, use it and ignore the supplied value:
101 * some ACPI implementations have been observed to pass bad values. 100 * some ACPI implementations have been observed to pass bad values.
102 * Additionally, ensure that the lapic is enabled as we are committed 101 * Additionally, ensure that the lapic is enabled as we are committed
103 * to using it at this point. Be conservative and assume that the MSR 102 * to using it at this point. Be conservative and assume that the MSR
104 * is not present on the Pentium (is it?). 103 * is not present on the Pentium (is it?).
105 */ 104 */
106 if (CPUID_TO_FAMILY(curcpu()->ci_signature) >= 6) { 105 if (CPUID_TO_FAMILY(curcpu()->ci_signature) >= 6) {
107 lapic_base = (paddr_t)rdmsr(LAPIC_MSR); 106 lapic_base = (paddr_t)rdmsr(LAPIC_MSR);
108 if ((lapic_base & LAPIC_MSR_ADDR) == 0) { 107 if ((lapic_base & LAPIC_MSR_ADDR) == 0) {
109 lapic_base |= LAPIC_BASE; 108 lapic_base |= LAPIC_BASE;
110 } 109 }
111 wrmsr(LAPIC_MSR, lapic_base | LAPIC_MSR_ENABLE); 110 wrmsr(LAPIC_MSR, lapic_base | LAPIC_MSR_ENABLE);
112 lapic_base &= LAPIC_MSR_ADDR; 111 lapic_base &= LAPIC_MSR_ADDR;
113 } 112 }
114 113
115 x86_disable_intr(); 114 x86_disable_intr();
116 s = lapic_tpr; 
117 115
118 /* 116 /*
119 * Map local apic. If we have a local apic, it's safe to assume 117 * Map local apic. If we have a local apic, it's safe to assume
120 * we're on a 486 or better and can use invlpg and non-cacheable PTE's 118 * we're on a 486 or better and can use invlpg and non-cacheable PTE's
121 * 119 *
122 * Whap the PTE "by hand" rather than calling pmap_kenter_pa because 120 * Whap the PTE "by hand" rather than calling pmap_kenter_pa because
123 * the latter will attempt to invoke TLB shootdown code just as we 121 * the latter will attempt to invoke TLB shootdown code just as we
124 * might have changed the value of cpu_number().. 122 * might have changed the value of cpu_number()..
125 */ 123 */
126 124
127 pte = kvtopte(va); 125 pte = kvtopte(va);
128 *pte = lapic_base | PG_RW | PG_V | PG_N | pmap_pg_g | pmap_pg_nx; 126 *pte = lapic_base | PG_RW | PG_V | PG_N | pmap_pg_g | pmap_pg_nx;
129 invlpg(va); 127 invlpg(va);
130 128
131#ifdef MULTIPROCESSOR 129#ifdef MULTIPROCESSOR
132 cpu_init_first(); /* catch up to changed cpu_number() */ 130 cpu_init_first(); /* catch up to changed cpu_number() */
133#endif 131#endif
134 132
135 lapic_tpr = s; 133 i82489_writereg(LAPIC_TPRI, 0);
136 x86_enable_intr(); 134 x86_enable_intr();
137} 135}
138 136
139/* 137/*
140 * enable local apic 138 * enable local apic
141 */ 139 */
142void 140void
143lapic_enable(void) 141lapic_enable(void)
144{ 142{
145 i82489_writereg(LAPIC_SVR, LAPIC_SVR_ENABLE | LAPIC_SPURIOUS_VECTOR); 143 i82489_writereg(LAPIC_SVR, LAPIC_SVR_ENABLE | LAPIC_SPURIOUS_VECTOR);
146} 144}
147 145
148void 146void