Fri Jan 13 11:21:47 2017 UTC ()
iwm(4): 3165 works fine with iwlwifi-7265D-17.ucode firmware.

firmware from http://git.kernel.org/cgit/linux/kernel/git/iwlwifi/linux-firmware.git/tree/?id=be8a6fcba2e48e00674d1f35e6def56e2268039c


(nonaka)
diff -r1.1149 -r1.1150 src/distrib/sets/lists/base/mi
diff -r1.3 -r1.4 src/external/intel-fw-public/iwl7265/Makefile
diff -r1.1 -r0 src/external/intel-fw-public/iwl7265/dist/iwlwifi-7265D-16.ucode
diff -r0 -r1.1 src/external/intel-fw-public/iwl7265/dist/iwlwifi-7265D-17.ucode
diff -r1.60 -r1.61 src/sys/dev/pci/if_iwm.c
diff -r1.4 -r1.5 src/sys/dev/pci/if_iwmreg.h
diff -r1.14 -r1.15 src/sys/dev/pci/if_iwmvar.h
cvs diff -r1.1149 -r1.1150 src/distrib/sets/lists/base/mi (expand / switch to unified diff)

--- src/distrib/sets/lists/base/mi 2017/01/11 12:02:24 1.1149
+++ src/distrib/sets/lists/base/mi 2017/01/13 11:21:47 1.1150
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1# $NetBSD: mi,v 1.1149 2017/01/11 12:02:24 joerg Exp $ 1# $NetBSD: mi,v 1.1150 2017/01/13 11:21:47 nonaka Exp $
2# 2#
3# Note: Don't delete entries from here - mark them as "obsolete" instead, 3# Note: Don't delete entries from here - mark them as "obsolete" instead,
4# unless otherwise stated below. 4# unless otherwise stated below.
5# 5#
6# Note: Do not mark "old" major and major.minor shared libraries as 6# Note: Do not mark "old" major and major.minor shared libraries as
7# "obsolete"; just remove the entry, as third-party applications 7# "obsolete"; just remove the entry, as third-party applications
8# may be linked against the old major shared library, and 8# may be linked against the old major shared library, and
9# that is a symlink to the old major.minor shared library. 9# that is a symlink to the old major.minor shared library.
10# e.g., "lib<name>.so.<N>" and "lib<name>.so.<N>.<M>" 10# e.g., "lib<name>.so.<N>" and "lib<name>.so.<N>.<M>"
11# Exceptions to this rule may include shared libraries that 11# Exceptions to this rule may include shared libraries that
12# are dlopen()ed at run-time, such as extra locales, etc. 12# are dlopen()ed at run-time, such as extra locales, etc.
13# 13#
14# /usr/bin/ident is in `base-util-bin', not `base-rcs-bin' as it is used by pkgsrc 14# /usr/bin/ident is in `base-util-bin', not `base-rcs-bin' as it is used by pkgsrc
@@ -153,27 +153,28 @@ @@ -153,27 +153,28 @@
153./libdata/firmware/if_iwm/LICENSE.iwlwifi-7260-ucode base-firmware-root 153./libdata/firmware/if_iwm/LICENSE.iwlwifi-7260-ucode base-firmware-root
154./libdata/firmware/if_iwm/LICENSE.iwlwifi-7265-ucode base-firmware-root 154./libdata/firmware/if_iwm/LICENSE.iwlwifi-7265-ucode base-firmware-root
155./libdata/firmware/if_iwm/LICENSE.iwlwifi-8000-ucode base-firmware-root 155./libdata/firmware/if_iwm/LICENSE.iwlwifi-8000-ucode base-firmware-root
156./libdata/firmware/if_iwm/README.iwlwifi-3160-ucode base-firmware-root 156./libdata/firmware/if_iwm/README.iwlwifi-3160-ucode base-firmware-root
157./libdata/firmware/if_iwm/README.iwlwifi-7260-ucode base-firmware-root 157./libdata/firmware/if_iwm/README.iwlwifi-7260-ucode base-firmware-root
158./libdata/firmware/if_iwm/README.iwlwifi-7265-ucode base-firmware-root 158./libdata/firmware/if_iwm/README.iwlwifi-7265-ucode base-firmware-root
159./libdata/firmware/if_iwm/README.iwlwifi-8000-ucode base-firmware-root 159./libdata/firmware/if_iwm/README.iwlwifi-8000-ucode base-firmware-root
160./libdata/firmware/if_iwm/iwlwifi-3160-16.ucode base-firmware-root 160./libdata/firmware/if_iwm/iwlwifi-3160-16.ucode base-firmware-root
161./libdata/firmware/if_iwm/iwlwifi-3160-9.ucode base-obsolete obsolete 161./libdata/firmware/if_iwm/iwlwifi-3160-9.ucode base-obsolete obsolete
162./libdata/firmware/if_iwm/iwlwifi-7260-16.ucode base-firmware-root 162./libdata/firmware/if_iwm/iwlwifi-7260-16.ucode base-firmware-root
163./libdata/firmware/if_iwm/iwlwifi-7260-9.ucode base-obsolete obsolete 163./libdata/firmware/if_iwm/iwlwifi-7260-9.ucode base-obsolete obsolete
164./libdata/firmware/if_iwm/iwlwifi-7265-16.ucode base-firmware-root 164./libdata/firmware/if_iwm/iwlwifi-7265-16.ucode base-firmware-root
165./libdata/firmware/if_iwm/iwlwifi-7265-9.ucode base-obsolete obsolete 165./libdata/firmware/if_iwm/iwlwifi-7265-9.ucode base-obsolete obsolete
166./libdata/firmware/if_iwm/iwlwifi-7265D-16.ucode base-firmware-root 166./libdata/firmware/if_iwm/iwlwifi-7265D-16.ucode base-obsolete obsolete
 167./libdata/firmware/if_iwm/iwlwifi-7265D-17.ucode base-firmware-root
167./libdata/firmware/if_iwm/iwlwifi-8000C-16.ucode base-firmware-root 168./libdata/firmware/if_iwm/iwlwifi-8000C-16.ucode base-firmware-root
168./libdata/firmware/if_iwn base-firmware-root 169./libdata/firmware/if_iwn base-firmware-root
169./libdata/firmware/if_iwn/LICENSE.iwlwifi-100-ucode base-firmware-root 170./libdata/firmware/if_iwn/LICENSE.iwlwifi-100-ucode base-firmware-root
170./libdata/firmware/if_iwn/LICENSE.iwlwifi-1000-ucode base-firmware-root 171./libdata/firmware/if_iwn/LICENSE.iwlwifi-1000-ucode base-firmware-root
171./libdata/firmware/if_iwn/LICENSE.iwlwifi-105-ucode base-firmware-root 172./libdata/firmware/if_iwn/LICENSE.iwlwifi-105-ucode base-firmware-root
172./libdata/firmware/if_iwn/LICENSE.iwlwifi-135-ucode base-firmware-root 173./libdata/firmware/if_iwn/LICENSE.iwlwifi-135-ucode base-firmware-root
173./libdata/firmware/if_iwn/LICENSE.iwlwifi-2000-ucode base-firmware-root 174./libdata/firmware/if_iwn/LICENSE.iwlwifi-2000-ucode base-firmware-root
174./libdata/firmware/if_iwn/LICENSE.iwlwifi-2030-ucode base-firmware-root 175./libdata/firmware/if_iwn/LICENSE.iwlwifi-2030-ucode base-firmware-root
175./libdata/firmware/if_iwn/LICENSE.iwlwifi-4965-ucode base-firmware-root 176./libdata/firmware/if_iwn/LICENSE.iwlwifi-4965-ucode base-firmware-root
176./libdata/firmware/if_iwn/LICENSE.iwlwifi-5000-ucode base-firmware-root 177./libdata/firmware/if_iwn/LICENSE.iwlwifi-5000-ucode base-firmware-root
177./libdata/firmware/if_iwn/LICENSE.iwlwifi-5150-ucode base-firmware-root 178./libdata/firmware/if_iwn/LICENSE.iwlwifi-5150-ucode base-firmware-root
178./libdata/firmware/if_iwn/LICENSE.iwlwifi-6000-ucode base-firmware-root 179./libdata/firmware/if_iwn/LICENSE.iwlwifi-6000-ucode base-firmware-root
179./libdata/firmware/if_iwn/LICENSE.iwlwifi-6000g2a-ucode base-firmware-root 180./libdata/firmware/if_iwn/LICENSE.iwlwifi-6000g2a-ucode base-firmware-root
cvs diff -r1.3 -r1.4 src/external/intel-fw-public/iwl7265/Makefile (expand / switch to unified diff)

--- src/external/intel-fw-public/iwl7265/Makefile 2016/12/18 17:57:38 1.3
+++ src/external/intel-fw-public/iwl7265/Makefile 2017/01/13 11:21:47 1.4
@@ -1,10 +1,10 @@ @@ -1,10 +1,10 @@
1# $NetBSD: Makefile,v 1.3 2016/12/18 17:57:38 christos Exp $ 1# $NetBSD: Makefile,v 1.4 2017/01/13 11:21:47 nonaka Exp $
2 2
3NOMAN= # define 3NOMAN= # define
4 4
5FILES= dist/LICENSE.iwlwifi-7265-ucode dist/README.iwlwifi-7265-ucode \ 5FILES= dist/LICENSE.iwlwifi-7265-ucode dist/README.iwlwifi-7265-ucode \
6 dist/iwlwifi-7265-16.ucode dist/iwlwifi-7265D-16.ucode 6 dist/iwlwifi-7265-16.ucode dist/iwlwifi-7265D-17.ucode
7 7
8FILESDIR= /libdata/firmware/if_iwm 8FILESDIR= /libdata/firmware/if_iwm
9 9
10.include <bsd.files.mk> 10.include <bsd.files.mk>
File Deleted: src/external/intel-fw-public/iwl7265/dist/Attic/iwlwifi-7265D-16.ucode
File Added: src/external/intel-fw-public/iwl7265/dist/Attic/iwlwifi-7265D-17.ucode
IWL
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cvs diff -r1.60 -r1.61 src/sys/dev/pci/if_iwm.c (expand / switch to unified diff)

--- src/sys/dev/pci/if_iwm.c 2017/01/10 08:40:27 1.60
+++ src/sys/dev/pci/if_iwm.c 2017/01/13 11:21:47 1.61
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: if_iwm.c,v 1.60 2017/01/10 08:40:27 nonaka Exp $ */ 1/* $NetBSD: if_iwm.c,v 1.61 2017/01/13 11:21:47 nonaka Exp $ */
2/* OpenBSD: if_iwm.c,v 1.148 2016/11/19 21:07:08 stsp Exp */ 2/* OpenBSD: if_iwm.c,v 1.148 2016/11/19 21:07:08 stsp Exp */
3#define IEEE80211_NO_HT 3#define IEEE80211_NO_HT
4/* 4/*
5 * Copyright (c) 2014, 2016 genua gmbh <info@genua.de> 5 * Copyright (c) 2014, 2016 genua gmbh <info@genua.de>
6 * Author: Stefan Sperling <stsp@openbsd.org> 6 * Author: Stefan Sperling <stsp@openbsd.org>
7 * Copyright (c) 2014 Fixup Software Ltd. 7 * Copyright (c) 2014 Fixup Software Ltd.
8 * 8 *
9 * Permission to use, copy, modify, and distribute this software for any 9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above 10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies. 11 * copyright notice and this permission notice appear in all copies.
12 * 12 *
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
@@ -97,27 +97,27 @@ @@ -97,27 +97,27 @@
97 * purpose with or without fee is hereby granted, provided that the above 97 * purpose with or without fee is hereby granted, provided that the above
98 * copyright notice and this permission notice appear in all copies. 98 * copyright notice and this permission notice appear in all copies.
99 * 99 *
100 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 100 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
101 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 101 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
102 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 102 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
103 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 103 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
104 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 104 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
105 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 105 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
106 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 106 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
107 */ 107 */
108 108
109#include <sys/cdefs.h> 109#include <sys/cdefs.h>
110__KERNEL_RCSID(0, "$NetBSD: if_iwm.c,v 1.60 2017/01/10 08:40:27 nonaka Exp $"); 110__KERNEL_RCSID(0, "$NetBSD: if_iwm.c,v 1.61 2017/01/13 11:21:47 nonaka Exp $");
111 111
112#include <sys/param.h> 112#include <sys/param.h>
113#include <sys/conf.h> 113#include <sys/conf.h>
114#include <sys/kernel.h> 114#include <sys/kernel.h>
115#include <sys/kmem.h> 115#include <sys/kmem.h>
116#include <sys/mbuf.h> 116#include <sys/mbuf.h>
117#include <sys/mutex.h> 117#include <sys/mutex.h>
118#include <sys/proc.h> 118#include <sys/proc.h>
119#include <sys/socket.h> 119#include <sys/socket.h>
120#include <sys/sockio.h> 120#include <sys/sockio.h>
121#include <sys/sysctl.h> 121#include <sys/sysctl.h>
122#include <sys/systm.h> 122#include <sys/systm.h>
123 123
@@ -229,27 +229,27 @@ struct iwm_nvm_section { @@ -229,27 +229,27 @@ struct iwm_nvm_section {
229}; 229};
230 230
231struct iwm_newstate_state { 231struct iwm_newstate_state {
232 struct work ns_wk; 232 struct work ns_wk;
233 enum ieee80211_state ns_nstate; 233 enum ieee80211_state ns_nstate;
234 int ns_arg; 234 int ns_arg;
235 int ns_generation; 235 int ns_generation;
236}; 236};
237 237
238static int iwm_store_cscheme(struct iwm_softc *, uint8_t *, size_t); 238static int iwm_store_cscheme(struct iwm_softc *, uint8_t *, size_t);
239static int iwm_firmware_store_section(struct iwm_softc *, 239static int iwm_firmware_store_section(struct iwm_softc *,
240 enum iwm_ucode_type, uint8_t *, size_t); 240 enum iwm_ucode_type, uint8_t *, size_t);
241static int iwm_set_default_calib(struct iwm_softc *, const void *); 241static int iwm_set_default_calib(struct iwm_softc *, const void *);
242static int iwm_read_firmware(struct iwm_softc *); 242static int iwm_read_firmware(struct iwm_softc *, enum iwm_ucode_type);
243static uint32_t iwm_read_prph(struct iwm_softc *, uint32_t); 243static uint32_t iwm_read_prph(struct iwm_softc *, uint32_t);
244static void iwm_write_prph(struct iwm_softc *, uint32_t, uint32_t); 244static void iwm_write_prph(struct iwm_softc *, uint32_t, uint32_t);
245#ifdef IWM_DEBUG 245#ifdef IWM_DEBUG
246static int iwm_read_mem(struct iwm_softc *, uint32_t, void *, int); 246static int iwm_read_mem(struct iwm_softc *, uint32_t, void *, int);
247#endif 247#endif
248static int iwm_write_mem(struct iwm_softc *, uint32_t, const void *, int); 248static int iwm_write_mem(struct iwm_softc *, uint32_t, const void *, int);
249static int iwm_write_mem32(struct iwm_softc *, uint32_t, uint32_t); 249static int iwm_write_mem32(struct iwm_softc *, uint32_t, uint32_t);
250static int iwm_poll_bit(struct iwm_softc *, int, uint32_t, uint32_t, int); 250static int iwm_poll_bit(struct iwm_softc *, int, uint32_t, uint32_t, int);
251static int iwm_nic_lock(struct iwm_softc *); 251static int iwm_nic_lock(struct iwm_softc *);
252static void iwm_nic_unlock(struct iwm_softc *); 252static void iwm_nic_unlock(struct iwm_softc *);
253static void iwm_set_bits_mask_prph(struct iwm_softc *, uint32_t, uint32_t, 253static void iwm_set_bits_mask_prph(struct iwm_softc *, uint32_t, uint32_t,
254 uint32_t); 254 uint32_t);
255static void iwm_set_bits_prph(struct iwm_softc *, uint32_t, uint32_t); 255static void iwm_set_bits_prph(struct iwm_softc *, uint32_t, uint32_t);
@@ -464,42 +464,47 @@ static int iwm_send_update_mcc_cmd(struc @@ -464,42 +464,47 @@ static int iwm_send_update_mcc_cmd(struc
464static void iwm_tt_tx_backoff(struct iwm_softc *, uint32_t); 464static void iwm_tt_tx_backoff(struct iwm_softc *, uint32_t);
465static int iwm_init_hw(struct iwm_softc *); 465static int iwm_init_hw(struct iwm_softc *);
466static int iwm_init(struct ifnet *); 466static int iwm_init(struct ifnet *);
467static void iwm_start(struct ifnet *); 467static void iwm_start(struct ifnet *);
468static void iwm_stop(struct ifnet *, int); 468static void iwm_stop(struct ifnet *, int);
469static void iwm_watchdog(struct ifnet *); 469static void iwm_watchdog(struct ifnet *);
470static int iwm_ioctl(struct ifnet *, u_long, void *); 470static int iwm_ioctl(struct ifnet *, u_long, void *);
471#ifdef IWM_DEBUG 471#ifdef IWM_DEBUG
472static const char *iwm_desc_lookup(uint32_t); 472static const char *iwm_desc_lookup(uint32_t);
473static void iwm_nic_error(struct iwm_softc *); 473static void iwm_nic_error(struct iwm_softc *);
474static void iwm_nic_umac_error(struct iwm_softc *); 474static void iwm_nic_umac_error(struct iwm_softc *);
475#endif 475#endif
476static void iwm_notif_intr(struct iwm_softc *); 476static void iwm_notif_intr(struct iwm_softc *);
477static void iwm_softintr(void *); 
478static int iwm_intr(void *); 477static int iwm_intr(void *);
 478static void iwm_softintr(void *);
479static int iwm_preinit(struct iwm_softc *); 479static int iwm_preinit(struct iwm_softc *);
480static void iwm_attach_hook(device_t); 480static void iwm_attach_hook(device_t);
481static void iwm_attach(device_t, device_t, void *); 481static void iwm_attach(device_t, device_t, void *);
482#if 0 482#if 0
483static void iwm_init_task(void *); 483static void iwm_init_task(void *);
484static int iwm_activate(device_t, enum devact); 484static int iwm_activate(device_t, enum devact);
485static void iwm_wakeup(struct iwm_softc *); 485static void iwm_wakeup(struct iwm_softc *);
486#endif 486#endif
487static void iwm_radiotap_attach(struct iwm_softc *); 487static void iwm_radiotap_attach(struct iwm_softc *);
488static int iwm_sysctl_fw_loaded_handler(SYSCTLFN_PROTO); 488static int iwm_sysctl_fw_loaded_handler(SYSCTLFN_PROTO);
489 489
490static int iwm_sysctl_root_num; 490static int iwm_sysctl_root_num;
491static int iwm_lar_disable; 491static int iwm_lar_disable;
492 492
 493#ifndef IWM_DEFAULT_MCC
 494#define IWM_DEFAULT_MCC "ZZ"
 495#endif
 496static char iwm_default_mcc[3] = IWM_DEFAULT_MCC;
 497
493static int 498static int
494iwm_firmload(struct iwm_softc *sc) 499iwm_firmload(struct iwm_softc *sc)
495{ 500{
496 struct iwm_fw_info *fw = &sc->sc_fw; 501 struct iwm_fw_info *fw = &sc->sc_fw;
497 firmware_handle_t fwh; 502 firmware_handle_t fwh;
498 int err; 503 int err;
499 504
500 if (ISSET(sc->sc_flags, IWM_FLAG_FW_LOADED)) 505 if (ISSET(sc->sc_flags, IWM_FLAG_FW_LOADED))
501 return 0; 506 return 0;
502 507
503 /* Open firmware image. */ 508 /* Open firmware image. */
504 err = firmware_open("if_iwm", sc->sc_fwname, &fwh); 509 err = firmware_open("if_iwm", sc->sc_fwname, &fwh);
505 if (err) { 510 if (err) {
@@ -638,36 +643,40 @@ iwm_set_default_calib(struct iwm_softc * @@ -638,36 +643,40 @@ iwm_set_default_calib(struct iwm_softc *
638 DEVNAME(sc), ucode_type)); 643 DEVNAME(sc), ucode_type));
639 return EINVAL; 644 return EINVAL;
640 } 645 }
641 646
642 sc->sc_default_calib[ucode_type].flow_trigger = 647 sc->sc_default_calib[ucode_type].flow_trigger =
643 def_calib->calib.flow_trigger; 648 def_calib->calib.flow_trigger;
644 sc->sc_default_calib[ucode_type].event_trigger = 649 sc->sc_default_calib[ucode_type].event_trigger =
645 def_calib->calib.event_trigger; 650 def_calib->calib.event_trigger;
646 651
647 return 0; 652 return 0;
648} 653}
649 654
650static int 655static int
651iwm_read_firmware(struct iwm_softc *sc) 656iwm_read_firmware(struct iwm_softc *sc, enum iwm_ucode_type ucode_type)
652{ 657{
653 struct iwm_fw_info *fw = &sc->sc_fw; 658 struct iwm_fw_info *fw = &sc->sc_fw;
654 struct iwm_tlv_ucode_header *uhdr; 659 struct iwm_tlv_ucode_header *uhdr;
655 struct iwm_ucode_tlv tlv; 660 struct iwm_ucode_tlv tlv;
656 enum iwm_ucode_tlv_type tlv_type; 661 enum iwm_ucode_tlv_type tlv_type;
657 uint8_t *data; 662 uint8_t *data;
658 int err, status; 663 int err, status;
659 size_t len; 664 size_t len;
660 665
 666 if (ucode_type != IWM_UCODE_TYPE_INIT &&
 667 fw->fw_status == IWM_FW_STATUS_DONE)
 668 return 0;
 669
661 if (fw->fw_status == IWM_FW_STATUS_NONE) { 670 if (fw->fw_status == IWM_FW_STATUS_NONE) {
662 fw->fw_status = IWM_FW_STATUS_INPROGRESS; 671 fw->fw_status = IWM_FW_STATUS_INPROGRESS;
663 } else { 672 } else {
664 while (fw->fw_status == IWM_FW_STATUS_INPROGRESS) 673 while (fw->fw_status == IWM_FW_STATUS_INPROGRESS)
665 tsleep(&sc->sc_fw, 0, "iwmfwp", 0); 674 tsleep(&sc->sc_fw, 0, "iwmfwp", 0);
666 } 675 }
667 status = fw->fw_status; 676 status = fw->fw_status;
668 677
669 if (status == IWM_FW_STATUS_DONE) 678 if (status == IWM_FW_STATUS_DONE)
670 return 0; 679 return 0;
671 680
672 err = iwm_firmload(sc); 681 err = iwm_firmload(sc);
673 if (err) { 682 if (err) {
@@ -809,42 +818,44 @@ iwm_read_firmware(struct iwm_softc *sc) @@ -809,42 +818,44 @@ iwm_read_firmware(struct iwm_softc *sc)
809 } 818 }
810 sc->sc_fw_phy_config = le32toh(*(uint32_t *)tlv_data); 819 sc->sc_fw_phy_config = le32toh(*(uint32_t *)tlv_data);
811 break; 820 break;
812 821
813 case IWM_UCODE_TLV_API_CHANGES_SET: { 822 case IWM_UCODE_TLV_API_CHANGES_SET: {
814 struct iwm_ucode_api *api; 823 struct iwm_ucode_api *api;
815 if (tlv_len != sizeof(*api)) { 824 if (tlv_len != sizeof(*api)) {
816 err = EINVAL; 825 err = EINVAL;
817 goto parse_out; 826 goto parse_out;
818 } 827 }
819 api = (struct iwm_ucode_api *)tlv_data; 828 api = (struct iwm_ucode_api *)tlv_data;
820 /* Flags may exceed 32 bits in future firmware. */ 829 /* Flags may exceed 32 bits in future firmware. */
821 if (le32toh(api->api_index) > 0) { 830 if (le32toh(api->api_index) > 0) {
 831 err = EINVAL;
822 goto parse_out; 832 goto parse_out;
823 } 833 }
824 sc->sc_ucode_api = le32toh(api->api_flags); 834 sc->sc_ucode_api = le32toh(api->api_flags);
825 break; 835 break;
826 } 836 }
827 837
828 case IWM_UCODE_TLV_ENABLED_CAPABILITIES: { 838 case IWM_UCODE_TLV_ENABLED_CAPABILITIES: {
829 struct iwm_ucode_capa *capa; 839 struct iwm_ucode_capa *capa;
830 int idx, i; 840 int idx, i;
831 if (tlv_len != sizeof(*capa)) { 841 if (tlv_len != sizeof(*capa)) {
832 err = EINVAL; 842 err = EINVAL;
833 goto parse_out; 843 goto parse_out;
834 } 844 }
835 capa = (struct iwm_ucode_capa *)tlv_data; 845 capa = (struct iwm_ucode_capa *)tlv_data;
836 idx = le32toh(capa->api_index); 846 idx = le32toh(capa->api_index);
837 if (idx >= howmany(IWM_NUM_UCODE_TLV_CAPA, 32)) { 847 if (idx >= howmany(IWM_NUM_UCODE_TLV_CAPA, 32)) {
 848 err = EINVAL;
838 goto parse_out; 849 goto parse_out;
839 } 850 }
840 for (i = 0; i < 32; i++) { 851 for (i = 0; i < 32; i++) {
841 if (!ISSET(le32toh(capa->api_capa), __BIT(i))) 852 if (!ISSET(le32toh(capa->api_capa), __BIT(i)))
842 continue; 853 continue;
843 setbit(sc->sc_enabled_capa, i + (32 * idx)); 854 setbit(sc->sc_enabled_capa, i + (32 * idx));
844 } 855 }
845 break; 856 break;
846 } 857 }
847 858
848 case IWM_UCODE_TLV_FW_UNDOCUMENTED1: 859 case IWM_UCODE_TLV_FW_UNDOCUMENTED1:
849 case IWM_UCODE_TLV_SDIO_ADMA_ADDR: 860 case IWM_UCODE_TLV_SDIO_ADMA_ADDR:
850 case IWM_UCODE_TLV_FW_GSCAN_CAPA: 861 case IWM_UCODE_TLV_FW_GSCAN_CAPA:
@@ -1009,27 +1020,27 @@ iwm_nic_lock(struct iwm_softc *sc) @@ -1009,27 +1020,27 @@ iwm_nic_lock(struct iwm_softc *sc)
1009 1020
1010 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL, 1021 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL,
1011 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1022 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1012 1023
1013 if (sc->sc_device_family == IWM_DEVICE_FAMILY_8000) 1024 if (sc->sc_device_family == IWM_DEVICE_FAMILY_8000)
1014 DELAY(2); 1025 DELAY(2);
1015 1026
1016 if (iwm_poll_bit(sc, IWM_CSR_GP_CNTRL, 1027 if (iwm_poll_bit(sc, IWM_CSR_GP_CNTRL,
1017 IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 1028 IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1018 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY 1029 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
1019 | IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP, 15000)) { 1030 | IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP, 15000)) {
1020 rv = 1; 1031 rv = 1;
1021 } else { 1032 } else {
1022 aprint_error_dev(sc->sc_dev, "device timeout\n"); 1033 aprint_error_dev(sc->sc_dev, "resetting device via NMI\n");
1023 IWM_WRITE(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_FORCE_NMI); 1034 IWM_WRITE(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_FORCE_NMI);
1024 } 1035 }
1025 1036
1026 return rv; 1037 return rv;
1027} 1038}
1028 1039
1029static void 1040static void
1030iwm_nic_unlock(struct iwm_softc *sc) 1041iwm_nic_unlock(struct iwm_softc *sc)
1031{ 1042{
1032 1043
1033 if (sc->sc_cmd_hold_nic_awake) 1044 if (sc->sc_cmd_hold_nic_awake)
1034 return; 1045 return;
1035 1046
@@ -1218,27 +1229,27 @@ iwm_free_rx_ring(struct iwm_softc *sc, s @@ -1218,27 +1229,27 @@ iwm_free_rx_ring(struct iwm_softc *sc, s
1218 } 1229 }
1219 if (data->map != NULL) { 1230 if (data->map != NULL) {
1220 bus_dmamap_destroy(sc->sc_dmat, data->map); 1231 bus_dmamap_destroy(sc->sc_dmat, data->map);
1221 data->map = NULL; 1232 data->map = NULL;
1222 } 1233 }
1223 } 1234 }
1224} 1235}
1225 1236
1226static int 1237static int
1227iwm_alloc_tx_ring(struct iwm_softc *sc, struct iwm_tx_ring *ring, int qid) 1238iwm_alloc_tx_ring(struct iwm_softc *sc, struct iwm_tx_ring *ring, int qid)
1228{ 1239{
1229 bus_addr_t paddr; 1240 bus_addr_t paddr;
1230 bus_size_t size; 1241 bus_size_t size;
1231 int i, err; 1242 int i, err, nsegs;
1232 1243
1233 ring->qid = qid; 1244 ring->qid = qid;
1234 ring->queued = 0; 1245 ring->queued = 0;
1235 ring->cur = 0; 1246 ring->cur = 0;
1236 1247
1237 /* Allocate TX descriptors (256-byte aligned). */ 1248 /* Allocate TX descriptors (256-byte aligned). */
1238 size = IWM_TX_RING_COUNT * sizeof (struct iwm_tfd); 1249 size = IWM_TX_RING_COUNT * sizeof (struct iwm_tfd);
1239 err = iwm_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, size, 256); 1250 err = iwm_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, size, 256);
1240 if (err) { 1251 if (err) {
1241 aprint_error_dev(sc->sc_dev, 1252 aprint_error_dev(sc->sc_dev,
1242 "could not allocate TX ring DMA memory\n"); 1253 "could not allocate TX ring DMA memory\n");
1243 goto fail; 1254 goto fail;
1244 } 1255 }
@@ -1261,33 +1272,35 @@ iwm_alloc_tx_ring(struct iwm_softc *sc,  @@ -1261,33 +1272,35 @@ iwm_alloc_tx_ring(struct iwm_softc *sc,
1261 ring->cmd = ring->cmd_dma.vaddr; 1272 ring->cmd = ring->cmd_dma.vaddr;
1262 1273
1263 paddr = ring->cmd_dma.paddr; 1274 paddr = ring->cmd_dma.paddr;
1264 for (i = 0; i < IWM_TX_RING_COUNT; i++) { 1275 for (i = 0; i < IWM_TX_RING_COUNT; i++) {
1265 struct iwm_tx_data *data = &ring->data[i]; 1276 struct iwm_tx_data *data = &ring->data[i];
1266 size_t mapsize; 1277 size_t mapsize;
1267 1278
1268 data->cmd_paddr = paddr; 1279 data->cmd_paddr = paddr;
1269 data->scratch_paddr = paddr + sizeof(struct iwm_cmd_header) 1280 data->scratch_paddr = paddr + sizeof(struct iwm_cmd_header)
1270 + offsetof(struct iwm_tx_cmd, scratch); 1281 + offsetof(struct iwm_tx_cmd, scratch);
1271 paddr += sizeof(struct iwm_device_cmd); 1282 paddr += sizeof(struct iwm_device_cmd);
1272 1283
1273 /* FW commands may require more mapped space than packets. */ 1284 /* FW commands may require more mapped space than packets. */
1274 if (qid == IWM_CMD_QUEUE) 1285 if (qid == IWM_CMD_QUEUE) {
1275 mapsize = (sizeof(struct iwm_cmd_header) + 1286 mapsize = IWM_RBUF_SIZE;
1276 IWM_MAX_CMD_PAYLOAD_SIZE); 1287 nsegs = 1;
1277 else 1288 } else {
1278 mapsize = MCLBYTES; 1289 mapsize = MCLBYTES;
1279 err = bus_dmamap_create(sc->sc_dmat, mapsize, 1290 nsegs = IWM_NUM_OF_TBS - 2;
1280 IWM_NUM_OF_TBS - 2, mapsize, 0, BUS_DMA_NOWAIT, &data->map); 1291 }
 1292 err = bus_dmamap_create(sc->sc_dmat, mapsize, nsegs, mapsize,
 1293 0, BUS_DMA_NOWAIT, &data->map);
1281 if (err) { 1294 if (err) {
1282 aprint_error_dev(sc->sc_dev, 1295 aprint_error_dev(sc->sc_dev,
1283 "could not create TX buf DMA map\n"); 1296 "could not create TX buf DMA map\n");
1284 goto fail; 1297 goto fail;
1285 } 1298 }
1286 } 1299 }
1287 KASSERT(paddr == ring->cmd_dma.paddr + size); 1300 KASSERT(paddr == ring->cmd_dma.paddr + size);
1288 return 0; 1301 return 0;
1289 1302
1290fail: iwm_free_tx_ring(sc, ring); 1303fail: iwm_free_tx_ring(sc, ring);
1291 return err; 1304 return err;
1292} 1305}
1293 1306
@@ -1545,29 +1558,30 @@ iwm_apm_config(struct iwm_softc *sc) @@ -1545,29 +1558,30 @@ iwm_apm_config(struct iwm_softc *sc)
1545} 1558}
1546 1559
1547/* 1560/*
1548 * Start up NIC's basic functionality after it has been reset 1561 * Start up NIC's basic functionality after it has been reset
1549 * e.g. after platform boot or shutdown. 1562 * e.g. after platform boot or shutdown.
1550 * NOTE: This does not load uCode nor start the embedded processor 1563 * NOTE: This does not load uCode nor start the embedded processor
1551 */ 1564 */
1552static int 1565static int
1553iwm_apm_init(struct iwm_softc *sc) 1566iwm_apm_init(struct iwm_softc *sc)
1554{ 1567{
1555 int err = 0; 1568 int err = 0;
1556 1569
1557 /* Disable L0S exit timer (platform NMI workaround) */ 1570 /* Disable L0S exit timer (platform NMI workaround) */
1558 if (sc->sc_device_family != IWM_DEVICE_FAMILY_8000) 1571 if (sc->sc_device_family != IWM_DEVICE_FAMILY_8000) {
1559 IWM_SETBITS(sc, IWM_CSR_GIO_CHICKEN_BITS, 1572 IWM_SETBITS(sc, IWM_CSR_GIO_CHICKEN_BITS,
1560 IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 1573 IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 1574 }
1561 1575
1562 /* 1576 /*
1563 * Disable L0s without affecting L1; 1577 * Disable L0s without affecting L1;
1564 * don't wait for ICH L0s (ICH bug W/A) 1578 * don't wait for ICH L0s (ICH bug W/A)
1565 */ 1579 */
1566 IWM_SETBITS(sc, IWM_CSR_GIO_CHICKEN_BITS, 1580 IWM_SETBITS(sc, IWM_CSR_GIO_CHICKEN_BITS,
1567 IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 1581 IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1568 1582
1569 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 1583 /* Set FH wait threshold to maximum (HW error during stress W/A) */
1570 IWM_SETBITS(sc, IWM_CSR_DBG_HPET_MEM_REG, IWM_CSR_DBG_HPET_MEM_REG_VAL); 1584 IWM_SETBITS(sc, IWM_CSR_DBG_HPET_MEM_REG, IWM_CSR_DBG_HPET_MEM_REG_VAL);
1571 1585
1572 /* 1586 /*
1573 * Enable HAP INTA (interrupt from management bus) to 1587 * Enable HAP INTA (interrupt from management bus) to
@@ -1715,31 +1729,35 @@ iwm_stop_device(struct iwm_softc *sc) @@ -1715,31 +1729,35 @@ iwm_stop_device(struct iwm_softc *sc)
1715 break; 1729 break;
1716 DELAY(20); 1730 DELAY(20);
1717 } 1731 }
1718 } 1732 }
1719 iwm_nic_unlock(sc); 1733 iwm_nic_unlock(sc);
1720 } 1734 }
1721 iwm_disable_rx_dma(sc); 1735 iwm_disable_rx_dma(sc);
1722 1736
1723 iwm_reset_rx_ring(sc, &sc->rxq); 1737 iwm_reset_rx_ring(sc, &sc->rxq);
1724 1738
1725 for (qid = 0; qid < __arraycount(sc->txq); qid++) 1739 for (qid = 0; qid < __arraycount(sc->txq); qid++)
1726 iwm_reset_tx_ring(sc, &sc->txq[qid]); 1740 iwm_reset_tx_ring(sc, &sc->txq[qid]);
1727 1741
1728 /* 1742 if (sc->sc_device_family == IWM_DEVICE_FAMILY_7000) {
1729 * Power-down device's busmaster DMA clocks 1743 /* Power-down device's busmaster DMA clocks */
1730 */ 1744 if (iwm_nic_lock(sc)) {
1731 iwm_write_prph(sc, IWM_APMG_CLK_DIS_REG, IWM_APMG_CLK_VAL_DMA_CLK_RQT); 1745 iwm_write_prph(sc, IWM_APMG_CLK_DIS_REG,
1732 DELAY(5); 1746 IWM_APMG_CLK_VAL_DMA_CLK_RQT);
 1747 DELAY(5);
 1748 iwm_nic_unlock(sc);
 1749 }
 1750 }
1733 1751
1734 /* Make sure (redundant) we've released our request to stay awake */ 1752 /* Make sure (redundant) we've released our request to stay awake */
1735 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL, 1753 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL,
1736 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1754 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1737 1755
1738 /* Stop the device, and put it in low power state */ 1756 /* Stop the device, and put it in low power state */
1739 iwm_apm_stop(sc); 1757 iwm_apm_stop(sc);
1740 1758
1741 /* 1759 /*
1742 * Upon stop, the APM issues an interrupt if HW RF kill is set. 1760 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1743 * Clean again the interrupt here 1761 * Clean again the interrupt here
1744 */ 1762 */
1745 iwm_disable_interrupts(sc); 1763 iwm_disable_interrupts(sc);
@@ -1775,30 +1793,31 @@ iwm_nic_config(struct iwm_softc *sc) @@ -1775,30 +1793,31 @@ iwm_nic_config(struct iwm_softc *sc)
1775 reg_val |= radio_cfg_step << IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP; 1793 reg_val |= radio_cfg_step << IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP;
1776 reg_val |= radio_cfg_dash << IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH; 1794 reg_val |= radio_cfg_dash << IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH;
1777 1795
1778 IWM_WRITE(sc, IWM_CSR_HW_IF_CONFIG_REG, reg_val); 1796 IWM_WRITE(sc, IWM_CSR_HW_IF_CONFIG_REG, reg_val);
1779 1797
1780 DPRINTF(("Radio type=0x%x-0x%x-0x%x\n", radio_cfg_type, 1798 DPRINTF(("Radio type=0x%x-0x%x-0x%x\n", radio_cfg_type,
1781 radio_cfg_step, radio_cfg_dash)); 1799 radio_cfg_step, radio_cfg_dash));
1782 1800
1783 /* 1801 /*
1784 * W/A : NIC is stuck in a reset state after Early PCIe power off 1802 * W/A : NIC is stuck in a reset state after Early PCIe power off
1785 * (PCIe power is lost before PERST# is asserted), causing ME FW 1803 * (PCIe power is lost before PERST# is asserted), causing ME FW
1786 * to lose ownership and not being able to obtain it back. 1804 * to lose ownership and not being able to obtain it back.
1787 */ 1805 */
1788 if (sc->sc_device_family == IWM_DEVICE_FAMILY_7000) 1806 if (sc->sc_device_family == IWM_DEVICE_FAMILY_7000) {
1789 iwm_set_bits_mask_prph(sc, IWM_APMG_PS_CTRL_REG, 1807 iwm_set_bits_mask_prph(sc, IWM_APMG_PS_CTRL_REG,
1790 IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS, 1808 IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
1791 ~IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS); 1809 ~IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
 1810 }
1792} 1811}
1793 1812
1794static int 1813static int
1795iwm_nic_rx_init(struct iwm_softc *sc) 1814iwm_nic_rx_init(struct iwm_softc *sc)
1796{ 1815{
1797 if (!iwm_nic_lock(sc)) 1816 if (!iwm_nic_lock(sc))
1798 return EBUSY; 1817 return EBUSY;
1799 1818
1800 memset(sc->rxq.stat, 0, sizeof(*sc->rxq.stat)); 1819 memset(sc->rxq.stat, 0, sizeof(*sc->rxq.stat));
1801 bus_dmamap_sync(sc->sc_dmat, sc->rxq.stat_dma.map, 1820 bus_dmamap_sync(sc->sc_dmat, sc->rxq.stat_dma.map,
1802 0, sc->rxq.stat_dma.size, 1821 0, sc->rxq.stat_dma.size,
1803 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1822 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1804 1823
@@ -1812,28 +1831,28 @@ iwm_nic_rx_init(struct iwm_softc *sc) @@ -1812,28 +1831,28 @@ iwm_nic_rx_init(struct iwm_softc *sc)
1812 IWM_WRITE(sc, 1831 IWM_WRITE(sc,
1813 IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG, sc->rxq.desc_dma.paddr >> 8); 1832 IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG, sc->rxq.desc_dma.paddr >> 8);
1814 1833
1815 /* Set physical address of RX status (16-byte aligned). */ 1834 /* Set physical address of RX status (16-byte aligned). */
1816 IWM_WRITE(sc, 1835 IWM_WRITE(sc,
1817 IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG, sc->rxq.stat_dma.paddr >> 4); 1836 IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG, sc->rxq.stat_dma.paddr >> 4);
1818 1837
1819 /* Enable RX. */ 1838 /* Enable RX. */
1820 IWM_WRITE(sc, IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG, 1839 IWM_WRITE(sc, IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG,
1821 IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | 1840 IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
1822 IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | /* HW bug */ 1841 IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | /* HW bug */
1823 IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | 1842 IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
1824 IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK | 1843 IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
1825 (IWM_RX_RB_TIMEOUT << IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) | 
1826 IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K | 1844 IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K |
 1845 (IWM_RX_RB_TIMEOUT << IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) |
1827 IWM_RX_QUEUE_SIZE_LOG << IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS); 1846 IWM_RX_QUEUE_SIZE_LOG << IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS);
1828 1847
1829 IWM_WRITE_1(sc, IWM_CSR_INT_COALESCING, IWM_HOST_INT_TIMEOUT_DEF); 1848 IWM_WRITE_1(sc, IWM_CSR_INT_COALESCING, IWM_HOST_INT_TIMEOUT_DEF);
1830 1849
1831 /* W/A for interrupt coalescing bug in 7260 and 3160 */ 1850 /* W/A for interrupt coalescing bug in 7260 and 3160 */
1832 if (sc->host_interrupt_operation_mode) 1851 if (sc->host_interrupt_operation_mode)
1833 IWM_SETBITS(sc, IWM_CSR_INT_COALESCING, IWM_HOST_INT_OPER_MODE); 1852 IWM_SETBITS(sc, IWM_CSR_INT_COALESCING, IWM_HOST_INT_OPER_MODE);
1834 1853
1835 /* 1854 /*
1836 * This value should initially be 0 (before preparing any RBs), 1855 * This value should initially be 0 (before preparing any RBs),
1837 * and should be 8 after preparing the first 8 RBs (for example). 1856 * and should be 8 after preparing the first 8 RBs (for example).
1838 */ 1857 */
1839 IWM_WRITE(sc, IWM_FH_RSCSR_CHNL0_WPTR, 8); 1858 IWM_WRITE(sc, IWM_FH_RSCSR_CHNL0_WPTR, 8);
@@ -1870,30 +1889,31 @@ iwm_nic_tx_init(struct iwm_softc *sc) @@ -1870,30 +1889,31 @@ iwm_nic_tx_init(struct iwm_softc *sc)
1870 iwm_write_prph(sc, IWM_SCD_GP_CTRL, IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE); 1889 iwm_write_prph(sc, IWM_SCD_GP_CTRL, IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE);
1871 1890
1872 iwm_nic_unlock(sc); 1891 iwm_nic_unlock(sc);
1873 1892
1874 return 0; 1893 return 0;
1875} 1894}
1876 1895
1877static int 1896static int
1878iwm_nic_init(struct iwm_softc *sc) 1897iwm_nic_init(struct iwm_softc *sc)
1879{ 1898{
1880 int err; 1899 int err;
1881 1900
1882 iwm_apm_init(sc); 1901 iwm_apm_init(sc);
1883 if (sc->sc_device_family == IWM_DEVICE_FAMILY_7000) 1902 if (sc->sc_device_family == IWM_DEVICE_FAMILY_7000) {
1884 iwm_set_bits_mask_prph(sc, IWM_APMG_PS_CTRL_REG, 1903 iwm_set_bits_mask_prph(sc, IWM_APMG_PS_CTRL_REG,
1885 IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 1904 IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
1886 ~IWM_APMG_PS_CTRL_MSK_PWR_SRC); 1905 ~IWM_APMG_PS_CTRL_MSK_PWR_SRC);
 1906 }
1887 1907
1888 iwm_nic_config(sc); 1908 iwm_nic_config(sc);
1889 1909
1890 err = iwm_nic_rx_init(sc); 1910 err = iwm_nic_rx_init(sc);
1891 if (err) 1911 if (err)
1892 return err; 1912 return err;
1893 1913
1894 err = iwm_nic_tx_init(sc); 1914 err = iwm_nic_tx_init(sc);
1895 if (err) 1915 if (err)
1896 return err; 1916 return err;
1897 1917
1898 DPRINTF(("shadow registers enabled\n")); 1918 DPRINTF(("shadow registers enabled\n"));
1899 IWM_SETBITS(sc, IWM_CSR_MAC_SHADOW_REG_CTRL, 0x800fffff); 1919 IWM_SETBITS(sc, IWM_CSR_MAC_SHADOW_REG_CTRL, 0x800fffff);
@@ -1913,43 +1933,50 @@ iwm_enable_txq(struct iwm_softc *sc, int @@ -1913,43 +1933,50 @@ iwm_enable_txq(struct iwm_softc *sc, int
1913{ 1933{
1914 if (!iwm_nic_lock(sc)) { 1934 if (!iwm_nic_lock(sc)) {
1915 DPRINTF(("%s: cannot enable txq %d\n", DEVNAME(sc), qid)); 1935 DPRINTF(("%s: cannot enable txq %d\n", DEVNAME(sc), qid));
1916 return EBUSY; 1936 return EBUSY;
1917 } 1937 }
1918 1938
1919 IWM_WRITE(sc, IWM_HBUS_TARG_WRPTR, qid << 8 | 0); 1939 IWM_WRITE(sc, IWM_HBUS_TARG_WRPTR, qid << 8 | 0);
1920 1940
1921 if (qid == IWM_CMD_QUEUE) { 1941 if (qid == IWM_CMD_QUEUE) {
1922 iwm_write_prph(sc, IWM_SCD_QUEUE_STATUS_BITS(qid), 1942 iwm_write_prph(sc, IWM_SCD_QUEUE_STATUS_BITS(qid),
1923 (0 << IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE) 1943 (0 << IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE)
1924 | (1 << IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); 1944 | (1 << IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
1925 1945
 1946 iwm_nic_unlock(sc);
 1947
1926 iwm_clear_bits_prph(sc, IWM_SCD_AGGR_SEL, (1 << qid)); 1948 iwm_clear_bits_prph(sc, IWM_SCD_AGGR_SEL, (1 << qid));
1927 1949
 1950 if (!iwm_nic_lock(sc))
 1951 return EBUSY;
1928 iwm_write_prph(sc, IWM_SCD_QUEUE_RDPTR(qid), 0); 1952 iwm_write_prph(sc, IWM_SCD_QUEUE_RDPTR(qid), 0);
 1953 iwm_nic_unlock(sc);
1929 1954
1930 iwm_write_mem32(sc, 1955 iwm_write_mem32(sc,
1931 sc->sched_base + IWM_SCD_CONTEXT_QUEUE_OFFSET(qid), 0); 1956 sc->sched_base + IWM_SCD_CONTEXT_QUEUE_OFFSET(qid), 0);
1932 1957
1933 /* Set scheduler window size and frame limit. */ 1958 /* Set scheduler window size and frame limit. */
1934 iwm_write_mem32(sc, 1959 iwm_write_mem32(sc,
1935 sc->sched_base + IWM_SCD_CONTEXT_QUEUE_OFFSET(qid) + 1960 sc->sched_base + IWM_SCD_CONTEXT_QUEUE_OFFSET(qid) +
1936 sizeof(uint32_t), 1961 sizeof(uint32_t),
1937 ((IWM_FRAME_LIMIT << IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & 1962 ((IWM_FRAME_LIMIT << IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1938 IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | 1963 IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1939 ((IWM_FRAME_LIMIT 1964 ((IWM_FRAME_LIMIT
1940 << IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 1965 << IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1941 IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 1966 IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1942 1967
 1968 if (!iwm_nic_lock(sc))
 1969 return EBUSY;
1943 iwm_write_prph(sc, IWM_SCD_QUEUE_STATUS_BITS(qid), 1970 iwm_write_prph(sc, IWM_SCD_QUEUE_STATUS_BITS(qid),
1944 (1 << IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE) | 1971 (1 << IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1945 (fifo << IWM_SCD_QUEUE_STTS_REG_POS_TXF) | 1972 (fifo << IWM_SCD_QUEUE_STTS_REG_POS_TXF) |
1946 (1 << IWM_SCD_QUEUE_STTS_REG_POS_WSL) | 1973 (1 << IWM_SCD_QUEUE_STTS_REG_POS_WSL) |
1947 IWM_SCD_QUEUE_STTS_REG_MSK); 1974 IWM_SCD_QUEUE_STTS_REG_MSK);
1948 } else { 1975 } else {
1949 struct iwm_scd_txq_cfg_cmd cmd; 1976 struct iwm_scd_txq_cfg_cmd cmd;
1950 int err; 1977 int err;
1951 1978
1952 iwm_nic_unlock(sc); 1979 iwm_nic_unlock(sc);
1953 1980
1954 memset(&cmd, 0, sizeof(cmd)); 1981 memset(&cmd, 0, sizeof(cmd));
1955 cmd.scd_queue = qid; 1982 cmd.scd_queue = qid;
@@ -1971,52 +1998,53 @@ iwm_enable_txq(struct iwm_softc *sc, int @@ -1971,52 +1998,53 @@ iwm_enable_txq(struct iwm_softc *sc, int
1971 iwm_write_prph(sc, IWM_SCD_EN_CTRL, 1998 iwm_write_prph(sc, IWM_SCD_EN_CTRL,
1972 iwm_read_prph(sc, IWM_SCD_EN_CTRL) | qid); 1999 iwm_read_prph(sc, IWM_SCD_EN_CTRL) | qid);
1973 2000
1974 iwm_nic_unlock(sc); 2001 iwm_nic_unlock(sc);
1975 2002
1976 DPRINTF(("enabled txq %d FIFO %d\n", qid, fifo)); 2003 DPRINTF(("enabled txq %d FIFO %d\n", qid, fifo));
1977 2004
1978 return 0; 2005 return 0;
1979} 2006}
1980 2007
1981static int 2008static int
1982iwm_post_alive(struct iwm_softc *sc) 2009iwm_post_alive(struct iwm_softc *sc)
1983{ 2010{
1984 int nwords; 2011 int nwords = (IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND -
 2012 IWM_SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(uint32_t);
1985 int err, chnl; 2013 int err, chnl;
1986 uint32_t base; 2014 uint32_t base;
1987 2015
1988 if (!iwm_nic_lock(sc)) 2016 if (!iwm_nic_lock(sc))
1989 return EBUSY; 2017 return EBUSY;
1990 2018
1991 base = iwm_read_prph(sc, IWM_SCD_SRAM_BASE_ADDR); 2019 base = iwm_read_prph(sc, IWM_SCD_SRAM_BASE_ADDR);
1992 if (sc->sched_base != base) { 2020 if (sc->sched_base != base) {
1993 DPRINTF(("%s: sched addr mismatch: 0x%08x != 0x%08x\n", 2021 DPRINTF(("%s: sched addr mismatch: 0x%08x != 0x%08x\n",
1994 DEVNAME(sc), sc->sched_base, base)); 2022 DEVNAME(sc), sc->sched_base, base));
1995 err = EINVAL; 2023 sc->sched_base = base;
1996 goto out; 
1997 } 2024 }
1998 2025
 2026 iwm_nic_unlock(sc);
 2027
1999 iwm_ict_reset(sc); 2028 iwm_ict_reset(sc);
2000 2029
2001 /* Clear TX scheduler state in SRAM. */ 2030 /* Clear TX scheduler state in SRAM. */
2002 nwords = (IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND - 
2003 IWM_SCD_CONTEXT_MEM_LOWER_BOUND) 
2004 / sizeof(uint32_t); 
2005 err = iwm_write_mem(sc, 2031 err = iwm_write_mem(sc,
2006 sc->sched_base + IWM_SCD_CONTEXT_MEM_LOWER_BOUND, 2032 sc->sched_base + IWM_SCD_CONTEXT_MEM_LOWER_BOUND, NULL, nwords);
2007 NULL, nwords); 
2008 if (err) 2033 if (err)
2009 goto out; 2034 return err;
 2035
 2036 if (!iwm_nic_lock(sc))
 2037 return EBUSY;
2010 2038
2011 /* Set physical address of TX scheduler rings (1KB aligned). */ 2039 /* Set physical address of TX scheduler rings (1KB aligned). */
2012 iwm_write_prph(sc, IWM_SCD_DRAM_BASE_ADDR, sc->sched_dma.paddr >> 10); 2040 iwm_write_prph(sc, IWM_SCD_DRAM_BASE_ADDR, sc->sched_dma.paddr >> 10);
2013 2041
2014 iwm_write_prph(sc, IWM_SCD_CHAINEXT_EN, 0); 2042 iwm_write_prph(sc, IWM_SCD_CHAINEXT_EN, 0);
2015 2043
2016 iwm_nic_unlock(sc); 2044 iwm_nic_unlock(sc);
2017 2045
2018 /* enable command channel */ 2046 /* enable command channel */
2019 err = iwm_enable_txq(sc, 0 /* unused */, IWM_CMD_QUEUE, 7); 2047 err = iwm_enable_txq(sc, 0 /* unused */, IWM_CMD_QUEUE, 7);
2020 if (err) 2048 if (err)
2021 return err; 2049 return err;
2022 2050
@@ -2027,33 +2055,34 @@ iwm_post_alive(struct iwm_softc *sc) @@ -2027,33 +2055,34 @@ iwm_post_alive(struct iwm_softc *sc)
2027 iwm_write_prph(sc, IWM_SCD_TXFACT, 0xff); 2055 iwm_write_prph(sc, IWM_SCD_TXFACT, 0xff);
2028 2056
2029 /* Enable DMA channels. */ 2057 /* Enable DMA channels. */
2030 for (chnl = 0; chnl < IWM_FH_TCSR_CHNL_NUM; chnl++) { 2058 for (chnl = 0; chnl < IWM_FH_TCSR_CHNL_NUM; chnl++) {
2031 IWM_WRITE(sc, IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl), 2059 IWM_WRITE(sc, IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl),
2032 IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 2060 IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
2033 IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); 2061 IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
2034 } 2062 }
2035 2063
2036 IWM_SETBITS(sc, IWM_FH_TX_CHICKEN_BITS_REG, 2064 IWM_SETBITS(sc, IWM_FH_TX_CHICKEN_BITS_REG,
2037 IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); 2065 IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
2038 2066
2039 /* Enable L1-Active */ 2067 /* Enable L1-Active */
2040 if (sc->sc_device_family != IWM_DEVICE_FAMILY_8000) 2068 if (sc->sc_device_family != IWM_DEVICE_FAMILY_8000) {
2041 iwm_clear_bits_prph(sc, IWM_APMG_PCIDEV_STT_REG, 2069 iwm_clear_bits_prph(sc, IWM_APMG_PCIDEV_STT_REG,
2042 IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 2070 IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 2071 }
2043 2072
2044 out: 
2045 iwm_nic_unlock(sc); 2073 iwm_nic_unlock(sc);
2046 return err; 2074
 2075 return 0;
2047} 2076}
2048 2077
2049static struct iwm_phy_db_entry * 2078static struct iwm_phy_db_entry *
2050iwm_phy_db_get_section(struct iwm_softc *sc, enum iwm_phy_db_section_type type, 2079iwm_phy_db_get_section(struct iwm_softc *sc, enum iwm_phy_db_section_type type,
2051 uint16_t chg_id) 2080 uint16_t chg_id)
2052{ 2081{
2053 struct iwm_phy_db *phy_db = &sc->sc_phy_db; 2082 struct iwm_phy_db *phy_db = &sc->sc_phy_db;
2054 2083
2055 if (type >= IWM_PHY_DB_MAX) 2084 if (type >= IWM_PHY_DB_MAX)
2056 return NULL; 2085 return NULL;
2057 2086
2058 switch (type) { 2087 switch (type) {
2059 case IWM_PHY_DB_CFG: 2088 case IWM_PHY_DB_CFG:
@@ -2398,27 +2427,28 @@ iwm_protect_session(struct iwm_softc *sc @@ -2398,27 +2427,28 @@ iwm_protect_session(struct iwm_softc *sc
2398static const int iwm_nvm_to_read[] = { 2427static const int iwm_nvm_to_read[] = {
2399 IWM_NVM_SECTION_TYPE_HW, 2428 IWM_NVM_SECTION_TYPE_HW,
2400 IWM_NVM_SECTION_TYPE_SW, 2429 IWM_NVM_SECTION_TYPE_SW,
2401 IWM_NVM_SECTION_TYPE_REGULATORY, 2430 IWM_NVM_SECTION_TYPE_REGULATORY,
2402 IWM_NVM_SECTION_TYPE_CALIBRATION, 2431 IWM_NVM_SECTION_TYPE_CALIBRATION,
2403 IWM_NVM_SECTION_TYPE_PRODUCTION, 2432 IWM_NVM_SECTION_TYPE_PRODUCTION,
2404 IWM_NVM_SECTION_TYPE_HW_8000, 2433 IWM_NVM_SECTION_TYPE_HW_8000,
2405 IWM_NVM_SECTION_TYPE_MAC_OVERRIDE, 2434 IWM_NVM_SECTION_TYPE_MAC_OVERRIDE,
2406 IWM_NVM_SECTION_TYPE_PHY_SKU, 2435 IWM_NVM_SECTION_TYPE_PHY_SKU,
2407}; 2436};
2408 2437
2409/* Default NVM size to read */ 2438/* Default NVM size to read */
2410#define IWM_NVM_DEFAULT_CHUNK_SIZE (2*1024) 2439#define IWM_NVM_DEFAULT_CHUNK_SIZE (2*1024)
2411#define IWM_MAX_NVM_SECTION_SIZE 8192 2440#define IWM_MAX_NVM_SECTION_SIZE_7000 (16 * 512 * sizeof(uint16_t)) /*16 KB*/
 2441#define IWM_MAX_NVM_SECTION_SIZE_8000 (32 * 512 * sizeof(uint16_t)) /*32 KB*/
2412 2442
2413#define IWM_NVM_WRITE_OPCODE 1 2443#define IWM_NVM_WRITE_OPCODE 1
2414#define IWM_NVM_READ_OPCODE 0 2444#define IWM_NVM_READ_OPCODE 0
2415 2445
2416static int 2446static int
2417iwm_nvm_read_chunk(struct iwm_softc *sc, uint16_t section, uint16_t offset, 2447iwm_nvm_read_chunk(struct iwm_softc *sc, uint16_t section, uint16_t offset,
2418 uint16_t length, uint8_t *data, uint16_t *len) 2448 uint16_t length, uint8_t *data, uint16_t *len)
2419{ 2449{
2420 offset = 0; 2450 offset = 0;
2421 struct iwm_nvm_access_cmd nvm_access_cmd = { 2451 struct iwm_nvm_access_cmd nvm_access_cmd = {
2422 .offset = htole16(offset), 2452 .offset = htole16(offset),
2423 .length = htole16(length), 2453 .length = htole16(length),
2424 .type = htole16(section), 2454 .type = htole16(section),
@@ -2491,27 +2521,27 @@ iwm_nvm_read_section(struct iwm_softc *s @@ -2491,27 +2521,27 @@ iwm_nvm_read_section(struct iwm_softc *s
2491 uint16_t *len, size_t max_len) 2521 uint16_t *len, size_t max_len)
2492{ 2522{
2493 uint16_t chunklen, seglen; 2523 uint16_t chunklen, seglen;
2494 int err; 2524 int err;
2495 2525
2496 chunklen = seglen = IWM_NVM_DEFAULT_CHUNK_SIZE; 2526 chunklen = seglen = IWM_NVM_DEFAULT_CHUNK_SIZE;
2497 *len = 0; 2527 *len = 0;
2498 2528
2499 /* Read NVM chunks until exhausted (reading less than requested) */ 2529 /* Read NVM chunks until exhausted (reading less than requested) */
2500 while (seglen == chunklen && *len < max_len) { 2530 while (seglen == chunklen && *len < max_len) {
2501 err = iwm_nvm_read_chunk(sc, section, *len, chunklen, data, 2531 err = iwm_nvm_read_chunk(sc, section, *len, chunklen, data,
2502 &seglen); 2532 &seglen);
2503 if (err) { 2533 if (err) {
2504 DPRINTF(("%s:Cannot read NVM from section %d " 2534 DPRINTF(("%s: Cannot read NVM from section %d "
2505 "offset %d, length %d\n", 2535 "offset %d, length %d\n",
2506 DEVNAME(sc), section, *len, chunklen)); 2536 DEVNAME(sc), section, *len, chunklen));
2507 return err; 2537 return err;
2508 } 2538 }
2509 *len += seglen; 2539 *len += seglen;
2510 } 2540 }
2511 2541
2512 DPRINTFN(4, ("NVM section %d read completed\n", section)); 2542 DPRINTFN(4, ("NVM section %d read completed\n", section));
2513 return 0; 2543 return 0;
2514} 2544}
2515 2545
2516static uint8_t 2546static uint8_t
2517iwm_fw_valid_tx_ant(struct iwm_softc *sc) 2547iwm_fw_valid_tx_ant(struct iwm_softc *sc)
@@ -2807,48 +2837,46 @@ iwm_set_hw_address_8000(struct iwm_softc @@ -2807,48 +2837,46 @@ iwm_set_hw_address_8000(struct iwm_softc
2807 memset(data->hw_addr, 0, sizeof(data->hw_addr)); 2837 memset(data->hw_addr, 0, sizeof(data->hw_addr));
2808} 2838}
2809 2839
2810static int 2840static int
2811iwm_parse_nvm_data(struct iwm_softc *sc, const uint16_t *nvm_hw, 2841iwm_parse_nvm_data(struct iwm_softc *sc, const uint16_t *nvm_hw,
2812 const uint16_t *nvm_sw, const uint16_t *nvm_calib, 2842 const uint16_t *nvm_sw, const uint16_t *nvm_calib,
2813 const uint16_t *mac_override, const uint16_t *phy_sku, 2843 const uint16_t *mac_override, const uint16_t *phy_sku,
2814 const uint16_t *regulatory) 2844 const uint16_t *regulatory)
2815{ 2845{
2816 struct iwm_nvm_data *data = &sc->sc_nvm; 2846 struct iwm_nvm_data *data = &sc->sc_nvm;
2817 uint8_t hw_addr[ETHER_ADDR_LEN]; 2847 uint8_t hw_addr[ETHER_ADDR_LEN];
2818 uint32_t sku; 2848 uint32_t sku;
2819 2849
2820 data->nvm_version = le16_to_cpup(nvm_sw + IWM_NVM_VERSION); 
2821 
2822 if (sc->sc_device_family == IWM_DEVICE_FAMILY_7000) { 2850 if (sc->sc_device_family == IWM_DEVICE_FAMILY_7000) {
2823 uint16_t radio_cfg = le16_to_cpup(nvm_sw + IWM_RADIO_CFG); 2851 uint16_t radio_cfg = le16_to_cpup(nvm_sw + IWM_RADIO_CFG);
2824 data->radio_cfg_type = IWM_NVM_RF_CFG_TYPE_MSK(radio_cfg); 2852 data->radio_cfg_type = IWM_NVM_RF_CFG_TYPE_MSK(radio_cfg);
2825 data->radio_cfg_step = IWM_NVM_RF_CFG_STEP_MSK(radio_cfg); 2853 data->radio_cfg_step = IWM_NVM_RF_CFG_STEP_MSK(radio_cfg);
2826 data->radio_cfg_dash = IWM_NVM_RF_CFG_DASH_MSK(radio_cfg); 2854 data->radio_cfg_dash = IWM_NVM_RF_CFG_DASH_MSK(radio_cfg);
2827 data->radio_cfg_pnum = IWM_NVM_RF_CFG_PNUM_MSK(radio_cfg); 2855 data->radio_cfg_pnum = IWM_NVM_RF_CFG_PNUM_MSK(radio_cfg);
2828 2856
 2857 data->nvm_version = le16_to_cpup(nvm_sw + IWM_NVM_VERSION);
2829 sku = le16_to_cpup(nvm_sw + IWM_SKU); 2858 sku = le16_to_cpup(nvm_sw + IWM_SKU);
2830 } else { 2859 } else {
2831 uint32_t radio_cfg = le32_to_cpup( 2860 uint32_t radio_cfg = le32_to_cpup(phy_sku + IWM_RADIO_CFG_8000);
2832 (const uint32_t *)(phy_sku + IWM_RADIO_CFG_8000)); 
2833 data->radio_cfg_type = IWM_NVM_RF_CFG_TYPE_MSK_8000(radio_cfg); 2861 data->radio_cfg_type = IWM_NVM_RF_CFG_TYPE_MSK_8000(radio_cfg);
2834 data->radio_cfg_step = IWM_NVM_RF_CFG_STEP_MSK_8000(radio_cfg); 2862 data->radio_cfg_step = IWM_NVM_RF_CFG_STEP_MSK_8000(radio_cfg);
2835 data->radio_cfg_dash = IWM_NVM_RF_CFG_DASH_MSK_8000(radio_cfg); 2863 data->radio_cfg_dash = IWM_NVM_RF_CFG_DASH_MSK_8000(radio_cfg);
2836 data->radio_cfg_pnum = IWM_NVM_RF_CFG_PNUM_MSK_8000(radio_cfg); 2864 data->radio_cfg_pnum = IWM_NVM_RF_CFG_PNUM_MSK_8000(radio_cfg);
2837 data->valid_tx_ant = IWM_NVM_RF_CFG_TX_ANT_MSK_8000(radio_cfg); 2865 data->valid_tx_ant = IWM_NVM_RF_CFG_TX_ANT_MSK_8000(radio_cfg);
2838 data->valid_rx_ant = IWM_NVM_RF_CFG_RX_ANT_MSK_8000(radio_cfg); 2866 data->valid_rx_ant = IWM_NVM_RF_CFG_RX_ANT_MSK_8000(radio_cfg);
2839 2867
2840 sku = le32_to_cpup( 2868 data->nvm_version = le32_to_cpup(nvm_sw + IWM_NVM_VERSION_8000);
2841 (const uint32_t *)(phy_sku + IWM_SKU_8000)); 2869 sku = le32_to_cpup(phy_sku + IWM_SKU_8000);
2842 } 2870 }
2843 2871
2844 data->sku_cap_band_24GHz_enable = sku & IWM_NVM_SKU_CAP_BAND_24GHZ; 2872 data->sku_cap_band_24GHz_enable = sku & IWM_NVM_SKU_CAP_BAND_24GHZ;
2845 data->sku_cap_band_52GHz_enable = sku & IWM_NVM_SKU_CAP_BAND_52GHZ; 2873 data->sku_cap_band_52GHz_enable = sku & IWM_NVM_SKU_CAP_BAND_52GHZ;
2846 data->sku_cap_11n_enable = sku & IWM_NVM_SKU_CAP_11N_ENABLE; 2874 data->sku_cap_11n_enable = sku & IWM_NVM_SKU_CAP_11N_ENABLE;
2847 data->sku_cap_mimo_disable = sku & IWM_NVM_SKU_CAP_MIMO_DISABLE; 2875 data->sku_cap_mimo_disable = sku & IWM_NVM_SKU_CAP_MIMO_DISABLE;
2848 2876
2849 data->n_hw_addrs = le16_to_cpup(nvm_sw + IWM_N_HW_ADDRS); 2877 data->n_hw_addrs = le16_to_cpup(nvm_sw + IWM_N_HW_ADDRS);
2850 2878
2851 if (sc->sc_device_family == IWM_DEVICE_FAMILY_7000) { 2879 if (sc->sc_device_family == IWM_DEVICE_FAMILY_7000) {
2852 memcpy(hw_addr, nvm_hw + IWM_HW_ADDR, ETHER_ADDR_LEN); 2880 memcpy(hw_addr, nvm_hw + IWM_HW_ADDR, ETHER_ADDR_LEN);
2853 data->hw_addr[0] = hw_addr[1]; 2881 data->hw_addr[0] = hw_addr[1];
2854 data->hw_addr[1] = hw_addr[0]; 2882 data->hw_addr[1] = hw_addr[0];
@@ -2932,27 +2960,28 @@ iwm_parse_nvm_sections(struct iwm_softc  @@ -2932,27 +2960,28 @@ iwm_parse_nvm_sections(struct iwm_softc
2932 sections[IWM_NVM_SECTION_TYPE_CALIBRATION].data; 2960 sections[IWM_NVM_SECTION_TYPE_CALIBRATION].data;
2933 2961
2934 return iwm_parse_nvm_data(sc, hw, sw, calib, mac_override, 2962 return iwm_parse_nvm_data(sc, hw, sw, calib, mac_override,
2935 phy_sku, regulatory); 2963 phy_sku, regulatory);
2936} 2964}
2937 2965
2938static int 2966static int
2939iwm_nvm_init(struct iwm_softc *sc) 2967iwm_nvm_init(struct iwm_softc *sc)
2940{ 2968{
2941 struct iwm_nvm_section nvm_sections[IWM_NVM_NUM_OF_SECTIONS]; 2969 struct iwm_nvm_section nvm_sections[IWM_NVM_NUM_OF_SECTIONS];
2942 int i, section, err; 2970 int i, section, err;
2943 uint16_t len; 2971 uint16_t len;
2944 uint8_t *buf; 2972 uint8_t *buf;
2945 const size_t bufsz = IWM_MAX_NVM_SECTION_SIZE; 2973 const size_t bufsz = (sc->sc_device_family == IWM_DEVICE_FAMILY_8000) ?
 2974 IWM_MAX_NVM_SECTION_SIZE_8000 : IWM_MAX_NVM_SECTION_SIZE_7000;
2946 2975
2947 /* Read From FW NVM */ 2976 /* Read From FW NVM */
2948 DPRINTF(("Read NVM\n")); 2977 DPRINTF(("Read NVM\n"));
2949 2978
2950 memset(nvm_sections, 0, sizeof(nvm_sections)); 2979 memset(nvm_sections, 0, sizeof(nvm_sections));
2951 2980
2952 buf = kmem_alloc(bufsz, KM_SLEEP); 2981 buf = kmem_alloc(bufsz, KM_SLEEP);
2953 if (buf == NULL) 2982 if (buf == NULL)
2954 return ENOMEM; 2983 return ENOMEM;
2955 2984
2956 for (i = 0; i < __arraycount(iwm_nvm_to_read); i++) { 2985 for (i = 0; i < __arraycount(iwm_nvm_to_read); i++) {
2957 section = iwm_nvm_to_read[i]; 2986 section = iwm_nvm_to_read[i];
2958 KASSERT(section <= IWM_NVM_NUM_OF_SECTIONS); 2987 KASSERT(section <= IWM_NVM_NUM_OF_SECTIONS);
@@ -2984,69 +3013,69 @@ iwm_nvm_init(struct iwm_softc *sc) @@ -2984,69 +3013,69 @@ iwm_nvm_init(struct iwm_softc *sc)
2984 3013
2985static int 3014static int
2986iwm_firmware_load_sect(struct iwm_softc *sc, uint32_t dst_addr, 3015iwm_firmware_load_sect(struct iwm_softc *sc, uint32_t dst_addr,
2987 const uint8_t *section, uint32_t byte_cnt) 3016 const uint8_t *section, uint32_t byte_cnt)
2988{ 3017{
2989 int err = EINVAL; 3018 int err = EINVAL;
2990 uint32_t chunk_sz, offset; 3019 uint32_t chunk_sz, offset;
2991 3020
2992 chunk_sz = MIN(IWM_FH_MEM_TB_MAX_LENGTH, byte_cnt); 3021 chunk_sz = MIN(IWM_FH_MEM_TB_MAX_LENGTH, byte_cnt);
2993 3022
2994 for (offset = 0; offset < byte_cnt; offset += chunk_sz) { 3023 for (offset = 0; offset < byte_cnt; offset += chunk_sz) {
2995 uint32_t addr, len; 3024 uint32_t addr, len;
2996 const uint8_t *data; 3025 const uint8_t *data;
 3026 bool is_extended = false;
2997 3027
2998 addr = dst_addr + offset; 3028 addr = dst_addr + offset;
2999 len = MIN(chunk_sz, byte_cnt - offset); 3029 len = MIN(chunk_sz, byte_cnt - offset);
3000 data = section + offset; 3030 data = section + offset;
3001 3031
 3032 if (addr >= IWM_FW_MEM_EXTENDED_START &&
 3033 addr <= IWM_FW_MEM_EXTENDED_END)
 3034 is_extended = true;
 3035
 3036 if (is_extended)
 3037 iwm_set_bits_prph(sc, IWM_LMPM_CHICK,
 3038 IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE);
 3039
3002 err = iwm_firmware_load_chunk(sc, addr, data, len); 3040 err = iwm_firmware_load_chunk(sc, addr, data, len);
 3041
 3042 if (is_extended)
 3043 iwm_clear_bits_prph(sc, IWM_LMPM_CHICK,
 3044 IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE);
 3045
3003 if (err) 3046 if (err)
3004 break; 3047 break;
3005 } 3048 }
3006 3049
3007 return err; 3050 return err;
3008} 3051}
3009 3052
3010static int 3053static int
3011iwm_firmware_load_chunk(struct iwm_softc *sc, uint32_t dst_addr, 3054iwm_firmware_load_chunk(struct iwm_softc *sc, uint32_t dst_addr,
3012 const uint8_t *section, uint32_t byte_cnt) 3055 const uint8_t *section, uint32_t byte_cnt)
3013{ 3056{
3014 struct iwm_dma_info *dma = &sc->fw_dma; 3057 struct iwm_dma_info *dma = &sc->fw_dma;
3015 bool is_extended = false; 
3016 int err; 3058 int err;
3017 3059
3018 /* Copy firmware chunk into pre-allocated DMA-safe memory. */ 3060 /* Copy firmware chunk into pre-allocated DMA-safe memory. */
3019 memcpy(dma->vaddr, section, byte_cnt); 3061 memcpy(dma->vaddr, section, byte_cnt);
3020 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, byte_cnt, 3062 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, byte_cnt,
3021 BUS_DMASYNC_PREWRITE); 3063 BUS_DMASYNC_PREWRITE);
3022 3064
3023 if (dst_addr >= IWM_FW_MEM_EXTENDED_START && 
3024 dst_addr <= IWM_FW_MEM_EXTENDED_END) 
3025 is_extended = true; 
3026 
3027 if (is_extended) { 
3028 iwm_set_bits_prph(sc, IWM_LMPM_CHICK, 
3029 IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE); 
3030 } 
3031 
3032 sc->sc_fw_chunk_done = 0; 3065 sc->sc_fw_chunk_done = 0;
3033 3066
3034 if (!iwm_nic_lock(sc)) { 3067 if (!iwm_nic_lock(sc))
3035 if (is_extended) 
3036 iwm_clear_bits_prph(sc, IWM_LMPM_CHICK, 
3037 IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE); 
3038 return EBUSY; 3068 return EBUSY;
3039 } 
3040 3069
3041 IWM_WRITE(sc, IWM_FH_TCSR_CHNL_TX_CONFIG_REG(IWM_FH_SRVC_CHNL), 3070 IWM_WRITE(sc, IWM_FH_TCSR_CHNL_TX_CONFIG_REG(IWM_FH_SRVC_CHNL),
3042 IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 3071 IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
3043 IWM_WRITE(sc, IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(IWM_FH_SRVC_CHNL), 3072 IWM_WRITE(sc, IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(IWM_FH_SRVC_CHNL),
3044 dst_addr); 3073 dst_addr);
3045 IWM_WRITE(sc, IWM_FH_TFDIB_CTRL0_REG(IWM_FH_SRVC_CHNL), 3074 IWM_WRITE(sc, IWM_FH_TFDIB_CTRL0_REG(IWM_FH_SRVC_CHNL),
3046 dma->paddr & IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 3075 dma->paddr & IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
3047 IWM_WRITE(sc, IWM_FH_TFDIB_CTRL1_REG(IWM_FH_SRVC_CHNL), 3076 IWM_WRITE(sc, IWM_FH_TFDIB_CTRL1_REG(IWM_FH_SRVC_CHNL),
3048 (iwm_get_dma_hi_addr(dma->paddr) 3077 (iwm_get_dma_hi_addr(dma->paddr)
3049 << IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 3078 << IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
3050 IWM_WRITE(sc, IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(IWM_FH_SRVC_CHNL), 3079 IWM_WRITE(sc, IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(IWM_FH_SRVC_CHNL),
3051 1 << IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | 3080 1 << IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
3052 1 << IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | 3081 1 << IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
@@ -3056,64 +3085,54 @@ iwm_firmware_load_chunk(struct iwm_softc @@ -3056,64 +3085,54 @@ iwm_firmware_load_chunk(struct iwm_softc
3056 IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 3085 IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
3057 IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 3086 IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
3058 3087
3059 iwm_nic_unlock(sc); 3088 iwm_nic_unlock(sc);
3060 3089
3061 /* Wait for this segment to load. */ 3090 /* Wait for this segment to load. */
3062 err = 0; 3091 err = 0;
3063 while (!sc->sc_fw_chunk_done) { 3092 while (!sc->sc_fw_chunk_done) {
3064 err = tsleep(&sc->sc_fw, 0, "iwmfw", mstohz(5000)); 3093 err = tsleep(&sc->sc_fw, 0, "iwmfw", mstohz(5000));
3065 if (err) 3094 if (err)
3066 break; 3095 break;
3067 } 3096 }
3068 if (!sc->sc_fw_chunk_done) { 3097 if (!sc->sc_fw_chunk_done) {
3069 aprint_error_dev(sc->sc_dev, 3098 DPRINTF(("%s: fw chunk addr 0x%x len %d failed to load\n",
3070 "fw chunk addr 0x%x len %d failed to load\n", 3099 DEVNAME(sc), dst_addr, byte_cnt));
3071 dst_addr, byte_cnt); 
3072 } 
3073 
3074 if (is_extended) { 
3075 int rv = iwm_nic_lock(sc); 
3076 iwm_clear_bits_prph(sc, IWM_LMPM_CHICK, 
3077 IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE); 
3078 if (rv == 0) 
3079 iwm_nic_unlock(sc); 
3080 } 3100 }
3081 3101
3082 return err; 3102 return err;
3083} 3103}
3084 3104
3085static int 3105static int
3086iwm_load_firmware_7000(struct iwm_softc *sc, enum iwm_ucode_type ucode_type) 3106iwm_load_firmware_7000(struct iwm_softc *sc, enum iwm_ucode_type ucode_type)
3087{ 3107{
3088 struct iwm_fw_sects *fws; 3108 struct iwm_fw_sects *fws;
3089 int err, i; 3109 int err, i;
3090 void *data; 3110 void *data;
3091 uint32_t dlen; 3111 uint32_t dlen;
3092 uint32_t offset; 3112 uint32_t offset;
3093 3113
3094 fws = &sc->sc_fw.fw_sects[ucode_type]; 3114 fws = &sc->sc_fw.fw_sects[ucode_type];
3095 for (i = 0; i < fws->fw_count; i++) { 3115 for (i = 0; i < fws->fw_count; i++) {
3096 data = fws->fw_sect[i].fws_data; 3116 data = fws->fw_sect[i].fws_data;
3097 dlen = fws->fw_sect[i].fws_len; 3117 dlen = fws->fw_sect[i].fws_len;
3098 offset = fws->fw_sect[i].fws_devoff; 3118 offset = fws->fw_sect[i].fws_devoff;
3099 if (dlen > sc->sc_fwdmasegsz) { 3119 if (dlen > sc->sc_fwdmasegsz) {
3100 err = EFBIG; 3120 err = EFBIG;
3101 } else 3121 } else
3102 err = iwm_firmware_load_sect(sc, offset, data, dlen); 3122 err = iwm_firmware_load_sect(sc, offset, data, dlen);
3103 if (err) { 3123 if (err) {
3104 aprint_error_dev(sc->sc_dev, 3124 DPRINTF(("%s: could not load firmware chunk %u of %u\n",
3105 "could not load firmware chunk %u of %u\n", 3125 DEVNAME(sc), i, fws->fw_count));
3106 i, fws->fw_count); 
3107 return err; 3126 return err;
3108 } 3127 }
3109 } 3128 }
3110 3129
3111 IWM_WRITE(sc, IWM_CSR_RESET, 0); 3130 IWM_WRITE(sc, IWM_CSR_RESET, 0);
3112 3131
3113 return 0; 3132 return 0;
3114} 3133}
3115 3134
3116static int 3135static int
3117iwm_load_cpu_sections_8000(struct iwm_softc *sc, struct iwm_fw_sects *fws, 3136iwm_load_cpu_sections_8000(struct iwm_softc *sc, struct iwm_fw_sects *fws,
3118 int cpu, int *first_ucode_section) 3137 int cpu, int *first_ucode_section)
3119{ 3138{
@@ -3143,29 +3162,28 @@ iwm_load_cpu_sections_8000(struct iwm_so @@ -3143,29 +3162,28 @@ iwm_load_cpu_sections_8000(struct iwm_so
3143 * CPU1 to CPU2. 3162 * CPU1 to CPU2.
3144 * PAGING_SEPARATOR_SECTION delimiter - separate between 3163 * PAGING_SEPARATOR_SECTION delimiter - separate between
3145 * CPU2 non paged to CPU2 paging sec. 3164 * CPU2 non paged to CPU2 paging sec.
3146 */ 3165 */
3147 if (!data || offset == IWM_CPU1_CPU2_SEPARATOR_SECTION || 3166 if (!data || offset == IWM_CPU1_CPU2_SEPARATOR_SECTION ||
3148 offset == IWM_PAGING_SEPARATOR_SECTION) 3167 offset == IWM_PAGING_SEPARATOR_SECTION)
3149 break; 3168 break;
3150 3169
3151 if (dlen > sc->sc_fwdmasegsz) { 3170 if (dlen > sc->sc_fwdmasegsz) {
3152 err = EFBIG; 3171 err = EFBIG;
3153 } else 3172 } else
3154 err = iwm_firmware_load_sect(sc, offset, data, dlen); 3173 err = iwm_firmware_load_sect(sc, offset, data, dlen);
3155 if (err) { 3174 if (err) {
3156 aprint_error_dev(sc->sc_dev, 3175 DPRINTF(("%s: could not load firmware chunk %d "
3157 "could not load firmware chunk %d (error %d)\n", 3176 "(error %d)\n", DEVNAME(sc), i, err));
3158 i, err); 
3159 return err; 3177 return err;
3160 } 3178 }
3161 3179
3162 /* Notify the ucode of the loaded section number and status */ 3180 /* Notify the ucode of the loaded section number and status */
3163 if (iwm_nic_lock(sc)) { 3181 if (iwm_nic_lock(sc)) {
3164 val = IWM_READ(sc, IWM_FH_UCODE_LOAD_STATUS); 3182 val = IWM_READ(sc, IWM_FH_UCODE_LOAD_STATUS);
3165 val = val | (sec_num << shift_param); 3183 val = val | (sec_num << shift_param);
3166 IWM_WRITE(sc, IWM_FH_UCODE_LOAD_STATUS, val); 3184 IWM_WRITE(sc, IWM_FH_UCODE_LOAD_STATUS, val);
3167 sec_num = (sec_num << 1) | 0x1; 3185 sec_num = (sec_num << 1) | 0x1;
3168 iwm_nic_unlock(sc); 3186 iwm_nic_unlock(sc);
3169 3187
3170 /* 3188 /*
3171 * The firmware won't load correctly without this delay. 3189 * The firmware won't load correctly without this delay.
@@ -3188,57 +3206,69 @@ iwm_load_cpu_sections_8000(struct iwm_so @@ -3188,57 +3206,69 @@ iwm_load_cpu_sections_8000(struct iwm_so
3188} 3206}
3189 3207
3190static int 3208static int
3191iwm_load_firmware_8000(struct iwm_softc *sc, enum iwm_ucode_type ucode_type) 3209iwm_load_firmware_8000(struct iwm_softc *sc, enum iwm_ucode_type ucode_type)
3192{ 3210{
3193 struct iwm_fw_sects *fws; 3211 struct iwm_fw_sects *fws;
3194 int err = 0; 3212 int err = 0;
3195 int first_ucode_section; 3213 int first_ucode_section;
3196 3214
3197 fws = &sc->sc_fw.fw_sects[ucode_type]; 3215 fws = &sc->sc_fw.fw_sects[ucode_type];
3198 3216
3199 /* configure the ucode to be ready to get the secured image */ 3217 /* configure the ucode to be ready to get the secured image */
3200 /* release CPU reset */ 3218 /* release CPU reset */
3201 iwm_write_prph(sc, IWM_RELEASE_CPU_RESET, IWM_RELEASE_CPU_RESET_BIT); 3219 if (iwm_nic_lock(sc)) {
 3220 iwm_write_prph(sc, IWM_RELEASE_CPU_RESET,
 3221 IWM_RELEASE_CPU_RESET_BIT);
 3222 iwm_nic_unlock(sc);
 3223 }
3202 3224
3203 /* load to FW the binary Secured sections of CPU1 */ 3225 /* load to FW the binary Secured sections of CPU1 */
3204 err = iwm_load_cpu_sections_8000(sc, fws, 1, &first_ucode_section); 3226 err = iwm_load_cpu_sections_8000(sc, fws, 1, &first_ucode_section);
3205 if (err) 3227 if (err)
3206 return err; 3228 return err;
3207 3229
3208 /* load to FW the binary sections of CPU2 */ 3230 /* load to FW the binary sections of CPU2 */
3209 return iwm_load_cpu_sections_8000(sc, fws, 2, &first_ucode_section); 3231 return iwm_load_cpu_sections_8000(sc, fws, 2, &first_ucode_section);
3210} 3232}
3211 3233
3212static int 3234static int
3213iwm_load_firmware(struct iwm_softc *sc, enum iwm_ucode_type ucode_type) 3235iwm_load_firmware(struct iwm_softc *sc, enum iwm_ucode_type ucode_type)
3214{ 3236{
3215 int err, w; 3237 int err, w;
3216 3238
3217 sc->sc_uc.uc_intr = 0; 3239 sc->sc_uc.uc_intr = 0;
3218 3240
3219 if (sc->sc_device_family == IWM_DEVICE_FAMILY_8000) 3241 if (sc->sc_device_family == IWM_DEVICE_FAMILY_8000)
3220 err = iwm_load_firmware_8000(sc, ucode_type); 3242 err = iwm_load_firmware_8000(sc, ucode_type);
3221 else 3243 else
3222 err = iwm_load_firmware_7000(sc, ucode_type); 3244 err = iwm_load_firmware_7000(sc, ucode_type);
3223 
3224 if (err) 3245 if (err)
3225 return err; 3246 return err;
3226 3247
3227 /* wait for the firmware to load */ 3248 /* wait for the firmware to load */
3228 for (w = 0; !sc->sc_uc.uc_intr && w < 10; w++) 3249 for (w = 0; !sc->sc_uc.uc_intr && w < 10; w++)
3229 err = tsleep(&sc->sc_uc, 0, "iwmuc", mstohz(100)); 3250 err = tsleep(&sc->sc_uc, 0, "iwmuc", mstohz(100));
3230 if (err || !sc->sc_uc.uc_ok) 3251 if (err || !sc->sc_uc.uc_ok) {
3231 aprint_error_dev(sc->sc_dev, "could not load firmware\n"); 3252 aprint_error_dev(sc->sc_dev,
 3253 "could not load firmware (error %d, ok %d)\n",
 3254 err, sc->sc_uc.uc_ok);
 3255 if (sc->sc_device_family == IWM_DEVICE_FAMILY_8000) {
 3256 aprint_error_dev(sc->sc_dev, "cpu1 status: 0x%x\n",
 3257 iwm_read_prph(sc, IWM_SB_CPU_1_STATUS));
 3258 aprint_error_dev(sc->sc_dev, "cpu2 status: 0x%x\n",
 3259 iwm_read_prph(sc, IWM_SB_CPU_2_STATUS));
 3260 }
 3261 }
3232 3262
3233 return err; 3263 return err;
3234} 3264}
3235 3265
3236static int 3266static int
3237iwm_start_fw(struct iwm_softc *sc, enum iwm_ucode_type ucode_type) 3267iwm_start_fw(struct iwm_softc *sc, enum iwm_ucode_type ucode_type)
3238{ 3268{
3239 int err; 3269 int err;
3240 3270
3241 IWM_WRITE(sc, IWM_CSR_INT, ~0); 3271 IWM_WRITE(sc, IWM_CSR_INT, ~0);
3242 3272
3243 err = iwm_nic_init(sc); 3273 err = iwm_nic_init(sc);
3244 if (err) { 3274 if (err) {
@@ -3287,27 +3317,27 @@ iwm_send_phy_cfg_cmd(struct iwm_softc *s @@ -3287,27 +3317,27 @@ iwm_send_phy_cfg_cmd(struct iwm_softc *s
3287 sc->sc_default_calib[ucode_type].flow_trigger; 3317 sc->sc_default_calib[ucode_type].flow_trigger;
3288 3318
3289 DPRINTFN(10, ("Sending Phy CFG command: 0x%x\n", phy_cfg_cmd.phy_cfg)); 3319 DPRINTFN(10, ("Sending Phy CFG command: 0x%x\n", phy_cfg_cmd.phy_cfg));
3290 return iwm_send_cmd_pdu(sc, IWM_PHY_CONFIGURATION_CMD, 0, 3320 return iwm_send_cmd_pdu(sc, IWM_PHY_CONFIGURATION_CMD, 0,
3291 sizeof(phy_cfg_cmd), &phy_cfg_cmd); 3321 sizeof(phy_cfg_cmd), &phy_cfg_cmd);
3292} 3322}
3293 3323
3294static int 3324static int
3295iwm_load_ucode_wait_alive(struct iwm_softc *sc, enum iwm_ucode_type ucode_type) 3325iwm_load_ucode_wait_alive(struct iwm_softc *sc, enum iwm_ucode_type ucode_type)
3296{ 3326{
3297 enum iwm_ucode_type old_type = sc->sc_uc_current; 3327 enum iwm_ucode_type old_type = sc->sc_uc_current;
3298 int err; 3328 int err;
3299 3329
3300 err = iwm_read_firmware(sc); 3330 err = iwm_read_firmware(sc, ucode_type);
3301 if (err) 3331 if (err)
3302 return err; 3332 return err;
3303 3333
3304 sc->sc_uc_current = ucode_type; 3334 sc->sc_uc_current = ucode_type;
3305 err = iwm_start_fw(sc, ucode_type); 3335 err = iwm_start_fw(sc, ucode_type);
3306 if (err) { 3336 if (err) {
3307 sc->sc_uc_current = old_type; 3337 sc->sc_uc_current = old_type;
3308 return err; 3338 return err;
3309 } 3339 }
3310 3340
3311 return iwm_post_alive(sc); 3341 return iwm_post_alive(sc);
3312} 3342}
3313 3343
@@ -3315,27 +3345,27 @@ static int @@ -3315,27 +3345,27 @@ static int
3315iwm_run_init_mvm_ucode(struct iwm_softc *sc, int justnvm) 3345iwm_run_init_mvm_ucode(struct iwm_softc *sc, int justnvm)
3316{ 3346{
3317 int err; 3347 int err;
3318 3348
3319 if ((sc->sc_flags & IWM_FLAG_RFKILL) && !justnvm) { 3349 if ((sc->sc_flags & IWM_FLAG_RFKILL) && !justnvm) {
3320 aprint_error_dev(sc->sc_dev, 3350 aprint_error_dev(sc->sc_dev,
3321 "radio is disabled by hardware switch\n"); 3351 "radio is disabled by hardware switch\n");
3322 return EPERM; 3352 return EPERM;
3323 } 3353 }
3324 3354
3325 sc->sc_init_complete = 0; 3355 sc->sc_init_complete = 0;
3326 err = iwm_load_ucode_wait_alive(sc, IWM_UCODE_TYPE_INIT); 3356 err = iwm_load_ucode_wait_alive(sc, IWM_UCODE_TYPE_INIT);
3327 if (err) { 3357 if (err) {
3328 aprint_error_dev(sc->sc_dev, "failed to load init firmware\n"); 3358 DPRINTF(("%s: failed to load init firmware\n", DEVNAME(sc)));
3329 return err; 3359 return err;
3330 } 3360 }
3331 3361
3332 if (justnvm) { 3362 if (justnvm) {
3333 err = iwm_nvm_init(sc); 3363 err = iwm_nvm_init(sc);
3334 if (err) { 3364 if (err) {
3335 aprint_error_dev(sc->sc_dev, "failed to read nvm\n"); 3365 aprint_error_dev(sc->sc_dev, "failed to read nvm\n");
3336 return err; 3366 return err;
3337 } 3367 }
3338 3368
3339 memcpy(&sc->sc_ic.ic_myaddr, &sc->sc_nvm.hw_addr, 3369 memcpy(&sc->sc_ic.ic_myaddr, &sc->sc_nvm.hw_addr,
3340 ETHER_ADDR_LEN); 3370 ETHER_ADDR_LEN);
3341 return 0; 3371 return 0;
@@ -3592,27 +3622,28 @@ iwm_rx_rx_mpdu(struct iwm_softc *sc, str @@ -3592,27 +3622,28 @@ iwm_rx_rx_mpdu(struct iwm_softc *sc, str
3592 tap->wr_flags = 0; 3622 tap->wr_flags = 0;
3593 if (phy_info->phy_flags & htole16(IWM_PHY_INFO_FLAG_SHPREAMBLE)) 3623 if (phy_info->phy_flags & htole16(IWM_PHY_INFO_FLAG_SHPREAMBLE))
3594 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3624 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3595 tap->wr_chan_freq = 3625 tap->wr_chan_freq =
3596 htole16(ic->ic_channels[phy_info->channel].ic_freq); 3626 htole16(ic->ic_channels[phy_info->channel].ic_freq);
3597 tap->wr_chan_flags = 3627 tap->wr_chan_flags =
3598 htole16(ic->ic_channels[phy_info->channel].ic_flags); 3628 htole16(ic->ic_channels[phy_info->channel].ic_flags);
3599 tap->wr_dbm_antsignal = (int8_t)rssi; 3629 tap->wr_dbm_antsignal = (int8_t)rssi;
3600 tap->wr_dbm_antnoise = (int8_t)sc->sc_noise; 3630 tap->wr_dbm_antnoise = (int8_t)sc->sc_noise;
3601 tap->wr_tsft = phy_info->system_timestamp; 3631 tap->wr_tsft = phy_info->system_timestamp;
3602 if (phy_info->phy_flags & 3632 if (phy_info->phy_flags &
3603 htole16(IWM_RX_RES_PHY_FLAGS_OFDM_HT)) { 3633 htole16(IWM_RX_RES_PHY_FLAGS_OFDM_HT)) {
3604 uint8_t mcs = (phy_info->rate_n_flags & 3634 uint8_t mcs = (phy_info->rate_n_flags &
3605 htole32(IWM_RATE_HT_MCS_RATE_CODE_MSK)); 3635 htole32(IWM_RATE_HT_MCS_RATE_CODE_MSK |
 3636 IWM_RATE_HT_MCS_NSS_MSK));
3606 tap->wr_rate = (0x80 | mcs); 3637 tap->wr_rate = (0x80 | mcs);
3607 } else { 3638 } else {
3608 uint8_t rate = (phy_info->rate_n_flags & 3639 uint8_t rate = (phy_info->rate_n_flags &
3609 htole32(IWM_RATE_LEGACY_RATE_MSK)); 3640 htole32(IWM_RATE_LEGACY_RATE_MSK));
3610 switch (rate) { 3641 switch (rate) {
3611 /* CCK rates. */ 3642 /* CCK rates. */
3612 case 10: tap->wr_rate = 2; break; 3643 case 10: tap->wr_rate = 2; break;
3613 case 20: tap->wr_rate = 4; break; 3644 case 20: tap->wr_rate = 4; break;
3614 case 55: tap->wr_rate = 11; break; 3645 case 55: tap->wr_rate = 11; break;
3615 case 110: tap->wr_rate = 22; break; 3646 case 110: tap->wr_rate = 22; break;
3616 /* OFDM rates. */ 3647 /* OFDM rates. */
3617 case 0xd: tap->wr_rate = 12; break; 3648 case 0xd: tap->wr_rate = 12; break;
3618 case 0xf: tap->wr_rate = 18; break; 3649 case 0xf: tap->wr_rate = 18; break;
@@ -3662,61 +3693,67 @@ iwm_rx_tx_cmd_single(struct iwm_softc *s @@ -3662,61 +3693,67 @@ iwm_rx_tx_cmd_single(struct iwm_softc *s
3662 3693
3663static void 3694static void
3664iwm_rx_tx_cmd(struct iwm_softc *sc, struct iwm_rx_packet *pkt, 3695iwm_rx_tx_cmd(struct iwm_softc *sc, struct iwm_rx_packet *pkt,
3665 struct iwm_rx_data *data) 3696 struct iwm_rx_data *data)
3666{ 3697{
3667 struct ieee80211com *ic = &sc->sc_ic; 3698 struct ieee80211com *ic = &sc->sc_ic;
3668 struct ifnet *ifp = IC2IFP(ic); 3699 struct ifnet *ifp = IC2IFP(ic);
3669 struct iwm_cmd_header *cmd_hdr = &pkt->hdr; 3700 struct iwm_cmd_header *cmd_hdr = &pkt->hdr;
3670 int idx = cmd_hdr->idx; 3701 int idx = cmd_hdr->idx;
3671 int qid = cmd_hdr->qid; 3702 int qid = cmd_hdr->qid;
3672 struct iwm_tx_ring *ring = &sc->txq[qid]; 3703 struct iwm_tx_ring *ring = &sc->txq[qid];
3673 struct iwm_tx_data *txd = &ring->data[idx]; 3704 struct iwm_tx_data *txd = &ring->data[idx];
3674 struct iwm_node *in = txd->in; 3705 struct iwm_node *in = txd->in;
 3706 int s;
 3707
 3708 s = splnet();
3675 3709
3676 if (txd->done) { 3710 if (txd->done) {
3677 DPRINTF(("%s: got tx interrupt that's already been handled!\n", 3711 DPRINTF(("%s: got tx interrupt that's already been handled!\n",
3678 DEVNAME(sc))); 3712 DEVNAME(sc)));
 3713 splx(s);
3679 return; 3714 return;
3680 } 3715 }
3681 3716
3682 bus_dmamap_sync(sc->sc_dmat, data->map, 0, IWM_RBUF_SIZE, 3717 bus_dmamap_sync(sc->sc_dmat, data->map, 0, IWM_RBUF_SIZE,
3683 BUS_DMASYNC_POSTREAD); 3718 BUS_DMASYNC_POSTREAD);
3684 3719
3685 sc->sc_tx_timer = 0; 3720 sc->sc_tx_timer = 0;
3686 3721
3687 iwm_rx_tx_cmd_single(sc, pkt, in); 3722 iwm_rx_tx_cmd_single(sc, pkt, in);
3688 3723
3689 bus_dmamap_sync(sc->sc_dmat, txd->map, 0, txd->map->dm_mapsize, 3724 bus_dmamap_sync(sc->sc_dmat, txd->map, 0, txd->map->dm_mapsize,
3690 BUS_DMASYNC_POSTWRITE); 3725 BUS_DMASYNC_POSTWRITE);
3691 bus_dmamap_unload(sc->sc_dmat, txd->map); 3726 bus_dmamap_unload(sc->sc_dmat, txd->map);
3692 m_freem(txd->m); 3727 m_freem(txd->m);
3693 3728
3694 DPRINTFN(8, ("free txd %p, in %p\n", txd, txd->in)); 3729 DPRINTFN(8, ("free txd %p, in %p\n", txd, txd->in));
3695 KASSERT(txd->done == 0); 3730 KASSERT(txd->done == 0);
3696 txd->done = 1; 3731 txd->done = 1;
3697 KASSERT(txd->in); 3732 KASSERT(txd->in);
3698 3733
3699 txd->m = NULL; 3734 txd->m = NULL;
3700 txd->in = NULL; 3735 txd->in = NULL;
3701 ieee80211_free_node(&in->in_ni); 3736 ieee80211_free_node(&in->in_ni);
3702 3737
3703 if (--ring->queued < IWM_TX_RING_LOMARK) { 3738 if (--ring->queued < IWM_TX_RING_LOMARK) {
3704 sc->qfullmsk &= ~(1 << ring->qid); 3739 sc->qfullmsk &= ~(1 << qid);
3705 if (sc->qfullmsk == 0 && (ifp->if_flags & IFF_OACTIVE)) { 3740 if (sc->qfullmsk == 0 && (ifp->if_flags & IFF_OACTIVE)) {
3706 ifp->if_flags &= ~IFF_OACTIVE; 3741 ifp->if_flags &= ~IFF_OACTIVE;
3707 if_start_lock(ifp); 3742 if_start_lock(ifp);
3708 } 3743 }
3709 } 3744 }
 3745
 3746 splx(s);
3710} 3747}
3711 3748
3712static int 3749static int
3713iwm_binding_cmd(struct iwm_softc *sc, struct iwm_node *in, uint32_t action) 3750iwm_binding_cmd(struct iwm_softc *sc, struct iwm_node *in, uint32_t action)
3714{ 3751{
3715 struct iwm_binding_cmd cmd; 3752 struct iwm_binding_cmd cmd;
3716 struct iwm_phy_ctxt *phyctxt = in->in_phyctxt; 3753 struct iwm_phy_ctxt *phyctxt = in->in_phyctxt;
3717 int i, err; 3754 int i, err;
3718 uint32_t status; 3755 uint32_t status;
3719 3756
3720 memset(&cmd, 0, sizeof(cmd)); 3757 memset(&cmd, 0, sizeof(cmd));
3721 3758
3722 cmd.id_and_color 3759 cmd.id_and_color
@@ -3910,36 +3947,36 @@ iwm_send_cmd(struct iwm_softc *sc, struc @@ -3910,36 +3947,36 @@ iwm_send_cmd(struct iwm_softc *sc, struc
3910 KASSERT(off == paylen); 3947 KASSERT(off == paylen);
3911 3948
3912 /* lo field is not aligned */ 3949 /* lo field is not aligned */
3913 addr_lo = htole32((uint32_t)paddr); 3950 addr_lo = htole32((uint32_t)paddr);
3914 memcpy(&desc->tbs[0].lo, &addr_lo, sizeof(uint32_t)); 3951 memcpy(&desc->tbs[0].lo, &addr_lo, sizeof(uint32_t));
3915 desc->tbs[0].hi_n_len = htole16(iwm_get_dma_hi_addr(paddr) 3952 desc->tbs[0].hi_n_len = htole16(iwm_get_dma_hi_addr(paddr)
3916 | ((hdrlen + paylen) << 4)); 3953 | ((hdrlen + paylen) << 4));
3917 desc->num_tbs = 1; 3954 desc->num_tbs = 1;
3918 3955
3919 DPRINTFN(8, ("iwm_send_cmd 0x%x size=%zu %s\n", 3956 DPRINTFN(8, ("iwm_send_cmd 0x%x size=%zu %s\n",
3920 code, hdrlen + paylen, async ? " (async)" : "")); 3957 code, hdrlen + paylen, async ? " (async)" : ""));
3921 3958
3922 if (paylen > datasz) { 3959 if (paylen > datasz) {
3923 bus_dmamap_sync(sc->sc_dmat, txdata->map, 0, 3960 bus_dmamap_sync(sc->sc_dmat, txdata->map, 0, hdrlen + paylen,
3924 hdrlen + paylen, BUS_DMASYNC_PREWRITE); 3961 BUS_DMASYNC_PREWRITE);
3925 } else { 3962 } else {
3926 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3963 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map,
3927 (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr, 3964 (uint8_t *)cmd - (uint8_t *)ring->cmd, hdrlen + paylen,
3928 hdrlen + paylen, BUS_DMASYNC_PREWRITE); 3965 BUS_DMASYNC_PREWRITE);
3929 } 3966 }
3930 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3967 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map,
3931 (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr, 3968 (uint8_t *)desc - (uint8_t *)ring->desc, sizeof(*desc),
3932 sizeof(*desc), BUS_DMASYNC_PREWRITE); 3969 BUS_DMASYNC_PREWRITE);
3933 3970
3934 err = iwm_set_cmd_in_flight(sc); 3971 err = iwm_set_cmd_in_flight(sc);
3935 if (err) 3972 if (err)
3936 goto out; 3973 goto out;
3937 ring->queued++; 3974 ring->queued++;
3938 3975
3939#if 0 3976#if 0
3940 iwm_update_sched(sc, ring->qid, ring->cur, 0, 0); 3977 iwm_update_sched(sc, ring->qid, ring->cur, 0, 0);
3941#endif 3978#endif
3942 DPRINTF(("sending command 0x%x qid %d, idx %d\n", 3979 DPRINTF(("sending command 0x%x qid %d, idx %d\n",
3943 code, ring->qid, ring->cur)); 3980 code, ring->qid, ring->cur));
3944 3981
3945 /* Kick command ring. */ 3982 /* Kick command ring. */
@@ -4038,51 +4075,56 @@ static void @@ -4038,51 +4075,56 @@ static void
4038iwm_free_resp(struct iwm_softc *sc, struct iwm_host_cmd *hcmd) 4075iwm_free_resp(struct iwm_softc *sc, struct iwm_host_cmd *hcmd)
4039{ 4076{
4040 KASSERT(sc->sc_wantresp != IWM_CMD_RESP_IDLE); 4077 KASSERT(sc->sc_wantresp != IWM_CMD_RESP_IDLE);
4041 KASSERT((hcmd->flags & IWM_CMD_WANT_SKB) == IWM_CMD_WANT_SKB); 4078 KASSERT((hcmd->flags & IWM_CMD_WANT_SKB) == IWM_CMD_WANT_SKB);
4042 sc->sc_wantresp = IWM_CMD_RESP_IDLE; 4079 sc->sc_wantresp = IWM_CMD_RESP_IDLE;
4043 wakeup(&sc->sc_wantresp); 4080 wakeup(&sc->sc_wantresp);
4044} 4081}
4045 4082
4046static void 4083static void
4047iwm_cmd_done(struct iwm_softc *sc, int qid, int idx) 4084iwm_cmd_done(struct iwm_softc *sc, int qid, int idx)
4048{ 4085{
4049 struct iwm_tx_ring *ring = &sc->txq[IWM_CMD_QUEUE]; 4086 struct iwm_tx_ring *ring = &sc->txq[IWM_CMD_QUEUE];
4050 struct iwm_tx_data *data; 4087 struct iwm_tx_data *data;
 4088 int s;
4051 4089
4052 if (qid != IWM_CMD_QUEUE) { 4090 if (qid != IWM_CMD_QUEUE) {
4053 return; /* Not a command ack. */ 4091 return; /* Not a command ack. */
4054 } 4092 }
4055 4093
 4094 s = splnet();
 4095
4056 data = &ring->data[idx]; 4096 data = &ring->data[idx];
4057 4097
4058 if (data->m != NULL) { 4098 if (data->m != NULL) {
4059 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 4099 bus_dmamap_sync(sc->sc_dmat, data->map, 0,
4060 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4100 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
4061 bus_dmamap_unload(sc->sc_dmat, data->map); 4101 bus_dmamap_unload(sc->sc_dmat, data->map);
4062 m_freem(data->m); 4102 m_freem(data->m);
4063 data->m = NULL; 4103 data->m = NULL;
4064 } 4104 }
4065 wakeup(&ring->desc[idx]); 4105 wakeup(&ring->desc[idx]);
4066 4106
4067 if (((idx + ring->queued) % IWM_TX_RING_COUNT) != ring->cur) { 4107 if (((idx + ring->queued) % IWM_TX_RING_COUNT) != ring->cur) {
4068 aprint_error_dev(sc->sc_dev, 4108 aprint_error_dev(sc->sc_dev,
4069 "Some HCMDs skipped?: idx=%d queued=%d cur=%d\n", 4109 "Some HCMDs skipped?: idx=%d queued=%d cur=%d\n",
4070 idx, ring->queued, ring->cur); 4110 idx, ring->queued, ring->cur);
4071 } 4111 }
4072 4112
4073 KASSERT(ring->queued > 0); 4113 KASSERT(ring->queued > 0);
4074 if (--ring->queued == 0) 4114 if (--ring->queued == 0)
4075 iwm_clear_cmd_in_flight(sc); 4115 iwm_clear_cmd_in_flight(sc);
 4116
 4117 splx(s);
4076} 4118}
4077 4119
4078#if 0 4120#if 0
4079/* 4121/*
4080 * necessary only for block ack mode 4122 * necessary only for block ack mode
4081 */ 4123 */
4082void 4124void
4083iwm_update_sched(struct iwm_softc *sc, int qid, int idx, uint8_t sta_id, 4125iwm_update_sched(struct iwm_softc *sc, int qid, int idx, uint8_t sta_id,
4084 uint16_t len) 4126 uint16_t len)
4085{ 4127{
4086 struct iwm_agn_scd_bc_tbl *scd_bc_tbl; 4128 struct iwm_agn_scd_bc_tbl *scd_bc_tbl;
4087 uint16_t w_val; 4129 uint16_t w_val;
4088 4130
@@ -4114,27 +4156,27 @@ iwm_update_sched(struct iwm_softc *sc, i @@ -4114,27 +4156,27 @@ iwm_update_sched(struct iwm_softc *sc, i
4114/* 4156/*
4115 * Fill in various bit for management frames, and leave them 4157 * Fill in various bit for management frames, and leave them
4116 * unfilled for data frames (firmware takes care of that). 4158 * unfilled for data frames (firmware takes care of that).
4117 * Return the selected TX rate. 4159 * Return the selected TX rate.
4118 */ 4160 */
4119static const struct iwm_rate * 4161static const struct iwm_rate *
4120iwm_tx_fill_cmd(struct iwm_softc *sc, struct iwm_node *in, 4162iwm_tx_fill_cmd(struct iwm_softc *sc, struct iwm_node *in,
4121 struct ieee80211_frame *wh, struct iwm_tx_cmd *tx) 4163 struct ieee80211_frame *wh, struct iwm_tx_cmd *tx)
4122{ 4164{
4123 struct ieee80211com *ic = &sc->sc_ic; 4165 struct ieee80211com *ic = &sc->sc_ic;
4124 struct ieee80211_node *ni = &in->in_ni; 4166 struct ieee80211_node *ni = &in->in_ni;
4125 const struct iwm_rate *rinfo; 4167 const struct iwm_rate *rinfo;
4126 int type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 4168 int type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
4127 int ridx, rate_flags, i; 4169 int ridx, rate_flags, i, ind;
4128 int nrates = ni->ni_rates.rs_nrates; 4170 int nrates = ni->ni_rates.rs_nrates;
4129 4171
4130 tx->rts_retry_limit = IWM_RTS_DFAULT_RETRY_LIMIT; 4172 tx->rts_retry_limit = IWM_RTS_DFAULT_RETRY_LIMIT;
4131 tx->data_retry_limit = IWM_DEFAULT_TX_RETRY; 4173 tx->data_retry_limit = IWM_DEFAULT_TX_RETRY;
4132 4174
4133 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 4175 if (IEEE80211_IS_MULTICAST(wh->i_addr1) ||
4134 type != IEEE80211_FC0_TYPE_DATA) { 4176 type != IEEE80211_FC0_TYPE_DATA) {
4135 /* for non-data, use the lowest supported rate */ 4177 /* for non-data, use the lowest supported rate */
4136 ridx = (IEEE80211_IS_CHAN_5GHZ(ni->ni_chan)) ? 4178 ridx = (IEEE80211_IS_CHAN_5GHZ(ni->ni_chan)) ?
4137 IWM_RIDX_OFDM : IWM_RIDX_CCK; 4179 IWM_RIDX_OFDM : IWM_RIDX_CCK;
4138 tx->data_retry_limit = IWM_MGMT_DFAULT_RETRY_LIMIT; 4180 tx->data_retry_limit = IWM_MGMT_DFAULT_RETRY_LIMIT;
4139#ifndef IEEE80211_NO_HT 4181#ifndef IEEE80211_NO_HT
4140 } else if (ic->ic_fixed_mcs != -1) { 4182 } else if (ic->ic_fixed_mcs != -1) {
@@ -4157,27 +4199,35 @@ iwm_tx_fill_cmd(struct iwm_softc *sc, st @@ -4157,27 +4199,35 @@ iwm_tx_fill_cmd(struct iwm_softc *sc, st
4157 ridx = (IEEE80211_IS_CHAN_5GHZ(ni->ni_chan)) ? 4199 ridx = (IEEE80211_IS_CHAN_5GHZ(ni->ni_chan)) ?
4158 IWM_RIDX_OFDM : IWM_RIDX_CCK; 4200 IWM_RIDX_OFDM : IWM_RIDX_CCK;
4159 for (i = 0; i < nrates; i++) { 4201 for (i = 0; i < nrates; i++) {
4160 if (iwm_rates[i].rate == (ni->ni_txrate & 4202 if (iwm_rates[i].rate == (ni->ni_txrate &
4161 IEEE80211_RATE_VAL)) { 4203 IEEE80211_RATE_VAL)) {
4162 ridx = i; 4204 ridx = i;
4163 break; 4205 break;
4164 } 4206 }
4165 } 4207 }
4166 return &iwm_rates[ridx]; 4208 return &iwm_rates[ridx];
4167 } 4209 }
4168 4210
4169 rinfo = &iwm_rates[ridx]; 4211 rinfo = &iwm_rates[ridx];
4170 rate_flags = 1 << IWM_RATE_MCS_ANT_POS; 4212 for (i = 0, ind = sc->sc_mgmt_last_antenna;
 4213 i < IWM_RATE_MCS_ANT_NUM; i++) {
 4214 ind = (ind + 1) % IWM_RATE_MCS_ANT_NUM;
 4215 if (iwm_fw_valid_tx_ant(sc) & (1 << ind)) {
 4216 sc->sc_mgmt_last_antenna = ind;
 4217 break;
 4218 }
 4219 }
 4220 rate_flags = (1 << sc->sc_mgmt_last_antenna) << IWM_RATE_MCS_ANT_POS;
4171 if (IWM_RIDX_IS_CCK(ridx)) 4221 if (IWM_RIDX_IS_CCK(ridx))
4172 rate_flags |= IWM_RATE_MCS_CCK_MSK; 4222 rate_flags |= IWM_RATE_MCS_CCK_MSK;
4173#ifndef IEEE80211_NO_HT 4223#ifndef IEEE80211_NO_HT
4174 if ((ni->ni_flags & IEEE80211_NODE_HT) && 4224 if ((ni->ni_flags & IEEE80211_NODE_HT) &&
4175 rinfo->ht_plcp != IWM_RATE_HT_SISO_MCS_INV_PLCP) { 4225 rinfo->ht_plcp != IWM_RATE_HT_SISO_MCS_INV_PLCP) {
4176 rate_flags |= IWM_RATE_MCS_HT_MSK; 4226 rate_flags |= IWM_RATE_MCS_HT_MSK;
4177 tx->rate_n_flags = htole32(rate_flags | rinfo->ht_plcp); 4227 tx->rate_n_flags = htole32(rate_flags | rinfo->ht_plcp);
4178 } else 4228 } else
4179#endif 4229#endif
4180 tx->rate_n_flags = htole32(rate_flags | rinfo->plcp); 4230 tx->rate_n_flags = htole32(rate_flags | rinfo->plcp);
4181 4231
4182 return rinfo; 4232 return rinfo;
4183} 4233}
@@ -4297,27 +4347,27 @@ iwm_tx(struct iwm_softc *sc, struct mbuf @@ -4297,27 +4347,27 @@ iwm_tx(struct iwm_softc *sc, struct mbuf
4297 4347
4298 tx->driver_txop = 0; 4348 tx->driver_txop = 0;
4299 tx->next_frame_len = 0; 4349 tx->next_frame_len = 0;
4300 4350
4301 tx->len = htole16(totlen); 4351 tx->len = htole16(totlen);
4302 tx->tid_tspec = tid; 4352 tx->tid_tspec = tid;
4303 tx->life_time = htole32(IWM_TX_CMD_LIFE_TIME_INFINITE); 4353 tx->life_time = htole32(IWM_TX_CMD_LIFE_TIME_INFINITE);
4304 4354
4305 /* Set physical address of "scratch area". */ 4355 /* Set physical address of "scratch area". */
4306 tx->dram_lsb_ptr = htole32(data->scratch_paddr); 4356 tx->dram_lsb_ptr = htole32(data->scratch_paddr);
4307 tx->dram_msb_ptr = iwm_get_dma_hi_addr(data->scratch_paddr); 4357 tx->dram_msb_ptr = iwm_get_dma_hi_addr(data->scratch_paddr);
4308 4358
4309 /* Copy 802.11 header in TX command. */ 4359 /* Copy 802.11 header in TX command. */
4310 memcpy(((uint8_t *)tx) + sizeof(*tx), wh, hdrlen); 4360 memcpy(tx + 1, wh, hdrlen);
4311 4361
4312 flags |= IWM_TX_CMD_FLG_BT_DIS | IWM_TX_CMD_FLG_SEQ_CTL; 4362 flags |= IWM_TX_CMD_FLG_BT_DIS | IWM_TX_CMD_FLG_SEQ_CTL;
4313 4363
4314 tx->sec_ctl = 0; 4364 tx->sec_ctl = 0;
4315 tx->tx_flags |= htole32(flags); 4365 tx->tx_flags |= htole32(flags);
4316 4366
4317 /* Trim 802.11 header. */ 4367 /* Trim 802.11 header. */
4318 m_adj(m, hdrlen); 4368 m_adj(m, hdrlen);
4319 4369
4320 err = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 4370 err = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m,
4321 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 4371 BUS_DMA_NOWAIT | BUS_DMA_WRITE);
4322 if (err) { 4372 if (err) {
4323 if (err != EFBIG) { 4373 if (err != EFBIG) {
@@ -4351,57 +4401,61 @@ iwm_tx(struct iwm_softc *sc, struct mbuf @@ -4351,57 +4401,61 @@ iwm_tx(struct iwm_softc *sc, struct mbuf
4351 aprint_error_dev(sc->sc_dev, 4401 aprint_error_dev(sc->sc_dev,
4352 "can't map mbuf (error %d)\n", err); 4402 "can't map mbuf (error %d)\n", err);
4353 m_freem(m); 4403 m_freem(m);
4354 return err; 4404 return err;
4355 } 4405 }
4356 } 4406 }
4357 data->m = m; 4407 data->m = m;
4358 data->in = in; 4408 data->in = in;
4359 data->done = 0; 4409 data->done = 0;
4360 4410
4361 DPRINTFN(8, ("sending txd %p, in %p\n", data, data->in)); 4411 DPRINTFN(8, ("sending txd %p, in %p\n", data, data->in));
4362 KASSERT(data->in != NULL); 4412 KASSERT(data->in != NULL);
4363 4413
4364 DPRINTFN(8, ("sending data: qid=%d idx=%d len=%d nsegs=%d\n", 4414 DPRINTFN(8, ("sending data: qid=%d idx=%d len=%d nsegs=%d type=%d "
4365 ring->qid, ring->cur, totlen, data->map->dm_nsegs)); 4415 "subtype=%x tx_flags=%08x init_rateidx=%08x rate_n_flags=%08x\n",
 4416 ring->qid, ring->cur, totlen, data->map->dm_nsegs, type,
 4417 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) >> 4,
 4418 le32toh(tx->tx_flags), le32toh(tx->initial_rate_index),
 4419 le32toh(tx->rate_n_flags)));
4366 4420
4367 /* Fill TX descriptor. */ 4421 /* Fill TX descriptor. */
4368 desc->num_tbs = 2 + data->map->dm_nsegs; 4422 desc->num_tbs = 2 + data->map->dm_nsegs;
4369 4423
4370 desc->tbs[0].lo = htole32(data->cmd_paddr); 4424 desc->tbs[0].lo = htole32(data->cmd_paddr);
4371 desc->tbs[0].hi_n_len = htole16(iwm_get_dma_hi_addr(data->cmd_paddr)) | 4425 desc->tbs[0].hi_n_len = htole16(iwm_get_dma_hi_addr(data->cmd_paddr)) |
4372 (TB0_SIZE << 4); 4426 (TB0_SIZE << 4);
4373 desc->tbs[1].lo = htole32(data->cmd_paddr + TB0_SIZE); 4427 desc->tbs[1].lo = htole32(data->cmd_paddr + TB0_SIZE);
4374 desc->tbs[1].hi_n_len = htole16(iwm_get_dma_hi_addr(data->cmd_paddr)) | 4428 desc->tbs[1].hi_n_len = htole16(iwm_get_dma_hi_addr(data->cmd_paddr)) |
4375 ((sizeof(struct iwm_cmd_header) + sizeof(*tx) 4429 ((sizeof(struct iwm_cmd_header) + sizeof(*tx)
4376 + hdrlen + pad - TB0_SIZE) << 4); 4430 + hdrlen + pad - TB0_SIZE) << 4);
4377 4431
4378 /* Other DMA segments are for data payload. */ 4432 /* Other DMA segments are for data payload. */
4379 seg = data->map->dm_segs; 4433 seg = data->map->dm_segs;
4380 for (i = 0; i < data->map->dm_nsegs; i++, seg++) { 4434 for (i = 0; i < data->map->dm_nsegs; i++, seg++) {
4381 desc->tbs[i+2].lo = htole32(seg->ds_addr); 4435 desc->tbs[i+2].lo = htole32(seg->ds_addr);
4382 desc->tbs[i+2].hi_n_len = 4436 desc->tbs[i+2].hi_n_len =
4383 htole16(iwm_get_dma_hi_addr(seg->ds_addr)) 4437 htole16(iwm_get_dma_hi_addr(seg->ds_addr))
4384 | ((seg->ds_len) << 4); 4438 | ((seg->ds_len) << 4);
4385 } 4439 }
4386 4440
4387 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 4441 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize,
4388 BUS_DMASYNC_PREWRITE); 4442 BUS_DMASYNC_PREWRITE);
4389 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 4443 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map,
4390 (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr, 4444 (uint8_t *)cmd - (uint8_t *)ring->cmd, sizeof(*cmd),
4391 sizeof (*cmd), BUS_DMASYNC_PREWRITE); 4445 BUS_DMASYNC_PREWRITE);
4392 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 4446 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map,
4393 (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr, 4447 (uint8_t *)desc - (uint8_t *)ring->desc, sizeof(*desc),
4394 sizeof (*desc), BUS_DMASYNC_PREWRITE); 4448 BUS_DMASYNC_PREWRITE);
4395 4449
4396#if 0 4450#if 0
4397 iwm_update_sched(sc, ring->qid, ring->cur, tx->sta_id, 4451 iwm_update_sched(sc, ring->qid, ring->cur, tx->sta_id,
4398 le16toh(tx->len)); 4452 le16toh(tx->len));
4399#endif 4453#endif
4400 4454
4401 /* Kick TX ring. */ 4455 /* Kick TX ring. */
4402 ring->cur = (ring->cur + 1) % IWM_TX_RING_COUNT; 4456 ring->cur = (ring->cur + 1) % IWM_TX_RING_COUNT;
4403 IWM_WRITE(sc, IWM_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 4457 IWM_WRITE(sc, IWM_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
4404 4458
4405 /* Mark TX ring as full if we reach a certain threshold. */ 4459 /* Mark TX ring as full if we reach a certain threshold. */
4406 if (++ring->queued > IWM_TX_RING_HIMARK) { 4460 if (++ring->queued > IWM_TX_RING_HIMARK) {
4407 sc->qfullmsk |= 1 << ring->qid; 4461 sc->qfullmsk |= 1 << ring->qid;
@@ -4789,60 +4843,57 @@ iwm_lmac_scan_fill_channels(struct iwm_s @@ -4789,60 +4843,57 @@ iwm_lmac_scan_fill_channels(struct iwm_s
4789 struct ieee80211com *ic = &sc->sc_ic; 4843 struct ieee80211com *ic = &sc->sc_ic;
4790 struct ieee80211_channel *c; 4844 struct ieee80211_channel *c;
4791 uint8_t nchan; 4845 uint8_t nchan;
4792 4846
4793 for (nchan = 0, c = &ic->ic_channels[1]; 4847 for (nchan = 0, c = &ic->ic_channels[1];
4794 c <= &ic->ic_channels[IEEE80211_CHAN_MAX] && 4848 c <= &ic->ic_channels[IEEE80211_CHAN_MAX] &&
4795 nchan < sc->sc_capa_n_scan_channels; 4849 nchan < sc->sc_capa_n_scan_channels;
4796 c++) { 4850 c++) {
4797 if (c->ic_flags == 0) 4851 if (c->ic_flags == 0)
4798 continue; 4852 continue;
4799 4853
4800 chan->channel_num = htole16(ieee80211_mhz2ieee(c->ic_freq, 0)); 4854 chan->channel_num = htole16(ieee80211_mhz2ieee(c->ic_freq, 0));
4801 chan->iter_count = htole16(1); 4855 chan->iter_count = htole16(1);
4802 chan->iter_interval = 0; 4856 chan->iter_interval = htole32(0);
4803 chan->flags = htole32(IWM_UNIFIED_SCAN_CHANNEL_PARTIAL); 4857 chan->flags = htole32(IWM_UNIFIED_SCAN_CHANNEL_PARTIAL);
4804#if 0 /* makes scanning while associated less useful */ 4858 chan->flags |= htole32(IWM_SCAN_CHANNEL_NSSIDS(n_ssids));
4805 if (n_ssids != 0) 4859 if (!IEEE80211_IS_CHAN_PASSIVE(c) && n_ssids != 0)
4806 chan->flags |= htole32(1 << 1); /* select SSID 0 */ 4860 chan->flags |= htole32(IWM_SCAN_CHANNEL_TYPE_ACTIVE);
4807#endif 
4808 chan++; 4861 chan++;
4809 nchan++; 4862 nchan++;
4810 } 4863 }
4811 4864
4812 return nchan; 4865 return nchan;
4813} 4866}
4814 4867
4815static uint8_t 4868static uint8_t
4816iwm_umac_scan_fill_channels(struct iwm_softc *sc, 4869iwm_umac_scan_fill_channels(struct iwm_softc *sc,
4817 struct iwm_scan_channel_cfg_umac *chan, int n_ssids) 4870 struct iwm_scan_channel_cfg_umac *chan, int n_ssids)
4818{ 4871{
4819 struct ieee80211com *ic = &sc->sc_ic; 4872 struct ieee80211com *ic = &sc->sc_ic;
4820 struct ieee80211_channel *c; 4873 struct ieee80211_channel *c;
4821 uint8_t nchan; 4874 uint8_t nchan;
4822 4875
4823 for (nchan = 0, c = &ic->ic_channels[1]; 4876 for (nchan = 0, c = &ic->ic_channels[1];
4824 c <= &ic->ic_channels[IEEE80211_CHAN_MAX] && 4877 c <= &ic->ic_channels[IEEE80211_CHAN_MAX] &&
4825 nchan < sc->sc_capa_n_scan_channels; 4878 nchan < sc->sc_capa_n_scan_channels;
4826 c++) { 4879 c++) {
4827 if (c->ic_flags == 0) 4880 if (c->ic_flags == 0)
4828 continue; 4881 continue;
 4882
4829 chan->channel_num = ieee80211_mhz2ieee(c->ic_freq, 0); 4883 chan->channel_num = ieee80211_mhz2ieee(c->ic_freq, 0);
4830 chan->iter_count = 1; 4884 chan->iter_count = 1;
4831 chan->iter_interval = htole16(0); 4885 chan->iter_interval = htole16(0);
4832#if 0 /* makes scanning while associated less useful */ 4886 chan->flags = htole32(IWM_SCAN_CHANNEL_UMAC_NSSIDS(n_ssids));
4833 if (n_ssids != 0) 
4834 chan->flags = htole32(1 << 0); /* select SSID 0 */ 
4835#endif 
4836 chan++; 4887 chan++;
4837 nchan++; 4888 nchan++;
4838 } 4889 }
4839 4890
4840 return nchan; 4891 return nchan;
4841} 4892}
4842 4893
4843static int 4894static int
4844iwm_fill_probe_req(struct iwm_softc *sc, struct iwm_scan_probe_req *preq) 4895iwm_fill_probe_req(struct iwm_softc *sc, struct iwm_scan_probe_req *preq)
4845{ 4896{
4846 struct ieee80211com *ic = &sc->sc_ic; 4897 struct ieee80211com *ic = &sc->sc_ic;
4847 struct ieee80211_frame *wh = (struct ieee80211_frame *)preq->buf; 4898 struct ieee80211_frame *wh = (struct ieee80211_frame *)preq->buf;
4848 struct ieee80211_rateset *rs; 4899 struct ieee80211_rateset *rs;
@@ -5951,31 +6002,34 @@ iwm_newstate(struct ieee80211com *ic, en @@ -5951,31 +6002,34 @@ iwm_newstate(struct ieee80211com *ic, en
5951 iwmns->ns_nstate = nstate; 6002 iwmns->ns_nstate = nstate;
5952 iwmns->ns_arg = arg; 6003 iwmns->ns_arg = arg;
5953 iwmns->ns_generation = sc->sc_generation; 6004 iwmns->ns_generation = sc->sc_generation;
5954 6005
5955 workqueue_enqueue(sc->sc_nswq, &iwmns->ns_wk, NULL); 6006 workqueue_enqueue(sc->sc_nswq, &iwmns->ns_wk, NULL);
5956 6007
5957 return 0; 6008 return 0;
5958} 6009}
5959 6010
5960static void 6011static void
5961iwm_endscan(struct iwm_softc *sc) 6012iwm_endscan(struct iwm_softc *sc)
5962{ 6013{
5963 struct ieee80211com *ic = &sc->sc_ic; 6014 struct ieee80211com *ic = &sc->sc_ic;
 6015 int s;
5964 6016
5965 DPRINTF(("scan ended\n")); 6017 DPRINTF(("%s: scan ended\n", DEVNAME(sc)));
5966 6018
5967 CLR(sc->sc_flags, IWM_FLAG_SCANNING); 6019 s = splnet();
5968 ieee80211_end_scan(ic); 6020 if (ic->ic_state == IEEE80211_S_SCAN)
 6021 ieee80211_end_scan(ic);
 6022 splx(s);
5969} 6023}
5970 6024
5971/* 6025/*
5972 * Aging and idle timeouts for the different possible scenarios 6026 * Aging and idle timeouts for the different possible scenarios
5973 * in default configuration 6027 * in default configuration
5974 */ 6028 */
5975static const uint32_t 6029static const uint32_t
5976iwm_sf_full_timeout_def[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES] = { 6030iwm_sf_full_timeout_def[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES] = {
5977 { 6031 {
5978 htole32(IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF), 6032 htole32(IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF),
5979 htole32(IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF) 6033 htole32(IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF)
5980 }, 6034 },
5981 { 6035 {
@@ -6203,27 +6257,28 @@ iwm_init_hw(struct iwm_softc *sc) @@ -6203,27 +6257,28 @@ iwm_init_hw(struct iwm_softc *sc)
6203 return err; 6257 return err;
6204 6258
6205 /* Should stop and start HW since INIT image just loaded. */ 6259 /* Should stop and start HW since INIT image just loaded. */
6206 iwm_stop_device(sc); 6260 iwm_stop_device(sc);
6207 err = iwm_start_hw(sc); 6261 err = iwm_start_hw(sc);
6208 if (err) { 6262 if (err) {
6209 aprint_error_dev(sc->sc_dev, "could not initialize hardware\n"); 6263 aprint_error_dev(sc->sc_dev, "could not initialize hardware\n");
6210 return err; 6264 return err;
6211 } 6265 }
6212 6266
6213 /* Restart, this time with the regular firmware */ 6267 /* Restart, this time with the regular firmware */
6214 err = iwm_load_ucode_wait_alive(sc, IWM_UCODE_TYPE_REGULAR); 6268 err = iwm_load_ucode_wait_alive(sc, IWM_UCODE_TYPE_REGULAR);
6215 if (err) { 6269 if (err) {
6216 aprint_error_dev(sc->sc_dev, "could not load firmware\n"); 6270 aprint_error_dev(sc->sc_dev,
 6271 "could not load firmware (error %d)\n", err);
6217 goto err; 6272 goto err;
6218 } 6273 }
6219 6274
6220 err = iwm_send_bt_init_conf(sc); 6275 err = iwm_send_bt_init_conf(sc);
6221 if (err) { 6276 if (err) {
6222 aprint_error_dev(sc->sc_dev, 6277 aprint_error_dev(sc->sc_dev,
6223 "could not init bt coex (error %d)\n", err); 6278 "could not init bt coex (error %d)\n", err);
6224 goto err; 6279 goto err;
6225 } 6280 }
6226 6281
6227 err = iwm_send_tx_ant_cfg(sc, iwm_fw_valid_tx_ant(sc)); 6282 err = iwm_send_tx_ant_cfg(sc, iwm_fw_valid_tx_ant(sc));
6228 if (err) { 6283 if (err) {
6229 aprint_error_dev(sc->sc_dev, 6284 aprint_error_dev(sc->sc_dev,
@@ -6272,27 +6327,27 @@ iwm_init_hw(struct iwm_softc *sc) @@ -6272,27 +6327,27 @@ iwm_init_hw(struct iwm_softc *sc)
6272 } 6327 }
6273 6328
6274 /* Initialize tx backoffs to the minimum. */ 6329 /* Initialize tx backoffs to the minimum. */
6275 if (sc->sc_device_family == IWM_DEVICE_FAMILY_7000) 6330 if (sc->sc_device_family == IWM_DEVICE_FAMILY_7000)
6276 iwm_tt_tx_backoff(sc, 0); 6331 iwm_tt_tx_backoff(sc, 0);
6277 6332
6278 err = iwm_power_update_device(sc); 6333 err = iwm_power_update_device(sc);
6279 if (err) { 6334 if (err) {
6280 aprint_error_dev(sc->sc_dev, 6335 aprint_error_dev(sc->sc_dev,
6281 "could send power command (error %d)\n", err); 6336 "could send power command (error %d)\n", err);
6282 goto err; 6337 goto err;
6283 } 6338 }
6284 6339
6285 err = iwm_send_update_mcc_cmd(sc, "ZZ"); 6340 err = iwm_send_update_mcc_cmd(sc, iwm_default_mcc);
6286 if (err) { 6341 if (err) {
6287 aprint_error_dev(sc->sc_dev, 6342 aprint_error_dev(sc->sc_dev,
6288 "could not init LAR (error %d)\n", err); 6343 "could not init LAR (error %d)\n", err);
6289 goto err; 6344 goto err;
6290 } 6345 }
6291 6346
6292 if (isset(sc->sc_enabled_capa, IWM_UCODE_TLV_CAPA_UMAC_SCAN)) { 6347 if (isset(sc->sc_enabled_capa, IWM_UCODE_TLV_CAPA_UMAC_SCAN)) {
6293 err = iwm_config_umac_scan(sc); 6348 err = iwm_config_umac_scan(sc);
6294 if (err) { 6349 if (err) {
6295 aprint_error_dev(sc->sc_dev, 6350 aprint_error_dev(sc->sc_dev,
6296 "could not configure scan (error %d)\n", err); 6351 "could not configure scan (error %d)\n", err);
6297 goto err; 6352 goto err;
6298 } 6353 }
@@ -6343,43 +6398,47 @@ iwm_allow_mcast(struct iwm_softc *sc) @@ -6343,43 +6398,47 @@ iwm_allow_mcast(struct iwm_softc *sc)
6343 cmd->pass_all = 1; 6398 cmd->pass_all = 1;
6344 IEEE80211_ADDR_COPY(cmd->bssid, ni->ni_bssid); 6399 IEEE80211_ADDR_COPY(cmd->bssid, ni->ni_bssid);
6345 6400
6346 err = iwm_send_cmd_pdu(sc, IWM_MCAST_FILTER_CMD, 0, size, cmd); 6401 err = iwm_send_cmd_pdu(sc, IWM_MCAST_FILTER_CMD, 0, size, cmd);
6347 kmem_intr_free(cmd, size); 6402 kmem_intr_free(cmd, size);
6348 return err; 6403 return err;
6349} 6404}
6350 6405
6351static int 6406static int
6352iwm_init(struct ifnet *ifp) 6407iwm_init(struct ifnet *ifp)
6353{ 6408{
6354 struct iwm_softc *sc = ifp->if_softc; 6409 struct iwm_softc *sc = ifp->if_softc;
6355 int err; 6410 int err;
 6411 int s;
6356 6412
6357 if (ISSET(sc->sc_flags, IWM_FLAG_HW_INITED)) 6413 if (ISSET(sc->sc_flags, IWM_FLAG_HW_INITED))
6358 return 0; 6414 return 0;
6359 6415
6360 sc->sc_generation++; 6416 sc->sc_generation++;
6361 sc->sc_flags &= ~IWM_FLAG_STOPPED; 6417 sc->sc_flags &= ~IWM_FLAG_STOPPED;
6362 6418
6363 err = iwm_init_hw(sc); 6419 err = iwm_init_hw(sc);
6364 if (err) { 6420 if (err) {
6365 iwm_stop(ifp, 1); 6421 iwm_stop(ifp, 1);
6366 return err; 6422 return err;
6367 } 6423 }
6368 6424
6369 ifp->if_flags &= ~IFF_OACTIVE; 6425 ifp->if_flags &= ~IFF_OACTIVE;
6370 ifp->if_flags |= IFF_RUNNING; 6426 ifp->if_flags |= IFF_RUNNING;
6371 6427
 6428 s = splnet();
6372 ieee80211_begin_scan(&sc->sc_ic, 0); 6429 ieee80211_begin_scan(&sc->sc_ic, 0);
 6430 splx(s);
 6431
6373 SET(sc->sc_flags, IWM_FLAG_HW_INITED); 6432 SET(sc->sc_flags, IWM_FLAG_HW_INITED);
6374 6433
6375 return 0; 6434 return 0;
6376} 6435}
6377 6436
6378static void 6437static void
6379iwm_start(struct ifnet *ifp) 6438iwm_start(struct ifnet *ifp)
6380{ 6439{
6381 struct iwm_softc *sc = ifp->if_softc; 6440 struct iwm_softc *sc = ifp->if_softc;
6382 struct ieee80211com *ic = &sc->sc_ic; 6441 struct ieee80211com *ic = &sc->sc_ic;
6383 struct ieee80211_node *ni; 6442 struct ieee80211_node *ni;
6384 struct ether_header *eh; 6443 struct ether_header *eh;
6385 struct mbuf *m; 6444 struct mbuf *m;
@@ -6457,37 +6516,40 @@ iwm_start(struct ifnet *ifp) @@ -6457,37 +6516,40 @@ iwm_start(struct ifnet *ifp)
6457 if (ifp->if_flags & IFF_UP) { 6516 if (ifp->if_flags & IFF_UP) {
6458 sc->sc_tx_timer = 15; 6517 sc->sc_tx_timer = 15;
6459 ifp->if_timer = 1; 6518 ifp->if_timer = 1;
6460 } 6519 }
6461 } 6520 }
6462} 6521}
6463 6522
6464static void 6523static void
6465iwm_stop(struct ifnet *ifp, int disable) 6524iwm_stop(struct ifnet *ifp, int disable)
6466{ 6525{
6467 struct iwm_softc *sc = ifp->if_softc; 6526 struct iwm_softc *sc = ifp->if_softc;
6468 struct ieee80211com *ic = &sc->sc_ic; 6527 struct ieee80211com *ic = &sc->sc_ic;
6469 struct iwm_node *in = (struct iwm_node *)ic->ic_bss; 6528 struct iwm_node *in = (struct iwm_node *)ic->ic_bss;
 6529 int s;
6470 6530
6471 sc->sc_flags &= ~IWM_FLAG_HW_INITED; 6531 sc->sc_flags &= ~IWM_FLAG_HW_INITED;
6472 sc->sc_flags |= IWM_FLAG_STOPPED; 6532 sc->sc_flags |= IWM_FLAG_STOPPED;
6473 sc->sc_generation++; 6533 sc->sc_generation++;
6474 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 6534 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
6475 6535
6476 if (in) 6536 if (in)
6477 in->in_phyctxt = NULL; 6537 in->in_phyctxt = NULL;
6478 6538
 6539 s = splnet();
6479 if (ic->ic_state != IEEE80211_S_INIT) 6540 if (ic->ic_state != IEEE80211_S_INIT)
6480 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 6541 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
 6542 splx(s);
6481 6543
6482 callout_stop(&sc->sc_calib_to); 6544 callout_stop(&sc->sc_calib_to);
6483 iwm_led_blink_stop(sc); 6545 iwm_led_blink_stop(sc);
6484 ifp->if_timer = sc->sc_tx_timer = 0; 6546 ifp->if_timer = sc->sc_tx_timer = 0;
6485 iwm_stop_device(sc); 6547 iwm_stop_device(sc);
6486} 6548}
6487 6549
6488static void 6550static void
6489iwm_watchdog(struct ifnet *ifp) 6551iwm_watchdog(struct ifnet *ifp)
6490{ 6552{
6491 struct iwm_softc *sc = ifp->if_softc; 6553 struct iwm_softc *sc = ifp->if_softc;
6492 6554
6493 ifp->if_timer = 0; 6555 ifp->if_timer = 0;
@@ -6976,89 +7038,118 @@ iwm_notif_intr(struct iwm_softc *sc) @@ -6976,89 +7038,118 @@ iwm_notif_intr(struct iwm_softc *sc)
6976 break; 7038 break;
6977 7039
6978 case IWM_MCC_CHUB_UPDATE_CMD: { 7040 case IWM_MCC_CHUB_UPDATE_CMD: {
6979 struct iwm_mcc_chub_notif *notif; 7041 struct iwm_mcc_chub_notif *notif;
6980 SYNC_RESP_STRUCT(notif, pkt); 7042 SYNC_RESP_STRUCT(notif, pkt);
6981 7043
6982 sc->sc_fw_mcc[0] = (notif->mcc & 0xff00) >> 8; 7044 sc->sc_fw_mcc[0] = (notif->mcc & 0xff00) >> 8;
6983 sc->sc_fw_mcc[1] = notif->mcc & 0xff; 7045 sc->sc_fw_mcc[1] = notif->mcc & 0xff;
6984 sc->sc_fw_mcc[2] = '\0'; 7046 sc->sc_fw_mcc[2] = '\0';
6985 break; 7047 break;
6986 } 7048 }
6987 7049
6988 case IWM_DTS_MEASUREMENT_NOTIFICATION: 7050 case IWM_DTS_MEASUREMENT_NOTIFICATION:
 7051 case IWM_WIDE_ID(IWM_PHY_OPS_GROUP,
 7052 IWM_DTS_MEASUREMENT_NOTIF_WIDE): {
 7053 struct iwm_dts_measurement_notif_v1 *notif1;
 7054 struct iwm_dts_measurement_notif_v2 *notif2;
 7055
 7056 if (iwm_rx_packet_payload_len(pkt) == sizeof(*notif1)) {
 7057 SYNC_RESP_STRUCT(notif1, pkt);
 7058 DPRINTF(("%s: DTS temp=%d \n",
 7059 DEVNAME(sc), notif1->temp));
 7060 break;
 7061 }
 7062 if (iwm_rx_packet_payload_len(pkt) == sizeof(*notif2)) {
 7063 SYNC_RESP_STRUCT(notif2, pkt);
 7064 DPRINTF(("%s: DTS temp=%d \n",
 7065 DEVNAME(sc), notif2->temp));
 7066 break;
 7067 }
6989 break; 7068 break;
 7069 }
6990 7070
6991 case IWM_PHY_CONFIGURATION_CMD: 7071 case IWM_PHY_CONFIGURATION_CMD:
6992 case IWM_TX_ANT_CONFIGURATION_CMD: 7072 case IWM_TX_ANT_CONFIGURATION_CMD:
6993 case IWM_ADD_STA: 7073 case IWM_ADD_STA:
6994 case IWM_MAC_CONTEXT_CMD: 7074 case IWM_MAC_CONTEXT_CMD:
6995 case IWM_REPLY_SF_CFG_CMD: 7075 case IWM_REPLY_SF_CFG_CMD:
6996 case IWM_POWER_TABLE_CMD: 7076 case IWM_POWER_TABLE_CMD:
6997 case IWM_PHY_CONTEXT_CMD: 7077 case IWM_PHY_CONTEXT_CMD:
6998 case IWM_BINDING_CONTEXT_CMD: 7078 case IWM_BINDING_CONTEXT_CMD:
6999 case IWM_TIME_EVENT_CMD: 7079 case IWM_TIME_EVENT_CMD:
7000 case IWM_SCAN_REQUEST_CMD: 7080 case IWM_SCAN_REQUEST_CMD:
7001 case IWM_WIDE_ID(IWM_ALWAYS_LONG_GROUP, IWM_SCAN_CFG_CMD): 7081 case IWM_WIDE_ID(IWM_ALWAYS_LONG_GROUP, IWM_SCAN_CFG_CMD):
7002 case IWM_WIDE_ID(IWM_ALWAYS_LONG_GROUP, IWM_SCAN_REQ_UMAC): 7082 case IWM_WIDE_ID(IWM_ALWAYS_LONG_GROUP, IWM_SCAN_REQ_UMAC):
 7083 case IWM_WIDE_ID(IWM_ALWAYS_LONG_GROUP, IWM_SCAN_ABORT_UMAC):
7003 case IWM_SCAN_OFFLOAD_REQUEST_CMD: 7084 case IWM_SCAN_OFFLOAD_REQUEST_CMD:
 7085 case IWM_SCAN_OFFLOAD_ABORT_CMD:
7004 case IWM_REPLY_BEACON_FILTERING_CMD: 7086 case IWM_REPLY_BEACON_FILTERING_CMD:
7005 case IWM_MAC_PM_POWER_TABLE: 7087 case IWM_MAC_PM_POWER_TABLE:
7006 case IWM_TIME_QUOTA_CMD: 7088 case IWM_TIME_QUOTA_CMD:
7007 case IWM_REMOVE_STA: 7089 case IWM_REMOVE_STA:
7008 case IWM_TXPATH_FLUSH: 7090 case IWM_TXPATH_FLUSH:
7009 case IWM_LQ_CMD: 7091 case IWM_LQ_CMD:
7010 case IWM_BT_CONFIG: 7092 case IWM_BT_CONFIG:
7011 case IWM_REPLY_THERMAL_MNG_BACKOFF: 7093 case IWM_REPLY_THERMAL_MNG_BACKOFF:
7012 SYNC_RESP_STRUCT(cresp, pkt); 7094 SYNC_RESP_STRUCT(cresp, pkt);
7013 if (sc->sc_wantresp == ((qid << 16) | idx)) { 7095 if (sc->sc_wantresp == ((qid << 16) | idx)) {
7014 memcpy(sc->sc_cmd_resp, 7096 memcpy(sc->sc_cmd_resp,
7015 pkt, sizeof(*pkt) + sizeof(*cresp)); 7097 pkt, sizeof(*pkt) + sizeof(*cresp));
7016 } 7098 }
7017 break; 7099 break;
7018 7100
7019 /* ignore */ 7101 /* ignore */
7020 case 0x6c: /* IWM_PHY_DB_CMD */ 7102 case IWM_PHY_DB_CMD:
7021 break; 7103 break;
7022 7104
7023 case IWM_INIT_COMPLETE_NOTIF: 7105 case IWM_INIT_COMPLETE_NOTIF:
7024 sc->sc_init_complete = 1; 7106 sc->sc_init_complete = 1;
7025 wakeup(&sc->sc_init_complete); 7107 wakeup(&sc->sc_init_complete);
7026 break; 7108 break;
7027 7109
7028 case IWM_SCAN_OFFLOAD_COMPLETE: { 7110 case IWM_SCAN_OFFLOAD_COMPLETE: {
7029 struct iwm_periodic_scan_complete *notif; 7111 struct iwm_periodic_scan_complete *notif;
7030 SYNC_RESP_STRUCT(notif, pkt); 7112 SYNC_RESP_STRUCT(notif, pkt);
7031 break; 7113 break;
7032 } 7114 }
7033 7115
7034 case IWM_SCAN_ITERATION_COMPLETE: { 7116 case IWM_SCAN_ITERATION_COMPLETE: {
7035 struct iwm_lmac_scan_complete_notif *notif; 7117 struct iwm_lmac_scan_complete_notif *notif;
7036 SYNC_RESP_STRUCT(notif, pkt); 7118 SYNC_RESP_STRUCT(notif, pkt);
7037 iwm_endscan(sc); 7119 if (ISSET(sc->sc_flags, IWM_FLAG_SCANNING)) {
 7120 CLR(sc->sc_flags, IWM_FLAG_SCANNING);
 7121 iwm_endscan(sc);
 7122 }
7038 break; 7123 break;
7039 } 7124 }
7040 7125
7041 case IWM_SCAN_COMPLETE_UMAC: { 7126 case IWM_SCAN_COMPLETE_UMAC: {
7042 struct iwm_umac_scan_complete *notif; 7127 struct iwm_umac_scan_complete *notif;
7043 SYNC_RESP_STRUCT(notif, pkt); 7128 SYNC_RESP_STRUCT(notif, pkt);
7044 iwm_endscan(sc); 7129 if (ISSET(sc->sc_flags, IWM_FLAG_SCANNING)) {
 7130 CLR(sc->sc_flags, IWM_FLAG_SCANNING);
 7131 iwm_endscan(sc);
 7132 }
7045 break; 7133 break;
7046 } 7134 }
7047 7135
7048 case IWM_SCAN_ITERATION_COMPLETE_UMAC: { 7136 case IWM_SCAN_ITERATION_COMPLETE_UMAC: {
7049 struct iwm_umac_scan_iter_complete_notif *notif; 7137 struct iwm_umac_scan_iter_complete_notif *notif;
7050 SYNC_RESP_STRUCT(notif, pkt); 7138 SYNC_RESP_STRUCT(notif, pkt);
7051 iwm_endscan(sc); 7139 if (ISSET(sc->sc_flags, IWM_FLAG_SCANNING)) {
 7140 CLR(sc->sc_flags, IWM_FLAG_SCANNING);
 7141 iwm_endscan(sc);
 7142 }
7052 break; 7143 break;
7053 } 7144 }
7054 7145
7055 case IWM_REPLY_ERROR: { 7146 case IWM_REPLY_ERROR: {
7056 struct iwm_error_resp *resp; 7147 struct iwm_error_resp *resp;
7057 SYNC_RESP_STRUCT(resp, pkt); 7148 SYNC_RESP_STRUCT(resp, pkt);
7058 aprint_error_dev(sc->sc_dev, 7149 aprint_error_dev(sc->sc_dev,
7059 "firmware error 0x%x, cmd 0x%x\n", 7150 "firmware error 0x%x, cmd 0x%x\n",
7060 le32toh(resp->error_type), resp->cmd_id); 7151 le32toh(resp->error_type), resp->cmd_id);
7061 break; 7152 break;
7062 } 7153 }
7063 7154
7064 case IWM_TIME_EVENT_NOTIFICATION: { 7155 case IWM_TIME_EVENT_NOTIFICATION: {
@@ -7095,37 +7186,98 @@ iwm_notif_intr(struct iwm_softc *sc) @@ -7095,37 +7186,98 @@ iwm_notif_intr(struct iwm_softc *sc)
7095 iwm_cmd_done(sc, qid, idx); 7186 iwm_cmd_done(sc, qid, idx);
7096 } 7187 }
7097 7188
7098 ADVANCE_RXQ(sc); 7189 ADVANCE_RXQ(sc);
7099 } 7190 }
7100 7191
7101 /* 7192 /*
7102 * Seems like the hardware gets upset unless we align the write by 8?? 7193 * Seems like the hardware gets upset unless we align the write by 8??
7103 */ 7194 */
7104 hw = (hw == 0) ? IWM_RX_RING_COUNT - 1 : hw - 1; 7195 hw = (hw == 0) ? IWM_RX_RING_COUNT - 1 : hw - 1;
7105 IWM_WRITE(sc, IWM_FH_RSCSR_CHNL0_WPTR, hw & ~7); 7196 IWM_WRITE(sc, IWM_FH_RSCSR_CHNL0_WPTR, hw & ~7);
7106} 7197}
7107 7198
 7199static int
 7200iwm_intr(void *arg)
 7201{
 7202 struct iwm_softc *sc = arg;
 7203 int r1, r2;
 7204
 7205 IWM_WRITE(sc, IWM_CSR_INT_MASK, 0);
 7206
 7207 if (sc->sc_flags & IWM_FLAG_USE_ICT) {
 7208 uint32_t *ict = sc->ict_dma.vaddr;
 7209 int tmp;
 7210
 7211 bus_dmamap_sync(sc->sc_dmat, sc->ict_dma.map,
 7212 0, sc->ict_dma.size, BUS_DMASYNC_POSTREAD);
 7213 tmp = htole32(ict[sc->ict_cur]);
 7214 if (!tmp)
 7215 goto out_ena;
 7216
 7217 /*
 7218 * ok, there was something. keep plowing until we have all.
 7219 */
 7220 r1 = r2 = 0;
 7221 while (tmp) {
 7222 r1 |= tmp;
 7223 ict[sc->ict_cur] = 0; /* Acknowledge. */
 7224 bus_dmamap_sync(sc->sc_dmat, sc->ict_dma.map,
 7225 &ict[sc->ict_cur] - ict, sizeof(*ict),
 7226 BUS_DMASYNC_PREWRITE);
 7227 sc->ict_cur = (sc->ict_cur + 1) % IWM_ICT_COUNT;
 7228 tmp = htole32(ict[sc->ict_cur]);
 7229 }
 7230
 7231 /* this is where the fun begins. don't ask */
 7232 if (r1 == 0xffffffff)
 7233 r1 = 0;
 7234
 7235 /* i am not expected to understand this */
 7236 if (r1 & 0xc0000)
 7237 r1 |= 0x8000;
 7238 r1 = (0xff & r1) | ((0xff00 & r1) << 16);
 7239 } else {
 7240 r1 = IWM_READ(sc, IWM_CSR_INT);
 7241 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0)
 7242 goto out;
 7243 r2 = IWM_READ(sc, IWM_CSR_FH_INT_STATUS);
 7244 }
 7245 if (r1 == 0 && r2 == 0) {
 7246 goto out_ena;
 7247 }
 7248
 7249 IWM_WRITE(sc, IWM_CSR_INT, r1 | ~sc->sc_intmask);
 7250
 7251 atomic_or_32(&sc->sc_soft_flags, r1);
 7252 softint_schedule(sc->sc_soft_ih);
 7253 return 1;
 7254
 7255 out_ena:
 7256 iwm_restore_interrupts(sc);
 7257 out:
 7258 return 0;
 7259}
 7260
7108static void 7261static void
7109iwm_softintr(void *arg) 7262iwm_softintr(void *arg)
7110{ 7263{
7111 struct iwm_softc *sc = arg; 7264 struct iwm_softc *sc = arg;
7112 struct ifnet *ifp = IC2IFP(&sc->sc_ic); 7265 struct ifnet *ifp = IC2IFP(&sc->sc_ic);
7113 uint32_t r1; 7266 uint32_t r1;
7114 int isperiodic = 0; 7267 int isperiodic = 0;
7115 7268
7116 r1 = atomic_swap_32(&sc->sc_soft_flags, 0); 7269 r1 = atomic_swap_32(&sc->sc_soft_flags, 0);
7117 7270
7118 restart: 
7119 if (r1 & IWM_CSR_INT_BIT_SW_ERR) { 7271 if (r1 & IWM_CSR_INT_BIT_SW_ERR) {
7120#ifdef IWM_DEBUG 7272#ifdef IWM_DEBUG
7121 int i; 7273 int i;
7122 7274
7123 iwm_nic_error(sc); 7275 iwm_nic_error(sc);
7124 7276
7125 /* Dump driver status (TX and RX rings) while we're here. */ 7277 /* Dump driver status (TX and RX rings) while we're here. */
7126 DPRINTF(("driver status:\n")); 7278 DPRINTF(("driver status:\n"));
7127 for (i = 0; i < IWM_MAX_QUEUES; i++) { 7279 for (i = 0; i < IWM_MAX_QUEUES; i++) {
7128 struct iwm_tx_ring *ring = &sc->txq[i]; 7280 struct iwm_tx_ring *ring = &sc->txq[i];
7129 DPRINTF((" tx ring %2d: qid=%-2d cur=%-3d " 7281 DPRINTF((" tx ring %2d: qid=%-2d cur=%-3d "
7130 "queued=%-3d\n", 7282 "queued=%-3d\n",
7131 i, ring->qid, ring->cur, ring->queued)); 7283 i, ring->qid, ring->cur, ring->queued));
@@ -7175,110 +7327,42 @@ iwm_softintr(void *arg) @@ -7175,110 +7327,42 @@ iwm_softintr(void *arg)
7175 if ((r1 & (IWM_CSR_INT_BIT_FH_RX | IWM_CSR_INT_BIT_SW_RX)) || 7327 if ((r1 & (IWM_CSR_INT_BIT_FH_RX | IWM_CSR_INT_BIT_SW_RX)) ||
7176 isperiodic) { 7328 isperiodic) {
7177 IWM_WRITE(sc, IWM_CSR_FH_INT_STATUS, IWM_CSR_FH_INT_RX_MASK); 7329 IWM_WRITE(sc, IWM_CSR_FH_INT_STATUS, IWM_CSR_FH_INT_RX_MASK);
7178 7330
7179 iwm_notif_intr(sc); 7331 iwm_notif_intr(sc);
7180 7332
7181 /* enable periodic interrupt, see above */ 7333 /* enable periodic interrupt, see above */
7182 if (r1 & (IWM_CSR_INT_BIT_FH_RX | IWM_CSR_INT_BIT_SW_RX) && 7334 if (r1 & (IWM_CSR_INT_BIT_FH_RX | IWM_CSR_INT_BIT_SW_RX) &&
7183 !isperiodic) 7335 !isperiodic)
7184 IWM_WRITE_1(sc, IWM_CSR_INT_PERIODIC_REG, 7336 IWM_WRITE_1(sc, IWM_CSR_INT_PERIODIC_REG,
7185 IWM_CSR_INT_PERIODIC_ENA); 7337 IWM_CSR_INT_PERIODIC_ENA);
7186 } 7338 }
7187 7339
7188 r1 = atomic_swap_32(&sc->sc_soft_flags, 0); 
7189 if (r1 != 0) 
7190 goto restart; 
7191 
7192 iwm_restore_interrupts(sc); 
7193} 
7194 
7195static int 
7196iwm_intr(void *arg) 
7197{ 
7198 struct iwm_softc *sc = arg; 
7199 int r1, r2; 
7200 
7201 IWM_WRITE(sc, IWM_CSR_INT_MASK, 0); 
7202 
7203 if (sc->sc_flags & IWM_FLAG_USE_ICT) { 
7204 uint32_t *ict = sc->ict_dma.vaddr; 
7205 int tmp; 
7206 
7207 bus_dmamap_sync(sc->sc_dmat, sc->ict_dma.map, 
7208 0, sc->ict_dma.size, BUS_DMASYNC_POSTREAD); 
7209 tmp = htole32(ict[sc->ict_cur]); 
7210 if (!tmp) 
7211 goto out_ena; 
7212 
7213 /* 
7214 * ok, there was something. keep plowing until we have all. 
7215 */ 
7216 r1 = r2 = 0; 
7217 while (tmp) { 
7218 r1 |= tmp; 
7219 ict[sc->ict_cur] = 0; /* Acknowledge. */ 
7220 bus_dmamap_sync(sc->sc_dmat, sc->ict_dma.map, 
7221 &ict[sc->ict_cur] - ict, sizeof(*ict), 
7222 BUS_DMASYNC_PREWRITE); 
7223 sc->ict_cur = (sc->ict_cur + 1) % IWM_ICT_COUNT; 
7224 tmp = htole32(ict[sc->ict_cur]); 
7225 } 
7226 
7227 /* this is where the fun begins. don't ask */ 
7228 if (r1 == 0xffffffff) 
7229 r1 = 0; 
7230 
7231 /* i am not expected to understand this */ 
7232 if (r1 & 0xc0000) 
7233 r1 |= 0x8000; 
7234 r1 = (0xff & r1) | ((0xff00 & r1) << 16); 
7235 } else { 
7236 r1 = IWM_READ(sc, IWM_CSR_INT); 
7237 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 
7238 goto out; 
7239 r2 = IWM_READ(sc, IWM_CSR_FH_INT_STATUS); 
7240 } 
7241 if (r1 == 0 && r2 == 0) { 
7242 goto out_ena; 
7243 } 
7244 
7245 IWM_WRITE(sc, IWM_CSR_INT, r1 | ~sc->sc_intmask); 
7246 
7247 atomic_or_32(&sc->sc_soft_flags, r1); 
7248 softint_schedule(sc->sc_soft_ih); 
7249 return 1; 
7250 
7251 out_ena: 
7252 iwm_restore_interrupts(sc); 7340 iwm_restore_interrupts(sc);
7253 out: 
7254 return 0; 
7255} 7341}
7256 7342
7257/* 7343/*
7258 * Autoconf glue-sniffing 7344 * Autoconf glue-sniffing
7259 */ 7345 */
7260 7346
7261static const pci_product_id_t iwm_devices[] = { 7347static const pci_product_id_t iwm_devices[] = {
7262 PCI_PRODUCT_INTEL_WIFI_LINK_7260_1, 7348 PCI_PRODUCT_INTEL_WIFI_LINK_7260_1,
7263 PCI_PRODUCT_INTEL_WIFI_LINK_7260_2, 7349 PCI_PRODUCT_INTEL_WIFI_LINK_7260_2,
7264 PCI_PRODUCT_INTEL_WIFI_LINK_3160_1, 7350 PCI_PRODUCT_INTEL_WIFI_LINK_3160_1,
7265 PCI_PRODUCT_INTEL_WIFI_LINK_3160_2, 7351 PCI_PRODUCT_INTEL_WIFI_LINK_3160_2,
7266 PCI_PRODUCT_INTEL_WIFI_LINK_7265_1, 7352 PCI_PRODUCT_INTEL_WIFI_LINK_7265_1,
7267 PCI_PRODUCT_INTEL_WIFI_LINK_7265_2, 7353 PCI_PRODUCT_INTEL_WIFI_LINK_7265_2,
7268#ifdef notyet 
7269 PCI_PRODUCT_INTEL_WIFI_LINK_3165_1, 7354 PCI_PRODUCT_INTEL_WIFI_LINK_3165_1,
7270 PCI_PRODUCT_INTEL_WIFI_LINK_3165_2, 7355 PCI_PRODUCT_INTEL_WIFI_LINK_3165_2,
7271#endif 
7272 PCI_PRODUCT_INTEL_WIFI_LINK_8260_1, 7356 PCI_PRODUCT_INTEL_WIFI_LINK_8260_1,
7273 PCI_PRODUCT_INTEL_WIFI_LINK_8260_2, 7357 PCI_PRODUCT_INTEL_WIFI_LINK_8260_2,
7274 PCI_PRODUCT_INTEL_WIFI_LINK_4165_1, 7358 PCI_PRODUCT_INTEL_WIFI_LINK_4165_1,
7275 PCI_PRODUCT_INTEL_WIFI_LINK_4165_2, 7359 PCI_PRODUCT_INTEL_WIFI_LINK_4165_2,
7276}; 7360};
7277 7361
7278static int 7362static int
7279iwm_match(device_t parent, cfdata_t match __unused, void *aux) 7363iwm_match(device_t parent, cfdata_t match __unused, void *aux)
7280{ 7364{
7281 struct pci_attach_args *pa = aux; 7365 struct pci_attach_args *pa = aux;
7282 7366
7283 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 7367 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL)
7284 return 0; 7368 return 0;
@@ -7403,35 +7487,32 @@ iwm_attach(device_t parent, device_t sel @@ -7403,35 +7487,32 @@ iwm_attach(device_t parent, device_t sel
7403 err = pci_mapreg_map(pa, PCI_MAPREG_START, memtype, 0, 7487 err = pci_mapreg_map(pa, PCI_MAPREG_START, memtype, 0,
7404 &sc->sc_st, &sc->sc_sh, NULL, &sc->sc_sz); 7488 &sc->sc_st, &sc->sc_sh, NULL, &sc->sc_sz);
7405 if (err) { 7489 if (err) {
7406 aprint_error_dev(self, "can't map mem space\n"); 7490 aprint_error_dev(self, "can't map mem space\n");
7407 return; 7491 return;
7408 } 7492 }
7409 7493
7410 /* Install interrupt handler. */ 7494 /* Install interrupt handler. */
7411 err = pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0); 7495 err = pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0);
7412 if (err) { 7496 if (err) {
7413 aprint_error_dev(self, "can't allocate interrupt\n"); 7497 aprint_error_dev(self, "can't allocate interrupt\n");
7414 return; 7498 return;
7415 } 7499 }
7416 if (pci_intr_type(sc->sc_pct, sc->sc_pihp[0]) == PCI_INTR_TYPE_INTX) { 7500 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG);
7417 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 7501 if (pci_intr_type(sc->sc_pct, sc->sc_pihp[0]) == PCI_INTR_TYPE_INTX)
7418 PCI_COMMAND_STATUS_REG); 7502 CLR(reg, PCI_COMMAND_INTERRUPT_DISABLE);
7419 if (ISSET(reg, PCI_COMMAND_INTERRUPT_DISABLE)) { 7503 else
7420 CLR(reg, PCI_COMMAND_INTERRUPT_DISABLE); 7504 SET(reg, PCI_COMMAND_INTERRUPT_DISABLE);
7421 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 7505 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg);
7422 PCI_COMMAND_STATUS_REG, reg); 
7423 } 
7424 } 
7425 intrstr = pci_intr_string(sc->sc_pct, sc->sc_pihp[0], intrbuf, 7506 intrstr = pci_intr_string(sc->sc_pct, sc->sc_pihp[0], intrbuf,
7426 sizeof(intrbuf)); 7507 sizeof(intrbuf));
7427 sc->sc_ih = pci_intr_establish_xname(sc->sc_pct, sc->sc_pihp[0], 7508 sc->sc_ih = pci_intr_establish_xname(sc->sc_pct, sc->sc_pihp[0],
7428 IPL_NET, iwm_intr, sc, device_xname(self)); 7509 IPL_NET, iwm_intr, sc, device_xname(self));
7429 if (sc->sc_ih == NULL) { 7510 if (sc->sc_ih == NULL) {
7430 aprint_error_dev(self, "can't establish interrupt"); 7511 aprint_error_dev(self, "can't establish interrupt");
7431 if (intrstr != NULL) 7512 if (intrstr != NULL)
7432 aprint_error(" at %s", intrstr); 7513 aprint_error(" at %s", intrstr);
7433 aprint_error("\n"); 7514 aprint_error("\n");
7434 return; 7515 return;
7435 } 7516 }
7436 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 7517 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
7437 7518
@@ -7439,45 +7520,45 @@ iwm_attach(device_t parent, device_t sel @@ -7439,45 +7520,45 @@ iwm_attach(device_t parent, device_t sel
7439 7520
7440 sc->sc_hw_rev = IWM_READ(sc, IWM_CSR_HW_REV); 7521 sc->sc_hw_rev = IWM_READ(sc, IWM_CSR_HW_REV);
7441 switch (PCI_PRODUCT(sc->sc_pciid)) { 7522 switch (PCI_PRODUCT(sc->sc_pciid)) {
7442 case PCI_PRODUCT_INTEL_WIFI_LINK_3160_1: 7523 case PCI_PRODUCT_INTEL_WIFI_LINK_3160_1:
7443 case PCI_PRODUCT_INTEL_WIFI_LINK_3160_2: 7524 case PCI_PRODUCT_INTEL_WIFI_LINK_3160_2:
7444 sc->sc_fwname = "iwlwifi-3160-16.ucode"; 7525 sc->sc_fwname = "iwlwifi-3160-16.ucode";
7445 sc->host_interrupt_operation_mode = 1; 7526 sc->host_interrupt_operation_mode = 1;
7446 sc->apmg_wake_up_wa = 1; 7527 sc->apmg_wake_up_wa = 1;
7447 sc->sc_device_family = IWM_DEVICE_FAMILY_7000; 7528 sc->sc_device_family = IWM_DEVICE_FAMILY_7000;
7448 sc->sc_fwdmasegsz = IWM_FWDMASEGSZ; 7529 sc->sc_fwdmasegsz = IWM_FWDMASEGSZ;
7449 break; 7530 break;
7450 case PCI_PRODUCT_INTEL_WIFI_LINK_3165_1: 7531 case PCI_PRODUCT_INTEL_WIFI_LINK_3165_1:
7451 case PCI_PRODUCT_INTEL_WIFI_LINK_3165_2: 7532 case PCI_PRODUCT_INTEL_WIFI_LINK_3165_2:
7452 sc->sc_fwname = "iwlwifi-7265D-16.ucode"; 7533 sc->sc_fwname = "iwlwifi-7265D-17.ucode";
7453 sc->host_interrupt_operation_mode = 0; 7534 sc->host_interrupt_operation_mode = 0;
7454 sc->apmg_wake_up_wa = 1; 7535 sc->apmg_wake_up_wa = 1;
7455 sc->sc_device_family = IWM_DEVICE_FAMILY_7000; 7536 sc->sc_device_family = IWM_DEVICE_FAMILY_7000;
7456 sc->sc_fwdmasegsz = IWM_FWDMASEGSZ; 7537 sc->sc_fwdmasegsz = IWM_FWDMASEGSZ;
7457 break; 7538 break;
7458 case PCI_PRODUCT_INTEL_WIFI_LINK_7260_1: 7539 case PCI_PRODUCT_INTEL_WIFI_LINK_7260_1:
7459 case PCI_PRODUCT_INTEL_WIFI_LINK_7260_2: 7540 case PCI_PRODUCT_INTEL_WIFI_LINK_7260_2:
7460 sc->sc_fwname = "iwlwifi-7260-16.ucode"; 7541 sc->sc_fwname = "iwlwifi-7260-16.ucode";
7461 sc->host_interrupt_operation_mode = 1; 7542 sc->host_interrupt_operation_mode = 1;
7462 sc->apmg_wake_up_wa = 1; 7543 sc->apmg_wake_up_wa = 1;
7463 sc->sc_device_family = IWM_DEVICE_FAMILY_7000; 7544 sc->sc_device_family = IWM_DEVICE_FAMILY_7000;
7464 sc->sc_fwdmasegsz = IWM_FWDMASEGSZ; 7545 sc->sc_fwdmasegsz = IWM_FWDMASEGSZ;
7465 break; 7546 break;
7466 case PCI_PRODUCT_INTEL_WIFI_LINK_7265_1: 7547 case PCI_PRODUCT_INTEL_WIFI_LINK_7265_1:
7467 case PCI_PRODUCT_INTEL_WIFI_LINK_7265_2: 7548 case PCI_PRODUCT_INTEL_WIFI_LINK_7265_2:
7468 sc->sc_fwname = (sc->sc_hw_rev & IWM_CSR_HW_REV_TYPE_MSK) == 7549 sc->sc_fwname = (sc->sc_hw_rev & IWM_CSR_HW_REV_TYPE_MSK) ==
7469 IWM_CSR_HW_REV_TYPE_7265D ? 7550 IWM_CSR_HW_REV_TYPE_7265D ?
7470 "iwlwifi-7265D-16.ucode": "iwlwifi-7265-16.ucode"; 7551 "iwlwifi-7265D-17.ucode": "iwlwifi-7265-16.ucode";
7471 sc->host_interrupt_operation_mode = 0; 7552 sc->host_interrupt_operation_mode = 0;
7472 sc->apmg_wake_up_wa = 1; 7553 sc->apmg_wake_up_wa = 1;
7473 sc->sc_device_family = IWM_DEVICE_FAMILY_7000; 7554 sc->sc_device_family = IWM_DEVICE_FAMILY_7000;
7474 sc->sc_fwdmasegsz = IWM_FWDMASEGSZ; 7555 sc->sc_fwdmasegsz = IWM_FWDMASEGSZ;
7475 break; 7556 break;
7476 case PCI_PRODUCT_INTEL_WIFI_LINK_8260_1: 7557 case PCI_PRODUCT_INTEL_WIFI_LINK_8260_1:
7477 case PCI_PRODUCT_INTEL_WIFI_LINK_8260_2: 7558 case PCI_PRODUCT_INTEL_WIFI_LINK_8260_2:
7478 case PCI_PRODUCT_INTEL_WIFI_LINK_4165_1: 7559 case PCI_PRODUCT_INTEL_WIFI_LINK_4165_1:
7479 case PCI_PRODUCT_INTEL_WIFI_LINK_4165_2: 7560 case PCI_PRODUCT_INTEL_WIFI_LINK_4165_2:
7480 sc->sc_fwname = "iwlwifi-8000C-16.ucode"; 7561 sc->sc_fwname = "iwlwifi-8000C-16.ucode";
7481 sc->host_interrupt_operation_mode = 0; 7562 sc->host_interrupt_operation_mode = 0;
7482 sc->apmg_wake_up_wa = 0; 7563 sc->apmg_wake_up_wa = 0;
7483 sc->sc_device_family = IWM_DEVICE_FAMILY_8000; 7564 sc->sc_device_family = IWM_DEVICE_FAMILY_8000;
@@ -7676,27 +7757,26 @@ iwm_attach(device_t parent, device_t sel @@ -7676,27 +7757,26 @@ iwm_attach(device_t parent, device_t sel
7676 ifp->if_start = iwm_start; 7757 ifp->if_start = iwm_start;
7677 ifp->if_watchdog = iwm_watchdog; 7758 ifp->if_watchdog = iwm_watchdog;
7678 IFQ_SET_READY(&ifp->if_snd); 7759 IFQ_SET_READY(&ifp->if_snd);
7679 memcpy(ifp->if_xname, DEVNAME(sc), IFNAMSIZ); 7760 memcpy(ifp->if_xname, DEVNAME(sc), IFNAMSIZ);
7680 7761
7681 if_initialize(ifp); 7762 if_initialize(ifp);
7682#if 0 7763#if 0
7683 ieee80211_ifattach(ic); 7764 ieee80211_ifattach(ic);
7684#else 7765#else
7685 ether_ifattach(ifp, ic->ic_myaddr); /* XXX */ 7766 ether_ifattach(ifp, ic->ic_myaddr); /* XXX */
7686#endif 7767#endif
7687 /* Use common softint-based if_input */ 7768 /* Use common softint-based if_input */
7688 ifp->if_percpuq = if_percpuq_create(ifp); 7769 ifp->if_percpuq = if_percpuq_create(ifp);
7689 if_deferred_start_init(ifp, NULL); 
7690 if_register(ifp); 7770 if_register(ifp);
7691 7771
7692 callout_init(&sc->sc_calib_to, 0); 7772 callout_init(&sc->sc_calib_to, 0);
7693 callout_setfunc(&sc->sc_calib_to, iwm_calib_timeout, sc); 7773 callout_setfunc(&sc->sc_calib_to, iwm_calib_timeout, sc);
7694 callout_init(&sc->sc_led_blink_to, 0); 7774 callout_init(&sc->sc_led_blink_to, 0);
7695 callout_setfunc(&sc->sc_led_blink_to, iwm_led_blink_timeout, sc); 7775 callout_setfunc(&sc->sc_led_blink_to, iwm_led_blink_timeout, sc);
7696#ifndef IEEE80211_NO_HT 7776#ifndef IEEE80211_NO_HT
7697 if (workqueue_create(&sc->sc_setratewq, "iwmsr", 7777 if (workqueue_create(&sc->sc_setratewq, "iwmsr",
7698 iwm_setrates_task, sc, PRI_NONE, IPL_NET, 0)) 7778 iwm_setrates_task, sc, PRI_NONE, IPL_NET, 0))
7699 panic("%s: could not create workqueue: setrates", 7779 panic("%s: could not create workqueue: setrates",
7700 device_xname(self)); 7780 device_xname(self));
7701 if (workqueue_create(&sc->sc_bawq, "iwmba", 7781 if (workqueue_create(&sc->sc_bawq, "iwmba",
7702 iwm_ba_task, sc, PRI_NONE, IPL_NET, 0)) 7782 iwm_ba_task, sc, PRI_NONE, IPL_NET, 0))
cvs diff -r1.4 -r1.5 src/sys/dev/pci/if_iwmreg.h (expand / switch to unified diff)

--- src/sys/dev/pci/if_iwmreg.h 2017/01/09 09:15:54 1.4
+++ src/sys/dev/pci/if_iwmreg.h 2017/01/13 11:21:47 1.5
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: if_iwmreg.h,v 1.4 2017/01/09 09:15:54 nonaka Exp $ */ 1/* $NetBSD: if_iwmreg.h,v 1.5 2017/01/13 11:21:47 nonaka Exp $ */
2/* OpenBSD: if_iwmreg.h,v 1.19 2016/09/20 11:46:09 stsp Exp */ 2/* OpenBSD: if_iwmreg.h,v 1.19 2016/09/20 11:46:09 stsp Exp */
3 3
4/****************************************************************************** 4/******************************************************************************
5 * 5 *
6 * This file is provided under a dual BSD/GPLv2 license. When using or 6 * This file is provided under a dual BSD/GPLv2 license. When using or
7 * redistributing this file, you may do so under either license. 7 * redistributing this file, you may do so under either license.
8 * 8 *
9 * GPL LICENSE SUMMARY 9 * GPL LICENSE SUMMARY
10 * 10 *
11 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 11 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
12 * 12 *
13 * This program is free software; you can redistribute it and/or modify 13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as 14 * it under the terms of version 2 of the GNU General Public License as
@@ -1767,27 +1767,27 @@ enum { @@ -1767,27 +1767,27 @@ enum {
1767 /* Scan offload */ 1767 /* Scan offload */
1768 IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51, 1768 IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51,
1769 IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52, 1769 IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52,
1770 IWM_HOT_SPOT_CMD = 0x53, 1770 IWM_HOT_SPOT_CMD = 0x53,
1771 IWM_SCAN_OFFLOAD_COMPLETE = 0x6d, 1771 IWM_SCAN_OFFLOAD_COMPLETE = 0x6d,
1772 IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6e, 1772 IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6e,
1773 IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f, 1773 IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f,
1774 IWM_MATCH_FOUND_NOTIFICATION = 0xd9, 1774 IWM_MATCH_FOUND_NOTIFICATION = 0xd9,
1775 IWM_SCAN_ITERATION_COMPLETE = 0xe7, 1775 IWM_SCAN_ITERATION_COMPLETE = 0xe7,
1776 1776
1777 /* Phy */ 1777 /* Phy */
1778 IWM_PHY_CONFIGURATION_CMD = 0x6a, 1778 IWM_PHY_CONFIGURATION_CMD = 0x6a,
1779 IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b, 1779 IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b,
1780 /* IWM_PHY_DB_CMD = 0x6c, */ 1780 IWM_PHY_DB_CMD = 0x6c,
1781 1781
1782 /* Power - legacy power table command */ 1782 /* Power - legacy power table command */
1783 IWM_POWER_TABLE_CMD = 0x77, 1783 IWM_POWER_TABLE_CMD = 0x77,
1784 IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78, 1784 IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78,
1785 1785
1786 /* Thermal Throttling*/ 1786 /* Thermal Throttling*/
1787 IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e, 1787 IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e,
1788 1788
1789 /* Scanning */ 1789 /* Scanning */
1790 IWM_SCAN_REQUEST_CMD = 0x80, 1790 IWM_SCAN_REQUEST_CMD = 0x80,
1791 IWM_SCAN_ABORT_CMD = 0x81, 1791 IWM_SCAN_ABORT_CMD = 0x81,
1792 IWM_SCAN_START_NOTIFICATION = 0x82, 1792 IWM_SCAN_START_NOTIFICATION = 0x82,
1793 IWM_SCAN_RESULTS_NOTIFICATION = 0x83, 1793 IWM_SCAN_RESULTS_NOTIFICATION = 0x83,
@@ -1857,26 +1857,45 @@ enum { @@ -1857,26 +1857,45 @@ enum {
1857 IWM_WOWLAN_GET_STATUSES = 0xe5, 1857 IWM_WOWLAN_GET_STATUSES = 0xe5,
1858 IWM_WOWLAN_TX_POWER_PER_DB = 0xe6, 1858 IWM_WOWLAN_TX_POWER_PER_DB = 0xe6,
1859 1859
1860 /* and for NetDetect */ 1860 /* and for NetDetect */
1861 IWM_NET_DETECT_CONFIG_CMD = 0x54, 1861 IWM_NET_DETECT_CONFIG_CMD = 0x54,
1862 IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56, 1862 IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56,
1863 IWM_NET_DETECT_PROFILES_CMD = 0x57, 1863 IWM_NET_DETECT_PROFILES_CMD = 0x57,
1864 IWM_NET_DETECT_HOTSPOTS_CMD = 0x58, 1864 IWM_NET_DETECT_HOTSPOTS_CMD = 0x58,
1865 IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59, 1865 IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59,
1866 1866
1867 IWM_REPLY_MAX = 0xff, 1867 IWM_REPLY_MAX = 0xff,
1868}; 1868};
1869 1869
 1870enum iwm_phy_ops_subcmd_ids {
 1871 IWM_CMD_DTS_MEASUREMENT_TRIGGER_WIDE = 0x0,
 1872 IWM_CTDP_CONFIG_CMD = 0x03,
 1873 IWM_TEMP_REPORTING_THRESHOLDS_CMD = 0x04,
 1874 IWM_CT_KILL_NOTIFICATION = 0xFE,
 1875 IWM_DTS_MEASUREMENT_NOTIF_WIDE = 0xFF,
 1876};
 1877
 1878/* command groups */
 1879enum {
 1880 IWM_LEGACY_GROUP = 0x0,
 1881 IWM_LONG_GROUP = 0x1,
 1882 IWM_SYSTEM_GROUP = 0x2,
 1883 IWM_MAC_CONF_GROUP = 0x3,
 1884 IWM_PHY_OPS_GROUP = 0x4,
 1885 IWM_DATA_PATH_GROUP = 0x5,
 1886 IWM_PROT_OFFLOAD_GROUP = 0xb,
 1887};
 1888
1870/** 1889/**
1871 * struct iwm_cmd_response - generic response struct for most commands 1890 * struct iwm_cmd_response - generic response struct for most commands
1872 * @status: status of the command asked, changes for each one 1891 * @status: status of the command asked, changes for each one
1873 */ 1892 */
1874struct iwm_cmd_response { 1893struct iwm_cmd_response {
1875 uint32_t status; 1894 uint32_t status;
1876}; 1895};
1877 1896
1878/* 1897/*
1879 * struct iwm_tx_ant_cfg_cmd 1898 * struct iwm_tx_ant_cfg_cmd
1880 * @valid: valid antenna configuration 1899 * @valid: valid antenna configuration
1881 */ 1900 */
1882struct iwm_tx_ant_cfg_cmd { 1901struct iwm_tx_ant_cfg_cmd {
@@ -1956,28 +1975,26 @@ struct iwm_phy_cfg_cmd { @@ -1956,28 +1975,26 @@ struct iwm_phy_cfg_cmd {
1956/* 1975/*
1957 * PHY db 1976 * PHY db
1958 */ 1977 */
1959 1978
1960enum iwm_phy_db_section_type { 1979enum iwm_phy_db_section_type {
1961 IWM_PHY_DB_CFG = 1, 1980 IWM_PHY_DB_CFG = 1,
1962 IWM_PHY_DB_CALIB_NCH, 1981 IWM_PHY_DB_CALIB_NCH,
1963 IWM_PHY_DB_UNUSED, 1982 IWM_PHY_DB_UNUSED,
1964 IWM_PHY_DB_CALIB_CHG_PAPD, 1983 IWM_PHY_DB_CALIB_CHG_PAPD,
1965 IWM_PHY_DB_CALIB_CHG_TXP, 1984 IWM_PHY_DB_CALIB_CHG_TXP,
1966 IWM_PHY_DB_MAX 1985 IWM_PHY_DB_MAX
1967}; 1986};
1968 1987
1969#define IWM_PHY_DB_CMD 0x6c /* TEMP API - The actual is 0x8c */ 
1970 
1971/* 1988/*
1972 * phy db - configure operational ucode 1989 * phy db - configure operational ucode
1973 */ 1990 */
1974struct iwm_phy_db_cmd { 1991struct iwm_phy_db_cmd {
1975 uint16_t type; 1992 uint16_t type;
1976 uint16_t length; 1993 uint16_t length;
1977 uint8_t data[]; 1994 uint8_t data[];
1978} __packed; 1995} __packed;
1979 1996
1980/* for parsing of tx power channel group data that comes from the firmware*/ 1997/* for parsing of tx power channel group data that comes from the firmware*/
1981struct iwm_phy_db_chg_txp { 1998struct iwm_phy_db_chg_txp {
1982 uint32_t space; 1999 uint32_t space;
1983 uint16_t max_channel_idx; 2000 uint16_t max_channel_idx;
@@ -4806,26 +4823,27 @@ struct iwm_scd_txq_cfg_cmd { @@ -4806,26 +4823,27 @@ struct iwm_scd_txq_cfg_cmd {
4806 */ 4823 */
4807struct iwm_scd_txq_cfg_rsp { 4824struct iwm_scd_txq_cfg_rsp {
4808 uint8_t token; 4825 uint8_t token;
4809 uint8_t sta_id; 4826 uint8_t sta_id;
4810 uint8_t tid; 4827 uint8_t tid;
4811 uint8_t scd_queue; 4828 uint8_t scd_queue;
4812} __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */ 4829} __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */
4813 4830
4814 4831
4815/* Scan Commands, Responses, Notifications */ 4832/* Scan Commands, Responses, Notifications */
4816 4833
4817/* Masks for iwm_scan_channel.type flags */ 4834/* Masks for iwm_scan_channel.type flags */
4818#define IWM_SCAN_CHANNEL_TYPE_ACTIVE (1 << 0) 4835#define IWM_SCAN_CHANNEL_TYPE_ACTIVE (1 << 0)
 4836#define IWM_SCAN_CHANNEL_NSSIDS(x) (((1 << (x)) - 1) << 1)
4819#define IWM_SCAN_CHANNEL_NARROW_BAND (1 << 22) 4837#define IWM_SCAN_CHANNEL_NARROW_BAND (1 << 22)
4820 4838
4821/* Max number of IEs for direct SSID scans in a command */ 4839/* Max number of IEs for direct SSID scans in a command */
4822#define IWM_PROBE_OPTION_MAX 20 4840#define IWM_PROBE_OPTION_MAX 20
4823 4841
4824/** 4842/**
4825 * struct iwm_scan_channel - entry in IWM_REPLY_SCAN_CMD channel table 4843 * struct iwm_scan_channel - entry in IWM_REPLY_SCAN_CMD channel table
4826 * @channel: band is selected by iwm_scan_cmd "flags" field 4844 * @channel: band is selected by iwm_scan_cmd "flags" field
4827 * @tx_gain: gain for analog radio 4845 * @tx_gain: gain for analog radio
4828 * @dsp_atten: gain for DSP 4846 * @dsp_atten: gain for DSP
4829 * @active_dwell: dwell time for active scan in TU, typically 5-50 4847 * @active_dwell: dwell time for active scan in TU, typically 5-50
4830 * @passive_dwell: dwell time for passive scan in TU, typically 20-500 4848 * @passive_dwell: dwell time for passive scan in TU, typically 20-500
4831 * @type: type is broken down to these bits: 4849 * @type: type is broken down to these bits:
@@ -5612,26 +5630,27 @@ enum iwm_umac_scan_general_flags { @@ -5612,26 +5630,27 @@ enum iwm_umac_scan_general_flags {
5612 IWM_UMAC_SCAN_GEN_FLAGS_MATCH = (1 << 9), 5630 IWM_UMAC_SCAN_GEN_FLAGS_MATCH = (1 << 9),
5613 IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL = (1 << 10), 5631 IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL = (1 << 10),
5614}; 5632};
5615 5633
5616/** 5634/**
5617 * struct iwm_scan_channel_cfg_umac 5635 * struct iwm_scan_channel_cfg_umac
5618 * @flags: bitmap - 0-19: directed scan to i'th ssid. 5636 * @flags: bitmap - 0-19: directed scan to i'th ssid.
5619 * @channel_num: channel number 1-13 etc. 5637 * @channel_num: channel number 1-13 etc.
5620 * @iter_count: repetition count for the channel. 5638 * @iter_count: repetition count for the channel.
5621 * @iter_interval: interval between two scan iterations on one channel. 5639 * @iter_interval: interval between two scan iterations on one channel.
5622 */ 5640 */
5623struct iwm_scan_channel_cfg_umac { 5641struct iwm_scan_channel_cfg_umac {
5624 uint32_t flags; 5642 uint32_t flags;
 5643#define IWM_SCAN_CHANNEL_UMAC_NSSIDS(x) ((1 << (x)) - 1)
5625 uint8_t channel_num; 5644 uint8_t channel_num;
5626 uint8_t iter_count; 5645 uint8_t iter_count;
5627 uint16_t iter_interval; 5646 uint16_t iter_interval;
5628} __packed; /* SCAN_CHANNEL_CFG_S_VER2 */ 5647} __packed; /* SCAN_CHANNEL_CFG_S_VER2 */
5629 5648
5630/** 5649/**
5631 * struct iwm_scan_umac_schedule 5650 * struct iwm_scan_umac_schedule
5632 * @interval: interval in seconds between scan iterations 5651 * @interval: interval in seconds between scan iterations
5633 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop 5652 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop
5634 * @reserved: for alignment and future use 5653 * @reserved: for alignment and future use
5635 */ 5654 */
5636struct iwm_scan_umac_schedule { 5655struct iwm_scan_umac_schedule {
5637 uint16_t interval; 5656 uint16_t interval;
@@ -6311,26 +6330,50 @@ enum iwm_mcc_source { @@ -6311,26 +6330,50 @@ enum iwm_mcc_source {
6311 IWM_MCC_SOURCE_ME = 1, 6330 IWM_MCC_SOURCE_ME = 1,
6312 IWM_MCC_SOURCE_BIOS = 2, 6331 IWM_MCC_SOURCE_BIOS = 2,
6313 IWM_MCC_SOURCE_3G_LTE_HOST = 3, 6332 IWM_MCC_SOURCE_3G_LTE_HOST = 3,
6314 IWM_MCC_SOURCE_3G_LTE_DEVICE = 4, 6333 IWM_MCC_SOURCE_3G_LTE_DEVICE = 4,
6315 IWM_MCC_SOURCE_WIFI = 5, 6334 IWM_MCC_SOURCE_WIFI = 5,
6316 IWM_MCC_SOURCE_RESERVED = 6, 6335 IWM_MCC_SOURCE_RESERVED = 6,
6317 IWM_MCC_SOURCE_DEFAULT = 7, 6336 IWM_MCC_SOURCE_DEFAULT = 7,
6318 IWM_MCC_SOURCE_UNINITIALIZED = 8, 6337 IWM_MCC_SOURCE_UNINITIALIZED = 8,
6319 IWM_MCC_SOURCE_MCC_API = 9, 6338 IWM_MCC_SOURCE_MCC_API = 9,
6320 IWM_MCC_SOURCE_GET_CURRENT = 0x10, 6339 IWM_MCC_SOURCE_GET_CURRENT = 0x10,
6321 IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE = 0x11, 6340 IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE = 0x11,
6322}; 6341};
6323 6342
 6343/**
 6344 * struct iwm_dts_measurement_notif_v1 - measurements notification
 6345 *
 6346 * @temp: the measured temperature
 6347 * @voltage: the measured voltage
 6348 */
 6349struct iwm_dts_measurement_notif_v1 {
 6350 int32_t temp;
 6351 int32_t voltage;
 6352} __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_1*/
 6353
 6354/**
 6355 * struct iwm_dts_measurement_notif_v2 - measurements notification
 6356 *
 6357 * @temp: the measured temperature
 6358 * @voltage: the measured voltage
 6359 * @threshold_idx: the trip index that was crossed
 6360 */
 6361struct iwm_dts_measurement_notif_v2 {
 6362 int32_t temp;
 6363 int32_t voltage;
 6364 int32_t threshold_idx;
 6365} __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_2 */
 6366
6324/* 6367/*
6325 * Some cherry-picked definitions 6368 * Some cherry-picked definitions
6326 */ 6369 */
6327 6370
6328#define IWM_FRAME_LIMIT 64 6371#define IWM_FRAME_LIMIT 64
6329 6372
6330/* 6373/*
6331 * From Linux commit ab02165ccec4c78162501acedeef1a768acdb811: 6374 * From Linux commit ab02165ccec4c78162501acedeef1a768acdb811:
6332 * As the firmware is slowly running out of command IDs and grouping of 6375 * As the firmware is slowly running out of command IDs and grouping of
6333 * commands is desirable anyway, the firmware is extending the command 6376 * commands is desirable anyway, the firmware is extending the command
6334 * header from 4 bytes to 8 bytes to introduce a group (in place of the 6377 * header from 4 bytes to 8 bytes to introduce a group (in place of the
6335 * former flags field, since that's always 0 on commands and thus can 6378 * former flags field, since that's always 0 on commands and thus can
6336 * be easily used to distinguish between the two). 6379 * be easily used to distinguish between the two).
@@ -6376,26 +6419,32 @@ struct iwm_cmd_header { @@ -6376,26 +6419,32 @@ struct iwm_cmd_header {
6376 uint8_t qid; 6419 uint8_t qid;
6377} __packed; 6420} __packed;
6378 6421
6379struct iwm_cmd_header_wide { 6422struct iwm_cmd_header_wide {
6380 uint8_t opcode; 6423 uint8_t opcode;
6381 uint8_t group_id; 6424 uint8_t group_id;
6382 uint8_t idx; 6425 uint8_t idx;
6383 uint8_t qid; 6426 uint8_t qid;
6384 uint16_t length; 6427 uint16_t length;
6385 uint8_t reserved; 6428 uint8_t reserved;
6386 uint8_t version; 6429 uint8_t version;
6387} __packed; 6430} __packed;
6388 6431
 6432/**
 6433 * enum iwm_power_scheme
 6434 * @IWM_POWER_LEVEL_CAM - Continuously Active Mode
 6435 * @IWM_POWER_LEVEL_BPS - Balanced Power Save (default)
 6436 * @IWM_POWER_LEVEL_LP - Low Power
 6437 */
6389enum iwm_power_scheme { 6438enum iwm_power_scheme {
6390 IWM_POWER_SCHEME_CAM = 1, 6439 IWM_POWER_SCHEME_CAM = 1,
6391 IWM_POWER_SCHEME_BPS, 6440 IWM_POWER_SCHEME_BPS,
6392 IWM_POWER_SCHEME_LP 6441 IWM_POWER_SCHEME_LP
6393}; 6442};
6394 6443
6395#define IWM_DEF_CMD_PAYLOAD_SIZE 320 6444#define IWM_DEF_CMD_PAYLOAD_SIZE 320
6396#define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header)) 6445#define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header))
6397#define IWM_CMD_FAILED_MSK 0x40 6446#define IWM_CMD_FAILED_MSK 0x40
6398 6447
6399/** 6448/**
6400 * struct iwm_device_cmd 6449 * struct iwm_device_cmd
6401 * 6450 *
@@ -6440,26 +6489,31 @@ static uint32_t @@ -6440,26 +6489,31 @@ static uint32_t
6440iwm_rx_packet_len(const struct iwm_rx_packet *pkt) 6489iwm_rx_packet_len(const struct iwm_rx_packet *pkt)
6441{ 6490{
6442 6491
6443 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK; 6492 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK;
6444} 6493}
6445 6494
6446static uint32_t 6495static uint32_t
6447iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt) 6496iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt)
6448{ 6497{
6449 6498
6450 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr); 6499 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr);
6451} 6500}
6452 6501
 6502/*
 6503 * Maximum number of HW queues the transport layer
 6504 * currently supports
 6505 */
 6506#define IWM_MAX_TID_COUNT 8
6453 6507
6454#define IWM_MIN_DBM -100 6508#define IWM_MIN_DBM -100
6455#define IWM_MAX_DBM -33 /* realistic guess */ 6509#define IWM_MAX_DBM -33 /* realistic guess */
6456 6510
6457#define IWM_READ(sc, reg) \ 6511#define IWM_READ(sc, reg) \
6458 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 6512 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
6459 6513
6460#define IWM_WRITE(sc, reg, val) \ 6514#define IWM_WRITE(sc, reg, val) \
6461 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6515 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
6462 6516
6463#define IWM_WRITE_1(sc, reg, val) \ 6517#define IWM_WRITE_1(sc, reg, val) \
6464 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6518 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
6465 6519
cvs diff -r1.14 -r1.15 src/sys/dev/pci/if_iwmvar.h (expand / switch to unified diff)

--- src/sys/dev/pci/if_iwmvar.h 2017/01/10 08:40:27 1.14
+++ src/sys/dev/pci/if_iwmvar.h 2017/01/13 11:21:47 1.15
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: if_iwmvar.h,v 1.14 2017/01/10 08:40:27 nonaka Exp $ */ 1/* $NetBSD: if_iwmvar.h,v 1.15 2017/01/13 11:21:47 nonaka Exp $ */
2/* OpenBSD: if_iwmvar.h,v 1.24 2016/09/21 13:53:18 stsp Exp */ 2/* OpenBSD: if_iwmvar.h,v 1.24 2016/09/21 13:53:18 stsp Exp */
3 3
4/* 4/*
5 * Copyright (c) 2014 genua mbh <info@genua.de> 5 * Copyright (c) 2014 genua mbh <info@genua.de>
6 * Copyright (c) 2014 Fixup Software Ltd. 6 * Copyright (c) 2014 Fixup Software Ltd.
7 * 7 *
8 * Permission to use, copy, modify, and distribute this software for any 8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above 9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies. 10 * copyright notice and this permission notice appear in all copies.
11 * 11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -438,26 +438,27 @@ struct iwm_softc { @@ -438,26 +438,27 @@ struct iwm_softc {
438 struct iwm_fw_info sc_fw; 438 struct iwm_fw_info sc_fw;
439 int sc_fw_phy_config; 439 int sc_fw_phy_config;
440 struct iwm_tlv_calib_ctrl sc_default_calib[IWM_UCODE_TYPE_MAX]; 440 struct iwm_tlv_calib_ctrl sc_default_calib[IWM_UCODE_TYPE_MAX];
441 441
442 struct iwm_nvm_data sc_nvm; 442 struct iwm_nvm_data sc_nvm;
443 struct iwm_phy_db sc_phy_db; 443 struct iwm_phy_db sc_phy_db;
444 444
445 struct iwm_bf_data sc_bf; 445 struct iwm_bf_data sc_bf;
446 446
447 int sc_tx_timer; 447 int sc_tx_timer;
448 int sc_rx_ba_sessions; 448 int sc_rx_ba_sessions;
449 449
450 int sc_scan_last_antenna; 450 int sc_scan_last_antenna;
 451 int sc_mgmt_last_antenna;
451 452
452 int sc_fixed_ridx; 453 int sc_fixed_ridx;
453 454
454 int sc_staid; 455 int sc_staid;
455 int sc_nodecolor; 456 int sc_nodecolor;
456 457
457 uint8_t sc_cmd_resp[IWM_CMD_RESP_MAX]; 458 uint8_t sc_cmd_resp[IWM_CMD_RESP_MAX];
458 int sc_wantresp; 459 int sc_wantresp;
459 460
460 struct workqueue *sc_nswq; 461 struct workqueue *sc_nswq;
461 462
462 struct iwm_rx_phy_info sc_last_phy_info; 463 struct iwm_rx_phy_info sc_last_phy_info;
463 int sc_ampdu_ref; 464 int sc_ampdu_ref;