Sun Jan 22 17:46:20 2017 UTC ()
Add TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_REG and bit definitions.


(jakllsch)
diff -r1.1 -r1.2 src/sys/arch/arm/nvidia/tegra_usbreg.h
cvs diff -r1.1 -r1.2 src/sys/arch/arm/nvidia/tegra_usbreg.h (expand / switch to unified diff)

--- src/sys/arch/arm/nvidia/tegra_usbreg.h 2015/10/21 20:02:12 1.1
+++ src/sys/arch/arm/nvidia/tegra_usbreg.h 2017/01/22 17:46:20 1.2
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: tegra_usbreg.h,v 1.1 2015/10/21 20:02:12 jmcneill Exp $ */ 1/* $NetBSD: tegra_usbreg.h,v 1.2 2017/01/22 17:46:20 jakllsch Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
@@ -65,26 +65,35 @@ @@ -65,26 +65,35 @@
65 65
66#define TEGRA_EHCI_SUSP_CTRL_REG 0x400 66#define TEGRA_EHCI_SUSP_CTRL_REG 0x400
67#define TEGRA_EHCI_SUSP_CTRL_UHSIC_RESET __BIT(14) 67#define TEGRA_EHCI_SUSP_CTRL_UHSIC_RESET __BIT(14)
68#define TEGRA_EHCI_SUSP_CTRL_ULPI_PHY_ENB __BIT(13) 68#define TEGRA_EHCI_SUSP_CTRL_ULPI_PHY_ENB __BIT(13)
69#define TEGRA_EHCI_SUSP_CTRL_UTMIP_PHY_ENB __BIT(12) 69#define TEGRA_EHCI_SUSP_CTRL_UTMIP_PHY_ENB __BIT(12)
70#define TEGRA_EHCI_SUSP_CTRL_UTMIP_RESET __BIT(11) 70#define TEGRA_EHCI_SUSP_CTRL_UTMIP_RESET __BIT(11)
71#define TEGRA_EHCI_SUSP_CTRL_PHY_CLK_VALID __BIT(7) 71#define TEGRA_EHCI_SUSP_CTRL_PHY_CLK_VALID __BIT(7)
72 72
73#define TEGRA_EHCI_PHY_VBUS_SENSORS_REG 0x404 73#define TEGRA_EHCI_PHY_VBUS_SENSORS_REG 0x404
74#define TEGRA_EHCI_PHY_VBUS_SENSORS_A_VBUS_VLD_STS __BIT(26) 74#define TEGRA_EHCI_PHY_VBUS_SENSORS_A_VBUS_VLD_STS __BIT(26)
75#define TEGRA_EHCI_PHY_VBUS_SENSORS_B_VLD_SW_VALUE __BIT(12) 75#define TEGRA_EHCI_PHY_VBUS_SENSORS_B_VLD_SW_VALUE __BIT(12)
76#define TEGRA_EHCI_PHY_VBUS_SENSORS_B_VLD_SW_EN __BIT(11) 76#define TEGRA_EHCI_PHY_VBUS_SENSORS_B_VLD_SW_EN __BIT(11)
77 77
 78#define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_REG 0x408
 79#define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_ID_PU __BIT(6)
 80#define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_ID_DEB_SEL_B __BIT(5)
 81#define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_ID_SW_VALUE __BIT(4)
 82#define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_ID_SW_EN __BIT(3)
 83#define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_ID_STS __BIT(2)
 84#define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_ID_CHG_DET __BIT(1)
 85#define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_ID_INT_EN __BIT(0)
 86
78#define TEGRA_EHCI_UTMIP_XCVR_CFG0_REG 0x808 87#define TEGRA_EHCI_UTMIP_XCVR_CFG0_REG 0x808
79#define TEGRA_EHCI_UTMIP_XCVR_CFG0_HSSLEW_MSB __BITS(31,25) 88#define TEGRA_EHCI_UTMIP_XCVR_CFG0_HSSLEW_MSB __BITS(31,25)
80#define TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP_MSB __BITS(24,22) 89#define TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP_MSB __BITS(24,22)
81#define TEGRA_EHCI_UTMIP_XCVR_CFG0_LSBIAS_SEL __BIT(21) 90#define TEGRA_EHCI_UTMIP_XCVR_CFG0_LSBIAS_SEL __BIT(21)
82#define TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP __BITS(3,0) 91#define TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP __BITS(3,0)
83#define TEGRA_EHCI_UTMIP_XCVR_CFG0_PDZI_POWERDOWN __BIT(18) 92#define TEGRA_EHCI_UTMIP_XCVR_CFG0_PDZI_POWERDOWN __BIT(18)
84#define TEGRA_EHCI_UTMIP_XCVR_CFG0_PD2_POWERDOWN __BIT(16) 93#define TEGRA_EHCI_UTMIP_XCVR_CFG0_PD2_POWERDOWN __BIT(16)
85#define TEGRA_EHCI_UTMIP_XCVR_CFG0_PD_POWERDOWN __BIT(14) 94#define TEGRA_EHCI_UTMIP_XCVR_CFG0_PD_POWERDOWN __BIT(14)
86 95
87#define TEGRA_EHCI_UTMIP_BIAS_CFG0_REG 0x80c 96#define TEGRA_EHCI_UTMIP_BIAS_CFG0_REG 0x80c
88#define TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL_MSB __BIT(24) 97#define TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL_MSB __BIT(24)
89#define TEGRA_EHCI_UTMIP_BIAS_CFG0_BIASPD __BIT(10) 98#define TEGRA_EHCI_UTMIP_BIAS_CFG0_BIASPD __BIT(10)
90#define TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL __BITS(3,2) 99#define TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL __BITS(3,2)