| @@ -2308,550 +2308,273 @@ int R600_comp_vs(RADEONChipFamily ChipSe | | | @@ -2308,550 +2308,273 @@ int R600_comp_vs(RADEONChipFamily ChipSe |
2308 | CONST_BUF_NO_STRIDE(0), | | 2308 | CONST_BUF_NO_STRIDE(0), |
2309 | MEGA_FETCH(0)); | | 2309 | MEGA_FETCH(0)); |
2310 | shader[i++] = VTX_DWORD_PAD; | | 2310 | shader[i++] = VTX_DWORD_PAD; |
2311 | | | 2311 | |
2312 | return i; | | 2312 | return i; |
2313 | } | | 2313 | } |
2314 | | | 2314 | |
2315 | /* comp ps --------------------------------------- */ | | 2315 | /* comp ps --------------------------------------- */ |
2316 | int R600_comp_ps(RADEONChipFamily ChipSet, uint32_t* shader) | | 2316 | int R600_comp_ps(RADEONChipFamily ChipSet, uint32_t* shader) |
2317 | { | | 2317 | { |
2318 | int i = 0; | | 2318 | int i = 0; |
2319 | | | 2319 | |
2320 | /* 0 */ | | 2320 | /* 0 */ |
2321 | /* call fetch-mask if boolean1 == true */ | | 2321 | shader[i++] = CF_DWORD0(ADDR(3)); |
2322 | shader[i++] = CF_DWORD0(ADDR(10)); | | | |
2323 | shader[i++] = CF_DWORD1(POP_COUNT(0), | | 2322 | shader[i++] = CF_DWORD1(POP_COUNT(0), |
2324 | CF_CONST(1), | | 2323 | CF_CONST(0), |
2325 | COND(SQ_CF_COND_BOOL), | | 2324 | COND(SQ_CF_COND_BOOL), |
2326 | I_COUNT(0), | | 2325 | I_COUNT(0), |
2327 | CALL_COUNT(0), | | 2326 | CALL_COUNT(0), |
2328 | END_OF_PROGRAM(0), | | 2327 | END_OF_PROGRAM(0), |
2329 | VALID_PIXEL_MODE(0), | | 2328 | VALID_PIXEL_MODE(0), |
2330 | CF_INST(SQ_CF_INST_CALL), | | 2329 | CF_INST(SQ_CF_INST_CALL), |
2331 | WHOLE_QUAD_MODE(0), | | 2330 | WHOLE_QUAD_MODE(0), |
2332 | BARRIER(0)); | | 2331 | BARRIER(0)); |
2333 | /* 1 */ | | 2332 | /* 1 */ |
2334 | /* call read-constant-mask if boolean1 == false */ | | 2333 | shader[i++] = CF_DWORD0(ADDR(7)); |
2335 | shader[i++] = CF_DWORD0(ADDR(12)); | | | |
2336 | shader[i++] = CF_DWORD1(POP_COUNT(0), | | 2334 | shader[i++] = CF_DWORD1(POP_COUNT(0), |
2337 | CF_CONST(1), | | 2335 | CF_CONST(0), |
2338 | COND(SQ_CF_COND_NOT_BOOL), | | 2336 | COND(SQ_CF_COND_NOT_BOOL), |
2339 | I_COUNT(0), | | 2337 | I_COUNT(0), |
2340 | CALL_COUNT(0), | | 2338 | CALL_COUNT(0), |
2341 | END_OF_PROGRAM(0), | | 2339 | END_OF_PROGRAM(0), |
2342 | VALID_PIXEL_MODE(0), | | 2340 | VALID_PIXEL_MODE(0), |
2343 | CF_INST(SQ_CF_INST_CALL), | | 2341 | CF_INST(SQ_CF_INST_CALL), |
2344 | WHOLE_QUAD_MODE(0), | | 2342 | WHOLE_QUAD_MODE(0), |
2345 | BARRIER(0)); | | 2343 | BARRIER(0)); |
2346 | /* 2 */ | | 2344 | /* 2 */ |
2347 | /* call fetch-src if boolean0 == true */ | | 2345 | shader[i++] = CF_DWORD0(ADDR(0)); |
2348 | shader[i++] = CF_DWORD0(ADDR(6)); | | | |
2349 | shader[i++] = CF_DWORD1(POP_COUNT(0), | | 2346 | shader[i++] = CF_DWORD1(POP_COUNT(0), |
2350 | CF_CONST(0), | | 2347 | CF_CONST(0), |
2351 | COND(SQ_CF_COND_BOOL), | | 2348 | COND(SQ_CF_COND_ACTIVE), |
2352 | I_COUNT(0), | | 2349 | I_COUNT(0), |
2353 | CALL_COUNT(0), | | 2350 | CALL_COUNT(0), |
2354 | END_OF_PROGRAM(0), | | 2351 | END_OF_PROGRAM(1), |
2355 | VALID_PIXEL_MODE(0), | | 2352 | VALID_PIXEL_MODE(0), |
2356 | CF_INST(SQ_CF_INST_CALL), | | 2353 | CF_INST(SQ_CF_INST_NOP), |
2357 | WHOLE_QUAD_MODE(0), | | 2354 | WHOLE_QUAD_MODE(0), |
2358 | BARRIER(0)); | | 2355 | BARRIER(1)); |
2359 | | | 2356 | |
2360 | /* 3 */ | | 2357 | /* 3 - mask sub */ |
2361 | /* call read-constant-src if boolean0 == false */ | | 2358 | shader[i++] = CF_DWORD0(ADDR(14)); |
2362 | shader[i++] = CF_DWORD0(ADDR(8)); | | | |
2363 | shader[i++] = CF_DWORD1(POP_COUNT(0), | | 2359 | shader[i++] = CF_DWORD1(POP_COUNT(0), |
2364 | CF_CONST(0), | | 2360 | CF_CONST(0), |
2365 | COND(SQ_CF_COND_NOT_BOOL), | | 2361 | COND(SQ_CF_COND_ACTIVE), |
2366 | I_COUNT(0), | | 2362 | I_COUNT(2), |
2367 | CALL_COUNT(0), | | 2363 | CALL_COUNT(0), |
2368 | END_OF_PROGRAM(0), | | 2364 | END_OF_PROGRAM(0), |
2369 | VALID_PIXEL_MODE(0), | | 2365 | VALID_PIXEL_MODE(0), |
2370 | CF_INST(SQ_CF_INST_CALL), | | 2366 | CF_INST(SQ_CF_INST_TEX), |
2371 | WHOLE_QUAD_MODE(0), | | 2367 | WHOLE_QUAD_MODE(0), |
2372 | BARRIER(0)); | | 2368 | BARRIER(1)); |
2373 | | | 2369 | |
2374 | /* 4 */ | | 2370 | /* 4 */ |
2375 | /* src IN mask (GPR0 := GPR1 .* GPR0) */ | | 2371 | shader[i++] = CF_ALU_DWORD0(ADDR(10), |
2376 | shader[i++] = CF_ALU_DWORD0(ADDR(14), | | | |
2377 | KCACHE_BANK0(0), | | 2372 | KCACHE_BANK0(0), |
2378 | KCACHE_BANK1(0), | | 2373 | KCACHE_BANK1(0), |
2379 | KCACHE_MODE0(SQ_CF_KCACHE_NOP)); | | 2374 | KCACHE_MODE0(SQ_CF_KCACHE_NOP)); |
2380 | shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), | | 2375 | shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), |
2381 | KCACHE_ADDR0(0), | | 2376 | KCACHE_ADDR0(0), |
2382 | KCACHE_ADDR1(0), | | 2377 | KCACHE_ADDR1(0), |
2383 | I_COUNT(4), | | 2378 | I_COUNT(4), |
2384 | USES_WATERFALL(0), | | 2379 | USES_WATERFALL(0), |
2385 | CF_INST(SQ_CF_INST_ALU), | | 2380 | CF_INST(SQ_CF_INST_ALU), |
2386 | WHOLE_QUAD_MODE(0), | | 2381 | WHOLE_QUAD_MODE(0), |
2387 | BARRIER(1)); | | 2382 | BARRIER(1)); |
2388 | | | 2383 | |
2389 | /* 5 */ | | 2384 | /* 5 */ |
2390 | /* export pixel data */ | | | |
2391 | shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0), | | 2385 | shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0), |
2392 | TYPE(SQ_EXPORT_PIXEL), | | 2386 | TYPE(SQ_EXPORT_PIXEL), |
2393 | RW_GPR(0), | | 2387 | RW_GPR(2), |
2394 | RW_REL(ABSOLUTE), | | 2388 | RW_REL(ABSOLUTE), |
2395 | INDEX_GPR(0), | | 2389 | INDEX_GPR(0), |
2396 | ELEM_SIZE(1)); | | 2390 | ELEM_SIZE(1)); |
2397 | shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), | | 2391 | shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), |
2398 | SRC_SEL_Y(SQ_SEL_Y), | | 2392 | SRC_SEL_Y(SQ_SEL_Y), |
2399 | SRC_SEL_Z(SQ_SEL_Z), | | 2393 | SRC_SEL_Z(SQ_SEL_Z), |
2400 | SRC_SEL_W(SQ_SEL_W), | | 2394 | SRC_SEL_W(SQ_SEL_W), |
2401 | R6xx_ELEM_LOOP(0), | | 2395 | R6xx_ELEM_LOOP(0), |
2402 | BURST_COUNT(1), | | 2396 | BURST_COUNT(1), |
2403 | END_OF_PROGRAM(1), | | 2397 | END_OF_PROGRAM(0), |
2404 | VALID_PIXEL_MODE(0), | | 2398 | VALID_PIXEL_MODE(0), |
2405 | CF_INST(SQ_CF_INST_EXPORT_DONE), | | 2399 | CF_INST(SQ_CF_INST_EXPORT_DONE), |
2406 | WHOLE_QUAD_MODE(0), | | 2400 | WHOLE_QUAD_MODE(0), |
2407 | BARRIER(1)); | | 2401 | BARRIER(1)); |
2408 | /* subroutine fetch src */ | | | |
2409 | /* 6 */ | | 2402 | /* 6 */ |
2410 | /* fetch src into GPR0*/ | | 2403 | shader[i++] = CF_DWORD0(ADDR(0)); |
2411 | shader[i++] = CF_DWORD0(ADDR(26)); | | | |
2412 | shader[i++] = CF_DWORD1(POP_COUNT(0), | | 2404 | shader[i++] = CF_DWORD1(POP_COUNT(0), |
2413 | CF_CONST(0), | | 2405 | CF_CONST(0), |
2414 | COND(SQ_CF_COND_ACTIVE), | | 2406 | COND(SQ_CF_COND_ACTIVE), |
2415 | I_COUNT(1), | | 2407 | I_COUNT(0), |
2416 | CALL_COUNT(0), | | 2408 | CALL_COUNT(0), |
2417 | END_OF_PROGRAM(0), | | 2409 | END_OF_PROGRAM(0), |
2418 | VALID_PIXEL_MODE(0), | | 2410 | VALID_PIXEL_MODE(0), |
2419 | CF_INST(SQ_CF_INST_TEX), | | 2411 | CF_INST(SQ_CF_INST_RETURN), |
2420 | WHOLE_QUAD_MODE(0), | | 2412 | WHOLE_QUAD_MODE(0), |
2421 | BARRIER(1)); | | 2413 | BARRIER(1)); |
2422 | | | 2414 | |
2423 | /* 7 */ | | 2415 | /* 7 non-mask sub */ |
2424 | /* return */ | | 2416 | shader[i++] = CF_DWORD0(ADDR(18)); |
2425 | shader[i++] = CF_DWORD0(ADDR(0)); | | | |
2426 | shader[i++] = CF_DWORD1(POP_COUNT(0), | | 2417 | shader[i++] = CF_DWORD1(POP_COUNT(0), |
2427 | CF_CONST(0), | | 2418 | CF_CONST(0), |
2428 | COND(SQ_CF_COND_ACTIVE), | | 2419 | COND(SQ_CF_COND_ACTIVE), |
2429 | I_COUNT(0), | | 2420 | I_COUNT(1), |
2430 | CALL_COUNT(0), | | 2421 | CALL_COUNT(0), |
2431 | END_OF_PROGRAM(0), | | 2422 | END_OF_PROGRAM(0), |
2432 | VALID_PIXEL_MODE(0), | | 2423 | VALID_PIXEL_MODE(0), |
2433 | CF_INST(SQ_CF_INST_RETURN), | | 2424 | CF_INST(SQ_CF_INST_TEX), |
2434 | WHOLE_QUAD_MODE(0), | | 2425 | WHOLE_QUAD_MODE(0), |
2435 | BARRIER(1)); | | 2426 | BARRIER(1)); |
2436 | | | | |
2437 | /* subroutine read-constant-src*/ | | | |
2438 | /* 8 */ | | 2427 | /* 8 */ |
2439 | /* read constants into GPR0 */ | | 2428 | shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0), |
2440 | shader[i++] = CF_ALU_DWORD0(ADDR(18), | | 2429 | TYPE(SQ_EXPORT_PIXEL), |
2441 | KCACHE_BANK0(0), | | 2430 | RW_GPR(0), |
2442 | KCACHE_BANK1(0), | | 2431 | RW_REL(ABSOLUTE), |
2443 | KCACHE_MODE0(SQ_CF_KCACHE_NOP)); | | 2432 | INDEX_GPR(0), |
2444 | shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), | | 2433 | ELEM_SIZE(1)); |
2445 | KCACHE_ADDR0(0), | | 2434 | shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X), |
2446 | KCACHE_ADDR1(0), | | 2435 | SRC_SEL_Y(SQ_SEL_Y), |
2447 | I_COUNT(4), | | 2436 | SRC_SEL_Z(SQ_SEL_Z), |
2448 | USES_WATERFALL(0), | | 2437 | SRC_SEL_W(SQ_SEL_W), |
2449 | CF_INST(SQ_CF_INST_ALU), | | 2438 | R6xx_ELEM_LOOP(0), |
2450 | WHOLE_QUAD_MODE(0), | | 2439 | BURST_COUNT(1), |
2451 | BARRIER(1)); | | 2440 | END_OF_PROGRAM(0), |
| | | 2441 | VALID_PIXEL_MODE(0), |
| | | 2442 | CF_INST(SQ_CF_INST_EXPORT_DONE), |
| | | 2443 | WHOLE_QUAD_MODE(0), |
| | | 2444 | BARRIER(1)); |
2452 | /* 9 */ | | 2445 | /* 9 */ |
2453 | /* return */ | | | |
2454 | shader[i++] = CF_DWORD0(ADDR(0)); | | 2446 | shader[i++] = CF_DWORD0(ADDR(0)); |
2455 | shader[i++] = CF_DWORD1(POP_COUNT(0), | | 2447 | shader[i++] = CF_DWORD1(POP_COUNT(0), |
2456 | CF_CONST(0), | | 2448 | CF_CONST(0), |
2457 | COND(SQ_CF_COND_ACTIVE), | | 2449 | COND(SQ_CF_COND_ACTIVE), |
2458 | I_COUNT(0), | | 2450 | I_COUNT(0), |
2459 | CALL_COUNT(0), | | 2451 | CALL_COUNT(0), |
2460 | END_OF_PROGRAM(0), | | 2452 | END_OF_PROGRAM(0), |
2461 | VALID_PIXEL_MODE(0), | | 2453 | VALID_PIXEL_MODE(0), |
2462 | CF_INST(SQ_CF_INST_RETURN), | | 2454 | CF_INST(SQ_CF_INST_RETURN), |
2463 | WHOLE_QUAD_MODE(0), | | 2455 | WHOLE_QUAD_MODE(0), |
2464 | BARRIER(1)); | | 2456 | BARRIER(1)); |
2465 | | | 2457 | |
2466 | /* subroutine fetch mask */ | | 2458 | /* 10 - alu 0 */ |
2467 | /* 10 */ | | 2459 | /* MUL gpr[2].x gpr[1].x gpr[0].x */ |
2468 | /* fetch mask into GPR1*/ | | | |
2469 | shader[i++] = CF_DWORD0(ADDR(28)); | | | |
2470 | shader[i++] = CF_DWORD1(POP_COUNT(0), | | | |
2471 | CF_CONST(0), | | | |
2472 | COND(SQ_CF_COND_ACTIVE), | | | |
2473 | I_COUNT(1), | | | |
2474 | CALL_COUNT(0), | | | |
2475 | END_OF_PROGRAM(0), | | | |
2476 | VALID_PIXEL_MODE(0), | | | |
2477 | CF_INST(SQ_CF_INST_TEX), | | | |
2478 | WHOLE_QUAD_MODE(0), | | | |
2479 | BARRIER(1)); | | | |
2480 | | | | |
2481 | /* 11 */ | | | |
2482 | /* return */ | | | |
2483 | shader[i++] = CF_DWORD0(ADDR(0)); | | | |
2484 | shader[i++] = CF_DWORD1(POP_COUNT(0), | | | |
2485 | CF_CONST(0), | | | |
2486 | COND(SQ_CF_COND_ACTIVE), | | | |
2487 | I_COUNT(0), | | | |
2488 | CALL_COUNT(0), | | | |
2489 | END_OF_PROGRAM(0), | | | |
2490 | VALID_PIXEL_MODE(0), | | | |
2491 | CF_INST(SQ_CF_INST_RETURN), | | | |
2492 | WHOLE_QUAD_MODE(0), | | | |
2493 | BARRIER(1)); | | | |
2494 | | | | |
2495 | /* subroutine read-constant-mask*/ | | | |
2496 | /* 12 */ | | | |
2497 | /* read constants into GPR1 */ | | | |
2498 | shader[i++] = CF_ALU_DWORD0(ADDR(22), | | | |
2499 | KCACHE_BANK0(0), | | | |
2500 | KCACHE_BANK1(0), | | | |
2501 | KCACHE_MODE0(SQ_CF_KCACHE_NOP)); | | | |
2502 | shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP), | | | |
2503 | KCACHE_ADDR0(0), | | | |
2504 | KCACHE_ADDR1(0), | | | |
2505 | I_COUNT(4), | | | |
2506 | USES_WATERFALL(0), | | | |
2507 | CF_INST(SQ_CF_INST_ALU), | | | |
2508 | WHOLE_QUAD_MODE(0), | | | |
2509 | BARRIER(1)); | | | |
2510 | /* 13 */ | | | |
2511 | /* return */ | | | |
2512 | shader[i++] = CF_DWORD0(ADDR(0)); | | | |
2513 | shader[i++] = CF_DWORD1(POP_COUNT(0), | | | |
2514 | CF_CONST(0), | | | |
2515 | COND(SQ_CF_COND_ACTIVE), | | | |
2516 | I_COUNT(0), | | | |
2517 | CALL_COUNT(0), | | | |
2518 | END_OF_PROGRAM(0), | | | |
2519 | VALID_PIXEL_MODE(0), | | | |
2520 | CF_INST(SQ_CF_INST_RETURN), | | | |
2521 | WHOLE_QUAD_MODE(0), | | | |
2522 | BARRIER(1)); | | | |
2523 | /* ALU clauses */ | | | |
2524 | | | | |
2525 | /* 14 - alu 0 */ | | | |
2526 | /* MUL gpr[0].x gpr[1].x gpr[0].x */ | | | |
2527 | shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), | | 2460 | shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), |
2528 | SRC0_REL(ABSOLUTE), | | 2461 | SRC0_REL(ABSOLUTE), |
2529 | SRC0_ELEM(ELEM_X), | | 2462 | SRC0_ELEM(ELEM_X), |
2530 | SRC0_NEG(0), | | 2463 | SRC0_NEG(0), |
2531 | SRC1_SEL(ALU_SRC_GPR_BASE + 0), | | 2464 | SRC1_SEL(ALU_SRC_GPR_BASE + 0), |
2532 | SRC1_REL(ABSOLUTE), | | 2465 | SRC1_REL(ABSOLUTE), |
2533 | SRC1_ELEM(ELEM_X), | | 2466 | SRC1_ELEM(ELEM_X), |
2534 | SRC1_NEG(0), | | 2467 | SRC1_NEG(0), |
2535 | INDEX_MODE(SQ_INDEX_LOOP), | | 2468 | INDEX_MODE(SQ_INDEX_LOOP), |
2536 | PRED_SEL(SQ_PRED_SEL_OFF), | | 2469 | PRED_SEL(SQ_PRED_SEL_OFF), |
2537 | LAST(0)); | | 2470 | LAST(0)); |
2538 | shader[i++] = ALU_DWORD1_OP2(ChipSet, | | 2471 | shader[i++] = ALU_DWORD1_OP2(ChipSet, |
2539 | SRC0_ABS(0), | | 2472 | SRC0_ABS(0), |
2540 | SRC1_ABS(0), | | 2473 | SRC1_ABS(0), |
2541 | UPDATE_EXECUTE_MASK(0), | | 2474 | UPDATE_EXECUTE_MASK(0), |
2542 | UPDATE_PRED(0), | | 2475 | UPDATE_PRED(0), |
2543 | WRITE_MASK(1), | | 2476 | WRITE_MASK(1), |
2544 | FOG_MERGE(0), | | 2477 | FOG_MERGE(0), |
2545 | OMOD(SQ_ALU_OMOD_OFF), | | 2478 | OMOD(SQ_ALU_OMOD_OFF), |
2546 | ALU_INST(SQ_OP2_INST_MUL), | | 2479 | ALU_INST(SQ_OP2_INST_MUL), |
2547 | BANK_SWIZZLE(SQ_ALU_VEC_012), | | 2480 | BANK_SWIZZLE(SQ_ALU_VEC_012), |
2548 | DST_GPR(0), | | 2481 | DST_GPR(2), |
2549 | DST_REL(ABSOLUTE), | | 2482 | DST_REL(ABSOLUTE), |
2550 | DST_ELEM(ELEM_X), | | 2483 | DST_ELEM(ELEM_X), |
2551 | CLAMP(1)); | | 2484 | CLAMP(1)); |
2552 | /* 15 - alu 1 */ | | 2485 | /* 11 - alu 1 */ |
2553 | /* MUL gpr[0].y gpr[1].y gpr[0].y */ | | 2486 | /* MUL gpr[2].y gpr[1].y gpr[0].y */ |
2554 | shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), | | 2487 | shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), |
2555 | SRC0_REL(ABSOLUTE), | | 2488 | SRC0_REL(ABSOLUTE), |
2556 | SRC0_ELEM(ELEM_Y), | | 2489 | SRC0_ELEM(ELEM_Y), |
2557 | SRC0_NEG(0), | | 2490 | SRC0_NEG(0), |
2558 | SRC1_SEL(ALU_SRC_GPR_BASE + 0), | | 2491 | SRC1_SEL(ALU_SRC_GPR_BASE + 0), |
2559 | SRC1_REL(ABSOLUTE), | | 2492 | SRC1_REL(ABSOLUTE), |
2560 | SRC1_ELEM(ELEM_Y), | | 2493 | SRC1_ELEM(ELEM_Y), |
2561 | SRC1_NEG(0), | | 2494 | SRC1_NEG(0), |
2562 | INDEX_MODE(SQ_INDEX_LOOP), | | 2495 | INDEX_MODE(SQ_INDEX_LOOP), |
2563 | PRED_SEL(SQ_PRED_SEL_OFF), | | 2496 | PRED_SEL(SQ_PRED_SEL_OFF), |
2564 | LAST(0)); | | 2497 | LAST(0)); |
2565 | shader[i++] = ALU_DWORD1_OP2(ChipSet, | | 2498 | shader[i++] = ALU_DWORD1_OP2(ChipSet, |
2566 | SRC0_ABS(0), | | 2499 | SRC0_ABS(0), |
2567 | SRC1_ABS(0), | | 2500 | SRC1_ABS(0), |
2568 | UPDATE_EXECUTE_MASK(0), | | 2501 | UPDATE_EXECUTE_MASK(0), |
2569 | UPDATE_PRED(0), | | 2502 | UPDATE_PRED(0), |
2570 | WRITE_MASK(1), | | 2503 | WRITE_MASK(1), |
2571 | FOG_MERGE(0), | | 2504 | FOG_MERGE(0), |
2572 | OMOD(SQ_ALU_OMOD_OFF), | | 2505 | OMOD(SQ_ALU_OMOD_OFF), |
2573 | ALU_INST(SQ_OP2_INST_MUL), | | 2506 | ALU_INST(SQ_OP2_INST_MUL), |
2574 | BANK_SWIZZLE(SQ_ALU_VEC_012), | | 2507 | BANK_SWIZZLE(SQ_ALU_VEC_012), |
2575 | DST_GPR(0), | | 2508 | DST_GPR(2), |
2576 | DST_REL(ABSOLUTE), | | 2509 | DST_REL(ABSOLUTE), |
2577 | DST_ELEM(ELEM_Y), | | 2510 | DST_ELEM(ELEM_Y), |
2578 | CLAMP(1)); | | 2511 | CLAMP(1)); |
2579 | /* 16 - alu 2 */ | | 2512 | /* 12 - alu 2 */ |
2580 | /* MUL gpr[0].z gpr[1].z gpr[0].z */ | | 2513 | /* MUL gpr[2].z gpr[1].z gpr[0].z */ |
2581 | shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), | | 2514 | shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), |
2582 | SRC0_REL(ABSOLUTE), | | 2515 | SRC0_REL(ABSOLUTE), |
2583 | SRC0_ELEM(ELEM_Z), | | 2516 | SRC0_ELEM(ELEM_Z), |
2584 | SRC0_NEG(0), | | 2517 | SRC0_NEG(0), |
2585 | SRC1_SEL(ALU_SRC_GPR_BASE + 0), | | 2518 | SRC1_SEL(ALU_SRC_GPR_BASE + 0), |
2586 | SRC1_REL(ABSOLUTE), | | 2519 | SRC1_REL(ABSOLUTE), |
2587 | SRC1_ELEM(ELEM_Z), | | 2520 | SRC1_ELEM(ELEM_Z), |
2588 | SRC1_NEG(0), | | 2521 | SRC1_NEG(0), |
2589 | INDEX_MODE(SQ_INDEX_LOOP), | | 2522 | INDEX_MODE(SQ_INDEX_LOOP), |
2590 | PRED_SEL(SQ_PRED_SEL_OFF), | | 2523 | PRED_SEL(SQ_PRED_SEL_OFF), |
2591 | LAST(0)); | | 2524 | LAST(0)); |
2592 | shader[i++] = ALU_DWORD1_OP2(ChipSet, | | 2525 | shader[i++] = ALU_DWORD1_OP2(ChipSet, |
2593 | SRC0_ABS(0), | | 2526 | SRC0_ABS(0), |
2594 | SRC1_ABS(0), | | 2527 | SRC1_ABS(0), |
2595 | UPDATE_EXECUTE_MASK(0), | | 2528 | UPDATE_EXECUTE_MASK(0), |
2596 | UPDATE_PRED(0), | | 2529 | UPDATE_PRED(0), |
2597 | WRITE_MASK(1), | | 2530 | WRITE_MASK(1), |
2598 | FOG_MERGE(0), | | 2531 | FOG_MERGE(0), |
2599 | OMOD(SQ_ALU_OMOD_OFF), | | 2532 | OMOD(SQ_ALU_OMOD_OFF), |
2600 | ALU_INST(SQ_OP2_INST_MUL), | | 2533 | ALU_INST(SQ_OP2_INST_MUL), |
2601 | BANK_SWIZZLE(SQ_ALU_VEC_012), | | 2534 | BANK_SWIZZLE(SQ_ALU_VEC_012), |
2602 | DST_GPR(0), | | 2535 | DST_GPR(2), |
2603 | DST_REL(ABSOLUTE), | | 2536 | DST_REL(ABSOLUTE), |
2604 | DST_ELEM(ELEM_Z), | | 2537 | DST_ELEM(ELEM_Z), |
2605 | CLAMP(1)); | | 2538 | CLAMP(1)); |
2606 | /* 17 - alu 3 */ | | 2539 | /* 13 - alu 3 */ |
2607 | /* MUL gpr[0].w gpr[1].w gpr[0].w */ | | 2540 | /* MUL gpr[2].w gpr[1].w gpr[0].w */ |
2608 | shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), | | 2541 | shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1), |
2609 | SRC0_REL(ABSOLUTE), | | 2542 | SRC0_REL(ABSOLUTE), |
2610 | SRC0_ELEM(ELEM_W), | | 2543 | SRC0_ELEM(ELEM_W), |
2611 | SRC0_NEG(0), | | 2544 | SRC0_NEG(0), |
2612 | SRC1_SEL(ALU_SRC_GPR_BASE + 0), | | 2545 | SRC1_SEL(ALU_SRC_GPR_BASE + 0), |
2613 | SRC1_REL(ABSOLUTE), | | 2546 | SRC1_REL(ABSOLUTE), |
2614 | SRC1_ELEM(ELEM_W), | | 2547 | SRC1_ELEM(ELEM_W), |
2615 | SRC1_NEG(0), | | 2548 | SRC1_NEG(0), |
2616 | INDEX_MODE(SQ_INDEX_LOOP), | | 2549 | INDEX_MODE(SQ_INDEX_LOOP), |
2617 | PRED_SEL(SQ_PRED_SEL_OFF), | | 2550 | PRED_SEL(SQ_PRED_SEL_OFF), |
2618 | LAST(1)); | | 2551 | LAST(1)); |
2619 | shader[i++] = ALU_DWORD1_OP2(ChipSet, | | 2552 | shader[i++] = ALU_DWORD1_OP2(ChipSet, |
2620 | SRC0_ABS(0), | | 2553 | SRC0_ABS(0), |
2621 | SRC1_ABS(0), | | 2554 | SRC1_ABS(0), |
2622 | UPDATE_EXECUTE_MASK(0), | | 2555 | UPDATE_EXECUTE_MASK(0), |
2623 | UPDATE_PRED(0), | | 2556 | UPDATE_PRED(0), |
2624 | WRITE_MASK(1), | | 2557 | WRITE_MASK(1), |
2625 | FOG_MERGE(0), | | 2558 | FOG_MERGE(0), |
2626 | OMOD(SQ_ALU_OMOD_OFF), | | 2559 | OMOD(SQ_ALU_OMOD_OFF), |
2627 | ALU_INST(SQ_OP2_INST_MUL), | | 2560 | ALU_INST(SQ_OP2_INST_MUL), |
2628 | BANK_SWIZZLE(SQ_ALU_VEC_012), | | 2561 | BANK_SWIZZLE(SQ_ALU_VEC_012), |
2629 | DST_GPR(0), | | 2562 | DST_GPR(2), |
2630 | DST_REL(ABSOLUTE), | | | |
2631 | DST_ELEM(ELEM_W), | | | |
2632 | CLAMP(1)); | | | |
2633 | | | | |
2634 | /* 18 */ | | | |
2635 | shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 0), | | | |
2636 | SRC0_REL(ABSOLUTE), | | | |
2637 | SRC0_ELEM(ELEM_X), | | | |
2638 | SRC0_NEG(0), | | | |
2639 | SRC1_SEL(ALU_SRC_GPR_BASE + 0), | | | |
2640 | SRC1_REL(ABSOLUTE), | | | |
2641 | SRC1_ELEM(ELEM_X), | | | |
2642 | SRC1_NEG(0), | | | |
2643 | INDEX_MODE(SQ_INDEX_AR_X), | | | |
2644 | PRED_SEL(SQ_PRED_SEL_OFF), | | | |
2645 | LAST(0)); | | | |
2646 | shader[i++] = ALU_DWORD1_OP2(ChipSet, | | | |
2647 | SRC0_ABS(0), | | | |
2648 | SRC1_ABS(0), | | | |
2649 | UPDATE_EXECUTE_MASK(0), | | | |
2650 | UPDATE_PRED(0), | | | |
2651 | WRITE_MASK(1), | | | |
2652 | FOG_MERGE(0), | | | |
2653 | OMOD(SQ_ALU_OMOD_OFF), | | | |
2654 | ALU_INST(SQ_OP2_INST_MOV), | | | |
2655 | BANK_SWIZZLE(SQ_ALU_VEC_012), | | | |
2656 | DST_GPR(0), | | | |
2657 | DST_REL(ABSOLUTE), | | | |
2658 | DST_ELEM(ELEM_X), | | | |
2659 | CLAMP(1)); | | | |
2660 | /* 19 */ | | | |
2661 | shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 0), | | | |
2662 | SRC0_REL(ABSOLUTE), | | | |
2663 | SRC0_ELEM(ELEM_Y), | | | |
2664 | SRC0_NEG(0), | | | |
2665 | SRC1_SEL(ALU_SRC_GPR_BASE + 0), | | | |
2666 | SRC1_REL(ABSOLUTE), | | | |
2667 | SRC1_ELEM(ELEM_Y), | | | |
2668 | SRC1_NEG(0), | | | |
2669 | INDEX_MODE(SQ_INDEX_AR_X), | | | |
2670 | PRED_SEL(SQ_PRED_SEL_OFF), | | | |
2671 | LAST(0)); | | | |
2672 | shader[i++] = ALU_DWORD1_OP2(ChipSet, | | | |
2673 | SRC0_ABS(0), | | | |
2674 | SRC1_ABS(0), | | | |
2675 | UPDATE_EXECUTE_MASK(0), | | | |
2676 | UPDATE_PRED(0), | | | |
2677 | WRITE_MASK(1), | | | |
2678 | FOG_MERGE(0), | | | |
2679 | OMOD(SQ_ALU_OMOD_OFF), | | | |
2680 | ALU_INST(SQ_OP2_INST_MOV), | | | |
2681 | BANK_SWIZZLE(SQ_ALU_VEC_012), | | | |
2682 | DST_GPR(0), | | | |
2683 | DST_REL(ABSOLUTE), | | | |
2684 | DST_ELEM(ELEM_Y), | | | |
2685 | CLAMP(1)); | | | |
2686 | /* 20 */ | | | |
2687 | shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 0), | | | |
2688 | SRC0_REL(ABSOLUTE), | | | |
2689 | SRC0_ELEM(ELEM_Z), | | | |
2690 | SRC0_NEG(0), | | | |
2691 | SRC1_SEL(ALU_SRC_GPR_BASE + 0), | | | |
2692 | SRC1_REL(ABSOLUTE), | | | |
2693 | SRC1_ELEM(ELEM_Z), | | | |
2694 | SRC1_NEG(0), | | | |
2695 | INDEX_MODE(SQ_INDEX_AR_X), | | | |
2696 | PRED_SEL(SQ_PRED_SEL_OFF), | | | |
2697 | LAST(0)); | | | |
2698 | shader[i++] = ALU_DWORD1_OP2(ChipSet, | | | |
2699 | SRC0_ABS(0), | | | |
2700 | SRC1_ABS(0), | | | |
2701 | UPDATE_EXECUTE_MASK(0), | | | |
2702 | UPDATE_PRED(0), | | | |
2703 | WRITE_MASK(1), | | | |
2704 | FOG_MERGE(0), | | | |
2705 | OMOD(SQ_ALU_OMOD_OFF), | | | |
2706 | ALU_INST(SQ_OP2_INST_MOV), | | | |
2707 | BANK_SWIZZLE(SQ_ALU_VEC_012), | | | |
2708 | DST_GPR(0), | | | |
2709 | DST_REL(ABSOLUTE), | | | |
2710 | DST_ELEM(ELEM_Z), | | | |
2711 | CLAMP(1)); | | | |
2712 | /* 21 */ | | | |
2713 | shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 0), | | | |
2714 | SRC0_REL(ABSOLUTE), | | | |
2715 | SRC0_ELEM(ELEM_W), | | | |
2716 | SRC0_NEG(0), | | | |
2717 | SRC1_SEL(ALU_SRC_GPR_BASE + 0), | | | |
2718 | SRC1_REL(ABSOLUTE), | | | |
2719 | SRC1_ELEM(ELEM_W), | | | |
2720 | SRC1_NEG(0), | | | |
2721 | INDEX_MODE(SQ_INDEX_AR_X), | | | |
2722 | PRED_SEL(SQ_PRED_SEL_OFF), | | | |
2723 | LAST(1)); | | | |
2724 | shader[i++] = ALU_DWORD1_OP2(ChipSet, | | | |
2725 | SRC0_ABS(0), | | | |
2726 | SRC1_ABS(0), | | | |
2727 | UPDATE_EXECUTE_MASK(0), | | | |
2728 | UPDATE_PRED(0), | | | |
2729 | WRITE_MASK(1), | | | |
2730 | FOG_MERGE(0), | | | |
2731 | OMOD(SQ_ALU_OMOD_OFF), | | | |
2732 | ALU_INST(SQ_OP2_INST_MOV), | | | |
2733 | BANK_SWIZZLE(SQ_ALU_VEC_012), | | | |
2734 | DST_GPR(0), | | | |
2735 | DST_REL(ABSOLUTE), | | 2563 | DST_REL(ABSOLUTE), |
2736 | DST_ELEM(ELEM_W), | | 2564 | DST_ELEM(ELEM_W), |
2737 | CLAMP(1)); | | 2565 | CLAMP(1)); |
2738 | | | 2566 | |
2739 | /* 22 */ | | 2567 | /* 14/15 - src - mask */ |
2740 | shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 1), | | | |
2741 | SRC0_REL(ABSOLUTE), | | | |
2742 | SRC0_ELEM(ELEM_X), | | | |
2743 | SRC0_NEG(0), | | | |
2744 | SRC1_SEL(ALU_SRC_GPR_BASE + 0), | | | |
2745 | SRC1_REL(ABSOLUTE), | | | |
2746 | SRC1_ELEM(ELEM_X), | | | |
2747 | SRC1_NEG(0), | | | |
2748 | INDEX_MODE(SQ_INDEX_AR_X), | | | |
2749 | PRED_SEL(SQ_PRED_SEL_OFF), | | | |
2750 | LAST(0)); | | | |
2751 | shader[i++] = ALU_DWORD1_OP2(ChipSet, | | | |
2752 | SRC0_ABS(0), | | | |
2753 | SRC1_ABS(0), | | | |
2754 | UPDATE_EXECUTE_MASK(0), | | | |
2755 | UPDATE_PRED(0), | | | |
2756 | WRITE_MASK(1), | | | |
2757 | FOG_MERGE(0), | | | |
2758 | OMOD(SQ_ALU_OMOD_OFF), | | | |
2759 | ALU_INST(SQ_OP2_INST_MOV), | | | |
2760 | BANK_SWIZZLE(SQ_ALU_VEC_012), | | | |
2761 | DST_GPR(1), | | | |
2762 | DST_REL(ABSOLUTE), | | | |
2763 | DST_ELEM(ELEM_X), | | | |
2764 | CLAMP(1)); | | | |
2765 | /* 23 */ | | | |
2766 | shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 1), | | | |
2767 | SRC0_REL(ABSOLUTE), | | | |
2768 | SRC0_ELEM(ELEM_Y), | | | |
2769 | SRC0_NEG(0), | | | |
2770 | SRC1_SEL(ALU_SRC_GPR_BASE + 0), | | | |
2771 | SRC1_REL(ABSOLUTE), | | | |
2772 | SRC1_ELEM(ELEM_Y), | | | |
2773 | SRC1_NEG(0), | | | |
2774 | INDEX_MODE(SQ_INDEX_AR_X), | | | |
2775 | PRED_SEL(SQ_PRED_SEL_OFF), | | | |
2776 | LAST(0)); | | | |
2777 | shader[i++] = ALU_DWORD1_OP2(ChipSet, | | | |
2778 | SRC0_ABS(0), | | | |
2779 | SRC1_ABS(0), | | | |
2780 | UPDATE_EXECUTE_MASK(0), | | | |
2781 | UPDATE_PRED(0), | | | |
2782 | WRITE_MASK(1), | | | |
2783 | FOG_MERGE(0), | | | |
2784 | OMOD(SQ_ALU_OMOD_OFF), | | | |
2785 | ALU_INST(SQ_OP2_INST_MOV), | | | |
2786 | BANK_SWIZZLE(SQ_ALU_VEC_012), | | | |
2787 | DST_GPR(1), | | | |
2788 | DST_REL(ABSOLUTE), | | | |
2789 | DST_ELEM(ELEM_Y), | | | |
2790 | CLAMP(1)); | | | |
2791 | /* 24 */ | | | |
2792 | shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 1), | | | |
2793 | SRC0_REL(ABSOLUTE), | | | |
2794 | SRC0_ELEM(ELEM_Z), | | | |
2795 | SRC0_NEG(0), | | | |
2796 | SRC1_SEL(ALU_SRC_GPR_BASE + 0), | | | |
2797 | SRC1_REL(ABSOLUTE), | | | |
2798 | SRC1_ELEM(ELEM_Z), | | | |
2799 | SRC1_NEG(0), | | | |
2800 | INDEX_MODE(SQ_INDEX_AR_X), | | | |
2801 | PRED_SEL(SQ_PRED_SEL_OFF), | | | |
2802 | LAST(0)); | | | |
2803 | shader[i++] = ALU_DWORD1_OP2(ChipSet, | | | |
2804 | SRC0_ABS(0), | | | |
2805 | SRC1_ABS(0), | | | |
2806 | UPDATE_EXECUTE_MASK(0), | | | |
2807 | UPDATE_PRED(0), | | | |
2808 | WRITE_MASK(1), | | | |
2809 | FOG_MERGE(0), | | | |
2810 | OMOD(SQ_ALU_OMOD_OFF), | | | |
2811 | ALU_INST(SQ_OP2_INST_MOV), | | | |
2812 | BANK_SWIZZLE(SQ_ALU_VEC_012), | | | |
2813 | DST_GPR(1), | | | |
2814 | DST_REL(ABSOLUTE), | | | |
2815 | DST_ELEM(ELEM_Z), | | | |
2816 | CLAMP(1)); | | | |
2817 | /* 25 */ | | | |
2818 | shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 1), | | | |
2819 | SRC0_REL(ABSOLUTE), | | | |
2820 | SRC0_ELEM(ELEM_W), | | | |
2821 | SRC0_NEG(0), | | | |
2822 | SRC1_SEL(ALU_SRC_GPR_BASE + 0), | | | |
2823 | SRC1_REL(ABSOLUTE), | | | |
2824 | SRC1_ELEM(ELEM_W), | | | |
2825 | SRC1_NEG(0), | | | |
2826 | INDEX_MODE(SQ_INDEX_AR_X), | | | |
2827 | PRED_SEL(SQ_PRED_SEL_OFF), | | | |
2828 | LAST(1)); | | | |
2829 | shader[i++] = ALU_DWORD1_OP2(ChipSet, | | | |
2830 | SRC0_ABS(0), | | | |
2831 | SRC1_ABS(0), | | | |
2832 | UPDATE_EXECUTE_MASK(0), | | | |
2833 | UPDATE_PRED(0), | | | |
2834 | WRITE_MASK(1), | | | |
2835 | FOG_MERGE(0), | | | |
2836 | OMOD(SQ_ALU_OMOD_OFF), | | | |
2837 | ALU_INST(SQ_OP2_INST_MOV), | | | |
2838 | BANK_SWIZZLE(SQ_ALU_VEC_012), | | | |
2839 | DST_GPR(1), | | | |
2840 | DST_REL(ABSOLUTE), | | | |
2841 | DST_ELEM(ELEM_W), | | | |
2842 | CLAMP(1)); | | | |
2843 | | | | |
2844 | /* 26/27 - src */ | | | |
2845 | shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), | | 2568 | shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), |
2846 | BC_FRAC_MODE(0), | | 2569 | BC_FRAC_MODE(0), |
2847 | FETCH_WHOLE_QUAD(0), | | 2570 | FETCH_WHOLE_QUAD(0), |
2848 | RESOURCE_ID(0), | | 2571 | RESOURCE_ID(0), |
2849 | SRC_GPR(0), | | 2572 | SRC_GPR(0), |
2850 | SRC_REL(ABSOLUTE), | | 2573 | SRC_REL(ABSOLUTE), |
2851 | R7xx_ALT_CONST(0)); | | 2574 | R7xx_ALT_CONST(0)); |
2852 | shader[i++] = TEX_DWORD1(DST_GPR(0), | | 2575 | shader[i++] = TEX_DWORD1(DST_GPR(0), |
2853 | DST_REL(ABSOLUTE), | | 2576 | DST_REL(ABSOLUTE), |
2854 | DST_SEL_X(SQ_SEL_X), | | 2577 | DST_SEL_X(SQ_SEL_X), |
2855 | DST_SEL_Y(SQ_SEL_Y), | | 2578 | DST_SEL_Y(SQ_SEL_Y), |
2856 | DST_SEL_Z(SQ_SEL_Z), | | 2579 | DST_SEL_Z(SQ_SEL_Z), |
2857 | DST_SEL_W(SQ_SEL_W), | | 2580 | DST_SEL_W(SQ_SEL_W), |
| @@ -2859,27 +2582,27 @@ int R600_comp_ps(RADEONChipFamily ChipSe | | | @@ -2859,27 +2582,27 @@ int R600_comp_ps(RADEONChipFamily ChipSe |
2859 | COORD_TYPE_X(TEX_NORMALIZED), | | 2582 | COORD_TYPE_X(TEX_NORMALIZED), |
2860 | COORD_TYPE_Y(TEX_NORMALIZED), | | 2583 | COORD_TYPE_Y(TEX_NORMALIZED), |
2861 | COORD_TYPE_Z(TEX_NORMALIZED), | | 2584 | COORD_TYPE_Z(TEX_NORMALIZED), |
2862 | COORD_TYPE_W(TEX_NORMALIZED)); | | 2585 | COORD_TYPE_W(TEX_NORMALIZED)); |
2863 | shader[i++] = TEX_DWORD2(OFFSET_X(0), | | 2586 | shader[i++] = TEX_DWORD2(OFFSET_X(0), |
2864 | OFFSET_Y(0), | | 2587 | OFFSET_Y(0), |
2865 | OFFSET_Z(0), | | 2588 | OFFSET_Z(0), |
2866 | SAMPLER_ID(0), | | 2589 | SAMPLER_ID(0), |
2867 | SRC_SEL_X(SQ_SEL_X), | | 2590 | SRC_SEL_X(SQ_SEL_X), |
2868 | SRC_SEL_Y(SQ_SEL_Y), | | 2591 | SRC_SEL_Y(SQ_SEL_Y), |
2869 | SRC_SEL_Z(SQ_SEL_0), | | 2592 | SRC_SEL_Z(SQ_SEL_0), |
2870 | SRC_SEL_W(SQ_SEL_1)); | | 2593 | SRC_SEL_W(SQ_SEL_1)); |
2871 | shader[i++] = TEX_DWORD_PAD; | | 2594 | shader[i++] = TEX_DWORD_PAD; |
2872 | /* 28/29 - mask */ | | 2595 | /* 16/17 - mask */ |
2873 | shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), | | 2596 | shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), |
2874 | BC_FRAC_MODE(0), | | 2597 | BC_FRAC_MODE(0), |
2875 | FETCH_WHOLE_QUAD(0), | | 2598 | FETCH_WHOLE_QUAD(0), |
2876 | RESOURCE_ID(1), | | 2599 | RESOURCE_ID(1), |
2877 | SRC_GPR(1), | | 2600 | SRC_GPR(1), |
2878 | SRC_REL(ABSOLUTE), | | 2601 | SRC_REL(ABSOLUTE), |
2879 | R7xx_ALT_CONST(0)); | | 2602 | R7xx_ALT_CONST(0)); |
2880 | shader[i++] = TEX_DWORD1(DST_GPR(1), | | 2603 | shader[i++] = TEX_DWORD1(DST_GPR(1), |
2881 | DST_REL(ABSOLUTE), | | 2604 | DST_REL(ABSOLUTE), |
2882 | DST_SEL_X(SQ_SEL_X), | | 2605 | DST_SEL_X(SQ_SEL_X), |
2883 | DST_SEL_Y(SQ_SEL_Y), | | 2606 | DST_SEL_Y(SQ_SEL_Y), |
2884 | DST_SEL_Z(SQ_SEL_Z), | | 2607 | DST_SEL_Z(SQ_SEL_Z), |
2885 | DST_SEL_W(SQ_SEL_W), | | 2608 | DST_SEL_W(SQ_SEL_W), |
| @@ -2888,15 +2611,44 @@ int R600_comp_ps(RADEONChipFamily ChipSe | | | @@ -2888,15 +2611,44 @@ int R600_comp_ps(RADEONChipFamily ChipSe |
2888 | COORD_TYPE_Y(TEX_NORMALIZED), | | 2611 | COORD_TYPE_Y(TEX_NORMALIZED), |
2889 | COORD_TYPE_Z(TEX_NORMALIZED), | | 2612 | COORD_TYPE_Z(TEX_NORMALIZED), |
2890 | COORD_TYPE_W(TEX_NORMALIZED)); | | 2613 | COORD_TYPE_W(TEX_NORMALIZED)); |
2891 | shader[i++] = TEX_DWORD2(OFFSET_X(0), | | 2614 | shader[i++] = TEX_DWORD2(OFFSET_X(0), |
2892 | OFFSET_Y(0), | | 2615 | OFFSET_Y(0), |
2893 | OFFSET_Z(0), | | 2616 | OFFSET_Z(0), |
2894 | SAMPLER_ID(1), | | 2617 | SAMPLER_ID(1), |
2895 | SRC_SEL_X(SQ_SEL_X), | | 2618 | SRC_SEL_X(SQ_SEL_X), |
2896 | SRC_SEL_Y(SQ_SEL_Y), | | 2619 | SRC_SEL_Y(SQ_SEL_Y), |
2897 | SRC_SEL_Z(SQ_SEL_0), | | 2620 | SRC_SEL_Z(SQ_SEL_0), |
2898 | SRC_SEL_W(SQ_SEL_1)); | | 2621 | SRC_SEL_W(SQ_SEL_1)); |
2899 | shader[i++] = TEX_DWORD_PAD; | | 2622 | shader[i++] = TEX_DWORD_PAD; |
2900 | | | 2623 | |
| | | 2624 | /* 18/19 - src - non-mask */ |
| | | 2625 | shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE), |
| | | 2626 | BC_FRAC_MODE(0), |
| | | 2627 | FETCH_WHOLE_QUAD(0), |
| | | 2628 | RESOURCE_ID(0), |
| | | 2629 | SRC_GPR(0), |
| | | 2630 | SRC_REL(ABSOLUTE), |
| | | 2631 | R7xx_ALT_CONST(0)); |
| | | 2632 | shader[i++] = TEX_DWORD1(DST_GPR(0), |
| | | 2633 | DST_REL(ABSOLUTE), |
| | | 2634 | DST_SEL_X(SQ_SEL_X), |
| | | 2635 | DST_SEL_Y(SQ_SEL_Y), |
| | | 2636 | DST_SEL_Z(SQ_SEL_Z), |
| | | 2637 | DST_SEL_W(SQ_SEL_W), |
| | | 2638 | LOD_BIAS(0), |
| | | 2639 | COORD_TYPE_X(TEX_NORMALIZED), |
| | | 2640 | COORD_TYPE_Y(TEX_NORMALIZED), |
| | | 2641 | COORD_TYPE_Z(TEX_NORMALIZED), |
| | | 2642 | COORD_TYPE_W(TEX_NORMALIZED)); |
| | | 2643 | shader[i++] = TEX_DWORD2(OFFSET_X(0), |
| | | 2644 | OFFSET_Y(0), |
| | | 2645 | OFFSET_Z(0), |
| | | 2646 | SAMPLER_ID(0), |
| | | 2647 | SRC_SEL_X(SQ_SEL_X), |
| | | 2648 | SRC_SEL_Y(SQ_SEL_Y), |
| | | 2649 | SRC_SEL_Z(SQ_SEL_0), |
| | | 2650 | SRC_SEL_W(SQ_SEL_1)); |
| | | 2651 | shader[i++] = TEX_DWORD_PAD; |
| | | 2652 | |
2901 | return i; | | 2653 | return i; |
2902 | } | | 2654 | } |