 @@ -1,14 +1,14 @@
-/* $NetBSD: awin_reg.h,v 1.90 2016/12/26 16:20:17 rjs Exp $ */
+/* $NetBSD: awin_reg.h,v 1.90.2.1 2017/04/17 20:41:55 bouyer Exp $ */
 /*-
  * Copyright (c) 2013 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Matt Thomas of 3am Software Foundry.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -3061,14 +3061,130 @@ struct awin_a31_dma_desc {
 #define AWIN_LRADC_INT_KEYUP1		__BIT(12)
 #define AWIN_LRADC_INT_ALREADYHOLD1	__BIT(11)
 #define AWIN_LRADC_INT_HOLD1		__BIT(10)
 #define AWIN_LRADC_INT_KEY1		__BIT(9)
 #define AWIN_LRADC_INT_DATA1		__BIT(8)
 #define AWIN_LRADC_INT_KEYUP0		__BIT(4)
 #define AWIN_LRADC_INT_ALREADYHOLD0	__BIT(3)
 #define AWIN_LRADC_INT_HOLD0		__BIT(2)
 #define AWIN_LRADC_INT_KEY0		__BIT(1)
 #define AWIN_LRADC_INT_DATA0		__BIT(0)
 #define AWIN_LRADC_DATA0_REG		0x0c
 #define AWIN_LRADC_DATA1_REG		0x10
 /* CAN mode select register */
 #define AWIN_CAN_MODSEL_REG		0x00
 #define AWIN_CAN_MODSEL_SLEEP		__BIT(4)
 #define AWIN_CAN_MODSEL_ACP_FLT_MOD	__BIT(3)
 #define AWIN_CAN_MODSEL_LB_MOD		__BIT(2)
 #define AWIN_CAN_MODSEL_LST_ONLY	__BIT(1)
 #define AWIN_CAN_MODSEL_RST		__BIT(0)
 /* CAN command register */
 #define AWIN_CAN_CMD_REG	0x04
 #define AWIN_CAN_CMD_BUS_OFF		__BIT(5)
 #define AWIN_CAN_CMD_SELF_REQ		__BIT(4)
 #define AWIN_CAN_CMD_CLR_OR		__BIT(3)
 #define AWIN_CAN_CMD_REL_RX_BUF		__BIT(2)
 #define AWIN_CAN_CMD_ABT_REQ		__BIT(1)
 #define AWIN_CAN_CMD_TANS_REQ		__BIT(0)
 /* CAN status register */
 #define AWIN_CAN_STA_REG	0x08
 #define AWIN_CAN_STA_ERR_CODE		__BITS(23,22)
 #define AWIN_CAN_STA_ERR_CODE_BIT		0
 #define AWIN_CAN_STA_ERR_CODE_FORM		1
 #define AWIN_CAN_STA_ERR_CODE_STUFF		2
 #define AWIN_CAN_STA_ERR_CODE_OTHER		3
 #define AWIN_CAN_STA_ERR_DIR		_BIT(21)
 #define AWIN_CAN_STA_ERR_SEG_CODE	__BITS(20,16)
 #define AWIN_CAN_STA_ARB_LOST		__BITS(12,8)
 #define AWIN_CAN_STA_BUS		__BIT(7)
 #define AWIN_CAN_STA_ERR		__BIT(6)
 #define AWIN_CAN_STA_TX 		__BIT(5)
 #define AWIN_CAN_STA_RX 		__BIT(4)
 #define AWIN_CAN_STA_TX_OVER		__BIT(3)
 #define AWIN_CAN_STA_TX_RDY		__BIT(2)
 #define AWIN_CAN_STA_DATA_OR		__BIT(1)
 #define AWIN_CAN_STA_RX_RDY		__BIT(0)
 /* CAN interrupt register */
 #define AWIN_CAN_INT_REG	0x0c
 #define AWIN_CAN_INT_BERR		__BIT(7)
 #define AWIN_CAN_INT_ARB_LOST		__BIT(6)
 #define AWIN_CAN_INT_ERR_PASSIVE	__BIT(5)
 #define AWIN_CAN_INT_WAKEUP		__BIT(4)
 #define AWIN_CAN_INT_DATA_OR		__BIT(3)
 #define AWIN_CAN_INT_ERR		__BIT(2)
 #define AWIN_CAN_INT_TX_FLAG		__BIT(1)
 #define AWIN_CAN_INT_RX_FLAG		__BIT(0)
 /* CAN interrupt enable register */
 #define AWIN_CAN_INTE_REG	0x10
 /* CAN bus timing register */
 #define AWIN_CAN_BUS_TIME_REG	0x14
 #define AWIN_CAN_BUS_TIME_SAM		__BIT(23)
 #define AWIN_CAN_BUS_TIME_PHSEG2	__BITS(22,20)
 #define AWIN_CAN_BUS_TIME_PHSEG1	__BITS(19,16)
 #define AWIN_CAN_BUS_TIME_SJW		__BITS(15,14)
 #define AWIN_CAN_BUS_TIME_TQ_BRP	__BITS(9,0)
 /* CAN tx error warning limit register */
 #define AWIN_CAN_EWL_REG	0x18
 #define AWIN_CAN_EWL_ERR_WRN_LMT	__BITS(7,0)
 /* CAN error counter register */
 #define AWIN_CAN_REC_REG	0x1c
 #define AWIN_CAN_REC_RX_ERR_CNT		__BITS(23,16)
 #define AWIN_CAN_REC_TX_ERR_CNT		__BITS(7,0)
 /* CAN receive message register */
 #define AWIN_CAN_RMSGC_REG	0x20
 #define AWIN_CAN_RMSGC_RX_MSG_CNT	__BITS(7,0)
 /* CAN receive buffer start address register */
 #define AWIN_CAN_RSADDR_REG	0x24
 #define AWIN_CAN_RSADDR_RX_BUF_SADDR	__BITS(5,0)
 /* CAN rx/tx message buffer 0 register */
 #define AWIN_CAN_TXBUF0_REG	0x40
 #define AWIN_CAN_TXBUF0_EFF		__BIT(7)
 #define AWIN_CAN_TXBUF0_RTR		__BIT(6)
 #define AWIN_CAN_TXBUF0_DL		__BITS(3,0)
 /* CAN rx/tx message buffer registers */
 #define AWIN_CAN_TXBUF1_REG	0x44
 #define AWIN_CAN_TXBUF2_REG	0x48
 #define AWIN_CAN_TXBUF3_REG	0x4c
 #define AWIN_CAN_TXBUF4_REG	0x50
 #define AWIN_CAN_TXBUF5_REG	0x54
 #define AWIN_CAN_TXBUF6_REG	0x58
 #define AWIN_CAN_TXBUF7_REG	0x5c
 #define AWIN_CAN_TXBUF8_REG	0x60
 #define AWIN_CAN_TXBUF9_REG	0x64
 #define AWIN_CAN_TXBUF10_REG	0x68
 #define AWIN_CAN_TXBUF11_REG	0x6c
 #define AWIN_CAN_TXBUF12_REG	0x70
 /* CAN acceptance code 0 register */
 #define AWIN_CAN_ACPC		0x40
 /* CAN acceptance mask 0 register */
 #define AWIN_CAN_ACPM		0x44
 /* CAN transmit buffer for read back registers */
 #define AWIN_CAN_RBUF_RBACK0	0x180
 #define AWIN_CAN_RBUF_RBACK1	0x184
 #define AWIN_CAN_RBUF_RBACK2	0x188
 #define AWIN_CAN_RBUF_RBACK3	0x18c
 #define AWIN_CAN_RBUF_RBACK4	0x190
 #define AWIN_CAN_RBUF_RBACK5	0x194
 #define AWIN_CAN_RBUF_RBACK6	0x198
 #define AWIN_CAN_RBUF_RBACK7	0x19c
 #define AWIN_CAN_RBUF_RBACK8	0x1a0
 #define AWIN_CAN_RBUF_RBACK9	0x1a4
 #define AWIN_CAN_RBUF_RBACK10	0x1a8
 #define AWIN_CAN_RBUF_RBACK11	0x1ac
 #define AWIN_CAN_RBUF_RBACK12	0x1b0
 #endif /* _ARM_ALLWINNER_AWIN_REG_H_ */