Sat Jun 10 06:25:29 2017 UTC ()
Pull up following revision(s) (requested by skrll in ticket #25):
	sys/arch/mips/mips/locore_mips1.S: revision 1.92, 1.93
fix tlb_record_asids 2nd arg to match usage - it's a maximum asid value
and not a mask
--
Add a missing ".set at" to make previous build


(snj)
diff -r1.91 -r1.91.8.1 src/sys/arch/mips/mips/locore_mips1.S
cvs diff -r1.91 -r1.91.8.1 src/sys/arch/mips/mips/locore_mips1.S (expand / switch to unified diff)

--- src/sys/arch/mips/mips/locore_mips1.S 2016/07/27 09:32:35 1.91
+++ src/sys/arch/mips/mips/locore_mips1.S 2017/06/10 06:25:29 1.91.8.1
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: locore_mips1.S,v 1.91 2016/07/27 09:32:35 skrll Exp $ */ 1/* $NetBSD: locore_mips1.S,v 1.91.8.1 2017/06/10 06:25:29 snj Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 1992, 1993 4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved. 5 * The Regents of the University of California. All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to Berkeley by 7 * This code is derived from software contributed to Berkeley by
8 * Digital Equipment Corporation and Ralph Campbell. 8 * Digital Equipment Corporation and Ralph Campbell.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -47,27 +47,27 @@ @@ -47,27 +47,27 @@
47 * v 1.1 89/07/10 14:27:41 nelson Exp SPRITE (DECWRL) 47 * v 1.1 89/07/10 14:27:41 nelson Exp SPRITE (DECWRL)
48 * 48 *
49 * @(#)locore.s 8.5 (Berkeley) 1/4/94 49 * @(#)locore.s 8.5 (Berkeley) 1/4/94
50 */ 50 */
51#include "opt_cputype.h" 51#include "opt_cputype.h"
52#include "opt_ddb.h" 52#include "opt_ddb.h"
53#include "opt_kgdb.h" 53#include "opt_kgdb.h"
54 54
55#include <sys/cdefs.h> 55#include <sys/cdefs.h>
56 56
57#include <mips/asm.h> 57#include <mips/asm.h>
58#include <mips/cpuregs.h> 58#include <mips/cpuregs.h>
59 59
60RCSID("$NetBSD: locore_mips1.S,v 1.91 2016/07/27 09:32:35 skrll Exp $") 60RCSID("$NetBSD: locore_mips1.S,v 1.91.8.1 2017/06/10 06:25:29 snj Exp $")
61 61
62#include "assym.h" 62#include "assym.h"
63 63
64#define _SLLV sllv 64#define _SLLV sllv
65 65
66#define _SLL sll 66#define _SLL sll
67#define _SRL srl 67#define _SRL srl
68#define WIRED_SHIFT 2 68#define WIRED_SHIFT 2
69 69
70/* 70/*
71 * Use correct-sized m?c0/dm?c0 opcodes. 71 * Use correct-sized m?c0/dm?c0 opcodes.
72 */ 72 */
73#define _MFC0 mfc0 73#define _MFC0 mfc0
@@ -1025,26 +1025,27 @@ LEAF_NOPROFILE(MIPSX(kern_tlb_miss)) @@ -1025,26 +1025,27 @@ LEAF_NOPROFILE(MIPSX(kern_tlb_miss))
1025 beqz k1, _C_LABEL(MIPSX(kern_gen_exception)) # full trap processing 1025 beqz k1, _C_LABEL(MIPSX(kern_gen_exception)) # full trap processing
1026 PTR_SRL k0, PGSHIFT - PTPSHIFT # - delay slot - 1026 PTR_SRL k0, PGSHIFT - PTPSHIFT # - delay slot -
1027 and k0, (NPTEPG-1) << PTPSHIFT # get ptp index (part2) 1027 and k0, (NPTEPG-1) << PTPSHIFT # get ptp index (part2)
1028 PTR_ADDU k1, k0 # add to PTP address 1028 PTR_ADDU k1, k0 # add to PTP address
1029 INT_L k0, 0(k1) # get PTE entry 1029 INT_L k0, 0(k1) # get PTE entry
1030 _MFC0 k1, MIPS_COP_0_EXC_PC # get return address 1030 _MFC0 k1, MIPS_COP_0_EXC_PC # get return address
1031 mtc0 k0, MIPS_COP_0_TLB_LOW # save PTE entry 1031 mtc0 k0, MIPS_COP_0_TLB_LOW # save PTE entry
1032 and k0, MIPS1_PG_V # check for valid PTE entry 1032 and k0, MIPS1_PG_V # check for valid PTE entry
1033 beqz k0, _C_LABEL(MIPSX(kern_gen_exception)) # PTE invalid 1033 beqz k0, _C_LABEL(MIPSX(kern_gen_exception)) # PTE invalid
1034 nop 1034 nop
1035 tlbwr # write random TLB 1035 tlbwr # write random TLB
1036 j k1 1036 j k1
1037 rfe 1037 rfe
 1038 .set at
1038END(MIPSX(kern_tlb_miss)) 1039END(MIPSX(kern_tlb_miss))
1039 1040
1040#if 0 1041#if 0
1041/*---------------------------------------------------------------------------- 1042/*----------------------------------------------------------------------------
1042 * 1043 *
1043 * mipsN_tlb_invalid_exception -- 1044 * mipsN_tlb_invalid_exception --
1044 * 1045 *
1045 * Handle a TLB modified exception. 1046 * Handle a TLB modified exception.
1046 * The BaddVAddr, Context, and EntryHi registers contain the failed 1047 * The BaddVAddr, Context, and EntryHi registers contain the failed
1047 * virtual address. 1048 * virtual address.
1048 * 1049 *
1049 * Results: 1050 * Results:
1050 * None. 1051 * None.
@@ -1358,27 +1359,27 @@ LEAF(MIPSX(tlb_invalidate_all)) @@ -1358,27 +1359,27 @@ LEAF(MIPSX(tlb_invalidate_all))
1358 # do {} while (t1 < a0) 1359 # do {} while (t1 < a0)
13591: 13601:
1360 mtc0 t0, MIPS_COP_0_TLB_INDEX # set TLBindex 1361 mtc0 t0, MIPS_COP_0_TLB_INDEX # set TLBindex
1361 addu t0, t0, 1 << MIPS1_TLB_INDEX_SHIFT # increment index 1362 addu t0, t0, 1 << MIPS1_TLB_INDEX_SHIFT # increment index
1362 bne t0, a0, 1b 1363 bne t0, a0, 1b
1363 tlbwi # invalidate the entry 1364 tlbwi # invalidate the entry
1364 1365
1365 mtc0 ta1, MIPS_COP_0_TLB_HI # restore PID 1366 mtc0 ta1, MIPS_COP_0_TLB_HI # restore PID
1366 j ra 1367 j ra
1367 mtc0 ta0, MIPS_COP_0_STATUS # restore status register 1368 mtc0 ta0, MIPS_COP_0_STATUS # restore status register
1368END(MIPSX(tlb_invalidate_all)) 1369END(MIPSX(tlb_invalidate_all))
1369 1370
1370/* 1371/*
1371 * u_int mipsN_tlb_record_asids(u_long *bitmap, uint32_t asid_mask) 1372 * u_int mipsN_tlb_record_asids(u_long *bitmap, uint32_t asid_max)
1372 * 1373 *
1373 * Scan the random part of the TLB looking at non-global entries and 1374 * Scan the random part of the TLB looking at non-global entries and
1374 * record each ASID in use into the bitmap. Additionally, return the 1375 * record each ASID in use into the bitmap. Additionally, return the
1375 * number of new unique ASIDs encountered. 1376 * number of new unique ASIDs encountered.
1376 */ 1377 */
1377LEAF(MIPSX(tlb_record_asids)) 1378LEAF(MIPSX(tlb_record_asids))
1378 mfc0 ta1, MIPS_COP_0_TLB_HI # save EntryHi 1379 mfc0 ta1, MIPS_COP_0_TLB_HI # save EntryHi
1379 li v1, MIPS1_TLB_FIRST_RAND_ENTRY << MIPS1_TLB_INDEX_SHIFT 1380 li v1, MIPS1_TLB_FIRST_RAND_ENTRY << MIPS1_TLB_INDEX_SHIFT
1380 INT_L a3, _C_LABEL(mips_options) + MO_NUM_TLB_ENTRIES 1381 INT_L a3, _C_LABEL(mips_options) + MO_NUM_TLB_ENTRIES
1381 move ta2, zero 1382 move ta2, zero
1382 li ta3, 1 1383 li ta3, 1
1383 sll a3, MIPS1_TLB_INDEX_SHIFT 1384 sll a3, MIPS1_TLB_INDEX_SHIFT
1384 1385
@@ -1392,27 +1393,28 @@ LEAF(MIPSX(tlb_record_asids)) @@ -1392,27 +1393,28 @@ LEAF(MIPSX(tlb_record_asids))
1392 mtc0 v1, MIPS_COP_0_TLB_INDEX # set index 1393 mtc0 v1, MIPS_COP_0_TLB_INDEX # set index
1393 nop 1394 nop
1394 tlbr # obtain an entry 1395 tlbr # obtain an entry
1395 mfc0 t0, MIPS_COP_0_TLB_LOW 1396 mfc0 t0, MIPS_COP_0_TLB_LOW
1396 nop 1397 nop
1397 and t0, MIPS1_PG_G # check to see it has G bit 1398 and t0, MIPS1_PG_G # check to see it has G bit
1398 bnez t0, 4f 1399 bnez t0, 4f
1399 nop 1400 nop
1400 1401
1401 mfc0 t0, MIPS_COP_0_TLB_HI # get va and ASID 1402 mfc0 t0, MIPS_COP_0_TLB_HI # get va and ASID
1402 nop 1403 nop
1403 and t0, MIPS1_TLB_PID 1404 and t0, MIPS1_TLB_PID
1404 srl t0, MIPS1_TLB_PID_SHIFT # shift to low bits 1405 srl t0, MIPS1_TLB_PID_SHIFT # shift to low bits
1405 and t0, a1 # focus on asid_mask 1406 bgt t0, a1, 4f # > ASID max? skip
 1407 nop
1406 1408
1407 srl a2, t0, 3 + LONG_SCALESHIFT # drop low 5 bits 1409 srl a2, t0, 3 + LONG_SCALESHIFT # drop low 5 bits
1408 sll a2, LONG_SCALESHIFT # make an index for the bitmap 1410 sll a2, LONG_SCALESHIFT # make an index for the bitmap
1409 sllv t0, ta3, t0 # t0 is mask (ta3 == 1) 1411 sllv t0, ta3, t0 # t0 is mask (ta3 == 1)
1410 1412
1411 PTR_ADDU a2, a0 # index into the bitmap 1413 PTR_ADDU a2, a0 # index into the bitmap
1412 beq a2, ta2, 3f # is the desired cell loaded? 1414 beq a2, ta2, 3f # is the desired cell loaded?
1413 nop # yes, don't reload it 1415 nop # yes, don't reload it
1414 beqz ta2, 2f # have we ever loaded it? 1416 beqz ta2, 2f # have we ever loaded it?
1415 nop # nope, so don't save it 1417 nop # nope, so don't save it
1416 1418
1417 LONG_S t2, 0(ta2) # save the updated value. 1419 LONG_S t2, 0(ta2) # save the updated value.
14182: 14202: