Sat Jun 10 15:13:19 2017 UTC ()
Get the EXYNOS kernel building again with recent FDT changes. Untested.


(jmcneill)
diff -r1.1 -r0 src/sys/arch/arm/samsung/exynos5422_dma.c
diff -r1.4 -r0 src/sys/arch/arm/samsung/exynos_fdt.c
diff -r1.2 -r1.3 src/sys/arch/arm/samsung/exynos_intr.h
diff -r0 -r1.1 src/sys/arch/arm/samsung/exynos_platform.c
diff -r1.13 -r1.14 src/sys/arch/arm/samsung/exynos_reg.h
diff -r1.31 -r1.32 src/sys/arch/arm/samsung/exynos_soc.c
diff -r1.7 -r1.8 src/sys/arch/arm/samsung/exynos_sscom.c
diff -r1.21 -r1.22 src/sys/arch/arm/samsung/files.exynos
diff -r1.8 -r1.9 src/sys/arch/arm/samsung/sscom.c
diff -r1.14 -r1.15 src/sys/arch/evbarm/conf/EXYNOS
diff -r1.2 -r1.3 src/sys/arch/evbarm/conf/files.exynos
diff -r1.1 -r1.2 src/sys/arch/evbarm/conf/std.exynos
diff -r1.7 -r0 src/sys/arch/evbarm/exynos/exynos_machdep.c
diff -r1.1 -r1.2 src/sys/arch/evbarm/exynos/platform.h

File Deleted: src/sys/arch/arm/samsung/Attic/exynos5422_dma.c

File Deleted: src/sys/arch/arm/samsung/Attic/exynos_fdt.c

cvs diff -r1.2 -r1.3 src/sys/arch/arm/samsung/exynos_intr.h (switch to unified diff)

--- src/sys/arch/arm/samsung/exynos_intr.h 2014/09/05 08:01:05 1.2
+++ src/sys/arch/arm/samsung/exynos_intr.h 2017/06/10 15:13:18 1.3
@@ -1,69 +1,53 @@ @@ -1,69 +1,53 @@
1/* $NetBSD: exynos_intr.h,v 1.2 2014/09/05 08:01:05 skrll Exp $ */ 1/* $NetBSD: exynos_intr.h,v 1.3 2017/06/10 15:13:18 jmcneill Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 4 * Copyright (c) 2014 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Nick Hudson 8 * by Nick Hudson
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright 15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the 16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution. 17 * documentation and/or other materials provided with the distribution.
18 * 18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE. 29 * POSSIBILITY OF SUCH DAMAGE.
30 */ 30 */
31 31
32#ifndef _ARM_SAMSUNG_EXYNOS_INTR_H_ 32#ifndef _ARM_SAMSUNG_EXYNOS_INTR_H_
33#define _ARM_SAMSUNG_EXYNOS_INTR_H_ 33#define _ARM_SAMSUNG_EXYNOS_INTR_H_
34 34
35#define PIC_MAXSOURCES GIC_MAXSOURCES(224) 
36#define PIC_MAXMAXSOURCES (PIC_MAXSOURCES + 32) /* XXX */ 
37 
38/* 
39 * The Exynos uses a generic interrupt controller 
40 */ 
41#include <arm/cortex/gic_intr.h> 
42 
43#ifdef _KERNEL_OPT 
44#include "opt_exynos.h" 
45#endif 
46 
47/* 35/*
48 * The GIC supports 36 * The GIC supports
49 * - 16 Software Generated Interrupts (SGIs) 37 * - 16 Software Generated Interrupts (SGIs)
50 * - 16 Private Peripheral Interrupts (PPIs) 38 * - 16 Private Peripheral Interrupts (PPIs)
51 * - 127 Shared Peripheral Interrupts (SPIs) 39 * - 127 Shared Peripheral Interrupts (SPIs)
52 */ 40 */
53 41
54#define EXYNOS_NSPI 128 42#define EXYNOS_NSPI 128
55#define EXYNOS_COMBINERBASE EXYNOS_SPIBASE + EXYNOS_NSPI 43#define EXYNOS_COMBINERBASE EXYNOS_SPIBASE + EXYNOS_NSPI
56 44
57#define EXYNOS_BITSPERGROUP 8 45#define EXYNOS_BITSPERGROUP 8
58 46
59#define EXYNOS_COMBINERIRQ(g, b) \ 47#define EXYNOS_COMBINERIRQ(g, b) \
60 (EXYNOS_COMBINERBASE + ((g) * EXYNOS_BITSPERGROUP + (b))) 48 (EXYNOS_COMBINERBASE + ((g) * EXYNOS_BITSPERGROUP + (b)))
61 49
62#define IRQ_MCT_LTIMER IRQ_PPI(12) 50#define IRQ_MCT_LTIMER IRQ_PPI(12)
63 51
64#ifdef EXYNOS5 
65#include <arm/cortex/gtmr_intr.h> 
66#endif 
67 
68#endif /* _ARM_SAMSUNG_EXYNOS_INTR_H_ */ 52#endif /* _ARM_SAMSUNG_EXYNOS_INTR_H_ */
69 53

File Added: src/sys/arch/arm/samsung/exynos_platform.c
/* $NetBSD: exynos_platform.c,v 1.1 2017/06/10 15:13:18 jmcneill Exp $ */

/*-
 * Copyright (c) 2017 Jared D. McNeill <jmcneill@invisible.ca>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#include "opt_exynos.h"
#include "opt_multiprocessor.h"
#include "opt_fdt_arm.h"

#include "ukbd.h"

#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: exynos_platform.c,v 1.1 2017/06/10 15:13:18 jmcneill Exp $");

#include <sys/param.h>
#include <sys/bus.h>
#include <sys/cpu.h>
#include <sys/device.h>
#include <sys/termios.h>

#include <dev/fdt/fdtvar.h>

#include <uvm/uvm_extern.h>

#include <machine/bootconfig.h>
#include <arm/cpufunc.h>

#include <arm/samsung/exynos_reg.h>
#include <arm/samsung/exynos_var.h>

#include <arm/cortex/gtmr_var.h>

#include <arm/fdt/arm_fdtvar.h>

#define	EXYNOS_CORE_VBASE	0xf0000000

#define	DEVMAP_ALIGN(a)	((a) & ~L1_S_OFFSET)
#define	DEVMAP_SIZE(s)	roundup2((s), L1_S_SIZE)
#define	DEVMAP_ENTRY(va, pa, sz)			\
	{						\
		.pd_va = DEVMAP_ALIGN(va),		\
		.pd_pa = DEVMAP_ALIGN(pa),		\
		.pd_size = DEVMAP_SIZE(sz),		\
		.pd_prot = VM_PROT_READ|VM_PROT_WRITE,	\
		.pd_cache = PTE_NOCACHE			\
	}
#define	DEVMAP_ENTRY_END	{ 0 }

static const struct pmap_devmap *
exynos_platform_devmap(void)
{
	static const struct pmap_devmap devmap[] = {
		DEVMAP_ENTRY(EXYNOS_CORE_VBASE,
			     EXYNOS_CORE_PBASE,
			     EXYNOS_CORE_SIZE),
		DEVMAP_ENTRY_END
	};	

	return devmap;
}

static void
exynos_platform_bootstrap(void)
{
	exynos_bootstrap(EXYNOS_CORE_PBASE, 0 /* XXX */);
}

static void
exynos_platform_init_attach_args(struct fdt_attach_args *faa)
{
	extern struct bus_space armv7_generic_bs_tag;
	extern struct bus_space armv7_generic_a4x_bs_tag;
	extern struct arm32_bus_dma_tag armv7_generic_dma_tag;

	faa->faa_bst = &armv7_generic_bs_tag;
	faa->faa_a4x_bst = &armv7_generic_a4x_bs_tag;
	faa->faa_dmat = &armv7_generic_dma_tag;
}

static void
exynos_platform_early_putchar(char c)
{
}

static void
exynos_platform_device_register(device_t self, void *aux)
{
	exynos_device_register(self, aux);
}

static void
exynos_platform_reset(void)
{
	printf("%s: not implemented\n", __func__);
}

static void
exynos_platform_delay(u_int us)
{
	gtmr_delay(us);
}

static u_int
exynos_platform_uart_freq(void)
{
	return EXYNOS_UART_FREQ;
}

static const struct arm_platform exynos5_platform = {
	.devmap = exynos_platform_devmap,
	.bootstrap = exynos_platform_bootstrap,
	.init_attach_args = exynos_platform_init_attach_args,
	.early_putchar = exynos_platform_early_putchar,
	.device_register = exynos_platform_device_register,
	.reset = exynos_platform_reset,
	.delay = exynos_platform_delay,
	.uart_freq = exynos_platform_uart_freq,
};

ARM_PLATFORM(exynos5, "samsung,exynos5", &exynos5_platform);

cvs diff -r1.13 -r1.14 src/sys/arch/arm/samsung/exynos_reg.h (switch to unified diff)

--- src/sys/arch/arm/samsung/exynos_reg.h 2014/09/30 14:20:55 1.13
+++ src/sys/arch/arm/samsung/exynos_reg.h 2017/06/10 15:13:18 1.14
@@ -1,201 +1,201 @@ @@ -1,201 +1,201 @@
1/* $NetBSD: exynos_reg.h,v 1.13 2014/09/30 14:20:55 reinoud Exp $ */ 1/* $NetBSD: exynos_reg.h,v 1.14 2017/06/10 15:13:18 jmcneill Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 4 * Copyright (c) 2014 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Reinoud Zandijk. 8 * by Reinoud Zandijk.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright 15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the 16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution. 17 * documentation and/or other materials provided with the distribution.
18 * 18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE. 29 * POSSIBILITY OF SUCH DAMAGE.
30 */ 30 */
31 31
32#ifndef _ARM_SAMSUNG_EXYNOS_REG_H_ 32#ifndef _ARM_SAMSUNG_EXYNOS_REG_H_
33#define _ARM_SAMSUNG_EXYNOS_REG_H_ 33#define _ARM_SAMSUNG_EXYNOS_REG_H_
34 34
35/* 35/*
36 * 36 *
37 * The exynos can boot from its iROM or from an external Nand memory. Since 37 * The exynos can boot from its iROM or from an external Nand memory. Since
38 * these are normally hardly used they are excluded from the normal register 38 * these are normally hardly used they are excluded from the normal register
39 * space here. 39 * space here.
40 * 40 *
41 * XXX What about the audio subsystem region. Where are the docs? 41 * XXX What about the audio subsystem region. Where are the docs?
42 * 42 *
43 * EXYNOS_CORE_PBASE points to the main SFR region. 43 * EXYNOS_CORE_PBASE points to the main SFR region.
44 * 44 *
45 * Notes: 45 * Notes:
46 * 46 *
47 * SFR Special Function Register 47 * SFR Special Function Register
48 * ISP In-System Programming, like a JTAG 48 * ISP In-System Programming, like a JTAG
49 * ACP Accelerator Coherency Port 49 * ACP Accelerator Coherency Port
50 * SSS Security Sub System 50 * SSS Security Sub System
51 * GIC Generic Interurrupt Controller 51 * GIC Generic Interurrupt Controller
52 * PMU Power Management Unit 52 * PMU Power Management Unit
53 * DMC 2D Graphics engine 53 * DMC 2D Graphics engine
54 * LEFTBUS Data bus / Peripheral bus 54 * LEFTBUS Data bus / Peripheral bus
55 * RIGHTBUS ,, 55 * RIGHTBUS ,,
56 * G3D 3D Graphics engine 56 * G3D 3D Graphics engine
57 * MFC Multi-Format Codec 57 * MFC Multi-Format Codec
58 * LCD0 LCD display 58 * LCD0 LCD display
59 * MCT Multi Core Timer 59 * MCT Multi Core Timer
60 * CMU Clock Management Unit 60 * CMU Clock Management Unit
61 * TMU Thermal Management Unit 61 * TMU Thermal Management Unit
62 * PPMU Pin Parametric Measurement Unit (?) 62 * PPMU Pin Parametric Measurement Unit (?)
63 * MMU Memory Management Unit 63 * MMU Memory Management Unit
64 * MCTimer ? 64 * MCTimer ?
65 * WDT Watch Dog Timer 65 * WDT Watch Dog Timer
66 * RTC Real Time Clock 66 * RTC Real Time Clock
67 * KEYIF Keypad interface 67 * KEYIF Keypad interface
68 * SECKEY ? 68 * SECKEY ?
69 * TZPC TrustZone Protection Controller 69 * TZPC TrustZone Protection Controller
70 * UART Universal asynchronous receiver/transmitter 70 * UART Universal asynchronous receiver/transmitter
71 * I2C Inter IC Connect 71 * I2C Inter IC Connect
72 * SPI Serial Peripheral Interface Bus 72 * SPI Serial Peripheral Interface Bus
73 * I2S Inter-IC Sound, Integrated Interchip Sound, or IIS 73 * I2S Inter-IC Sound, Integrated Interchip Sound, or IIS
74 * PCM Pulse-code modulation, audio stream at set fixed rate 74 * PCM Pulse-code modulation, audio stream at set fixed rate
75 * SPDIF Sony/Philips Digital Interface Format 75 * SPDIF Sony/Philips Digital Interface Format
76 * Slimbus Serial Low-power Inter-chip Media Bus 76 * Slimbus Serial Low-power Inter-chip Media Bus
77 * SMMU System mmu. No idea as how its programmed (or not) 77 * SMMU System mmu. No idea as how its programmed (or not)
78 * PERI-L UART, I2C, SPI, I2S, PCM, SPDIF, PWM, I2CHDMI, Slimbus 78 * PERI-L UART, I2C, SPI, I2S, PCM, SPDIF, PWM, I2CHDMI, Slimbus
79 * PERI-R CHIPID, SYSREG, PMU/CMU/TMU Bus I/F, MCTimer, WDT, RTC, KEYIF, 79 * PERI-R CHIPID, SYSREG, PMU/CMU/TMU Bus I/F, MCTimer, WDT, RTC, KEYIF,
80 * SECKEY, TZPC 80 * SECKEY, TZPC
81 */ 81 */
82 82
83/* 83/*
84 * Common to Exynos4 and Exynos 5 84 * Common to Exynos4 and Exynos 5
85 * */ 85 * */
86#define EXYNOS_CORE_PBASE 0x10000000 /* SFR */ 86#define EXYNOS_CORE_PBASE 0x10000000 /* SFR */
87#define EXYNOS_CORE_SIZE 0x10000000 87#define EXYNOS_CORE_SIZE 0x10000000
88 88
89 89
90#define EXYNOS_CHIPID_OFFSET 0x00000000 90#define EXYNOS_CHIPID_OFFSET 0x00000000
91#define EXYNOS_PROD_ID_OFFSET (EXYNOS_CHIPID_OFFSET + 0) 91#define EXYNOS_PROD_ID_OFFSET (EXYNOS_CHIPID_OFFSET + 0)
92#define EXYNOS_PACKAGE_ID_OFFSET (EXYNOS_CHIPID_OFFSET + 4) 92#define EXYNOS_PACKAGE_ID_OFFSET (EXYNOS_CHIPID_OFFSET + 4)
93 93
94#define EXYNOS_PACKAGE_ID_2_GIG 0x06030058 94#define EXYNOS_PACKAGE_ID_2_GIG 0x06030058
95 95
96/* standard block size for offsets defined below */ 96/* standard block size for offsets defined below */
97#define EXYNOS_BLOCK_SIZE 0x00010000 97#define EXYNOS_BLOCK_SIZE 0x00010000
98 98
99 99
100#if defined(EXYNOS5) 100#if defined(SOC_EXYNOS5)
101#include <arm/samsung/exynos5_reg.h> 101#include <arm/samsung/exynos5_reg.h>
102#endif 102#endif
103#if defined(EXYNOS4) 103#if defined(SOC_EXYNOS4)
104#include <arm/samsung/exynos4_reg.h> 104#include <arm/samsung/exynos4_reg.h>
105#endif 105#endif
106 106
107 107
108/* standard frequency settings */ 108/* standard frequency settings */
109#define EXYNOS_ACLK_REF_FREQ (200*1000*1000) /* 200 Mhz */ 109#define EXYNOS_ACLK_REF_FREQ (200*1000*1000) /* 200 Mhz */
110#define EXYNOS_UART_FREQ (109*1000*1000) /* should be EXYNOS_ACLK_REF_FREQ! */ 110#define EXYNOS_UART_FREQ (109*1000*1000) /* should be EXYNOS_ACLK_REF_FREQ! */
111 111
112#define EXYNOS_F_IN_FREQ (24*1000*1000) /* 24 Mhz */ 112#define EXYNOS_F_IN_FREQ (24*1000*1000) /* 24 Mhz */
113#define EXYNOS_USB_FREQ EXYNOS_F_IN_FREQ/* 24 Mhz */ 113#define EXYNOS_USB_FREQ EXYNOS_F_IN_FREQ/* 24 Mhz */
114 114
115 115
116/* PLLs */ 116/* PLLs */
117#define PLL_LOCK_OFFSET 0x000 117#define PLL_LOCK_OFFSET 0x000
118#define PLL_CON0_OFFSET 0x100 118#define PLL_CON0_OFFSET 0x100
119#define PLL_CON1_OFFSET 0x104 119#define PLL_CON1_OFFSET 0x104
120 120
121#define PLL_CON0_ENABLE __BIT(31) 121#define PLL_CON0_ENABLE __BIT(31)
122#define PLL_CON0_LOCKED __BIT(29) /* has the PLL locked on */ 122#define PLL_CON0_LOCKED __BIT(29) /* has the PLL locked on */
123#define PLL_CON0_M __BITS(16,25) /* PLL M divide value */ 123#define PLL_CON0_M __BITS(16,25) /* PLL M divide value */
124#define PLL_CON0_P __BITS( 8,13) /* PLL P divide value */ 124#define PLL_CON0_P __BITS( 8,13) /* PLL P divide value */
125#define PLL_CON0_S __BITS( 0, 2) /* PLL S divide value */ 125#define PLL_CON0_S __BITS( 0, 2) /* PLL S divide value */
126 126
127#define PLL_PMS2FREQ(F, M, P, S) (((M)*(F))/((P)*(1<<(S)))) 127#define PLL_PMS2FREQ(F, M, P, S) (((M)*(F))/((P)*(1<<(S))))
128#define PLL_FREQ(f, v) PLL_PMS2FREQ( \ 128#define PLL_FREQ(f, v) PLL_PMS2FREQ( \
129 (f),\ 129 (f),\
130 __SHIFTOUT((v), PLL_CON0_M),\ 130 __SHIFTOUT((v), PLL_CON0_M),\
131 __SHIFTOUT((v), PLL_CON0_P),\ 131 __SHIFTOUT((v), PLL_CON0_P),\
132 __SHIFTOUT((v), PLL_CON0_S)) 132 __SHIFTOUT((v), PLL_CON0_S))
133 133
134 134
135/* Watchdog register definitions */ 135/* Watchdog register definitions */
136#define EXYNOS_WDT_WTCON 0x0000 136#define EXYNOS_WDT_WTCON 0x0000
137#define WTCON_PRESCALER __BITS(15,8) 137#define WTCON_PRESCALER __BITS(15,8)
138#define WTCON_ENABLE __BIT(5) 138#define WTCON_ENABLE __BIT(5)
139#define WTCON_CLOCK_SELECT __BITS(4,3) 139#define WTCON_CLOCK_SELECT __BITS(4,3)
140#define WTCON_CLOCK_SELECT_16 __SHIFTIN(0, WTCON_CLOCK_SELECT) 140#define WTCON_CLOCK_SELECT_16 __SHIFTIN(0, WTCON_CLOCK_SELECT)
141#define WTCON_CLOCK_SELECT_32 __SHIFTIN(1, WTCON_CLOCK_SELECT) 141#define WTCON_CLOCK_SELECT_32 __SHIFTIN(1, WTCON_CLOCK_SELECT)
142#define WTCON_CLOCK_SELECT_64 __SHIFTIN(2, WTCON_CLOCK_SELECT) 142#define WTCON_CLOCK_SELECT_64 __SHIFTIN(2, WTCON_CLOCK_SELECT)
143#define WTCON_CLOCK_SELECT_128 __SHIFTIN(3, WTCON_CLOCK_SELECT) 143#define WTCON_CLOCK_SELECT_128 __SHIFTIN(3, WTCON_CLOCK_SELECT)
144#define WTCON_INT_ENABLE __BIT(2) 144#define WTCON_INT_ENABLE __BIT(2)
145#define WTCON_RESET_ENABLE __BIT(0) 145#define WTCON_RESET_ENABLE __BIT(0)
146#define EXYNOS_WDT_WTDAT 0x0004 146#define EXYNOS_WDT_WTDAT 0x0004
147#define WTDAT_RELOAD __BITS(15,0) 147#define WTDAT_RELOAD __BITS(15,0)
148#define EXYNOS_WDT_WTCNT 0x0008 148#define EXYNOS_WDT_WTCNT 0x0008
149#define WTCNT_COUNT __BITS(15,0) 149#define WTCNT_COUNT __BITS(15,0)
150#define EXYNOS_WDT_WTCLRINT 0x000C 150#define EXYNOS_WDT_WTCLRINT 0x000C
151 151
152 152
153/* GPIO register definitions */ 153/* GPIO register definitions */
154#define EXYNOS_GPIO_GRP_SIZE 0x20 154#define EXYNOS_GPIO_GRP_SIZE 0x20
155#define EXYNOS_GPIO_CON 0x00 155#define EXYNOS_GPIO_CON 0x00
156#define EXYNOS_GPIO_DAT 0x04 156#define EXYNOS_GPIO_DAT 0x04
157#define EXYNOS_GPIO_PUD 0x08 157#define EXYNOS_GPIO_PUD 0x08
158#define EXYNOS_GPIO_DRV 0x0C 158#define EXYNOS_GPIO_DRV 0x0C
159#define EXYNOS_GPIO_CONPWD 0x10 159#define EXYNOS_GPIO_CONPWD 0x10
160#define EXYNOS_GPIO_PUDPWD 0x14 160#define EXYNOS_GPIO_PUDPWD 0x14
161/* rest of space is not used */ 161/* rest of space is not used */
162 162
163#define EXYNOS_GPIO_FUNC_INPUT 0x0 163#define EXYNOS_GPIO_FUNC_INPUT 0x0
164#define EXYNOS_GPIO_FUNC_OUTPUT 0x1 164#define EXYNOS_GPIO_FUNC_OUTPUT 0x1
165/* intermediate values are devices, definitions dependent on pin */ 165/* intermediate values are devices, definitions dependent on pin */
166#define EXYNOS_GPIO_FUNC_EXTINT 0xF 166#define EXYNOS_GPIO_FUNC_EXTINT 0xF
167 167
168#define EXYNOS_GPIO_PIN_FLOAT 0 168#define EXYNOS_GPIO_PIN_FLOAT 0
169#define EXYNOS_GPIO_PIN_PULL_DOWN 1 169#define EXYNOS_GPIO_PIN_PULL_DOWN 1
170#define EXYNOS_GPIO_PIN_PULL_UP 3 170#define EXYNOS_GPIO_PIN_PULL_UP 3
171 171
172 172
173/* used PMU registers */ 173/* used PMU registers */
174/* Exynos 4210 or Exynos 5 */ 174/* Exynos 4210 or Exynos 5 */
175#define EXYNOS_PMU_USBDEV_PHY_CTRL 0x704 175#define EXYNOS_PMU_USBDEV_PHY_CTRL 0x704
176#define EXYNOS_PMU_USBHOST_PHY_CTRL 0x708 176#define EXYNOS_PMU_USBHOST_PHY_CTRL 0x708
177/* Exynos 4x12 */ 177/* Exynos 4x12 */
178#define EXYNOS_PMU_USB_PHY_CTRL 0x704 178#define EXYNOS_PMU_USB_PHY_CTRL 0x704
179#define EXYNOS_PMU_USB_HSIC_1_PHY_CTRL 0x708 179#define EXYNOS_PMU_USB_HSIC_1_PHY_CTRL 0x708
180#define EXYNOS_PMU_USB_HSIC_2_PHY_CTRL 0x70C 180#define EXYNOS_PMU_USB_HSIC_2_PHY_CTRL 0x70C
181 181
182#define PMU_PHY_ENABLE (1 << 0) 182#define PMU_PHY_ENABLE (1 << 0)
183#define PMU_PHY_DISABLE (0) 183#define PMU_PHY_DISABLE (0)
184 184
185#define EXYNOS_PMU_DEBUG_CLKOUT 0x0A00 185#define EXYNOS_PMU_DEBUG_CLKOUT 0x0A00
186 186
187/* used SYSREG registers */ 187/* used SYSREG registers */
188#define EXYNOS5_SYSREG_USB20_PHY_TYPE 0x230 188#define EXYNOS5_SYSREG_USB20_PHY_TYPE 0x230
189#define USB20_PHY_HOST_LINK_EN (1 << 0) 189#define USB20_PHY_HOST_LINK_EN (1 << 0)
190 190
191 191
192/* Generic USB registers/constants */ 192/* Generic USB registers/constants */
193#define FSEL_CLKSEL_50M 7 193#define FSEL_CLKSEL_50M 7
194#define FSEL_CLKSEL_24M 5 194#define FSEL_CLKSEL_24M 5
195#define FSEL_CLKSEL_20M 4 195#define FSEL_CLKSEL_20M 4
196#define FSEL_CLKSEL_19200K 3 196#define FSEL_CLKSEL_19200K 3
197#define FSEL_CLKSEL_12M 2 197#define FSEL_CLKSEL_12M 2
198#define FSEL_CLKSEL_10M 1 198#define FSEL_CLKSEL_10M 1
199#define FSEL_CLKSEL_9600K 0 199#define FSEL_CLKSEL_9600K 0
200 200
201#endif /* _ARM_SAMSUNG_EXYNOS_REG_H_ */ 201#endif /* _ARM_SAMSUNG_EXYNOS_REG_H_ */

cvs diff -r1.31 -r1.32 src/sys/arch/arm/samsung/exynos_soc.c (switch to unified diff)

--- src/sys/arch/arm/samsung/exynos_soc.c 2015/12/21 04:58:50 1.31
+++ src/sys/arch/arm/samsung/exynos_soc.c 2017/06/10 15:13:18 1.32
@@ -1,926 +1,930 @@ @@ -1,926 +1,930 @@
1/* $NetBSD: exynos_soc.c,v 1.31 2015/12/21 04:58:50 marty Exp $ */ 1/* $NetBSD: exynos_soc.c,v 1.32 2017/06/10 15:13:18 jmcneill Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 4 * Copyright (c) 2014 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Reinoud Zandijk. 8 * by Reinoud Zandijk.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright 15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the 16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution. 17 * documentation and/or other materials provided with the distribution.
18 * 18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE. 29 * POSSIBILITY OF SUCH DAMAGE.
30 */ 30 */
31 31
32#include "opt_exynos.h" 32#include "opt_exynos.h"
33 33
34#define _ARM32_BUS_DMA_PRIVATE 
35 
36#include <sys/cdefs.h> 34#include <sys/cdefs.h>
37__KERNEL_RCSID(1, "$NetBSD: exynos_soc.c,v 1.31 2015/12/21 04:58:50 marty Exp $"); 35__KERNEL_RCSID(1, "$NetBSD: exynos_soc.c,v 1.32 2017/06/10 15:13:18 jmcneill Exp $");
38 36
39#include <sys/param.h> 37#include <sys/param.h>
40#include <sys/bus.h> 38#include <sys/bus.h>
41#include <sys/cpu.h> 39#include <sys/cpu.h>
42#include <sys/device.h> 40#include <sys/device.h>
43 41
44#include <prop/proplib.h> 42#include <prop/proplib.h>
45 43
46#include <net/if.h> 44#include <net/if.h>
47#include <net/if_ether.h> 45#include <net/if_ether.h>
48 46
49#include <arm/locore.h> 47#include <arm/locore.h>
50 48
51#include <arm/mainbus/mainbus.h> 49#include <arm/mainbus/mainbus.h>
52#include <arm/cortex/mpcore_var.h> 50#include <arm/cortex/mpcore_var.h>
53 51
54#include <arm/samsung/exynos_reg.h> 52#include <arm/samsung/exynos_reg.h>
55#include <arm/samsung/exynos_var.h> 53#include <arm/samsung/exynos_var.h>
56#include <arm/samsung/mct_reg.h> 54#include <arm/samsung/mct_reg.h>
57#include <arm/samsung/smc.h> 55#include <arm/samsung/smc.h>
58 56
59#include <arm/cortex/pl310_var.h> 57#include <arm/cortex/pl310_var.h>
60#include <arm/cortex/pl310_reg.h> 58#include <arm/cortex/pl310_reg.h>
61 59
62/* XXXNH */ 60/* XXXNH */
63#include <evbarm/exynos/platform.h> 61#include <evbarm/exynos/platform.h>
64 62
65 63
66/* these variables are retrieved in start.S and stored in .data */ 64/* these variables are retrieved in start.S and stored in .data */
67uint32_t exynos_soc_id = 0; 65uint32_t exynos_soc_id = 0;
68uint32_t exynos_pop_id = 0; 66uint32_t exynos_pop_id = 0;
69 67
70/* cpu frequencies */ 68/* cpu frequencies */
71struct cpu_freq { 69struct cpu_freq {
72 uint64_t freq; 70 uint64_t freq;
73 int P; 71 int P;
74 int M; 72 int M;
75 int S; 73 int S;
76}; 74};
77 75
78 76
79#ifdef EXYNOS4 77#ifdef SOC_EXYNOS4
80const struct cpu_freq cpu_freq_settings_exynos4[] = { 78const struct cpu_freq cpu_freq_settings_exynos4[] = {
81 { 200, 3, 100, 2}, 79 { 200, 3, 100, 2},
82 { 300, 4, 200, 2}, 80 { 300, 4, 200, 2},
83 { 400, 3, 100, 1}, 81 { 400, 3, 100, 1},
84 { 500, 3, 125, 1}, 82 { 500, 3, 125, 1},
85 { 600, 4, 200, 1}, 83 { 600, 4, 200, 1},
86 { 700, 3, 175, 1}, 84 { 700, 3, 175, 1},
87 { 800, 3, 100, 0}, 85 { 800, 3, 100, 0},
88 { 900, 4, 150, 0}, 86 { 900, 4, 150, 0},
89 {1000, 3, 125, 0}, 87 {1000, 3, 125, 0},
90 {1100, 6, 275, 0}, 88 {1100, 6, 275, 0},
91 {1200, 4, 200, 0}, 89 {1200, 4, 200, 0},
92 {1300, 6, 325, 0}, 90 {1300, 6, 325, 0},
93 {1400, 3, 175, 0}, 91 {1400, 3, 175, 0},
94 {1600, 3, 200, 0}, 92 {1600, 3, 200, 0},
95// {1704, 3, 213, 0}, 93// {1704, 3, 213, 0},
96// {1800, 4, 300, 0}, 94// {1800, 4, 300, 0},
97// {1920, 3, 240, 0}, 95// {1920, 3, 240, 0},
98// {2000, 3, 250, 0}, 96// {2000, 3, 250, 0},
99}; 97};
100#endif 98#endif
101 99
102 100
103#ifdef EXYNOS5 101#ifdef SOC_EXYNOS5
104#define EXYNOS5_DEFAULT_ENTRY 7 102#define EXYNOS5_DEFAULT_ENTRY 7
105const struct cpu_freq cpu_freq_settings_exynos5[] = { 103const struct cpu_freq cpu_freq_settings_exynos5[] = {
106 { 200, 3, 100, 2}, 104 { 200, 3, 100, 2},
107 { 333, 4, 222, 2}, 105 { 333, 4, 222, 2},
108 { 400, 3, 100, 1}, 106 { 400, 3, 100, 1},
109 { 533, 12, 533, 1}, 107 { 533, 12, 533, 1},
110 { 600, 4, 200, 1}, 108 { 600, 4, 200, 1},
111 { 667, 7, 389, 1}, 109 { 667, 7, 389, 1},
112 { 800, 3, 100, 0}, 110 { 800, 3, 100, 0},
113 { 900, 4, 150, 0}, 111 { 900, 4, 150, 0},
114 {1000, 3, 125, 0}, 112 {1000, 3, 125, 0},
115 {1066, 12, 533, 0}, 113 {1066, 12, 533, 0},
116 {1200, 3, 150, 0}, 114 {1200, 3, 150, 0},
117 {1400, 3, 175, 0}, 115 {1400, 3, 175, 0},
118 {1600, 3, 200, 0}, 116 {1600, 3, 200, 0},
119}; 117};
120#endif 118#endif
121 119
122static struct cpu_freq const *cpu_freq_settings = NULL; 120static struct cpu_freq const *cpu_freq_settings = NULL;
123static int ncpu_freq_settings = 0; 121static int ncpu_freq_settings = 0;
124 122
125static int cpu_freq_target = 0; 123static int cpu_freq_target = 0;
126#define NFRQS 18 124#define NFRQS 18
127static char sysctl_cpu_freqs_txt[NFRQS*5]; 125static char sysctl_cpu_freqs_txt[NFRQS*5];
128 126
129bus_space_handle_t exynos_core_bsh; 127bus_space_handle_t exynos_core_bsh;
130bus_space_handle_t exynos_audiocore_bsh; 128bus_space_handle_t exynos_audiocore_bsh;
131 129
132bus_space_handle_t exynos_wdt_bsh; 130bus_space_handle_t exynos_wdt_bsh;
133bus_space_handle_t exynos_pmu_bsh; 131bus_space_handle_t exynos_pmu_bsh;
134bus_space_handle_t exynos_cmu_bsh; 132bus_space_handle_t exynos_cmu_bsh;
135bus_space_handle_t exynos_cmu_apll_bsh; 133bus_space_handle_t exynos_cmu_apll_bsh;
136bus_space_handle_t exynos_sysreg_bsh; 134bus_space_handle_t exynos_sysreg_bsh;
137 135
138 136
139static int sysctl_cpufreq_target(SYSCTLFN_ARGS); 137static int sysctl_cpufreq_target(SYSCTLFN_ARGS);
140static int sysctl_cpufreq_current(SYSCTLFN_ARGS); 138static int sysctl_cpufreq_current(SYSCTLFN_ARGS);
141 139
142/* 140/*
143 * the early serial console 141 * the early serial console
144 */ 142 */
145#ifdef EXYNOS_CONSOLE_EARLY 143#ifdef EXYNOS_CONSOLE_EARLY
146 144
147#include "opt_sscom.h" 145#include "opt_sscom.h"
148#include <arm/samsung/sscom_reg.h> 146#include <arm/samsung/sscom_reg.h>
149#include <arm/samsung/sscom_var.h> 147#include <arm/samsung/sscom_var.h>
150#include <dev/cons.h> 148#include <dev/cons.h>
151 149
152static volatile uint8_t *uart_base; 150static volatile uint8_t *uart_base;
153 151
154#define CON_REG(a) (*((volatile uint32_t *)(uart_base + (a)))) 152#define CON_REG(a) (*((volatile uint32_t *)(uart_base + (a))))
155 153
156static int 154static int
157exynos_cngetc(dev_t dv) 155exynos_cngetc(dev_t dv)
158{ 156{
159 if ((CON_REG(SSCOM_UTRSTAT) & UTRSTAT_RXREADY) == 0) 157 if ((CON_REG(SSCOM_UTRSTAT) & UTRSTAT_RXREADY) == 0)
160 return -1; 158 return -1;
161 159
162 return CON_REG(SSCOM_URXH); 160 return CON_REG(SSCOM_URXH);
163} 161}
164 162
165static void 163static void
166exynos_cnputc(dev_t dv, int c) 164exynos_cnputc(dev_t dv, int c)
167{ 165{
168 int timo = 150000; 166 int timo = 150000;
169 167
170 while ((CON_REG(SSCOM_UFSTAT) & UFSTAT_TXFULL) && --timo > 0); 168 while ((CON_REG(SSCOM_UFSTAT) & UFSTAT_TXFULL) && --timo > 0);
171 169
172 CON_REG(SSCOM_UTXH) = c & 0xff; 170 CON_REG(SSCOM_UTXH) = c & 0xff;
173} 171}
174 172
175static struct consdev exynos_earlycons = { 173static struct consdev exynos_earlycons = {
176 .cn_putc = exynos_cnputc, 174 .cn_putc = exynos_cnputc,
177 .cn_getc = exynos_cngetc, 175 .cn_getc = exynos_cngetc,
178 .cn_pollc = nullcnpollc, 176 .cn_pollc = nullcnpollc,
179}; 177};
180#endif /* EXYNOS_CONSOLE_EARLY */ 178#endif /* EXYNOS_CONSOLE_EARLY */
181 179
182 180
183#ifdef ARM_TRUSTZONE_FIRMWARE 181#ifdef ARM_TRUSTZONE_FIRMWARE
184int 182int
185exynos_do_idle(void) 183exynos_do_idle(void)
186{ 184{
187 exynos_smc(SMC_CMD_SLEEP, 0, 0, 0); 185 exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
188 186
189 return 0; 187 return 0;
190} 188}
191 189
192 190
193int 191int
194exynos_set_cpu_boot_addr(int cpu, vaddr_t boot_addr) 192exynos_set_cpu_boot_addr(int cpu, vaddr_t boot_addr)
195{ 193{
196 /* XXX we need to map in iRAM space for this XXX */ 194 /* XXX we need to map in iRAM space for this XXX */
197 return 0; 195 return 0;
198} 196}
199 197
200 198
201int 199int
202exynos_cpu_boot(int cpu) 200exynos_cpu_boot(int cpu)
203{ 201{
204 exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0); 202 exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
205 203
206 return 0; 204 return 0;
207} 205}
208 206
209 207
210#ifdef EXYNOS4 208#ifdef SOC_EXYNOS4
211/* 209/*
212 * The latency values used below are `magic' and probably chosen empirically. 210 * The latency values used below are `magic' and probably chosen empirically.
213 * For the 4210 variant the data latency is lower, a 0x110. This is currently 211 * For the 4210 variant the data latency is lower, a 0x110. This is currently
214 * not enforced. 212 * not enforced.
215 * 213 *
216 * The prefetch values are also different for the revision 0 of the 214 * The prefetch values are also different for the revision 0 of the
217 * Exynos4412, but why? 215 * Exynos4412, but why?
218 */ 216 */
219 217
220int 218int
221exynos4_l2cc_init(void) 219exynos4_l2cc_init(void)
222{ 220{
223 const uint32_t tag_latency = 0x110; 221 const uint32_t tag_latency = 0x110;
224 const uint32_t data_latency = IS_EXYNOS4410_P() ? 0x110 : 0x120; 222 const uint32_t data_latency = IS_EXYNOS4410_P() ? 0x110 : 0x120;
225 const uint32_t prefetch4412 = /* 0111 0001 0000 0000 0000 0000 0000 0111 */ 223 const uint32_t prefetch4412 = /* 0111 0001 0000 0000 0000 0000 0000 0111 */
226 PREFETCHCTL_DBLLINEF_EN | 224 PREFETCHCTL_DBLLINEF_EN |
227 PREFETCHCTL_INSTRPREF_EN | 225 PREFETCHCTL_INSTRPREF_EN |
228 PREFETCHCTL_DATAPREF_EN | 226 PREFETCHCTL_DATAPREF_EN |
229 PREFETCHCTL_PREF_DROP_EN | 227 PREFETCHCTL_PREF_DROP_EN |
230 PREFETCHCTL_PREFETCH_OFFSET_7; 228 PREFETCHCTL_PREFETCH_OFFSET_7;
231 const uint32_t prefetch4412_r0 = /* 0011 0000 0000 0000 0000 0000 0000 0111 */ 229 const uint32_t prefetch4412_r0 = /* 0011 0000 0000 0000 0000 0000 0000 0111 */
232 PREFETCHCTL_INSTRPREF_EN | 230 PREFETCHCTL_INSTRPREF_EN |
233 PREFETCHCTL_DATAPREF_EN | 231 PREFETCHCTL_DATAPREF_EN |
234 PREFETCHCTL_PREFETCH_OFFSET_7; 232 PREFETCHCTL_PREFETCH_OFFSET_7;
235 const uint32_t aux_val = /* 0111 1100 0100 0111 0000 0000 0000 0001 */ 233 const uint32_t aux_val = /* 0111 1100 0100 0111 0000 0000 0000 0001 */
236 AUXCTL_EARLY_BRESP_EN | 234 AUXCTL_EARLY_BRESP_EN |
237 AUXCTL_I_PREFETCH | 235 AUXCTL_I_PREFETCH |
238 AUXCTL_D_PREFETCH | 236 AUXCTL_D_PREFETCH |
239 AUXCTL_NS_INT_ACC_CTL | 237 AUXCTL_NS_INT_ACC_CTL |
240 AUXCTL_NS_INT_LOCK_EN | 238 AUXCTL_NS_INT_LOCK_EN |
241 AUXCTL_SHARED_ATT_OVR | 239 AUXCTL_SHARED_ATT_OVR |
242 AUXCTL_WAY_SIZE_RSVD7 << 16 | /* why rsvd7 ??? */ 240 AUXCTL_WAY_SIZE_RSVD7 << 16 | /* why rsvd7 ??? */
243 AUXCTL_FULL_LINE_WR0; 241 AUXCTL_FULL_LINE_WR0;
244 const uint32_t aux_keepmask = /* 1100 0010 0000 0000 1111 1111 1111 1111 */ 242 const uint32_t aux_keepmask = /* 1100 0010 0000 0000 1111 1111 1111 1111 */
245 AUXCTL_RSVD31 | 243 AUXCTL_RSVD31 |
246 AUXCTL_EARLY_BRESP_EN | 244 AUXCTL_EARLY_BRESP_EN |
247 AUXCTL_CACHE_REPL_RR | 245 AUXCTL_CACHE_REPL_RR |
248 246
249 AUXCTL_SH_ATTR_INV_ENA| 247 AUXCTL_SH_ATTR_INV_ENA|
250 AUXCTL_EXCL_CACHE_CFG | 248 AUXCTL_EXCL_CACHE_CFG |
251 AUXCTL_ST_BUF_DEV_LIM_EN | 249 AUXCTL_ST_BUF_DEV_LIM_EN |
252 AUXCTL_HIPRO_SO_DEV_EN | 250 AUXCTL_HIPRO_SO_DEV_EN |
253 AUXCTL_FULL_LINE_WR0 | 251 AUXCTL_FULL_LINE_WR0 |
254 0xffff; 252 0xffff;
255 uint32_t prefetch; 253 uint32_t prefetch;
256 254
257 /* check the bitmaps are the same as the linux implementation uses */ 255 /* check the bitmaps are the same as the linux implementation uses */
258 KASSERT(prefetch4412 == 0x71000007); 256 KASSERT(prefetch4412 == 0x71000007);
259 KASSERT(prefetch4412_r0 == 0x30000007); 257 KASSERT(prefetch4412_r0 == 0x30000007);
260 KASSERT(aux_val == 0x7C470001); 258 KASSERT(aux_val == 0x7C470001);
261 KASSERT(aux_keepmask == 0xC200FFFF); 259 KASSERT(aux_keepmask == 0xC200FFFF);
262 260
263 if (IS_EXYNOS4412_R0_P()) 261 if (IS_EXYNOS4412_R0_P())
264 prefetch = prefetch4412_r0; 262 prefetch = prefetch4412_r0;
265 else 263 else
266 prefetch = prefetch4412; /* newer than >= r1_0 */ 264 prefetch = prefetch4412; /* newer than >= r1_0 */
267 ; 265 ;
268 266
269 exynos_smc(SMC_CMD_L2X0SETUP1, tag_latency, data_latency, prefetch); 267 exynos_smc(SMC_CMD_L2X0SETUP1, tag_latency, data_latency, prefetch);
270 exynos_smc(SMC_CMD_L2X0SETUP2, 268 exynos_smc(SMC_CMD_L2X0SETUP2,
271 POWERCTL_DYNCLKGATE | POWERCTL_STANDBY, 269 POWERCTL_DYNCLKGATE | POWERCTL_STANDBY,
272 aux_val, aux_keepmask); 270 aux_val, aux_keepmask);
273 exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0); 271 exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
274 exynos_smc(SMC_CMD_L2X0CTRL, 1, 0, 0); 272 exynos_smc(SMC_CMD_L2X0CTRL, 1, 0, 0);
275 273
276 return 0; 274 return 0;
277} 275}
278#endif 276#endif
279#endif /* ARM_TRUSTZONE_FIRMWARE */ 277#endif /* ARM_TRUSTZONE_FIRMWARE */
280 278
281 279
282void 280void
283exynos_sysctl_cpufreq_init(void) 281exynos_sysctl_cpufreq_init(void)
284{ 282{
285 const struct sysctlnode *node, *cpunode, *freqnode; 283 const struct sysctlnode *node, *cpunode, *freqnode;
286 char *cpos; 284 char *cpos;
287 int i, val; 285 int i, val;
288 int error; 286 int error;
289 287
290 memset(sysctl_cpu_freqs_txt, (int) ' ', sizeof(sysctl_cpu_freqs_txt)); 288 memset(sysctl_cpu_freqs_txt, (int) ' ', sizeof(sysctl_cpu_freqs_txt));
291 cpos = sysctl_cpu_freqs_txt; 289 cpos = sysctl_cpu_freqs_txt;
292 for (i = 0; i < ncpu_freq_settings; i++) { 290 for (i = 0; i < ncpu_freq_settings; i++) {
293 val = cpu_freq_settings[i].freq; 291 val = cpu_freq_settings[i].freq;
294 snprintf(cpos, 6, "%d ", val); 292 snprintf(cpos, 6, "%d ", val);
295 cpos += (val < 1000) ? 4 : 5; 293 cpos += (val < 1000) ? 4 : 5;
296 } 294 }
297 *cpos = 0; 295 *cpos = 0;
298 296
299 error = sysctl_createv(NULL, 0, NULL, &node, 297 error = sysctl_createv(NULL, 0, NULL, &node,
300 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 298 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL,
301 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL); 299 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL);
302 if (error) 300 if (error)
303 printf("couldn't create `machdep' node\n"); 301 printf("couldn't create `machdep' node\n");
304 302
305 error = sysctl_createv(NULL, 0, &node, &cpunode, 303 error = sysctl_createv(NULL, 0, &node, &cpunode,
306 0, CTLTYPE_NODE, "cpu", NULL, 304 0, CTLTYPE_NODE, "cpu", NULL,
307 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 305 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL);
308 if (error) 306 if (error)
309 printf("couldn't create `cpu' node\n"); 307 printf("couldn't create `cpu' node\n");
310 308
311 error = sysctl_createv(NULL, 0, &cpunode, &freqnode, 309 error = sysctl_createv(NULL, 0, &cpunode, &freqnode,
312 0, CTLTYPE_NODE, "frequency", NULL, 310 0, CTLTYPE_NODE, "frequency", NULL,
313 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 311 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL);
314 if (error) 312 if (error)
315 printf("couldn't create `frequency' node\n"); 313 printf("couldn't create `frequency' node\n");
316 314
317 error = sysctl_createv(NULL, 0, &freqnode, &node, 315 error = sysctl_createv(NULL, 0, &freqnode, &node,
318 CTLFLAG_READWRITE, CTLTYPE_INT, "target", NULL, 316 CTLFLAG_READWRITE, CTLTYPE_INT, "target", NULL,
319 sysctl_cpufreq_target, 0, &cpu_freq_target, 0, 317 sysctl_cpufreq_target, 0, &cpu_freq_target, 0,
320 CTL_CREATE, CTL_EOL); 318 CTL_CREATE, CTL_EOL);
321 if (error) 319 if (error)
322 printf("couldn't create `target' node\n"); 320 printf("couldn't create `target' node\n");
323 321
324 error = sysctl_createv(NULL, 0, &freqnode, &node, 322 error = sysctl_createv(NULL, 0, &freqnode, &node,
325 0, CTLTYPE_INT, "current", NULL, 323 0, CTLTYPE_INT, "current", NULL,
326 sysctl_cpufreq_current, 0, NULL, 0, 324 sysctl_cpufreq_current, 0, NULL, 0,
327 CTL_CREATE, CTL_EOL); 325 CTL_CREATE, CTL_EOL);
328 if (error) 326 if (error)
329 printf("couldn't create `current' node\n"); 327 printf("couldn't create `current' node\n");
330 328
331 error = sysctl_createv(NULL, 0, &freqnode, &node, 329 error = sysctl_createv(NULL, 0, &freqnode, &node,
332 CTLFLAG_READONLY, CTLTYPE_STRING, "available", NULL, 330 CTLFLAG_READONLY, CTLTYPE_STRING, "available", NULL,
333 NULL, 0, sysctl_cpu_freqs_txt, 0, 331 NULL, 0, sysctl_cpu_freqs_txt, 0,
334 CTL_CREATE, CTL_EOL); 332 CTL_CREATE, CTL_EOL);
335 if (error) 333 if (error)
336 printf("couldn't create `available' node\b"); 334 printf("couldn't create `available' node\b");
337} 335}
338 336
339 337
340uint64_t 338uint64_t
341exynos_get_cpufreq(void) 339exynos_get_cpufreq(void)
342{ 340{
343 uint32_t regval; 341 uint32_t regval;
344 uint32_t freq; 342 uint32_t freq;
345 343
346 regval = bus_space_read_4(&armv7_generic_bs_tag, exynos_cmu_apll_bsh, 344 regval = bus_space_read_4(&armv7_generic_bs_tag, exynos_cmu_apll_bsh,
347 PLL_CON0_OFFSET); 345 PLL_CON0_OFFSET);
348 freq = PLL_FREQ(EXYNOS_F_IN_FREQ, regval); 346 freq = PLL_FREQ(EXYNOS_F_IN_FREQ, regval);
349 347
350 return freq; 348 return freq;
351} 349}
352 350
353 351
354static void 352static void
355exynos_set_cpufreq(const struct cpu_freq *freqreq) 353exynos_set_cpufreq(const struct cpu_freq *freqreq)
356{ 354{
357 struct cpu_info *ci; 355 struct cpu_info *ci;
358 uint32_t regval; 356 uint32_t regval;
359 int M, P, S; 357 int M, P, S;
360 int cii; 358 int cii;
361 359
362 M = freqreq->M; 360 M = freqreq->M;
363 P = freqreq->P; 361 P = freqreq->P;
364 S = freqreq->S; 362 S = freqreq->S;
365 363
366 regval = __SHIFTIN(M, PLL_CON0_M) | 364 regval = __SHIFTIN(M, PLL_CON0_M) |
367 __SHIFTIN(P, PLL_CON0_P) | 365 __SHIFTIN(P, PLL_CON0_P) |
368 __SHIFTIN(S, PLL_CON0_S); 366 __SHIFTIN(S, PLL_CON0_S);
369 367
370 /* enable PPL and write config */ 368 /* enable PPL and write config */
371 regval |= PLL_CON0_ENABLE; 369 regval |= PLL_CON0_ENABLE;
372 bus_space_write_4(&armv7_generic_bs_tag, exynos_cmu_apll_bsh, PLL_CON0_OFFSET, 370 bus_space_write_4(&armv7_generic_bs_tag, exynos_cmu_apll_bsh, PLL_CON0_OFFSET,
373 regval); 371 regval);
374 372
375 /* update our cycle counter i.e. our CPU frequency for all CPUs */ 373 /* update our cycle counter i.e. our CPU frequency for all CPUs */
376 for (CPU_INFO_FOREACH(cii, ci)) { 374 for (CPU_INFO_FOREACH(cii, ci)) {
377 ci->ci_data.cpu_cc_freq = exynos_get_cpufreq(); 375 ci->ci_data.cpu_cc_freq = exynos_get_cpufreq();
378 } 376 }
379} 377}
380 378
381 379
382static int 380static int
383sysctl_cpufreq_target(SYSCTLFN_ARGS) 381sysctl_cpufreq_target(SYSCTLFN_ARGS)
384{ 382{
385 struct sysctlnode node; 383 struct sysctlnode node;
386 uint32_t t, curfreq, minfreq, maxfreq; 384 uint32_t t, curfreq, minfreq, maxfreq;
387 int i, best_i, diff; 385 int i, best_i, diff;
388 int error; 386 int error;
389 387
390 curfreq = exynos_get_cpufreq() / (1000*1000); 388 curfreq = exynos_get_cpufreq() / (1000*1000);
391 t = *(int *)rnode->sysctl_data; 389 t = *(int *)rnode->sysctl_data;
392 if (t == 0) 390 if (t == 0)
393 t = curfreq; 391 t = curfreq;
394 392
395 node = *rnode; 393 node = *rnode;
396 node.sysctl_data = &t; 394 node.sysctl_data = &t;
397 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 395 error = sysctl_lookup(SYSCTLFN_CALL(&node));
398 if (error || newp == NULL) 396 if (error || newp == NULL)
399 return error; 397 return error;
400 398
401 minfreq = cpu_freq_settings[0].freq; 399 minfreq = cpu_freq_settings[0].freq;
402 maxfreq = cpu_freq_settings[ncpu_freq_settings-1].freq; 400 maxfreq = cpu_freq_settings[ncpu_freq_settings-1].freq;
403 401
404 if ((t < minfreq) || (t > maxfreq)) 402 if ((t < minfreq) || (t > maxfreq))
405 return EINVAL; 403 return EINVAL;
406 404
407 if (t == curfreq) { 405 if (t == curfreq) {
408 *(int *)rnode->sysctl_data = t; 406 *(int *)rnode->sysctl_data = t;
409 return 0; 407 return 0;
410 } 408 }
411 409
412 diff = maxfreq; 410 diff = maxfreq;
413 best_i = -1; 411 best_i = -1;
414 for (i = 0; i < ncpu_freq_settings; i++) { 412 for (i = 0; i < ncpu_freq_settings; i++) {
415 if (abs(t - cpu_freq_settings[i].freq) <= diff) { 413 if (abs(t - cpu_freq_settings[i].freq) <= diff) {
416 diff = labs(t - cpu_freq_settings[i].freq); 414 diff = labs(t - cpu_freq_settings[i].freq);
417 best_i = i; 415 best_i = i;
418 } 416 }
419 } 417 }
420 if (best_i < 0) 418 if (best_i < 0)
421 return EINVAL; 419 return EINVAL;
422 420
423 exynos_set_cpufreq(&cpu_freq_settings[best_i]); 421 exynos_set_cpufreq(&cpu_freq_settings[best_i]);
424 422
425 *(int *)rnode->sysctl_data = t; 423 *(int *)rnode->sysctl_data = t;
426 return 0; 424 return 0;
427} 425}
428 426
429 427
430static int 428static int
431sysctl_cpufreq_current(SYSCTLFN_ARGS) 429sysctl_cpufreq_current(SYSCTLFN_ARGS)
432{ 430{
433 struct sysctlnode node = *rnode; 431 struct sysctlnode node = *rnode;
434 uint32_t freq; 432 uint32_t freq;
435 433
436 freq = exynos_get_cpufreq() / (1000*1000); 434 freq = exynos_get_cpufreq() / (1000*1000);
437 node.sysctl_data = &freq; 435 node.sysctl_data = &freq;
438 436
439 return sysctl_lookup(SYSCTLFN_CALL(&node)); 437 return sysctl_lookup(SYSCTLFN_CALL(&node));
440} 438}
441 439
442 440
443#ifdef VERBOSE_INIT_ARM 441#ifdef VERBOSE_INIT_ARM
444#define DUMP_PLL(v, var) \ 442#define DUMP_PLL(v, var) \
445 reg = EXYNOS##v##_CMU_##var + PLL_CON0_OFFSET;\ 443 reg = EXYNOS##v##_CMU_##var + PLL_CON0_OFFSET;\
446 regval = bus_space_read_4(&armv7_generic_bs_tag, exynos_cmu_bsh, reg); \ 444 regval = bus_space_read_4(&armv7_generic_bs_tag, exynos_cmu_bsh, reg); \
447 freq = PLL_FREQ(EXYNOS_F_IN_FREQ, regval); \ 445 freq = PLL_FREQ(EXYNOS_F_IN_FREQ, regval); \
448 printf("%8s at %d Mhz\n", #var, freq/(1000*1000)); 446 printf("%8s at %d Mhz\n", #var, freq/(1000*1000));
449 447
450 448
451static void 449static void
452exynos_dump_clocks(void) 450exynos_dump_clocks(void)
453{ 451{
454 uint32_t reg = 0; 452 uint32_t reg = 0;
455 uint32_t regval; 453 uint32_t regval;
456 uint32_t freq; 454 uint32_t freq;
457 455
458 printf("Initial PLL settings\n"); 456 printf("Initial PLL settings\n");
459#ifdef EXYNOS4 457#ifdef SOC_EXYNOS4
460 DUMP_PLL(4, APLL); 458 DUMP_PLL(4, APLL);
461 DUMP_PLL(4, MPLL); 459 DUMP_PLL(4, MPLL);
462 DUMP_PLL(4, EPLL); 460 DUMP_PLL(4, EPLL);
463 DUMP_PLL(4, VPLL); 461 DUMP_PLL(4, VPLL);
464#endif 462#endif
465#ifdef EXYNOS5 463#ifdef SOC_EXYNOS5
466 DUMP_PLL(5, APLL); 464 DUMP_PLL(5, APLL);
467 DUMP_PLL(5, MPLL); 465 DUMP_PLL(5, MPLL);
468 DUMP_PLL(5, KPLL); 466 DUMP_PLL(5, KPLL);
469 DUMP_PLL(5, DPLL); 467 DUMP_PLL(5, DPLL);
470 DUMP_PLL(5, VPLL); 468 DUMP_PLL(5, VPLL);
471 DUMP_PLL(5, CPLL); 469 DUMP_PLL(5, CPLL);
472 DUMP_PLL(5, GPLL); 470 DUMP_PLL(5, GPLL);
473 DUMP_PLL(5, BPLL); 471 DUMP_PLL(5, BPLL);
474#endif 472#endif
475} 473}
476#undef DUMP_PLL 474#undef DUMP_PLL
477#endif 475#endif
478 476
479 477
480/* XXX clock stuff needs major work XXX */ 478/* XXX clock stuff needs major work XXX */
481 479
482void 480void
 481exynos_init_clkout_for_usb(void)
 482{
 483 /* Select XUSBXTI as source for CLKOUT */
 484 bus_space_write_4(&armv7_generic_bs_tag, exynos_pmu_bsh,
 485 EXYNOS_PMU_DEBUG_CLKOUT, 0x1000);
 486}
 487
 488
 489void
483exynos_clocks_bootstrap(void) 490exynos_clocks_bootstrap(void)
484{ 491{
485 KASSERT(ncpu_freq_settings != 0); 492 KASSERT(ncpu_freq_settings != 0);
486 KASSERT(ncpu_freq_settings < NFRQS); 493 KASSERT(ncpu_freq_settings < NFRQS);
487 int fsel; 494 int fsel;
488 495
489#ifdef VERBOSE_INIT_ARM 496#ifdef VERBOSE_INIT_ARM
490 exynos_dump_clocks(); 497 exynos_dump_clocks();
491#endif 498#endif
492 499
493 /* set (max) cpufreq */ 500 /* set (max) cpufreq */
494 fsel = ncpu_freq_settings-1; 501 fsel = ncpu_freq_settings-1;
495 502
496#ifdef EXYNOS5 503#ifdef SOC_EXYNOS5
497 /* XXX BUGFIX selecting freq on E5 goes wrong for now XXX */ 504 /* XXX BUGFIX selecting freq on E5 goes wrong for now XXX */
498 fsel = EXYNOS5_DEFAULT_ENTRY; 505 fsel = EXYNOS5_DEFAULT_ENTRY;
499#endif 506#endif
500 507
501 exynos_set_cpufreq(&cpu_freq_settings[fsel]); 508 exynos_set_cpufreq(&cpu_freq_settings[fsel]);
502 509
503 /* set external USB frequency to XCLKOUT */ 510 /* set external USB frequency to XCLKOUT */
504 exynos_init_clkout_for_usb(); 511 exynos_init_clkout_for_usb();
505} 512}
506 513
507 514
508void 515void
509exynos_bootstrap(vaddr_t iobase, vaddr_t uartbase) 516exynos_bootstrap(vaddr_t iobase, vaddr_t uartbase)
510{ 517{
511 int error; 518 int error;
512 size_t core_size, audiocore_size; 519 size_t core_size, audiocore_size;
513 bus_addr_t audiocore_pbase; 520 bus_addr_t audiocore_pbase;
514 bus_addr_t audiocore_vbase __diagused; 521 bus_addr_t audiocore_vbase __diagused;
515 bus_addr_t exynos_wdt_offset; 522 bus_addr_t exynos_wdt_offset;
516 bus_addr_t exynos_pmu_offset; 523 bus_addr_t exynos_pmu_offset;
517 bus_addr_t exynos_sysreg_offset; 524 bus_addr_t exynos_sysreg_offset;
518 bus_addr_t exynos_cmu_apll_offset; 525 bus_addr_t exynos_cmu_apll_offset;
519 526
520 /* set up early console so we can use printf() and friends */ 527 /* set up early console so we can use printf() and friends */
521#ifdef EXYNOS_CONSOLE_EARLY 528#ifdef EXYNOS_CONSOLE_EARLY
522 uart_base = (volatile uint8_t *) uartbase; 529 uart_base = (volatile uint8_t *) uartbase;
523 cn_tab = &exynos_earlycons; 530 cn_tab = &exynos_earlycons;
524 printf("Exynos early console operational\n\n"); 531 printf("Exynos early console operational\n\n");
525#endif 532#endif
526 533
527#ifdef EXYNOS4 534#ifdef SOC_EXYNOS4
528 core_size = EXYNOS4_CORE_SIZE; 535 core_size = EXYNOS4_CORE_SIZE;
529 audiocore_size = EXYNOS4_AUDIOCORE_SIZE; 536 audiocore_size = EXYNOS4_AUDIOCORE_SIZE;
530 audiocore_pbase = EXYNOS4_AUDIOCORE_PBASE; 537 audiocore_pbase = EXYNOS4_AUDIOCORE_PBASE;
531 audiocore_vbase = EXYNOS4_AUDIOCORE_VBASE; 538 audiocore_vbase = EXYNOS4_AUDIOCORE_VBASE;
532 exynos_wdt_offset = EXYNOS4_WDT_OFFSET; 539 exynos_wdt_offset = EXYNOS4_WDT_OFFSET;
533 exynos_pmu_offset = EXYNOS4_PMU_OFFSET; 540 exynos_pmu_offset = EXYNOS4_PMU_OFFSET;
534 exynos_sysreg_offset = EXYNOS4_SYSREG_OFFSET; 541 exynos_sysreg_offset = EXYNOS4_SYSREG_OFFSET;
535 exynos_cmu_apll_offset = EXYNOS4_CMU_APLL; 542 exynos_cmu_apll_offset = EXYNOS4_CMU_APLL;
536 543
537 cpu_freq_settings = cpu_freq_settings_exynos4; 544 cpu_freq_settings = cpu_freq_settings_exynos4;
538 ncpu_freq_settings = __arraycount(cpu_freq_settings_exynos4); 545 ncpu_freq_settings = __arraycount(cpu_freq_settings_exynos4);
539#endif 546#endif
540 547
541#ifdef EXYNOS5 548#ifdef SOC_EXYNOS5
542 core_size = EXYNOS5_CORE_SIZE; 549 core_size = EXYNOS5_CORE_SIZE;
543 audiocore_size = EXYNOS5_AUDIOCORE_SIZE; 550 audiocore_size = EXYNOS5_AUDIOCORE_SIZE;
544 audiocore_pbase = EXYNOS5_AUDIOCORE_PBASE; 551 audiocore_pbase = EXYNOS5_AUDIOCORE_PBASE;
545 audiocore_vbase = EXYNOS5_AUDIOCORE_VBASE; 552 audiocore_vbase = EXYNOS5_AUDIOCORE_VBASE;
546 exynos_wdt_offset = EXYNOS5_WDT_OFFSET; 553 exynos_wdt_offset = EXYNOS5_WDT_OFFSET;
547 exynos_pmu_offset = EXYNOS5_PMU_OFFSET; 554 exynos_pmu_offset = EXYNOS5_PMU_OFFSET;
548 exynos_sysreg_offset = EXYNOS5_SYSREG_OFFSET; 555 exynos_sysreg_offset = EXYNOS5_SYSREG_OFFSET;
549 exynos_cmu_apll_offset = EXYNOS5_CMU_APLL; 556 exynos_cmu_apll_offset = EXYNOS5_CMU_APLL;
550 557
551 cpu_freq_settings = cpu_freq_settings_exynos5; 558 cpu_freq_settings = cpu_freq_settings_exynos5;
552 ncpu_freq_settings = __arraycount(cpu_freq_settings_exynos5); 559 ncpu_freq_settings = __arraycount(cpu_freq_settings_exynos5);
553#endif 560#endif
554 561
555 /* map in the exynos io registers */ 562 /* map in the exynos io registers */
556 error = bus_space_map(&armv7_generic_bs_tag, EXYNOS_CORE_PBASE, 563 error = bus_space_map(&armv7_generic_bs_tag, EXYNOS_CORE_PBASE,
557 core_size, 0, &exynos_core_bsh); 564 core_size, 0, &exynos_core_bsh);
558 if (error) 565 if (error)
559 panic("%s: failed to map in Exynos SFR registers: %d", 566 panic("%s: failed to map in Exynos SFR registers: %d",
560 __func__, error); 567 __func__, error);
561 KASSERT(exynos_core_bsh == iobase); 568 KASSERT(exynos_core_bsh == iobase);
562 569
563 error = bus_space_map(&armv7_generic_bs_tag, audiocore_pbase, 570 error = bus_space_map(&armv7_generic_bs_tag, audiocore_pbase,
564 audiocore_size, 0, &exynos_audiocore_bsh); 571 audiocore_size, 0, &exynos_audiocore_bsh);
565 if (error) 572 if (error)
566 panic("%s: failed to map in Exynos audio SFR registers: %d", 573 panic("%s: failed to map in Exynos audio SFR registers: %d",
567 __func__, error); 574 __func__, error);
568 KASSERT(exynos_audiocore_bsh == audiocore_vbase); 575 KASSERT(exynos_audiocore_bsh == audiocore_vbase);
569 576
570 /* map in commonly used subregions and common used register banks */ 577 /* map in commonly used subregions and common used register banks */
571 error = bus_space_subregion(&armv7_generic_bs_tag, exynos_core_bsh, 578 error = bus_space_subregion(&armv7_generic_bs_tag, exynos_core_bsh,
572 exynos_wdt_offset, EXYNOS_BLOCK_SIZE, &exynos_wdt_bsh); 579 exynos_wdt_offset, EXYNOS_BLOCK_SIZE, &exynos_wdt_bsh);
573 if (error) 580 if (error)
574 panic("%s: failed to subregion wdt registers: %d", 581 panic("%s: failed to subregion wdt registers: %d",
575 __func__, error); 582 __func__, error);
576 583
577 error = bus_space_subregion(&armv7_generic_bs_tag, exynos_core_bsh, 584 error = bus_space_subregion(&armv7_generic_bs_tag, exynos_core_bsh,
578 exynos_pmu_offset, EXYNOS_BLOCK_SIZE, &exynos_pmu_bsh); 585 exynos_pmu_offset, EXYNOS_BLOCK_SIZE, &exynos_pmu_bsh);
579 if (error) 586 if (error)
580 panic("%s: failed to subregion pmu registers: %d", 587 panic("%s: failed to subregion pmu registers: %d",
581 __func__, error); 588 __func__, error);
582 589
583 exynos_cmu_bsh = exynos_core_bsh; 590 exynos_cmu_bsh = exynos_core_bsh;
584 bus_space_subregion(&armv7_generic_bs_tag, exynos_core_bsh, 591 bus_space_subregion(&armv7_generic_bs_tag, exynos_core_bsh,
585 exynos_sysreg_offset, EXYNOS_BLOCK_SIZE, 592 exynos_sysreg_offset, EXYNOS_BLOCK_SIZE,
586 &exynos_sysreg_bsh); 593 &exynos_sysreg_bsh);
587 if (error) 594 if (error)
588 panic("%s: failed to subregion sysreg registers: %d", 595 panic("%s: failed to subregion sysreg registers: %d",
589 __func__, error); 596 __func__, error);
590 597
591 error = bus_space_subregion(&armv7_generic_bs_tag, exynos_cmu_bsh, 598 error = bus_space_subregion(&armv7_generic_bs_tag, exynos_cmu_bsh,
592 exynos_cmu_apll_offset, 0xfff, &exynos_cmu_apll_bsh); 599 exynos_cmu_apll_offset, 0xfff, &exynos_cmu_apll_bsh);
593 if (error) 600 if (error)
594 panic("%s: failed to subregion cmu apll registers: %d", 601 panic("%s: failed to subregion cmu apll registers: %d",
595 __func__, error); 602 __func__, error);
596 603
597 /* init bus dma tags */ 
598 exynos_dma_bootstrap(physmem * PAGE_SIZE); 
599 
600 /* gpio bootstrapping delayed */ 604 /* gpio bootstrapping delayed */
601} 605}
602 606
603 607
604void 608void
605exynos_device_register(device_t self, void *aux) 609exynos_device_register(device_t self, void *aux)
606{ 610{
607 if (device_is_a(self, "armperiph") 611 if (device_is_a(self, "armperiph")
608 && device_is_a(device_parent(self), "mainbus")) { 612 && device_is_a(device_parent(self), "mainbus")) {
609 /* 613 /*
610 * XXX KLUDGE ALERT XXX 614 * XXX KLUDGE ALERT XXX
611 * The iot mainbus supplies is completely wrong since it scales 615 * The iot mainbus supplies is completely wrong since it scales
612 * addresses by 2. The simplest remedy is to replace with our 616 * addresses by 2. The simplest remedy is to replace with our
613 * bus space used for the armcore registers (which armperiph uses). 617 * bus space used for the armcore registers (which armperiph uses).
614 */ 618 */
615 struct mainbus_attach_args * const mb = aux; 619 struct mainbus_attach_args * const mb = aux;
616 mb->mb_iot = &armv7_generic_bs_tag; 620 mb->mb_iot = &armv7_generic_bs_tag;
617 return; 621 return;
618 } 622 }
619 if (device_is_a(self, "armgic") 623 if (device_is_a(self, "armgic")
620 && device_is_a(device_parent(self), "armperiph")) { 624 && device_is_a(device_parent(self), "armperiph")) {
621 /* 625 /*
622 * The Exynos4420 armgic is located at a different location! 626 * The Exynos4420 armgic is located at a different location!
623 */ 627 */
624 628
625 extern uint32_t exynos_soc_id; 629 extern uint32_t exynos_soc_id;
626 630
627 switch (EXYNOS_PRODUCT_ID(exynos_soc_id)) { 631 switch (EXYNOS_PRODUCT_ID(exynos_soc_id)) {
628#ifdef EXYNOS5 632#ifdef SOC_EXYNOS5
629 case 0xe5410: 633 case 0xe5410:
630 /* offsets not changed on matt's request */ 634 /* offsets not changed on matt's request */
631#if 0 635#if 0
632 mpcaa->mpcaa_memh = EXYNOS_CORE_VBASE; 636 mpcaa->mpcaa_memh = EXYNOS_CORE_VBASE;
633 mpcaa->mpcaa_off1 = EXYNOS5_GIC_IOP_DISTRIBUTOR_OFFSET; 637 mpcaa->mpcaa_off1 = EXYNOS5_GIC_IOP_DISTRIBUTOR_OFFSET;
634 mpcaa->mpcaa_off2 = EXYNOS5_GIC_IOP_CONTROLLER_OFFSET; 638 mpcaa->mpcaa_off2 = EXYNOS5_GIC_IOP_CONTROLLER_OFFSET;
635#endif 639#endif
636 break; 640 break;
637 case 0xe5422: { 641 case 0xe5422: {
638 struct mpcore_attach_args * const mpcaa = aux; 642 struct mpcore_attach_args * const mpcaa = aux;
639 643
640 mpcaa->mpcaa_memh = EXYNOS_CORE_VBASE; 644 mpcaa->mpcaa_memh = EXYNOS_CORE_VBASE;
641 mpcaa->mpcaa_off1 = EXYNOS5_GIC_IOP_DISTRIBUTOR_OFFSET; 645 mpcaa->mpcaa_off1 = EXYNOS5_GIC_IOP_DISTRIBUTOR_OFFSET;
642 mpcaa->mpcaa_off2 = EXYNOS5_GIC_IOP_CONTROLLER_OFFSET; 646 mpcaa->mpcaa_off2 = EXYNOS5_GIC_IOP_CONTROLLER_OFFSET;
643 break; 647 break;
644 } 648 }
645#endif 649#endif
646#ifdef EXYNOS4 650#ifdef SOC_EXYNOS4
647 case 0xe4410: 651 case 0xe4410:
648 case 0xe4412: { 652 case 0xe4412: {
649 struct mpcore_attach_args * const mpcaa = aux; 653 struct mpcore_attach_args * const mpcaa = aux;
650 654
651 mpcaa->mpcaa_memh = EXYNOS_CORE_VBASE; 655 mpcaa->mpcaa_memh = EXYNOS_CORE_VBASE;
652 mpcaa->mpcaa_off1 = EXYNOS4_GIC_DISTRIBUTOR_OFFSET; 656 mpcaa->mpcaa_off1 = EXYNOS4_GIC_DISTRIBUTOR_OFFSET;
653 mpcaa->mpcaa_off2 = EXYNOS4_GIC_CNTR_OFFSET; 657 mpcaa->mpcaa_off2 = EXYNOS4_GIC_CNTR_OFFSET;
654 break; 658 break;
655 } 659 }
656#endif 660#endif
657 default: 661 default:
658 panic("%s: unknown SoC product id %#x", __func__, 662 panic("%s: unknown SoC product id %#x", __func__,
659 (u_int)EXYNOS_PRODUCT_ID(exynos_soc_id)); 663 (u_int)EXYNOS_PRODUCT_ID(exynos_soc_id));
660 } 664 }
661 return; 665 return;
662 } 666 }
663 if (device_is_a(self, "armgtmr") || device_is_a(self, "mct")) { 667 if (device_is_a(self, "armgtmr") || device_is_a(self, "mct")) {
664#ifdef EXYNOS5 668#ifdef SOC_EXYNOS5
665 /* 669 /*
666 * The global timer is dependent on the MCT running. 670 * The global timer is dependent on the MCT running.
667 */ 671 */
668 bus_size_t o = EXYNOS5_MCT_OFFSET + MCT_G_TCON; 672 bus_size_t o = EXYNOS5_MCT_OFFSET + MCT_G_TCON;
669 uint32_t v = bus_space_read_4(&armv7_generic_bs_tag, exynos_core_bsh, 673 uint32_t v = bus_space_read_4(&armv7_generic_bs_tag, exynos_core_bsh,
670 o); 674 o);
671 v |= G_TCON_START; 675 v |= G_TCON_START;
672 bus_space_write_4(&armv7_generic_bs_tag, exynos_core_bsh, o, v); 676 bus_space_write_4(&armv7_generic_bs_tag, exynos_core_bsh, o, v);
673#endif 677#endif
674 /* 678 /*
675 * The frequencies of the timers are the reference 679 * The frequencies of the timers are the reference
676 * frequency. 680 * frequency.
677 */ 681 */
678 prop_dictionary_set_uint32(device_properties(self), 682 prop_dictionary_set_uint32(device_properties(self),
679 "frequency", EXYNOS_F_IN_FREQ); 683 "frequency", EXYNOS_F_IN_FREQ);
680 return; 684 return;
681 } 685 }
682} 686}
683 687
684 688
685void 689void
686exynos_device_register_post_config(device_t self, void *aux) 690exynos_device_register_post_config(device_t self, void *aux)
687{ 691{
688} 692}
689 693
690void 694void
691exynos_usb_soc_powerup(void) 695exynos_usb_soc_powerup(void)
692{ 696{
693 /* XXX 5422 XXX */ 697 /* XXX 5422 XXX */
694} 698}
695 699
696 700
697/* 701/*
698 * USB Phy SoC dependent handling 702 * USB Phy SoC dependent handling
699 */ 703 */
700 704
701/* XXX 5422 not handled since its unknown how it handles this XXX*/ 705/* XXX 5422 not handled since its unknown how it handles this XXX*/
702static void 706static void
703exynos_usb2_set_isolation(bool on) 707exynos_usb2_set_isolation(bool on)
704{ 708{
705 uint32_t en_mask, regval; 709 uint32_t en_mask, regval;
706 bus_addr_t reg; 710 bus_addr_t reg;
707 711
708 /* enable PHY */ 712 /* enable PHY */
709 reg = EXYNOS_PMU_USB_PHY_CTRL; 713 reg = EXYNOS_PMU_USB_PHY_CTRL;
710 714
711 if (IS_EXYNOS5_P() || IS_EXYNOS4410_P()) { 715 if (IS_EXYNOS5_P() || IS_EXYNOS4410_P()) {
712 /* set usbhost mode */ 716 /* set usbhost mode */
713 regval = on ? 0 : USB20_PHY_HOST_LINK_EN; 717 regval = on ? 0 : USB20_PHY_HOST_LINK_EN;
714 bus_space_write_4(&armv7_generic_bs_tag, exynos_sysreg_bsh, 718 bus_space_write_4(&armv7_generic_bs_tag, exynos_sysreg_bsh,
715 EXYNOS5_SYSREG_USB20_PHY_TYPE, regval); 719 EXYNOS5_SYSREG_USB20_PHY_TYPE, regval);
716 reg = EXYNOS_PMU_USBHOST_PHY_CTRL; 720 reg = EXYNOS_PMU_USBHOST_PHY_CTRL;
717 } 721 }
718 722
719 /* do enable PHY */ 723 /* do enable PHY */
720 en_mask = PMU_PHY_ENABLE; 724 en_mask = PMU_PHY_ENABLE;
721 regval = bus_space_read_4(&armv7_generic_bs_tag, exynos_pmu_bsh, reg); 725 regval = bus_space_read_4(&armv7_generic_bs_tag, exynos_pmu_bsh, reg);
722 regval = on ? regval & ~en_mask : regval | en_mask; 726 regval = on ? regval & ~en_mask : regval | en_mask;
723 727
724 bus_space_write_4(&armv7_generic_bs_tag, exynos_pmu_bsh, 728 bus_space_write_4(&armv7_generic_bs_tag, exynos_pmu_bsh,
725 reg, regval); 729 reg, regval);
726 730
727 if (IS_EXYNOS4X12_P()) { 731 if (IS_EXYNOS4X12_P()) {
728 bus_space_write_4(&armv7_generic_bs_tag, exynos_pmu_bsh, 732 bus_space_write_4(&armv7_generic_bs_tag, exynos_pmu_bsh,
729 EXYNOS_PMU_USB_HSIC_1_PHY_CTRL, regval); 733 EXYNOS_PMU_USB_HSIC_1_PHY_CTRL, regval);
730 bus_space_write_4(&armv7_generic_bs_tag, exynos_pmu_bsh, 734 bus_space_write_4(&armv7_generic_bs_tag, exynos_pmu_bsh,
731 EXYNOS_PMU_USB_HSIC_2_PHY_CTRL, regval); 735 EXYNOS_PMU_USB_HSIC_2_PHY_CTRL, regval);
732 } 736 }
733} 737}
734 738
735 739
736#ifdef EXYNOS4 740#ifdef SOC_EXYNOS4
737static void 741static void
738exynos4_usb2phy_enable(bus_space_handle_t usb2phy_bsh) 742exynos4_usb2phy_enable(bus_space_handle_t usb2phy_bsh)
739{ 743{
740 uint32_t phypwr, rstcon, clkreg; 744 uint32_t phypwr, rstcon, clkreg;
741 745
742 /* write clock value */ 746 /* write clock value */
743 clkreg = FSEL_CLKSEL_24M; 747 clkreg = FSEL_CLKSEL_24M;
744 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 748 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh,
745 USB_PHYCLK, clkreg); 749 USB_PHYCLK, clkreg);
746 750
747 /* set device and host to normal */ 751 /* set device and host to normal */
748 phypwr = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh, 752 phypwr = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh,
749 USB_PHYPWR); 753 USB_PHYPWR);
750 754
751 /* enable analog, enable otg, unsleep phy0 (host) */ 755 /* enable analog, enable otg, unsleep phy0 (host) */
752 phypwr &= ~PHYPWR_NORMAL_MASK_PHY0; 756 phypwr &= ~PHYPWR_NORMAL_MASK_PHY0;
753 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 757 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh,
754 USB_PHYPWR, phypwr); 758 USB_PHYPWR, phypwr);
755 759
756 if (IS_EXYNOS4X12_P()) { 760 if (IS_EXYNOS4X12_P()) {
757 /* enable hsic0 (host), enable hsic1 and phy1 (otg) */ 761 /* enable hsic0 (host), enable hsic1 and phy1 (otg) */
758 phypwr = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh, 762 phypwr = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh,
759 USB_PHYPWR); 763 USB_PHYPWR);
760 phypwr &= ~(PHYPWR_NORMAL_MASK_HSIC0 | 764 phypwr &= ~(PHYPWR_NORMAL_MASK_HSIC0 |
761 PHYPWR_NORMAL_MASK_HSIC1 | 765 PHYPWR_NORMAL_MASK_HSIC1 |
762 PHYPWR_NORMAL_MASK_PHY1); 766 PHYPWR_NORMAL_MASK_PHY1);
763 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 767 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh,
764 USB_PHYPWR, phypwr); 768 USB_PHYPWR, phypwr);
765 } 769 }
766 770
767 /* reset both phy and link of device */ 771 /* reset both phy and link of device */
768 rstcon = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh, 772 rstcon = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh,
769 USB_RSTCON); 773 USB_RSTCON);
770 rstcon |= RSTCON_DEVPHY_SWRST; 774 rstcon |= RSTCON_DEVPHY_SWRST;
771 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 775 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh,
772 USB_RSTCON, rstcon); 776 USB_RSTCON, rstcon);
773 DELAY(10000); 777 DELAY(10000);
774 rstcon &= ~RSTCON_DEVPHY_SWRST; 778 rstcon &= ~RSTCON_DEVPHY_SWRST;
775 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 779 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh,
776 USB_RSTCON, rstcon); 780 USB_RSTCON, rstcon);
777 781
778 if (IS_EXYNOS4X12_P()) { 782 if (IS_EXYNOS4X12_P()) {
779 /* reset both phy and link of host */ 783 /* reset both phy and link of host */
780 rstcon = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh, 784 rstcon = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh,
781 USB_RSTCON); 785 USB_RSTCON);
782 rstcon |= RSTCON_HOSTPHY_SWRST | RSTCON_HOSTPHYLINK_SWRST; 786 rstcon |= RSTCON_HOSTPHY_SWRST | RSTCON_HOSTPHYLINK_SWRST;
783 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 787 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh,
784 USB_RSTCON, rstcon); 788 USB_RSTCON, rstcon);
785 DELAY(10000); 789 DELAY(10000);
786 rstcon &= ~(RSTCON_HOSTPHY_SWRST | RSTCON_HOSTPHYLINK_SWRST); 790 rstcon &= ~(RSTCON_HOSTPHY_SWRST | RSTCON_HOSTPHYLINK_SWRST);
787 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 791 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh,
788 USB_RSTCON, rstcon); 792 USB_RSTCON, rstcon);
789 } 793 }
790 794
791 /* wait for everything to be initialized */ 795 /* wait for everything to be initialized */
792 DELAY(80000); 796 DELAY(80000);
793} 797}
794#endif 798#endif
795 799
796 800
797#ifdef EXYNOS5 801#ifdef SOC_EXYNOS5
798static void 802static void
799exynos5410_usb2phy_enable(bus_space_handle_t usb2phy_bsh) 803exynos5410_usb2phy_enable(bus_space_handle_t usb2phy_bsh)
800{ 804{
801 uint32_t phyhost; //, phyotg; 805 uint32_t phyhost; //, phyotg;
802 uint32_t phyhsic; 806 uint32_t phyhsic;
803 uint32_t ehcictrl, ohcictrl; 807 uint32_t ehcictrl, ohcictrl;
804 808
805 /* host configuration: */ 809 /* host configuration: */
806 phyhost = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh, 810 phyhost = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh,
807 USB_PHY_HOST_CTRL0); 811 USB_PHY_HOST_CTRL0);
808 812
809 /* host phy reference clock; assumption its 24 MHz now */ 813 /* host phy reference clock; assumption its 24 MHz now */
810 phyhost &= ~HOST_CTRL0_FSEL_MASK; 814 phyhost &= ~HOST_CTRL0_FSEL_MASK;
811 phyhost |= __SHIFTIN(FSEL_CLKSEL_24M, HOST_CTRL0_FSEL_MASK); 815 phyhost |= __SHIFTIN(FSEL_CLKSEL_24M, HOST_CTRL0_FSEL_MASK);
812 816
813 /* enable normal mode of operation */ 817 /* enable normal mode of operation */
814 phyhost &= ~(HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP); 818 phyhost &= ~(HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP);
815 819
816 /* host phy reset */ 820 /* host phy reset */
817 phyhost &= ~(HOST_CTRL0_PHY_SWRST | HOST_CTRL0_PHY_SWRST_ALL | 821 phyhost &= ~(HOST_CTRL0_PHY_SWRST | HOST_CTRL0_PHY_SWRST_ALL |
818 HOST_CTRL0_SIDDQ | HOST_CTRL0_FORCESUSPEND | 822 HOST_CTRL0_SIDDQ | HOST_CTRL0_FORCESUSPEND |
819 HOST_CTRL0_FORCESLEEP); 823 HOST_CTRL0_FORCESLEEP);
820 824
821 /* host link reset */ 825 /* host link reset */
822 phyhost |= HOST_CTRL0_LINK_SWRST | HOST_CTRL0_UTMI_SWRST | 826 phyhost |= HOST_CTRL0_LINK_SWRST | HOST_CTRL0_UTMI_SWRST |
823 HOST_CTRL0_COMMONON_N; 827 HOST_CTRL0_COMMONON_N;
824 /* do the reset */ 828 /* do the reset */
825 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, USB_PHY_HOST_CTRL0, 829 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, USB_PHY_HOST_CTRL0,
826 phyhost); 830 phyhost);
827 DELAY(10000); 831 DELAY(10000);
828 832
829 phyhost &= ~(HOST_CTRL0_LINK_SWRST | HOST_CTRL0_UTMI_SWRST); 833 phyhost &= ~(HOST_CTRL0_LINK_SWRST | HOST_CTRL0_UTMI_SWRST);
830 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, USB_PHY_HOST_CTRL0, 834 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, USB_PHY_HOST_CTRL0,
831 phyhost); 835 phyhost);
832 836
833 /* HSIC control */ 837 /* HSIC control */
834 phyhsic = 838 phyhsic =
835 __SHIFTIN(HSIC_CTRL_REFCLKDIV_12, HSIC_CTRL_REFCLKDIV_MASK) | 839 __SHIFTIN(HSIC_CTRL_REFCLKDIV_12, HSIC_CTRL_REFCLKDIV_MASK) |
836 __SHIFTIN(HSIC_CTRL_REFCLKSEL_DEFAULT, HSIC_CTRL_REFCLKSEL_MASK) | 840 __SHIFTIN(HSIC_CTRL_REFCLKSEL_DEFAULT, HSIC_CTRL_REFCLKSEL_MASK) |
837 HSIC_CTRL_PHY_SWRST; 841 HSIC_CTRL_PHY_SWRST;
838 842
839 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL1, 843 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL1,
840 phyhsic); 844 phyhsic);
841 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL2, 845 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL2,
842 phyhsic); 846 phyhsic);
843 DELAY(10); 847 DELAY(10);
844 848
845 phyhsic &= ~HSIC_CTRL_PHY_SWRST; 849 phyhsic &= ~HSIC_CTRL_PHY_SWRST;
846 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL1, 850 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL1,
847 phyhsic); 851 phyhsic);
848 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL2, 852 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, USB_PHY_HSIC_CTRL2,
849 phyhsic); 853 phyhsic);
850 DELAY(80); 854 DELAY(80);
851 855
852#if 0 856#if 0
853 /* otg configuration: */ 857 /* otg configuration: */
854 phyotg = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh, 858 phyotg = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh,
855 USB_PHY_OTG_SYS); 859 USB_PHY_OTG_SYS);
856 860
857 /* otg phy refrence clock: assumption its 24 Mhz now */ 861 /* otg phy refrence clock: assumption its 24 Mhz now */
858 phyotg &= ~OTG_SYS_FSEL_MASK; 862 phyotg &= ~OTG_SYS_FSEL_MASK;
859 phyotg |= __SHIFTIN(OTG_SYS_FSEL_MASK, FSEL_CLKSEL_24M); 863 phyotg |= __SHIFTIN(OTG_SYS_FSEL_MASK, FSEL_CLKSEL_24M);
860 864
861 /* enable normal mode of operation */ 865 /* enable normal mode of operation */
862 phyotg &= ~(OTG_SYS_FORCESUSPEND | OTG_SYS_FORCESLEEP | 866 phyotg &= ~(OTG_SYS_FORCESUSPEND | OTG_SYS_FORCESLEEP |
863 OTG_SYS_SIDDQ_UOTG | OTG_SYS_REFCLKSEL_MASK | 867 OTG_SYS_SIDDQ_UOTG | OTG_SYS_REFCLKSEL_MASK |
864 OTG_SYS_COMMON_ON); 868 OTG_SYS_COMMON_ON);
865 869
866 /* OTG phy and link reset */ 870 /* OTG phy and link reset */
867 phyotg |= OTG_SYS_PHY0_SWRST | OTG_SYS_PHYLINK_SWRST | 871 phyotg |= OTG_SYS_PHY0_SWRST | OTG_SYS_PHYLINK_SWRST |
868 OTG_SYS_OTGDISABLE | OTG_SYS_REFCLKSEL_MASK; 872 OTG_SYS_OTGDISABLE | OTG_SYS_REFCLKSEL_MASK;
869 873
870 /* do the reset */ 874 /* do the reset */
871 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 875 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh,
872 USB_PHY_OTG_SYS, phyotg); 876 USB_PHY_OTG_SYS, phyotg);
873 DELAY(10000); 877 DELAY(10000);
874 phyotg &= ~(OTG_SYS_PHY0_SWRST | OTG_SYS_LINK_SWRST_UOTG | 878 phyotg &= ~(OTG_SYS_PHY0_SWRST | OTG_SYS_LINK_SWRST_UOTG |
875 OTG_SYS_PHYLINK_SWRST); 879 OTG_SYS_PHYLINK_SWRST);
876 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 880 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh,
877 USB_PHY_OTG_SYS, phyotg); 881 USB_PHY_OTG_SYS, phyotg);
878#endif 882#endif
879 883
880 /* enable EHCI DMA burst: */ 884 /* enable EHCI DMA burst: */
881 ehcictrl = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh, 885 ehcictrl = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh,
882 USB_PHY_HOST_EHCICTRL); 886 USB_PHY_HOST_EHCICTRL);
883 ehcictrl |= HOST_EHCICTRL_ENA_INCRXALIGN | 887 ehcictrl |= HOST_EHCICTRL_ENA_INCRXALIGN |
884 HOST_EHCICTRL_ENA_INCR4 | HOST_EHCICTRL_ENA_INCR8 | 888 HOST_EHCICTRL_ENA_INCR4 | HOST_EHCICTRL_ENA_INCR8 |
885 HOST_EHCICTRL_ENA_INCR16; 889 HOST_EHCICTRL_ENA_INCR16;
886 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 890 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh,
887 USB_PHY_HOST_EHCICTRL, ehcictrl); 891 USB_PHY_HOST_EHCICTRL, ehcictrl);
888 892
889 /* Set OHCI suspend */ 893 /* Set OHCI suspend */
890 ohcictrl = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh, 894 ohcictrl = bus_space_read_4(&armv7_generic_bs_tag, usb2phy_bsh,
891 USB_PHY_HOST_OHCICTRL); 895 USB_PHY_HOST_OHCICTRL);
892 ohcictrl |= HOST_OHCICTRL_SUSPLGCY; 896 ohcictrl |= HOST_OHCICTRL_SUSPLGCY;
893 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh, 897 bus_space_write_4(&armv7_generic_bs_tag, usb2phy_bsh,
894 USB_PHY_HOST_OHCICTRL, ohcictrl); 898 USB_PHY_HOST_OHCICTRL, ohcictrl);
895} 899}
896 900
897 901
898static void 902static void
899exynos5422_usb2phy_enable(bus_space_handle_t usb2phy_bsh) 903exynos5422_usb2phy_enable(bus_space_handle_t usb2phy_bsh)
900{ 904{
901 aprint_error("%s not implemented\n", __func__); 905 aprint_error("%s not implemented\n", __func__);
902} 906}
903#endif 907#endif
904 908
905 909
906void 910void
907exynos_usb_phy_init(bus_space_handle_t usb2phy_bsh) 911exynos_usb_phy_init(bus_space_handle_t usb2phy_bsh)
908{ 912{
909 /* disable phy isolation */ 913 /* disable phy isolation */
910 exynos_usb2_set_isolation(false); 914 exynos_usb2_set_isolation(false);
911 915
912#ifdef EXYNOS4 916#ifdef SOC_EXYNOS4
913 exynos4_usb2phy_enable(usb2phy_bsh); 917 exynos4_usb2phy_enable(usb2phy_bsh);
914#endif 918#endif
915#ifdef EXYNOS5 919#ifdef SOC_EXYNOS5
916 if (IS_EXYNOS5410_P()) { 920 if (IS_EXYNOS5410_P()) {
917 exynos5410_usb2phy_enable(usb2phy_bsh); 921 exynos5410_usb2phy_enable(usb2phy_bsh);
918 /* TBD: USB3 phy init */ 922 /* TBD: USB3 phy init */
919 } else if (IS_EXYNOS5422_P()) { 923 } else if (IS_EXYNOS5422_P()) {
920 exynos5422_usb2phy_enable(usb2phy_bsh); 924 exynos5422_usb2phy_enable(usb2phy_bsh);
921 /* TBD: USB3 phy init */ 925 /* TBD: USB3 phy init */
922 } 926 }
923#endif 927#endif
924} 928}
925 929
926 930

cvs diff -r1.7 -r1.8 src/sys/arch/arm/samsung/Attic/exynos_sscom.c (switch to unified diff)

--- src/sys/arch/arm/samsung/Attic/exynos_sscom.c 2015/12/21 00:54:35 1.7
+++ src/sys/arch/arm/samsung/Attic/exynos_sscom.c 2017/06/10 15:13:18 1.8
@@ -1,228 +1,274 @@ @@ -1,228 +1,274 @@
1/* $NetBSD: exynos_sscom.c,v 1.7 2015/12/21 00:54:35 marty Exp $ */ 1/* $NetBSD: exynos_sscom.c,v 1.8 2017/06/10 15:13:18 jmcneill Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2014 Reinoud Zandijk 4 * Copyright (c) 2014 Reinoud Zandijk
5 * Copyright (c) 2002, 2003 Fujitsu Component Limited 5 * Copyright (c) 2002, 2003 Fujitsu Component Limited
6 * Copyright (c) 2002, 2003 Genetec Corporation 6 * Copyright (c) 2002, 2003 Genetec Corporation
7 * All rights reserved. 7 * All rights reserved.
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
11 * are met: 11 * are met:
12 * 1. Redistributions of source code must retain the above copyright 12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer. 13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright 14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the 15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution. 16 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of The Fujitsu Component Limited nor the name of 17 * 3. Neither the name of The Fujitsu Component Limited nor the name of
18 * Genetec corporation may not be used to endorse or promote products 18 * Genetec corporation may not be used to endorse or promote products
19 * derived from this software without specific prior written permission. 19 * derived from this software without specific prior written permission.
20 * 20 *
21 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC 21 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
22 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
23 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC 25 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
26 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE. 33 * SUCH DAMAGE.
34 */ 34 */
35 35
36#include <sys/cdefs.h> 36#include <sys/cdefs.h>
37__KERNEL_RCSID(0, "$NetBSD: exynos_sscom.c,v 1.7 2015/12/21 00:54:35 marty Exp $"); 37__KERNEL_RCSID(0, "$NetBSD: exynos_sscom.c,v 1.8 2017/06/10 15:13:18 jmcneill Exp $");
38 38
39#include "opt_sscom.h" 39#include "opt_sscom.h"
40#include "opt_ddb.h" 40#include "opt_ddb.h"
41#include "opt_kgdb.h" 41#include "opt_kgdb.h"
42 42
43#include <sys/param.h> 43#include <sys/param.h>
44#include <sys/systm.h> 44#include <sys/systm.h>
45#include <sys/ioctl.h> 45#include <sys/ioctl.h>
46#include <sys/select.h> 46#include <sys/select.h>
47#include <sys/tty.h> 47#include <sys/tty.h>
48#include <sys/proc.h> 48#include <sys/proc.h>
49#include <sys/conf.h> 49#include <sys/conf.h>
50#include <sys/file.h> 50#include <sys/file.h>
51#include <sys/uio.h> 51#include <sys/uio.h>
52#include <sys/kernel.h> 52#include <sys/kernel.h>
53#include <sys/syslog.h> 53#include <sys/syslog.h>
54#include <sys/types.h> 54#include <sys/types.h>
55#include <sys/device.h> 55#include <sys/device.h>
56#include <sys/malloc.h> 56#include <sys/malloc.h>
57#include <sys/timepps.h> 57#include <sys/timepps.h>
58#include <sys/vnode.h> 58#include <sys/vnode.h>
59 59
60#include <machine/intr.h> 60#include <machine/intr.h>
61#include <sys/bus.h> 61#include <sys/bus.h>
62 62
63#include <arm/samsung/sscom_reg.h> 63#include <arm/samsung/sscom_reg.h>
64#include <arm/samsung/sscom_var.h> 64#include <arm/samsung/sscom_var.h>
65#include <arm/samsung/exynos_reg.h> 65#include <arm/samsung/exynos_reg.h>
66#include <arm/samsung/exynos_var.h> 66#include <arm/samsung/exynos_var.h>
67#include <sys/termios.h> 67#include <sys/termios.h>
68 68
69#include <dev/fdt/fdtvar.h> 69#include <dev/fdt/fdtvar.h>
70 70
71#include <evbarm/exynos/platform.h> 71#include <evbarm/exynos/platform.h>
72 72
73extern int num_exynos_uarts_entries; 73extern int num_exynos_uarts_entries;
74extern int exynos_uarts[]; 74extern int exynos_uarts[];
75 75
76static int sscom_match(device_t, cfdata_t, void *); 76static int sscom_match(device_t, cfdata_t, void *);
77static void sscom_attach(device_t, device_t, void *); 77static void sscom_attach(device_t, device_t, void *);
78 78
79CFATTACH_DECL_NEW(exynos_sscom, sizeof(struct sscom_softc), sscom_match, 79CFATTACH_DECL_NEW(exynos_sscom, sizeof(struct sscom_softc), sscom_match,
80 sscom_attach, NULL, NULL); 80 sscom_attach, NULL, NULL);
81 81
 82static const char * const compatible[] = {
 83 "samsung,exynos4210-uart",
 84 NULL
 85};
 86
82static int 87static int
83sscom_match(device_t parent, cfdata_t cf, void *aux) 88sscom_match(device_t parent, cfdata_t cf, void *aux)
84{ 89{
85 const char * const compatible[] = { "samsung,exynos4210-uart", NULL }; 
86 struct fdt_attach_args * const faa = aux; 90 struct fdt_attach_args * const faa = aux;
87 91
88 return of_match_compatible(faa->faa_phandle, compatible); 92 return of_match_compatible(faa->faa_phandle, compatible);
89} 93}
90 94
91static void 95static void
92exynos_unmask_interrupts(struct sscom_softc *sc, int intbits) 96exynos_unmask_interrupts(struct sscom_softc *sc, int intbits)
93{ 97{
94 int psw = disable_interrupts(IF32_bits); 98 int psw = disable_interrupts(IF32_bits);
95 uint32_t val; 99 uint32_t val;
96 100
97 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSCOM_UINTM); 101 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSCOM_UINTM);
98 val &= ~intbits; 102 val &= ~intbits;
99 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSCOM_UINTM, val); 103 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSCOM_UINTM, val);
100 104
101 restore_interrupts(psw); 105 restore_interrupts(psw);
102} 106}
103 107
104static void 108static void
105exynos_mask_interrupts(struct sscom_softc *sc, int intbits) 109exynos_mask_interrupts(struct sscom_softc *sc, int intbits)
106{ 110{
107 int psw = disable_interrupts(IF32_bits); 111 int psw = disable_interrupts(IF32_bits);
108 uint32_t val; 112 uint32_t val;
109 113
110 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSCOM_UINTM); 114 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSCOM_UINTM);
111 val |= intbits; 115 val |= intbits;
112 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSCOM_UINTM, val); 116 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSCOM_UINTM, val);
113 117
114 restore_interrupts(psw); 118 restore_interrupts(psw);
115} 119}
116 120
117static void 121static void
118exynos_change_txrx_interrupts(struct sscom_softc *sc, bool unmask_p, 122exynos_change_txrx_interrupts(struct sscom_softc *sc, bool unmask_p,
119 u_int flags) 123 u_int flags)
120{ 124{
121 int intbits = 0; 125 int intbits = 0;
122 if (flags & SSCOM_HW_RXINT) 126 if (flags & SSCOM_HW_RXINT)
123 intbits |= UINT_RXD; 127 intbits |= UINT_RXD;
124 if (flags & SSCOM_HW_TXINT) 128 if (flags & SSCOM_HW_TXINT)
125 intbits |= UINT_TXD; 129 intbits |= UINT_TXD;
126 if (unmask_p) { 130 if (unmask_p) {
127 exynos_unmask_interrupts(sc, intbits); 131 exynos_unmask_interrupts(sc, intbits);
128 } else { 132 } else {
129 exynos_mask_interrupts(sc, intbits); 133 exynos_mask_interrupts(sc, intbits);
130 } 134 }
131} 135}
132 136
133static void 137static void
134exynos_clear_interrupts(struct sscom_softc *sc, u_int flags) 138exynos_clear_interrupts(struct sscom_softc *sc, u_int flags)
135{ 139{
136 uint32_t val = 0; 140 uint32_t val = 0;
137 141
138 if (flags & SSCOM_HW_RXINT) 142 if (flags & SSCOM_HW_RXINT)
139 val |= UINT_RXD; 143 val |= UINT_RXD;
140 if (flags & SSCOM_HW_TXINT) 144 if (flags & SSCOM_HW_TXINT)
141 val |= UINT_TXD; 145 val |= UINT_TXD;
142 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSCOM_UINTP, val); 146 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSCOM_UINTP, val);
143} 147}
144 148
145static void 149static void
146sscom_attach(device_t parent, device_t self, void *aux) 150sscom_attach(device_t parent, device_t self, void *aux)
147{ 151{
148 struct sscom_softc *sc = device_private(self); 152 struct sscom_softc *sc = device_private(self);
149 struct fdt_attach_args *faa = aux; 153 struct fdt_attach_args *faa = aux;
150 int unit = -1; 154 const int phandle = faa->faa_phandle;
 155 bus_space_tag_t bst = faa->faa_bst;
151 bus_space_handle_t bsh; 156 bus_space_handle_t bsh;
152 bus_space_tag_t bst; 157 struct clk *clk_uart, *clk_uart_baud0;
153 bus_addr_t addr; 158 bus_addr_t addr;
154 bus_size_t size; 159 bus_size_t size;
155 int error; 
156 int i; 
157 160
158 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 161 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
159 aprint_error(": couldn't get registers\n"); 162 aprint_error(": couldn't get registers\n");
160 return; 163 return;
161 } 164 }
162 /* unit is required for the sscom driver, which desperately 165
163 * needs to be rewritten. For now, this hack gets the answer. 166 if (bus_space_map(bst, addr, size, 0, &bsh) != 0) {
164 * MJF: FIX ME 167 aprint_error(": couldn't map registers\n");
165 */ 168 return;
166 for (i = 1; i < num_exynos_uarts_entries; i += 2) 169 }
167 if (EXYNOS_CORE_PBASE + exynos_uarts[i] == addr) 170
168 break; 171 clk_uart = fdtbus_clock_get(phandle, "uart");
169 unit = exynos_uarts[i-1]; 172 clk_uart_baud0 = fdtbus_clock_get(phandle, "clk_uart_baud0");
 173 if (clk_uart == NULL || clk_uart_baud0 == NULL) {
 174 aprint_error(": couldn't get clocks\n");
 175 return;
 176 }
 177 if (clk_enable(clk_uart) != 0 || clk_enable(clk_uart_baud0) != 0) {
 178 aprint_error(": couldn't enable clocks\n");
 179 return;
 180 }
170 181
171 sc->sc_dev = self; 182 sc->sc_dev = self;
172 sc->sc_iot = bst = faa->faa_bst; 183 sc->sc_iot = bst = faa->faa_bst;
173 sc->sc_ioh = exynos_uarts[i] + EXYNOS_CORE_VBASE; 184 sc->sc_ioh = bsh;
174 sc->sc_unit = unit; 185 sc->sc_unit = phandle;
175 sc->sc_frequency = EXYNOS_UART_FREQ; 186 sc->sc_frequency = clk_get_rate(clk_uart);
176 187
177 sc->sc_change_txrx_interrupts = exynos_change_txrx_interrupts; 188 sc->sc_change_txrx_interrupts = exynos_change_txrx_interrupts;
178 sc->sc_clear_interrupts = exynos_clear_interrupts; 189 sc->sc_clear_interrupts = exynos_clear_interrupts;
179 190
180 /* not used here, but do initialise */ 191 /* not used here, but do initialise */
181 sc->sc_rx_irqno = 0; 192 sc->sc_rx_irqno = 0;
182 sc->sc_tx_irqno = 0; 193 sc->sc_tx_irqno = 0;
183 194
184 if (!sscom_is_console(sc->sc_iot, unit, &sc->sc_ioh)) { 195 if (sscom_is_console(sc->sc_iot, phandle, &sc->sc_ioh))
185 error = bus_space_map(bst, addr, size, 0, &bsh); 196 aprint_normal(" (console)");
186 if (error) { 
187 aprint_error(": couldn't map %#llx: %d\n", 
188 (uint64_t)addr, error); 
189 return; 
190 } 
191 sc->sc_ioh = bsh; 
192 } else { 
193 aprint_normal(" (console) "); 
194 } 
195 197
196 aprint_normal("\n"); 198 aprint_normal("\n");
197 199
198#if 0 200 void *ih = fdtbus_intr_establish(phandle, 0, IPL_SERIAL,
199 void *ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_SERIAL, 
200 FDT_INTR_MPSAFE, sscomintr, sc); 201 FDT_INTR_MPSAFE, sscomintr, sc);
201 if (ih == NULL) 202 if (ih == NULL)
202 aprint_error_dev(self, "failed to establish interrupt\n"); 203 aprint_error_dev(self, "failed to establish interrupt\n");
203#endif 
204 204
205 sscom_attach_subr(sc); 205 sscom_attach_subr(sc);
206 206
207} 207}
208 208
209 209
210#if 0 210#if 0
211int 211int
212exynos_sscom_cnattach(bus_space_tag_t iot, int unit, int rate, 212exynos_sscom_cnattach(bus_space_tag_t iot, int unit, int rate,
213 int frequency, tcflag_t cflag) 213 int frequency, tcflag_t cflag)
214{ 214{
215 return sscom_cnattach(iot, exynos_uart_config + unit, 215 return sscom_cnattach(iot, exynos_uart_config + unit,
216 rate, frequency, cflag); 216 rate, frequency, cflag);
217} 217}
218 218
219#ifdef KGDB 219#ifdef KGDB
220int 220int
221exynos_sscom_kgdb_attach(bus_space_tag_t iot, int unit, int rate, 221exynos_sscom_kgdb_attach(bus_space_tag_t iot, int unit, int rate,
222 int frequency, tcflag_t cflag) 222 int frequency, tcflag_t cflag)
223{ 223{
224 return sscom_kgdb_attach(iot, exynos_uart_config + unit, 224 return sscom_kgdb_attach(iot, exynos_uart_config + unit,
225 rate, frequency, cflag); 225 rate, frequency, cflag);
226} 226}
227#endif /* KGDB */ 227#endif /* KGDB */
228#endif 228#endif
 229
 230
 231/*
 232 * Console support
 233 */
 234
 235static int
 236exynos_sscom_console_match(int phandle)
 237{
 238 return of_match_compatible(phandle, compatible);
 239}
 240
 241static void
 242exynos_sscom_console_consinit(struct fdt_attach_args *faa, u_int uart_freq)
 243{
 244 const struct sscom_uart_info info = {
 245 .iobase = 0, /* Offset from bsh */
 246 .unit = faa->faa_phandle
 247 };
 248 const int phandle = faa->faa_phandle;
 249 bus_space_tag_t bst = faa->faa_bst;
 250 bus_space_handle_t bsh;
 251 bus_addr_t addr;
 252 bus_size_t size;
 253 tcflag_t flags;
 254 int speed;
 255
 256 fdtbus_get_reg(phandle, 0, &addr, &size);
 257 speed = fdtbus_get_stdout_speed();
 258 if (speed < 0)
 259 speed = 115200; /* default */
 260 flags = fdtbus_get_stdout_flags();
 261
 262 if (bus_space_map(bst, addr, size, 0, &bsh) != 0)
 263 panic("cannot map console UART");
 264
 265 if (sscom_cnattach(bst, bsh, &info, speed, uart_freq, flags) != 0)
 266 panic("cannot attach console UART");
 267}
 268
 269static const struct fdt_console exynos_sscom_console = {
 270 .match = exynos_sscom_console_match,
 271 .consinit = exynos_sscom_console_consinit,
 272};
 273
 274FDT_CONSOLE(exynos_sscom, &exynos_sscom_console);

cvs diff -r1.21 -r1.22 src/sys/arch/arm/samsung/files.exynos (switch to unified diff)

--- src/sys/arch/arm/samsung/files.exynos 2016/01/03 04:10:58 1.21
+++ src/sys/arch/arm/samsung/files.exynos 2017/06/10 15:13:18 1.22
@@ -1,127 +1,122 @@ @@ -1,127 +1,122 @@
1# $NetBSD: files.exynos,v 1.21 2016/01/03 04:10:58 marty Exp $ 1# $NetBSD: files.exynos,v 1.22 2017/06/10 15:13:18 jmcneill Exp $
2# 2#
3# Configuration info for Samsung Exynos SoC ARM Peripherals 3# Configuration info for Samsung Exynos SoC ARM Peripherals
4# 4#
5 5
6include "arch/arm/pic/files.pic" 6include "arch/arm/pic/files.pic"
7include "arch/arm/cortex/files.cortex" 7include "arch/arm/cortex/files.cortex"
8 8
9defflag opt_cpuoptions.h ARM_TRUSTZONE_FIRMWARE 9defflag opt_cpuoptions.h ARM_TRUSTZONE_FIRMWARE
10 10
11file arch/arm/arm32/arm32_boot.c 11file arch/arm/arm32/arm32_boot.c
12file arch/arm/arm32/arm32_kvminit.c 12file arch/arm/arm32/arm32_kvminit.c
13file arch/arm/arm32/arm32_reboot.c 13file arch/arm/arm32/arm32_reboot.c
14file arch/arm/arm32/irq_dispatch.S 14file arch/arm/arm32/irq_dispatch.S
15file arch/arm/arm32/armv7_generic_space.c 15file arch/arm/arm32/armv7_generic_space.c
 16file arch/arm/arm32/armv7_generic_dma.c
16file arch/arm/arm/bus_space_a4x.S 17file arch/arm/arm/bus_space_a4x.S
17 18
18file arch/arm/samsung/exynos_soc.c 19file arch/arm/samsung/exynos_soc.c
19#file arch/arm/samsung/exynos_space.c 
20file arch/arm/samsung/exynos_smc.S arm_trustzone_firmware 20file arch/arm/samsung/exynos_smc.S arm_trustzone_firmware
21 21
22# Console parameters 22# Console parameters
23defparam opt_exynos.h CONADDR 23defparam opt_exynos.h CONADDR
24defparam opt_exynos.h CONSPEED 24defparam opt_exynos.h CONSPEED
25defparam opt_exynos.h CONMODE 25defparam opt_exynos.h CONMODE
26 26
27# Memory size in megabytes 27# Memory size in megabytes
28defparam opt_exynos.h MEMSIZE 28defparam opt_exynos.h MEMSIZE
29defparam opt_exynos.h EXYNOS_WDT_DEFAULT_PERIOD 29defparam opt_exynos.h EXYNOS_WDT_DEFAULT_PERIOD
30defflag opt_exynos.h EXYNOS_CONSOLE_EARLY 30defflag opt_exynos.h EXYNOS_CONSOLE_EARLY
31 31
32# 32#
33defflag opt_exynos.h EXYNOS4: CPU_CORTEXA9 33defflag opt_exynos.h SOC_EXYNOS4: CPU_CORTEXA9
34defflag opt_exynos.h EXYNOS4120: EXYNOS4 34defflag opt_exynos.h SOC_EXYNOS4120: SOC_EXYNOS4
35defflag opt_exynos.h EXYNOS4212: EXYNOS4 35defflag opt_exynos.h SOC_EXYNOS4212: SOC_EXYNOS4
36defflag opt_exynos.h EXYNOS4412: EXYNOS4 36defflag opt_exynos.h SOC_EXYNOS4412: SOC_EXYNOS4
37defflag opt_exynos.h EXYNOS4412P: EXYNOS4 37defflag opt_exynos.h SOC_EXYNOS4412P: SOC_EXYNOS4
38defflag opt_exynos.h EXYNOS5: CPU_CORTEXA15 38defflag opt_exynos.h SOC_EXYNOS5: CPU_CORTEXA15
39defflag opt_exynos.h EXYNOS5250: EXYNOS5 39defflag opt_exynos.h SOC_EXYNOS5250: SOC_EXYNOS5
40defflag opt_exynos.h EXYNOS5260: EXYNOS5 40defflag opt_exynos.h SOC_EXYNOS5260: SOC_EXYNOS5
41defflag opt_exynos.h EXYNOS5410: EXYNOS5 41defflag opt_exynos.h SOC_EXYNOS5410: SOC_EXYNOS5
42defflag opt_exynos.h EXYNOS5420: EXYNOS5 42defflag opt_exynos.h SOC_EXYNOS5420: SOC_EXYNOS5
43defflag opt_exynos.h EXYNOS5440: EXYNOS5 43defflag opt_exynos.h SOC_EXYNOS5440: SOC_EXYNOS5
44defflag opt_exynos.h EXYNOS5422: EXYNOS5 44defflag opt_exynos.h SOC_EXYNOS5422: SOC_EXYNOS5
45 45
46# On-board I/O 46file arch/arm/samsung/exynos_platform.c soc_exynos5
47device exynosfdt : bus_space_generic, fdtbus 
48attach exynosfdt at mainbus with exynos_fdt 
49file arch/arm/samsung/exynos_fdt.c exynos_fdt 
50 47
51# Interrupt combiner 48# Interrupt combiner
52device exyointr 49device exyointr
53attach exyointr at fdt with exynos_intr 50attach exyointr at fdt with exynos_intr
54file arch/arm/samsung/exynos_combiner.c exynos_intr 51file arch/arm/samsung/exynos_combiner.c exynos_intr
55 52
56# CHIP ID register 53# CHIP ID register
57device chipid : fdtbus 54device chipid : fdtbus
58attach chipid at fdt with exynos_chipid 55attach chipid at fdt with exynos_chipid
59file arch/arm/samsung/exynos_chipid.c exynos_chipid 56file arch/arm/samsung/exynos_chipid.c exynos_chipid
60 57
61# SYSMMU 58# SYSMMU
62device sysmmu : fdtbus 59device sysmmu : fdtbus
63attach sysmmu at fdt with exynos_sysmmu 60attach sysmmu at fdt with exynos_sysmmu
64file arch/arm/samsung/exynos_sysmmu.c exynos_sysmmu 61file arch/arm/samsung/exynos_sysmmu.c exynos_sysmmu
65 62
66# real time clock 63# real time clock
67device exyortc : ftdbus 64device exyortc : ftdbus
68attach exyortc at fdt with exynos_rtc 65attach exyortc at fdt with exynos_rtc
69file arch/arm/samsung/exynos_rtc.c exynos_rtc 66file arch/arm/samsung/exynos_rtc.c exynos_rtc
70 67
71# Multi Core timer 68# Multi Core timer
72device mct : ftdbus 69device mct : ftdbus
73attach mct at fdt with exyo_mct 70attach mct at fdt with exyo_mct
74file arch/arm/samsung/mct.c exyo_mct 71file arch/arm/samsung/mct.c exyo_mct
75 72
76# Watchdog 73# Watchdog
77device exyowdt : sysmon_wdog 74device exyowdt : sysmon_wdog
78attach exyowdt at fdt with exynos_wdt 75attach exyowdt at fdt with exynos_wdt
79file arch/arm/samsung/exynos_wdt.c exynos_wdt needs-flag 76file arch/arm/samsung/exynos_wdt.c exynos_wdt needs-flag
80 77
81# UARTs 78# UARTs
82device sscom { } : bus_space_generic 79device sscom { } : bus_space_generic
83attach sscom at fdt with exynos_sscom 80attach sscom at fdt with exynos_sscom
84file arch/arm/samsung/sscom.c sscom needs-flag 81file arch/arm/samsung/sscom.c sscom needs-flag
85file arch/arm/samsung/exynos_sscom.c exynos_sscom  82file arch/arm/samsung/exynos_sscom.c exynos_sscom
86defflag opt_sscom.h SSCOM0CONSOLE SSCOM1CONSOLE 83defflag opt_sscom.h SSCOM0CONSOLE SSCOM1CONSOLE
87defparam opt_sscom.h SSCOM_FREQ  84defparam opt_sscom.h SSCOM_FREQ
88 85
89# PINCTL 86# PINCTL
90device exyopctl : gpiobus 87device exyopctl : gpiobus
91attach exyopctl at fdt with exynos_pinctrl 88attach exyopctl at fdt with exynos_pinctrl
92file arch/arm/samsung/exynos_pinctrl.c exynos_pinctrl needs-flag 89file arch/arm/samsung/exynos_pinctrl.c exynos_pinctrl needs-flag
93file arch/arm/samsung/exynos_gpio.c exynos_pinctrl needs-flag 90file arch/arm/samsung/exynos_gpio.c exynos_pinctrl needs-flag
94 91
95# USB2 phy 92# USB2 phy
96device exyousbphy 93device exyousbphy
97attach exyousbphy at fdt with exynos_usbphy 94attach exyousbphy at fdt with exynos_usbphy
98file arch/arm/samsung/exynos_usbphy.c exynos_usbphy 95file arch/arm/samsung/exynos_usbphy.c exynos_usbphy
99 96
100# USB2 Host Controller (OHCI) 97# USB2 Host Controller (OHCI)
101attach ohci at fdt with exynos_ohci 98attach ohci at fdt with exynos_ohci
102file arch/arm/samsung/exynos_ohci.c exynos_ohci 99file arch/arm/samsung/exynos_ohci.c exynos_ohci
103 100
104#USB 2 Host Controller (EHCI) 101#USB 2 Host Controller (EHCI)
105attach ehci at fdt with exynos_ehci 102attach ehci at fdt with exynos_ehci
106file arch/arm/samsung/exynos_ehci.c exynos_ehci 103file arch/arm/samsung/exynos_ehci.c exynos_ehci
107 104
108# USB3 Host Controller (xHCI) 105# USB3 Host Controller (xHCI)
109device exyousb : fdtbus 106device exyousb : fdtbus
110attach exyousb at fdt with exynos_usb 107attach exyousb at fdt with exynos_usb
111attach xhci at fdt 108attach xhci at fdt
112file arch/arm/samsung/exynos_usb3.c exynos_usb 109file arch/arm/samsung/exynos_usb3.c exynos_usb
113 110
114# SD/MMC Host Controller 111# SD/MMC Host Controller
115attach dwcmmc at fdt with exynos_dwcmmc 112attach dwcmmc at fdt with exynos_dwcmmc
116file arch/arm/samsung/exynos_dwcmmc.c exynos_dwcmmc 113file arch/arm/samsung/exynos_dwcmmc.c exynos_dwcmmc
117 114
118# I2C support, bitbanging through GPIO 115# I2C support, bitbanging through GPIO
119device exyoi2c: i2cbus, i2c_bitbang 116device exyoi2c: i2cbus, i2c_bitbang
120attach exyoi2c at fdt with exynos_i2c 117attach exyoi2c at fdt with exynos_i2c
121file arch/arm/samsung/exynos_i2c.c exynos_i2c needs-flag 118file arch/arm/samsung/exynos_i2c.c exynos_i2c needs-flag
122 119
123file arch/arm/samsung/exynos5422_dma.c 
124 
125device exy5422clk: clk 120device exy5422clk: clk
126attach exy5422clk at fdt with exynos5422_clock 121attach exy5422clk at fdt with exynos5422_clock
127file arch/arm/samsung/exynos5422_clock.c exynos5422_clock 122file arch/arm/samsung/exynos5422_clock.c exynos5422_clock

cvs diff -r1.8 -r1.9 src/sys/arch/arm/samsung/Attic/sscom.c (switch to unified diff)

--- src/sys/arch/arm/samsung/Attic/sscom.c 2015/04/13 21:18:41 1.8
+++ src/sys/arch/arm/samsung/Attic/sscom.c 2017/06/10 15:13:18 1.9
@@ -1,2120 +1,2106 @@ @@ -1,2120 +1,2106 @@
1/* $NetBSD: sscom.c,v 1.8 2015/04/13 21:18:41 riastradh Exp $ */ 1/* $NetBSD: sscom.c,v 1.9 2017/06/10 15:13:18 jmcneill Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2002, 2003 Fujitsu Component Limited 4 * Copyright (c) 2002, 2003 Fujitsu Component Limited
5 * Copyright (c) 2002, 2003 Genetec Corporation 5 * Copyright (c) 2002, 2003 Genetec Corporation
6 * All rights reserved. 6 * All rights reserved.
7 * 7 *
8 * Redistribution and use in source and binary forms, with or without 8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions 9 * modification, are permitted provided that the following conditions
10 * are met: 10 * are met:
11 * 1. Redistributions of source code must retain the above copyright 11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer. 12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright 13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the 14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution. 15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of The Fujitsu Component Limited nor the name of 16 * 3. Neither the name of The Fujitsu Component Limited nor the name of
17 * Genetec corporation may not be used to endorse or promote products 17 * Genetec corporation may not be used to endorse or promote products
18 * derived from this software without specific prior written permission. 18 * derived from this software without specific prior written permission.
19 * 19 *
20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC 20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC 24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE. 32 * SUCH DAMAGE.
33 */ 33 */
34 34
35/*- 35/*-
36 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 36 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
37 * All rights reserved. 37 * All rights reserved.
38 * 38 *
39 * This code is derived from software contributed to The NetBSD Foundation 39 * This code is derived from software contributed to The NetBSD Foundation
40 * by Charles M. Hannum. 40 * by Charles M. Hannum.
41 * 41 *
42 * Redistribution and use in source and binary forms, with or without 42 * Redistribution and use in source and binary forms, with or without
43 * modification, are permitted provided that the following conditions 43 * modification, are permitted provided that the following conditions
44 * are met: 44 * are met:
45 * 1. Redistributions of source code must retain the above copyright 45 * 1. Redistributions of source code must retain the above copyright
46 * notice, this list of conditions and the following disclaimer. 46 * notice, this list of conditions and the following disclaimer.
47 * 2. Redistributions in binary form must reproduce the above copyright 47 * 2. Redistributions in binary form must reproduce the above copyright
48 * notice, this list of conditions and the following disclaimer in the 48 * notice, this list of conditions and the following disclaimer in the
49 * documentation and/or other materials provided with the distribution. 49 * documentation and/or other materials provided with the distribution.
50 * 50 *
51 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 51 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
52 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 52 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
53 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 53 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
54 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 54 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
55 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
56 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
57 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
58 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
59 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
60 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 60 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
61 * POSSIBILITY OF SUCH DAMAGE. 61 * POSSIBILITY OF SUCH DAMAGE.
62 */ 62 */
63 63
64/* 64/*
65 * Copyright (c) 1991 The Regents of the University of California. 65 * Copyright (c) 1991 The Regents of the University of California.
66 * All rights reserved. 66 * All rights reserved.
67 * 67 *
68 * Redistribution and use in source and binary forms, with or without 68 * Redistribution and use in source and binary forms, with or without
69 * modification, are permitted provided that the following conditions 69 * modification, are permitted provided that the following conditions
70 * are met: 70 * are met:
71 * 1. Redistributions of source code must retain the above copyright 71 * 1. Redistributions of source code must retain the above copyright
72 * notice, this list of conditions and the following disclaimer. 72 * notice, this list of conditions and the following disclaimer.
73 * 2. Redistributions in binary form must reproduce the above copyright 73 * 2. Redistributions in binary form must reproduce the above copyright
74 * notice, this list of conditions and the following disclaimer in the 74 * notice, this list of conditions and the following disclaimer in the
75 * documentation and/or other materials provided with the distribution. 75 * documentation and/or other materials provided with the distribution.
76 * 3. Neither the name of the University nor the names of its contributors 76 * 3. Neither the name of the University nor the names of its contributors
77 * may be used to endorse or promote products derived from this software 77 * may be used to endorse or promote products derived from this software
78 * without specific prior written permission. 78 * without specific prior written permission.
79 * 79 *
80 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 80 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
81 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 81 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
82 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 82 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
83 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 83 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
84 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 84 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
85 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 85 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
86 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 86 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
87 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 87 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
88 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 88 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
89 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 89 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
90 * SUCH DAMAGE. 90 * SUCH DAMAGE.
91 * 91 *
92 * @(#)com.c 7.5 (Berkeley) 5/16/91 92 * @(#)com.c 7.5 (Berkeley) 5/16/91
93 */ 93 */
94 94
95/* 95/*
96 * Support integrated UARTs of Samsung S3C2800/2400X/2410X 96 * Support integrated UARTs of Samsung S3C2800/2400X/2410X
97 * Derived from sys/dev/ic/com.c 97 * Derived from sys/dev/ic/com.c
98 */ 98 */
99 99
100#include <sys/cdefs.h> 100#include <sys/cdefs.h>
101__KERNEL_RCSID(0, "$NetBSD: sscom.c,v 1.8 2015/04/13 21:18:41 riastradh Exp $"); 101__KERNEL_RCSID(0, "$NetBSD: sscom.c,v 1.9 2017/06/10 15:13:18 jmcneill Exp $");
102 102
103#include "opt_sscom.h" 103#include "opt_sscom.h"
104#include "opt_ddb.h" 104#include "opt_ddb.h"
105#include "opt_kgdb.h" 105#include "opt_kgdb.h"
106#include "opt_multiprocessor.h" 106#include "opt_multiprocessor.h"
107#include "opt_lockdebug.h" 107#include "opt_lockdebug.h"
108 108
109#ifdef RND_COM 109#ifdef RND_COM
110#include <sys/rndsource.h> 110#include <sys/rndsource.h>
111#endif 111#endif
112 112
113/* 113/*
114 * Override cnmagic(9) macro before including <sys/systm.h>. 114 * Override cnmagic(9) macro before including <sys/systm.h>.
115 * We need to know if cn_check_magic triggered debugger, so set a flag. 115 * We need to know if cn_check_magic triggered debugger, so set a flag.
116 * Callers of cn_check_magic must declare int cn_trapped = 0; 116 * Callers of cn_check_magic must declare int cn_trapped = 0;
117 * XXX: this is *ugly*! 117 * XXX: this is *ugly*!
118 */ 118 */
119#define cn_trap() \ 119#define cn_trap() \
120 do { \ 120 do { \
121 console_debugger(); \ 121 console_debugger(); \
122 cn_trapped = 1; \ 122 cn_trapped = 1; \
123 } while (/* CONSTCOND */ 0) 123 } while (/* CONSTCOND */ 0)
124 124
125#include <sys/param.h> 125#include <sys/param.h>
126#include <sys/systm.h> 126#include <sys/systm.h>
127#include <sys/ioctl.h> 127#include <sys/ioctl.h>
128#include <sys/select.h> 128#include <sys/select.h>
129#include <sys/tty.h> 129#include <sys/tty.h>
130#include <sys/proc.h> 130#include <sys/proc.h>
131#include <sys/conf.h> 131#include <sys/conf.h>
132#include <sys/file.h> 132#include <sys/file.h>
133#include <sys/uio.h> 133#include <sys/uio.h>
134#include <sys/kernel.h> 134#include <sys/kernel.h>
135#include <sys/syslog.h> 135#include <sys/syslog.h>
136#include <sys/types.h> 136#include <sys/types.h>
137#include <sys/device.h> 137#include <sys/device.h>
138#include <sys/malloc.h> 138#include <sys/malloc.h>
139#include <sys/timepps.h> 139#include <sys/timepps.h>
140#include <sys/vnode.h> 140#include <sys/vnode.h>
141#include <sys/kauth.h> 141#include <sys/kauth.h>
142#include <sys/intr.h> 142#include <sys/intr.h>
143#include <sys/bus.h> 143#include <sys/bus.h>
144#include <sys/mutex.h> 144#include <sys/mutex.h>
145 145
146#include <arm/samsung/sscom_reg.h> 146#include <arm/samsung/sscom_reg.h>
147#include <arm/samsung/sscom_var.h> 147#include <arm/samsung/sscom_var.h>
148#include <dev/cons.h> 148#include <dev/cons.h>
149 149
150dev_type_open(sscomopen); 150dev_type_open(sscomopen);
151dev_type_close(sscomclose); 151dev_type_close(sscomclose);
152dev_type_read(sscomread); 152dev_type_read(sscomread);
153dev_type_write(sscomwrite); 153dev_type_write(sscomwrite);
154dev_type_ioctl(sscomioctl); 154dev_type_ioctl(sscomioctl);
155dev_type_stop(sscomstop); 155dev_type_stop(sscomstop);
156dev_type_tty(sscomtty); 156dev_type_tty(sscomtty);
157dev_type_poll(sscompoll); 157dev_type_poll(sscompoll);
158 158
159int sscomcngetc (dev_t); 159int sscomcngetc (dev_t);
160void sscomcnputc (dev_t, int); 160void sscomcnputc (dev_t, int);
161void sscomcnpollc (dev_t, int); 161void sscomcnpollc (dev_t, int);
162 162
163#define integrate static inline 163#define integrate static inline
164void sscomsoft (void *); 164void sscomsoft (void *);
165 165
166integrate void sscom_rxsoft (struct sscom_softc *, struct tty *); 166integrate void sscom_rxsoft (struct sscom_softc *, struct tty *);
167integrate void sscom_txsoft (struct sscom_softc *, struct tty *); 167integrate void sscom_txsoft (struct sscom_softc *, struct tty *);
168integrate void sscom_stsoft (struct sscom_softc *, struct tty *); 168integrate void sscom_stsoft (struct sscom_softc *, struct tty *);
169integrate void sscom_schedrx (struct sscom_softc *); 169integrate void sscom_schedrx (struct sscom_softc *);
170static void sscom_modem(struct sscom_softc *, int); 170static void sscom_modem(struct sscom_softc *, int);
171static void sscom_break(struct sscom_softc *, int); 171static void sscom_break(struct sscom_softc *, int);
172static void sscom_iflush(struct sscom_softc *); 172static void sscom_iflush(struct sscom_softc *);
173static void sscom_hwiflow(struct sscom_softc *); 173static void sscom_hwiflow(struct sscom_softc *);
174static void sscom_loadchannelregs(struct sscom_softc *); 174static void sscom_loadchannelregs(struct sscom_softc *);
175static void tiocm_to_sscom(struct sscom_softc *, u_long, int); 175static void tiocm_to_sscom(struct sscom_softc *, u_long, int);
176static int sscom_to_tiocm(struct sscom_softc *); 176static int sscom_to_tiocm(struct sscom_softc *);
177static void tiocm_to_sscom(struct sscom_softc *, u_long, int); 177static void tiocm_to_sscom(struct sscom_softc *, u_long, int);
178static int sscom_to_tiocm(struct sscom_softc *); 178static int sscom_to_tiocm(struct sscom_softc *);
179static void sscom_iflush(struct sscom_softc *); 179static void sscom_iflush(struct sscom_softc *);
180 180
181static int sscomhwiflow(struct tty *tp, int block); 181static int sscomhwiflow(struct tty *tp, int block);
182#if defined(KGDB) || \ 
183 defined(SSCOM0CONSOLE) || defined(SSCOM1CONSOLE) || \ 
184 defined(SSCOM2CONSOLE) || defined(SSCOM3CONSOLE) 
185static int sscom_init(bus_space_tag_t, bus_space_handle_t, 182static int sscom_init(bus_space_tag_t, bus_space_handle_t,
186 const struct sscom_uart_info *, 183 const struct sscom_uart_info *,
187 int, int, tcflag_t, bus_space_handle_t *); 184 int, int, tcflag_t, bus_space_handle_t *);
188#endif 
189 185
190extern struct cfdriver sscom_cd; 186extern struct cfdriver sscom_cd;
191 187
192const struct cdevsw sscom_cdevsw = { 188const struct cdevsw sscom_cdevsw = {
193 .d_open = sscomopen, 189 .d_open = sscomopen,
194 .d_close = sscomclose, 190 .d_close = sscomclose,
195 .d_read = sscomread, 191 .d_read = sscomread,
196 .d_write = sscomwrite, 192 .d_write = sscomwrite,
197 .d_ioctl = sscomioctl, 193 .d_ioctl = sscomioctl,
198 .d_stop = sscomstop, 194 .d_stop = sscomstop,
199 .d_tty = sscomtty, 195 .d_tty = sscomtty,
200 .d_poll = sscompoll, 196 .d_poll = sscompoll,
201 .d_mmap = nommap, 197 .d_mmap = nommap,
202 .d_kqfilter = ttykqfilter, 198 .d_kqfilter = ttykqfilter,
203 .d_flag = D_TTY 199 .d_flag = D_TTY
204}; 200};
205 201
206/* 202/*
207 * Make this an option variable one can patch. 203 * Make this an option variable one can patch.
208 * But be warned: this must be a power of 2! 204 * But be warned: this must be a power of 2!
209 */ 205 */
210u_int sscom_rbuf_size = SSCOM_RING_SIZE; 206u_int sscom_rbuf_size = SSCOM_RING_SIZE;
211 207
212/* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 208/* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */
213u_int sscom_rbuf_hiwat = (SSCOM_RING_SIZE * 1) / 4; 209u_int sscom_rbuf_hiwat = (SSCOM_RING_SIZE * 1) / 4;
214u_int sscom_rbuf_lowat = (SSCOM_RING_SIZE * 3) / 4; 210u_int sscom_rbuf_lowat = (SSCOM_RING_SIZE * 3) / 4;
215 211
216static int sscomconsunit = -1; 212static int sscomconsunit = -1;
217static bus_space_tag_t sscomconstag; 213static bus_space_tag_t sscomconstag;
218static bus_space_handle_t sscomconsioh; 214static bus_space_handle_t sscomconsioh;
219static int sscomconsattached; 215static int sscomconsattached;
220static int sscomconsrate; 216static int sscomconsrate;
221static tcflag_t sscomconscflag; 217static tcflag_t sscomconscflag;
222static struct cnm_state sscom_cnm_state; 218static struct cnm_state sscom_cnm_state;
223 219
224#ifdef KGDB 220#ifdef KGDB
225#include <sys/kgdb.h> 221#include <sys/kgdb.h>
226 222
227static int sscom_kgdb_unit = -1; 223static int sscom_kgdb_unit = -1;
228static bus_space_tag_t sscom_kgdb_iot; 224static bus_space_tag_t sscom_kgdb_iot;
229static bus_space_handle_t sscom_kgdb_ioh; 225static bus_space_handle_t sscom_kgdb_ioh;
230static int sscom_kgdb_attached; 226static int sscom_kgdb_attached;
231 227
232int sscom_kgdb_getc (void *); 228int sscom_kgdb_getc (void *);
233void sscom_kgdb_putc (void *, int); 229void sscom_kgdb_putc (void *, int);
234#endif /* KGDB */ 230#endif /* KGDB */
235 231
236#define SSCOMUNIT_MASK 0x7f 232#define SSCOMUNIT_MASK 0x7f
237#define SSCOMDIALOUT_MASK 0x80 233#define SSCOMDIALOUT_MASK 0x80
238 234
239#define SSCOMUNIT(x) (minor(x) & SSCOMUNIT_MASK) 235#define SSCOMUNIT(x) (minor(x) & SSCOMUNIT_MASK)
240#define SSCOMDIALOUT(x) (minor(x) & SSCOMDIALOUT_MASK) 236#define SSCOMDIALOUT(x) (minor(x) & SSCOMDIALOUT_MASK)
241 237
242#if 0 238#if 0
243#define SSCOM_ISALIVE(sc) ((sc)->enabled != 0 && \ 239#define SSCOM_ISALIVE(sc) ((sc)->enabled != 0 && \
244 device_is_active(&(sc)->sc_dev)) 240 device_is_active(&(sc)->sc_dev))
245#else 241#else
246#define SSCOM_ISALIVE(sc) device_is_active((sc)->sc_dev) 242#define SSCOM_ISALIVE(sc) device_is_active((sc)->sc_dev)
247#endif 243#endif
248 244
249#define BR BUS_SPACE_BARRIER_READ 245#define BR BUS_SPACE_BARRIER_READ
250#define BW BUS_SPACE_BARRIER_WRITE 246#define BW BUS_SPACE_BARRIER_WRITE
251#define SSCOM_BARRIER(t, h, f) /* no-op */ 247#define SSCOM_BARRIER(t, h, f) /* no-op */
252 248
253#if (defined(MULTIPROCESSOR) || defined(LOCKDEBUG)) && defined(SSCOM_MPLOCK) 249#if (defined(MULTIPROCESSOR) || defined(LOCKDEBUG)) && defined(SSCOM_MPLOCK)
254 250
255#define SSCOM_LOCK(sc) mutex_enter((sc)->sc_lock) 251#define SSCOM_LOCK(sc) mutex_enter((sc)->sc_lock)
256#define SSCOM_UNLOCK(sc) mutex_exit((sc)->sc_lock) 252#define SSCOM_UNLOCK(sc) mutex_exit((sc)->sc_lock)
257 253
258#else 254#else
259 255
260#define SSCOM_LOCK(sc) 256#define SSCOM_LOCK(sc)
261#define SSCOM_UNLOCK(sc) 257#define SSCOM_UNLOCK(sc)
262 258
263#endif 259#endif
264 260
265#ifndef SSCOM_TOLERANCE 261#ifndef SSCOM_TOLERANCE
266#define SSCOM_TOLERANCE 30 /* XXX: baud rate tolerance, in 0.1% units */ 262#define SSCOM_TOLERANCE 30 /* XXX: baud rate tolerance, in 0.1% units */
267#endif 263#endif
268 264
269/* value for UCON */ 265/* value for UCON */
270#define UCON_RXINT_MASK \ 266#define UCON_RXINT_MASK \
271 (UCON_RXMODE_MASK|UCON_ERRINT|UCON_TOINT|UCON_RXINT_TYPE) 267 (UCON_RXMODE_MASK|UCON_ERRINT|UCON_TOINT|UCON_RXINT_TYPE)
272#define UCON_RXINT_ENABLE \ 268#define UCON_RXINT_ENABLE \
273 (UCON_RXMODE_INT|UCON_ERRINT|UCON_TOINT|UCON_RXINT_TYPE_LEVEL) 269 (UCON_RXMODE_INT|UCON_ERRINT|UCON_TOINT|UCON_RXINT_TYPE_LEVEL)
274#define UCON_TXINT_MASK (UCON_TXMODE_MASK|UCON_TXINT_TYPE) 270#define UCON_TXINT_MASK (UCON_TXMODE_MASK|UCON_TXINT_TYPE)
275#define UCON_TXINT_ENABLE (UCON_TXMODE_INT|UCON_TXINT_TYPE_LEVEL) 271#define UCON_TXINT_ENABLE (UCON_TXMODE_INT|UCON_TXINT_TYPE_LEVEL)
276 272
277/* we don't want tx interrupt on debug port, but it is needed to 273/* we don't want tx interrupt on debug port, but it is needed to
278 have transmitter active */ 274 have transmitter active */
279#define UCON_DEBUGPORT (UCON_RXINT_ENABLE|UCON_TXINT_ENABLE) 275#define UCON_DEBUGPORT (UCON_RXINT_ENABLE|UCON_TXINT_ENABLE)
280 276
281 277
282static inline void 278static inline void
283__sscom_output_chunk(struct sscom_softc *sc, int ufstat) 279__sscom_output_chunk(struct sscom_softc *sc, int ufstat)
284{ 280{
285 int n, space; 281 int n, space;
286 bus_space_tag_t iot = sc->sc_iot; 282 bus_space_tag_t iot = sc->sc_iot;
287 bus_space_handle_t ioh = sc->sc_ioh; 283 bus_space_handle_t ioh = sc->sc_ioh;
288 284
289 n = sc->sc_tbc; 285 n = sc->sc_tbc;
290 space = 16 - __SHIFTOUT(ufstat, UFSTAT_TXCOUNT); 286 space = 16 - __SHIFTOUT(ufstat, UFSTAT_TXCOUNT);
291 287
292 if (n > space) 288 if (n > space)
293 n = space; 289 n = space;
294 290
295 if (n > 0) { 291 if (n > 0) {
296 bus_space_write_multi_1(iot, ioh, SSCOM_UTXH, sc->sc_tba, n); 292 bus_space_write_multi_1(iot, ioh, SSCOM_UTXH, sc->sc_tba, n);
297 sc->sc_tbc -= n; 293 sc->sc_tbc -= n;
298 sc->sc_tba += n; 294 sc->sc_tba += n;
299 } 295 }
300} 296}
301 297
302static void 298static void
303sscom_output_chunk(struct sscom_softc *sc) 299sscom_output_chunk(struct sscom_softc *sc)
304{ 300{
305 uint32_t ufstat = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSCOM_UFSTAT); 301 uint32_t ufstat = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSCOM_UFSTAT);
306 302
307 if (!(ufstat & UFSTAT_TXFULL)) 303 if (!(ufstat & UFSTAT_TXFULL))
308 __sscom_output_chunk(sc, ufstat); 304 __sscom_output_chunk(sc, ufstat);
309} 305}
310 306
311int 307int
312sscomspeed(long speed, long frequency) 308sscomspeed(long speed, long frequency)
313{ 309{
314#define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 310#define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */
315 311
316 int x, err; 312 int x, err;
317 313
318 if (speed <= 0) 314 if (speed <= 0)
319 return -1; 315 return -1;
320 x = divrnd(frequency / 16, speed); 316 x = divrnd(frequency / 16, speed);
321 if (x <= 0) 317 if (x <= 0)
322 return -1; 318 return -1;
323 err = divrnd(((quad_t)frequency) * 1000 / 16, speed * x) - 1000; 319 err = divrnd(((quad_t)frequency) * 1000 / 16, speed * x) - 1000;
324 if (err < 0) 320 if (err < 0)
325 err = -err; 321 err = -err;
326 if (err > SSCOM_TOLERANCE) 322 if (err > SSCOM_TOLERANCE)
327 return -1; 323 return -1;
328 return x-1; 324 return x-1;
329 325
330#undef divrnd 326#undef divrnd
331} 327}
332 328
333void sscomstatus (struct sscom_softc *, const char *); 329void sscomstatus (struct sscom_softc *, const char *);
334 330
335#ifdef SSCOM_DEBUG 331#ifdef SSCOM_DEBUG
336int sscom_debug = 0; 332int sscom_debug = 0;
337 333
338/* XXX not all is printed in this version XXX */ 334/* XXX not all is printed in this version XXX */
339void 335void
340sscomstatus(struct sscom_softc *sc, const char *str) 336sscomstatus(struct sscom_softc *sc, const char *str)
341{ 337{
342 struct tty *tp = sc->sc_tty; 338 struct tty *tp = sc->sc_tty;
343 int umstat = bus_space_read_1(sc->sc_iot, sc->sc_ioh, SSCOM_UMSTAT); 339 int umstat = bus_space_read_1(sc->sc_iot, sc->sc_ioh, SSCOM_UMSTAT);
344 int umcon = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSCOM_UMCON); 340 int umcon = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSCOM_UMCON);
345 341
346 printf("%s: %s %sclocal %sdcd %sts_carr_on %sdtr %stx_stopped\n", 342 printf("%s: %s %sclocal %sdcd %sts_carr_on %sdtr %stx_stopped\n",
347 device_xname(sc->sc_dev), str, 343 device_xname(sc->sc_dev), str,
348 ISSET(tp->t_cflag, CLOCAL) ? "+" : "-", 344 ISSET(tp->t_cflag, CLOCAL) ? "+" : "-",
349 "+", /* DCD */ 345 "+", /* DCD */
350 ISSET(tp->t_state, TS_CARR_ON) ? "+" : "-", 346 ISSET(tp->t_state, TS_CARR_ON) ? "+" : "-",
351 "+", /* DTR */ 347 "+", /* DTR */
352 sc->sc_tx_stopped ? "+" : "-"); 348 sc->sc_tx_stopped ? "+" : "-");
353 349
354 printf("%s: %s %scrtscts %scts %sts_ttstop %srts %xrx_flags\n", 350 printf("%s: %s %scrtscts %scts %sts_ttstop %srts %xrx_flags\n",
355 device_xname(sc->sc_dev), str, 351 device_xname(sc->sc_dev), str,
356 ISSET(tp->t_cflag, CRTSCTS) ? "+" : "-", 352 ISSET(tp->t_cflag, CRTSCTS) ? "+" : "-",
357 ISSET(umstat, UMSTAT_CTS) ? "+" : "-", 353 ISSET(umstat, UMSTAT_CTS) ? "+" : "-",
358 ISSET(tp->t_state, TS_TTSTOP) ? "+" : "-", 354 ISSET(tp->t_state, TS_TTSTOP) ? "+" : "-",
359 ISSET(umcon, UMCON_RTS) ? "+" : "-", 355 ISSET(umcon, UMCON_RTS) ? "+" : "-",
360 sc->sc_rx_flags); 356 sc->sc_rx_flags);
361} 357}
362#else 358#else
363#define sscom_debug 0 359#define sscom_debug 0
364#endif 360#endif
365 361
366static void 362static void
367sscom_enable_debugport(struct sscom_softc *sc) 363sscom_enable_debugport(struct sscom_softc *sc)
368{ 364{
369 int s; 365 int s;
370 366
371 /* Turn on line break interrupt, set carrier. */ 367 /* Turn on line break interrupt, set carrier. */
372 s = splserial(); 368 s = splserial();
373 SSCOM_LOCK(sc); 369 SSCOM_LOCK(sc);
374 sc->sc_ucon = UCON_DEBUGPORT; 370 sc->sc_ucon = UCON_DEBUGPORT;
375 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSCOM_UCON, sc->sc_ucon); 371 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSCOM_UCON, sc->sc_ucon);
376 sc->sc_umcon = UMCON_RTS|UMCON_DTR; 372 sc->sc_umcon = UMCON_RTS|UMCON_DTR;
377 sc->sc_set_modem_control(sc); 373 sc->sc_set_modem_control(sc);
378 sscom_enable_rxint(sc); 374 sscom_enable_rxint(sc);
379 sscom_disable_txint(sc); 375 sscom_disable_txint(sc);
380 SSCOM_UNLOCK(sc); 376 SSCOM_UNLOCK(sc);
381 splx(s); 377 splx(s);
382} 378}
383 379
384static void 380static void
385sscom_set_modem_control(struct sscom_softc *sc) 381sscom_set_modem_control(struct sscom_softc *sc)
386{ 382{
387 /* flob RTS */ 383 /* flob RTS */
388 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 384 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
389 SSCOM_UMCON, sc->sc_umcon & UMCON_HW_MASK); 385 SSCOM_UMCON, sc->sc_umcon & UMCON_HW_MASK);
390 /* ignore DTR */ 386 /* ignore DTR */
391} 387}
392 388
393static int 389static int
394sscom_read_modem_status(struct sscom_softc *sc) 390sscom_read_modem_status(struct sscom_softc *sc)
395{ 391{
396 int msts; 392 int msts;
397 393
398 msts = bus_space_read_1(sc->sc_iot, sc->sc_ioh, SSCOM_UMSTAT); 394 msts = bus_space_read_1(sc->sc_iot, sc->sc_ioh, SSCOM_UMSTAT);
399 395
400 /* DCD and DSR are always on */ 396 /* DCD and DSR are always on */
401 return (msts & UMSTAT_CTS) | MSTS_DCD | MSTS_DSR; 397 return (msts & UMSTAT_CTS) | MSTS_DCD | MSTS_DSR;
402} 398}
403 399
404void 400void
405sscom_attach_subr(struct sscom_softc *sc) 401sscom_attach_subr(struct sscom_softc *sc)
406{ 402{
407 int unit = sc->sc_unit; 403 int unit = sc->sc_unit;
408 bus_space_tag_t iot = sc->sc_iot; 404 bus_space_tag_t iot = sc->sc_iot;
409 bus_space_handle_t ioh = sc->sc_ioh; 405 bus_space_handle_t ioh = sc->sc_ioh;
410 struct tty *tp; 406 struct tty *tp;
411 407
412 callout_init(&sc->sc_diag_callout, 0); 408 callout_init(&sc->sc_diag_callout, 0);
413#if (defined(MULTIPROCESSOR) || defined(LOCKDEBUG)) && defined(SSCOM_MPLOCK) 409#if (defined(MULTIPROCESSOR) || defined(LOCKDEBUG)) && defined(SSCOM_MPLOCK)
414 sc->sc_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_SERIAL); 410 sc->sc_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_SERIAL);
415#endif 411#endif
416 412
417 sc->sc_ucon = UCON_RXINT_ENABLE|UCON_TXINT_ENABLE; 413 sc->sc_ucon = UCON_RXINT_ENABLE|UCON_TXINT_ENABLE;
418 414
419 /* 415 /*
420 * set default for modem control hook 416 * set default for modem control hook
421 */ 417 */
422 if (sc->sc_set_modem_control == NULL) 418 if (sc->sc_set_modem_control == NULL)
423 sc->sc_set_modem_control = sscom_set_modem_control; 419 sc->sc_set_modem_control = sscom_set_modem_control;
424 if (sc->sc_read_modem_status == NULL) 420 if (sc->sc_read_modem_status == NULL)
425 sc->sc_read_modem_status = sscom_read_modem_status; 421 sc->sc_read_modem_status = sscom_read_modem_status;
426 422
427 /* Disable interrupts before configuring the device. */ 423 /* Disable interrupts before configuring the device. */
428 KASSERT(sc->sc_change_txrx_interrupts != NULL); 424 KASSERT(sc->sc_change_txrx_interrupts != NULL);
429 KASSERT(sc->sc_clear_interrupts != NULL); 425 KASSERT(sc->sc_clear_interrupts != NULL);
430 sscom_disable_txrxint(sc); 426 sscom_disable_txrxint(sc);
431 427
432#ifdef KGDB 428#ifdef KGDB
433 /* 429 /*
434 * Allow kgdb to "take over" this port. If this is 430 * Allow kgdb to "take over" this port. If this is
435 * the kgdb device, it has exclusive use. 431 * the kgdb device, it has exclusive use.
436 */ 432 */
437 if (unit == sscom_kgdb_unit) { 433 if (unit == sscom_kgdb_unit) {
438 SET(sc->sc_hwflags, SSCOM_HW_KGDB); 434 SET(sc->sc_hwflags, SSCOM_HW_KGDB);
439 sc->sc_ucon = UCON_DEBUGPORT; 435 sc->sc_ucon = UCON_DEBUGPORT;
440 } 436 }
441#endif 437#endif
442 438
443 if (unit == sscomconsunit) { 439 if (unit == sscomconsunit) {
444 uint32_t stat; 440 uint32_t stat;
445 int timo; 441 int timo;
446 442
447 sscomconsattached = 1; 443 sscomconsattached = 1;
448 sscomconstag = iot; 444 sscomconstag = iot;
449 sscomconsioh = ioh; 445 sscomconsioh = ioh;
450 446
451 /* wait for this transmission to complete */ 447 /* wait for this transmission to complete */
452 timo = 1500000; 448 timo = 1500000;
453 do { 449 do {
454 stat = bus_space_read_4(iot, ioh, SSCOM_UTRSTAT); 450 stat = bus_space_read_4(iot, ioh, SSCOM_UTRSTAT);
455 } while ((stat & UTRSTAT_TXEMPTY) == 0 && --timo > 0); 451 } while ((stat & UTRSTAT_TXEMPTY) == 0 && --timo > 0);
456 452
457 /* Make sure the console is always "hardwired". */ 453 /* Make sure the console is always "hardwired". */
458 SET(sc->sc_hwflags, SSCOM_HW_CONSOLE); 454 SET(sc->sc_hwflags, SSCOM_HW_CONSOLE);
459 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 455 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR);
460 456
461 sc->sc_ucon = UCON_DEBUGPORT; 457 sc->sc_ucon = UCON_DEBUGPORT;
462 } 458 }
463 459
464 /* set RX/TX trigger to half values */ 460 /* set RX/TX trigger to half values */
465 bus_space_write_4(iot, ioh, SSCOM_UFCON, 461 bus_space_write_4(iot, ioh, SSCOM_UFCON,
466 __SHIFTIN(4, UFCON_TXTRIGGER) | 462 __SHIFTIN(4, UFCON_TXTRIGGER) |
467 __SHIFTIN(4, UFCON_RXTRIGGER) | 463 __SHIFTIN(4, UFCON_RXTRIGGER) |
468 UFCON_FIFO_ENABLE |  464 UFCON_FIFO_ENABLE |
469 UFCON_TXFIFO_RESET| 465 UFCON_TXFIFO_RESET|
470 UFCON_RXFIFO_RESET); 466 UFCON_RXFIFO_RESET);
471 /* tx/rx fifo reset are auto-cleared */ 467 /* tx/rx fifo reset are auto-cleared */
472 468
473 bus_space_write_4(iot, ioh, SSCOM_UCON, sc->sc_ucon); 469 bus_space_write_4(iot, ioh, SSCOM_UCON, sc->sc_ucon);
474 470
475#ifdef KGDB 471#ifdef KGDB
476 if (ISSET(sc->sc_hwflags, SSCOM_HW_KGDB)) { 472 if (ISSET(sc->sc_hwflags, SSCOM_HW_KGDB)) {
477 sscom_kgdb_attached = 1; 473 sscom_kgdb_attached = 1;
478 printf("%s: kgdb\n", device_xname(sc->sc_dev)); 474 printf("%s: kgdb\n", device_xname(sc->sc_dev));
479 sscom_enable_debugport(sc); 475 sscom_enable_debugport(sc);
480 return; 476 return;
481 } 477 }
482#endif 478#endif
483 479
484 tp = tty_alloc(); 480 tp = tty_alloc();
485 tp->t_oproc = sscomstart; 481 tp->t_oproc = sscomstart;
486 tp->t_param = sscomparam; 482 tp->t_param = sscomparam;
487 tp->t_hwiflow = sscomhwiflow; 483 tp->t_hwiflow = sscomhwiflow;
488 484
489 sc->sc_tty = tp; 485 sc->sc_tty = tp;
490 sc->sc_rbuf = malloc(sscom_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 486 sc->sc_rbuf = malloc(sscom_rbuf_size << 1, M_DEVBUF, M_NOWAIT);
491 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 487 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf;
492 sc->sc_rbavail = sscom_rbuf_size; 488 sc->sc_rbavail = sscom_rbuf_size;
493 if (sc->sc_rbuf == NULL) { 489 if (sc->sc_rbuf == NULL) {
494 printf("%s: unable to allocate ring buffer\n", 490 printf("%s: unable to allocate ring buffer\n",
495 device_xname(sc->sc_dev)); 491 device_xname(sc->sc_dev));
496 return; 492 return;
497 } 493 }
498 sc->sc_ebuf = sc->sc_rbuf + (sscom_rbuf_size << 1); 494 sc->sc_ebuf = sc->sc_rbuf + (sscom_rbuf_size << 1);
499 495
500 tty_attach(tp); 496 tty_attach(tp);
501 497
502 if (ISSET(sc->sc_hwflags, SSCOM_HW_CONSOLE)) { 498 if (ISSET(sc->sc_hwflags, SSCOM_HW_CONSOLE)) {
503 int maj; 499 int maj;
504 500
505 /* locate the major number */ 501 /* locate the major number */
506 maj = cdevsw_lookup_major(&sscom_cdevsw); 502 maj = cdevsw_lookup_major(&sscom_cdevsw);
507 503
508 cn_tab->cn_dev = makedev(maj, device_unit(sc->sc_dev)); 504 cn_tab->cn_dev = makedev(maj, device_unit(sc->sc_dev));
509 505
510 printf("%s: console (major=%d)\n", device_xname(sc->sc_dev), maj); 506 printf("%s: console (major=%d)\n", device_xname(sc->sc_dev), maj);
511 } 507 }
512 508
513 509
514 sc->sc_si = softint_establish(SOFTINT_SERIAL, sscomsoft, sc); 510 sc->sc_si = softint_establish(SOFTINT_SERIAL, sscomsoft, sc);
515 511
516#ifdef RND_COM 512#ifdef RND_COM
517 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 513 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev),
518 RND_TYPE_TTY, RND_FLAG_DEFAULT); 514 RND_TYPE_TTY, RND_FLAG_DEFAULT);
519#endif 515#endif
520 516
521 /* if there are no enable/disable functions, assume the device 517 /* if there are no enable/disable functions, assume the device
522 is always enabled */ 518 is always enabled */
523 519
524 if (ISSET(sc->sc_hwflags, SSCOM_HW_CONSOLE)) 520 if (ISSET(sc->sc_hwflags, SSCOM_HW_CONSOLE))
525 sscom_enable_debugport(sc); 521 sscom_enable_debugport(sc);
526 else  522 else
527 sscom_disable_txrxint(sc); 523 sscom_disable_txrxint(sc);
528 524
529 SET(sc->sc_hwflags, SSCOM_HW_DEV_OK); 525 SET(sc->sc_hwflags, SSCOM_HW_DEV_OK);
530} 526}
531 527
532int 528int
533sscom_detach(device_t self, int flags) 529sscom_detach(device_t self, int flags)
534{ 530{
535 struct sscom_softc *sc = device_private(self); 531 struct sscom_softc *sc = device_private(self);
536 532
537 if (sc->sc_hwflags & (SSCOM_HW_CONSOLE|SSCOM_HW_KGDB)) 533 if (sc->sc_hwflags & (SSCOM_HW_CONSOLE|SSCOM_HW_KGDB))
538 return EBUSY; 534 return EBUSY;
539 535
540 return 0; 536 return 0;
541} 537}
542 538
543int 539int
544sscom_activate(device_t self, enum devact act) 540sscom_activate(device_t self, enum devact act)
545{ 541{
546#ifdef notyet 542#ifdef notyet
547 struct sscom_softc *sc = device_private(self); 543 struct sscom_softc *sc = device_private(self);
548#endif 544#endif
549 545
550 switch (act) { 546 switch (act) {
551 case DVACT_DEACTIVATE: 547 case DVACT_DEACTIVATE:
552#ifdef notyet 548#ifdef notyet
553 sc->enabled = 0; 549 sc->enabled = 0;
554#endif 550#endif
555 return 0; 551 return 0;
556 default: 552 default:
557 return EOPNOTSUPP; 553 return EOPNOTSUPP;
558 } 554 }
559} 555}
560 556
561void 557void
562sscom_shutdown(struct sscom_softc *sc) 558sscom_shutdown(struct sscom_softc *sc)
563{ 559{
564#ifdef notyet 560#ifdef notyet
565 struct tty *tp = sc->sc_tty; 561 struct tty *tp = sc->sc_tty;
566 int s; 562 int s;
567 563
568 s = splserial(); 564 s = splserial();
569 SSCOM_LOCK(sc);  565 SSCOM_LOCK(sc);
570 566
571 /* If we were asserting flow control, then deassert it. */ 567 /* If we were asserting flow control, then deassert it. */
572 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 568 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED);
573 sscom_hwiflow(sc); 569 sscom_hwiflow(sc);
574 570
575 /* Clear any break condition set with TIOCSBRK. */ 571 /* Clear any break condition set with TIOCSBRK. */
576 sscom_break(sc, 0); 572 sscom_break(sc, 0);
577 573
578 /* 574 /*
579 * Hang up if necessary. Wait a bit, so the other side has time to 575 * Hang up if necessary. Wait a bit, so the other side has time to
580 * notice even if we immediately open the port again. 576 * notice even if we immediately open the port again.
581 * Avoid tsleeping above splhigh(). 577 * Avoid tsleeping above splhigh().
582 */ 578 */
583 if (ISSET(tp->t_cflag, HUPCL)) { 579 if (ISSET(tp->t_cflag, HUPCL)) {
584 sscom_modem(sc, 0); 580 sscom_modem(sc, 0);
585 SSCOM_UNLOCK(sc); 581 SSCOM_UNLOCK(sc);
586 splx(s); 582 splx(s);
587 /* XXX tsleep will only timeout */ 583 /* XXX tsleep will only timeout */
588 (void) tsleep(sc, TTIPRI, ttclos, hz); 584 (void) tsleep(sc, TTIPRI, ttclos, hz);
589 s = splserial(); 585 s = splserial();
590 SSCOM_LOCK(sc);  586 SSCOM_LOCK(sc);
591 } 587 }
592 588
593 if (ISSET(sc->sc_hwflags, SSCOM_HW_CONSOLE)) 589 if (ISSET(sc->sc_hwflags, SSCOM_HW_CONSOLE))
594 /* interrupt on break */ 590 /* interrupt on break */
595 sc->sc_ucon = UCON_DEBUGPORT; 591 sc->sc_ucon = UCON_DEBUGPORT;
596 else 592 else
597 sc->sc_ucon = 0; 593 sc->sc_ucon = 0;
598 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSCOM_UCON, sc->sc_ucon); 594 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSCOM_UCON, sc->sc_ucon);
599 595
600#ifdef DIAGNOSTIC 596#ifdef DIAGNOSTIC
601 if (!sc->enabled) 597 if (!sc->enabled)
602 panic("sscom_shutdown: not enabled?"); 598 panic("sscom_shutdown: not enabled?");
603#endif 599#endif
604 sc->enabled = 0; 600 sc->enabled = 0;
605 SSCOM_UNLOCK(sc); 601 SSCOM_UNLOCK(sc);
606 splx(s); 602 splx(s);
607#endif 603#endif
608} 604}
609 605
610int 606int
611sscomopen(dev_t dev, int flag, int mode, struct lwp *l) 607sscomopen(dev_t dev, int flag, int mode, struct lwp *l)
612{ 608{
613 struct sscom_softc *sc; 609 struct sscom_softc *sc;
614 struct tty *tp; 610 struct tty *tp;
615 int s, s2; 611 int s, s2;
616 int error; 612 int error;
617 613
618 sc = device_lookup_private(&sscom_cd, SSCOMUNIT(dev)); 614 sc = device_lookup_private(&sscom_cd, SSCOMUNIT(dev));
619 if (sc == NULL || !ISSET(sc->sc_hwflags, SSCOM_HW_DEV_OK) || 615 if (sc == NULL || !ISSET(sc->sc_hwflags, SSCOM_HW_DEV_OK) ||
620 sc->sc_rbuf == NULL) 616 sc->sc_rbuf == NULL)
621 return ENXIO; 617 return ENXIO;
622 618
623 if (!device_is_active(sc->sc_dev)) 619 if (!device_is_active(sc->sc_dev))
624 return ENXIO; 620 return ENXIO;
625 621
626#ifdef KGDB 622#ifdef KGDB
627 /* 623 /*
628 * If this is the kgdb port, no other use is permitted. 624 * If this is the kgdb port, no other use is permitted.
629 */ 625 */
630 if (ISSET(sc->sc_hwflags, SSCOM_HW_KGDB)) 626 if (ISSET(sc->sc_hwflags, SSCOM_HW_KGDB))
631 return EBUSY; 627 return EBUSY;
632#endif 628#endif
633 629
634 tp = sc->sc_tty; 630 tp = sc->sc_tty;
635 631
636 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 632 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp))
637 return (EBUSY); 633 return (EBUSY);
638 634
639 s = spltty(); 635 s = spltty();
640 636
641 /* 637 /*
642 * Do the following iff this is a first open. 638 * Do the following iff this is a first open.
643 */ 639 */
644 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 640 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
645 struct termios t; 641 struct termios t;
646 642
647 tp->t_dev = dev; 643 tp->t_dev = dev;
648 644
649 s2 = splserial(); 645 s2 = splserial();
650 SSCOM_LOCK(sc); 646 SSCOM_LOCK(sc);
651 647
652 /* Turn on interrupts. */ 648 /* Turn on interrupts. */
653 sscom_enable_txrxint(sc); 649 sscom_enable_txrxint(sc);
654 650
655 /* Fetch the current modem control status, needed later. */ 651 /* Fetch the current modem control status, needed later. */
656 sc->sc_msts = sc->sc_read_modem_status(sc); 652 sc->sc_msts = sc->sc_read_modem_status(sc);
657 653
658#if 0 654#if 0
659 /* Clear PPS capture state on first open. */ 655 /* Clear PPS capture state on first open. */
660 sc->sc_ppsmask = 0; 656 sc->sc_ppsmask = 0;
661 sc->ppsparam.mode = 0; 657 sc->ppsparam.mode = 0;
662#endif 658#endif
663 659
664 SSCOM_UNLOCK(sc); 660 SSCOM_UNLOCK(sc);
665 splx(s2); 661 splx(s2);
666 662
667 /* 663 /*
668 * Initialize the termios status to the defaults. Add in the 664 * Initialize the termios status to the defaults. Add in the
669 * sticky bits from TIOCSFLAGS. 665 * sticky bits from TIOCSFLAGS.
670 */ 666 */
671 t.c_ispeed = 0; 667 t.c_ispeed = 0;
672 if (ISSET(sc->sc_hwflags, SSCOM_HW_CONSOLE)) { 668 if (ISSET(sc->sc_hwflags, SSCOM_HW_CONSOLE)) {
673 t.c_ospeed = sscomconsrate; 669 t.c_ospeed = sscomconsrate;
674 t.c_cflag = sscomconscflag; 670 t.c_cflag = sscomconscflag;
675 } else { 671 } else {
676 t.c_ospeed = TTYDEF_SPEED; 672 t.c_ospeed = TTYDEF_SPEED;
677 t.c_cflag = TTYDEF_CFLAG; 673 t.c_cflag = TTYDEF_CFLAG;
678 } 674 }
679 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 675 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL))
680 SET(t.c_cflag, CLOCAL); 676 SET(t.c_cflag, CLOCAL);
681 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 677 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS))
682 SET(t.c_cflag, CRTSCTS); 678 SET(t.c_cflag, CRTSCTS);
683 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 679 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF))
684 SET(t.c_cflag, MDMBUF); 680 SET(t.c_cflag, MDMBUF);
685 /* Make sure sscomparam() will do something. */ 681 /* Make sure sscomparam() will do something. */
686 tp->t_ospeed = 0; 682 tp->t_ospeed = 0;
687 (void) sscomparam(tp, &t); 683 (void) sscomparam(tp, &t);
688 tp->t_iflag = TTYDEF_IFLAG; 684 tp->t_iflag = TTYDEF_IFLAG;
689 tp->t_oflag = TTYDEF_OFLAG; 685 tp->t_oflag = TTYDEF_OFLAG;
690 tp->t_lflag = TTYDEF_LFLAG; 686 tp->t_lflag = TTYDEF_LFLAG;
691 ttychars(tp); 687 ttychars(tp);
692 ttsetwater(tp); 688 ttsetwater(tp);
693 689
694 s2 = splserial(); 690 s2 = splserial();
695 SSCOM_LOCK(sc); 691 SSCOM_LOCK(sc);
696 692
697 /* 693 /*
698 * Turn on DTR. We must always do this, even if carrier is not 694 * Turn on DTR. We must always do this, even if carrier is not
699 * present, because otherwise we'd have to use TIOCSDTR 695 * present, because otherwise we'd have to use TIOCSDTR
700 * immediately after setting CLOCAL, which applications do not 696 * immediately after setting CLOCAL, which applications do not
701 * expect. We always assert DTR while the device is open 697 * expect. We always assert DTR while the device is open
702 * unless explicitly requested to deassert it. 698 * unless explicitly requested to deassert it.
703 */ 699 */
704 sscom_modem(sc, 1); 700 sscom_modem(sc, 1);
705 701
706 /* Clear the input ring, and unblock. */ 702 /* Clear the input ring, and unblock. */
707 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 703 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf;
708 sc->sc_rbavail = sscom_rbuf_size; 704 sc->sc_rbavail = sscom_rbuf_size;
709 sscom_iflush(sc); 705 sscom_iflush(sc);
710 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 706 CLR(sc->sc_rx_flags, RX_ANY_BLOCK);
711 sscom_hwiflow(sc); 707 sscom_hwiflow(sc);
712 708
713 if (sscom_debug) 709 if (sscom_debug)
714 sscomstatus(sc, "sscomopen "); 710 sscomstatus(sc, "sscomopen ");
715 711
716 SSCOM_UNLOCK(sc); 712 SSCOM_UNLOCK(sc);
717 splx(s2); 713 splx(s2);
718 } 714 }
719  715
720 splx(s); 716 splx(s);
721 717
722 error = ttyopen(tp, SSCOMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 718 error = ttyopen(tp, SSCOMDIALOUT(dev), ISSET(flag, O_NONBLOCK));
723 if (error) 719 if (error)
724 goto bad; 720 goto bad;
725 721
726 error = (*tp->t_linesw->l_open)(dev, tp); 722 error = (*tp->t_linesw->l_open)(dev, tp);
727 if (error) 723 if (error)
728 goto bad; 724 goto bad;
729 725
730 return 0; 726 return 0;
731 727
732bad: 728bad:
733 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 729 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
734 /* 730 /*
735 * We failed to open the device, and nobody else had it opened. 731 * We failed to open the device, and nobody else had it opened.
736 * Clean up the state as appropriate. 732 * Clean up the state as appropriate.
737 */ 733 */
738 sscom_shutdown(sc); 734 sscom_shutdown(sc);
739 } 735 }
740 736
741 return error; 737 return error;
742} 738}
743  739
744int 740int
745sscomclose(dev_t dev, int flag, int mode, struct lwp *l) 741sscomclose(dev_t dev, int flag, int mode, struct lwp *l)
746{ 742{
747 struct sscom_softc *sc = device_lookup_private(&sscom_cd, SSCOMUNIT(dev)); 743 struct sscom_softc *sc = device_lookup_private(&sscom_cd, SSCOMUNIT(dev));
748 struct tty *tp = sc->sc_tty; 744 struct tty *tp = sc->sc_tty;
749 745
750 /* XXX This is for cons.c. */ 746 /* XXX This is for cons.c. */
751 if (!ISSET(tp->t_state, TS_ISOPEN)) 747 if (!ISSET(tp->t_state, TS_ISOPEN))
752 return 0; 748 return 0;
753 749
754 (*tp->t_linesw->l_close)(tp, flag); 750 (*tp->t_linesw->l_close)(tp, flag);
755 ttyclose(tp); 751 ttyclose(tp);
756 752
757 if (SSCOM_ISALIVE(sc) == 0) 753 if (SSCOM_ISALIVE(sc) == 0)
758 return 0; 754 return 0;
759 755
760 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 756 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
761 /* 757 /*
762 * Although we got a last close, the device may still be in 758 * Although we got a last close, the device may still be in
763 * use; e.g. if this was the dialout node, and there are still 759 * use; e.g. if this was the dialout node, and there are still
764 * processes waiting for carrier on the non-dialout node. 760 * processes waiting for carrier on the non-dialout node.
765 */ 761 */
766 sscom_shutdown(sc); 762 sscom_shutdown(sc);
767 } 763 }
768 764
769 return 0; 765 return 0;
770} 766}
771  767
772int 768int
773sscomread(dev_t dev, struct uio *uio, int flag) 769sscomread(dev_t dev, struct uio *uio, int flag)
774{ 770{
775 struct sscom_softc *sc = device_lookup_private(&sscom_cd, SSCOMUNIT(dev)); 771 struct sscom_softc *sc = device_lookup_private(&sscom_cd, SSCOMUNIT(dev));
776 struct tty *tp = sc->sc_tty; 772 struct tty *tp = sc->sc_tty;
777 773
778 if (SSCOM_ISALIVE(sc) == 0) 774 if (SSCOM_ISALIVE(sc) == 0)
779 return EIO; 775 return EIO;
780  776
781 return (*tp->t_linesw->l_read)(tp, uio, flag); 777 return (*tp->t_linesw->l_read)(tp, uio, flag);
782} 778}
783  779
784int 780int
785sscomwrite(dev_t dev, struct uio *uio, int flag) 781sscomwrite(dev_t dev, struct uio *uio, int flag)
786{ 782{
787 struct sscom_softc *sc = device_lookup_private(&sscom_cd, SSCOMUNIT(dev)); 783 struct sscom_softc *sc = device_lookup_private(&sscom_cd, SSCOMUNIT(dev));
788 struct tty *tp = sc->sc_tty; 784 struct tty *tp = sc->sc_tty;
789 785
790 if (SSCOM_ISALIVE(sc) == 0) 786 if (SSCOM_ISALIVE(sc) == 0)
791 return EIO; 787 return EIO;
792  788
793 return (*tp->t_linesw->l_write)(tp, uio, flag); 789 return (*tp->t_linesw->l_write)(tp, uio, flag);
794} 790}
795 791
796int 792int
797sscompoll(dev_t dev, int events, struct lwp *l) 793sscompoll(dev_t dev, int events, struct lwp *l)
798{ 794{
799 struct sscom_softc *sc = device_lookup_private(&sscom_cd, SSCOMUNIT(dev)); 795 struct sscom_softc *sc = device_lookup_private(&sscom_cd, SSCOMUNIT(dev));
800 struct tty *tp = sc->sc_tty; 796 struct tty *tp = sc->sc_tty;
801 797
802 if (SSCOM_ISALIVE(sc) == 0) 798 if (SSCOM_ISALIVE(sc) == 0)
803 return EIO; 799 return EIO;
804  800
805 return (*tp->t_linesw->l_poll)(tp, events, l); 801 return (*tp->t_linesw->l_poll)(tp, events, l);
806} 802}
807 803
808struct tty * 804struct tty *
809sscomtty(dev_t dev) 805sscomtty(dev_t dev)
810{ 806{
811 struct sscom_softc *sc = device_lookup_private(&sscom_cd, SSCOMUNIT(dev)); 807 struct sscom_softc *sc = device_lookup_private(&sscom_cd, SSCOMUNIT(dev));
812 struct tty *tp = sc->sc_tty; 808 struct tty *tp = sc->sc_tty;
813 809
814 return tp; 810 return tp;
815} 811}
816 812
817int 813int
818sscomioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 814sscomioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l)
819{ 815{
820 struct sscom_softc *sc = device_lookup_private(&sscom_cd, SSCOMUNIT(dev)); 816 struct sscom_softc *sc = device_lookup_private(&sscom_cd, SSCOMUNIT(dev));
821 struct tty *tp = sc->sc_tty; 817 struct tty *tp = sc->sc_tty;
822 int error; 818 int error;
823 int s; 819 int s;
824 820
825 if (SSCOM_ISALIVE(sc) == 0) 821 if (SSCOM_ISALIVE(sc) == 0)
826 return EIO; 822 return EIO;
827 823
828 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 824 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l);
829 if (error != EPASSTHROUGH) 825 if (error != EPASSTHROUGH)
830 return error; 826 return error;
831 827
832 error = ttioctl(tp, cmd, data, flag, l); 828 error = ttioctl(tp, cmd, data, flag, l);
833 if (error != EPASSTHROUGH) 829 if (error != EPASSTHROUGH)
834 return error; 830 return error;
835 831
836 error = 0; 832 error = 0;
837 833
838 s = splserial(); 834 s = splserial();
839 SSCOM_LOCK(sc);  835 SSCOM_LOCK(sc);
840 836
841 switch (cmd) { 837 switch (cmd) {
842 case TIOCSBRK: 838 case TIOCSBRK:
843 sscom_break(sc, 1); 839 sscom_break(sc, 1);
844 break; 840 break;
845 841
846 case TIOCCBRK: 842 case TIOCCBRK:
847 sscom_break(sc, 0); 843 sscom_break(sc, 0);
848 break; 844 break;
849 845
850 case TIOCSDTR: 846 case TIOCSDTR:
851 sscom_modem(sc, 1); 847 sscom_modem(sc, 1);
852 break; 848 break;
853 849
854 case TIOCCDTR: 850 case TIOCCDTR:
855 sscom_modem(sc, 0); 851 sscom_modem(sc, 0);
856 break; 852 break;
857 853
858 case TIOCGFLAGS: 854 case TIOCGFLAGS:
859 *(int *)data = sc->sc_swflags; 855 *(int *)data = sc->sc_swflags;
860 break; 856 break;
861 857
862 case TIOCSFLAGS: 858 case TIOCSFLAGS:
863 error = kauth_authorize_device_tty(l->l_cred, 859 error = kauth_authorize_device_tty(l->l_cred,
864 KAUTH_DEVICE_TTY_PRIVSET, tp);  860 KAUTH_DEVICE_TTY_PRIVSET, tp);
865 if (error) 861 if (error)
866 break; 862 break;
867 sc->sc_swflags = *(int *)data; 863 sc->sc_swflags = *(int *)data;
868 break; 864 break;
869 865
870 case TIOCMSET: 866 case TIOCMSET:
871 case TIOCMBIS: 867 case TIOCMBIS:
872 case TIOCMBIC: 868 case TIOCMBIC:
873 tiocm_to_sscom(sc, cmd, *(int *)data); 869 tiocm_to_sscom(sc, cmd, *(int *)data);
874 break; 870 break;
875 871
876 case TIOCMGET: 872 case TIOCMGET:
877 *(int *)data = sscom_to_tiocm(sc); 873 *(int *)data = sscom_to_tiocm(sc);
878 break; 874 break;
879 875
880 default: 876 default:
881 error = EPASSTHROUGH; 877 error = EPASSTHROUGH;
882 break; 878 break;
883 } 879 }
884 880
885 SSCOM_UNLOCK(sc); 881 SSCOM_UNLOCK(sc);
886 splx(s); 882 splx(s);
887 883
888 if (sscom_debug) 884 if (sscom_debug)
889 sscomstatus(sc, "sscomioctl "); 885 sscomstatus(sc, "sscomioctl ");
890 886
891 return error; 887 return error;
892} 888}
893 889
894integrate void 890integrate void
895sscom_schedrx(struct sscom_softc *sc) 891sscom_schedrx(struct sscom_softc *sc)
896{ 892{
897 893
898 sc->sc_rx_ready = 1; 894 sc->sc_rx_ready = 1;
899 895
900 /* Wake up the poller. */ 896 /* Wake up the poller. */
901 softint_schedule(sc->sc_si); 897 softint_schedule(sc->sc_si);
902} 898}
903 899
904static void 900static void
905sscom_break(struct sscom_softc *sc, int onoff) 901sscom_break(struct sscom_softc *sc, int onoff)
906{ 902{
907 903
908 if (onoff) 904 if (onoff)
909 SET(sc->sc_ucon, UCON_SBREAK); 905 SET(sc->sc_ucon, UCON_SBREAK);
910 else 906 else
911 CLR(sc->sc_ucon, UCON_SBREAK); 907 CLR(sc->sc_ucon, UCON_SBREAK);
912 908
913 if (!sc->sc_heldchange) { 909 if (!sc->sc_heldchange) {
914 if (sc->sc_tx_busy) { 910 if (sc->sc_tx_busy) {
915 sc->sc_heldtbc = sc->sc_tbc; 911 sc->sc_heldtbc = sc->sc_tbc;
916 sc->sc_tbc = 0; 912 sc->sc_tbc = 0;
917 sc->sc_heldchange = 1; 913 sc->sc_heldchange = 1;
918 } else 914 } else
919 sscom_loadchannelregs(sc); 915 sscom_loadchannelregs(sc);
920 } 916 }
921} 917}
922 918
923static void 919static void
924sscom_modem(struct sscom_softc *sc, int onoff) 920sscom_modem(struct sscom_softc *sc, int onoff)
925{ 921{
926 if (onoff) 922 if (onoff)
927 SET(sc->sc_umcon, UMCON_DTR); 923 SET(sc->sc_umcon, UMCON_DTR);
928 else 924 else
929 CLR(sc->sc_umcon, UMCON_DTR); 925 CLR(sc->sc_umcon, UMCON_DTR);
930 926
931 if (!sc->sc_heldchange) { 927 if (!sc->sc_heldchange) {
932 if (sc->sc_tx_busy) { 928 if (sc->sc_tx_busy) {
933 sc->sc_heldtbc = sc->sc_tbc; 929 sc->sc_heldtbc = sc->sc_tbc;
934 sc->sc_tbc = 0; 930 sc->sc_tbc = 0;
935 sc->sc_heldchange = 1; 931 sc->sc_heldchange = 1;
936 } else 932 } else
937 sscom_loadchannelregs(sc); 933 sscom_loadchannelregs(sc);
938 } 934 }
939} 935}
940 936
941static void 937static void
942tiocm_to_sscom(struct sscom_softc *sc, u_long how, int ttybits) 938tiocm_to_sscom(struct sscom_softc *sc, u_long how, int ttybits)
943{ 939{
944 u_char sscombits; 940 u_char sscombits;
945 941
946 sscombits = 0; 942 sscombits = 0;
947 if (ISSET(ttybits, TIOCM_DTR)) 943 if (ISSET(ttybits, TIOCM_DTR))
948 sscombits = UMCON_DTR; 944 sscombits = UMCON_DTR;
949 if (ISSET(ttybits, TIOCM_RTS)) 945 if (ISSET(ttybits, TIOCM_RTS))
950 SET(sscombits, UMCON_RTS); 946 SET(sscombits, UMCON_RTS);
951  947
952 switch (how) { 948 switch (how) {
953 case TIOCMBIC: 949 case TIOCMBIC:
954 CLR(sc->sc_umcon, sscombits); 950 CLR(sc->sc_umcon, sscombits);
955 break; 951 break;
956 952
957 case TIOCMBIS: 953 case TIOCMBIS:
958 SET(sc->sc_umcon, sscombits); 954 SET(sc->sc_umcon, sscombits);
959 break; 955 break;
960 956
961 case TIOCMSET: 957 case TIOCMSET:
962 CLR(sc->sc_umcon, UMCON_DTR); 958 CLR(sc->sc_umcon, UMCON_DTR);
963 SET(sc->sc_umcon, sscombits); 959 SET(sc->sc_umcon, sscombits);
964 break; 960 break;
965 } 961 }
966 962
967 if (!sc->sc_heldchange) { 963 if (!sc->sc_heldchange) {
968 if (sc->sc_tx_busy) { 964 if (sc->sc_tx_busy) {
969 sc->sc_heldtbc = sc->sc_tbc; 965 sc->sc_heldtbc = sc->sc_tbc;
970 sc->sc_tbc = 0; 966 sc->sc_tbc = 0;
971 sc->sc_heldchange = 1; 967 sc->sc_heldchange = 1;
972 } else 968 } else
973 sscom_loadchannelregs(sc); 969 sscom_loadchannelregs(sc);
974 } 970 }
975} 971}
976 972
977static int 973static int
978sscom_to_tiocm(struct sscom_softc *sc) 974sscom_to_tiocm(struct sscom_softc *sc)
979{ 975{
980 u_char sscombits; 976 u_char sscombits;
981 int ttybits = 0; 977 int ttybits = 0;
982 978
983 sscombits = sc->sc_umcon; 979 sscombits = sc->sc_umcon;
984#if 0 980#if 0
985 if (ISSET(sscombits, MCR_DTR)) 981 if (ISSET(sscombits, MCR_DTR))
986 SET(ttybits, TIOCM_DTR); 982 SET(ttybits, TIOCM_DTR);
987#endif 983#endif
988 if (ISSET(sscombits, UMCON_RTS)) 984 if (ISSET(sscombits, UMCON_RTS))
989 SET(ttybits, TIOCM_RTS); 985 SET(ttybits, TIOCM_RTS);
990 986
991 sscombits = sc->sc_msts; 987 sscombits = sc->sc_msts;
992 if (ISSET(sscombits, MSTS_DCD)) 988 if (ISSET(sscombits, MSTS_DCD))
993 SET(ttybits, TIOCM_CD); 989 SET(ttybits, TIOCM_CD);
994 if (ISSET(sscombits, MSTS_DSR)) 990 if (ISSET(sscombits, MSTS_DSR))
995 SET(ttybits, TIOCM_DSR); 991 SET(ttybits, TIOCM_DSR);
996 if (ISSET(sscombits, MSTS_CTS)) 992 if (ISSET(sscombits, MSTS_CTS))
997 SET(ttybits, TIOCM_CTS); 993 SET(ttybits, TIOCM_CTS);
998 994
999 if (sc->sc_ucon != 0) 995 if (sc->sc_ucon != 0)
1000 SET(ttybits, TIOCM_LE); 996 SET(ttybits, TIOCM_LE);
1001 997
1002 return ttybits; 998 return ttybits;
1003} 999}
1004 1000
1005static int 1001static int
1006cflag2lcr(tcflag_t cflag) 1002cflag2lcr(tcflag_t cflag)
1007{ 1003{
1008 u_char lcr = ULCON_PARITY_NONE; 1004 u_char lcr = ULCON_PARITY_NONE;
1009 1005
1010 switch (cflag & (PARENB|PARODD)) { 1006 switch (cflag & (PARENB|PARODD)) {
1011 case PARENB|PARODD: lcr = ULCON_PARITY_ODD; break; 1007 case PARENB|PARODD: lcr = ULCON_PARITY_ODD; break;
1012 case PARENB: lcr = ULCON_PARITY_EVEN; 1008 case PARENB: lcr = ULCON_PARITY_EVEN;
1013 } 1009 }
1014 1010
1015 switch (ISSET(cflag, CSIZE)) { 1011 switch (ISSET(cflag, CSIZE)) {
1016 case CS5: 1012 case CS5:
1017 SET(lcr, ULCON_LENGTH_5); 1013 SET(lcr, ULCON_LENGTH_5);
1018 break; 1014 break;
1019 case CS6: 1015 case CS6:
1020 SET(lcr, ULCON_LENGTH_6); 1016 SET(lcr, ULCON_LENGTH_6);
1021 break; 1017 break;
1022 case CS7: 1018 case CS7:
1023 SET(lcr, ULCON_LENGTH_7); 1019 SET(lcr, ULCON_LENGTH_7);
1024 break; 1020 break;
1025 case CS8: 1021 case CS8:
1026 SET(lcr, ULCON_LENGTH_8); 1022 SET(lcr, ULCON_LENGTH_8);
1027 break; 1023 break;
1028 } 1024 }
1029 if (ISSET(cflag, CSTOPB)) 1025 if (ISSET(cflag, CSTOPB))
1030 SET(lcr, ULCON_STOP); 1026 SET(lcr, ULCON_STOP);
1031 1027
1032 return lcr; 1028 return lcr;
1033} 1029}
1034 1030
1035int 1031int
1036sscomparam(struct tty *tp, struct termios *t) 1032sscomparam(struct tty *tp, struct termios *t)
1037{ 1033{
1038 struct sscom_softc *sc = device_lookup_private(&sscom_cd, SSCOMUNIT(tp->t_dev)); 1034 struct sscom_softc *sc = device_lookup_private(&sscom_cd, SSCOMUNIT(tp->t_dev));
1039 int ospeed; 1035 int ospeed;
1040 u_char lcr; 1036 u_char lcr;
1041 int s; 1037 int s;
1042 1038
1043 if (SSCOM_ISALIVE(sc) == 0) 1039 if (SSCOM_ISALIVE(sc) == 0)
1044 return EIO; 1040 return EIO;
1045 1041
1046 ospeed = sscomspeed(t->c_ospeed, sc->sc_frequency); 1042 ospeed = sscomspeed(t->c_ospeed, sc->sc_frequency);
1047 1043
1048 /* Check requested parameters. */ 1044 /* Check requested parameters. */
1049 if (ospeed < 0) 1045 if (ospeed < 0)
1050 return EINVAL; 1046 return EINVAL;
1051 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1047 if (t->c_ispeed && t->c_ispeed != t->c_ospeed)
1052 return EINVAL; 1048 return EINVAL;
1053 1049
1054 /* 1050 /*
1055 * For the console, always force CLOCAL and !HUPCL, so that the port 1051 * For the console, always force CLOCAL and !HUPCL, so that the port
1056 * is always active. 1052 * is always active.
1057 */ 1053 */
1058 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1054 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) ||
1059 ISSET(sc->sc_hwflags, SSCOM_HW_CONSOLE)) { 1055 ISSET(sc->sc_hwflags, SSCOM_HW_CONSOLE)) {
1060 SET(t->c_cflag, CLOCAL); 1056 SET(t->c_cflag, CLOCAL);
1061 CLR(t->c_cflag, HUPCL); 1057 CLR(t->c_cflag, HUPCL);
1062 } 1058 }
1063 1059
1064 /* 1060 /*
1065 * If there were no changes, don't do anything. This avoids dropping 1061 * If there were no changes, don't do anything. This avoids dropping
1066 * input and improves performance when all we did was frob things like 1062 * input and improves performance when all we did was frob things like
1067 * VMIN and VTIME. 1063 * VMIN and VTIME.
1068 */ 1064 */
1069 if (tp->t_ospeed == t->c_ospeed && 1065 if (tp->t_ospeed == t->c_ospeed &&
1070 tp->t_cflag == t->c_cflag) 1066 tp->t_cflag == t->c_cflag)
1071 return 0; 1067 return 0;
1072 1068
1073 lcr = cflag2lcr(t->c_cflag); 1069 lcr = cflag2lcr(t->c_cflag);
1074 1070
1075 s = splserial(); 1071 s = splserial();
1076 SSCOM_LOCK(sc);  1072 SSCOM_LOCK(sc);
1077 1073
1078 sc->sc_ulcon = lcr; 1074 sc->sc_ulcon = lcr;
1079 1075
1080 /* 1076 /*
1081 * If we're not in a mode that assumes a connection is present, then 1077 * If we're not in a mode that assumes a connection is present, then
1082 * ignore carrier changes. 1078 * ignore carrier changes.
1083 */ 1079 */
1084 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1080 if (ISSET(t->c_cflag, CLOCAL | MDMBUF))
1085 sc->sc_msr_dcd = 0; 1081 sc->sc_msr_dcd = 0;
1086 else 1082 else
1087 sc->sc_msr_dcd = MSTS_DCD; 1083 sc->sc_msr_dcd = MSTS_DCD;
1088 1084
1089 /* 1085 /*
1090 * Set the flow control pins depending on the current flow control 1086 * Set the flow control pins depending on the current flow control
1091 * mode. 1087 * mode.
1092 */ 1088 */
1093 if (ISSET(t->c_cflag, CRTSCTS)) { 1089 if (ISSET(t->c_cflag, CRTSCTS)) {
1094 sc->sc_mcr_dtr = UMCON_DTR; 1090 sc->sc_mcr_dtr = UMCON_DTR;
1095 sc->sc_mcr_rts = UMCON_RTS; 1091 sc->sc_mcr_rts = UMCON_RTS;
1096 sc->sc_msr_cts = MSTS_CTS; 1092 sc->sc_msr_cts = MSTS_CTS;
1097 } 1093 }
1098 else if (ISSET(t->c_cflag, MDMBUF)) { 1094 else if (ISSET(t->c_cflag, MDMBUF)) {
1099 /* 1095 /*
1100 * For DTR/DCD flow control, make sure we don't toggle DTR for 1096 * For DTR/DCD flow control, make sure we don't toggle DTR for
1101 * carrier detection. 1097 * carrier detection.
1102 */ 1098 */
1103 sc->sc_mcr_dtr = 0; 1099 sc->sc_mcr_dtr = 0;
1104 sc->sc_mcr_rts = UMCON_DTR; 1100 sc->sc_mcr_rts = UMCON_DTR;
1105 sc->sc_msr_cts = MSTS_DCD; 1101 sc->sc_msr_cts = MSTS_DCD;
1106 }  1102 }
1107 else { 1103 else {
1108 /* 1104 /*
1109 * If no flow control, then always set RTS. This will make 1105 * If no flow control, then always set RTS. This will make
1110 * the other side happy if it mistakenly thinks we're doing 1106 * the other side happy if it mistakenly thinks we're doing
1111 * RTS/CTS flow control. 1107 * RTS/CTS flow control.
1112 */ 1108 */
1113 sc->sc_mcr_dtr = UMCON_DTR | UMCON_RTS; 1109 sc->sc_mcr_dtr = UMCON_DTR | UMCON_RTS;
1114 sc->sc_mcr_rts = 0; 1110 sc->sc_mcr_rts = 0;
1115 sc->sc_msr_cts = 0; 1111 sc->sc_msr_cts = 0;
1116 if (ISSET(sc->sc_umcon, UMCON_DTR)) 1112 if (ISSET(sc->sc_umcon, UMCON_DTR))
1117 SET(sc->sc_umcon, UMCON_RTS); 1113 SET(sc->sc_umcon, UMCON_RTS);
1118 else 1114 else
1119 CLR(sc->sc_umcon, UMCON_RTS); 1115 CLR(sc->sc_umcon, UMCON_RTS);
1120 } 1116 }
1121 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1117 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd;
1122 1118
1123 if (ospeed == 0) 1119 if (ospeed == 0)
1124 CLR(sc->sc_umcon, sc->sc_mcr_dtr); 1120 CLR(sc->sc_umcon, sc->sc_mcr_dtr);
1125 else 1121 else
1126 SET(sc->sc_umcon, sc->sc_mcr_dtr); 1122 SET(sc->sc_umcon, sc->sc_mcr_dtr);
1127 1123
1128 sc->sc_ubrdiv = ospeed; 1124 sc->sc_ubrdiv = ospeed;
1129 1125
1130 /* And copy to tty. */ 1126 /* And copy to tty. */
1131 tp->t_ispeed = 0; 1127 tp->t_ispeed = 0;
1132 tp->t_ospeed = t->c_ospeed; 1128 tp->t_ospeed = t->c_ospeed;
1133 tp->t_cflag = t->c_cflag; 1129 tp->t_cflag = t->c_cflag;
1134 1130
1135 if (!sc->sc_heldchange) { 1131 if (!sc->sc_heldchange) {
1136 if (sc->sc_tx_busy) { 1132 if (sc->sc_tx_busy) {
1137 sc->sc_heldtbc = sc->sc_tbc; 1133 sc->sc_heldtbc = sc->sc_tbc;
1138 sc->sc_tbc = 0; 1134 sc->sc_tbc = 0;
1139 sc->sc_heldchange = 1; 1135 sc->sc_heldchange = 1;
1140 } else 1136 } else
1141 sscom_loadchannelregs(sc); 1137 sscom_loadchannelregs(sc);
1142 } 1138 }
1143 1139
1144 if (!ISSET(t->c_cflag, CHWFLOW)) { 1140 if (!ISSET(t->c_cflag, CHWFLOW)) {
1145 /* Disable the high water mark. */ 1141 /* Disable the high water mark. */
1146 sc->sc_r_hiwat = 0; 1142 sc->sc_r_hiwat = 0;
1147 sc->sc_r_lowat = 0; 1143 sc->sc_r_lowat = 0;
1148 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1144 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) {
1149 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1145 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED);
1150 sscom_schedrx(sc); 1146 sscom_schedrx(sc);
1151 } 1147 }
1152 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1148 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) {
1153 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1149 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED);
1154 sscom_hwiflow(sc); 1150 sscom_hwiflow(sc);
1155 } 1151 }
1156 } else { 1152 } else {
1157 sc->sc_r_hiwat = sscom_rbuf_hiwat; 1153 sc->sc_r_hiwat = sscom_rbuf_hiwat;
1158 sc->sc_r_lowat = sscom_rbuf_lowat; 1154 sc->sc_r_lowat = sscom_rbuf_lowat;
1159 } 1155 }
1160 1156
1161 SSCOM_UNLOCK(sc); 1157 SSCOM_UNLOCK(sc);
1162 splx(s); 1158 splx(s);
1163 1159
1164 /* 1160 /*
1165 * Update the tty layer's idea of the carrier bit, in case we changed 1161 * Update the tty layer's idea of the carrier bit, in case we changed
1166 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1162 * CLOCAL or MDMBUF. We don't hang up here; we only do that by
1167 * explicit request. 1163 * explicit request.
1168 */ 1164 */
1169 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msts, MSTS_DCD)); 1165 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msts, MSTS_DCD));
1170 1166
1171 if (sscom_debug) 1167 if (sscom_debug)
1172 sscomstatus(sc, "sscomparam "); 1168 sscomstatus(sc, "sscomparam ");
1173 1169
1174 if (!ISSET(t->c_cflag, CHWFLOW)) { 1170 if (!ISSET(t->c_cflag, CHWFLOW)) {
1175 if (sc->sc_tx_stopped) { 1171 if (sc->sc_tx_stopped) {
1176 sc->sc_tx_stopped = 0; 1172 sc->sc_tx_stopped = 0;
1177 sscomstart(tp); 1173 sscomstart(tp);
1178 } 1174 }
1179 } 1175 }
1180 1176
1181 return 0; 1177 return 0;
1182} 1178}
1183 1179
1184static void 1180static void
1185sscom_iflush(struct sscom_softc *sc) 1181sscom_iflush(struct sscom_softc *sc)
1186{ 1182{
1187 bus_space_tag_t iot = sc->sc_iot; 1183 bus_space_tag_t iot = sc->sc_iot;
1188 bus_space_handle_t ioh = sc->sc_ioh; 1184 bus_space_handle_t ioh = sc->sc_ioh;
1189 int timo; 1185 int timo;
1190 1186
1191 1187
1192 timo = 50000; 1188 timo = 50000;
1193 /* flush any pending I/O */ 1189 /* flush any pending I/O */
1194 while ( sscom_rxrdy(iot, ioh) && --timo) 1190 while ( sscom_rxrdy(iot, ioh) && --timo)
1195 (void)sscom_getc(iot,ioh); 1191 (void)sscom_getc(iot,ioh);
1196#ifdef DIAGNOSTIC 1192#ifdef DIAGNOSTIC
1197 if (!timo) 1193 if (!timo)
1198 printf("%s: sscom_iflush timeout\n", device_xname(sc->sc_dev)); 1194 printf("%s: sscom_iflush timeout\n", device_xname(sc->sc_dev));
1199#endif 1195#endif
1200} 1196}
1201 1197
1202static void 1198static void
1203sscom_loadchannelregs(struct sscom_softc *sc) 1199sscom_loadchannelregs(struct sscom_softc *sc)
1204{ 1200{
1205 bus_space_tag_t iot = sc->sc_iot; 1201 bus_space_tag_t iot = sc->sc_iot;
1206 bus_space_handle_t ioh = sc->sc_ioh; 1202 bus_space_handle_t ioh = sc->sc_ioh;
1207 1203
1208 /* XXXXX necessary? */ 1204 /* XXXXX necessary? */
1209 sscom_iflush(sc); 1205 sscom_iflush(sc);
1210 1206
1211 bus_space_write_4(iot, ioh, SSCOM_UCON, 0); 1207 bus_space_write_4(iot, ioh, SSCOM_UCON, 0);
1212 1208
1213#if 0 1209#if 0
1214 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1210 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) {
1215 bus_space_write_1(iot, ioh, com_lcr, LCR_EERS); 1211 bus_space_write_1(iot, ioh, com_lcr, LCR_EERS);
1216 bus_space_write_1(iot, ioh, com_efr, sc->sc_efr); 1212 bus_space_write_1(iot, ioh, com_efr, sc->sc_efr);
1217 } 1213 }
1218#endif 1214#endif
1219 1215
1220 bus_space_write_2(iot, ioh, SSCOM_UBRDIV, sc->sc_ubrdiv); 1216 bus_space_write_2(iot, ioh, SSCOM_UBRDIV, sc->sc_ubrdiv);
1221 bus_space_write_1(iot, ioh, SSCOM_ULCON, sc->sc_ulcon); 1217 bus_space_write_1(iot, ioh, SSCOM_ULCON, sc->sc_ulcon);
1222 sc->sc_set_modem_control(sc); 1218 sc->sc_set_modem_control(sc);
1223 bus_space_write_4(iot, ioh, SSCOM_UCON, sc->sc_ucon); 1219 bus_space_write_4(iot, ioh, SSCOM_UCON, sc->sc_ucon);
1224} 1220}
1225 1221
1226static int 1222static int
1227sscomhwiflow(struct tty *tp, int block) 1223sscomhwiflow(struct tty *tp, int block)
1228{ 1224{
1229 struct sscom_softc *sc = device_lookup_private(&sscom_cd, SSCOMUNIT(tp->t_dev)); 1225 struct sscom_softc *sc = device_lookup_private(&sscom_cd, SSCOMUNIT(tp->t_dev));
1230 int s; 1226 int s;
1231 1227
1232 if (SSCOM_ISALIVE(sc) == 0) 1228 if (SSCOM_ISALIVE(sc) == 0)
1233 return 0; 1229 return 0;
1234 1230
1235 if (sc->sc_mcr_rts == 0) 1231 if (sc->sc_mcr_rts == 0)
1236 return 0; 1232 return 0;
1237 1233
1238 s = splserial(); 1234 s = splserial();
1239 SSCOM_LOCK(sc); 1235 SSCOM_LOCK(sc);
1240  1236
1241 if (block) { 1237 if (block) {
1242 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1238 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) {
1243 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1239 SET(sc->sc_rx_flags, RX_TTY_BLOCKED);
1244 sscom_hwiflow(sc); 1240 sscom_hwiflow(sc);
1245 } 1241 }
1246 } else { 1242 } else {
1247 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1243 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) {
1248 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1244 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED);
1249 sscom_schedrx(sc); 1245 sscom_schedrx(sc);
1250 } 1246 }
1251 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1247 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) {
1252 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1248 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED);
1253 sscom_hwiflow(sc); 1249 sscom_hwiflow(sc);
1254 } 1250 }
1255 } 1251 }
1256 1252
1257 SSCOM_UNLOCK(sc); 1253 SSCOM_UNLOCK(sc);
1258 splx(s); 1254 splx(s);
1259 return 1; 1255 return 1;
1260} 1256}
1261  1257
1262/* 1258/*
1263 * (un)block input via hw flowcontrol 1259 * (un)block input via hw flowcontrol
1264 */ 1260 */
1265static void 1261static void
1266sscom_hwiflow(struct sscom_softc *sc) 1262sscom_hwiflow(struct sscom_softc *sc)
1267{ 1263{
1268 if (sc->sc_mcr_rts == 0) 1264 if (sc->sc_mcr_rts == 0)
1269 return; 1265 return;
1270 1266
1271 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1267 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) {
1272 CLR(sc->sc_umcon, sc->sc_mcr_rts); 1268 CLR(sc->sc_umcon, sc->sc_mcr_rts);
1273 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1269 CLR(sc->sc_mcr_active, sc->sc_mcr_rts);
1274 } else { 1270 } else {
1275 SET(sc->sc_umcon, sc->sc_mcr_rts); 1271 SET(sc->sc_umcon, sc->sc_mcr_rts);
1276 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1272 SET(sc->sc_mcr_active, sc->sc_mcr_rts);
1277 } 1273 }
1278 sc->sc_set_modem_control(sc); 1274 sc->sc_set_modem_control(sc);
1279} 1275}
1280 1276
1281 1277
1282void 1278void
1283sscomstart(struct tty *tp) 1279sscomstart(struct tty *tp)
1284{ 1280{
1285 struct sscom_softc *sc = device_lookup_private(&sscom_cd, SSCOMUNIT(tp->t_dev)); 1281 struct sscom_softc *sc = device_lookup_private(&sscom_cd, SSCOMUNIT(tp->t_dev));
1286 int s; 1282 int s;
1287 1283
1288 if (SSCOM_ISALIVE(sc) == 0) 1284 if (SSCOM_ISALIVE(sc) == 0)
1289 return; 1285 return;
1290 1286
1291 s = spltty(); 1287 s = spltty();
1292 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1288 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP))
1293 goto out; 1289 goto out;
1294 if (sc->sc_tx_stopped) 1290 if (sc->sc_tx_stopped)
1295 goto out; 1291 goto out;
1296 if (!ttypull(tp)) 1292 if (!ttypull(tp))
1297 goto out; 1293 goto out;
1298 1294
1299 /* Grab the first contiguous region of buffer space. */ 1295 /* Grab the first contiguous region of buffer space. */
1300 { 1296 {
1301 u_char *tba; 1297 u_char *tba;
1302 int tbc; 1298 int tbc;
1303 1299
1304 tba = tp->t_outq.c_cf; 1300 tba = tp->t_outq.c_cf;
1305 tbc = ndqb(&tp->t_outq, 0); 1301 tbc = ndqb(&tp->t_outq, 0);
1306 1302
1307 (void)splserial(); 1303 (void)splserial();
1308 SSCOM_LOCK(sc); 1304 SSCOM_LOCK(sc);
1309 1305
1310 sc->sc_tba = tba; 1306 sc->sc_tba = tba;
1311 sc->sc_tbc = tbc; 1307 sc->sc_tbc = tbc;
1312 } 1308 }
1313 1309
1314 SET(tp->t_state, TS_BUSY); 1310 SET(tp->t_state, TS_BUSY);
1315 sc->sc_tx_busy = 1; 1311 sc->sc_tx_busy = 1;
1316 1312
1317 /* Output the first chunk of the contiguous buffer. */ 1313 /* Output the first chunk of the contiguous buffer. */
1318 sscom_output_chunk(sc); 1314 sscom_output_chunk(sc);
1319 1315
1320 /* Enable transmit completion interrupts if necessary. */ 1316 /* Enable transmit completion interrupts if necessary. */
1321 if ((sc->sc_hwflags & SSCOM_HW_TXINT) == 0) 1317 if ((sc->sc_hwflags & SSCOM_HW_TXINT) == 0)
1322 sscom_enable_txint(sc); 1318 sscom_enable_txint(sc);
1323 1319
1324 SSCOM_UNLOCK(sc); 1320 SSCOM_UNLOCK(sc);
1325out: 1321out:
1326 splx(s); 1322 splx(s);
1327 return; 1323 return;
1328} 1324}
1329 1325
1330/* 1326/*
1331 * Stop output on a line. 1327 * Stop output on a line.
1332 */ 1328 */
1333void 1329void
1334sscomstop(struct tty *tp, int flag) 1330sscomstop(struct tty *tp, int flag)
1335{ 1331{
1336 struct sscom_softc *sc = device_lookup_private(&sscom_cd, SSCOMUNIT(tp->t_dev)); 1332 struct sscom_softc *sc = device_lookup_private(&sscom_cd, SSCOMUNIT(tp->t_dev));
1337 int s; 1333 int s;
1338 1334
1339 s = splserial(); 1335 s = splserial();
1340 SSCOM_LOCK(sc); 1336 SSCOM_LOCK(sc);
1341 if (ISSET(tp->t_state, TS_BUSY)) { 1337 if (ISSET(tp->t_state, TS_BUSY)) {
1342 /* Stop transmitting at the next chunk. */ 1338 /* Stop transmitting at the next chunk. */
1343 sc->sc_tbc = 0; 1339 sc->sc_tbc = 0;
1344 sc->sc_heldtbc = 0; 1340 sc->sc_heldtbc = 0;
1345 if (!ISSET(tp->t_state, TS_TTSTOP)) 1341 if (!ISSET(tp->t_state, TS_TTSTOP))
1346 SET(tp->t_state, TS_FLUSH); 1342 SET(tp->t_state, TS_FLUSH);
1347 } 1343 }
1348 SSCOM_UNLOCK(sc);  1344 SSCOM_UNLOCK(sc);
1349 splx(s); 1345 splx(s);
1350} 1346}
1351 1347
1352void 1348void
1353sscomdiag(void *arg) 1349sscomdiag(void *arg)
1354{ 1350{
1355 struct sscom_softc *sc = arg; 1351 struct sscom_softc *sc = arg;
1356 int overflows, floods; 1352 int overflows, floods;
1357 int s; 1353 int s;
1358 1354
1359 s = splserial(); 1355 s = splserial();
1360 SSCOM_LOCK(sc); 1356 SSCOM_LOCK(sc);
1361 overflows = sc->sc_overflows; 1357 overflows = sc->sc_overflows;
1362 sc->sc_overflows = 0; 1358 sc->sc_overflows = 0;
1363 floods = sc->sc_floods; 1359 floods = sc->sc_floods;
1364 sc->sc_floods = 0; 1360 sc->sc_floods = 0;
1365 sc->sc_errors = 0; 1361 sc->sc_errors = 0;
1366 SSCOM_UNLOCK(sc); 1362 SSCOM_UNLOCK(sc);
1367 splx(s); 1363 splx(s);
1368 1364
1369 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1365 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n",
1370 device_xname(sc->sc_dev), 1366 device_xname(sc->sc_dev),
1371 overflows, overflows == 1 ? "" : "s", 1367 overflows, overflows == 1 ? "" : "s",
1372 floods, floods == 1 ? "" : "s"); 1368 floods, floods == 1 ? "" : "s");
1373} 1369}
1374 1370
1375integrate void 1371integrate void
1376sscom_rxsoft(struct sscom_softc *sc, struct tty *tp) 1372sscom_rxsoft(struct sscom_softc *sc, struct tty *tp)
1377{ 1373{
1378 int (*rint) (int, struct tty *) = tp->t_linesw->l_rint; 1374 int (*rint) (int, struct tty *) = tp->t_linesw->l_rint;
1379 u_char *get, *end; 1375 u_char *get, *end;
1380 u_int cc, scc; 1376 u_int cc, scc;
1381 u_char rsr; 1377 u_char rsr;
1382 int code; 1378 int code;
1383 int s; 1379 int s;
1384 1380
1385 end = sc->sc_ebuf; 1381 end = sc->sc_ebuf;
1386 get = sc->sc_rbget; 1382 get = sc->sc_rbget;
1387 scc = cc = sscom_rbuf_size - sc->sc_rbavail; 1383 scc = cc = sscom_rbuf_size - sc->sc_rbavail;
1388 1384
1389 if (cc == sscom_rbuf_size) { 1385 if (cc == sscom_rbuf_size) {
1390 sc->sc_floods++; 1386 sc->sc_floods++;
1391 if (sc->sc_errors++ == 0) 1387 if (sc->sc_errors++ == 0)
1392 callout_reset(&sc->sc_diag_callout, 60 * hz, 1388 callout_reset(&sc->sc_diag_callout, 60 * hz,
1393 sscomdiag, sc); 1389 sscomdiag, sc);
1394 } 1390 }
1395 1391
1396 while (cc) { 1392 while (cc) {
1397 code = get[0]; 1393 code = get[0];
1398 rsr = get[1]; 1394 rsr = get[1];
1399 if (rsr) { 1395 if (rsr) {
1400 if (ISSET(rsr, UERSTAT_OVERRUN)) { 1396 if (ISSET(rsr, UERSTAT_OVERRUN)) {
1401 sc->sc_overflows++; 1397 sc->sc_overflows++;
1402 if (sc->sc_errors++ == 0) 1398 if (sc->sc_errors++ == 0)
1403 callout_reset(&sc->sc_diag_callout, 1399 callout_reset(&sc->sc_diag_callout,
1404 60 * hz, sscomdiag, sc); 1400 60 * hz, sscomdiag, sc);
1405 } 1401 }
1406 if (ISSET(rsr, UERSTAT_BREAK | UERSTAT_FRAME)) 1402 if (ISSET(rsr, UERSTAT_BREAK | UERSTAT_FRAME))
1407 SET(code, TTY_FE); 1403 SET(code, TTY_FE);
1408 if (ISSET(rsr, UERSTAT_PARITY)) 1404 if (ISSET(rsr, UERSTAT_PARITY))
1409 SET(code, TTY_PE); 1405 SET(code, TTY_PE);
1410 } 1406 }
1411 if ((*rint)(code, tp) == -1) { 1407 if ((*rint)(code, tp) == -1) {
1412 /* 1408 /*
1413 * The line discipline's buffer is out of space. 1409 * The line discipline's buffer is out of space.
1414 */ 1410 */
1415 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1411 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) {
1416 /* 1412 /*
1417 * We're either not using flow control, or the 1413 * We're either not using flow control, or the
1418 * line discipline didn't tell us to block for 1414 * line discipline didn't tell us to block for
1419 * some reason. Either way, we have no way to 1415 * some reason. Either way, we have no way to
1420 * know when there's more space available, so 1416 * know when there's more space available, so
1421 * just drop the rest of the data. 1417 * just drop the rest of the data.
1422 */ 1418 */
1423 get += cc << 1; 1419 get += cc << 1;
1424 if (get >= end) 1420 if (get >= end)
1425 get -= sscom_rbuf_size << 1; 1421 get -= sscom_rbuf_size << 1;
1426 cc = 0; 1422 cc = 0;
1427 } else { 1423 } else {
1428 /* 1424 /*
1429 * Don't schedule any more receive processing 1425 * Don't schedule any more receive processing
1430 * until the line discipline tells us there's 1426 * until the line discipline tells us there's
1431 * space available (through sscomhwiflow()). 1427 * space available (through sscomhwiflow()).
1432 * Leave the rest of the data in the input 1428 * Leave the rest of the data in the input
1433 * buffer. 1429 * buffer.
1434 */ 1430 */
1435 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1431 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED);
1436 } 1432 }
1437 break; 1433 break;
1438 } 1434 }
1439 get += 2; 1435 get += 2;
1440 if (get >= end) 1436 if (get >= end)
1441 get = sc->sc_rbuf; 1437 get = sc->sc_rbuf;
1442 cc--; 1438 cc--;
1443 } 1439 }
1444 1440
1445 if (cc != scc) { 1441 if (cc != scc) {
1446 sc->sc_rbget = get; 1442 sc->sc_rbget = get;
1447 s = splserial(); 1443 s = splserial();
1448 SSCOM_LOCK(sc); 1444 SSCOM_LOCK(sc);
1449  1445
1450 cc = sc->sc_rbavail += scc - cc; 1446 cc = sc->sc_rbavail += scc - cc;
1451 /* Buffers should be ok again, release possible block. */ 1447 /* Buffers should be ok again, release possible block. */
1452 if (cc >= sc->sc_r_lowat) { 1448 if (cc >= sc->sc_r_lowat) {
1453 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1449 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) {
1454 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1450 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED);
1455 sscom_enable_rxint(sc); 1451 sscom_enable_rxint(sc);
1456 sc->sc_ucon |= UCON_ERRINT; 1452 sc->sc_ucon |= UCON_ERRINT;
1457 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSCOM_UCON,  1453 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSCOM_UCON,
1458 sc->sc_ucon); 1454 sc->sc_ucon);
1459 1455
1460 } 1456 }
1461 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1457 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) {
1462 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1458 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED);
1463 sscom_hwiflow(sc); 1459 sscom_hwiflow(sc);
1464 } 1460 }
1465 } 1461 }
1466 SSCOM_UNLOCK(sc); 1462 SSCOM_UNLOCK(sc);
1467 splx(s); 1463 splx(s);
1468 } 1464 }
1469} 1465}
1470 1466
1471integrate void 1467integrate void
1472sscom_txsoft(struct sscom_softc *sc, struct tty *tp) 1468sscom_txsoft(struct sscom_softc *sc, struct tty *tp)
1473{ 1469{
1474 1470
1475 CLR(tp->t_state, TS_BUSY); 1471 CLR(tp->t_state, TS_BUSY);
1476 if (ISSET(tp->t_state, TS_FLUSH)) 1472 if (ISSET(tp->t_state, TS_FLUSH))
1477 CLR(tp->t_state, TS_FLUSH); 1473 CLR(tp->t_state, TS_FLUSH);
1478 else 1474 else
1479 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1475 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf));
1480 (*tp->t_linesw->l_start)(tp); 1476 (*tp->t_linesw->l_start)(tp);
1481} 1477}
1482 1478
1483integrate void 1479integrate void
1484sscom_stsoft(struct sscom_softc *sc, struct tty *tp) 1480sscom_stsoft(struct sscom_softc *sc, struct tty *tp)
1485{ 1481{
1486 u_char msr, delta; 1482 u_char msr, delta;
1487 int s; 1483 int s;
1488 1484
1489 s = splserial(); 1485 s = splserial();
1490 SSCOM_LOCK(sc); 1486 SSCOM_LOCK(sc);
1491 msr = sc->sc_msts; 1487 msr = sc->sc_msts;
1492 delta = sc->sc_msr_delta; 1488 delta = sc->sc_msr_delta;
1493 sc->sc_msr_delta = 0; 1489 sc->sc_msr_delta = 0;
1494 SSCOM_UNLOCK(sc);  1490 SSCOM_UNLOCK(sc);
1495 splx(s); 1491 splx(s);
1496 1492
1497 if (ISSET(delta, sc->sc_msr_dcd)) { 1493 if (ISSET(delta, sc->sc_msr_dcd)) {
1498 /* 1494 /*
1499 * Inform the tty layer that carrier detect changed. 1495 * Inform the tty layer that carrier detect changed.
1500 */ 1496 */
1501 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSTS_DCD)); 1497 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSTS_DCD));
1502 } 1498 }
1503 1499
1504 if (ISSET(delta, sc->sc_msr_cts)) { 1500 if (ISSET(delta, sc->sc_msr_cts)) {
1505 /* Block or unblock output according to flow control. */ 1501 /* Block or unblock output according to flow control. */
1506 if (ISSET(msr, sc->sc_msr_cts)) { 1502 if (ISSET(msr, sc->sc_msr_cts)) {
1507 sc->sc_tx_stopped = 0; 1503 sc->sc_tx_stopped = 0;
1508 (*tp->t_linesw->l_start)(tp); 1504 (*tp->t_linesw->l_start)(tp);
1509 } else { 1505 } else {
1510 sc->sc_tx_stopped = 1; 1506 sc->sc_tx_stopped = 1;
1511 } 1507 }
1512 } 1508 }
1513 1509
1514 if (sscom_debug) 1510 if (sscom_debug)
1515 sscomstatus(sc, "sscom_stsoft"); 1511 sscomstatus(sc, "sscom_stsoft");
1516} 1512}
1517 1513
1518void 1514void
1519sscomsoft(void *arg) 1515sscomsoft(void *arg)
1520{ 1516{
1521 struct sscom_softc *sc = arg; 1517 struct sscom_softc *sc = arg;
1522 struct tty *tp; 1518 struct tty *tp;
1523 1519
1524 if (SSCOM_ISALIVE(sc) == 0) 1520 if (SSCOM_ISALIVE(sc) == 0)
1525 return; 1521 return;
1526 1522
1527 { 1523 {
1528 tp = sc->sc_tty; 1524 tp = sc->sc_tty;
1529  1525
1530 if (sc->sc_rx_ready) { 1526 if (sc->sc_rx_ready) {
1531 sc->sc_rx_ready = 0; 1527 sc->sc_rx_ready = 0;
1532 sscom_rxsoft(sc, tp); 1528 sscom_rxsoft(sc, tp);
1533 } 1529 }
1534 1530
1535 if (sc->sc_st_check) { 1531 if (sc->sc_st_check) {
1536 sc->sc_st_check = 0; 1532 sc->sc_st_check = 0;
1537 sscom_stsoft(sc, tp); 1533 sscom_stsoft(sc, tp);
1538 } 1534 }
1539 1535
1540 if (sc->sc_tx_done) { 1536 if (sc->sc_tx_done) {
1541 sc->sc_tx_done = 0; 1537 sc->sc_tx_done = 0;
1542 sscom_txsoft(sc, tp); 1538 sscom_txsoft(sc, tp);
1543 } 1539 }
1544 } 1540 }
1545} 1541}
1546 1542
1547 1543
1548int 1544int
1549sscomrxintr(void *arg) 1545sscomrxintr(void *arg)
1550{ 1546{
1551 struct sscom_softc *sc = arg; 1547 struct sscom_softc *sc = arg;
1552 bus_space_tag_t iot = sc->sc_iot; 1548 bus_space_tag_t iot = sc->sc_iot;
1553 bus_space_handle_t ioh = sc->sc_ioh; 1549 bus_space_handle_t ioh = sc->sc_ioh;
1554 u_char *put, *end; 1550 u_char *put, *end;
1555 u_int cc; 1551 u_int cc;
1556 1552
1557 if (SSCOM_ISALIVE(sc) == 0) 1553 if (SSCOM_ISALIVE(sc) == 0)
1558 return 0; 1554 return 0;
1559 1555
1560 SSCOM_LOCK(sc); 1556 SSCOM_LOCK(sc);
1561 1557
1562 end = sc->sc_ebuf; 1558 end = sc->sc_ebuf;
1563 put = sc->sc_rbput; 1559 put = sc->sc_rbput;
1564 cc = sc->sc_rbavail; 1560 cc = sc->sc_rbavail;
1565 1561
1566 do { 1562 do {
1567 u_char msts, delta; 1563 u_char msts, delta;
1568 u_char uerstat; 1564 u_char uerstat;
1569 uint32_t ufstat; 1565 uint32_t ufstat;
1570 1566
1571 ufstat = bus_space_read_4(iot, ioh, SSCOM_UFSTAT); 1567 ufstat = bus_space_read_4(iot, ioh, SSCOM_UFSTAT);
1572 1568
1573 /* XXX: break interrupt with no character? */ 1569 /* XXX: break interrupt with no character? */
1574 1570
1575 if ( (ufstat & (UFSTAT_RXCOUNT|UFSTAT_RXFULL)) && 1571 if ( (ufstat & (UFSTAT_RXCOUNT|UFSTAT_RXFULL)) &&
1576 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1572 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) {
1577 1573
1578 while (cc > 0) { 1574 while (cc > 0) {
1579 int cn_trapped = 0; 1575 int cn_trapped = 0;
1580 1576
1581 /* get status and received character. 1577 /* get status and received character.
1582 read status register first */ 1578 read status register first */
1583 uerstat = sscom_geterr(iot, ioh); 1579 uerstat = sscom_geterr(iot, ioh);
1584 put[0] = sscom_getc(iot, ioh); 1580 put[0] = sscom_getc(iot, ioh);
1585 1581
1586 if (ISSET(uerstat, UERSTAT_BREAK)) { 1582 if (ISSET(uerstat, UERSTAT_BREAK)) {
1587 int con_trapped = 0; 1583 int con_trapped = 0;
1588 cn_check_magic(sc->sc_tty->t_dev, 1584 cn_check_magic(sc->sc_tty->t_dev,
1589 CNC_BREAK, sscom_cnm_state); 1585 CNC_BREAK, sscom_cnm_state);
1590 if (con_trapped) 1586 if (con_trapped)
1591 continue; 1587 continue;
1592#if defined(KGDB) 1588#if defined(KGDB)
1593 if (ISSET(sc->sc_hwflags, 1589 if (ISSET(sc->sc_hwflags,
1594 SSCOM_HW_KGDB)) { 1590 SSCOM_HW_KGDB)) {
1595 kgdb_connect(1); 1591 kgdb_connect(1);
1596 continue; 1592 continue;
1597 } 1593 }
1598#endif 1594#endif
1599 } 1595 }
1600 1596
1601 put[1] = uerstat; 1597 put[1] = uerstat;
1602 cn_check_magic(sc->sc_tty->t_dev, 1598 cn_check_magic(sc->sc_tty->t_dev,
1603 put[0], sscom_cnm_state); 1599 put[0], sscom_cnm_state);
1604 if (!cn_trapped) { 1600 if (!cn_trapped) {
1605 put += 2; 1601 put += 2;
1606 if (put >= end) 1602 if (put >= end)
1607 put = sc->sc_rbuf; 1603 put = sc->sc_rbuf;
1608 cc--; 1604 cc--;
1609 } 1605 }
1610 1606
1611 ufstat = bus_space_read_4(iot, ioh, SSCOM_UFSTAT); 1607 ufstat = bus_space_read_4(iot, ioh, SSCOM_UFSTAT);
1612 if ( (ufstat & (UFSTAT_RXFULL|UFSTAT_RXCOUNT)) == 0 ) 1608 if ( (ufstat & (UFSTAT_RXFULL|UFSTAT_RXCOUNT)) == 0 )
1613 break; 1609 break;
1614 } 1610 }
1615 1611
1616 /* 1612 /*
1617 * Current string of incoming characters ended because 1613 * Current string of incoming characters ended because
1618 * no more data was available or we ran out of space. 1614 * no more data was available or we ran out of space.
1619 * Schedule a receive event if any data was received. 1615 * Schedule a receive event if any data was received.
1620 * If we're out of space, turn off receive interrupts. 1616 * If we're out of space, turn off receive interrupts.
1621 */ 1617 */
1622 sc->sc_rbput = put; 1618 sc->sc_rbput = put;
1623 sc->sc_rbavail = cc; 1619 sc->sc_rbavail = cc;
1624 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 1620 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED))
1625 sc->sc_rx_ready = 1; 1621 sc->sc_rx_ready = 1;
1626 1622
1627 /* 1623 /*
1628 * See if we are in danger of overflowing a buffer. If 1624 * See if we are in danger of overflowing a buffer. If
1629 * so, use hardware flow control to ease the pressure. 1625 * so, use hardware flow control to ease the pressure.
1630 */ 1626 */
1631 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 1627 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) &&
1632 cc < sc->sc_r_hiwat) { 1628 cc < sc->sc_r_hiwat) {
1633 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1629 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED);
1634 sscom_hwiflow(sc); 1630 sscom_hwiflow(sc);
1635 } 1631 }
1636 1632
1637 /* 1633 /*
1638 * If we're out of space, disable receive interrupts 1634 * If we're out of space, disable receive interrupts
1639 * until the queue has drained a bit. 1635 * until the queue has drained a bit.
1640 */ 1636 */
1641 if (!cc) { 1637 if (!cc) {
1642 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1638 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED);
1643 sscom_disable_rxint(sc); 1639 sscom_disable_rxint(sc);
1644 sc->sc_ucon &= ~UCON_ERRINT; 1640 sc->sc_ucon &= ~UCON_ERRINT;
1645 bus_space_write_4(iot, ioh, SSCOM_UCON, sc->sc_ucon); 1641 bus_space_write_4(iot, ioh, SSCOM_UCON, sc->sc_ucon);
1646 } 1642 }
1647 } 1643 }
1648 1644
1649 1645
1650 msts = sc->sc_read_modem_status(sc); 1646 msts = sc->sc_read_modem_status(sc);
1651 delta = msts ^ sc->sc_msts; 1647 delta = msts ^ sc->sc_msts;
1652 sc->sc_msts = msts; 1648 sc->sc_msts = msts;
1653 1649
1654#ifdef notyet 1650#ifdef notyet
1655 /* 1651 /*
1656 * Pulse-per-second (PSS) signals on edge of DCD? 1652 * Pulse-per-second (PSS) signals on edge of DCD?
1657 * Process these even if line discipline is ignoring DCD. 1653 * Process these even if line discipline is ignoring DCD.
1658 */ 1654 */
1659 if (delta & sc->sc_ppsmask) { 1655 if (delta & sc->sc_ppsmask) {
1660 struct timeval tv; 1656 struct timeval tv;
1661 if ((msr & sc->sc_ppsmask) == sc->sc_ppsassert) { 1657 if ((msr & sc->sc_ppsmask) == sc->sc_ppsassert) {
1662 /* XXX nanotime() */ 1658 /* XXX nanotime() */
1663 microtime(&tv); 1659 microtime(&tv);
1664 TIMEVAL_TO_TIMESPEC(&tv,  1660 TIMEVAL_TO_TIMESPEC(&tv,
1665 &sc->ppsinfo.assert_timestamp); 1661 &sc->ppsinfo.assert_timestamp);
1666 if (sc->ppsparam.mode & PPS_OFFSETASSERT) { 1662 if (sc->ppsparam.mode & PPS_OFFSETASSERT) {
1667 timespecadd(&sc->ppsinfo.assert_timestamp, 1663 timespecadd(&sc->ppsinfo.assert_timestamp,
1668 &sc->ppsparam.assert_offset, 1664 &sc->ppsparam.assert_offset,
1669 &sc->ppsinfo.assert_timestamp); 1665 &sc->ppsinfo.assert_timestamp);
1670 } 1666 }
1671 1667
1672#ifdef PPS_SYNC 1668#ifdef PPS_SYNC
1673 if (sc->ppsparam.mode & PPS_HARDPPSONASSERT) 1669 if (sc->ppsparam.mode & PPS_HARDPPSONASSERT)
1674 hardpps(&tv, tv.tv_usec); 1670 hardpps(&tv, tv.tv_usec);
1675#endif 1671#endif
1676 sc->ppsinfo.assert_sequence++; 1672 sc->ppsinfo.assert_sequence++;
1677 sc->ppsinfo.current_mode = sc->ppsparam.mode; 1673 sc->ppsinfo.current_mode = sc->ppsparam.mode;
1678 1674
1679 } else if ((msr & sc->sc_ppsmask) == sc->sc_ppsclear) { 1675 } else if ((msr & sc->sc_ppsmask) == sc->sc_ppsclear) {
1680 /* XXX nanotime() */ 1676 /* XXX nanotime() */
1681 microtime(&tv); 1677 microtime(&tv);
1682 TIMEVAL_TO_TIMESPEC(&tv,  1678 TIMEVAL_TO_TIMESPEC(&tv,
1683 &sc->ppsinfo.clear_timestamp); 1679 &sc->ppsinfo.clear_timestamp);
1684 if (sc->ppsparam.mode & PPS_OFFSETCLEAR) { 1680 if (sc->ppsparam.mode & PPS_OFFSETCLEAR) {
1685 timespecadd(&sc->ppsinfo.clear_timestamp, 1681 timespecadd(&sc->ppsinfo.clear_timestamp,
1686 &sc->ppsparam.clear_offset, 1682 &sc->ppsparam.clear_offset,
1687 &sc->ppsinfo.clear_timestamp); 1683 &sc->ppsinfo.clear_timestamp);
1688 } 1684 }
1689 1685
1690#ifdef PPS_SYNC 1686#ifdef PPS_SYNC
1691 if (sc->ppsparam.mode & PPS_HARDPPSONCLEAR) 1687 if (sc->ppsparam.mode & PPS_HARDPPSONCLEAR)
1692 hardpps(&tv, tv.tv_usec); 1688 hardpps(&tv, tv.tv_usec);
1693#endif 1689#endif
1694 sc->ppsinfo.clear_sequence++; 1690 sc->ppsinfo.clear_sequence++;
1695 sc->ppsinfo.current_mode = sc->ppsparam.mode; 1691 sc->ppsinfo.current_mode = sc->ppsparam.mode;
1696 } 1692 }
1697 } 1693 }
1698#endif 1694#endif
1699 1695
1700 /* 1696 /*
1701 * Process normal status changes 1697 * Process normal status changes
1702 */ 1698 */
1703 if (ISSET(delta, sc->sc_msr_mask)) { 1699 if (ISSET(delta, sc->sc_msr_mask)) {
1704 SET(sc->sc_msr_delta, delta); 1700 SET(sc->sc_msr_delta, delta);
1705 1701
1706 /* 1702 /*
1707 * Stop output immediately if we lose the output 1703 * Stop output immediately if we lose the output
1708 * flow control signal or carrier detect. 1704 * flow control signal or carrier detect.
1709 */ 1705 */
1710 if (ISSET(~msts, sc->sc_msr_mask)) { 1706 if (ISSET(~msts, sc->sc_msr_mask)) {
1711 sc->sc_tbc = 0; 1707 sc->sc_tbc = 0;
1712 sc->sc_heldtbc = 0; 1708 sc->sc_heldtbc = 0;
1713#ifdef SSCOM_DEBUG 1709#ifdef SSCOM_DEBUG
1714 if (sscom_debug) 1710 if (sscom_debug)
1715 sscomstatus(sc, "sscomintr "); 1711 sscomstatus(sc, "sscomintr ");
1716#endif 1712#endif
1717 } 1713 }
1718 1714
1719 sc->sc_st_check = 1; 1715 sc->sc_st_check = 1;
1720 } 1716 }
1721 1717
1722 /*  1718 /*
1723 * Done handling any receive interrupts.  1719 * Done handling any receive interrupts.
1724 */ 1720 */
1725 1721
1726 /* 1722 /*
1727 * If we've delayed a parameter change, do it 1723 * If we've delayed a parameter change, do it
1728 * now, and restart * output. 1724 * now, and restart * output.
1729 */ 1725 */
1730 if ((ufstat & UFSTAT_TXCOUNT) == 0) { 1726 if ((ufstat & UFSTAT_TXCOUNT) == 0) {
1731 /* XXX: we should check transmitter empty also */ 1727 /* XXX: we should check transmitter empty also */
1732 1728
1733 if (sc->sc_heldchange) { 1729 if (sc->sc_heldchange) {
1734 sscom_loadchannelregs(sc); 1730 sscom_loadchannelregs(sc);
1735 sc->sc_heldchange = 0; 1731 sc->sc_heldchange = 0;
1736 sc->sc_tbc = sc->sc_heldtbc; 1732 sc->sc_tbc = sc->sc_heldtbc;
1737 sc->sc_heldtbc = 0; 1733 sc->sc_heldtbc = 0;
1738 } 1734 }
1739 } 1735 }
1740 1736
1741 1737
1742 } while (0); 1738 } while (0);
1743 1739
1744 SSCOM_UNLOCK(sc); 1740 SSCOM_UNLOCK(sc);
1745 1741
1746 /* Wake up the poller. */ 1742 /* Wake up the poller. */
1747 softint_schedule(sc->sc_si); 1743 softint_schedule(sc->sc_si);
1748 1744
1749#ifdef RND_COM 1745#ifdef RND_COM
1750 rnd_add_uint32(&sc->rnd_source, iir | rsr); 1746 rnd_add_uint32(&sc->rnd_source, iir | rsr);
1751#endif 1747#endif
1752 1748
1753 return 1; 1749 return 1;
1754} 1750}
1755 1751
1756int 1752int
1757sscomtxintr(void *arg) 1753sscomtxintr(void *arg)
1758{ 1754{
1759 struct sscom_softc *sc = arg; 1755 struct sscom_softc *sc = arg;
1760 bus_space_tag_t iot = sc->sc_iot; 1756 bus_space_tag_t iot = sc->sc_iot;
1761 bus_space_handle_t ioh = sc->sc_ioh; 1757 bus_space_handle_t ioh = sc->sc_ioh;
1762 uint32_t ufstat; 1758 uint32_t ufstat;
1763 1759
1764 if (SSCOM_ISALIVE(sc) == 0) 1760 if (SSCOM_ISALIVE(sc) == 0)
1765 return 0; 1761 return 0;
1766 1762
1767 SSCOM_LOCK(sc); 1763 SSCOM_LOCK(sc);
1768 1764
1769 ufstat = bus_space_read_4(iot, ioh, SSCOM_UFSTAT); 1765 ufstat = bus_space_read_4(iot, ioh, SSCOM_UFSTAT);
1770 1766
1771 /* 1767 /*
1772 * If we've delayed a parameter change, do it 1768 * If we've delayed a parameter change, do it
1773 * now, and restart * output. 1769 * now, and restart * output.
1774 */ 1770 */
1775 if (sc->sc_heldchange && (ufstat & UFSTAT_TXCOUNT) == 0) { 1771 if (sc->sc_heldchange && (ufstat & UFSTAT_TXCOUNT) == 0) {
1776 /* XXX: we should check transmitter empty also */ 1772 /* XXX: we should check transmitter empty also */
1777 sscom_loadchannelregs(sc); 1773 sscom_loadchannelregs(sc);
1778 sc->sc_heldchange = 0; 1774 sc->sc_heldchange = 0;
1779 sc->sc_tbc = sc->sc_heldtbc; 1775 sc->sc_tbc = sc->sc_heldtbc;
1780 sc->sc_heldtbc = 0; 1776 sc->sc_heldtbc = 0;
1781 } 1777 }
1782 1778
1783 /* 1779 /*
1784 * See if data can be transmitted as well. Schedule tx 1780 * See if data can be transmitted as well. Schedule tx
1785 * done event if no data left and tty was marked busy. 1781 * done event if no data left and tty was marked busy.
1786 */ 1782 */
1787 if (!ISSET(ufstat,UFSTAT_TXFULL)) { 1783 if (!ISSET(ufstat,UFSTAT_TXFULL)) {
1788 /*  1784 /*
1789 * Output the next chunk of the contiguous 1785 * Output the next chunk of the contiguous
1790 * buffer, if any. 1786 * buffer, if any.
1791 */ 1787 */
1792 if (sc->sc_tbc > 0) { 1788 if (sc->sc_tbc > 0) {
1793 __sscom_output_chunk(sc, ufstat); 1789 __sscom_output_chunk(sc, ufstat);
1794 } 1790 }
1795 else { 1791 else {
1796 /* 1792 /*
1797 * Disable transmit sscompletion 1793 * Disable transmit sscompletion
1798 * interrupts if necessary. 1794 * interrupts if necessary.
1799 */ 1795 */
1800 if (sc->sc_hwflags & SSCOM_HW_TXINT) 1796 if (sc->sc_hwflags & SSCOM_HW_TXINT)
1801 sscom_disable_txint(sc); 1797 sscom_disable_txint(sc);
1802 if (sc->sc_tx_busy) { 1798 if (sc->sc_tx_busy) {
1803 sc->sc_tx_busy = 0; 1799 sc->sc_tx_busy = 0;
1804 sc->sc_tx_done = 1; 1800 sc->sc_tx_done = 1;
1805 } 1801 }
1806 } 1802 }
1807 } 1803 }
1808 1804
1809 SSCOM_UNLOCK(sc); 1805 SSCOM_UNLOCK(sc);
1810 1806
1811 /* Wake up the poller. */ 1807 /* Wake up the poller. */
1812 softint_schedule(sc->sc_si); 1808 softint_schedule(sc->sc_si);
1813 1809
1814#ifdef RND_COM 1810#ifdef RND_COM
1815 rnd_add_uint32(&sc->rnd_source, iir | rsr); 1811 rnd_add_uint32(&sc->rnd_source, iir | rsr);
1816#endif 1812#endif
1817 1813
1818 return 1; 1814 return 1;
1819} 1815}
1820 1816
1821int 1817int
1822sscomintr(void *v) 1818sscomintr(void *v)
1823{ 1819{
1824 struct sscom_softc *sc = v; 1820 struct sscom_softc *sc = v;
1825 int clear = 0; 1821 int clear = 0;
1826 1822
1827 if (sscomrxintr(v)) 1823 if (sscomrxintr(v))
1828 clear |= SSCOM_HW_RXINT; 1824 clear |= SSCOM_HW_RXINT;
1829 if (sscomtxintr(v)) 1825 if (sscomtxintr(v))
1830 clear |= SSCOM_HW_TXINT; 1826 clear |= SSCOM_HW_TXINT;
1831 1827
1832 if (clear) 1828 if (clear)
1833 sc->sc_clear_interrupts(sc, clear); 1829 sc->sc_clear_interrupts(sc, clear);
1834 1830
1835 return clear? 1: 0; 1831 return clear? 1: 0;
1836} 1832}
1837 1833
1838 1834
1839#if defined(KGDB) || \ 
1840 defined(SSCOM0CONSOLE) || defined(SSCOM1CONSOLE) || \ 
1841 defined(SSCOM2CONSOLE) || defined(SSCOM3CONSOLE) 
1842/* 1835/*
1843 * Initialize UART for use as console or KGDB line. 1836 * Initialize UART for use as console or KGDB line.
1844 */ 1837 */
1845static int 1838static int
1846sscom_init(bus_space_tag_t iot, bus_space_handle_t base_ioh, 1839sscom_init(bus_space_tag_t iot, bus_space_handle_t base_ioh,
1847 const struct sscom_uart_info *config, 1840 const struct sscom_uart_info *config,
1848 int rate, int frequency, tcflag_t cflag, bus_space_handle_t *iohp) 1841 int rate, int frequency, tcflag_t cflag, bus_space_handle_t *iohp)
1849{ 1842{
1850 bus_space_handle_t ioh; 1843 bus_space_handle_t ioh;
1851 bus_addr_t iobase = config->iobase; 1844 bus_addr_t iobase = config->iobase;
1852 int timo = 150000; 1845 int timo = 150000;
1853 1846
1854 bus_space_subregion(iot, base_ioh, iobase, SSCOM_SIZE, &ioh); 1847 bus_space_subregion(iot, base_ioh, iobase, SSCOM_SIZE, &ioh);
1855 1848
1856 /* wait until all is transmitted until we enable this device */ 1849 /* wait until all is transmitted until we enable this device */
1857 while (!(bus_space_read_4(iot, ioh, SSCOM_UTRSTAT) & 1850 while (!(bus_space_read_4(iot, ioh, SSCOM_UTRSTAT) &
1858 UTRSTAT_TXSHIFTER_EMPTY) && --timo); 1851 UTRSTAT_TXSHIFTER_EMPTY) && --timo);
1859 1852
1860 /* reset UART control */ 1853 /* reset UART control */
1861 bus_space_write_4(iot, ioh, SSCOM_UCON, 0); 1854 bus_space_write_4(iot, ioh, SSCOM_UCON, 0);
1862 1855
1863 /* set RX/TX trigger to half values */ 1856 /* set RX/TX trigger to half values */
1864 bus_space_write_4(iot, ioh, SSCOM_UFCON, 1857 bus_space_write_4(iot, ioh, SSCOM_UFCON,
1865 __SHIFTIN(4, UFCON_TXTRIGGER) | 1858 __SHIFTIN(4, UFCON_TXTRIGGER) |
1866 __SHIFTIN(4, UFCON_RXTRIGGER) | 1859 __SHIFTIN(4, UFCON_RXTRIGGER) |
1867 UFCON_FIFO_ENABLE |  1860 UFCON_FIFO_ENABLE |
1868 UFCON_TXFIFO_RESET| 1861 UFCON_TXFIFO_RESET|
1869 UFCON_RXFIFO_RESET); 1862 UFCON_RXFIFO_RESET);
1870 /* tx/rx fifo reset are auto-cleared */ 1863 /* tx/rx fifo reset are auto-cleared */
1871 1864
1872 rate = sscomspeed(rate, frequency); 1865 rate = sscomspeed(rate, frequency);
1873 bus_space_write_4(iot, ioh, SSCOM_UBRDIV, rate); 1866 bus_space_write_4(iot, ioh, SSCOM_UBRDIV, rate);
1874 bus_space_write_4(iot, ioh, SSCOM_ULCON, cflag2lcr(cflag)); 1867 bus_space_write_4(iot, ioh, SSCOM_ULCON, cflag2lcr(cflag));
1875 1868
1876 /* enable UART */ 1869 /* enable UART */
1877 bus_space_write_4(iot, ioh, SSCOM_UCON,  1870 bus_space_write_4(iot, ioh, SSCOM_UCON,
1878 UCON_TXMODE_INT|UCON_RXMODE_INT); 1871 UCON_TXMODE_INT|UCON_RXMODE_INT);
1879 bus_space_write_4(iot, ioh, SSCOM_UMCON, UMCON_RTS); 1872 bus_space_write_4(iot, ioh, SSCOM_UMCON, UMCON_RTS);
1880 1873
1881 *iohp = ioh; 1874 *iohp = ioh;
1882 return 0; 1875 return 0;
1883} 1876}
1884 1877
1885#endif 
1886 
1887#if \ 
1888 defined(SSCOM0CONSOLE) || defined(SSCOM1CONSOLE) || \ 
1889 defined(SSCOM2CONSOLE) || defined(SSCOM3CONSOLE) 
1890/* 1878/*
1891 * Following are all routines needed for SSCOM to act as console 1879 * Following are all routines needed for SSCOM to act as console
1892 */ 1880 */
1893struct consdev sscomcons = { 1881struct consdev sscomcons = {
1894 NULL, NULL, sscomcngetc, sscomcnputc, sscomcnpollc, NULL, 1882 NULL, NULL, sscomcngetc, sscomcnputc, sscomcnpollc, NULL,
1895 NULL, NULL, NODEV, CN_NORMAL 1883 NULL, NULL, NODEV, CN_NORMAL
1896}; 1884};
1897 1885
1898 1886
1899int 1887int
1900sscom_cnattach(bus_space_tag_t iot, bus_space_handle_t ioh, 1888sscom_cnattach(bus_space_tag_t iot, bus_space_handle_t ioh,
1901 const struct sscom_uart_info *config, 1889 const struct sscom_uart_info *config,
1902 int rate, int frequency, tcflag_t cflag) 1890 int rate, int frequency, tcflag_t cflag)
1903{ 1891{
1904 int res; 1892 int res;
1905 1893
1906 res = sscom_init(iot, ioh, config, rate, frequency, cflag, 1894 res = sscom_init(iot, ioh, config, rate, frequency, cflag,
1907 &sscomconsioh); 1895 &sscomconsioh);
1908 if (res) 1896 if (res)
1909 return res; 1897 return res;
1910 1898
1911 cn_tab = &sscomcons; 1899 cn_tab = &sscomcons;
1912 cn_init_magic(&sscom_cnm_state); 1900 cn_init_magic(&sscom_cnm_state);
1913 cn_set_magic("\047\001"); /* default magic is BREAK */ 1901 cn_set_magic("\047\001"); /* default magic is BREAK */
1914 1902
1915 sscomconstag = iot; 1903 sscomconstag = iot;
1916 sscomconsunit = config->unit; 1904 sscomconsunit = config->unit;
1917 sscomconsrate = rate; 1905 sscomconsrate = rate;
1918 sscomconscflag = cflag; 1906 sscomconscflag = cflag;
1919 1907
1920 return 0; 1908 return 0;
1921} 1909}
1922 1910
1923void 1911void
1924sscom_cndetach(void) 1912sscom_cndetach(void)
1925{ 1913{
1926 bus_space_unmap(sscomconstag, sscomconsioh, SSCOM_SIZE); 1914 bus_space_unmap(sscomconstag, sscomconsioh, SSCOM_SIZE);
1927 sscomconstag = NULL; 1915 sscomconstag = NULL;
1928 1916
1929 cn_tab = NULL; 1917 cn_tab = NULL;
1930} 1918}
1931 1919
1932/* 1920/*
1933 * The read-ahead code is so that you can detect pending in-band 1921 * The read-ahead code is so that you can detect pending in-band
1934 * cn_magic in polled mode while doing output rather than having to 1922 * cn_magic in polled mode while doing output rather than having to
1935 * wait until the kernel decides it needs input. 1923 * wait until the kernel decides it needs input.
1936 */ 1924 */
1937 1925
1938#define MAX_READAHEAD 20 1926#define MAX_READAHEAD 20
1939static int sscom_readahead[MAX_READAHEAD]; 1927static int sscom_readahead[MAX_READAHEAD];
1940static int sscom_readaheadcount = 0; 1928static int sscom_readaheadcount = 0;
1941 1929
1942int 1930int
1943sscomcngetc(dev_t dev) 1931sscomcngetc(dev_t dev)
1944{ 1932{
1945 int s = splserial(); 1933 int s = splserial();
1946 u_char __attribute__((__unused__)) stat; 1934 u_char __attribute__((__unused__)) stat;
1947 u_char c; 1935 u_char c;
1948 1936
1949 /* got a character from reading things earlier */ 1937 /* got a character from reading things earlier */
1950 if (sscom_readaheadcount > 0) { 1938 if (sscom_readaheadcount > 0) {
1951 int i; 1939 int i;
1952 1940
1953 c = sscom_readahead[0]; 1941 c = sscom_readahead[0];
1954 for (i = 1; i < sscom_readaheadcount; i++) { 1942 for (i = 1; i < sscom_readaheadcount; i++) {
1955 sscom_readahead[i-1] = sscom_readahead[i]; 1943 sscom_readahead[i-1] = sscom_readahead[i];
1956 } 1944 }
1957 sscom_readaheadcount--; 1945 sscom_readaheadcount--;
1958 splx(s); 1946 splx(s);
1959 return c; 1947 return c;
1960 } 1948 }
1961 1949
1962 /* block until a character becomes available */ 1950 /* block until a character becomes available */
1963 while (!sscom_rxrdy(sscomconstag, sscomconsioh)) 1951 while (!sscom_rxrdy(sscomconstag, sscomconsioh))
1964 ; 1952 ;
1965 1953
1966 c = sscom_getc(sscomconstag, sscomconsioh); 1954 c = sscom_getc(sscomconstag, sscomconsioh);
1967 stat = sscom_geterr(sscomconstag, sscomconsioh); 1955 stat = sscom_geterr(sscomconstag, sscomconsioh);
1968 { 1956 {
1969 int __attribute__((__unused__))cn_trapped = 0; 1957 int __attribute__((__unused__))cn_trapped = 0;
1970#ifdef DDB 1958#ifdef DDB
1971 extern int db_active; 1959 extern int db_active;
1972 if (!db_active) 1960 if (!db_active)
1973#endif 1961#endif
1974 cn_check_magic(dev, c, sscom_cnm_state); 1962 cn_check_magic(dev, c, sscom_cnm_state);
1975 } 1963 }
1976 splx(s); 1964 splx(s);
1977 return c; 1965 return c;
1978} 1966}
1979 1967
1980/* 1968/*
1981 * Console kernel output character routine. 1969 * Console kernel output character routine.
1982 */ 1970 */
1983void 1971void
1984sscomcnputc(dev_t dev, int c) 1972sscomcnputc(dev_t dev, int c)
1985{ 1973{
1986 int s = splserial(); 1974 int s = splserial();
1987 int timo; 1975 int timo;
1988 1976
1989 int cin; 1977 int cin;
1990 int __attribute__((__unused__)) stat; 1978 int __attribute__((__unused__)) stat;
1991 if (sscom_readaheadcount < MAX_READAHEAD &&  1979 if (sscom_readaheadcount < MAX_READAHEAD &&
1992 sscom_rxrdy(sscomconstag, sscomconsioh)) { 1980 sscom_rxrdy(sscomconstag, sscomconsioh)) {
1993  1981
1994 int __attribute__((__unused__))cn_trapped = 0; 1982 int __attribute__((__unused__))cn_trapped = 0;
1995 cin = sscom_getc(sscomconstag, sscomconsioh); 1983 cin = sscom_getc(sscomconstag, sscomconsioh);
1996 stat = sscom_geterr(sscomconstag, sscomconsioh); 1984 stat = sscom_geterr(sscomconstag, sscomconsioh);
1997 cn_check_magic(dev, cin, sscom_cnm_state); 1985 cn_check_magic(dev, cin, sscom_cnm_state);
1998 sscom_readahead[sscom_readaheadcount++] = cin; 1986 sscom_readahead[sscom_readaheadcount++] = cin;
1999 } 1987 }
2000 1988
2001 /* wait for any pending transmission to finish */ 1989 /* wait for any pending transmission to finish */
2002 timo = 150000; 1990 timo = 150000;
2003 while (ISSET(bus_space_read_4(sscomconstag, sscomconsioh, SSCOM_UFSTAT),  1991 while (ISSET(bus_space_read_4(sscomconstag, sscomconsioh, SSCOM_UFSTAT),
2004 UFSTAT_TXFULL) && --timo) 1992 UFSTAT_TXFULL) && --timo)
2005 continue; 1993 continue;
2006 1994
2007 bus_space_write_1(sscomconstag, sscomconsioh, SSCOM_UTXH, c); 1995 bus_space_write_1(sscomconstag, sscomconsioh, SSCOM_UTXH, c);
2008 SSCOM_BARRIER(sscomconstag, sscomconsioh, BR | BW); 1996 SSCOM_BARRIER(sscomconstag, sscomconsioh, BR | BW);
2009 1997
2010#if 0  1998#if 0
2011 /* wait for this transmission to complete */ 1999 /* wait for this transmission to complete */
2012 timo = 1500000; 2000 timo = 1500000;
2013 while (!ISSET(bus_space_read_4(sscomconstag, sscomconsioh, SSCOM_UTRSTAT),  2001 while (!ISSET(bus_space_read_4(sscomconstag, sscomconsioh, SSCOM_UTRSTAT),
2014 UTRSTAT_TXEMPTY) && --timo) 2002 UTRSTAT_TXEMPTY) && --timo)
2015 continue; 2003 continue;
2016#endif 2004#endif
2017 splx(s); 2005 splx(s);
2018} 2006}
2019 2007
2020void 2008void
2021sscomcnpollc(dev_t dev, int on) 2009sscomcnpollc(dev_t dev, int on)
2022{ 2010{
2023 2011
2024 sscom_readaheadcount = 0; 2012 sscom_readaheadcount = 0;
2025} 2013}
2026 2014
2027#endif /* SSCOM0CONSOLE||SSCOM1CONSOLE */ 
2028 
2029#ifdef KGDB 2015#ifdef KGDB
2030int 2016int
2031sscom_kgdb_attach(bus_space_tag_t iot, bus_space_handle_t ioh, 2017sscom_kgdb_attach(bus_space_tag_t iot, bus_space_handle_t ioh,
2032 const struct sscom_uart_info *config, 2018 const struct sscom_uart_info *config,
2033 int rate, int frequency, tcflag_t cflag) 2019 int rate, int frequency, tcflag_t cflag)
2034{ 2020{
2035 int res; 2021 int res;
2036 2022
2037 if (iot == sscomconstag && config->unit == sscomconsunit) { 2023 if (iot == sscomconstag && config->unit == sscomconsunit) {
2038 printf( "console==kgdb_port (%d): kgdb disabled\n", sscomconsunit); 2024 printf( "console==kgdb_port (%d): kgdb disabled\n", sscomconsunit);
2039 return EBUSY; /* cannot share with console */ 2025 return EBUSY; /* cannot share with console */
2040 } 2026 }
2041 2027
2042 res = sscom_init(iot, ioh, config, 2028 res = sscom_init(iot, ioh, config,
2043 rate, frequency, cflag, &sscom_kgdb_ioh); 2029 rate, frequency, cflag, &sscom_kgdb_ioh);
2044 if (res) 2030 if (res)
2045 return res; 2031 return res;
2046 2032
2047 kgdb_attach(sscom_kgdb_getc, sscom_kgdb_putc, NULL); 2033 kgdb_attach(sscom_kgdb_getc, sscom_kgdb_putc, NULL);
2048 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2034 kgdb_dev = 123; /* unneeded, only to satisfy some tests */
2049 2035
2050 sscom_kgdb_iot = iot; 2036 sscom_kgdb_iot = iot;
2051 sscom_kgdb_unit = config->unit; 2037 sscom_kgdb_unit = config->unit;
2052 2038
2053 return 0; 2039 return 0;
2054} 2040}
2055 2041
2056/* ARGSUSED */ 2042/* ARGSUSED */
2057int 2043int
2058sscom_kgdb_getc(void *arg) 2044sscom_kgdb_getc(void *arg)
2059{ 2045{
2060 int c, stat; 2046 int c, stat;
2061 2047
2062 /* block until a character becomes available */ 2048 /* block until a character becomes available */
2063 while (!sscom_rxrdy(sscom_kgdb_iot, sscom_kgdb_ioh)) 2049 while (!sscom_rxrdy(sscom_kgdb_iot, sscom_kgdb_ioh))
2064 ; 2050 ;
2065 2051
2066 c = sscom_getc(sscom_kgdb_iot, sscom_kgdb_ioh); 2052 c = sscom_getc(sscom_kgdb_iot, sscom_kgdb_ioh);
2067 stat = sscom_geterr(sscom_kgdb_iot, sscom_kgdb_ioh); 2053 stat = sscom_geterr(sscom_kgdb_iot, sscom_kgdb_ioh);
2068 2054
2069 return c; 2055 return c;
2070} 2056}
2071 2057
2072/* ARGSUSED */ 2058/* ARGSUSED */
2073void 2059void
2074sscom_kgdb_putc(void *arg, int c) 2060sscom_kgdb_putc(void *arg, int c)
2075{ 2061{
2076 int timo; 2062 int timo;
2077 2063
2078 /* wait for any pending transmission to finish */ 2064 /* wait for any pending transmission to finish */
2079 timo = 150000; 2065 timo = 150000;
2080 while (ISSET(bus_space_read_4(sscom_kgdb_iot, sscom_kgdb_ioh, 2066 while (ISSET(bus_space_read_4(sscom_kgdb_iot, sscom_kgdb_ioh,
2081 SSCOM_UFSTAT), UFSTAT_TXFULL) && --timo) 2067 SSCOM_UFSTAT), UFSTAT_TXFULL) && --timo)
2082 continue; 2068 continue;
2083 2069
2084 bus_space_write_1(sscom_kgdb_iot, sscom_kgdb_ioh, SSCOM_UTXH, c); 2070 bus_space_write_1(sscom_kgdb_iot, sscom_kgdb_ioh, SSCOM_UTXH, c);
2085 SSCOM_BARRIER(sscom_kgdb_iot, sscom_kgdb_ioh, BR | BW); 2071 SSCOM_BARRIER(sscom_kgdb_iot, sscom_kgdb_ioh, BR | BW);
2086 2072
2087#if 0  2073#if 0
2088 /* wait for this transmission to complete */ 2074 /* wait for this transmission to complete */
2089 timo = 1500000; 2075 timo = 1500000;
2090 while (!ISSET(bus_space_read_4(sscom_kgdb_iot, sscom_kgdb_ioh, 2076 while (!ISSET(bus_space_read_4(sscom_kgdb_iot, sscom_kgdb_ioh,
2091 SSCOM_UTRSTAT), UTRSTAT_TXEMPTY) && --timo) 2077 SSCOM_UTRSTAT), UTRSTAT_TXEMPTY) && --timo)
2092 continue; 2078 continue;
2093#endif 2079#endif
2094} 2080}
2095#endif /* KGDB */ 2081#endif /* KGDB */
2096 2082
2097/* helper function to identify the sscom ports used by 2083/* helper function to identify the sscom ports used by
2098 console or KGDB (and not yet autoconf attached) */ 2084 console or KGDB (and not yet autoconf attached) */
2099int 2085int
2100sscom_is_console(bus_space_tag_t iot, int unit, 2086sscom_is_console(bus_space_tag_t iot, int unit,
2101 bus_space_handle_t *ioh) 2087 bus_space_handle_t *ioh)
2102{ 2088{
2103 bus_space_handle_t help; 2089 bus_space_handle_t help;
2104 2090
2105 if (!sscomconsattached && 2091 if (!sscomconsattached &&
2106 iot == sscomconstag && unit == sscomconsunit) 2092 iot == sscomconstag && unit == sscomconsunit)
2107 help = sscomconsioh; 2093 help = sscomconsioh;
2108#ifdef KGDB 2094#ifdef KGDB
2109 else if (!sscom_kgdb_attached && 2095 else if (!sscom_kgdb_attached &&
2110 iot == sscom_kgdb_iot && unit == sscom_kgdb_unit) 2096 iot == sscom_kgdb_iot && unit == sscom_kgdb_unit)
2111 help = sscom_kgdb_ioh; 2097 help = sscom_kgdb_ioh;
2112#endif 2098#endif
2113 else 2099 else
2114 return 0; 2100 return 0;
2115 2101
2116 if (ioh) 2102 if (ioh)
2117 *ioh = help; 2103 *ioh = help;
2118 return 1; 2104 return 1;
2119} 2105}
2120 2106

cvs diff -r1.14 -r1.15 src/sys/arch/evbarm/conf/Attic/EXYNOS (switch to unified diff)

--- src/sys/arch/evbarm/conf/Attic/EXYNOS 2017/04/16 15:49:26 1.14
+++ src/sys/arch/evbarm/conf/Attic/EXYNOS 2017/06/10 15:13:19 1.15
@@ -1,301 +1,94 @@ @@ -1,301 +1,94 @@
1# 1#
2# $NetBSD: EXYNOS,v 1.14 2017/04/16 15:49:26 jmcneill Exp $ 2# $NetBSD: EXYNOS,v 1.15 2017/06/10 15:13:19 jmcneill Exp $
3# 3#
4# ODROID-XU -- ODROID-XU4 Exynos5422 based kernel 4# Samsung Exynos SoC kernel
5# 5#
6 6
7include "arch/evbarm/conf/std.exynos" 7include "arch/evbarm/conf/std.exynos"
 8include "arch/evbarm/conf/GENERIC.common"
8 9
9no makeoptions CPUFLAGS 
10makeoptions CPUFLAGS="-mcpu=cortex-a7 -mfpu=neon" 
11no makeoptions BOARDTYPE 
12makeoptions BOARDTYPE="hardkernel_odroid_xu4" 
13no makeoptions KERNEL_BASE_PHYS 
14no makeoptions KERNEL_BASE_VIRT 
15makeoptions KERNEL_BASE_PHYS="0x80000000" 
16makeoptions KERNEL_BASE_VIRT="0x80000000" 
17options PMAP_NEED_ALLOC_POOLPAGE 
18options MEMSIZE=2048 
19 
20# estimated number of users 
21 
22maxusers 8 
23 
24# Standard system options 
25 
26options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT 
27#options NTP # NTP phase/frequency locked loop 
28 
29# CPU options 
30options CPU_CORTEX 
31options CPU_CORTEXA7 10options CPU_CORTEXA7
32options CPU_CORTEXA15 11options CPU_CORTEXA15
33options EXYNOS5422 12options SOC_EXYNOS5422
34#options MULTIPROCESSOR 13options MULTIPROCESSOR
35 14
36options FDT # not really but soon 15pseudo-device openfirm # /dev/openfirm
37pseudo-device openfirm # jmcneill: oops, fdtbus should depend on 16
38 # openfirm. don't let me forget. 17#options DIAGNOSTIC # internal consistency checks
39 18#options DEBUG
40 19#options LOCKDEBUG
41options PMAPCOUNTERS 20#options PMAP_DEBUG # Enable pmap_debug_level code
42options BUSDMA_COUNTERS 
43options EXYNOS_CONSOLE_EARLY 
44#options UVMHIST 
45options USBHIST 
46options USBHIST_SIZE=100000 
47#options UVMHIST_PRINT,KERNHIST_DELAY=0 
48options __HAVE_MM_MD_DIRECT_MAPPED_PHYS 
49#options PMAP_NEED_ALLOC_POOLPAGE 
50 
51# Specify the memory size in megabytes (optional). 
52#options MEMSIZE=2048 
53 
54# File systems 
55file-system FFS # UFS 
56#file-system LFS # log-structured file system 
57file-system MFS # memory file system 
58file-system NFS # Network file system 
59#file-system ADOSFS # AmigaDOS-compatible file system 
60#file-system EXT2FS # second extended file system (linux) 
61#file-system CD9660 # ISO 9660 + Rock Ridge file system 
62file-system MSDOSFS # MS-DOS file system 
63#file-system FDESC # /dev/fd 
64file-system KERNFS # /kern 
65#file-system NULLFS # loopback file system 
66file-system PROCFS # /proc 
67#file-system PUFFS # Userspace file systems (e.g. ntfs-3g & sshfs) 
68#file-system UMAPFS # NULLFS + uid and gid remapping 
69#file-system UNION # union file system 
70file-system TMPFS # memory file system 
71file-system PTYFS # /dev/pts/N support 
72 
73# File system options 
74#options QUOTA # legacy UFS quotas 
75#options QUOTA2 # new, in-filesystem UFS quotas 
76#options DISKLABEL_EI # disklabel Endian Independent support 
77#options FFS_EI # FFS Endian Independent support 
78options NFSSERVER 
79options WAPBL # File system journaling support 
80#options FFS_NO_SNAPSHOT # No FFS snapshot support 
81 
82# Networking options 
83 
84#options GATEWAY # packet forwarding 
85options INET # IP + ICMP + TCP + UDP 
86options INET6 # IPV6 
87#options IPSEC # IP security 
88#options IPSEC_DEBUG # debug for IP security 
89#options MROUTING # IP multicast routing 
90#options PIM # Protocol Independent Multicast 
91#options NETATALK # AppleTalk networking 
92#options PPP_BSDCOMP # BSD-Compress compression support for PPP 
93#options PPP_DEFLATE # Deflate compression support for PPP 
94#options PPP_FILTER # Active filter support for PPP (requires bpf) 
95#options TCP_DEBUG # Record last TCP_NDEBUG packets with SO_DEBUG 
96 
97#options NFS_BOOT_BOOTP 
98#options NFS_BOOT_DHCP 
99#options NFS_BOOT_BOOTSTATIC 
100#options NFS_BOOTSTATIC_MYIP="\"192.168.0.22\"" 
101#options NFS_BOOTSTATIC_GWIP="\"192.168.0.1\"" 
102#options NFS_BOOTSTATIC_MASK="\"255.255.255.0\"" 
103#options NFS_BOOTSTATIC_SERVADDR="\"192.168.0.5\"" 
104#options NFS_BOOTSTATIC_SERVER="\"192.168.0.5:/stuff/nfs/odroid\"" 
105 
106#options NFS_BOOT_RWSIZE=1024 
107 
108# Compatibility options 
109 
110options COMPAT_NETBSD32 # allow running arm (e.g. non-earm) binaries 
111#options COMPAT_43 # 4.3BSD compatibility. 
112#options COMPAT_09 # NetBSD 0.9, 
113#options COMPAT_10 # NetBSD 1.0, 
114#options COMPAT_11 # NetBSD 1.1, 
115#options COMPAT_12 # NetBSD 1.2, 
116#options COMPAT_13 # NetBSD 1.3, 
117#options COMPAT_14 # NetBSD 1.4, 
118#options COMPAT_15 # NetBSD 1.5, 
119#options COMPAT_16 # NetBSD 1.6, 
120#options COMPAT_20 # NetBSD 2.0, 
121#options COMPAT_30 # NetBSD 3.0, 
122#options COMPAT_40 # NetBSD 4.0, 
123#options COMPAT_50 # NetBSD 5.0, 
124options COMPAT_60 # NetBSD 6.0, and 
125options COMPAT_70 # NetBSD 7.0 binary compatibility. 
126#options TCP_COMPAT_42 # 4.2BSD TCP/IP bug compat. Not recommended. 
127#options COMPAT_BSDPTY # /dev/[pt]ty?? ptys. 
128 
129# Shared memory options 
130 
131options SYSVMSG # System V-like message queues 
132options SYSVSEM # System V-like semaphores 
133options SYSVSHM # System V-like memory sharing 
134 
135# Device options 
136 
137#options MEMORY_DISK_HOOKS # boottime setup of ramdisk 
138#options MEMORY_DISK_ROOT_SIZE=8192 # Size in blocks 
139#options MEMORY_DISK_DYNAMIC 
140#options MINIROOTSIZE=1000 # Size in blocks 
141#options MEMORY_DISK_IS_ROOT # use memory disk as root 
142 
143# Wedge support 
144options DKWEDGE_AUTODISCOVER # Automatically add dk(4) instances 
145options DKWEDGE_METHOD_GPT # Supports GPT partitions as wedges 
146 
147# Miscellaneous kernel options 
148options KTRACE # system call tracing, a la ktrace(1) 
149#options SCSIVERBOSE # Verbose SCSI errors 
150#options MIIVERBOSE # Verbose MII autoconfuration messages 
151options DDB_KEYCODE=0x40 
152#options USERCONF # userconf(4) support 
153#options PIPE_SOCKETPAIR # smaller, but slower pipe(2) 
154 
155# Development and Debugging options 
156 
157#options PERFCTRS # performance counters 
158options DIAGNOSTIC # internal consistency checks 
159options DEBUG 
160options LOCKDEBUG 
161options PMAP_DEBUG # Enable pmap_debug_level code 
162#options IPKDB # remote kernel debugging 21#options IPKDB # remote kernel debugging
163options VERBOSE_INIT_ARM # verbose bootstraping messages 22#options VERBOSE_INIT_ARM # verbose bootstrapping messages
164options DDB # in-kernel debugger 23# CONSADDR is required for early init messages from VERBOSE_INIT_ARM.
165options DDB_ONPANIC=1 24#options CONSADDR=0x70006300
166options DDB_HISTORY_SIZE=100 # Enable history editing in DDB 25
167options DDB_VERBOSE_HELP 
168#options KGDB 
169makeoptions DEBUG="-g" # compile full symbol table 26makeoptions DEBUG="-g" # compile full symbol table
170makeoptions COPY_SYMTAB=1 27makeoptions COPY_SYMTAB=1
171 28
172## USB Debugging options 
173options USB_DEBUG 
174options EHCI_DEBUG 
175options OHCI_DEBUG 
176options UHUB_DEBUG 
177options USBVERBOSE 
178 
179 
180# Valid options for BOOT_ARGS: 
181# single Boot to single user only 
182# kdb Give control to kernel debugger 
183# ask Ask for file name to reboot from 
184# memorydisk=<n> Set memorydisk size to <n> KB 
185# quiet Show aprint_naive output 
186# verbose Show aprint_normal and aprint_verbose output 
187#options BOOT_ARGS="\"\"" 
188options BOOT_ARGS="\"verbose\"" 
189 
190config netbsd root on ? type ? 29config netbsd root on ? type ?
191 30
192# The main bus device 31# Device tree support
193mainbus0 at root 32armfdt0 at root
194 
195# The boot cpu and secondary CPUs 
196cpu0 at mainbus? 
197cpu* at mainbus? # Multiprocessor 
198 
199# core devices 
200armperiph0 at mainbus? 
201armgic0 at armperiph? # Interrupt Controller 
202armgtmr0 at armperiph? # Generic Timer 
203 
204# On-board I/O 
205exynosfdt0 at mainbus? 
206fdt* at fdtbus? 33fdt* at fdtbus?
207 34
208fregulator* at fdt? 35# CPUs
209 36cpus* at fdt? pass 0
210#interrupt controller 37cpu* at cpus?
211exyointr0 at fdt? 38
212gic* at fdt? 39fclock* at fdt? pass 4
 40fregulator* at fdt? pass 4
 41gpiokeys* at fdt?
 42
 43# Timer
 44gtmr* at fdt? pass 1 # ARM Generic Timer
 45armgtmr0 at gtmr?
 46mct* at fdt? # Exynos Multi Core Timer (MCT)
 47
 48# Interrupt controller
 49exyointr* at fdt? pass 1
 50gic* at fdt? pass 1 # GIC
 51armgic0 at gic?
213 52
214# Clock controller 53# Clock controller
215exy5422clk* at fdt? # Exynos5422 clock controller 54exy5422clk* at fdt? pass 3 # Exynos5422 clock controller
216 55
217# Integrated Samsung UARTs 56# GPIO controller
218sscom* at fdt? # UART ? 57exyopctl* at fdt? pass 2 # GPIO
219 58gpio* at gpiobus?
220# Exynos Watchdog Timer 
221exyowdt* at fdt? # watchdog 
222 59
223# Exynos chip id 60# Exynos SoC support
224chipid* at fdt? 61chipid* at fdt?
 62sysmmu* at fdt?
225 63
226# Exynos system MMUs 64# UART
227sysmmu* at fdt? 65sscom* at fdt? # UART
228 
229# Exynos RTC 
230exyortc* at fdt? 
231 66
232# Exynos Multi Core timer (MCT) 67# I2C
233mct* at fdt? 68exyoi2c* at fdt? # I2C
 69iic* at exyoi2c?
234 70
235# GPIO 71# RTC
236exyopctl* at fdt? 72exyortc* at fdt? # RTC
237gpio* at gpiobus? 
238 
239# On-board USB 2.0 
240exyousbphy* at fdt? 
241ohci* at fdt? 
242ehci* at fdt? 
243usb* at ohci? 
244usb* at ehci? 
245 
246# On-board USB 3.0 
247exyousb* at fdt? 
248#xhci* at fdt? 
249#usb* at xhci? 
250 
251# I2C devices 
252exyoi2c* at fdt? 
253#i2c* at exyoi2c? 
254 73
255# SD/MMC 74# SDMMC
256dwcmmc* at fdt? 75dwcmmc* at fdt? # SDMMC
257sdmmc* at dwcmmc? 76sdmmc* at dwcmmc?
258ld0 at sdmmc0 77ld0 at sdmmc0
259ld1 at sdmmc1 78ld1 at sdmmc1
260ld2 at sdmmc2 79ld2 at sdmmc2
 80ld3 at sdmmc3
261ld* at sdmmc? 81ld* at sdmmc?
262 82
263# MISSING SUPPORT 83# USB
264# eMMC 84exyousbphy* at fdt?
265# uSD 85exyousb* at fdt?
266# SPI 86ohci* at fdt? # OUSB
267# ADC 87ehci* at fdt? # EUSB
268# PMIC (via I2C #4) 88usb* at ohci?
269# PWM for Cooling fan 89usb* at ehci?
270# HDMI 
271# I2S 
272# GPU 
273 
274# serial console connectivity 
275options SSCOM2CONSOLE, CONSPEED=115200 
276 90
277# include all USB devices 
278include "dev/usb/usbdevices.config" 91include "dev/usb/usbdevices.config"
279 
280midi* at midibus? 92midi* at midibus?
281 93
282# Pseudo-Devices 94cinclude "arch/evbarm/conf/TEGRA.local"
283 
284# disk/mass storage pseudo-devices 
285#pseudo-device md # memory disk device (ramdisk) 
286#pseudo-device vnd # disk-like interface to files 
287#pseudo-device fss # file system snapshot device 
288#pseudo-device putter # for puffs and pud 
289pseudo-device drvctl # driver control 
290 
291# network pseudo-devices 
292pseudo-device bpfilter # Berkeley packet filter 
293pseudo-device loop # network loopback 
294#pseudo-device kttcp # network loopback 
295 
296# miscellaneous pseudo-devices 
297pseudo-device pty # pseudo-terminals 
298#options RND_COM 
299#pseudo-device clockctl # user control of clock subsystem 
300pseudo-device ksyms # /dev/ksyms 
301#pseudo-device lockstat # lock profiling 

cvs diff -r1.2 -r1.3 src/sys/arch/evbarm/conf/Attic/files.exynos (switch to unified diff)

--- src/sys/arch/evbarm/conf/Attic/files.exynos 2015/12/14 22:06:57 1.2
+++ src/sys/arch/evbarm/conf/Attic/files.exynos 2017/06/10 15:13:19 1.3
@@ -1,18 +1,8 @@ @@ -1,18 +1,8 @@
1# $NetBSD: files.exynos,v 1.2 2015/12/14 22:06:57 marty Exp $ 1# $NetBSD: files.exynos,v 1.3 2017/06/10 15:13:19 jmcneill Exp $
2# 2#
3# EXYNOS 5422 board configuration info 3# EXYNOS board configuration info
4# 4#
5 5
6file arch/evbarm/exynos/exynos_machdep.c 6include "arch/evbarm/conf/files.fdt"
7 7
8# Kernel boot arguments 8include "arch/arm/samsung/files.exynos"
9defparam opt_machdep.h BOOT_ARGS 
10 
11# FDT 
12 
13include "dev/ofw/files.ofw" 
14include "dev/fdt/files.fdt" 
15include "arch/arm/fdt/files.fdt" 
16 
17# Pull in Exynos SoC default 
18include "arch/arm/samsung/files.exynos" 

cvs diff -r1.1 -r1.2 src/sys/arch/evbarm/conf/Attic/std.exynos (switch to unified diff)

--- src/sys/arch/evbarm/conf/Attic/std.exynos 2015/12/06 00:31:24 1.1
+++ src/sys/arch/evbarm/conf/Attic/std.exynos 2017/06/10 15:13:19 1.2
@@ -1,35 +1,35 @@ @@ -1,35 +1,35 @@
1# $NetBSD: std.exynos,v 1.1 2015/12/06 00:31:24 marty Exp $ 1# $NetBSD: std.exynos,v 1.2 2017/06/10 15:13:19 jmcneill Exp $
2# 2#
3# standard NetBSD/evbarm for EXYNOS options 
4 3
5machine evbarm arm 4machine evbarm arm
6include "arch/evbarm/conf/std.evbarm" 5include "arch/evbarm/conf/std.evbarm"
7 6
8# Pull in EXYNOS config definitions 7include "arch/evbarm/conf/files.exynos"
9include "arch/evbarm/conf/files.exynos" 
10 8
11makeoptions CPUFLAGS="-march=armv7-a -mfpu=neon" 9makeoptions CPUFLAGS="-march=armv7-a -mfpu=neon"
12 10
13# To support easy transit to ../arch/arm/arm32 11options ARM_TRUSTZONE_FIRMWARE
 12options __NO_FIQ
 13
 14options FDT # Flattened Device Tree support
14options MODULAR 15options MODULAR
15options MODULAR_DEFAULT_AUTOLOAD 16options MODULAR_DEFAULT_AUTOLOAD
16options ARM_HAS_VBAR 
17options CORTEX_PMC 
18options __HAVE_CPU_COUNTER 17options __HAVE_CPU_COUNTER
19options __HAVE_FAST_SOFTINTS # should be in types.h 18options __HAVE_FAST_SOFTINTS # should be in types.h
 19options ARM_HAS_VBAR
20#options __HAVE_MM_MD_DIRECT_MAPPED_PHYS 20#options __HAVE_MM_MD_DIRECT_MAPPED_PHYS
 21#options PMAP_NEED_ALLOC_POOLPAGE
21options TPIDRPRW_IS_CURCPU 22options TPIDRPRW_IS_CURCPU
22options KERNEL_BASE_EXT=0x80000000 23options KERNEL_BASE_EXT=0x80000000
23options FPU_VFP 24options FPU_VFP
24 25options PCI_NETBSD_CONFIGURE
25# All shipped Samsung SoC's that are not Samsung products have this 26options __HAVE_PCI_CONF_HOOK
26options ARM_TRUSTZONE_FIRMWARE 27options __BUS_SPACE_HAS_STREAM_METHODS
27options __NO_FIQ 
28 28
29makeoptions KERNEL_BASE_PHYS="0x80000000" 29makeoptions KERNEL_BASE_PHYS="0x80000000"
30makeoptions KERNEL_BASE_VIRT="0x80000000" 30makeoptions KERNEL_BASE_VIRT="0x80000000"
31makeoptions BOARDTYPE="exynos" 31makeoptions BOARDTYPE="exynos"
32makeoptions BOARDMKFRAG="${THISARM}/conf/mk.exynos" 32makeoptions BOARDMKFRAG="${THISARM}/conf/mk.exynos"
33 33
34options ARM_INTR_IMPL="<arch/arm/samsung/exynos_intr.h>" 34options ARM_INTR_IMPL="<arch/arm/fdt/fdt_intr.h>"
35options ARM_GENERIC_TODR 35options ARM_GENERIC_TODR

File Deleted: src/sys/arch/evbarm/exynos/Attic/exynos_machdep.c

cvs diff -r1.1 -r1.2 src/sys/arch/evbarm/exynos/Attic/platform.h (switch to unified diff)

--- src/sys/arch/evbarm/exynos/Attic/platform.h 2015/12/06 00:33:44 1.1
+++ src/sys/arch/evbarm/exynos/Attic/platform.h 2017/06/10 15:13:19 1.2
@@ -1,47 +1,43 @@ @@ -1,47 +1,43 @@
1/* $NetBSD: platform.h,v 1.1 2015/12/06 00:33:44 marty Exp $ */ 1/* $NetBSD: platform.h,v 1.2 2017/06/10 15:13:19 jmcneill Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 4 * Copyright (c) 2014 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Nick Hudson 8 * by Nick Hudson
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright 15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the 16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution. 17 * documentation and/or other materials provided with the distribution.
18 * 18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE. 29 * POSSIBILITY OF SUCH DAMAGE.
30 */ 30 */
31 31
32#ifndef _ARM_EXYNOS_PLATFORM_H 32#ifndef _ARM_EXYNOS_PLATFORM_H
33#define _ARM_EXYNOS_PLATFORM_H 33#define _ARM_EXYNOS_PLATFORM_H
34 34
35/* 35#include <arch/evbarm/fdt/platform.h>
36 * Kernel VM space 16Mb behind KERNEL_BASE upto 0xeff00000 
37 */ 
38#define KERNEL_VM_BASE 0xc0000000 
39#define KERNEL_VM_SIZE (EXYNOS_CORE_VBASE - KERNEL_VM_BASE) 
40 36
41/* 37/*
42 * IO space 38 * IO space
43 */ 39 */
44 40
45#define EXYNOS_CORE_VBASE 0xf0000000 41#define EXYNOS_CORE_VBASE 0xf0000000
46 42
47#endif /* _ARM_EXYNOS_PLATFORM_H */ 43#endif /* _ARM_EXYNOS_PLATFORM_H */