| @@ -1,488 +1,492 @@ | | | @@ -1,488 +1,492 @@ |
1 | /* $NetBSD: ehci_pci.c,v 1.64 2016/10/13 20:05:06 jdolecek Exp $ */ | | 1 | /* $NetBSD: ehci_pci.c,v 1.65 2017/06/12 10:59:47 sborrill Exp $ */ |
2 | | | 2 | |
3 | /* | | 3 | /* |
4 | * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. | | 4 | * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. |
5 | * All rights reserved. | | 5 | * All rights reserved. |
6 | * | | 6 | * |
7 | * This code is derived from software contributed to The NetBSD Foundation | | 7 | * This code is derived from software contributed to The NetBSD Foundation |
8 | * by Lennart Augustsson (lennart@augustsson.net). | | 8 | * by Lennart Augustsson (lennart@augustsson.net). |
9 | * | | 9 | * |
10 | * Redistribution and use in source and binary forms, with or without | | 10 | * Redistribution and use in source and binary forms, with or without |
11 | * modification, are permitted provided that the following conditions | | 11 | * modification, are permitted provided that the following conditions |
12 | * are met: | | 12 | * are met: |
13 | * 1. Redistributions of source code must retain the above copyright | | 13 | * 1. Redistributions of source code must retain the above copyright |
14 | * notice, this list of conditions and the following disclaimer. | | 14 | * notice, this list of conditions and the following disclaimer. |
15 | * 2. Redistributions in binary form must reproduce the above copyright | | 15 | * 2. Redistributions in binary form must reproduce the above copyright |
16 | * notice, this list of conditions and the following disclaimer in the | | 16 | * notice, this list of conditions and the following disclaimer in the |
17 | * documentation and/or other materials provided with the distribution. | | 17 | * documentation and/or other materials provided with the distribution. |
18 | * | | 18 | * |
19 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS | | 19 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
20 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED | | 20 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
21 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | | 21 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
22 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS | | 22 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
23 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | | 23 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | | 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | | 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | | 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | | 27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | | 28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
29 | * POSSIBILITY OF SUCH DAMAGE. | | 29 | * POSSIBILITY OF SUCH DAMAGE. |
30 | */ | | 30 | */ |
31 | | | 31 | |
32 | #include <sys/cdefs.h> | | 32 | #include <sys/cdefs.h> |
33 | __KERNEL_RCSID(0, "$NetBSD: ehci_pci.c,v 1.64 2016/10/13 20:05:06 jdolecek Exp $"); | | 33 | __KERNEL_RCSID(0, "$NetBSD: ehci_pci.c,v 1.65 2017/06/12 10:59:47 sborrill Exp $"); |
34 | | | 34 | |
35 | #include <sys/param.h> | | 35 | #include <sys/param.h> |
36 | #include <sys/systm.h> | | 36 | #include <sys/systm.h> |
37 | #include <sys/kernel.h> | | 37 | #include <sys/kernel.h> |
38 | #include <sys/device.h> | | 38 | #include <sys/device.h> |
39 | #include <sys/proc.h> | | 39 | #include <sys/proc.h> |
40 | #include <sys/queue.h> | | 40 | #include <sys/queue.h> |
41 | | | 41 | |
42 | #include <sys/bus.h> | | 42 | #include <sys/bus.h> |
43 | | | 43 | |
44 | #include <dev/pci/pcidevs.h> | | 44 | #include <dev/pci/pcidevs.h> |
45 | #include <dev/pci/pcivar.h> | | 45 | #include <dev/pci/pcivar.h> |
46 | #include <dev/pci/usb_pci.h> | | 46 | #include <dev/pci/usb_pci.h> |
47 | | | 47 | |
48 | #include <dev/usb/usb.h> | | 48 | #include <dev/usb/usb.h> |
49 | #include <dev/usb/usbdi.h> | | 49 | #include <dev/usb/usbdi.h> |
50 | #include <dev/usb/usbdivar.h> | | 50 | #include <dev/usb/usbdivar.h> |
51 | #include <dev/usb/usb_mem.h> | | 51 | #include <dev/usb/usb_mem.h> |
52 | | | 52 | |
53 | #include <dev/usb/ehcireg.h> | | 53 | #include <dev/usb/ehcireg.h> |
54 | #include <dev/usb/ehcivar.h> | | 54 | #include <dev/usb/ehcivar.h> |
55 | | | 55 | |
56 | #ifdef EHCI_DEBUG | | 56 | #ifdef EHCI_DEBUG |
57 | #define DPRINTF(x) if (ehcidebug) printf x | | 57 | #define DPRINTF(x) if (ehcidebug) printf x |
58 | extern int ehcidebug; | | 58 | extern int ehcidebug; |
59 | #else | | 59 | #else |
60 | #define DPRINTF(x) | | 60 | #define DPRINTF(x) |
61 | #endif | | 61 | #endif |
62 | | | 62 | |
63 | enum ehci_pci_quirk_flags { | | 63 | enum ehci_pci_quirk_flags { |
64 | EHCI_PCI_QUIRK_AMD_SB600 = 0x1, /* always need a quirk */ | | 64 | EHCI_PCI_QUIRK_AMD_SB600 = 0x1, /* always need a quirk */ |
65 | EHCI_PCI_QUIRK_AMD_SB700 = 0x2, /* depends on the SMB revision */ | | 65 | EHCI_PCI_QUIRK_AMD_SB700 = 0x2, /* depends on the SMB revision */ |
66 | }; | | 66 | }; |
67 | | | 67 | |
68 | static const struct pci_quirkdata ehci_pci_quirks[] = { | | 68 | static const struct pci_quirkdata ehci_pci_quirks[] = { |
69 | { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_USB_EHCI, | | 69 | { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_USB_EHCI, |
70 | EHCI_PCI_QUIRK_AMD_SB600 }, | | 70 | EHCI_PCI_QUIRK_AMD_SB600 }, |
71 | { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_USB_EHCI, | | 71 | { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_USB_EHCI, |
72 | EHCI_PCI_QUIRK_AMD_SB700 }, | | 72 | EHCI_PCI_QUIRK_AMD_SB700 }, |
73 | }; | | 73 | }; |
74 | | | 74 | |
75 | static void ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, | | 75 | static void ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, |
76 | pcitag_t tag); | | 76 | pcitag_t tag); |
77 | static void ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, | | 77 | static void ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, |
78 | pcitag_t tag); | | 78 | pcitag_t tag); |
79 | static bool ehci_pci_suspend(device_t, const pmf_qual_t *); | | 79 | static bool ehci_pci_suspend(device_t, const pmf_qual_t *); |
80 | static bool ehci_pci_resume(device_t, const pmf_qual_t *); | | 80 | static bool ehci_pci_resume(device_t, const pmf_qual_t *); |
81 | | | 81 | |
82 | struct ehci_pci_softc { | | 82 | struct ehci_pci_softc { |
83 | ehci_softc_t sc; | | 83 | ehci_softc_t sc; |
84 | pci_chipset_tag_t sc_pc; | | 84 | pci_chipset_tag_t sc_pc; |
85 | pcitag_t sc_tag; | | 85 | pcitag_t sc_tag; |
86 | void *sc_ih; /* interrupt vectoring */ | | 86 | void *sc_ih; /* interrupt vectoring */ |
87 | }; | | 87 | }; |
88 | | | 88 | |
89 | static int ehci_sb700_match(const struct pci_attach_args *pa); | | 89 | static int ehci_sb700_match(const struct pci_attach_args *pa); |
90 | static int ehci_apply_amd_quirks(struct ehci_pci_softc *sc); | | 90 | static int ehci_apply_amd_quirks(struct ehci_pci_softc *sc); |
91 | enum ehci_pci_quirk_flags ehci_pci_lookup_quirkdata(pci_vendor_id_t, | | 91 | enum ehci_pci_quirk_flags ehci_pci_lookup_quirkdata(pci_vendor_id_t, |
92 | pci_product_id_t); | | 92 | pci_product_id_t); |
93 | | | 93 | |
94 | #define EHCI_MAX_BIOS_WAIT 100 /* ms*10 */ | | 94 | #define EHCI_MAX_BIOS_WAIT 100 /* ms*10 */ |
95 | #define EHCI_SBx00_WORKAROUND_REG 0x50 | | 95 | #define EHCI_SBx00_WORKAROUND_REG 0x50 |
96 | #define EHCI_SBx00_WORKAROUND_ENABLE __BIT(27) | | 96 | #define EHCI_SBx00_WORKAROUND_ENABLE __BIT(27) |
97 | | | 97 | |
98 | | | 98 | |
99 | static int | | 99 | static int |
100 | ehci_pci_match(device_t parent, cfdata_t match, void *aux) | | 100 | ehci_pci_match(device_t parent, cfdata_t match, void *aux) |
101 | { | | 101 | { |
102 | struct pci_attach_args *pa = (struct pci_attach_args *) aux; | | 102 | struct pci_attach_args *pa = (struct pci_attach_args *) aux; |
103 | | | 103 | |
104 | if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS && | | 104 | if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS && |
105 | PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB && | | 105 | PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB && |
106 | PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_EHCI) | | 106 | PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_EHCI) |
107 | return 1; | | 107 | return 1; |
108 | | | 108 | |
109 | return 0; | | 109 | return 0; |
110 | } | | 110 | } |
111 | | | 111 | |
112 | static void | | 112 | static void |
113 | ehci_pci_attach(device_t parent, device_t self, void *aux) | | 113 | ehci_pci_attach(device_t parent, device_t self, void *aux) |
114 | { | | 114 | { |
115 | struct ehci_pci_softc *sc = device_private(self); | | 115 | struct ehci_pci_softc *sc = device_private(self); |
116 | struct pci_attach_args *pa = (struct pci_attach_args *)aux; | | 116 | struct pci_attach_args *pa = (struct pci_attach_args *)aux; |
117 | pci_chipset_tag_t pc = pa->pa_pc; | | 117 | pci_chipset_tag_t pc = pa->pa_pc; |
118 | pcitag_t tag = pa->pa_tag; | | 118 | pcitag_t tag = pa->pa_tag; |
119 | char const *intrstr; | | 119 | char const *intrstr; |
120 | pci_intr_handle_t ih; | | 120 | pci_intr_handle_t ih; |
121 | pcireg_t csr; | | 121 | pcireg_t csr; |
122 | int ncomp; | | 122 | int ncomp; |
123 | struct usb_pci *up; | | 123 | struct usb_pci *up; |
124 | int quirk; | | 124 | int quirk; |
125 | char intrbuf[PCI_INTRSTR_LEN]; | | 125 | char intrbuf[PCI_INTRSTR_LEN]; |
126 | | | 126 | |
127 | sc->sc.sc_dev = self; | | 127 | sc->sc.sc_dev = self; |
128 | sc->sc.sc_bus.ub_hcpriv = sc; | | 128 | sc->sc.sc_bus.ub_hcpriv = sc; |
129 | | | 129 | |
130 | pci_aprint_devinfo(pa, "USB controller"); | | 130 | pci_aprint_devinfo(pa, "USB controller"); |
131 | | | 131 | |
132 | /* Check for quirks */ | | 132 | /* Check for quirks */ |
133 | quirk = ehci_pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), | | 133 | quirk = ehci_pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), |
134 | PCI_PRODUCT(pa->pa_id)); | | 134 | PCI_PRODUCT(pa->pa_id)); |
135 | | | 135 | |
136 | /* Map I/O registers */ | | 136 | /* Map I/O registers */ |
137 | if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0, | | 137 | if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0, |
138 | &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) { | | 138 | &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) { |
139 | sc->sc.sc_size = 0; | | 139 | sc->sc.sc_size = 0; |
140 | aprint_error_dev(self, "can't map memory space\n"); | | 140 | aprint_error_dev(self, "can't map memory space\n"); |
141 | return; | | 141 | return; |
142 | } | | 142 | } |
143 | | | 143 | |
144 | sc->sc_pc = pc; | | 144 | sc->sc_pc = pc; |
145 | sc->sc_tag = tag; | | 145 | sc->sc_tag = tag; |
146 | sc->sc.sc_bus.ub_dmatag = pa->pa_dmat; | | 146 | sc->sc.sc_bus.ub_dmatag = pa->pa_dmat; |
147 | | | 147 | |
148 | /* Disable interrupts, so we don't get any spurious ones. */ | | 148 | /* Disable interrupts, so we don't get any spurious ones. */ |
149 | sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH); | | 149 | sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH); |
150 | DPRINTF(("%s: offs=%d\n", device_xname(self), sc->sc.sc_offs)); | | 150 | DPRINTF(("%s: offs=%d\n", device_xname(self), sc->sc.sc_offs)); |
151 | EOWRITE4(&sc->sc, EHCI_USBINTR, 0); | | 151 | EOWRITE4(&sc->sc, EHCI_USBINTR, 0); |
152 | | | 152 | |
153 | /* Handle quirks */ | | 153 | /* Handle quirks */ |
154 | switch (quirk) { | | 154 | switch (quirk) { |
155 | case EHCI_PCI_QUIRK_AMD_SB600: | | 155 | case EHCI_PCI_QUIRK_AMD_SB600: |
156 | ehci_apply_amd_quirks(sc); | | 156 | ehci_apply_amd_quirks(sc); |
157 | break; | | 157 | break; |
158 | case EHCI_PCI_QUIRK_AMD_SB700: | | 158 | case EHCI_PCI_QUIRK_AMD_SB700: |
159 | if (pci_find_device(NULL, ehci_sb700_match)) | | 159 | if (pci_find_device(NULL, ehci_sb700_match)) |
160 | ehci_apply_amd_quirks(sc); | | 160 | ehci_apply_amd_quirks(sc); |
161 | break; | | 161 | break; |
162 | } | | 162 | } |
163 | | | 163 | |
| | | 164 | pcireg_t intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); |
| | | 165 | int pin = PCI_INTERRUPT_PIN(intr); |
| | | 166 | |
164 | /* Enable the device. */ | | 167 | /* Enable the device. */ |
165 | csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); | | 168 | csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); |
166 | pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, | | 169 | csr |= PCI_COMMAND_MASTER_ENABLE; |
167 | csr | PCI_COMMAND_MASTER_ENABLE); | | 170 | csr &= ~(pin ? PCI_COMMAND_INTERRUPT_DISABLE : 0); |
| | | 171 | pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); |
168 | | | 172 | |
169 | /* Map and establish the interrupt. */ | | 173 | /* Map and establish the interrupt. */ |
170 | if (pci_intr_map(pa, &ih)) { | | 174 | if (pci_intr_map(pa, &ih)) { |
171 | aprint_error_dev(self, "couldn't map interrupt\n"); | | 175 | aprint_error_dev(self, "couldn't map interrupt\n"); |
172 | goto fail; | | 176 | goto fail; |
173 | } | | 177 | } |
174 | | | 178 | |
175 | /* | | 179 | /* |
176 | * Allocate IRQ | | 180 | * Allocate IRQ |
177 | */ | | 181 | */ |
178 | intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); | | 182 | intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); |
179 | sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_USB, ehci_intr, sc, | | 183 | sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_USB, ehci_intr, sc, |
180 | device_xname(self)); | | 184 | device_xname(self)); |
181 | if (sc->sc_ih == NULL) { | | 185 | if (sc->sc_ih == NULL) { |
182 | aprint_error_dev(self, "couldn't establish interrupt"); | | 186 | aprint_error_dev(self, "couldn't establish interrupt"); |
183 | if (intrstr != NULL) | | 187 | if (intrstr != NULL) |
184 | aprint_error(" at %s", intrstr); | | 188 | aprint_error(" at %s", intrstr); |
185 | aprint_error("\n"); | | 189 | aprint_error("\n"); |
186 | goto fail; | | 190 | goto fail; |
187 | } | | 191 | } |
188 | aprint_normal_dev(self, "interrupting at %s\n", intrstr); | | 192 | aprint_normal_dev(self, "interrupting at %s\n", intrstr); |
189 | | | 193 | |
190 | switch(pci_conf_read(pc, tag, PCI_USBREV) & PCI_USBREV_MASK) { | | 194 | switch(pci_conf_read(pc, tag, PCI_USBREV) & PCI_USBREV_MASK) { |
191 | case PCI_USBREV_PRE_1_0: | | 195 | case PCI_USBREV_PRE_1_0: |
192 | case PCI_USBREV_1_0: | | 196 | case PCI_USBREV_1_0: |
193 | case PCI_USBREV_1_1: | | 197 | case PCI_USBREV_1_1: |
194 | sc->sc.sc_bus.ub_revision = USBREV_UNKNOWN; | | 198 | sc->sc.sc_bus.ub_revision = USBREV_UNKNOWN; |
195 | aprint_verbose_dev(self, "pre-2.0 USB rev\n"); | | 199 | aprint_verbose_dev(self, "pre-2.0 USB rev\n"); |
196 | goto fail; | | 200 | goto fail; |
197 | case PCI_USBREV_2_0: | | 201 | case PCI_USBREV_2_0: |
198 | sc->sc.sc_bus.ub_revision = USBREV_2_0; | | 202 | sc->sc.sc_bus.ub_revision = USBREV_2_0; |
199 | break; | | 203 | break; |
200 | default: | | 204 | default: |
201 | sc->sc.sc_bus.ub_revision = USBREV_UNKNOWN; | | 205 | sc->sc.sc_bus.ub_revision = USBREV_UNKNOWN; |
202 | break; | | 206 | break; |
203 | } | | 207 | } |
204 | | | 208 | |
205 | /* Figure out vendor for root hub descriptor. */ | | 209 | /* Figure out vendor for root hub descriptor. */ |
206 | sc->sc.sc_id_vendor = PCI_VENDOR(pa->pa_id); | | 210 | sc->sc.sc_id_vendor = PCI_VENDOR(pa->pa_id); |
207 | pci_findvendor(sc->sc.sc_vendor, | | 211 | pci_findvendor(sc->sc.sc_vendor, |
208 | sizeof(sc->sc.sc_vendor), sc->sc.sc_id_vendor); | | 212 | sizeof(sc->sc.sc_vendor), sc->sc.sc_id_vendor); |
209 | /* Enable workaround for dropped interrupts as required */ | | 213 | /* Enable workaround for dropped interrupts as required */ |
210 | switch (sc->sc.sc_id_vendor) { | | 214 | switch (sc->sc.sc_id_vendor) { |
211 | case PCI_VENDOR_ATI: | | 215 | case PCI_VENDOR_ATI: |
212 | case PCI_VENDOR_VIATECH: | | 216 | case PCI_VENDOR_VIATECH: |
213 | sc->sc.sc_flags |= EHCIF_DROPPED_INTR_WORKAROUND; | | 217 | sc->sc.sc_flags |= EHCIF_DROPPED_INTR_WORKAROUND; |
214 | aprint_normal_dev(self, "dropped intr workaround enabled\n"); | | 218 | aprint_normal_dev(self, "dropped intr workaround enabled\n"); |
215 | break; | | 219 | break; |
216 | default: | | 220 | default: |
217 | break; | | 221 | break; |
218 | } | | 222 | } |
219 | | | 223 | |
220 | /* | | 224 | /* |
221 | * Find companion controllers. According to the spec they always | | 225 | * Find companion controllers. According to the spec they always |
222 | * have lower function numbers so they should be enumerated already. | | 226 | * have lower function numbers so they should be enumerated already. |
223 | */ | | 227 | */ |
224 | const u_int maxncomp = EHCI_HCS_N_CC(EREAD4(&sc->sc, EHCI_HCSPARAMS)); | | 228 | const u_int maxncomp = EHCI_HCS_N_CC(EREAD4(&sc->sc, EHCI_HCSPARAMS)); |
225 | KASSERT(maxncomp <= EHCI_COMPANION_MAX); | | 229 | KASSERT(maxncomp <= EHCI_COMPANION_MAX); |
226 | ncomp = 0; | | 230 | ncomp = 0; |
227 | TAILQ_FOREACH(up, &ehci_pci_alldevs, next) { | | 231 | TAILQ_FOREACH(up, &ehci_pci_alldevs, next) { |
228 | if (up->bus == pa->pa_bus && up->device == pa->pa_device | | 232 | if (up->bus == pa->pa_bus && up->device == pa->pa_device |
229 | && !up->claimed) { | | 233 | && !up->claimed) { |
230 | DPRINTF(("ehci_pci_attach: companion %s\n", | | 234 | DPRINTF(("ehci_pci_attach: companion %s\n", |
231 | device_xname(up->usb))); | | 235 | device_xname(up->usb))); |
232 | sc->sc.sc_comps[ncomp++] = up->usb; | | 236 | sc->sc.sc_comps[ncomp++] = up->usb; |
233 | up->claimed = true; | | 237 | up->claimed = true; |
234 | if (ncomp == maxncomp) | | 238 | if (ncomp == maxncomp) |
235 | break; | | 239 | break; |
236 | } | | 240 | } |
237 | } | | 241 | } |
238 | sc->sc.sc_ncomp = ncomp; | | 242 | sc->sc.sc_ncomp = ncomp; |
239 | | | 243 | |
240 | ehci_get_ownership(&sc->sc, pc, tag); | | 244 | ehci_get_ownership(&sc->sc, pc, tag); |
241 | | | 245 | |
242 | int err = ehci_init(&sc->sc); | | 246 | int err = ehci_init(&sc->sc); |
243 | if (err) { | | 247 | if (err) { |
244 | aprint_error_dev(self, "init failed, error=%d\n", err); | | 248 | aprint_error_dev(self, "init failed, error=%d\n", err); |
245 | goto fail; | | 249 | goto fail; |
246 | } | | 250 | } |
247 | | | 251 | |
248 | if (!pmf_device_register1(self, ehci_pci_suspend, ehci_pci_resume, | | 252 | if (!pmf_device_register1(self, ehci_pci_suspend, ehci_pci_resume, |
249 | ehci_shutdown)) | | 253 | ehci_shutdown)) |
250 | aprint_error_dev(self, "couldn't establish power handler\n"); | | 254 | aprint_error_dev(self, "couldn't establish power handler\n"); |
251 | | | 255 | |
252 | /* Attach usb device. */ | | 256 | /* Attach usb device. */ |
253 | sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint); | | 257 | sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint); |
254 | return; | | 258 | return; |
255 | | | 259 | |
256 | fail: | | 260 | fail: |
257 | if (sc->sc_ih) { | | 261 | if (sc->sc_ih) { |
258 | pci_intr_disestablish(sc->sc_pc, sc->sc_ih); | | 262 | pci_intr_disestablish(sc->sc_pc, sc->sc_ih); |
259 | sc->sc_ih = NULL; | | 263 | sc->sc_ih = NULL; |
260 | } | | 264 | } |
261 | if (sc->sc.sc_size) { | | 265 | if (sc->sc.sc_size) { |
262 | ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); | | 266 | ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); |
263 | bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); | | 267 | bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); |
264 | sc->sc.sc_size = 0; | | 268 | sc->sc.sc_size = 0; |
265 | } | | 269 | } |
266 | return; | | 270 | return; |
267 | } | | 271 | } |
268 | | | 272 | |
269 | static int | | 273 | static int |
270 | ehci_pci_detach(device_t self, int flags) | | 274 | ehci_pci_detach(device_t self, int flags) |
271 | { | | 275 | { |
272 | struct ehci_pci_softc *sc = device_private(self); | | 276 | struct ehci_pci_softc *sc = device_private(self); |
273 | int rv; | | 277 | int rv; |
274 | | | 278 | |
275 | rv = ehci_detach(&sc->sc, flags); | | 279 | rv = ehci_detach(&sc->sc, flags); |
276 | if (rv) | | 280 | if (rv) |
277 | return rv; | | 281 | return rv; |
278 | | | 282 | |
279 | pmf_device_deregister(self); | | 283 | pmf_device_deregister(self); |
280 | ehci_shutdown(self, flags); | | 284 | ehci_shutdown(self, flags); |
281 | | | 285 | |
282 | /* disable interrupts */ | | 286 | /* disable interrupts */ |
283 | EOWRITE4(&sc->sc, EHCI_USBINTR, 0); | | 287 | EOWRITE4(&sc->sc, EHCI_USBINTR, 0); |
284 | /* XXX grotty hack to flush the write */ | | 288 | /* XXX grotty hack to flush the write */ |
285 | (void)EOREAD4(&sc->sc, EHCI_USBINTR); | | 289 | (void)EOREAD4(&sc->sc, EHCI_USBINTR); |
286 | | | 290 | |
287 | if (sc->sc_ih != NULL) { | | 291 | if (sc->sc_ih != NULL) { |
288 | pci_intr_disestablish(sc->sc_pc, sc->sc_ih); | | 292 | pci_intr_disestablish(sc->sc_pc, sc->sc_ih); |
289 | sc->sc_ih = NULL; | | 293 | sc->sc_ih = NULL; |
290 | } | | 294 | } |
291 | if (sc->sc.sc_size) { | | 295 | if (sc->sc.sc_size) { |
292 | ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); | | 296 | ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); |
293 | bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); | | 297 | bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); |
294 | sc->sc.sc_size = 0; | | 298 | sc->sc.sc_size = 0; |
295 | } | | 299 | } |
296 | | | 300 | |
297 | #if 1 | | 301 | #if 1 |
298 | /* XXX created in ehci.c */ | | 302 | /* XXX created in ehci.c */ |
299 | mutex_destroy(&sc->sc.sc_lock); | | 303 | mutex_destroy(&sc->sc.sc_lock); |
300 | mutex_destroy(&sc->sc.sc_intr_lock); | | 304 | mutex_destroy(&sc->sc.sc_intr_lock); |
301 | | | 305 | |
302 | softint_disestablish(sc->sc.sc_doorbell_si); | | 306 | softint_disestablish(sc->sc.sc_doorbell_si); |
303 | softint_disestablish(sc->sc.sc_pcd_si); | | 307 | softint_disestablish(sc->sc.sc_pcd_si); |
304 | #endif | | 308 | #endif |
305 | | | 309 | |
306 | return 0; | | 310 | return 0; |
307 | } | | 311 | } |
308 | | | 312 | |
309 | CFATTACH_DECL3_NEW(ehci_pci, sizeof(struct ehci_pci_softc), | | 313 | CFATTACH_DECL3_NEW(ehci_pci, sizeof(struct ehci_pci_softc), |
310 | ehci_pci_match, ehci_pci_attach, ehci_pci_detach, ehci_activate, NULL, | | 314 | ehci_pci_match, ehci_pci_attach, ehci_pci_detach, ehci_activate, NULL, |
311 | ehci_childdet, DVF_DETACH_SHUTDOWN); | | 315 | ehci_childdet, DVF_DETACH_SHUTDOWN); |
312 | | | 316 | |
313 | #ifdef EHCI_DEBUG | | 317 | #ifdef EHCI_DEBUG |
314 | static void | | 318 | static void |
315 | ehci_dump_caps(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) | | 319 | ehci_dump_caps(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) |
316 | { | | 320 | { |
317 | uint32_t cparams, legctlsts, addr, cap, id; | | 321 | uint32_t cparams, legctlsts, addr, cap, id; |
318 | int maxdump = 10; | | 322 | int maxdump = 10; |
319 | | | 323 | |
320 | cparams = EREAD4(sc, EHCI_HCCPARAMS); | | 324 | cparams = EREAD4(sc, EHCI_HCCPARAMS); |
321 | addr = EHCI_HCC_EECP(cparams); | | 325 | addr = EHCI_HCC_EECP(cparams); |
322 | while (addr != 0) { | | 326 | while (addr != 0) { |
323 | cap = pci_conf_read(pc, tag, addr); | | 327 | cap = pci_conf_read(pc, tag, addr); |
324 | id = EHCI_CAP_GET_ID(cap); | | 328 | id = EHCI_CAP_GET_ID(cap); |
325 | switch (id) { | | 329 | switch (id) { |
326 | case EHCI_CAP_ID_LEGACY: | | 330 | case EHCI_CAP_ID_LEGACY: |
327 | legctlsts = pci_conf_read(pc, tag, | | 331 | legctlsts = pci_conf_read(pc, tag, |
328 | addr + PCI_EHCI_USBLEGCTLSTS); | | 332 | addr + PCI_EHCI_USBLEGCTLSTS); |
329 | printf("ehci_dump_caps: legsup=0x%08x " | | 333 | printf("ehci_dump_caps: legsup=0x%08x " |
330 | "legctlsts=0x%08x\n", cap, legctlsts); | | 334 | "legctlsts=0x%08x\n", cap, legctlsts); |
331 | break; | | 335 | break; |
332 | default: | | 336 | default: |
333 | printf("ehci_dump_caps: cap=0x%08x\n", cap); | | 337 | printf("ehci_dump_caps: cap=0x%08x\n", cap); |
334 | break; | | 338 | break; |
335 | } | | 339 | } |
336 | if (--maxdump < 0) | | 340 | if (--maxdump < 0) |
337 | break; | | 341 | break; |
338 | addr = EHCI_CAP_GET_NEXT(cap); | | 342 | addr = EHCI_CAP_GET_NEXT(cap); |
339 | } | | 343 | } |
340 | } | | 344 | } |
341 | #endif | | 345 | #endif |
342 | | | 346 | |
343 | static void | | 347 | static void |
344 | ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) | | 348 | ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) |
345 | { | | 349 | { |
346 | const char *devname = device_xname(sc->sc_dev); | | 350 | const char *devname = device_xname(sc->sc_dev); |
347 | uint32_t cparams, addr, cap; | | 351 | uint32_t cparams, addr, cap; |
348 | pcireg_t legsup; | | 352 | pcireg_t legsup; |
349 | int maxcap = 10; | | 353 | int maxcap = 10; |
350 | | | 354 | |
351 | cparams = EREAD4(sc, EHCI_HCCPARAMS); | | 355 | cparams = EREAD4(sc, EHCI_HCCPARAMS); |
352 | addr = EHCI_HCC_EECP(cparams); | | 356 | addr = EHCI_HCC_EECP(cparams); |
353 | while (addr != 0) { | | 357 | while (addr != 0) { |
354 | cap = pci_conf_read(pc, tag, addr); | | 358 | cap = pci_conf_read(pc, tag, addr); |
355 | if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) | | 359 | if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) |
356 | goto next; | | 360 | goto next; |
357 | legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); | | 361 | legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); |
358 | pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, | | 362 | pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, |
359 | legsup & ~EHCI_LEG_HC_OS_OWNED); | | 363 | legsup & ~EHCI_LEG_HC_OS_OWNED); |
360 | | | 364 | |
361 | next: | | 365 | next: |
362 | if (--maxcap < 0) { | | 366 | if (--maxcap < 0) { |
363 | aprint_normal("%s: broken extended capabilities " | | 367 | aprint_normal("%s: broken extended capabilities " |
364 | "ignored\n", devname); | | 368 | "ignored\n", devname); |
365 | return; | | 369 | return; |
366 | } | | 370 | } |
367 | addr = EHCI_CAP_GET_NEXT(cap); | | 371 | addr = EHCI_CAP_GET_NEXT(cap); |
368 | } | | 372 | } |
369 | } | | 373 | } |
370 | | | 374 | |
371 | static void | | 375 | static void |
372 | ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) | | 376 | ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) |
373 | { | | 377 | { |
374 | const char *devname = device_xname(sc->sc_dev); | | 378 | const char *devname = device_xname(sc->sc_dev); |
375 | uint32_t cparams, addr, cap; | | 379 | uint32_t cparams, addr, cap; |
376 | pcireg_t legsup; | | 380 | pcireg_t legsup; |
377 | int maxcap = 10; | | 381 | int maxcap = 10; |
378 | int ms; | | 382 | int ms; |
379 | | | 383 | |
380 | #ifdef EHCI_DEBUG | | 384 | #ifdef EHCI_DEBUG |
381 | if (ehcidebug) | | 385 | if (ehcidebug) |
382 | ehci_dump_caps(sc, pc, tag); | | 386 | ehci_dump_caps(sc, pc, tag); |
383 | #endif | | 387 | #endif |
384 | cparams = EREAD4(sc, EHCI_HCCPARAMS); | | 388 | cparams = EREAD4(sc, EHCI_HCCPARAMS); |
385 | addr = EHCI_HCC_EECP(cparams); | | 389 | addr = EHCI_HCC_EECP(cparams); |
386 | while (addr != 0) { | | 390 | while (addr != 0) { |
387 | cap = pci_conf_read(pc, tag, addr); | | 391 | cap = pci_conf_read(pc, tag, addr); |
388 | if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) | | 392 | if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) |
389 | goto next; | | 393 | goto next; |
390 | legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); | | 394 | legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); |
391 | if (legsup & EHCI_LEG_HC_BIOS_OWNED) { | | 395 | if (legsup & EHCI_LEG_HC_BIOS_OWNED) { |
392 | /* Ask BIOS to give up ownership */ | | 396 | /* Ask BIOS to give up ownership */ |
393 | pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, | | 397 | pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, |
394 | legsup | EHCI_LEG_HC_OS_OWNED); | | 398 | legsup | EHCI_LEG_HC_OS_OWNED); |
395 | for (ms = 0; ms < EHCI_MAX_BIOS_WAIT; ms++) { | | 399 | for (ms = 0; ms < EHCI_MAX_BIOS_WAIT; ms++) { |
396 | legsup = pci_conf_read(pc, tag, | | 400 | legsup = pci_conf_read(pc, tag, |
397 | addr + PCI_EHCI_USBLEGSUP); | | 401 | addr + PCI_EHCI_USBLEGSUP); |
398 | if (!(legsup & EHCI_LEG_HC_BIOS_OWNED)) | | 402 | if (!(legsup & EHCI_LEG_HC_BIOS_OWNED)) |
399 | break; | | 403 | break; |
400 | delay(10000); | | 404 | delay(10000); |
401 | } | | 405 | } |
402 | if (ms == EHCI_MAX_BIOS_WAIT) { | | 406 | if (ms == EHCI_MAX_BIOS_WAIT) { |
403 | aprint_normal("%s: BIOS refuses to give up " | | 407 | aprint_normal("%s: BIOS refuses to give up " |
404 | "ownership, using force\n", devname); | | 408 | "ownership, using force\n", devname); |
405 | pci_conf_write(pc, tag, | | 409 | pci_conf_write(pc, tag, |
406 | addr + PCI_EHCI_USBLEGSUP, 0); | | 410 | addr + PCI_EHCI_USBLEGSUP, 0); |
407 | } else | | 411 | } else |
408 | aprint_verbose("%s: BIOS has given up " | | 412 | aprint_verbose("%s: BIOS has given up " |
409 | "ownership\n", devname); | | 413 | "ownership\n", devname); |
410 | } | | 414 | } |
411 | | | 415 | |
412 | /* Disable SMIs */ | | 416 | /* Disable SMIs */ |
413 | pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGCTLSTS, 0); | | 417 | pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGCTLSTS, 0); |
414 | | | 418 | |
415 | next: | | 419 | next: |
416 | if (--maxcap < 0) { | | 420 | if (--maxcap < 0) { |
417 | aprint_normal("%s: broken extended capabilities " | | 421 | aprint_normal("%s: broken extended capabilities " |
418 | "ignored\n", devname); | | 422 | "ignored\n", devname); |
419 | return; | | 423 | return; |
420 | } | | 424 | } |
421 | addr = EHCI_CAP_GET_NEXT(cap); | | 425 | addr = EHCI_CAP_GET_NEXT(cap); |
422 | } | | 426 | } |
423 | | | 427 | |
424 | } | | 428 | } |
425 | | | 429 | |
426 | static bool | | 430 | static bool |
427 | ehci_pci_suspend(device_t dv, const pmf_qual_t *qual) | | 431 | ehci_pci_suspend(device_t dv, const pmf_qual_t *qual) |
428 | { | | 432 | { |
429 | struct ehci_pci_softc *sc = device_private(dv); | | 433 | struct ehci_pci_softc *sc = device_private(dv); |
430 | | | 434 | |
431 | ehci_suspend(dv, qual); | | 435 | ehci_suspend(dv, qual); |
432 | ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); | | 436 | ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); |
433 | | | 437 | |
434 | return true; | | 438 | return true; |
435 | } | | 439 | } |
436 | | | 440 | |
437 | static bool | | 441 | static bool |
438 | ehci_pci_resume(device_t dv, const pmf_qual_t *qual) | | 442 | ehci_pci_resume(device_t dv, const pmf_qual_t *qual) |
439 | { | | 443 | { |
440 | struct ehci_pci_softc *sc = device_private(dv); | | 444 | struct ehci_pci_softc *sc = device_private(dv); |
441 | | | 445 | |
442 | ehci_get_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); | | 446 | ehci_get_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); |
443 | return ehci_resume(dv, qual); | | 447 | return ehci_resume(dv, qual); |
444 | } | | 448 | } |
445 | | | 449 | |
446 | static int | | 450 | static int |
447 | ehci_sb700_match(const struct pci_attach_args *pa) | | 451 | ehci_sb700_match(const struct pci_attach_args *pa) |
448 | { | | 452 | { |
449 | if (!(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI && | | 453 | if (!(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI && |
450 | PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB)) | | 454 | PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB)) |
451 | return 0; | | 455 | return 0; |
452 | | | 456 | |
453 | switch (PCI_REVISION(pa->pa_class)) { | | 457 | switch (PCI_REVISION(pa->pa_class)) { |
454 | case 0x3a: | | 458 | case 0x3a: |
455 | case 0x3b: | | 459 | case 0x3b: |
456 | return 1; | | 460 | return 1; |
457 | } | | 461 | } |
458 | | | 462 | |
459 | return 0; | | 463 | return 0; |
460 | } | | 464 | } |
461 | | | 465 | |
462 | static int | | 466 | static int |
463 | ehci_apply_amd_quirks(struct ehci_pci_softc *sc) | | 467 | ehci_apply_amd_quirks(struct ehci_pci_softc *sc) |
464 | { | | 468 | { |
465 | pcireg_t value; | | 469 | pcireg_t value; |
466 | | | 470 | |
467 | aprint_normal_dev(sc->sc.sc_dev, | | 471 | aprint_normal_dev(sc->sc.sc_dev, |
468 | "applying AMD SB600/SB700 USB freeze workaround\n"); | | 472 | "applying AMD SB600/SB700 USB freeze workaround\n"); |
469 | value = pci_conf_read(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG); | | 473 | value = pci_conf_read(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG); |
470 | pci_conf_write(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG, | | 474 | pci_conf_write(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG, |
471 | value | EHCI_SBx00_WORKAROUND_ENABLE); | | 475 | value | EHCI_SBx00_WORKAROUND_ENABLE); |
472 | | | 476 | |
473 | return 0; | | 477 | return 0; |
474 | } | | 478 | } |
475 | | | 479 | |
476 | enum ehci_pci_quirk_flags | | 480 | enum ehci_pci_quirk_flags |
477 | ehci_pci_lookup_quirkdata(pci_vendor_id_t vendor, pci_product_id_t product) | | 481 | ehci_pci_lookup_quirkdata(pci_vendor_id_t vendor, pci_product_id_t product) |
478 | { | | 482 | { |
479 | int i; | | 483 | int i; |
480 | | | 484 | |
481 | for (i = 0; i < __arraycount(ehci_pci_quirks); i++) { | | 485 | for (i = 0; i < __arraycount(ehci_pci_quirks); i++) { |
482 | if (vendor == ehci_pci_quirks[i].vendor && | | 486 | if (vendor == ehci_pci_quirks[i].vendor && |
483 | product == ehci_pci_quirks[i].product) | | 487 | product == ehci_pci_quirks[i].product) |
484 | return ehci_pci_quirks[i].quirks; | | 488 | return ehci_pci_quirks[i].quirks; |
485 | } | | 489 | } |
486 | return 0; | | 490 | return 0; |
487 | } | | 491 | } |
488 | | | 492 | |