 @@ -1,14 +1,14 @@
-/*	$NetBSD: pci_subr.c,v 1.186 2017/06/08 03:39:18 msaitoh Exp $	*/
+/*	$NetBSD: pci_subr.c,v 1.187 2017/06/15 05:42:27 msaitoh Exp $	*/
 /*
  * Copyright (c) 1997 Zubin D. Dittia.  All rights reserved.
  * Copyright (c) 1995, 1996, 1998, 2000
  *	Christopher G. Demetriou.  All rights reserved.
  * Copyright (c) 1994 Charles M. Hannum.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
 @@ -30,27 +30,27 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * PCI autoconfiguration support functions.
+ *
  * Note: This file is also built into a userland library (libpci).
  * Pay attention to this when you make modifications.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.186 2017/06/08 03:39:18 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.187 2017/06/15 05:42:27 msaitoh Exp $");
 #ifdef _KERNEL_OPT
 #include "opt_pci.h"
 #endif
 #include <sys/param.h>
 #ifdef _KERNEL
 #include <sys/systm.h>
 #include <sys/intr.h>
 #include <sys/module.h>
 #else
 #include <pci.h>
 @@ -1897,28 +1897,30 @@ pci_conf_print_pcie_cap(const pcireg_t *
 		printf("      Negotiated Link Width: x%u lanes\n",
 		    (unsigned int)__SHIFTOUT(reg, PCIE_LCSR_NLW));
 		onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR);
 		onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN);
 		onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG);
 		onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE);
 		onoff("Link Bandwidth Management Status", reg,
 		    PCIE_LCSR_LINK_BW_MGMT);
 		onoff("Link Autonomous Bandwidth Status", reg,
 		    PCIE_LCSR_LINK_AUTO_BW);
+	}
 	if (check_slot == true) {
 		pcireg_t slcap;
 		/* Slot Capability Register */
-		reg = regs[o2i(capoff + PCIE_SLCAP)];
+		slcap = reg = regs[o2i(capoff + PCIE_SLCAP)];
 		printf("    Slot Capability Register: 0x%08x\n", reg);
 		onoff("Attention Button Present", reg, PCIE_SLCAP_ABP);
 		onoff("Power Controller Present", reg, PCIE_SLCAP_PCP);
 		onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP);
 		onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP);
 		onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP);
 		onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS);
 		onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC);
 		printf("      Slot Power Limit Value: ");
 		pci_conf_print_pcie_power(__SHIFTOUT(reg, PCIE_SLCAP_SPLV),
 		    __SHIFTOUT(reg, PCIE_SLCAP_SPLS));
 		onoff("Electromechanical Interlock Present", reg,
 		    PCIE_SLCAP_EIP);
 @@ -1926,55 +1928,64 @@ pci_conf_print_pcie_cap(const pcireg_t *
 		printf("      Physical Slot Number: %d\n",
 		    (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19);
 		/* Slot Control Register */
 		reg = regs[o2i(capoff + PCIE_SLCSR)];
 		printf("    Slot Control Register: 0x%04x\n", reg & 0xffff);
 		onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE);
 		onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE);
 		onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE);
 		onoff("Presence Detect Changed Enabled", reg, PCIE_SLCSR_PDE);
 		onoff("Command Completed Interrupt Enabled", reg,
 		    PCIE_SLCSR_CCE);
 		onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE);
-		printf("      Attention Indicator Control: ");
+		/*
-		switch ((reg & PCIE_SLCSR_AIC) >> 6) {
+		 * For Attention Indicator Control and Power Indicator Control,
-		case 0x0:
+		 * it's allowed to be a read only value 0 if corresponding
-			printf("reserved\n");
+		 * capability register bit is 0.
-			break;
+		 */
-		case PCIE_SLCSR_IND_ON:
+		if (slcap & PCIE_SLCAP_AIP) {
-			printf("on\n");
+			printf("      Attention Indicator Control: ");
-			break;
+			switch ((reg & PCIE_SLCSR_AIC) >> 6) {
-		case PCIE_SLCSR_IND_BLINK:
+			case 0x0:
-			printf("blink\n");
+				printf("reserved\n");
-			break;
+				break;
-		case PCIE_SLCSR_IND_OFF:
+			case PCIE_SLCSR_IND_ON:
-			printf("off\n");
+				printf("on\n");
-			break;
+				break;
 			case PCIE_SLCSR_IND_BLINK:
 				printf("blink\n");
 				break;
 			case PCIE_SLCSR_IND_OFF:
 				printf("off\n");
 				break;
+			}
+		}
-		printf("      Power Indicator Control: ");
+		if (slcap & PCIE_SLCAP_PIP) {
-		switch ((reg & PCIE_SLCSR_PIC) >> 8) {
+			printf("      Power Indicator Control: ");
-		case 0x0:
+			switch ((reg & PCIE_SLCSR_PIC) >> 8) {
-			printf("reserved\n");
+			case 0x0:
-			break;
+				printf("reserved\n");
-		case PCIE_SLCSR_IND_ON:
+				break;
-			printf("on\n");
+			case PCIE_SLCSR_IND_ON:
-			break;
+				printf("on\n");
-		case PCIE_SLCSR_IND_BLINK:
+				break;
-			printf("blink\n");
+			case PCIE_SLCSR_IND_BLINK:
-			break;
+				printf("blink\n");
-		case PCIE_SLCSR_IND_OFF:
+				break;
-			printf("off\n");
+			case PCIE_SLCSR_IND_OFF:
-			break;
+				printf("off\n");
 				break;
+			}
+		}
 		printf("      Power Controller Control: Power %s\n",
 		    reg & PCIE_SLCSR_PCC ? "off" : "on");
 		onoff("Electromechanical Interlock Control",
 		    reg, PCIE_SLCSR_EIC);
 		onoff("Data Link Layer State Changed Enable", reg,
 		    PCIE_SLCSR_DLLSCE);
 		onoff("Auto Slot Power Limit Disable", reg,
 		    PCIE_SLCSR_AUTOSPLDIS);
 		/* Slot Status Register */
 		printf("    Slot Status Register: 0x%04x\n", reg >> 16);
 		onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP);