 @@ -1,976 +1,976 @@
-/*	$NetBSD: vector.S,v 1.50 2017/07/16 14:02:48 cherry Exp $	*/
+/*	$NetBSD: vector.S,v 1.51 2017/08/15 09:08:39 maxv Exp $	*/
 /*-
  * Copyright (c) 1998, 2007, 2008 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Charles M. Hannum and by Andrew Doran.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Copyright (c) 2001 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Frank van der Linden for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *      This product includes software developed for the NetBSD Project by
  *      Wasabi Systems, Inc.
  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  *    or promote products derived from this software without specific prior
  *    written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <machine/asm.h>
 #include "opt_ddb.h"
 #include "opt_multiprocessor.h"
 #include "opt_xen.h"
 #include "opt_dtrace.h"
 #define ALIGN_TEXT	.align 16,0x90
 #include <machine/i8259.h>
 #include <machine/i82093reg.h>
 #include <machine/i82489reg.h>
 #include <machine/frameasm.h>
 #include <machine/segments.h>
 #include <machine/trap.h>
 #include <machine/specialreg.h>
 #include "ioapic.h"
 #include "lapic.h"
 #include "assym.h"
 #include "amd64_trap.S"
 /*****************************************************************************/
 #define __HAVE_GENERIC_SOFT_INTERRUPTS	/* XXX */
 /*
  * Macros for interrupt entry, call to handler, and exit.
+ *
  * XXX
  * The interrupt frame is set up to look like a trap frame.  This may be a
  * waste.  The only handler which needs a frame is the clock handler, and it
  * only needs a few bits.  Xdoreti() needs a trap frame for handling ASTs, but
  * it could easily convert the frame on demand.
+ *
  * The direct costs of setting up a trap frame are two pushq's (error code and
  * trap number), an addl to get rid of these, and pushing and popping the
  * callee-saved registers %esi, %edi, %ebx, and %ebp twice.
+ *
  * If the interrupt frame is made more flexible,  INTR can push %eax first and
  * decide the ipending case with less overhead, e.g., by avoiding loading the
  * segment registers.
  */
 #if NLAPIC > 0
 #ifdef MULTIPROCESSOR
 IDTVEC(recurse_lapic_ipi)
 	INTR_RECURSE_HWFRAME
 	pushq	$0
 	pushq	$T_ASTFLT
 	INTRENTRY
 	jmp	1f
 IDTVEC_END(recurse_lapic_ipi)
 IDTVEC(intr_x2apic_ipi)
 	pushq	$0
 	pushq	$T_ASTFLT
 	INTRENTRY
 	movl	$(MSR_X2APIC_BASE + MSR_X2APIC_EOI),%ecx
 	xorl	%eax,%eax
 	xorl	%edx,%edx
 	wrmsr
 	movl	CPUVAR(ILEVEL),%ebx
 	cmpl	$IPL_HIGH,%ebx
 	jae	2f
 	jmp	1f
 IDTVEC_END(intr_x2apic_ipi)
 IDTVEC(intr_lapic_ipi)
 	pushq	$0
 	pushq	$T_ASTFLT
 	INTRENTRY
 	movq	_C_LABEL(local_apic_va),%rbx
 	movl	$0,LAPIC_EOI(%rbx)
 	movl	CPUVAR(ILEVEL),%ebx
 	cmpl	$IPL_HIGH,%ebx
 	jae	2f
 IDTVEC_END(intr_lapic_ipi)
 IDTVEC(resume_lapic_ipi)
 :
 	incl	CPUVAR(IDEPTH)
 	movl	$IPL_HIGH,CPUVAR(ILEVEL)
 	sti
 	pushq	%rbx
 	call	_C_LABEL(x86_ipi_handler)
 	jmp	_C_LABEL(Xdoreti)
 :
 	orl	$(1 << LIR_IPI),CPUVAR(IPENDING)
 	INTRFASTEXIT
 IDTVEC_END(resume_lapic_ipi)
 #if defined(DDB)
-IDTVEC(intrddb)
+IDTVEC(intrddbipi)
 :
 	pushq	$0
 	pushq	$T_BPTFLT
 	INTRENTRY
 	movl	$0xf,%eax
 	movq	%rax,%cr8
 	movq	_C_LABEL(local_apic_va),%rbx
 	movl	$0,LAPIC_EOI(%rbx)
 	sti
 	call	_C_LABEL(ddb_ipi)
 	xorl	%eax,%eax
 	movq	%rax,%cr8
 	INTRFASTEXIT
-IDTVEC_END(intrddb)
+IDTVEC_END(intrddbipi)
-IDTVEC(x2apic_intrddb)
+IDTVEC(x2apic_intrddbipi)
 :
 	pushq	$0
 	pushq	$T_BPTFLT
 	INTRENTRY
 	movl	$0xf,%eax
 	movq	%rax,%cr8
 	movl	$(MSR_X2APIC_BASE + MSR_X2APIC_EOI),%ecx
 	xorl	%eax,%eax
 	xorl	%edx,%edx
 	wrmsr
 	sti
 	call	_C_LABEL(ddb_ipi)
 	xorl	%eax,%eax
 	movq	%rax,%cr8
 	INTRFASTEXIT
-IDTVEC_END(x2apic_intrddb)
+IDTVEC_END(x2apic_intrddbipi)
 #endif /* DDB */
 #endif /* MULTIPROCESSOR */
 	/*
 	 * Interrupt from the local APIC timer.
 	 */
 IDTVEC(recurse_lapic_ltimer)
 	INTR_RECURSE_HWFRAME
 	pushq	$0
 	pushq	$T_ASTFLT
 	INTRENTRY
 	jmp	1f
 IDTVEC_END(recurse_lapic_ltimer)
 IDTVEC(intr_x2apic_ltimer)
 	pushq	$0
 	pushq	$T_ASTFLT
 	INTRENTRY
 	movl	$(MSR_X2APIC_BASE + MSR_X2APIC_EOI),%ecx
 	xorl	%eax,%eax
 	xorl	%edx,%edx
 	wrmsr
 	movl	CPUVAR(ILEVEL),%ebx
 	cmpl	$IPL_CLOCK,%ebx
 	jae	2f
 	jmp	1f
 IDTVEC_END(intr_x2apic_ltimer)
 IDTVEC(intr_lapic_ltimer)
 	pushq	$0
 	pushq	$T_ASTFLT
 	INTRENTRY
 	movq	_C_LABEL(local_apic_va),%rbx
 	movl	$0,LAPIC_EOI(%rbx)
 	movl	CPUVAR(ILEVEL),%ebx
 	cmpl	$IPL_CLOCK,%ebx
 	jae	2f
 IDTVEC_END(intr_lapic_ltimer)
 IDTVEC(resume_lapic_ltimer)
 :
 	incl	CPUVAR(IDEPTH)
 	movl	$IPL_CLOCK,CPUVAR(ILEVEL)
 	sti
 	pushq	%rbx
 	movq	%rsp,%rsi
 	xorq	%rdi,%rdi
 	call	_C_LABEL(lapic_clockintr)
 	jmp	_C_LABEL(Xdoreti)
 :
 	orl	$(1 << LIR_TIMER),CPUVAR(IPENDING)
 	INTRFASTEXIT
 IDTVEC_END(resume_lapic_ltimer)
 #endif /* NLAPIC > 0 */
 #ifndef XEN
 /*
  * TLB shootdown handler.
  */
 IDTVEC(intr_lapic_tlb)
 	pushq	$0
 	pushq	$T_ASTFLT
 	INTRENTRY
 	movq	_C_LABEL(local_apic_va),%rax
 	movl	$0,LAPIC_EOI(%rax)
 	callq	_C_LABEL(pmap_tlb_intr)
 	INTRFASTEXIT
 IDTVEC_END(intr_lapic_tlb)
 IDTVEC(intr_x2apic_tlb)
 	pushq	$0
 	pushq	$T_ASTFLT
 	INTRENTRY
 	movl	$(MSR_X2APIC_BASE + MSR_X2APIC_EOI),%ecx
 	xorl	%eax,%eax
 	xorl	%edx,%edx
 	wrmsr
 	callq	_C_LABEL(pmap_tlb_intr)
 	INTRFASTEXIT
 IDTVEC_END(intr_x2apic_tlb)
 #endif /* !XEN */
 #define voidop(num)
 #ifndef XEN
 /*
  * This macro defines the generic stub code. Its arguments modifiy it
  * for specific PICs.
  */
 #define	INTRSTUB(name, num, early_ack, late_ack, mask, unmask, level_mask) \
 IDTVEC(recurse_ ## name ## num)						;\
 	INTR_RECURSE_HWFRAME						;\
 	subq	$8,%rsp							;\
 	pushq	$T_ASTFLT		/* trap # for doing ASTs */	;\
 	INTRENTRY							;\
 IDTVEC(resume_ ## name ## num)						\
 	movq	$IREENT_MAGIC,TF_ERR(%rsp)				;\
 	movl	%ebx,%r13d						;\
 	movq	CPUVAR(ISOURCES) + (num) * 8,%r14			;\
 	movl	IS_MAXLEVEL(%r14),%ebx					;\
 	jmp	1f							;\
 IDTVEC(intr_ ## name ## num)						;\
 	pushq	$0			/* dummy error code */		;\
 	pushq	$T_ASTFLT		/* trap # for doing ASTs */	;\
 	INTRENTRY							;\
 	movq	CPUVAR(ISOURCES) + (num) * 8,%r14			;\
 	mask(num)			/* mask it in hardware */	;\
 	early_ack(num)			/* and allow other intrs */	;\
 	testq	%r14,%r14						;\
 	jz	9f			/* stray */			;\
 	movl	IS_MAXLEVEL(%r14),%ebx					;\
 	movl	CPUVAR(ILEVEL),%r13d					;\
 	cmpl	%ebx,%r13d						;\
 	jae	10f			/* currently masked; hold it */	;\
 	incq	CPUVAR(NINTR)		/* statistical info */		;\
 	incq	IS_EVCNT(%r14)						;\
 :									\
 	pushq	%r13			/* save for Xdoreti */		;\
 	movl	%ebx,CPUVAR(ILEVEL)					;\
 	sti								;\
 	incl	CPUVAR(IDEPTH)						;\
 	movq	IS_HANDLERS(%r14),%rbx					;\
 :									\
 	movl	IH_LEVEL(%rbx),%r12d					;\
 	cmpl	%r13d,%r12d						;\
 	jle	7f							;\
 	movq	%rsp,%rsi						;\
 	movq	IH_ARG(%rbx),%rdi					;\
 	movl	%r12d,CPUVAR(ILEVEL)					;\
 	call	*IH_FUN(%rbx)		/* call it */			;\
 	movq	IH_NEXT(%rbx),%rbx	/* next handler in chain */	;\
 	testq	%rbx,%rbx						;\
 	jnz	6b							;\
 :									\
 	cli								;\
 	unmask(num)			/* unmask it in hardware */	;\
 	late_ack(num)							;\
 	sti								;\
 	jmp	_C_LABEL(Xdoreti)	/* lower spl and do ASTs */	;\
 :									\
 	cli								;\
 	orl	$(1 << num),CPUVAR(IPENDING)				;\
 	level_mask(num)							;\
 	late_ack(num)							;\
 	sti								;\
 	jmp	_C_LABEL(Xdoreti)	/* lower spl and do ASTs */	;\
 :									\
 	cli								;\
 	orl	$(1 << num),CPUVAR(IPENDING)				;\
 	level_mask(num)							;\
 	late_ack(num)							;\
 	INTRFASTEXIT							;\
 :									\
 	unmask(num)							;\
 	late_ack(num)							;\
 	INTRFASTEXIT
 #define ICUADDR IO_ICU1
 INTRSTUB(legacy,0,i8259_asm_ack1,voidop,i8259_asm_mask,i8259_asm_unmask,
     voidop)
 INTRSTUB(legacy,1,i8259_asm_ack1,voidop,i8259_asm_mask,i8259_asm_unmask,
     voidop)
 INTRSTUB(legacy,2,i8259_asm_ack1,voidop,i8259_asm_mask,i8259_asm_unmask,
     voidop)
 INTRSTUB(legacy,3,i8259_asm_ack1,voidop,i8259_asm_mask,i8259_asm_unmask,
     voidop)
 INTRSTUB(legacy,4,i8259_asm_ack1,voidop,i8259_asm_mask,i8259_asm_unmask,
     voidop)
 INTRSTUB(legacy,5,i8259_asm_ack1,voidop,i8259_asm_mask,i8259_asm_unmask,
     voidop)
 INTRSTUB(legacy,6,i8259_asm_ack1,voidop,i8259_asm_mask,i8259_asm_unmask,
     voidop)
 INTRSTUB(legacy,7,i8259_asm_ack1,voidop,i8259_asm_mask,i8259_asm_unmask,
     voidop)
 #undef ICUADDR
 #define ICUADDR IO_ICU2
 INTRSTUB(legacy,8,i8259_asm_ack2,voidop,i8259_asm_mask,i8259_asm_unmask,
     voidop)
 INTRSTUB(legacy,9,i8259_asm_ack2,voidop,i8259_asm_mask,i8259_asm_unmask,
     voidop)
 INTRSTUB(legacy,10,i8259_asm_ack2,voidop,i8259_asm_mask,i8259_asm_unmask,
     voidop)
 INTRSTUB(legacy,11,i8259_asm_ack2,voidop,i8259_asm_mask,i8259_asm_unmask,
     voidop)
 INTRSTUB(legacy,12,i8259_asm_ack2,voidop,i8259_asm_mask,i8259_asm_unmask,
     voidop)
 INTRSTUB(legacy,13,i8259_asm_ack2,voidop,i8259_asm_mask,i8259_asm_unmask,
     voidop)
 INTRSTUB(legacy,14,i8259_asm_ack2,voidop,i8259_asm_mask,i8259_asm_unmask,
     voidop)
 INTRSTUB(legacy,15,i8259_asm_ack2,voidop,i8259_asm_mask,i8259_asm_unmask,
     voidop)
 #if NIOAPIC > 0
 INTRSTUB(ioapic_edge,0,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,1,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,2,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,3,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,4,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,5,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,6,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,7,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,8,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,9,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,10,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,11,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,12,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,13,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,14,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,15,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,16,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,17,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,18,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,19,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,20,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,21,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,22,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,23,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,24,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,25,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,26,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,27,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,28,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,29,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,30,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_edge,31,voidop,ioapic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(ioapic_level,0,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,1,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,2,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,3,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,4,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,5,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,6,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,7,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,8,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,9,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,10,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,11,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,12,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,13,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,14,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,15,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,16,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,17,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,18,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,19,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,20,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,21,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,22,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,23,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,24,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,25,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,26,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,27,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,28,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,29,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,30,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(ioapic_level,31,voidop,ioapic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_edge,0,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,1,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,2,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,3,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,4,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,5,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,6,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,7,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,8,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,9,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,10,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,11,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,12,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,13,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,14,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,15,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,16,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,17,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,18,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,19,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,20,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,21,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,22,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,23,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,24,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,25,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,26,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,27,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,28,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,29,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,30,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_edge,31,voidop,x2apic_asm_ack,voidop,voidop,voidop)
 INTRSTUB(x2apic_level,0,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,1,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,2,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,3,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,4,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,5,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,6,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,7,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,8,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,9,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,10,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,11,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,12,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,13,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,14,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,15,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,16,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,17,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,18,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,19,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,20,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,21,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,22,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,23,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,24,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,25,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,26,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,27,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,28,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,29,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,30,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 INTRSTUB(x2apic_level,31,voidop,x2apic_asm_ack,voidop,ioapic_unmask,ioapic_mask)
 #endif
 	.type _C_LABEL(i8259_stubs), @object
 LABEL(i8259_stubs)
 	.quad _C_LABEL(Xintr_legacy0), _C_LABEL(Xrecurse_legacy0)
 	.quad _C_LABEL(Xresume_legacy0)
 	.quad _C_LABEL(Xintr_legacy1), _C_LABEL(Xrecurse_legacy1)
 	.quad _C_LABEL(Xresume_legacy1)
 	.quad _C_LABEL(Xintr_legacy2), _C_LABEL(Xrecurse_legacy2)
 	.quad _C_LABEL(Xresume_legacy2)
 	.quad _C_LABEL(Xintr_legacy3), _C_LABEL(Xrecurse_legacy3)
 	.quad _C_LABEL(Xresume_legacy3)
 	.quad _C_LABEL(Xintr_legacy4), _C_LABEL(Xrecurse_legacy4)
 	.quad _C_LABEL(Xresume_legacy4)
 	.quad _C_LABEL(Xintr_legacy5), _C_LABEL(Xrecurse_legacy5)
 	.quad _C_LABEL(Xresume_legacy5)
 	.quad _C_LABEL(Xintr_legacy6), _C_LABEL(Xrecurse_legacy6)
 	.quad _C_LABEL(Xresume_legacy6)
 	.quad _C_LABEL(Xintr_legacy7), _C_LABEL(Xrecurse_legacy7)
 	.quad _C_LABEL(Xresume_legacy7)
 	.quad _C_LABEL(Xintr_legacy8), _C_LABEL(Xrecurse_legacy8)
 	.quad _C_LABEL(Xresume_legacy8)
 	.quad _C_LABEL(Xintr_legacy9), _C_LABEL(Xrecurse_legacy9)
 	.quad _C_LABEL(Xresume_legacy9)
 	.quad _C_LABEL(Xintr_legacy10), _C_LABEL(Xrecurse_legacy10)
 	.quad _C_LABEL(Xresume_legacy10)
 	.quad _C_LABEL(Xintr_legacy11), _C_LABEL(Xrecurse_legacy11)
 	.quad _C_LABEL(Xresume_legacy11)
 	.quad _C_LABEL(Xintr_legacy12), _C_LABEL(Xrecurse_legacy12)
 	.quad _C_LABEL(Xresume_legacy12)
 	.quad _C_LABEL(Xintr_legacy13), _C_LABEL(Xrecurse_legacy13)
 	.quad _C_LABEL(Xresume_legacy13)
 	.quad _C_LABEL(Xintr_legacy14), _C_LABEL(Xrecurse_legacy14)
 	.quad _C_LABEL(Xresume_legacy14)
 	.quad _C_LABEL(Xintr_legacy15), _C_LABEL(Xrecurse_legacy15)
 	.quad _C_LABEL(Xresume_legacy15)
 END(i8259_stubs)
 #if NIOAPIC > 0
 	.type _C_LABEL(ioapic_edge_stubs), @object
 LABEL(ioapic_edge_stubs)
 	.quad _C_LABEL(Xintr_ioapic_edge0), _C_LABEL(Xrecurse_ioapic_edge0)
 	.quad _C_LABEL(Xresume_ioapic_edge0)
 	.quad _C_LABEL(Xintr_ioapic_edge1), _C_LABEL(Xrecurse_ioapic_edge1)
 	.quad _C_LABEL(Xresume_ioapic_edge1)
 	.quad _C_LABEL(Xintr_ioapic_edge2), _C_LABEL(Xrecurse_ioapic_edge2)
 	.quad _C_LABEL(Xresume_ioapic_edge2)
 	.quad _C_LABEL(Xintr_ioapic_edge3), _C_LABEL(Xrecurse_ioapic_edge3)
 	.quad _C_LABEL(Xresume_ioapic_edge3)
 	.quad _C_LABEL(Xintr_ioapic_edge4), _C_LABEL(Xrecurse_ioapic_edge4)
 	.quad _C_LABEL(Xresume_ioapic_edge4)
 	.quad _C_LABEL(Xintr_ioapic_edge5), _C_LABEL(Xrecurse_ioapic_edge5)
 	.quad _C_LABEL(Xresume_ioapic_edge5)
 	.quad _C_LABEL(Xintr_ioapic_edge6), _C_LABEL(Xrecurse_ioapic_edge6)
 	.quad _C_LABEL(Xresume_ioapic_edge6)
 	.quad _C_LABEL(Xintr_ioapic_edge7), _C_LABEL(Xrecurse_ioapic_edge7)
 	.quad _C_LABEL(Xresume_ioapic_edge7)
 	.quad _C_LABEL(Xintr_ioapic_edge8), _C_LABEL(Xrecurse_ioapic_edge8)
 	.quad _C_LABEL(Xresume_ioapic_edge8)
 	.quad _C_LABEL(Xintr_ioapic_edge9), _C_LABEL(Xrecurse_ioapic_edge9)
 	.quad _C_LABEL(Xresume_ioapic_edge9)
 	.quad _C_LABEL(Xintr_ioapic_edge10), _C_LABEL(Xrecurse_ioapic_edge10)
 	.quad _C_LABEL(Xresume_ioapic_edge10)
 	.quad _C_LABEL(Xintr_ioapic_edge11), _C_LABEL(Xrecurse_ioapic_edge11)
 	.quad _C_LABEL(Xresume_ioapic_edge11)
 	.quad _C_LABEL(Xintr_ioapic_edge12), _C_LABEL(Xrecurse_ioapic_edge12)
 	.quad _C_LABEL(Xresume_ioapic_edge12)
 	.quad _C_LABEL(Xintr_ioapic_edge13), _C_LABEL(Xrecurse_ioapic_edge13)
 	.quad _C_LABEL(Xresume_ioapic_edge13)
 	.quad _C_LABEL(Xintr_ioapic_edge14), _C_LABEL(Xrecurse_ioapic_edge14)
 	.quad _C_LABEL(Xresume_ioapic_edge14)
 	.quad _C_LABEL(Xintr_ioapic_edge15), _C_LABEL(Xrecurse_ioapic_edge15)
 	.quad _C_LABEL(Xresume_ioapic_edge15)
 	.quad _C_LABEL(Xintr_ioapic_edge16), _C_LABEL(Xrecurse_ioapic_edge16)
 	.quad _C_LABEL(Xresume_ioapic_edge16)
 	.quad _C_LABEL(Xintr_ioapic_edge17), _C_LABEL(Xrecurse_ioapic_edge17)
 	.quad _C_LABEL(Xresume_ioapic_edge17)
 	.quad _C_LABEL(Xintr_ioapic_edge18), _C_LABEL(Xrecurse_ioapic_edge18)
 	.quad _C_LABEL(Xresume_ioapic_edge18)
 	.quad _C_LABEL(Xintr_ioapic_edge19), _C_LABEL(Xrecurse_ioapic_edge19)
 	.quad _C_LABEL(Xresume_ioapic_edge19)
 	.quad _C_LABEL(Xintr_ioapic_edge20), _C_LABEL(Xrecurse_ioapic_edge20)
 	.quad _C_LABEL(Xresume_ioapic_edge20)
 	.quad _C_LABEL(Xintr_ioapic_edge21), _C_LABEL(Xrecurse_ioapic_edge21)
 	.quad _C_LABEL(Xresume_ioapic_edge21)
 	.quad _C_LABEL(Xintr_ioapic_edge22), _C_LABEL(Xrecurse_ioapic_edge22)
 	.quad _C_LABEL(Xresume_ioapic_edge22)
 	.quad _C_LABEL(Xintr_ioapic_edge23), _C_LABEL(Xrecurse_ioapic_edge23)
 	.quad _C_LABEL(Xresume_ioapic_edge23)
 	.quad _C_LABEL(Xintr_ioapic_edge24), _C_LABEL(Xrecurse_ioapic_edge24)
 	.quad _C_LABEL(Xresume_ioapic_edge24)
 	.quad _C_LABEL(Xintr_ioapic_edge25), _C_LABEL(Xrecurse_ioapic_edge25)
 	.quad _C_LABEL(Xresume_ioapic_edge25)
 	.quad _C_LABEL(Xintr_ioapic_edge26), _C_LABEL(Xrecurse_ioapic_edge26)
 	.quad _C_LABEL(Xresume_ioapic_edge26)
 	.quad _C_LABEL(Xintr_ioapic_edge27), _C_LABEL(Xrecurse_ioapic_edge27)
 	.quad _C_LABEL(Xresume_ioapic_edge27)
 	.quad _C_LABEL(Xintr_ioapic_edge28), _C_LABEL(Xrecurse_ioapic_edge28)
 	.quad _C_LABEL(Xresume_ioapic_edge28)
 	.quad _C_LABEL(Xintr_ioapic_edge29), _C_LABEL(Xrecurse_ioapic_edge29)
 	.quad _C_LABEL(Xresume_ioapic_edge29)
 	.quad _C_LABEL(Xintr_ioapic_edge30), _C_LABEL(Xrecurse_ioapic_edge30)
 	.quad _C_LABEL(Xresume_ioapic_edge30)
 	.quad _C_LABEL(Xintr_ioapic_edge31), _C_LABEL(Xrecurse_ioapic_edge31)
 	.quad _C_LABEL(Xresume_ioapic_edge31)
 END(ioapic_edge_stubs)
 	.type _C_LABEL(ioapic_level_stubs), @object
 LABEL(ioapic_level_stubs)
 	.quad _C_LABEL(Xintr_ioapic_level0), _C_LABEL(Xrecurse_ioapic_level0)
 	.quad _C_LABEL(Xresume_ioapic_level0)
 	.quad _C_LABEL(Xintr_ioapic_level1), _C_LABEL(Xrecurse_ioapic_level1)
 	.quad _C_LABEL(Xresume_ioapic_level1)
 	.quad _C_LABEL(Xintr_ioapic_level2), _C_LABEL(Xrecurse_ioapic_level2)
 	.quad _C_LABEL(Xresume_ioapic_level2)
 	.quad _C_LABEL(Xintr_ioapic_level3), _C_LABEL(Xrecurse_ioapic_level3)
 	.quad _C_LABEL(Xresume_ioapic_level3)
 	.quad _C_LABEL(Xintr_ioapic_level4), _C_LABEL(Xrecurse_ioapic_level4)
 	.quad _C_LABEL(Xresume_ioapic_level4)
 	.quad _C_LABEL(Xintr_ioapic_level5), _C_LABEL(Xrecurse_ioapic_level5)
 	.quad _C_LABEL(Xresume_ioapic_level5)
 	.quad _C_LABEL(Xintr_ioapic_level6), _C_LABEL(Xrecurse_ioapic_level6)
 	.quad _C_LABEL(Xresume_ioapic_level6)
 	.quad _C_LABEL(Xintr_ioapic_level7), _C_LABEL(Xrecurse_ioapic_level7)
 	.quad _C_LABEL(Xresume_ioapic_level7)
 	.quad _C_LABEL(Xintr_ioapic_level8), _C_LABEL(Xrecurse_ioapic_level8)
 	.quad _C_LABEL(Xresume_ioapic_level8)
 	.quad _C_LABEL(Xintr_ioapic_level9), _C_LABEL(Xrecurse_ioapic_level9)
 	.quad _C_LABEL(Xresume_ioapic_level9)
 	.quad _C_LABEL(Xintr_ioapic_level10), _C_LABEL(Xrecurse_ioapic_level10)
 	.quad _C_LABEL(Xresume_ioapic_level10)
 	.quad _C_LABEL(Xintr_ioapic_level11), _C_LABEL(Xrecurse_ioapic_level11)
 	.quad _C_LABEL(Xresume_ioapic_level11)
 	.quad _C_LABEL(Xintr_ioapic_level12), _C_LABEL(Xrecurse_ioapic_level12)
 	.quad _C_LABEL(Xresume_ioapic_level12)
 	.quad _C_LABEL(Xintr_ioapic_level13), _C_LABEL(Xrecurse_ioapic_level13)
 	.quad _C_LABEL(Xresume_ioapic_level13)
 	.quad _C_LABEL(Xintr_ioapic_level14), _C_LABEL(Xrecurse_ioapic_level14)
 	.quad _C_LABEL(Xresume_ioapic_level14)
 	.quad _C_LABEL(Xintr_ioapic_level15), _C_LABEL(Xrecurse_ioapic_level15)
 	.quad _C_LABEL(Xresume_ioapic_level15)
 	.quad _C_LABEL(Xintr_ioapic_level16), _C_LABEL(Xrecurse_ioapic_level16)
 	.quad _C_LABEL(Xresume_ioapic_level16)
 	.quad _C_LABEL(Xintr_ioapic_level17), _C_LABEL(Xrecurse_ioapic_level17)
 	.quad _C_LABEL(Xresume_ioapic_level17)
 	.quad _C_LABEL(Xintr_ioapic_level18), _C_LABEL(Xrecurse_ioapic_level18)
 	.quad _C_LABEL(Xresume_ioapic_level18)
 	.quad _C_LABEL(Xintr_ioapic_level19), _C_LABEL(Xrecurse_ioapic_level19)
 	.quad _C_LABEL(Xresume_ioapic_level19)
 	.quad _C_LABEL(Xintr_ioapic_level20), _C_LABEL(Xrecurse_ioapic_level20)
 	.quad _C_LABEL(Xresume_ioapic_level20)
 	.quad _C_LABEL(Xintr_ioapic_level21), _C_LABEL(Xrecurse_ioapic_level21)
 	.quad _C_LABEL(Xresume_ioapic_level21)
 	.quad _C_LABEL(Xintr_ioapic_level22), _C_LABEL(Xrecurse_ioapic_level22)
 	.quad _C_LABEL(Xresume_ioapic_level22)
 	.quad _C_LABEL(Xintr_ioapic_level23), _C_LABEL(Xrecurse_ioapic_level23)
 	.quad _C_LABEL(Xresume_ioapic_level23)
 	.quad _C_LABEL(Xintr_ioapic_level24), _C_LABEL(Xrecurse_ioapic_level24)
 	.quad _C_LABEL(Xresume_ioapic_level24)
 	.quad _C_LABEL(Xintr_ioapic_level25), _C_LABEL(Xrecurse_ioapic_level25)
 	.quad _C_LABEL(Xresume_ioapic_level25)
 	.quad _C_LABEL(Xintr_ioapic_level26), _C_LABEL(Xrecurse_ioapic_level26)
 	.quad _C_LABEL(Xresume_ioapic_level26)
 	.quad _C_LABEL(Xintr_ioapic_level27), _C_LABEL(Xrecurse_ioapic_level27)
 	.quad _C_LABEL(Xresume_ioapic_level27)
 	.quad _C_LABEL(Xintr_ioapic_level28), _C_LABEL(Xrecurse_ioapic_level28)
 	.quad _C_LABEL(Xresume_ioapic_level28)
 	.quad _C_LABEL(Xintr_ioapic_level29), _C_LABEL(Xrecurse_ioapic_level29)
 	.quad _C_LABEL(Xresume_ioapic_level29)
 	.quad _C_LABEL(Xintr_ioapic_level30), _C_LABEL(Xrecurse_ioapic_level30)
 	.quad _C_LABEL(Xresume_ioapic_level30)
 	.quad _C_LABEL(Xintr_ioapic_level31), _C_LABEL(Xrecurse_ioapic_level31)
 	.quad _C_LABEL(Xresume_ioapic_level31)
 END(ioapic_level_stubs)
 	.type _C_LABEL(x2apic_edge_stubs), @object
 LABEL(x2apic_edge_stubs)
 	.quad _C_LABEL(Xintr_x2apic_edge0), _C_LABEL(Xrecurse_x2apic_edge0)
 	.quad _C_LABEL(Xresume_x2apic_edge0)
 	.quad _C_LABEL(Xintr_x2apic_edge1), _C_LABEL(Xrecurse_x2apic_edge1)
 	.quad _C_LABEL(Xresume_x2apic_edge1)
 	.quad _C_LABEL(Xintr_x2apic_edge2), _C_LABEL(Xrecurse_x2apic_edge2)
 	.quad _C_LABEL(Xresume_x2apic_edge2)
 	.quad _C_LABEL(Xintr_x2apic_edge3), _C_LABEL(Xrecurse_x2apic_edge3)
 	.quad _C_LABEL(Xresume_x2apic_edge3)
 	.quad _C_LABEL(Xintr_x2apic_edge4), _C_LABEL(Xrecurse_x2apic_edge4)
 	.quad _C_LABEL(Xresume_x2apic_edge4)
 	.quad _C_LABEL(Xintr_x2apic_edge5), _C_LABEL(Xrecurse_x2apic_edge5)
 	.quad _C_LABEL(Xresume_x2apic_edge5)
 	.quad _C_LABEL(Xintr_x2apic_edge6), _C_LABEL(Xrecurse_x2apic_edge6)
 	.quad _C_LABEL(Xresume_x2apic_edge6)
 	.quad _C_LABEL(Xintr_x2apic_edge7), _C_LABEL(Xrecurse_x2apic_edge7)
 	.quad _C_LABEL(Xresume_x2apic_edge7)
 	.quad _C_LABEL(Xintr_x2apic_edge8), _C_LABEL(Xrecurse_x2apic_edge8)
 	.quad _C_LABEL(Xresume_x2apic_edge8)
 	.quad _C_LABEL(Xintr_x2apic_edge9), _C_LABEL(Xrecurse_x2apic_edge9)
 	.quad _C_LABEL(Xresume_x2apic_edge9)
 	.quad _C_LABEL(Xintr_x2apic_edge10), _C_LABEL(Xrecurse_x2apic_edge10)
 	.quad _C_LABEL(Xresume_x2apic_edge10)
 	.quad _C_LABEL(Xintr_x2apic_edge11), _C_LABEL(Xrecurse_x2apic_edge11)
 	.quad _C_LABEL(Xresume_x2apic_edge11)
 	.quad _C_LABEL(Xintr_x2apic_edge12), _C_LABEL(Xrecurse_x2apic_edge12)
 	.quad _C_LABEL(Xresume_x2apic_edge12)
 	.quad _C_LABEL(Xintr_x2apic_edge13), _C_LABEL(Xrecurse_x2apic_edge13)
 	.quad _C_LABEL(Xresume_x2apic_edge13)
 	.quad _C_LABEL(Xintr_x2apic_edge14), _C_LABEL(Xrecurse_x2apic_edge14)
 	.quad _C_LABEL(Xresume_x2apic_edge14)
 	.quad _C_LABEL(Xintr_x2apic_edge15), _C_LABEL(Xrecurse_x2apic_edge15)
 	.quad _C_LABEL(Xresume_x2apic_edge15)
 	.quad _C_LABEL(Xintr_x2apic_edge16), _C_LABEL(Xrecurse_x2apic_edge16)
 	.quad _C_LABEL(Xresume_x2apic_edge16)
 	.quad _C_LABEL(Xintr_x2apic_edge17), _C_LABEL(Xrecurse_x2apic_edge17)
 	.quad _C_LABEL(Xresume_x2apic_edge17)
 	.quad _C_LABEL(Xintr_x2apic_edge18), _C_LABEL(Xrecurse_x2apic_edge18)
 	.quad _C_LABEL(Xresume_x2apic_edge18)
 	.quad _C_LABEL(Xintr_x2apic_edge19), _C_LABEL(Xrecurse_x2apic_edge19)
 	.quad _C_LABEL(Xresume_x2apic_edge19)
 	.quad _C_LABEL(Xintr_x2apic_edge20), _C_LABEL(Xrecurse_x2apic_edge20)
 	.quad _C_LABEL(Xresume_x2apic_edge20)
 	.quad _C_LABEL(Xintr_x2apic_edge21), _C_LABEL(Xrecurse_x2apic_edge21)
 	.quad _C_LABEL(Xresume_x2apic_edge21)
 	.quad _C_LABEL(Xintr_x2apic_edge22), _C_LABEL(Xrecurse_x2apic_edge22)
 	.quad _C_LABEL(Xresume_x2apic_edge22)
 	.quad _C_LABEL(Xintr_x2apic_edge23), _C_LABEL(Xrecurse_x2apic_edge23)
 	.quad _C_LABEL(Xresume_x2apic_edge23)
 	.quad _C_LABEL(Xintr_x2apic_edge24), _C_LABEL(Xrecurse_x2apic_edge24)
 	.quad _C_LABEL(Xresume_x2apic_edge24)
 	.quad _C_LABEL(Xintr_x2apic_edge25), _C_LABEL(Xrecurse_x2apic_edge25)
 	.quad _C_LABEL(Xresume_x2apic_edge25)
 	.quad _C_LABEL(Xintr_x2apic_edge26), _C_LABEL(Xrecurse_x2apic_edge26)
 	.quad _C_LABEL(Xresume_x2apic_edge26)
 	.quad _C_LABEL(Xintr_x2apic_edge27), _C_LABEL(Xrecurse_x2apic_edge27)
 	.quad _C_LABEL(Xresume_x2apic_edge27)
 	.quad _C_LABEL(Xintr_x2apic_edge28), _C_LABEL(Xrecurse_x2apic_edge28)
 	.quad _C_LABEL(Xresume_x2apic_edge28)
 	.quad _C_LABEL(Xintr_x2apic_edge29), _C_LABEL(Xrecurse_x2apic_edge29)
 	.quad _C_LABEL(Xresume_x2apic_edge29)
 	.quad _C_LABEL(Xintr_x2apic_edge30), _C_LABEL(Xrecurse_x2apic_edge30)
 	.quad _C_LABEL(Xresume_x2apic_edge30)
 	.quad _C_LABEL(Xintr_x2apic_edge31), _C_LABEL(Xrecurse_x2apic_edge31)
 	.quad _C_LABEL(Xresume_x2apic_edge31)
 END(x2apic_edge_stubs)
 	.type _C_LABEL(x2apic_level_stubs), @object
 LABEL(x2apic_level_stubs)
 	.quad _C_LABEL(Xintr_x2apic_level0), _C_LABEL(Xrecurse_x2apic_level0)
 	.quad _C_LABEL(Xresume_x2apic_level0)
 	.quad _C_LABEL(Xintr_x2apic_level1), _C_LABEL(Xrecurse_x2apic_level1)
 	.quad _C_LABEL(Xresume_x2apic_level1)
 	.quad _C_LABEL(Xintr_x2apic_level2), _C_LABEL(Xrecurse_x2apic_level2)
 	.quad _C_LABEL(Xresume_x2apic_level2)
 	.quad _C_LABEL(Xintr_x2apic_level3), _C_LABEL(Xrecurse_x2apic_level3)
 	.quad _C_LABEL(Xresume_x2apic_level3)
 	.quad _C_LABEL(Xintr_x2apic_level4), _C_LABEL(Xrecurse_x2apic_level4)
 	.quad _C_LABEL(Xresume_x2apic_level4)
 	.quad _C_LABEL(Xintr_x2apic_level5), _C_LABEL(Xrecurse_x2apic_level5)
 	.quad _C_LABEL(Xresume_x2apic_level5)
 	.quad _C_LABEL(Xintr_x2apic_level6), _C_LABEL(Xrecurse_x2apic_level6)
 	.quad _C_LABEL(Xresume_x2apic_level6)
 	.quad _C_LABEL(Xintr_x2apic_level7), _C_LABEL(Xrecurse_x2apic_level7)
 	.quad _C_LABEL(Xresume_x2apic_level7)
 	.quad _C_LABEL(Xintr_x2apic_level8), _C_LABEL(Xrecurse_x2apic_level8)
 	.quad _C_LABEL(Xresume_x2apic_level8)
 	.quad _C_LABEL(Xintr_x2apic_level9), _C_LABEL(Xrecurse_x2apic_level9)
 	.quad _C_LABEL(Xresume_x2apic_level9)
 	.quad _C_LABEL(Xintr_x2apic_level10), _C_LABEL(Xrecurse_x2apic_level10)
 	.quad _C_LABEL(Xresume_x2apic_level10)
 	.quad _C_LABEL(Xintr_x2apic_level11), _C_LABEL(Xrecurse_x2apic_level11)
 	.quad _C_LABEL(Xresume_x2apic_level11)
 	.quad _C_LABEL(Xintr_x2apic_level12), _C_LABEL(Xrecurse_x2apic_level12)
 	.quad _C_LABEL(Xresume_x2apic_level12)
 	.quad _C_LABEL(Xintr_x2apic_level13), _C_LABEL(Xrecurse_x2apic_level13)
 	.quad _C_LABEL(Xresume_x2apic_level13)
 	.quad _C_LABEL(Xintr_x2apic_level14), _C_LABEL(Xrecurse_x2apic_level14)
 	.quad _C_LABEL(Xresume_x2apic_level14)
 	.quad _C_LABEL(Xintr_x2apic_level15), _C_LABEL(Xrecurse_x2apic_level15)
 	.quad _C_LABEL(Xresume_x2apic_level15)
 	.quad _C_LABEL(Xintr_x2apic_level16), _C_LABEL(Xrecurse_x2apic_level16)
 	.quad _C_LABEL(Xresume_x2apic_level16)
 	.quad _C_LABEL(Xintr_x2apic_level17), _C_LABEL(Xrecurse_x2apic_level17)
 	.quad _C_LABEL(Xresume_x2apic_level17)
 	.quad _C_LABEL(Xintr_x2apic_level18), _C_LABEL(Xrecurse_x2apic_level18)
 	.quad _C_LABEL(Xresume_x2apic_level18)
 	.quad _C_LABEL(Xintr_x2apic_level19), _C_LABEL(Xrecurse_x2apic_level19)
 	.quad _C_LABEL(Xresume_x2apic_level19)
 	.quad _C_LABEL(Xintr_x2apic_level20), _C_LABEL(Xrecurse_x2apic_level20)
 	.quad _C_LABEL(Xresume_x2apic_level20)
 	.quad _C_LABEL(Xintr_x2apic_level21), _C_LABEL(Xrecurse_x2apic_level21)
 	.quad _C_LABEL(Xresume_x2apic_level21)
 	.quad _C_LABEL(Xintr_x2apic_level22), _C_LABEL(Xrecurse_x2apic_level22)
 	.quad _C_LABEL(Xresume_x2apic_level22)
 	.quad _C_LABEL(Xintr_x2apic_level23), _C_LABEL(Xrecurse_x2apic_level23)
 	.quad _C_LABEL(Xresume_x2apic_level23)
 	.quad _C_LABEL(Xintr_x2apic_level24), _C_LABEL(Xrecurse_x2apic_level24)
 	.quad _C_LABEL(Xresume_x2apic_level24)
 	.quad _C_LABEL(Xintr_x2apic_level25), _C_LABEL(Xrecurse_x2apic_level25)
 	.quad _C_LABEL(Xresume_x2apic_level25)
 	.quad _C_LABEL(Xintr_x2apic_level26), _C_LABEL(Xrecurse_x2apic_level26)
 	.quad _C_LABEL(Xresume_x2apic_level26)
 	.quad _C_LABEL(Xintr_x2apic_level27), _C_LABEL(Xrecurse_x2apic_level27)
 	.quad _C_LABEL(Xresume_x2apic_level27)
 	.quad _C_LABEL(Xintr_x2apic_level28), _C_LABEL(Xrecurse_x2apic_level28)
 	.quad _C_LABEL(Xresume_x2apic_level28)
 	.quad _C_LABEL(Xintr_x2apic_level29), _C_LABEL(Xrecurse_x2apic_level29)
 	.quad _C_LABEL(Xresume_x2apic_level29)
 	.quad _C_LABEL(Xintr_x2apic_level30), _C_LABEL(Xrecurse_x2apic_level30)
 	.quad _C_LABEL(Xresume_x2apic_level30)
 	.quad _C_LABEL(Xintr_x2apic_level31), _C_LABEL(Xrecurse_x2apic_level31)
 	.quad _C_LABEL(Xresume_x2apic_level31)
 END(x2apic_level_stubs)
 #endif
 #endif /* !defined(XEN) */
 #if defined(XEN)
 /* Resume/recurse procedures for spl() */
 #define	XENINTRSTUB(name, num, early_ack, late_ack, mask, unmask, level_mask) \
 IDTVEC(recurse_ ## name ## num)						;\
 	INTR_RECURSE_HWFRAME						;\
 	subq	$8,%rsp							;\
 	pushq	$T_ASTFLT		/* trap # for doing ASTs */	;\
 	INTRENTRY							;\
 IDTVEC(resume_ ## name ## num)						\
 	movq	$IREENT_MAGIC,TF_ERR(%rsp)				;\
 	movl	%ebx,%r13d						;\
 	movq	CPUVAR(ISOURCES) + (num) * 8,%r14			;\
 :									\
 	pushq	%r13							;\
 	movl	$num,CPUVAR(ILEVEL)					;\
 	STI(si)								;\
 	incl	CPUVAR(IDEPTH)						;\
 	movq	IS_HANDLERS(%r14),%rbx					;\
 :									\
 	movq	IH_ARG(%rbx),%rdi					;\
 	movq	%rsp,%rsi						;\
 	call	*IH_FUN(%rbx)		/* call it */			;\
 	movq	IH_NEXT(%rbx),%rbx	/* next handler in chain */	;\
 	testq	%rbx,%rbx						;\
 	jnz	6b							;\
 :									\
 	CLI(si)								;\
 	unmask(num)			/* unmask it in hardware */	;\
 	late_ack(num)							;\
 	STI(si)								;\
 	jmp	_C_LABEL(Xdoreti)	/* lower spl and do ASTs */	;\
 /* The unmask func for Xen events */
 #define hypervisor_asm_unmask(num)			\
 	movq	$num,%rdi				;\
 	call	_C_LABEL(hypervisor_enable_ipl)
 XENINTRSTUB(xenev,0,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,1,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,2,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,3,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,4,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,5,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,6,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,7,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,8,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,9,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,10,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,11,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,12,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,13,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,14,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,15,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,16,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,17,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,18,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,19,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,20,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,21,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,22,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,23,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,24,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,25,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,26,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,27,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,28,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,29,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,30,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 XENINTRSTUB(xenev,31,voidop,voidop,voidop,hypervisor_asm_unmask,voidop)
 LABEL(xenev_stubs)
 	.quad _C_LABEL(Xrecurse_xenev0), _C_LABEL(Xresume_xenev0)
 	.quad _C_LABEL(Xrecurse_xenev1) ,_C_LABEL(Xresume_xenev1)
 	.quad _C_LABEL(Xrecurse_xenev2) ,_C_LABEL(Xresume_xenev2)
 	.quad _C_LABEL(Xrecurse_xenev3) ,_C_LABEL(Xresume_xenev3)
 	.quad _C_LABEL(Xrecurse_xenev4) ,_C_LABEL(Xresume_xenev4)
 	.quad _C_LABEL(Xrecurse_xenev5) ,_C_LABEL(Xresume_xenev5)
 	.quad _C_LABEL(Xrecurse_xenev6) ,_C_LABEL(Xresume_xenev6)
 	.quad _C_LABEL(Xrecurse_xenev7) ,_C_LABEL(Xresume_xenev7)
 	.quad _C_LABEL(Xrecurse_xenev8) ,_C_LABEL(Xresume_xenev8)
 	.quad _C_LABEL(Xrecurse_xenev9) ,_C_LABEL(Xresume_xenev9)
 	.quad _C_LABEL(Xrecurse_xenev10), _C_LABEL(Xresume_xenev10)
 	.quad _C_LABEL(Xrecurse_xenev11), _C_LABEL(Xresume_xenev11)
 	.quad _C_LABEL(Xrecurse_xenev12), _C_LABEL(Xresume_xenev12)
 	.quad _C_LABEL(Xrecurse_xenev13), _C_LABEL(Xresume_xenev13)
 	.quad _C_LABEL(Xrecurse_xenev14), _C_LABEL(Xresume_xenev14)
 	.quad _C_LABEL(Xrecurse_xenev15), _C_LABEL(Xresume_xenev15)
 	.quad _C_LABEL(Xrecurse_xenev16), _C_LABEL(Xresume_xenev16)
 	.quad _C_LABEL(Xrecurse_xenev17), _C_LABEL(Xresume_xenev17)
 	.quad _C_LABEL(Xrecurse_xenev18), _C_LABEL(Xresume_xenev18)
 	.quad _C_LABEL(Xrecurse_xenev19), _C_LABEL(Xresume_xenev19)
 	.quad _C_LABEL(Xrecurse_xenev20), _C_LABEL(Xresume_xenev20)
 	.quad _C_LABEL(Xrecurse_xenev21), _C_LABEL(Xresume_xenev21)
 	.quad _C_LABEL(Xrecurse_xenev22), _C_LABEL(Xresume_xenev22)
 	.quad _C_LABEL(Xrecurse_xenev23), _C_LABEL(Xresume_xenev23)
 	.quad _C_LABEL(Xrecurse_xenev24), _C_LABEL(Xresume_xenev24)
 	.quad _C_LABEL(Xrecurse_xenev25), _C_LABEL(Xresume_xenev25)
 	.quad _C_LABEL(Xrecurse_xenev26), _C_LABEL(Xresume_xenev26)
 	.quad _C_LABEL(Xrecurse_xenev27), _C_LABEL(Xresume_xenev27)
 	.quad _C_LABEL(Xrecurse_xenev28), _C_LABEL(Xresume_xenev28)
 	.quad _C_LABEL(Xrecurse_xenev29), _C_LABEL(Xresume_xenev29)
 	.quad _C_LABEL(Xrecurse_xenev30), _C_LABEL(Xresume_xenev30)
 	.quad _C_LABEL(Xrecurse_xenev31), _C_LABEL(Xresume_xenev31)
 END(xenev_stubs)
 /*
  * Xen callbacks
  */
 /* Hypervisor callback */
 NENTRY(hypervisor_callback)
 	movq	(%rsp),%rcx
 	movq	8(%rsp),%r11
 	addq	$16,%rsp
 	pushq	$0		/* Dummy error code */
 	pushq	$T_ASTFLT
 	INTRENTRY
 	/* sti?? */
 	movq	%rsp,%rdi
 	subq	$8,%rdi;	/* don't forget if_ppl */
 	call	do_hypervisor_callback
 	testb	$SEL_RPL,TF_CS(%rsp)
 	jnz	doreti_checkast
 :
 	INTRFASTEXIT
 END(hypervisor_callback)
 /* Panic? */
 NENTRY(failsafe_callback)
 	movq	(%rsp),%rcx
 	movq	8(%rsp),%r11
 	addq	$16,%rsp
 	pushq	$0
 	pushq	$T_ASTFLT
 	INTRENTRY
 	movq	%rsp,%rdi
 	subq	$8,%rdi;	/* don't forget if_ppl */
 	call	xen_failsafe_handler
 	INTRFASTEXIT
 /*	jmp	HYPERVISOR_iret */
 END(failsafe_callback)
 #endif	/* !XEN */

 @@ -1,937 +1,937 @@
-/*	$NetBSD: lapic.c,v 1.61 2017/08/11 06:18:29 maxv Exp $	*/
+/*	$NetBSD: lapic.c,v 1.62 2017/08/15 09:08:39 maxv Exp $	*/
 /*-
  * Copyright (c) 2000, 2008 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by RedBack Networks Inc.
+ *
  * Author: Bill Sommerfeld
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: lapic.c,v 1.61 2017/08/11 06:18:29 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: lapic.c,v 1.62 2017/08/15 09:08:39 maxv Exp $");
 #include "acpica.h"
 #include "ioapic.h"
 #include "opt_acpi.h"
 #include "opt_ddb.h"
 #include "opt_mpbios.h"		/* for MPDEBUG */
 #include "opt_multiprocessor.h"
 #include "opt_ntp.h"
 #include <sys/param.h>
 #include <sys/proc.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <sys/timetc.h>
 #include <uvm/uvm_extern.h>
 #include <dev/ic/i8253reg.h>
 #include <machine/cpu.h>
 #include <machine/cpu_counter.h>
 #include <machine/cpufunc.h>
 #include <machine/cpuvar.h>
 #include <machine/pmap.h>
 #include <machine/vmparam.h>
 #include <machine/mpacpi.h>
 #include <machine/mpbiosvar.h>
 #include <machine/pcb.h>
 #include <machine/specialreg.h>
 #include <machine/segments.h>
 #include <x86/x86/tsc.h>
 #include <x86/i82093var.h>
 #include <machine/apicvar.h>
 #include <machine/i82489reg.h>
 #include <machine/i82489var.h>
 #if NACPICA > 0
 #include <dev/acpi/acpica.h>
 #include <dev/acpi/acpivar.h>
 #endif
 #ifdef DDB
 #include <machine/db_machdep.h>
 #ifdef MULTIPROCESSOR
 #ifdef __x86_64__
 typedef void (vector)(void);
-extern vector Xx2apic_intrddb;
+extern vector Xx2apic_intrddbipi;
 extern int ddb_vec;
 #endif
 #endif
 #endif
 #include <x86/x86/vmtreg.h>	/* for vmt_hvcall() */
 #include <x86/x86/vmtvar.h>	/* for vmt_hvcall() */
 /* Referenced from vector.S */
 void		lapic_clockintr(void *, struct intrframe *);
 static void	lapic_delay(unsigned int);
 static uint32_t lapic_gettick(void);
 static void 	lapic_setup_bsp(paddr_t);
 static void 	lapic_map(paddr_t);
 static void lapic_hwmask(struct pic *, int);
 static void lapic_hwunmask(struct pic *, int);
 static void lapic_setup(struct pic *, struct cpu_info *, int, int, int);
 /* Make it public to call via ddb */
 void	lapic_dump(void);
 struct pic local_pic = {
 	.pic_name = "lapic",
 	.pic_type = PIC_LAPIC,
 	.pic_lock = __SIMPLELOCK_UNLOCKED,
 	.pic_hwmask = lapic_hwmask,
 	.pic_hwunmask = lapic_hwunmask,
 	.pic_addroute = lapic_setup,
 	.pic_delroute = lapic_setup,
 };
 static int i82489_ipi(int vec, int target, int dl);
 static int x2apic_ipi(int vec, int target, int dl);
 int (*x86_ipi)(int, int, int) = i82489_ipi;
 bool x2apic_mode __read_mostly;
 #ifdef LAPIC_ENABLE_X2APIC
 bool x2apic_enable = true;
 #else
 bool x2apic_enable = false;
 #endif
 static uint32_t
 i82489_readreg(u_int reg)
+{
 	return *((volatile uint32_t *)(local_apic_va + reg));
+}
 static void
 i82489_writereg(u_int reg, uint32_t val)
+{
 	*((volatile uint32_t *)(local_apic_va + reg)) = val;
+}
 static uint32_t
 i82489_cpu_number(void)
+{
 	return i82489_readreg(LAPIC_ID) >> LAPIC_ID_SHIFT;
+}
 static uint32_t
 x2apic_readreg(u_int reg)
+{
 	return rdmsr(MSR_X2APIC_BASE + (reg >> 4));
+}
 static void
 x2apic_writereg(u_int reg, uint32_t val)
+{
 	x86_mfence();
 	wrmsr(MSR_X2APIC_BASE + (reg >> 4), val);
+}
 static void
 x2apic_writereg64(u_int reg, uint64_t val)
+{
 	KDASSERT(reg == LAPIC_ICRLO);
 	x86_mfence();
 	wrmsr(MSR_X2APIC_BASE + (reg >> 4), val);
+}
 static void
 x2apic_write_icr(uint32_t hi, uint32_t lo)
+{
 	x2apic_writereg64(LAPIC_ICRLO, ((uint64_t)hi << 32) | lo);
+}
 static uint32_t
 x2apic_cpu_number(void)
+{
 	return x2apic_readreg(LAPIC_ID);
+}
 uint32_t
 lapic_readreg(u_int reg)
+{
 	if (x2apic_mode)
 		return x2apic_readreg(reg);
 	return i82489_readreg(reg);
+}
 void
 lapic_writereg(u_int reg, uint32_t val)
+{
 	if (x2apic_mode)
 		x2apic_writereg(reg, val);
 	else
 		i82489_writereg(reg, val);
+}
 void
 lapic_write_tpri(uint32_t val)
+{
 	val &= LAPIC_TPRI_MASK;
 #ifdef i386
 	lapic_writereg(LAPIC_TPRI, val);
 #else
 	lcr8(val >> 4);
 #endif
+}
 void
 lapic_eoi(void)
+{
 	lapic_writereg(LAPIC_EOI, 0);
+}
 uint32_t
 lapic_cpu_number(void)
+{
 	if (x2apic_mode)
 		return x2apic_cpu_number();
 	return i82489_cpu_number();
+}
 static void
 lapic_enable_x2apic(void)
+{
 	uint64_t apicbase;
 	apicbase = rdmsr(MSR_APICBASE);
 	if (!ISSET(apicbase, APICBASE_EN)) {
 		apicbase |= APICBASE_EN;
 		wrmsr(MSR_APICBASE, apicbase);
+	}
 	apicbase |= APICBASE_EXTD;
 	wrmsr(MSR_APICBASE, apicbase);
+}
 bool
 lapic_is_x2apic(void)
+{
 	uint64_t msr;
 	if (!ISSET(cpu_feature[0], CPUID_APIC) ||
 	    rdmsr_safe(MSR_APICBASE, &msr) == EFAULT)
 		return false;
 	return (msr & (APICBASE_EN | APICBASE_EXTD)) ==
 	    (APICBASE_EN | APICBASE_EXTD);
+}
 /*
  * Initialize the local APIC on the BSP.
  */
 static void
 lapic_setup_bsp(paddr_t lapic_base)
+{
 	u_int regs[4];
 	const char *reason = NULL;
 	const char *hw_vendor;
 	bool bios_x2apic;
 	if (ISSET(cpu_feature[1], CPUID2_X2APIC)) {
 #if NACPICA > 0
 		if (acpi_present) {
 			ACPI_TABLE_DMAR *dmar;
 			ACPI_STATUS status;
 			/*
 			 * Automatically detect several configurations where
 			 * x2APIC mode is known to cause troubles.  User can
 			 * override the setting with hw.x2apic_enable tunable.
 			 */
 			status = AcpiGetTable(ACPI_SIG_DMAR, 1,
 			    (ACPI_TABLE_HEADER **)&dmar);
 			if (ACPI_SUCCESS(status)) {
 				if (ISSET(dmar->Flags, ACPI_DMAR_X2APIC_OPT_OUT)) {
 					reason = "by DMAR table";
+				}
 				AcpiPutTable(&dmar->Header);
+			}
+		}
 #endif	/* NACPICA > 0 */
 		if (vm_guest == VM_GUEST_VMWARE) {
 			vmt_hvcall(VM_CMD_GET_VCPU_INFO, regs);
 			if (ISSET(regs[0], VCPUINFO_VCPU_RESERVED) ||
 			    !ISSET(regs[0], VCPUINFO_LEGACY_X2APIC))
 				reason = "inside VMWare without intr redirection";
 		} else if (vm_guest == VM_GUEST_XEN) {
 			reason = "due to running under XEN";
 		} else if (vm_guest == VM_GUEST_NO &&
 		    CPUID_TO_FAMILY(curcpu()->ci_signature) == 6 &&
 		    CPUID_TO_MODEL(curcpu()->ci_signature) == 0x2a) {
 			hw_vendor = pmf_get_platform("board-vendor");
 			if (hw_vendor != NULL) {
 				/*
 				 * It seems that some Lenovo and ASUS
 				 * SandyBridge-based notebook BIOSes have a bug
 				 * which prevents booting AP in x2APIC mode.
 				 * Since the only way to detect mobile CPU is
 				 * to check northbridge pci id, which cannot be done
 				 * that early, disable x2APIC for all Lenovo and ASUS
 				 * SandyBridge machines.
 				 */
 				if (strcmp(hw_vendor, "LENOVO") == 0 ||
 				    strcmp(hw_vendor, "ASUSTeK Computer Inc.") == 0) {
 					reason =
 					    "for a suspected SandyBridge BIOS bug";
+				}
+			}
+		}
 		bios_x2apic = lapic_is_x2apic();
 		if (reason != NULL && bios_x2apic) {
 			aprint_verbose("x2APIC should be disabled %s but "
 			    "already enabled by BIOS; enabling.\n", reason);
 			reason = NULL;
+		}
 		if (reason == NULL)
 			x2apic_mode = true;
 		else
 			aprint_verbose("x2APIC available but disabled %s\n", reason);
 		if (x2apic_enable != x2apic_mode) {
 			if (bios_x2apic && !x2apic_enable)
 				aprint_verbose("x2APIC disabled by user and "
 				    "enabled by BIOS; ignoring user setting.\n");
 			else
 				x2apic_mode = x2apic_enable;
+		}
+	}
 	if (x2apic_mode) {
 		x86_ipi = x2apic_ipi;
 #if NIOAPIC > 0
 		struct ioapic_softc *ioapic;
 		for (ioapic = ioapics; ioapic != NULL; ioapic = ioapic->sc_next) {
 			ioapic->sc_pic.pic_edge_stubs = x2apic_edge_stubs;
 			ioapic->sc_pic.pic_level_stubs = x2apic_level_stubs;
+		}
 #endif
 #if defined(DDB) && defined(MULTIPROCESSOR)
 #ifdef __x86_64__
-		setgate(&idt[ddb_vec], &Xx2apic_intrddb, 1, SDT_SYS386IGT, SEL_KPL,
+		setgate(&idt[ddb_vec], &Xx2apic_intrddbipi, 1, SDT_SYS386IGT,
-		    GSEL(GCODE_SEL, SEL_KPL));
+		    SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
 #else
 		/* Set DDB IPI handler in cpu_set_tss_gates() when cpu0 is attached. */
 #endif
 #endif
 		x86_disable_intr();
 		lapic_enable_x2apic();
 #ifdef MULTIPROCESSOR
 		cpu_init_first();	/* catch up to changed cpu_number() */
 #endif
 		lapic_write_tpri(0);
 		x86_enable_intr();
 	} else
 		lapic_map(lapic_base);
+}
 static void
 lapic_map(paddr_t lapic_base)
+{
 	pt_entry_t *pte;
 	vaddr_t va = local_apic_va;
 	/*
 	 * If the CPU has an APIC MSR, use it and ignore the supplied value:
 	 * some ACPI implementations have been observed to pass bad values.
 	 * Additionally, ensure that the lapic is enabled as we are committed
 	 * to using it at this point.  Be conservative and assume that the MSR
 	 * is not present on the Pentium (is it?).
 	 */
 	if (CPUID_TO_FAMILY(curcpu()->ci_signature) >= 6) {
 		lapic_base = (paddr_t)rdmsr(MSR_APICBASE);
 		if ((lapic_base & APICBASE_PHYSADDR) == 0) {
 			lapic_base |= LAPIC_BASE;
+		}
 		wrmsr(MSR_APICBASE, lapic_base | APICBASE_EN);
 		lapic_base &= APICBASE_PHYSADDR;
+	}
 	x86_disable_intr();
 	/*
 	 * Map local apic.  If we have a local apic, it's safe to assume
 	 * we're on a 486 or better and can use invlpg and non-cacheable PTE's
+	 *
 	 * Whap the PTE "by hand" rather than calling pmap_kenter_pa because
 	 * the latter will attempt to invoke TLB shootdown code just as we
 	 * might have changed the value of cpu_number()..
 	 */
 	pte = kvtopte(va);
 	*pte = lapic_base | PG_RW | PG_V | PG_N | pmap_pg_g | pmap_pg_nx;
 	invlpg(va);
 #ifdef MULTIPROCESSOR
 	cpu_init_first();	/* catch up to changed cpu_number() */
 #endif
 	lapic_write_tpri(0);
 	x86_enable_intr();
+}
 /*
  * enable local apic
  */
 void
 lapic_enable(void)
+{
 	lapic_writereg(LAPIC_SVR, LAPIC_SVR_ENABLE | LAPIC_SPURIOUS_VECTOR);
+}
 void
 lapic_set_lvt(void)
+{
 	struct cpu_info *ci = curcpu();
 	int i;
 	struct mp_intr_map *mpi;
 	uint32_t lint0, lint1;
 #ifdef MULTIPROCESSOR
 	if (mp_verbose) {
 		apic_format_redir(device_xname(ci->ci_dev), "prelint", 0, 0,
 		    lapic_readreg(LAPIC_LVINT0));
 		apic_format_redir(device_xname(ci->ci_dev), "prelint", 1, 0,
 		    lapic_readreg(LAPIC_LVINT1));
+	}
 #endif
 	/*
 	 * If an I/O APIC has been attached, assume that it is used instead of
 	 * the 8259A for interrupt delivery.  Otherwise request the LAPIC to
 	 * get external interrupts via LINT0 for the primary CPU.
 	 */
 	lint0 = LAPIC_LVT_DM_EXTINT;
 	if (nioapics > 0 || !CPU_IS_PRIMARY(curcpu()))
 		lint0 |= LAPIC_LVT_MASKED;
 	lapic_writereg(LAPIC_LVINT0, lint0);
 	/*
 	 * Non Maskable Interrupts are to be delivered to the primary CPU.
 	 */
 	lint1 = LAPIC_LVT_DM_NMI;
 	if (!CPU_IS_PRIMARY(curcpu()))
 		lint1 |= LAPIC_LVT_MASKED;
 	lapic_writereg(LAPIC_LVINT1, lint1);
 	for (i = 0; i < mp_nintr; i++) {
 		mpi = &mp_intrs[i];
 		if (mpi->ioapic == NULL && (mpi->cpu_id == MPS_ALL_APICS ||
 		    mpi->cpu_id == ci->ci_cpuid)) {
 			if (mpi->ioapic_pin > 1)
 				aprint_error_dev(ci->ci_dev,
 				    "%s: WARNING: bad pin value %d\n",
 				    __func__, mpi->ioapic_pin);
 			if (mpi->ioapic_pin == 0)
 				lapic_writereg(LAPIC_LVINT0, mpi->redir);
 			else
 				lapic_writereg(LAPIC_LVINT1, mpi->redir);
+		}
+	}
 #ifdef MULTIPROCESSOR
 	if (mp_verbose)
 		lapic_dump();
 #endif
+}
 /*
  * Initialize fixed idt vectors for use by local apic.
  */
 void
 lapic_boot_init(paddr_t lapic_base)
+{
 	lapic_setup_bsp(lapic_base);
 #ifdef MULTIPROCESSOR
 	idt_vec_reserve(LAPIC_IPI_VECTOR);
 	idt_vec_set(LAPIC_IPI_VECTOR, x2apic_mode ? Xintr_x2apic_ipi : Xintr_lapic_ipi);
 	idt_vec_reserve(LAPIC_TLB_VECTOR);
 	idt_vec_set(LAPIC_TLB_VECTOR, x2apic_mode ? Xintr_x2apic_tlb : Xintr_lapic_tlb);
 #endif
 	idt_vec_reserve(LAPIC_SPURIOUS_VECTOR);
 	idt_vec_set(LAPIC_SPURIOUS_VECTOR, Xintrspurious);
 	idt_vec_reserve(LAPIC_TIMER_VECTOR);
 	idt_vec_set(LAPIC_TIMER_VECTOR, x2apic_mode ? Xintr_x2apic_ltimer :
 	    Xintr_lapic_ltimer);
+}
 static uint32_t
 lapic_gettick(void)
+{
 	return lapic_readreg(LAPIC_CCR_TIMER);
+}
 #include <sys/kernel.h>		/* for hz */
 int lapic_timer = 0;
 uint32_t lapic_tval;
 /*
  * this gets us up to a 4GHz busclock....
  */
 uint32_t lapic_per_second;
 uint32_t lapic_frac_usec_per_cycle;
 uint64_t lapic_frac_cycle_per_usec;
 uint32_t lapic_delaytab[26];
 static u_int
 lapic_get_timecount(struct timecounter *tc)
+{
 	struct cpu_info *ci;
 	uint32_t cur_timer;
 	int s;
 	s = splhigh();
 	ci = curcpu();
 	/*
 	 * Check for a race against the clockinterrupt.
 	 * The update of ci_lapic_counter is blocked by splhigh() and
 	 * the check for a pending clockinterrupt compensates for that.
+	 *
 	 * If the current tick is almost the Initial Counter, explicitly
 	 * check for the pending interrupt bit as the interrupt delivery
 	 * could be asynchronious and compensate as well.
+	 *
 	 * This can't be done without splhigh() as the calling code might
 	 * have masked the clockinterrupt already.
+	 *
 	 * This code assumes that clockinterrupts are not missed.
 	 */
 	cur_timer = lapic_gettick();
 	if (cur_timer >= lapic_tval - 1) {
 		uint16_t reg = LAPIC_IRR + LAPIC_TIMER_VECTOR / 32 * 16;
 		if (lapic_readreg(reg) & (1 << (LAPIC_TIMER_VECTOR % 32))) {
 			cur_timer -= lapic_tval;
+		}
 	} else if (ci->ci_istate.ipending & (1 << LIR_TIMER))
 		cur_timer = lapic_gettick() - lapic_tval;
 	cur_timer = ci->ci_lapic_counter - cur_timer;
 	splx(s);
 	return cur_timer;
+}
 static struct timecounter lapic_timecounter = {
 	lapic_get_timecount,
 	NULL,
 	~0u,
 ,
 	"lapic",
 #ifndef MULTIPROCESSOR
 ,
 #else
 	-100, /* per CPU state */
 #endif
 	NULL,
 	NULL,
 };
 extern u_int i8254_get_timecount(struct timecounter *);
 void
 lapic_clockintr(void *arg, struct intrframe *frame)
+{
 	struct cpu_info *ci = curcpu();
 	ci->ci_lapic_counter += lapic_tval;
 	ci->ci_isources[LIR_TIMER]->is_evcnt.ev_count++;
 	hardclock((struct clockframe *)frame);
+}
 void
 lapic_initclocks(void)
+{
 	/*
 	 * Start local apic countdown timer running, in repeated mode.
+	 *
 	 * Mask the clock interrupt and set mode,
 	 * then set divisor,
 	 * then unmask and set the vector.
 	 */
 	lapic_writereg(LAPIC_LVTT, LAPIC_LVTT_TM | LAPIC_LVTT_M);
 	lapic_writereg(LAPIC_DCR_TIMER, LAPIC_DCRT_DIV1);
 	lapic_writereg(LAPIC_ICR_TIMER, lapic_tval);
 	lapic_writereg(LAPIC_LVTT, LAPIC_LVTT_TM | LAPIC_TIMER_VECTOR);
 	lapic_eoi();
+}
 extern unsigned int gettick(void);	/* XXX put in header file */
 extern u_long rtclock_tval; /* XXX put in header file */
 extern void (*initclock_func)(void); /* XXX put in header file */
 /*
  * Calibrate the local apic count-down timer (which is running at
  * bus-clock speed) vs. the i8254 counter/timer (which is running at
  * a fixed rate).
+ *
  * The Intel MP spec says: "An MP operating system may use the IRQ8
  * real-time clock as a reference to determine the actual APIC timer clock
  * speed."
+ *
  * We're actually using the IRQ0 timer.  Hmm.
  */
 void
 lapic_calibrate_timer(struct cpu_info *ci)
+{
 	unsigned int seen, delta, initial_i8254, initial_lapic;
 	unsigned int cur_i8254, cur_lapic;
 	uint64_t tmp;
 	int i;
 	char tbuf[9];
 	aprint_debug_dev(ci->ci_dev, "calibrating local timer\n");
 	/*
 	 * Configure timer to one-shot, interrupt masked,
 	 * large positive number.
 	 */
 	lapic_writereg(LAPIC_LVTT, LAPIC_LVTT_M);
 	lapic_writereg(LAPIC_DCR_TIMER, LAPIC_DCRT_DIV1);
 	lapic_writereg(LAPIC_ICR_TIMER, 0x80000000);
 	x86_disable_intr();
 	initial_lapic = lapic_gettick();
 	initial_i8254 = gettick();
 	for (seen = 0; seen < TIMER_FREQ / 100; seen += delta) {
 		cur_i8254 = gettick();
 		if (cur_i8254 > initial_i8254)
 			delta = rtclock_tval - (cur_i8254 - initial_i8254);
 		else
 			delta = initial_i8254 - cur_i8254;
 		initial_i8254 = cur_i8254;
+	}
 	cur_lapic = lapic_gettick();
 	x86_enable_intr();
 	tmp = initial_lapic - cur_lapic;
 	lapic_per_second = (tmp * TIMER_FREQ + seen / 2) / seen;
 	humanize_number(tbuf, sizeof(tbuf), lapic_per_second, "Hz", 1000);
 	aprint_debug_dev(ci->ci_dev, "apic clock running at %s\n", tbuf);
 	if (lapic_per_second != 0) {
 		/*
 		 * reprogram the apic timer to run in periodic mode.
 		 * XXX need to program timer on other CPUs, too.
 		 */
 		lapic_tval = (lapic_per_second * 2) / hz;
 		lapic_tval = (lapic_tval / 2) + (lapic_tval & 0x1);
 		lapic_writereg(LAPIC_LVTT, LAPIC_LVTT_TM | LAPIC_LVTT_M
 		    | LAPIC_TIMER_VECTOR);
 		lapic_writereg(LAPIC_DCR_TIMER, LAPIC_DCRT_DIV1);
 		lapic_writereg(LAPIC_ICR_TIMER, lapic_tval);
 		/*
 		 * Compute fixed-point ratios between cycles and
 		 * microseconds to avoid having to do any division
 		 * in lapic_delay.
 		 */
 		tmp = (1000000 * (uint64_t)1 << 32) / lapic_per_second;
 		lapic_frac_usec_per_cycle = tmp;
 		tmp = (lapic_per_second * (uint64_t)1 << 32) / 1000000;
 		lapic_frac_cycle_per_usec = tmp;
 		/*
 		 * Compute delay in cycles for likely short delays in usec.
 		 */
 		for (i = 0; i < 26; i++)
 			lapic_delaytab[i] = (lapic_frac_cycle_per_usec * i) >>
 ;
 		/*
 		 * Now that the timer's calibrated, use the apic timer routines
 		 * for all our timing needs..
 		 */
 		delay_func = lapic_delay;
 		initclock_func = lapic_initclocks;
 		initrtclock(0);
 		if (lapic_timecounter.tc_frequency == 0) {
 			/*
 			 * Hook up time counter.
 			 * This assume that all LAPICs have the same frequency.
 			 */
 			lapic_timecounter.tc_frequency = lapic_per_second;
 			tc_init(&lapic_timecounter);
+		}
+	}
+}
 /*
  * delay for N usec.
  */
 static void
 lapic_delay(unsigned int usec)
+{
 	int32_t xtick, otick;
 	int64_t deltat;		/* XXX may want to be 64bit */
 	otick = lapic_gettick();
 	if (usec <= 0)
 		return;
 	if (usec <= 25)
 		deltat = lapic_delaytab[usec];
 	else
 		deltat = (lapic_frac_cycle_per_usec * usec) >> 32;
 	while (deltat > 0) {
 		xtick = lapic_gettick();
 		if (xtick > otick)
 			deltat -= lapic_tval - (xtick - otick);
 		else
 			deltat -= otick - xtick;
 		otick = xtick;
 		x86_pause();
+	}
+}
 /*
  * XXX the following belong mostly or partly elsewhere..
  */
 static void
 i82489_icr_wait(void)
+{
 #ifdef DIAGNOSTIC
 	unsigned j = 100000;
 #endif /* DIAGNOSTIC */
 	while ((i82489_readreg(LAPIC_ICRLO) & LAPIC_DLSTAT_BUSY) != 0) {
 		x86_pause();
 #ifdef DIAGNOSTIC
 		j--;
 		if (j == 0)
 			panic("i82489_icr_wait: busy");
 #endif /* DIAGNOSTIC */
+	}
+}
 static int
 i82489_ipi_init(int target)
+{
 	uint32_t esr;
 	i82489_writereg(LAPIC_ESR, 0);
 	(void)i82489_readreg(LAPIC_ESR);
 	i82489_writereg(LAPIC_ICRHI, target << LAPIC_ID_SHIFT);
 	i82489_writereg(LAPIC_ICRLO, LAPIC_DLMODE_INIT | LAPIC_LEVEL_ASSERT);
 	i82489_icr_wait();
 	i8254_delay(10000);
 	i82489_writereg(LAPIC_ICRLO,
 	    LAPIC_DLMODE_INIT | LAPIC_TRIGGER_LEVEL | LAPIC_LEVEL_DEASSERT);
 	i82489_icr_wait();
 	if ((i82489_readreg(LAPIC_ICRLO) & LAPIC_DLSTAT_BUSY) != 0)
 		return EBUSY;
 	esr = i82489_readreg(LAPIC_ESR);
 	if (esr != 0)
 		aprint_debug("%s: ESR %08x\n", __func__, esr);
 	return 0;
+}
 static int
 i82489_ipi_startup(int target, int vec)
+{
 	uint32_t esr;
 	i82489_writereg(LAPIC_ESR, 0);
 	(void)i82489_readreg(LAPIC_ESR);
 	i82489_icr_wait();
 	i82489_writereg(LAPIC_ICRHI, target << LAPIC_ID_SHIFT);
 	i82489_writereg(LAPIC_ICRLO, vec | LAPIC_DLMODE_STARTUP |
 	    LAPIC_LEVEL_ASSERT);
 	i82489_icr_wait();
 	if ((i82489_readreg(LAPIC_ICRLO) & LAPIC_DLSTAT_BUSY) != 0)
 		return EBUSY;
 	esr = i82489_readreg(LAPIC_ESR);
 	if (esr != 0)
 		aprint_debug("%s: ESR %08x\n", __func__, esr);
 	return 0;
+}
 static int
 i82489_ipi(int vec, int target, int dl)
+{
 	int result, s;
 	s = splhigh();
 	i82489_icr_wait();
 	if ((target & LAPIC_DEST_MASK) == 0)
 		i82489_writereg(LAPIC_ICRHI, target << LAPIC_ID_SHIFT);
 	i82489_writereg(LAPIC_ICRLO,
 	    (target & LAPIC_DEST_MASK) | vec | dl | LAPIC_LEVEL_ASSERT);
 #ifdef DIAGNOSTIC
 	i82489_icr_wait();
 	result = (i82489_readreg(LAPIC_ICRLO) & LAPIC_DLSTAT_BUSY) ? EBUSY : 0;
 #else
 	/* Don't wait - if it doesn't go, we're in big trouble anyway. */
         result = 0;
 #endif
 	splx(s);
 	return result;
+}
 static int
 x2apic_ipi_init(int target)
+{
 	x2apic_write_icr(target, LAPIC_DLMODE_INIT | LAPIC_LEVEL_ASSERT);
 	i8254_delay(10000);
 	x2apic_write_icr(0,
 	    LAPIC_DLMODE_INIT | LAPIC_TRIGGER_LEVEL | LAPIC_LEVEL_DEASSERT);
 	return 0;
+}
 static int
 x2apic_ipi_startup(int target, int vec)
+{
 	x2apic_write_icr(target, vec | LAPIC_DLMODE_STARTUP | LAPIC_LEVEL_ASSERT);
 	return 0;
+}
 static int
 x2apic_ipi(int vec, int target, int dl)
+{
 	uint32_t dest_id = 0;
 	if ((target & LAPIC_DEST_MASK) == 0)
 		dest_id = target;
 	x2apic_write_icr(dest_id,
 	    (target & LAPIC_DEST_MASK) | vec | dl | LAPIC_LEVEL_ASSERT);
 	return 0;
+}
 int
 x86_ipi_init(int target)
+{
 	if (x2apic_mode)
 		return x2apic_ipi_init(target);
 	return i82489_ipi_init(target);
+}
 int
 x86_ipi_startup(int target, int vec)
+{
 	if (x2apic_mode)
 		return x2apic_ipi_startup(target, vec);
 	return i82489_ipi_startup(target, vec);
+}
 /*
  * Using 'pin numbers' as:
  * 0 - timer
  * 1 - unused
  * 2 - PCINT
  * 3 - LVINT0
  * 4 - LVINT1
  * 5 - LVERR
  */
 static void
 lapic_hwmask(struct pic *pic, int pin)
+{
 	int reg;
 	uint32_t val;
 	reg = LAPIC_LVTT + (pin << 4);
 	val = lapic_readreg(reg);
 	val |= LAPIC_LVT_MASKED;
 	lapic_writereg(reg, val);
+}
 static void
 lapic_hwunmask(struct pic *pic, int pin)
+{
 	int reg;
 	uint32_t val;
 	reg = LAPIC_LVTT + (pin << 4);
 	val = lapic_readreg(reg);
 	val &= ~LAPIC_LVT_MASKED;
 	lapic_writereg(reg, val);
+}
 static void
 lapic_setup(struct pic *pic, struct cpu_info *ci,
     int pin, int idtvec, int type)
+{
+}
 void
 lapic_dump(void)
+{
 	struct cpu_info *ci = curcpu();
 	apic_format_redir(device_xname(ci->ci_dev), "timer", 0, 0,
 	    lapic_readreg(LAPIC_LVTT));
 	apic_format_redir(device_xname(ci->ci_dev), "pcint", 0, 0,
 	    lapic_readreg(LAPIC_PCINT));
 	apic_format_redir(device_xname(ci->ci_dev), "lint", 0, 0,
 	    lapic_readreg(LAPIC_LVINT0));
 	apic_format_redir(device_xname(ci->ci_dev), "lint", 1, 0,
 	    lapic_readreg(LAPIC_LVINT1));
 	apic_format_redir(device_xname(ci->ci_dev), "err", 0, 0,
 	    lapic_readreg(LAPIC_LVERR));
+}

 @@ -1,324 +1,324 @@
-/*	$NetBSD: db_interface.c,v 1.26 2017/08/15 06:57:53 maxv Exp $	*/
+/*	$NetBSD: db_interface.c,v 1.27 2017/08/15 09:08:39 maxv Exp $	*/
 /*
  * Mach Operating System
  * Copyright (c) 1991,1990 Carnegie Mellon University
  * All Rights Reserved.
+ *
  * Permission to use, copy, modify and distribute this software and its
  * documentation is hereby granted, provided that both the copyright
  * notice and this permission notice appear in all copies of the
  * software, derivative works or modified versions, and any portions
  * thereof, and that both notices appear in supporting documentation.
+ *
  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
+ *
  * Carnegie Mellon requests users of this software to return to
+ *
  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
  *  School of Computer Science
  *  Carnegie Mellon University
  *  Pittsburgh PA 15213-3890
+ *
  * any improvements or extensions that they make and grant Carnegie the
  * rights to redistribute these changes.
+ *
  *	db_interface.c,v 2.4 1991/02/05 17:11:13 mrt (CMU)
  */
 /*
  * Interface to new debugger.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.26 2017/08/15 06:57:53 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.27 2017/08/15 09:08:39 maxv Exp $");
 #include "opt_ddb.h"
 #include "opt_multiprocessor.h"
 #include "lapic.h"
 #include <sys/param.h>
 #include <sys/proc.h>
 #include <sys/reboot.h>
 #include <sys/systm.h>
 #include <sys/atomic.h>
 #include <sys/cpu.h>
 #include <dev/cons.h>
 #include <machine/cpufunc.h>
 #include <machine/db_machdep.h>
 #include <machine/cpuvar.h>
 #include <machine/i82093var.h>
 #include <machine/i82489reg.h>
 #include <machine/i82489var.h>
 #include <ddb/db_sym.h>
 #include <ddb/db_command.h>
 #include <ddb/db_extern.h>
 #include <ddb/db_access.h>
 #include <ddb/db_output.h>
 #include <ddb/ddbvar.h>
 extern const char *const trap_type[];
 extern int trap_types;
 int	db_active = 0;
 db_regs_t ddb_regs;	/* register state */
 db_regs_t *ddb_regp = NULL;
 void db_mach_cpu (db_expr_t, bool, db_expr_t, const char *);
 const struct db_command db_machine_command_table[] = {
 #ifdef MULTIPROCESSOR
 	{ DDB_ADD_CMD("cpu",	db_mach_cpu,	0,
 	  "switch to another cpu", "cpu-no", NULL) },
 #endif
 	{ DDB_ADD_CMD(NULL, NULL, 0, NULL, NULL, NULL) },
 };
 void kdbprinttrap(int, int);
 #ifdef MULTIPROCESSOR
 extern void ddb_ipi(struct trapframe);
 static void ddb_suspend(struct trapframe *);
 #ifndef XEN
 int ddb_vec;
 #endif /* XEN */
 static bool ddb_mp_online;
 #endif
 #define NOCPU	-1
 int ddb_cpu = NOCPU;
 typedef void (vector)(void);
-extern vector Xintrddb, Xx2apic_intrddb;
+extern vector Xintrddbipi, Xx2apic_intrddbipi;
 void
 db_machine_init(void)
+{
 #ifdef MULTIPROCESSOR
 #ifndef XEN
-	vector *handler = &Xintrddb;
+	vector *handler = &Xintrddbipi;
 #if NLAPIC > 0
 	if (lapic_is_x2apic())
-		handler = &Xx2apic_intrddb;
+		handler = &Xx2apic_intrddbipi;
 #endif
 	ddb_vec = idt_vec_alloc(0xf0, 0xff);
 	setgate(&idt[ddb_vec], handler, 1, SDT_SYS386IGT, SEL_KPL,
 	    GSEL(GCODE_SEL, SEL_KPL));
 #else
 	/* Initialised as part of xen_ipi_init() */
 #endif /* XEN */
 #endif
+}
 #ifdef MULTIPROCESSOR
 __cpu_simple_lock_t db_lock;
 static int
 db_suspend_others(void)
+{
 	int cpu_me = cpu_number();
 	int win;
 #ifndef XEN
 	if (ddb_vec == 0)
 		return 1;
 #endif /* XEN */
 	__cpu_simple_lock(&db_lock);
 	if (ddb_cpu == NOCPU)
 		ddb_cpu = cpu_me;
 	win = (ddb_cpu == cpu_me);
 	__cpu_simple_unlock(&db_lock);
 	if (win) {
 #ifdef XEN
 		xen_broadcast_ipi(XEN_IPI_DDB);
 #else
 		x86_ipi(ddb_vec, LAPIC_DEST_ALLEXCL, LAPIC_DLMODE_FIXED);
 #endif /* XEN */
+	}
 	ddb_mp_online = x86_mp_online;
 	x86_mp_online = false;
 	return win;
+}
 static void
 db_resume_others(void)
+{
 	CPU_INFO_ITERATOR cii;
 	struct cpu_info *ci;
 	x86_mp_online = ddb_mp_online;
 	__cpu_simple_lock(&db_lock);
 	ddb_cpu = NOCPU;
 	__cpu_simple_unlock(&db_lock);
 	for (CPU_INFO_FOREACH(cii, ci)) {
 		if (ci->ci_flags & CPUF_PAUSE)
 			atomic_and_32(&ci->ci_flags, ~CPUF_PAUSE);
+	}
+}
 #endif
 /*
  * Print trap reason.
  */
 void
 kdbprinttrap(int type, int code)
+{
 	db_printf("kernel: ");
 	if (type >= trap_types || type < 0)
 		db_printf("type %d", type);
 	else
 		db_printf("%s", trap_type[type]);
 	db_printf(" trap, code=%x\n", code);
+}
 /*
  *  kdb_trap - field a TRACE or BPT trap
  */
 int
 kdb_trap(int type, int code, db_regs_t *regs)
+{
 	int s;
 	db_regs_t dbreg;
 	switch (type) {
 	case T_NMI:	/* NMI */
 		printf("NMI ... going to debugger\n");
 		/*FALLTHROUGH*/
 	case T_BPTFLT:	/* breakpoint */
 	case T_TRCTRAP:	/* single_step */
 	case -1:	/* keyboard interrupt */
 		break;
 	default:
 		if (!db_onpanic && db_recover == 0)
 			return (0);
 		kdbprinttrap(type, code);
 		if (db_recover != 0) {
 			db_error("Faulted in DDB; continuing...\n");
 			/*NOTREACHED*/
+		}
+	}
 #ifdef MULTIPROCESSOR
 	if (!db_suspend_others()) {
 		ddb_suspend(regs);
 	} else {
 	curcpu()->ci_ddb_regs = &dbreg;
 	ddb_regp = &dbreg;
 #endif
 	ddb_regs = *regs;
 	ddb_regs.tf_cs &= 0xffff;
 	ddb_regs.tf_ds &= 0xffff;
 	ddb_regs.tf_es &= 0xffff;
 	ddb_regs.tf_fs &= 0xffff;
 	ddb_regs.tf_gs &= 0xffff;
 	ddb_regs.tf_ss &= 0xffff;
 	s = splhigh();
 	db_active++;
 	cnpollc(true);
 	db_trap(type, code);
 	cnpollc(false);
 	db_active--;
 	splx(s);
 #ifdef MULTIPROCESSOR
 	db_resume_others();
+	}
 #endif
 	ddb_regp = &dbreg;
 	*regs = ddb_regs;
 	return (1);
+}
 void
 cpu_Debugger(void)
+{
 	breakpoint();
+}
 #ifdef MULTIPROCESSOR
 /*
  * Called when we receive a debugger IPI (inter-processor interrupt).
  * As with trap() in trap.c, this function is called from an assembly
  * language IDT gate entry routine which prepares a suitable stack frame,
  * and restores this frame after the exception has been processed. Note
  * that the effect is as if the arguments were passed call by reference.
  */
 void
 ddb_ipi(struct trapframe frame)
+{
 	ddb_suspend(&frame);
+}
 static void
 ddb_suspend(struct trapframe *frame)
+{
 	volatile struct cpu_info *ci = curcpu();
 	db_regs_t regs;
 	regs = *frame;
 	ci->ci_ddb_regs = &regs;
 	atomic_or_32(&ci->ci_flags, CPUF_PAUSE);
 	while (ci->ci_flags & CPUF_PAUSE)
+		;
 	ci->ci_ddb_regs = 0;
 	tlbflushg();
+}
 extern void cpu_debug_dump(void); /* XXX */
 void
 db_mach_cpu(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif)
+{
 	struct cpu_info *ci;
 	if (!have_addr) {
 		cpu_debug_dump();
 		return;
+	}
 	if (addr < 0) {
 		db_printf("%ld: CPU out of range\n", addr);
 		return;
+	}
 	ci = cpu_lookup(addr);
 	if (ci == NULL) {
 		db_printf("CPU %ld not configured\n", addr);
 		return;
+	}
 	if (ci != curcpu()) {
 		if (!(ci->ci_flags & CPUF_PAUSE)) {
 			db_printf("CPU %ld not paused\n", addr);
 			return;
+		}
+	}
 	if (ci->ci_ddb_regs == 0) {
 		db_printf("CPU %ld has no saved regs\n", addr);
 		return;
+	}
 	db_printf("using CPU %ld", addr);
 	ddb_regp = ci->ci_ddb_regs;
+}
 #endif