 @@ -1,14 +1,14 @@
-#	$NetBSD: files.sunxi,v 1.31 2017/10/07 21:53:16 jmcneill Exp $
+#	$NetBSD: files.sunxi,v 1.32 2017/10/08 18:00:36 jmcneill Exp $
+#
 # Configuration info for Allwinner sunxi family SoCs
+#
+#
 include	"arch/arm/pic/files.pic"
 include	"arch/arm/cortex/files.cortex"
 file	arch/arm/arm32/arm32_boot.c
 file	arch/arm/arm32/arm32_kvminit.c
 file	arch/arm/arm32/arm32_reboot.c
 file	arch/arm/arm32/irq_dispatch.S
 file	arch/arm/arm32/armv7_generic_space.c
 @@ -48,61 +48,72 @@ device	sun8ia83tccu: sunxi_ccu
 attach	sun8ia83tccu at fdt with sunxi_a83t_ccu
 file	arch/arm/sunxi/sun8i_a83t_ccu.c		sunxi_a83t_ccu
 # CCU (H3)
 device	sun8ih3ccu: sunxi_ccu
 attach	sun8ih3ccu at fdt with sunxi_h3_ccu
 file	arch/arm/sunxi/sun8i_h3_ccu.c		sunxi_h3_ccu
 # CCU (H3 PRCM)
 device	sun8ih3rccu: sunxi_ccu
 attach	sun8ih3rccu at fdt with sunxi_h3_r_ccu
 file	arch/arm/sunxi/sun8i_h3_r_ccu.c		sunxi_h3_r_ccu
 # CCU (A80)
 device	sun9ia80ccu: sunxi_ccu
 attach	sun9ia80ccu at fdt with sunxi_a80_ccu
 file	arch/arm/sunxi/sun9i_a80_ccu.c		sunxi_a80_ccu
 # CCU (A64)
 device	sun50ia64ccu: sunxi_ccu
 attach	sun50ia64ccu at fdt with sunxi_a64_ccu
 file	arch/arm/sunxi/sun50i_a64_ccu.c		sunxi_a64_ccu
 # Misc. clock resets
 device	sunxiresets
 attach	sunxiresets at fdt with sunxi_resets
 file	arch/arm/sunxi/sunxi_resets.c		sunxi_resets
 # Misc. clock gates
 device	sunxigates
 attach	sunxigates at fdt with sunxi_gates
 file	arch/arm/sunxi/sunxi_gates.c		sunxi_gates
 # GMAC MII/RGMII clock mux
 device	sunxigmacclk
 attach	sunxigmacclk at fdt with sunxi_gmacclk
 file	arch/arm/sunxi/sunxi_gmacclk.c		sunxi_gmacclk
 # SD/MMC-COMM (A80)
 device	sun9immcclk
 attach	sun9immcclk at fdt with sunxi_a80_mmcclk
 file	arch/arm/sunxi/sun9i_a80_mmcclk.c	sunxi_a80_mmcclk
 # Interrupt controller
 device	sunxiintc: pic, pic_splfuncs
 attach	sunxiintc at fdt with sunxi_intc
 file	arch/arm/sunxi/sunxi_intc.c		sunxi_intc
 # GPIO
 device	sunxigpio: gpiobus
 attach	sunxigpio at fdt with sunxi_gpio
 file	arch/arm/sunxi/sunxi_gpio.c		sunxi_gpio
 file	arch/arm/sunxi/sun4i_a10_gpio.c		sunxi_gpio & soc_sun4i_a10
 file	arch/arm/sunxi/sun5i_a13_gpio.c		sunxi_gpio & soc_sun5i_a13
 file	arch/arm/sunxi/sun6i_a31_gpio.c		sunxi_gpio & soc_sun6i_a31
 file	arch/arm/sunxi/sun7i_a20_gpio.c		sunxi_gpio & soc_sun7i_a20
 file	arch/arm/sunxi/sun8i_a83t_gpio.c	sunxi_gpio & soc_sun8i_a83t
 file	arch/arm/sunxi/sun8i_h3_gpio.c		sunxi_gpio & soc_sun8i_h3
 file	arch/arm/sunxi/sun9i_a80_gpio.c		sunxi_gpio & soc_sun9i_a80
 file	arch/arm/sunxi/sun50i_a64_gpio.c	sunxi_gpio & soc_sun50i_a64
 # UART
 attach	com at fdt with sunxi_com
 file	arch/arm/sunxi/sunxi_com.c		sunxi_com needs-flag
 # SD/MMC
 device	sunximmc: sdmmcbus
 attach	sunximmc at fdt with sunxi_mmc
 file	arch/arm/sunxi/sunxi_mmc.c		sunxi_mmc
 # USB PHY
 device	sunxiusbphy
 @@ -203,15 +214,17 @@ file	arch/arm/sunxi/sunxi_sata.c		sunxi_
 # SOC parameters
 defflag	opt_soc.h			SOC_SUNXI
 defflag	opt_soc.h			SOC_SUN4I: SOC_SUNXI
 defflag	opt_soc.h			SOC_SUN4I_A10: SOC_SUN4I
 defflag	opt_soc.h			SOC_SUN5I: SOC_SUNXI
 defflag	opt_soc.h			SOC_SUN5I_A13: SOC_SUN5I
 defflag	opt_soc.h			SOC_SUN6I: SOC_SUNXI
 defflag	opt_soc.h			SOC_SUN6I_A31: SOC_SUN6I
 defflag	opt_soc.h			SOC_SUN7I: SOC_SUNXI
 defflag	opt_soc.h			SOC_SUN7I_A20: SOC_SUN7I
 defflag	opt_soc.h			SOC_SUN8I: SOC_SUNXI
 defflag	opt_soc.h			SOC_SUN8I_A83T: SOC_SUN8I
 defflag	opt_soc.h			SOC_SUN8I_H3: SOC_SUN8I
 defflag	opt_soc.h			SOC_SUN9I: SOC_SUNXI
 defflag	opt_soc.h			SOC_SUN9I_A80: SOC_SUN9I
 defflag	opt_soc.h			SOC_SUN50I: SOC_SUNXI
 defflag	opt_soc.h			SOC_SUN50I_A64: SOC_SUN50I

 @@ -1,14 +1,14 @@
-/* $NetBSD: sunxi_gpio.c,v 1.14 2017/10/06 21:20:59 jmcneill Exp $ */
+/* $NetBSD: sunxi_gpio.c,v 1.15 2017/10/08 18:00:36 jmcneill Exp $ */
 /*-
  * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -19,116 +19,124 @@
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include "opt_soc.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sunxi_gpio.c,v 1.14 2017/10/06 21:20:59 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sunxi_gpio.c,v 1.15 2017/10/08 18:00:36 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/mutex.h>
 #include <sys/kmem.h>
 #include <sys/gpio.h>
 #include <sys/bitops.h>
 #include <sys/lwp.h>
 #include <dev/fdt/fdtvar.h>
 #include <dev/gpio/gpiovar.h>
 #include <arm/sunxi/sunxi_gpio.h>
 #define	SUNXI_GPIO_MAX_EINT_BANK	5
 #define	SUNXI_GPIO_MAX_EINT		32
 #define	SUNXI_GPIO_PORT(port)		(0x24 * (port))
 #define SUNXI_GPIO_CFG(port, pin)	(SUNXI_GPIO_PORT(port) + 0x00 + (0x4 * ((pin) / 8)))
 #define  SUNXI_GPIO_CFG_PINMASK(pin)	(0x7 << (((pin) % 8) * 4))
 #define	SUNXI_GPIO_DATA(port)		(SUNXI_GPIO_PORT(port) + 0x10)
 #define	SUNXI_GPIO_DRV(port, pin)	(SUNXI_GPIO_PORT(port) + 0x14 + (0x4 * ((pin) / 16)))
 #define  SUNXI_GPIO_DRV_PINMASK(pin)	(0x3 << (((pin) % 16) * 2))
 #define	SUNXI_GPIO_PULL(port, pin)	(SUNXI_GPIO_PORT(port) + 0x1c + (0x4 * ((pin) / 16)))
 #define	 SUNXI_GPIO_PULL_DISABLE	0
 #define	 SUNXI_GPIO_PULL_UP		1
 #define	 SUNXI_GPIO_PULL_DOWN		2
 #define  SUNXI_GPIO_PULL_PINMASK(pin)	(0x3 << (((pin) % 16) * 2))
-#define	SUNXI_GPIO_INT_CFG(eint)	(0x200 + (0x4 * ((eint) / 8)))
+#define	SUNXI_GPIO_INT_CFG(bank, eint)	(0x200 + (0x20 * (bank)) + (0x4 * ((eint) / 8)))
 #define	 SUNXI_GPIO_INT_MODEMASK(eint)	(0xf << (((eint) % 8) * 4))
 #define	  SUNXI_GPIO_INT_MODE_POS_EDGE		0x0
 #define	  SUNXI_GPIO_INT_MODE_NEG_EDGE		0x1
 #define	  SUNXI_GPIO_INT_MODE_HIGH_LEVEL	0x2
 #define	  SUNXI_GPIO_INT_MODE_LOW_LEVEL		0x3
 #define	  SUNXI_GPIO_INT_MODE_DOUBLE_EDGE	0x4
-#define	SUNXI_GPIO_INT_CTL		0x210
+#define	SUNXI_GPIO_INT_CTL(bank)	(0x210 + 0x20 * (bank))
-#define	SUNXI_GPIO_INT_STATUS		0x214
+#define	SUNXI_GPIO_INT_STATUS(bank)	(0x214 + 0x20 * (bank))
 static const struct of_compat_data compat_data[] = {
 #ifdef SOC_SUN4I_A10
 	{ "allwinner,sun4i-a10-pinctrl",	(uintptr_t)&sun4i_a10_padconf },
 #endif
 #ifdef SOC_SUN5I_A13
 	{ "allwinner,sun5i-a13-pinctrl",	(uintptr_t)&sun5i_a13_padconf },
 #endif
 #ifdef SOC_SUN6I_A31
 	{ "allwinner,sun6i-a31-pinctrl",	(uintptr_t)&sun6i_a31_padconf },
 	{ "allwinner,sun6i-a31-r-pinctrl",	(uintptr_t)&sun6i_a31_r_padconf },
 #endif
 #ifdef SOC_SUN7I_A20
 	{ "allwinner,sun7i-a20-pinctrl",	(uintptr_t)&sun7i_a20_padconf },
 #endif
 #ifdef SOC_SUN8I_A83T
 	{ "allwinner,sun8i-a83t-pinctrl",	(uintptr_t)&sun8i_a83t_padconf },
 	{ "allwinner,sun8i-a83t-r-pinctrl",	(uintptr_t)&sun8i_a83t_r_padconf },
 #endif
 #ifdef SOC_SUN8I_H3
 	{ "allwinner,sun8i-h3-pinctrl",		(uintptr_t)&sun8i_h3_padconf },
 	{ "allwinner,sun8i-h3-r-pinctrl",	(uintptr_t)&sun8i_h3_r_padconf },
 #endif
 #ifdef SOC_SUN9I_A80
 	{ "allwinner,sun9i-a80-pinctrl",	(uintptr_t)&sun9i_a80_padconf },
 	{ "allwinner,sun9i-a80-r-pinctrl",	(uintptr_t)&sun9i_a80_r_padconf },
 #endif
 #ifdef SOC_SUN50I_A64
 	{ "allwinner,sun50i-a64-pinctrl",	(uintptr_t)&sun50i_a64_padconf },
 	{ "allwinner,sun50i-a64-r-pinctrl",	(uintptr_t)&sun50i_a64_r_padconf },
 #endif
 	{ NULL }
 };
 struct sunxi_gpio_eint {
 	int (*eint_func)(void *);
 	void *eint_arg;
 	int eint_flags;
 	int eint_bank;
 	int eint_num;
 };
 struct sunxi_gpio_softc {
 	device_t sc_dev;
 	bus_space_tag_t sc_bst;
 	bus_space_handle_t sc_bsh;
 	const struct sunxi_gpio_padconf *sc_padconf;
 	kmutex_t sc_lock;
 	struct gpio_chipset_tag sc_gp;
 	gpio_pin_t *sc_pins;
 	device_t sc_gpiodev;
 	u_int sc_eint_bank_max;
 	void *sc_ih;
-	struct sunxi_gpio_eint sc_eint[SUNXI_GPIO_MAX_EINT];
+	struct sunxi_gpio_eint sc_eint[SUNXI_GPIO_MAX_EINT_BANK][SUNXI_GPIO_MAX_EINT];
 };
 struct sunxi_gpio_pin {
 	struct sunxi_gpio_softc *pin_sc;
 	const struct sunxi_gpio_pins *pin_def;
 	int pin_flags;
 	bool pin_actlo;
 };
 #define GPIO_READ(sc, reg) 		\
     bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
 #define GPIO_WRITE(sc, reg, val) 	\
     bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
 @@ -378,42 +386,47 @@ sunxi_gpio_write(device_t dev, void *pri
 static struct fdtbus_gpio_controller_func sunxi_gpio_funcs = {
 	.acquire = sunxi_gpio_acquire,
 	.release = sunxi_gpio_release,
 	.read = sunxi_gpio_read,
 	.write = sunxi_gpio_write,
 };
 static int
 sunxi_gpio_intr(void *priv)
+{
 	struct sunxi_gpio_softc * const sc = priv;
 	struct sunxi_gpio_eint *eint;
 	uint32_t status, bit;
 	u_int bank;
 	int ret = 0;
-	status = GPIO_READ(sc, SUNXI_GPIO_INT_STATUS);
+	for (bank = 0; bank <= sc->sc_eint_bank_max; bank++) {
-	GPIO_WRITE(sc, SUNXI_GPIO_INT_STATUS, status);
+		status = GPIO_READ(sc, SUNXI_GPIO_INT_STATUS(bank));
 		if (status == 0)
 	while ((bit = ffs32(status)) != 0) {
 		status &= ~__BIT(bit - 1);
 		eint = &sc->sc_eint[bit - 1];
 		if (eint->eint_func == NULL)
 			continue;
-		const bool mpsafe = (eint->eint_flags & FDT_INTR_MPSAFE) != 0;
+		GPIO_WRITE(sc, SUNXI_GPIO_INT_STATUS(bank), status);
 		if (!mpsafe)
-			KERNEL_LOCK(1, curlwp);
+		while ((bit = ffs32(status)) != 0) {
-		ret |= eint->eint_func(eint->eint_arg);
+			status &= ~__BIT(bit - 1);
-		if (!mpsafe)
+			eint = &sc->sc_eint[bank][bit - 1];
-			KERNEL_UNLOCK_ONE(curlwp);
+			if (eint->eint_func == NULL)
 				continue;
 			const bool mpsafe = (eint->eint_flags & FDT_INTR_MPSAFE) != 0;
 			if (!mpsafe)
 				KERNEL_LOCK(1, curlwp);
 			ret |= eint->eint_func(eint->eint_arg);
 			if (!mpsafe)
 				KERNEL_UNLOCK_ONE(curlwp);
+		}
+	}
 	return ret;
+}
 static void *
 sunxi_gpio_establish(device_t dev, u_int *specifier, int ipl, int flags,
     int (*func)(void *), void *arg)
+{
 	struct sunxi_gpio_softc * const sc = device_private(dev);
 	const struct sunxi_gpio_pins *pin_def;
 	struct sunxi_gpio_eint *eint;
 	uint32_t val;
 @@ -455,75 +468,76 @@ sunxi_gpio_establish(device_t dev, u_int
+	}
 	pin_def = sunxi_gpio_lookup(sc, port, pin);
 	if (pin_def == NULL)
 		return NULL;
 	if (pin_def->functions[pin_def->eint_func] == NULL ||
 	    strcmp(pin_def->functions[pin_def->eint_func], "eint") != 0)
 		return NULL;
 	KASSERT(pin_def->eint_num < SUNXI_GPIO_MAX_EINT);
 	mutex_enter(&sc->sc_lock);
-	eint = &sc->sc_eint[pin_def->eint_num];
+	eint = &sc->sc_eint[pin_def->eint_bank][pin_def->eint_num];
 	if (eint->eint_func != NULL) {
 		mutex_exit(&sc->sc_lock);
 		return NULL;	/* in use */
+	}
 	/* Set function */
 	if (sunxi_gpio_setfunc(sc, pin_def, "eint") != 0) {
 		mutex_exit(&sc->sc_lock);
 		return NULL;
+	}
 	eint->eint_func = func;
 	eint->eint_arg = arg;
 	eint->eint_flags = flags;
 	eint->eint_bank = pin_def->eint_bank;
 	eint->eint_num = pin_def->eint_num;
 	/* Configure eint mode */
-	val = GPIO_READ(sc, SUNXI_GPIO_INT_CFG(eint->eint_num));
+	val = GPIO_READ(sc, SUNXI_GPIO_INT_CFG(eint->eint_bank, eint->eint_num));
 	val &= ~SUNXI_GPIO_INT_MODEMASK(eint->eint_num);
 	val |= __SHIFTIN(mode, SUNXI_GPIO_INT_MODEMASK(eint->eint_num));
-	GPIO_WRITE(sc, SUNXI_GPIO_INT_CFG(eint->eint_num), val);
+	GPIO_WRITE(sc, SUNXI_GPIO_INT_CFG(eint->eint_bank, eint->eint_num), val);
 	/* Enable eint */
-	val = GPIO_READ(sc, SUNXI_GPIO_INT_CTL);
+	val = GPIO_READ(sc, SUNXI_GPIO_INT_CTL(eint->eint_bank));
 	val |= __BIT(eint->eint_num);
-	GPIO_WRITE(sc, SUNXI_GPIO_INT_CTL, val);
+	GPIO_WRITE(sc, SUNXI_GPIO_INT_CTL(eint->eint_bank), val);
 	mutex_exit(&sc->sc_lock);
 	return eint;
+}
 static void
 sunxi_gpio_disestablish(device_t dev, void *ih)
+{
 	struct sunxi_gpio_softc * const sc = device_private(dev);
 	struct sunxi_gpio_eint * const eint = ih;
 	uint32_t val;
 	KASSERT(eint->eint_func != NULL);
 	mutex_enter(&sc->sc_lock);
 	/* Disable eint */
-	val = GPIO_READ(sc, SUNXI_GPIO_INT_CTL);
+	val = GPIO_READ(sc, SUNXI_GPIO_INT_CTL(eint->eint_bank));
 	val &= ~__BIT(eint->eint_num);
-	GPIO_WRITE(sc, SUNXI_GPIO_INT_CTL, val);
+	GPIO_WRITE(sc, SUNXI_GPIO_INT_CTL(eint->eint_bank), val);
-	GPIO_WRITE(sc, SUNXI_GPIO_INT_STATUS, __BIT(eint->eint_num));
+	GPIO_WRITE(sc, SUNXI_GPIO_INT_STATUS(eint->eint_bank), __BIT(eint->eint_num));
 	eint->eint_func = NULL;
 	eint->eint_arg = NULL;
 	eint->eint_flags = 0;
 	mutex_exit(&sc->sc_lock);
+}
 static bool
 sunxi_gpio_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen)
+{
 	struct sunxi_gpio_softc * const sc = device_private(dev);
 	const struct sunxi_gpio_pins *pin_def;
 @@ -823,28 +837,37 @@ sunxi_gpio_attach(device_t parent, devic
 	fdtbus_register_gpio_controller(self, phandle, &sunxi_gpio_funcs);
 	for (child = OF_child(phandle); child; child = OF_peer(child)) {
 		if (!of_hasprop(child, "function") || !of_hasprop(child, "pins"))
 			continue;
 		fdtbus_register_pinctrl_config(self, child, &sunxi_pinctrl_funcs);
+	}
 	fdtbus_pinctrl_configure();
 	sunxi_gpio_attach_ports(sc);
 	/* Disable all external interrupts */
-	GPIO_WRITE(sc, SUNXI_GPIO_INT_CTL, 0);
+	for (int i = 0; i < sc->sc_padconf->npins; i++) {
-	GPIO_WRITE(sc, SUNXI_GPIO_INT_STATUS, GPIO_READ(sc, SUNXI_GPIO_INT_STATUS));
+		const struct sunxi_gpio_pins *pin_def = &sc->sc_padconf->pins[i];
 		if (pin_def->eint_func == 0)
 			continue;
 		GPIO_WRITE(sc, SUNXI_GPIO_INT_CTL(pin_def->eint_bank), __BIT(pin_def->eint_num));
 		GPIO_WRITE(sc, SUNXI_GPIO_INT_STATUS(pin_def->eint_bank), __BIT(pin_def->eint_num));
 		if (sc->sc_eint_bank_max < pin_def->eint_bank)
 			sc->sc_eint_bank_max = pin_def->eint_bank;
+	}
 	KASSERT(sc->sc_eint_bank_max < SUNXI_GPIO_MAX_EINT_BANK);
 	if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
 		aprint_error_dev(self, "failed to decode interrupt\n");
 		return;
+	}
 	sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_VM, FDT_INTR_MPSAFE,
 	    sunxi_gpio_intr, sc);
 	if (sc->sc_ih == NULL) {
 		aprint_error_dev(self, "failed to establish interrupt on %s\n",
 		    intrstr);
 		return;
+	}
 	aprint_normal_dev(self, "interrupting on %s\n", intrstr);

 @@ -1,14 +1,14 @@
-/* $NetBSD: sunxi_gpio.h,v 1.6 2017/10/06 21:20:59 jmcneill Exp $ */
+/* $NetBSD: sunxi_gpio.h,v 1.7 2017/10/08 18:00:36 jmcneill Exp $ */
 /*-
  * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
  * Copyright (c) 2016 Emmanuel Vadot <manu@bidouilliste.com>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
 @@ -33,26 +33,27 @@
 #define	_ARM_SUNXI_GPIO_H
 #include "opt_soc.h"
 #define SUNXI_GPIO_MAXFUNC	8
 struct sunxi_gpio_pins {
 	const char *name;
 	uint8_t port;
 	uint8_t pin;
 	const char *functions[SUNXI_GPIO_MAXFUNC];
 	uint8_t eint_func;
 	uint8_t eint_num;
 	uint8_t eint_bank;
 };
 struct sunxi_gpio_padconf {
 	uint32_t npins;
 	const struct sunxi_gpio_pins *pins;
 };
 #ifdef SOC_SUN4I_A10
 extern const struct sunxi_gpio_padconf sun4i_a10_padconf;
 #endif
 #ifdef SOC_SUN5I_A13
 extern const struct sunxi_gpio_padconf sun5i_a13_padconf;
 @@ -67,19 +68,24 @@ extern const struct sunxi_gpio_padconf s
 extern const struct sunxi_gpio_padconf sun7i_a20_padconf;
 #endif
 #ifdef SOC_SUN8I_A83T
 extern const struct sunxi_gpio_padconf sun8i_a83t_padconf;
 extern const struct sunxi_gpio_padconf sun8i_a83t_r_padconf;
 #endif
 #ifdef SOC_SUN8I_H3
 extern const struct sunxi_gpio_padconf sun8i_h3_padconf;
 extern const struct sunxi_gpio_padconf sun8i_h3_r_padconf;
 #endif
 #ifdef SOC_SUN9I_A80
 extern const struct sunxi_gpio_padconf sun9i_a80_padconf;
 extern const struct sunxi_gpio_padconf sun9i_a80_r_padconf;
 #endif
 #ifdef SOC_SUN50I_A64
 extern const struct sunxi_gpio_padconf sun50i_a64_padconf;
 extern const struct sunxi_gpio_padconf sun50i_a64_r_padconf;
 #endif
 #endif /* _ARM_SUNXI_GPIO_H */

 @@ -1,14 +1,14 @@
-/* $NetBSD: sunxi_mmc.c,v 1.9 2017/10/08 13:48:40 jmcneill Exp $ */
+/* $NetBSD: sunxi_mmc.c,v 1.10 2017/10/08 18:00:36 jmcneill Exp $ */
 /*-
  * Copyright (c) 2014-2017 Jared McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -17,27 +17,27 @@
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sunxi_mmc.c,v 1.9 2017/10/08 13:48:40 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sunxi_mmc.c,v 1.10 2017/10/08 18:00:36 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/gpio.h>
 #include <dev/sdmmc/sdmmcvar.h>
 #include <dev/sdmmc/sdmmcchip.h>
 #include <dev/sdmmc/sdmmc_ioreg.h>
 @@ -48,34 +48,42 @@ __KERNEL_RCSID(0, "$NetBSD: sunxi_mmc.c,
 enum sunxi_mmc_timing {
 	SUNXI_MMC_TIMING_400K,
 	SUNXI_MMC_TIMING_25M,
 	SUNXI_MMC_TIMING_50M,
 	SUNXI_MMC_TIMING_50M_DDR,
 	SUNXI_MMC_TIMING_50M_DDR_8BIT,
 };
 struct sunxi_mmc_delay {
 	u_int	output_phase;
 	u_int	sample_phase;
 };
-static const struct sunxi_mmc_delay sunxi_mmc_delays[] = {
+static const struct sunxi_mmc_delay sun7i_mmc_delays[] = {
 	[SUNXI_MMC_TIMING_400K]		= { 180,	180 },
 	[SUNXI_MMC_TIMING_25M]		= { 180,	 75 },
 	[SUNXI_MMC_TIMING_50M]		= {  90,	120 },
 	[SUNXI_MMC_TIMING_50M_DDR]	= {  60,	120 },
 	[SUNXI_MMC_TIMING_50M_DDR_8BIT]	= {  90,	180 },
 };
 static const struct sunxi_mmc_delay sun9i_mmc_delays[] = {
 	[SUNXI_MMC_TIMING_400K]		= { 180,	180 },
 	[SUNXI_MMC_TIMING_25M]		= { 180,	 75 },
 	[SUNXI_MMC_TIMING_50M]		= { 150,	120 },
 	[SUNXI_MMC_TIMING_50M_DDR]	= {  54,	 36 },
 	[SUNXI_MMC_TIMING_50M_DDR_8BIT]	= {  72,	 72 },
 };
 #define SUNXI_MMC_NDESC		16
 struct sunxi_mmc_softc;
 static int	sunxi_mmc_match(device_t, cfdata_t, void *);
 static void	sunxi_mmc_attach(device_t, device_t, void *);
 static void	sunxi_mmc_attach_i(device_t);
 static int	sunxi_mmc_intr(void *);
 static int	sunxi_mmc_idma_setup(struct sunxi_mmc_softc *);
 static int	sunxi_mmc_host_reset(sdmmc_chipset_handle_t);
 static uint32_t	sunxi_mmc_host_ocr(sdmmc_chipset_handle_t);
 @@ -178,43 +186,51 @@ static const struct sunxi_mmc_config sun
 	.flags = 0,
 };
 static const struct sunxi_mmc_config sun5i_a13_mmc_config = {
 	.idma_xferlen = 0x10000,
 	.dma_ftrglevel = 0x20070008,
 	.delays = NULL,
 	.flags = 0,
 };
 static const struct sunxi_mmc_config sun7i_a20_mmc_config = {
 	.idma_xferlen = 0x2000,
 	.dma_ftrglevel = 0x20070008,
-	.delays = sunxi_mmc_delays,
+	.delays = sun7i_mmc_delays,
 	.flags = 0,
 };
 static const struct sunxi_mmc_config sun9i_a80_mmc_config = {
 	.idma_xferlen = 0x10000,
 	.dma_ftrglevel = 0x200f0010,
 	.delays = sun9i_mmc_delays,
 	.flags = 0,
 };
 static const struct sunxi_mmc_config sun50i_a64_mmc_config = {
 	.idma_xferlen = 0x10000,
 	.dma_ftrglevel = 0x20070008,
 	.delays = NULL,
 	.flags = SUNXI_MMC_FLAG_CALIB_REG |
 		 SUNXI_MMC_FLAG_NEW_TIMINGS |
 		 SUNXI_MMC_FLAG_MASK_DATA0,
 };
 static const struct of_compat_data compat_data[] = {
 	{ "allwinner,sun4i-a10-mmc",	(uintptr_t)&sun4i_a10_mmc_config },
 	{ "allwinner,sun5i-a13-mmc",	(uintptr_t)&sun5i_a13_mmc_config },
 	{ "allwinner,sun7i-a20-mmc",	(uintptr_t)&sun7i_a20_mmc_config },
 	{ "allwinner,sun9i-a80-mmc",	(uintptr_t)&sun9i_a80_mmc_config },
 	{ "allwinner,sun50i-a64-mmc",	(uintptr_t)&sun50i_a64_mmc_config },
 	{ NULL }
 };
 static int
 sunxi_mmc_match(device_t parent, cfdata_t cf, void *aux)
+{
 	struct fdt_attach_args * const faa = aux;
 	return of_match_compat_data(faa->faa_phandle, compat_data);
+}
 static void

 @@ -1,14 +1,14 @@
-/* $NetBSD: sunxi_platform.c,v 1.9 2017/10/06 21:12:23 jmcneill Exp $ */
+/* $NetBSD: sunxi_platform.c,v 1.10 2017/10/08 18:00:36 jmcneill Exp $ */
 /*-
  * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -21,27 +21,27 @@
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include "opt_soc.h"
 #include "opt_multiprocessor.h"
 #include "opt_fdt_arm.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sunxi_platform.c,v 1.9 2017/10/06 21:12:23 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sunxi_platform.c,v 1.10 2017/10/08 18:00:36 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/cpu.h>
 #include <sys/device.h>
 #include <sys/termios.h>
 #include <dev/fdt/fdtvar.h>
 #include <arm/fdt/arm_fdtvar.h>
 #include <uvm/uvm_extern.h>
 #include <machine/bootconfig.h>
 @@ -72,26 +72,33 @@ __KERNEL_RCSID(0, "$NetBSD: sunxi_platfo
 #define	 SUN4I_WDT_CTRL_KEY	(0x333 << 1)
 #define	 SUN4I_WDT_CTRL_RESTART	__BIT(0)
 #define	SUN4I_WDT_MODE		0x04
 #define	 SUN4I_WDT_MODE_RST_EN	__BIT(1)
 #define	 SUN4I_WDT_MODE_EN	__BIT(0)
 #define	SUN6I_WDT_BASE		0x01c20ca0
 #define	SUN6I_WDT_SIZE		0x20
 #define	SUN6I_WDT_CFG		0x14
 #define	 SUN6I_WDT_CFG_SYS	__BIT(0)
 #define	SUN6I_WDT_MODE		0x18
 #define	 SUN6I_WDT_MODE_EN	__BIT(0)
 #define	SUN9I_WDT_BASE		0x06000ca0
 #define	SUN9I_WDT_SIZE		0x20
 #define	SUN9I_WDT_CFG		0x14
 #define	 SUN9I_WDT_CFG_SYS	__BIT(0)
 #define	SUN9I_WDT_MODE		0x18
 #define	 SUN9I_WDT_MODE_EN	__BIT(0)
 #define	DEVMAP_ALIGN(a)	((a) & ~L1_S_OFFSET)
 #define	DEVMAP_SIZE(s)	roundup2((s), L1_S_SIZE)
 #define	DEVMAP_ENTRY(va, pa, sz)			\
 	{						\
 		.pd_va = DEVMAP_ALIGN(va),		\
 		.pd_pa = DEVMAP_ALIGN(pa),		\
 		.pd_size = DEVMAP_SIZE(sz),		\
 		.pd_prot = VM_PROT_READ|VM_PROT_WRITE,	\
 		.pd_cache = PTE_NOCACHE			\
+	}
 #define	DEVMAP_ENTRY_END	{ 0 }
 @@ -206,26 +213,38 @@ sun4i_platform_delay(u_int n)
 static void
 sun6i_platform_reset(void)
+{
 	bus_space_tag_t bst = &armv7_generic_bs_tag;
 	bus_space_handle_t bsh;
 	bus_space_map(bst, SUN6I_WDT_BASE, SUN6I_WDT_SIZE, 0, &bsh);
 	bus_space_write_4(bst, bsh, SUN6I_WDT_CFG, SUN6I_WDT_CFG_SYS);
 	bus_space_write_4(bst, bsh, SUN6I_WDT_MODE, SUN6I_WDT_MODE_EN);
+}
 static void
 sun9i_platform_reset(void)
+{
 	bus_space_tag_t bst = &armv7_generic_bs_tag;
 	bus_space_handle_t bsh;
 	bus_space_map(bst, SUN9I_WDT_BASE, SUN9I_WDT_SIZE, 0, &bsh);
 	bus_space_write_4(bst, bsh, SUN9I_WDT_CFG, SUN9I_WDT_CFG_SYS);
 	bus_space_write_4(bst, bsh, SUN9I_WDT_MODE, SUN9I_WDT_MODE_EN);
+}
 static const struct arm_platform sun4i_platform = {
 	.devmap = sunxi_platform_devmap,
 	.bootstrap = sunxi_platform_bootstrap,
 	.init_attach_args = sunxi_platform_init_attach_args,
 	.early_putchar = sunxi_platform_early_putchar,
 	.device_register = sunxi_platform_device_register,
 	.reset = sun4i_platform_reset,
 	.delay = sun4i_platform_delay,
 	.uart_freq = sunxi_platform_uart_freq,
 };
 ARM_PLATFORM(sun4i_a10, "allwinner,sun4i-a10", &sun4i_platform);
 @@ -273,25 +292,38 @@ static const struct arm_platform sun8i_p
 	.bootstrap = sunxi_platform_psci_bootstrap,
 	.init_attach_args = sunxi_platform_init_attach_args,
 	.early_putchar = sunxi_platform_early_putchar,
 	.device_register = sunxi_platform_device_register,
 	.reset = sun6i_platform_reset,
 	.delay = gtmr_delay,
 	.uart_freq = sunxi_platform_uart_freq,
 };
 ARM_PLATFORM(sun8i_h2plus, "allwinner,sun8i-h2-plus", &sun8i_platform);
 ARM_PLATFORM(sun8i_h3, "allwinner,sun8i-h3", &sun8i_platform);
 ARM_PLATFORM(sun8i_a83t, "allwinner,sun8i-a83t", &sun8i_platform);
 static const struct arm_platform sun9i_platform = {
 	.devmap = sunxi_platform_devmap,
 	.bootstrap = sunxi_platform_bootstrap,
 	.init_attach_args = sunxi_platform_init_attach_args,
 	.early_putchar = sunxi_platform_early_putchar,
 	.device_register = sunxi_platform_device_register,
 	.reset = sun9i_platform_reset,
 	.delay = gtmr_delay,
 	.uart_freq = sunxi_platform_uart_freq,
 };
 ARM_PLATFORM(sun9i_a80, "allwinner,sun9i-a80", &sun9i_platform);
 static const struct arm_platform sun50i_platform = {
 	.devmap = sunxi_platform_devmap,
 	.bootstrap = sunxi_platform_bootstrap,
 	.init_attach_args = sunxi_platform_init_attach_args,
 	.early_putchar = sunxi_platform_early_putchar,
 	.device_register = sunxi_platform_device_register,
 	.reset = sun6i_platform_reset,
 	.delay = gtmr_delay,
 	.uart_freq = sunxi_platform_uart_freq,
 };
 ARM_PLATFORM(sun50i_a64, "allwinner,sun50i-a64", &sun50i_platform);