 @@ -1,14 +1,14 @@
-/* $NetBSD: tegra_pcie.c,v 1.22 2017/09/27 10:19:13 jmcneill Exp $ */
+/* $NetBSD: tegra_pcie.c,v 1.23 2017/10/19 16:01:58 skrll Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -17,27 +17,27 @@
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_pcie.c,v 1.22 2017/09/27 10:19:13 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_pcie.c,v 1.23 2017/10/19 16:01:58 skrll Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/extent.h>
 #include <sys/queue.h>
 #include <sys/mutex.h>
 #include <sys/kmem.h>
 #include <arm/cpufunc.h>
 @@ -345,41 +345,43 @@ tegra_pcie_enable_clocks(struct tegra_pc
 		if (clk == NULL || clk_enable(clk) != 0)
 			aprint_error_dev(sc->sc_dev, "couldn't enable clock %s\n",
 			    clock_names[n]);
+	}
 	for (n = 0; n < __arraycount(reset_names); n++) {
 		rst = fdtbus_reset_get(sc->sc_phandle, reset_names[n]);
 		if (rst == NULL || fdtbus_reset_deassert(rst) != 0)
 			aprint_error_dev(sc->sc_dev, "couldn't de-assert reset %s\n",
 			    reset_names[n]);
+	}
+}
 #if 0
 static void
 tegra_pcie_reset_port(struct tegra_pcie_softc * const sc, int index)
+{
 	uint32_t val;
 	val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index));
 	val &= ~AFI_PEXn_CTRL_RST_L;
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index), val);
 	delay(2000);
 	val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index));
 	val |= AFI_PEXn_CTRL_RST_L;
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index), val);
+}
 #endif
 static void
 tegra_pcie_enable_ports(struct tegra_pcie_softc * const sc)
+{
 	struct fdtbus_phy *phy;
 	const u_int *data;
 	int child, len, n;
 	uint32_t val;
 	for (child = OF_child(sc->sc_phandle); child; child = OF_peer(child)) {
 		if (!fdtbus_status_okay(child))
 			continue;
 @@ -390,27 +392,29 @@ tegra_pcie_enable_ports(struct tegra_pci
 				    fdtbus_get_string(child, "name"), n);
 		data = fdtbus_get_prop(child, "reg", &len);
 		if (data == NULL || len < 4)
 			continue;
 		const u_int index = ((be32toh(data[0]) >> 11) & 0x1f) - 1;
 		val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index));
 		val |= AFI_PEXn_CTRL_CLKREQ_EN;
 		val |= AFI_PEXn_CTRL_REFCLK_EN;
 		val |= AFI_PEXn_CTRL_REFCLK_OVERRIDE_EN;
 		bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index), val);
 #if 0
 		tegra_pcie_reset_port(sc, index);
 #endif
+	}
+}
 static void
 tegra_pcie_setup(struct tegra_pcie_softc * const sc)
+{
 	uint32_t val, cfg, lanes;
 	int child, len;
 	const u_int *data;
 	size_t i;
 	/* Enable PLLE control */