Mon Nov 27 14:09:11 2017 UTC ()
Pull up following revision(s) (requested by jmcneill in ticket #397):
	sys/arch/mips/cavium/dev/if_cnmac.c: revision 1.7
Set ETHERCAP_VLAN_MTU capability flag.


(martin)
diff -r1.5 -r1.5.8.1 src/sys/arch/mips/cavium/dev/if_cnmac.c
cvs diff -r1.5 -r1.5.8.1 src/sys/arch/mips/cavium/dev/if_cnmac.c (switch to unified diff)

--- src/sys/arch/mips/cavium/dev/if_cnmac.c 2016/12/15 09:28:03 1.5
+++ src/sys/arch/mips/cavium/dev/if_cnmac.c 2017/11/27 14:09:11 1.5.8.1
@@ -1,1367 +1,1370 @@ @@ -1,1367 +1,1370 @@
1/* $NetBSD: if_cnmac.c,v 1.5 2016/12/15 09:28:03 ozaki-r Exp $ */ 1/* $NetBSD: if_cnmac.c,v 1.5.8.1 2017/11/27 14:09:11 martin Exp $ */
2 2
3#include <sys/cdefs.h> 3#include <sys/cdefs.h>
4#if 0 4#if 0
5__KERNEL_RCSID(0, "$NetBSD: if_cnmac.c,v 1.5 2016/12/15 09:28:03 ozaki-r Exp $"); 5__KERNEL_RCSID(0, "$NetBSD: if_cnmac.c,v 1.5.8.1 2017/11/27 14:09:11 martin Exp $");
6#endif 6#endif
7 7
8#include "opt_octeon.h" 8#include "opt_octeon.h"
9 9
10#ifdef OCTEON_ETH_DEBUG 10#ifdef OCTEON_ETH_DEBUG
11 11
12#ifndef DIAGNOSTIC 12#ifndef DIAGNOSTIC
13#define DIAGNOSTIC 13#define DIAGNOSTIC
14#endif 14#endif
15 15
16#ifndef DEBUG 16#ifndef DEBUG
17#define DEBUG 17#define DEBUG
18#endif 18#endif
19 19
20#endif 20#endif
21 21
22/* 22/*
23 * If no free send buffer is available, free all the sent buffer and bail out. 23 * If no free send buffer is available, free all the sent buffer and bail out.
24 */ 24 */
25#define OCTEON_ETH_SEND_QUEUE_CHECK 25#define OCTEON_ETH_SEND_QUEUE_CHECK
26 26
27/* XXX XXX XXX XXX XXX XXX */ 27/* XXX XXX XXX XXX XXX XXX */
28 28
29#include <sys/param.h> 29#include <sys/param.h>
30#include <sys/systm.h> 30#include <sys/systm.h>
31#include <sys/pool.h> 31#include <sys/pool.h>
32#include <sys/mbuf.h> 32#include <sys/mbuf.h>
33#include <sys/malloc.h> 33#include <sys/malloc.h>
34#include <sys/kernel.h> 34#include <sys/kernel.h>
35#include <sys/socket.h> 35#include <sys/socket.h>
36#include <sys/ioctl.h> 36#include <sys/ioctl.h>
37#include <sys/errno.h> 37#include <sys/errno.h>
38#include <sys/device.h> 38#include <sys/device.h>
39#include <sys/queue.h> 39#include <sys/queue.h>
40#include <sys/conf.h> 40#include <sys/conf.h>
41#include <sys/sysctl.h> 41#include <sys/sysctl.h>
42#include <sys/syslog.h> 42#include <sys/syslog.h>
43 43
44#include <net/if.h> 44#include <net/if.h>
45#include <net/if_dl.h> 45#include <net/if_dl.h>
46#include <net/if_media.h> 46#include <net/if_media.h>
47#include <net/if_ether.h> 47#include <net/if_ether.h>
48#include <net/route.h> 48#include <net/route.h>
49 49
50#include <net/bpf.h> 50#include <net/bpf.h>
51 51
52#include <netinet/in.h> 52#include <netinet/in.h>
53#include <netinet/in_systm.h> 53#include <netinet/in_systm.h>
54#include <netinet/in_var.h> 54#include <netinet/in_var.h>
55#include <netinet/ip.h> 55#include <netinet/ip.h>
56 56
57#include <sys/bus.h> 57#include <sys/bus.h>
58#include <machine/intr.h> 58#include <machine/intr.h>
59#include <machine/endian.h> 59#include <machine/endian.h>
60#include <machine/locore.h> 60#include <machine/locore.h>
61 61
62#include <dev/mii/mii.h> 62#include <dev/mii/mii.h>
63#include <dev/mii/miivar.h> 63#include <dev/mii/miivar.h>
64 64
65#include <mips/cpuregs.h> 65#include <mips/cpuregs.h>
66 66
67#include <mips/cavium/dev/octeon_asxreg.h> 67#include <mips/cavium/dev/octeon_asxreg.h>
68#include <mips/cavium/dev/octeon_ciureg.h> 68#include <mips/cavium/dev/octeon_ciureg.h>
69#include <mips/cavium/dev/octeon_npireg.h> 69#include <mips/cavium/dev/octeon_npireg.h>
70#include <mips/cavium/dev/octeon_gmxreg.h> 70#include <mips/cavium/dev/octeon_gmxreg.h>
71#include <mips/cavium/dev/octeon_ipdreg.h> 71#include <mips/cavium/dev/octeon_ipdreg.h>
72#include <mips/cavium/dev/octeon_pipreg.h> 72#include <mips/cavium/dev/octeon_pipreg.h>
73#include <mips/cavium/dev/octeon_powreg.h> 73#include <mips/cavium/dev/octeon_powreg.h>
74#include <mips/cavium/dev/octeon_faureg.h> 74#include <mips/cavium/dev/octeon_faureg.h>
75#include <mips/cavium/dev/octeon_fpareg.h> 75#include <mips/cavium/dev/octeon_fpareg.h>
76#include <mips/cavium/dev/octeon_bootbusreg.h> 76#include <mips/cavium/dev/octeon_bootbusreg.h>
77#include <mips/cavium/include/iobusvar.h> 77#include <mips/cavium/include/iobusvar.h>
78#include <mips/cavium/octeonvar.h> 78#include <mips/cavium/octeonvar.h>
79#include <mips/cavium/dev/octeon_fpavar.h> 79#include <mips/cavium/dev/octeon_fpavar.h>
80#include <mips/cavium/dev/octeon_gmxvar.h> 80#include <mips/cavium/dev/octeon_gmxvar.h>
81#include <mips/cavium/dev/octeon_fauvar.h> 81#include <mips/cavium/dev/octeon_fauvar.h>
82#include <mips/cavium/dev/octeon_powvar.h> 82#include <mips/cavium/dev/octeon_powvar.h>
83#include <mips/cavium/dev/octeon_ipdvar.h> 83#include <mips/cavium/dev/octeon_ipdvar.h>
84#include <mips/cavium/dev/octeon_pipvar.h> 84#include <mips/cavium/dev/octeon_pipvar.h>
85#include <mips/cavium/dev/octeon_pkovar.h> 85#include <mips/cavium/dev/octeon_pkovar.h>
86#include <mips/cavium/dev/octeon_asxvar.h> 86#include <mips/cavium/dev/octeon_asxvar.h>
87#include <mips/cavium/dev/octeon_smivar.h> 87#include <mips/cavium/dev/octeon_smivar.h>
88#include <mips/cavium/dev/if_cnmacvar.h> 88#include <mips/cavium/dev/if_cnmacvar.h>
89 89
90#ifdef OCTEON_ETH_DEBUG 90#ifdef OCTEON_ETH_DEBUG
91#define OCTEON_ETH_KASSERT(x) KASSERT(x) 91#define OCTEON_ETH_KASSERT(x) KASSERT(x)
92#define OCTEON_ETH_KDASSERT(x) KDASSERT(x) 92#define OCTEON_ETH_KDASSERT(x) KDASSERT(x)
93#else 93#else
94#define OCTEON_ETH_KASSERT(x) 94#define OCTEON_ETH_KASSERT(x)
95#define OCTEON_ETH_KDASSERT(x) 95#define OCTEON_ETH_KDASSERT(x)
96#endif 96#endif
97 97
98/* 98/*
99 * Set the PKO to think command buffers are an odd length. This makes it so we 99 * Set the PKO to think command buffers are an odd length. This makes it so we
100 * never have to divide a comamnd across two buffers. 100 * never have to divide a comamnd across two buffers.
101 */ 101 */
102#define OCTEON_POOL_NWORDS_CMD \ 102#define OCTEON_POOL_NWORDS_CMD \
103 (((uint32_t)OCTEON_POOL_SIZE_CMD / sizeof(uint64_t)) - 1) 103 (((uint32_t)OCTEON_POOL_SIZE_CMD / sizeof(uint64_t)) - 1)
104#define FPA_COMMAND_BUFFER_POOL_NWORDS OCTEON_POOL_NWORDS_CMD /* XXX */ 104#define FPA_COMMAND_BUFFER_POOL_NWORDS OCTEON_POOL_NWORDS_CMD /* XXX */
105 105
106static void octeon_eth_buf_init(struct octeon_eth_softc *); 106static void octeon_eth_buf_init(struct octeon_eth_softc *);
107 107
108static int octeon_eth_match(device_t, struct cfdata *, void *); 108static int octeon_eth_match(device_t, struct cfdata *, void *);
109static void octeon_eth_attach(device_t, device_t, void *); 109static void octeon_eth_attach(device_t, device_t, void *);
110static void octeon_eth_pip_init(struct octeon_eth_softc *); 110static void octeon_eth_pip_init(struct octeon_eth_softc *);
111static void octeon_eth_ipd_init(struct octeon_eth_softc *); 111static void octeon_eth_ipd_init(struct octeon_eth_softc *);
112static void octeon_eth_pko_init(struct octeon_eth_softc *); 112static void octeon_eth_pko_init(struct octeon_eth_softc *);
113static void octeon_eth_asx_init(struct octeon_eth_softc *); 113static void octeon_eth_asx_init(struct octeon_eth_softc *);
114static void octeon_eth_smi_init(struct octeon_eth_softc *); 114static void octeon_eth_smi_init(struct octeon_eth_softc *);
115 115
116static void octeon_eth_board_mac_addr(uint8_t *, size_t, struct octeon_eth_softc *); 116static void octeon_eth_board_mac_addr(uint8_t *, size_t, struct octeon_eth_softc *);
117 117
118static int octeon_eth_mii_readreg(device_t, int, int); 118static int octeon_eth_mii_readreg(device_t, int, int);
119static void octeon_eth_mii_writereg(device_t, int, int, int); 119static void octeon_eth_mii_writereg(device_t, int, int, int);
120static void octeon_eth_mii_statchg(struct ifnet *); 120static void octeon_eth_mii_statchg(struct ifnet *);
121 121
122static int octeon_eth_mediainit(struct octeon_eth_softc *); 122static int octeon_eth_mediainit(struct octeon_eth_softc *);
123static void octeon_eth_mediastatus(struct ifnet *, struct ifmediareq *); 123static void octeon_eth_mediastatus(struct ifnet *, struct ifmediareq *);
124static int octeon_eth_mediachange(struct ifnet *); 124static int octeon_eth_mediachange(struct ifnet *);
125 125
126static inline void octeon_eth_send_queue_flush_prefetch(struct octeon_eth_softc *); 126static inline void octeon_eth_send_queue_flush_prefetch(struct octeon_eth_softc *);
127static inline void octeon_eth_send_queue_flush_fetch(struct octeon_eth_softc *); 127static inline void octeon_eth_send_queue_flush_fetch(struct octeon_eth_softc *);
128static inline void octeon_eth_send_queue_flush(struct octeon_eth_softc *); 128static inline void octeon_eth_send_queue_flush(struct octeon_eth_softc *);
129static inline void octeon_eth_send_queue_flush_sync(struct octeon_eth_softc *); 129static inline void octeon_eth_send_queue_flush_sync(struct octeon_eth_softc *);
130static inline int octeon_eth_send_queue_is_full(struct octeon_eth_softc *); 130static inline int octeon_eth_send_queue_is_full(struct octeon_eth_softc *);
131static inline void octeon_eth_send_queue_add(struct octeon_eth_softc *, 131static inline void octeon_eth_send_queue_add(struct octeon_eth_softc *,
132 struct mbuf *, uint64_t *); 132 struct mbuf *, uint64_t *);
133static inline void octeon_eth_send_queue_del(struct octeon_eth_softc *, 133static inline void octeon_eth_send_queue_del(struct octeon_eth_softc *,
134 struct mbuf **, uint64_t **); 134 struct mbuf **, uint64_t **);
135static inline int octeon_eth_buf_free_work(struct octeon_eth_softc *, 135static inline int octeon_eth_buf_free_work(struct octeon_eth_softc *,
136 uint64_t *, uint64_t); 136 uint64_t *, uint64_t);
137static inline void octeon_eth_buf_ext_free_m(struct mbuf *, void *, size_t, void *); 137static inline void octeon_eth_buf_ext_free_m(struct mbuf *, void *, size_t, void *);
138static inline void octeon_eth_buf_ext_free_ext(struct mbuf *, void *, size_t, void *); 138static inline void octeon_eth_buf_ext_free_ext(struct mbuf *, void *, size_t, void *);
139 139
140static int octeon_eth_ioctl(struct ifnet *, u_long, void *); 140static int octeon_eth_ioctl(struct ifnet *, u_long, void *);
141static void octeon_eth_watchdog(struct ifnet *); 141static void octeon_eth_watchdog(struct ifnet *);
142static int octeon_eth_init(struct ifnet *); 142static int octeon_eth_init(struct ifnet *);
143static void octeon_eth_stop(struct ifnet *, int); 143static void octeon_eth_stop(struct ifnet *, int);
144static void octeon_eth_start(struct ifnet *); 144static void octeon_eth_start(struct ifnet *);
145 145
146static inline int octeon_eth_send_cmd(struct octeon_eth_softc *, uint64_t, 146static inline int octeon_eth_send_cmd(struct octeon_eth_softc *, uint64_t,
147 uint64_t); 147 uint64_t);
148static inline uint64_t octeon_eth_send_makecmd_w1(int, paddr_t); 148static inline uint64_t octeon_eth_send_makecmd_w1(int, paddr_t);
149static inline uint64_t octeon_eth_send_makecmd_w0(uint64_t, uint64_t, size_t, 149static inline uint64_t octeon_eth_send_makecmd_w0(uint64_t, uint64_t, size_t,
150 int); 150 int);
151static inline int octeon_eth_send_makecmd_gbuf(struct octeon_eth_softc *, 151static inline int octeon_eth_send_makecmd_gbuf(struct octeon_eth_softc *,
152 struct mbuf *, uint64_t *, int *); 152 struct mbuf *, uint64_t *, int *);
153static inline int octeon_eth_send_makecmd(struct octeon_eth_softc *, 153static inline int octeon_eth_send_makecmd(struct octeon_eth_softc *,
154 struct mbuf *, uint64_t *, uint64_t *, uint64_t *); 154 struct mbuf *, uint64_t *, uint64_t *, uint64_t *);
155static inline int octeon_eth_send_buf(struct octeon_eth_softc *, 155static inline int octeon_eth_send_buf(struct octeon_eth_softc *,
156 struct mbuf *, uint64_t *); 156 struct mbuf *, uint64_t *);
157static inline int octeon_eth_send(struct octeon_eth_softc *, 157static inline int octeon_eth_send(struct octeon_eth_softc *,
158 struct mbuf *); 158 struct mbuf *);
159 159
160static int octeon_eth_reset(struct octeon_eth_softc *); 160static int octeon_eth_reset(struct octeon_eth_softc *);
161static int octeon_eth_configure(struct octeon_eth_softc *); 161static int octeon_eth_configure(struct octeon_eth_softc *);
162static int octeon_eth_configure_common(struct octeon_eth_softc *); 162static int octeon_eth_configure_common(struct octeon_eth_softc *);
163 163
164static void octeon_eth_tick_free(void *arg); 164static void octeon_eth_tick_free(void *arg);
165static void octeon_eth_tick_misc(void *); 165static void octeon_eth_tick_misc(void *);
166 166
167static inline int octeon_eth_recv_mbuf(struct octeon_eth_softc *, 167static inline int octeon_eth_recv_mbuf(struct octeon_eth_softc *,
168 uint64_t *, struct mbuf **); 168 uint64_t *, struct mbuf **);
169static inline int octeon_eth_recv_check_code(struct octeon_eth_softc *, 169static inline int octeon_eth_recv_check_code(struct octeon_eth_softc *,
170 uint64_t); 170 uint64_t);
171static inline int octeon_eth_recv_check_jumbo(struct octeon_eth_softc *, 171static inline int octeon_eth_recv_check_jumbo(struct octeon_eth_softc *,
172 uint64_t); 172 uint64_t);
173static inline int octeon_eth_recv_check_link(struct octeon_eth_softc *, 173static inline int octeon_eth_recv_check_link(struct octeon_eth_softc *,
174 uint64_t); 174 uint64_t);
175static inline int octeon_eth_recv_check(struct octeon_eth_softc *, 175static inline int octeon_eth_recv_check(struct octeon_eth_softc *,
176 uint64_t); 176 uint64_t);
177static inline int octeon_eth_recv(struct octeon_eth_softc *, uint64_t *); 177static inline int octeon_eth_recv(struct octeon_eth_softc *, uint64_t *);
178static void octeon_eth_recv_redir(struct ifnet *, struct mbuf *); 178static void octeon_eth_recv_redir(struct ifnet *, struct mbuf *);
179static inline void octeon_eth_recv_intr(void *, uint64_t *); 179static inline void octeon_eth_recv_intr(void *, uint64_t *);
180 180
181/* device driver context */ 181/* device driver context */
182static struct octeon_eth_softc *octeon_eth_gsc[GMX_PORT_NUNITS]; 182static struct octeon_eth_softc *octeon_eth_gsc[GMX_PORT_NUNITS];
183static void *octeon_eth_pow_recv_ih; 183static void *octeon_eth_pow_recv_ih;
184 184
185/* sysctl'able parameters */ 185/* sysctl'able parameters */
186int octeon_eth_param_pko_cmd_w0_n2 = 1; 186int octeon_eth_param_pko_cmd_w0_n2 = 1;
187int octeon_eth_param_pip_dyn_rs = 1; 187int octeon_eth_param_pip_dyn_rs = 1;
188int octeon_eth_param_redir = 0; 188int octeon_eth_param_redir = 0;
189int octeon_eth_param_pktbuf = 0; 189int octeon_eth_param_pktbuf = 0;
190int octeon_eth_param_rate = 0; 190int octeon_eth_param_rate = 0;
191int octeon_eth_param_intr = 0; 191int octeon_eth_param_intr = 0;
192 192
193CFATTACH_DECL_NEW(cnmac, sizeof(struct octeon_eth_softc), 193CFATTACH_DECL_NEW(cnmac, sizeof(struct octeon_eth_softc),
194 octeon_eth_match, octeon_eth_attach, NULL, NULL); 194 octeon_eth_match, octeon_eth_attach, NULL, NULL);
195 195
196#ifdef OCTEON_ETH_DEBUG 196#ifdef OCTEON_ETH_DEBUG
197 197
198static const struct octeon_evcnt_entry octeon_evcnt_entries[] = { 198static const struct octeon_evcnt_entry octeon_evcnt_entries[] = {
199#define _ENTRY(name, type, parent, descr) \ 199#define _ENTRY(name, type, parent, descr) \
200 OCTEON_EVCNT_ENTRY(struct octeon_eth_softc, name, type, parent, descr) 200 OCTEON_EVCNT_ENTRY(struct octeon_eth_softc, name, type, parent, descr)
201 _ENTRY(rx, MISC, NULL, "rx"), 201 _ENTRY(rx, MISC, NULL, "rx"),
202 _ENTRY(rxint, INTR, NULL, "rx intr"), 202 _ENTRY(rxint, INTR, NULL, "rx intr"),
203 _ENTRY(rxrs, MISC, NULL, "rx dynamic short"), 203 _ENTRY(rxrs, MISC, NULL, "rx dynamic short"),
204 _ENTRY(rxbufpkalloc, MISC, NULL, "rx buf pkt alloc"), 204 _ENTRY(rxbufpkalloc, MISC, NULL, "rx buf pkt alloc"),
205 _ENTRY(rxbufpkput, MISC, NULL, "rx buf pkt put"), 205 _ENTRY(rxbufpkput, MISC, NULL, "rx buf pkt put"),
206 _ENTRY(rxbufwqalloc, MISC, NULL, "rx buf wqe alloc"), 206 _ENTRY(rxbufwqalloc, MISC, NULL, "rx buf wqe alloc"),
207 _ENTRY(rxbufwqput, MISC, NULL, "rx buf wqe put"), 207 _ENTRY(rxbufwqput, MISC, NULL, "rx buf wqe put"),
208 _ENTRY(rxerrcode, MISC, NULL, "rx code error"), 208 _ENTRY(rxerrcode, MISC, NULL, "rx code error"),
209 _ENTRY(rxerrfix, MISC, NULL, "rx fixup error"), 209 _ENTRY(rxerrfix, MISC, NULL, "rx fixup error"),
210 _ENTRY(rxerrjmb, MISC, NULL, "rx jmb error"), 210 _ENTRY(rxerrjmb, MISC, NULL, "rx jmb error"),
211 _ENTRY(rxerrlink, MISC, NULL, "rx link error"), 211 _ENTRY(rxerrlink, MISC, NULL, "rx link error"),
212 _ENTRY(rxerroff, MISC, NULL, "rx offload error"), 212 _ENTRY(rxerroff, MISC, NULL, "rx offload error"),
213 _ENTRY(rxonperrshort, MISC, NULL, "rx onp fixup short error"), 213 _ENTRY(rxonperrshort, MISC, NULL, "rx onp fixup short error"),
214 _ENTRY(rxonperrpreamble, MISC, NULL, "rx onp fixup preamble error"), 214 _ENTRY(rxonperrpreamble, MISC, NULL, "rx onp fixup preamble error"),
215 _ENTRY(rxonperrcrc, MISC, NULL, "rx onp fixup crc error"), 215 _ENTRY(rxonperrcrc, MISC, NULL, "rx onp fixup crc error"),
216 _ENTRY(rxonperraddress, MISC, NULL, "rx onp fixup address error"), 216 _ENTRY(rxonperraddress, MISC, NULL, "rx onp fixup address error"),
217 _ENTRY(rxonponp, MISC, NULL, "rx onp fixup onp packets"), 217 _ENTRY(rxonponp, MISC, NULL, "rx onp fixup onp packets"),
218 _ENTRY(rxonpok, MISC, NULL, "rx onp fixup success packets"), 218 _ENTRY(rxonpok, MISC, NULL, "rx onp fixup success packets"),
219 _ENTRY(tx, MISC, NULL, "tx"), 219 _ENTRY(tx, MISC, NULL, "tx"),
220 _ENTRY(txadd, MISC, NULL, "tx add"), 220 _ENTRY(txadd, MISC, NULL, "tx add"),
221 _ENTRY(txbufcballoc, MISC, NULL, "tx buf cb alloc"), 221 _ENTRY(txbufcballoc, MISC, NULL, "tx buf cb alloc"),
222 _ENTRY(txbufcbget, MISC, NULL, "tx buf cb get"), 222 _ENTRY(txbufcbget, MISC, NULL, "tx buf cb get"),
223 _ENTRY(txbufgballoc, MISC, NULL, "tx buf gb alloc"), 223 _ENTRY(txbufgballoc, MISC, NULL, "tx buf gb alloc"),
224 _ENTRY(txbufgbget, MISC, NULL, "tx buf gb get"), 224 _ENTRY(txbufgbget, MISC, NULL, "tx buf gb get"),
225 _ENTRY(txbufgbput, MISC, NULL, "tx buf gb put"), 225 _ENTRY(txbufgbput, MISC, NULL, "tx buf gb put"),
226 _ENTRY(txdel, MISC, NULL, "tx del"), 226 _ENTRY(txdel, MISC, NULL, "tx del"),
227 _ENTRY(txerr, MISC, NULL, "tx error"), 227 _ENTRY(txerr, MISC, NULL, "tx error"),
228 _ENTRY(txerrcmd, MISC, NULL, "tx cmd error"), 228 _ENTRY(txerrcmd, MISC, NULL, "tx cmd error"),
229 _ENTRY(txerrgbuf, MISC, NULL, "tx gbuf error"), 229 _ENTRY(txerrgbuf, MISC, NULL, "tx gbuf error"),
230 _ENTRY(txerrlink, MISC, NULL, "tx link error"), 230 _ENTRY(txerrlink, MISC, NULL, "tx link error"),
231 _ENTRY(txerrmkcmd, MISC, NULL, "tx makecmd error"), 231 _ENTRY(txerrmkcmd, MISC, NULL, "tx makecmd error"),
232#undef _ENTRY 232#undef _ENTRY
233}; 233};
234#endif 234#endif
235 235
236/* ---- buffer management */ 236/* ---- buffer management */
237 237
238static const struct octeon_eth_pool_param { 238static const struct octeon_eth_pool_param {
239 int poolno; 239 int poolno;
240 size_t size; 240 size_t size;
241 size_t nelems; 241 size_t nelems;
242} octeon_eth_pool_params[] = { 242} octeon_eth_pool_params[] = {
243#define _ENTRY(x) { OCTEON_POOL_NO_##x, OCTEON_POOL_SIZE_##x, OCTEON_POOL_NELEMS_##x } 243#define _ENTRY(x) { OCTEON_POOL_NO_##x, OCTEON_POOL_SIZE_##x, OCTEON_POOL_NELEMS_##x }
244 _ENTRY(PKT), 244 _ENTRY(PKT),
245 _ENTRY(WQE), 245 _ENTRY(WQE),
246 _ENTRY(CMD), 246 _ENTRY(CMD),
247 _ENTRY(SG) 247 _ENTRY(SG)
248#undef _ENTRY 248#undef _ENTRY
249}; 249};
250struct octeon_fpa_buf *octeon_eth_pools[8/* XXX */]; 250struct octeon_fpa_buf *octeon_eth_pools[8/* XXX */];
251#define octeon_eth_fb_pkt octeon_eth_pools[OCTEON_POOL_NO_PKT] 251#define octeon_eth_fb_pkt octeon_eth_pools[OCTEON_POOL_NO_PKT]
252#define octeon_eth_fb_wqe octeon_eth_pools[OCTEON_POOL_NO_WQE] 252#define octeon_eth_fb_wqe octeon_eth_pools[OCTEON_POOL_NO_WQE]
253#define octeon_eth_fb_cmd octeon_eth_pools[OCTEON_POOL_NO_CMD] 253#define octeon_eth_fb_cmd octeon_eth_pools[OCTEON_POOL_NO_CMD]
254#define octeon_eth_fb_sg octeon_eth_pools[OCTEON_POOL_NO_SG] 254#define octeon_eth_fb_sg octeon_eth_pools[OCTEON_POOL_NO_SG]
255 255
256static void 256static void
257octeon_eth_buf_init(struct octeon_eth_softc *sc) 257octeon_eth_buf_init(struct octeon_eth_softc *sc)
258{ 258{
259 static int once; 259 static int once;
260 int i; 260 int i;
261 const struct octeon_eth_pool_param *pp; 261 const struct octeon_eth_pool_param *pp;
262 struct octeon_fpa_buf *fb; 262 struct octeon_fpa_buf *fb;
263 263
264 if (once == 1) 264 if (once == 1)
265 return; 265 return;
266 once = 1; 266 once = 1;
267 267
268 for (i = 0; i < (int)__arraycount(octeon_eth_pool_params); i++) { 268 for (i = 0; i < (int)__arraycount(octeon_eth_pool_params); i++) {
269 pp = &octeon_eth_pool_params[i]; 269 pp = &octeon_eth_pool_params[i];
270 octeon_fpa_buf_init(pp->poolno, pp->size, pp->nelems, &fb); 270 octeon_fpa_buf_init(pp->poolno, pp->size, pp->nelems, &fb);
271 octeon_eth_pools[i] = fb; 271 octeon_eth_pools[i] = fb;
272 } 272 }
273} 273}
274 274
275/* ---- autoconf */ 275/* ---- autoconf */
276 276
277static int 277static int
278octeon_eth_match(device_t parent, struct cfdata *match, void *aux) 278octeon_eth_match(device_t parent, struct cfdata *match, void *aux)
279{ 279{
280 struct octeon_gmx_attach_args *ga = aux; 280 struct octeon_gmx_attach_args *ga = aux;
281 281
282 if (strcmp(match->cf_name, ga->ga_name) != 0) { 282 if (strcmp(match->cf_name, ga->ga_name) != 0) {
283 return 0; 283 return 0;
284 } 284 }
285 return 1; 285 return 1;
286} 286}
287 287
288static void 288static void
289octeon_eth_attach(device_t parent, device_t self, void *aux) 289octeon_eth_attach(device_t parent, device_t self, void *aux)
290{ 290{
291 struct octeon_eth_softc *sc = device_private(self); 291 struct octeon_eth_softc *sc = device_private(self);
292 struct octeon_gmx_attach_args *ga = aux; 292 struct octeon_gmx_attach_args *ga = aux;
293 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 293 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
294 uint8_t enaddr[ETHER_ADDR_LEN]; 294 uint8_t enaddr[ETHER_ADDR_LEN];
295 295
296 sc->sc_dev = self; 296 sc->sc_dev = self;
297 sc->sc_regt = ga->ga_regt; 297 sc->sc_regt = ga->ga_regt;
298 sc->sc_port = ga->ga_portno; 298 sc->sc_port = ga->ga_portno;
299 sc->sc_port_type = ga->ga_port_type; 299 sc->sc_port_type = ga->ga_port_type;
300 sc->sc_gmx = ga->ga_gmx; 300 sc->sc_gmx = ga->ga_gmx;
301 sc->sc_gmx_port = ga->ga_gmx_port; 301 sc->sc_gmx_port = ga->ga_gmx_port;
302 302
303 sc->sc_init_flag = 0; 303 sc->sc_init_flag = 0;
304 /* 304 /*
305 * XXXUEBAYASI 305 * XXXUEBAYASI
306 * Setting PIP_IP_OFFSET[OFFSET] to 8 causes panic ... why??? 306 * Setting PIP_IP_OFFSET[OFFSET] to 8 causes panic ... why???
307 */ 307 */
308 sc->sc_ip_offset = 0/* XXX */; 308 sc->sc_ip_offset = 0/* XXX */;
309 309
310 if (MIPS_PRID_IMPL(mips_options.mips_cpu_id) <= MIPS_CN30XX) { 310 if (MIPS_PRID_IMPL(mips_options.mips_cpu_id) <= MIPS_CN30XX) {
311 SET(sc->sc_quirks, OCTEON_ETH_QUIRKS_NO_PRE_ALIGN); 311 SET(sc->sc_quirks, OCTEON_ETH_QUIRKS_NO_PRE_ALIGN);
312 SET(sc->sc_quirks, OCTEON_ETH_QUIRKS_NO_RX_INBND); 312 SET(sc->sc_quirks, OCTEON_ETH_QUIRKS_NO_RX_INBND);
313 } 313 }
314 314
315 octeon_eth_board_mac_addr(enaddr, sizeof(enaddr), sc); 315 octeon_eth_board_mac_addr(enaddr, sizeof(enaddr), sc);
316 printf("%s: Ethernet address %s\n", device_xname(sc->sc_dev), 316 printf("%s: Ethernet address %s\n", device_xname(sc->sc_dev),
317 ether_sprintf(enaddr)); 317 ether_sprintf(enaddr));
318 318
319 octeon_eth_gsc[sc->sc_port] = sc; 319 octeon_eth_gsc[sc->sc_port] = sc;
320 320
321 SIMPLEQ_INIT(&sc->sc_sendq); 321 SIMPLEQ_INIT(&sc->sc_sendq);
322 sc->sc_soft_req_thresh = 15/* XXX */; 322 sc->sc_soft_req_thresh = 15/* XXX */;
323 sc->sc_ext_callback_cnt = 0; 323 sc->sc_ext_callback_cnt = 0;
324 324
325 octeon_gmx_stats_init(sc->sc_gmx_port); 325 octeon_gmx_stats_init(sc->sc_gmx_port);
326 326
327 callout_init(&sc->sc_tick_misc_ch, 0); 327 callout_init(&sc->sc_tick_misc_ch, 0);
328 callout_init(&sc->sc_tick_free_ch, 0); 328 callout_init(&sc->sc_tick_free_ch, 0);
329 329
330 octeon_fau_op_init(&sc->sc_fau_done, 330 octeon_fau_op_init(&sc->sc_fau_done,
331 OCTEON_CVMSEG_ETHER_OFFSET(sc->sc_port, csm_ether_fau_done), 331 OCTEON_CVMSEG_ETHER_OFFSET(sc->sc_port, csm_ether_fau_done),
332 OCT_FAU_REG_ADDR_END - (8 * (sc->sc_port + 1))/* XXX */); 332 OCT_FAU_REG_ADDR_END - (8 * (sc->sc_port + 1))/* XXX */);
333 octeon_fau_op_set_8(&sc->sc_fau_done, 0); 333 octeon_fau_op_set_8(&sc->sc_fau_done, 0);
334 334
335 octeon_eth_pip_init(sc); 335 octeon_eth_pip_init(sc);
336 octeon_eth_ipd_init(sc); 336 octeon_eth_ipd_init(sc);
337 octeon_eth_pko_init(sc); 337 octeon_eth_pko_init(sc);
338 octeon_eth_asx_init(sc); 338 octeon_eth_asx_init(sc);
339 octeon_eth_smi_init(sc); 339 octeon_eth_smi_init(sc);
340 340
341 sc->sc_gmx_port->sc_ipd = sc->sc_ipd; 341 sc->sc_gmx_port->sc_ipd = sc->sc_ipd;
342 sc->sc_gmx_port->sc_port_asx = sc->sc_asx; 342 sc->sc_gmx_port->sc_port_asx = sc->sc_asx;
343 sc->sc_gmx_port->sc_port_mii = &sc->sc_mii; 343 sc->sc_gmx_port->sc_port_mii = &sc->sc_mii;
344 sc->sc_gmx_port->sc_port_ec = &sc->sc_ethercom; 344 sc->sc_gmx_port->sc_port_ec = &sc->sc_ethercom;
345 /* XXX */ 345 /* XXX */
346 sc->sc_gmx_port->sc_quirks = sc->sc_quirks; 346 sc->sc_gmx_port->sc_quirks = sc->sc_quirks;
347 347
348 /* XXX */ 348 /* XXX */
349 sc->sc_pow = &octeon_pow_softc; 349 sc->sc_pow = &octeon_pow_softc;
350 350
351 octeon_eth_mediainit(sc); 351 octeon_eth_mediainit(sc);
352 352
353 strncpy(ifp->if_xname, device_xname(sc->sc_dev), sizeof(ifp->if_xname)); 353 strncpy(ifp->if_xname, device_xname(sc->sc_dev), sizeof(ifp->if_xname));
354 ifp->if_softc = sc; 354 ifp->if_softc = sc;
355 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 355 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
356 ifp->if_ioctl = octeon_eth_ioctl; 356 ifp->if_ioctl = octeon_eth_ioctl;
357 ifp->if_start = octeon_eth_start; 357 ifp->if_start = octeon_eth_start;
358 ifp->if_watchdog = octeon_eth_watchdog; 358 ifp->if_watchdog = octeon_eth_watchdog;
359 ifp->if_init = octeon_eth_init; 359 ifp->if_init = octeon_eth_init;
360 ifp->if_stop = octeon_eth_stop; 360 ifp->if_stop = octeon_eth_stop;
361 IFQ_SET_MAXLEN(&ifp->if_snd, max(GATHER_QUEUE_SIZE, IFQ_MAXLEN)); 361 IFQ_SET_MAXLEN(&ifp->if_snd, max(GATHER_QUEUE_SIZE, IFQ_MAXLEN));
362 IFQ_SET_READY(&ifp->if_snd); 362 IFQ_SET_READY(&ifp->if_snd);
363 363
364 /* XXX: not yet tx checksum */ 364 /* XXX: not yet tx checksum */
365 ifp->if_capabilities = 365 ifp->if_capabilities =
366 IFCAP_CSUM_IPv4_Rx | IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 366 IFCAP_CSUM_IPv4_Rx | IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx |
367 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 367 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx;
368 368
 369 /* 802.1Q VLAN-sized frames are supported */
 370 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU;
 371
369 octeon_gmx_set_mac_addr(sc->sc_gmx_port, enaddr); 372 octeon_gmx_set_mac_addr(sc->sc_gmx_port, enaddr);
370 octeon_gmx_set_filter(sc->sc_gmx_port); 373 octeon_gmx_set_filter(sc->sc_gmx_port);
371 374
372 if_attach(ifp); 375 if_attach(ifp);
373 ether_ifattach(ifp, enaddr); 376 ether_ifattach(ifp, enaddr);
374 377
375 /* XXX */ 378 /* XXX */
376 sc->sc_rate_recv_check_link_cap.tv_sec = 1; 379 sc->sc_rate_recv_check_link_cap.tv_sec = 1;
377 sc->sc_rate_recv_check_jumbo_cap.tv_sec = 1; 380 sc->sc_rate_recv_check_jumbo_cap.tv_sec = 1;
378 sc->sc_rate_recv_check_code_cap.tv_sec = 1; 381 sc->sc_rate_recv_check_code_cap.tv_sec = 1;
379 sc->sc_rate_recv_fixup_odd_nibble_short_cap.tv_sec = 1; 382 sc->sc_rate_recv_fixup_odd_nibble_short_cap.tv_sec = 1;
380 sc->sc_rate_recv_fixup_odd_nibble_preamble_cap.tv_sec = 1; 383 sc->sc_rate_recv_fixup_odd_nibble_preamble_cap.tv_sec = 1;
381 sc->sc_rate_recv_fixup_odd_nibble_crc_cap.tv_sec = 1; 384 sc->sc_rate_recv_fixup_odd_nibble_crc_cap.tv_sec = 1;
382#ifdef OCTEON_ETH_DEBUG 385#ifdef OCTEON_ETH_DEBUG
383 sc->sc_rate_recv_fixup_odd_nibble_addr_cap.tv_sec = 1; 386 sc->sc_rate_recv_fixup_odd_nibble_addr_cap.tv_sec = 1;
384#endif 387#endif
385 /* XXX */ 388 /* XXX */
386 389
387#if 1 390#if 1
388 octeon_eth_buf_init(sc); 391 octeon_eth_buf_init(sc);
389#endif 392#endif
390 393
391 if (octeon_eth_pow_recv_ih == NULL) 394 if (octeon_eth_pow_recv_ih == NULL)
392 octeon_eth_pow_recv_ih = octeon_pow_intr_establish(OCTEON_POW_GROUP_PIP, 395 octeon_eth_pow_recv_ih = octeon_pow_intr_establish(OCTEON_POW_GROUP_PIP,
393 IPL_NET, octeon_eth_recv_intr, NULL, NULL); 396 IPL_NET, octeon_eth_recv_intr, NULL, NULL);
394 397
395 OCTEON_EVCNT_ATTACH_EVCNTS(sc, octeon_evcnt_entries, 398 OCTEON_EVCNT_ATTACH_EVCNTS(sc, octeon_evcnt_entries,
396 device_xname(sc->sc_dev)); 399 device_xname(sc->sc_dev));
397} 400}
398 401
399/* ---- submodules */ 402/* ---- submodules */
400 403
401/* XXX */ 404/* XXX */
402static void 405static void
403octeon_eth_pip_init(struct octeon_eth_softc *sc) 406octeon_eth_pip_init(struct octeon_eth_softc *sc)
404{ 407{
405 struct octeon_pip_attach_args pip_aa; 408 struct octeon_pip_attach_args pip_aa;
406 409
407 pip_aa.aa_port = sc->sc_port; 410 pip_aa.aa_port = sc->sc_port;
408 pip_aa.aa_regt = sc->sc_regt; 411 pip_aa.aa_regt = sc->sc_regt;
409 pip_aa.aa_tag_type = POW_TAG_TYPE_ORDERED/* XXX */; 412 pip_aa.aa_tag_type = POW_TAG_TYPE_ORDERED/* XXX */;
410 pip_aa.aa_receive_group = OCTEON_POW_GROUP_PIP; 413 pip_aa.aa_receive_group = OCTEON_POW_GROUP_PIP;
411 pip_aa.aa_ip_offset = sc->sc_ip_offset; 414 pip_aa.aa_ip_offset = sc->sc_ip_offset;
412 octeon_pip_init(&pip_aa, &sc->sc_pip); 415 octeon_pip_init(&pip_aa, &sc->sc_pip);
413} 416}
414 417
415/* XXX */ 418/* XXX */
416static void 419static void
417octeon_eth_ipd_init(struct octeon_eth_softc *sc) 420octeon_eth_ipd_init(struct octeon_eth_softc *sc)
418{ 421{
419 struct octeon_ipd_attach_args ipd_aa; 422 struct octeon_ipd_attach_args ipd_aa;
420 423
421 ipd_aa.aa_port = sc->sc_port; 424 ipd_aa.aa_port = sc->sc_port;
422 ipd_aa.aa_regt = sc->sc_regt; 425 ipd_aa.aa_regt = sc->sc_regt;
423 ipd_aa.aa_first_mbuff_skip = 184/* XXX */; 426 ipd_aa.aa_first_mbuff_skip = 184/* XXX */;
424 ipd_aa.aa_not_first_mbuff_skip = 0/* XXX */; 427 ipd_aa.aa_not_first_mbuff_skip = 0/* XXX */;
425 octeon_ipd_init(&ipd_aa, &sc->sc_ipd); 428 octeon_ipd_init(&ipd_aa, &sc->sc_ipd);
426} 429}
427 430
428/* XXX */ 431/* XXX */
429static void 432static void
430octeon_eth_pko_init(struct octeon_eth_softc *sc) 433octeon_eth_pko_init(struct octeon_eth_softc *sc)
431{ 434{
432 struct octeon_pko_attach_args pko_aa; 435 struct octeon_pko_attach_args pko_aa;
433 436
434 pko_aa.aa_port = sc->sc_port; 437 pko_aa.aa_port = sc->sc_port;
435 pko_aa.aa_regt = sc->sc_regt; 438 pko_aa.aa_regt = sc->sc_regt;
436 pko_aa.aa_cmdptr = &sc->sc_cmdptr; 439 pko_aa.aa_cmdptr = &sc->sc_cmdptr;
437 pko_aa.aa_cmd_buf_pool = OCTEON_POOL_NO_CMD; 440 pko_aa.aa_cmd_buf_pool = OCTEON_POOL_NO_CMD;
438 pko_aa.aa_cmd_buf_size = OCTEON_POOL_NWORDS_CMD; 441 pko_aa.aa_cmd_buf_size = OCTEON_POOL_NWORDS_CMD;
439 octeon_pko_init(&pko_aa, &sc->sc_pko); 442 octeon_pko_init(&pko_aa, &sc->sc_pko);
440} 443}
441 444
442/* XXX */ 445/* XXX */
443static void 446static void
444octeon_eth_asx_init(struct octeon_eth_softc *sc) 447octeon_eth_asx_init(struct octeon_eth_softc *sc)
445{ 448{
446 struct octeon_asx_attach_args asx_aa; 449 struct octeon_asx_attach_args asx_aa;
447 450
448 asx_aa.aa_port = sc->sc_port; 451 asx_aa.aa_port = sc->sc_port;
449 asx_aa.aa_regt = sc->sc_regt; 452 asx_aa.aa_regt = sc->sc_regt;
450 octeon_asx_init(&asx_aa, &sc->sc_asx); 453 octeon_asx_init(&asx_aa, &sc->sc_asx);
451} 454}
452 455
453static void 456static void
454octeon_eth_smi_init(struct octeon_eth_softc *sc) 457octeon_eth_smi_init(struct octeon_eth_softc *sc)
455{ 458{
456 struct octeon_smi_attach_args smi_aa; 459 struct octeon_smi_attach_args smi_aa;
457 460
458 smi_aa.aa_port = sc->sc_port; 461 smi_aa.aa_port = sc->sc_port;
459 smi_aa.aa_regt = sc->sc_regt; 462 smi_aa.aa_regt = sc->sc_regt;
460 octeon_smi_init(&smi_aa, &sc->sc_smi); 463 octeon_smi_init(&smi_aa, &sc->sc_smi);
461 octeon_smi_set_clock(sc->sc_smi, 0x1464ULL); /* XXX */ 464 octeon_smi_set_clock(sc->sc_smi, 0x1464ULL); /* XXX */
462} 465}
463 466
464/* ---- XXX */ 467/* ---- XXX */
465 468
466#define ADDR2UINT64(u, a) \ 469#define ADDR2UINT64(u, a) \
467 do { \ 470 do { \
468 u = \ 471 u = \
469 (((uint64_t)a[0] << 40) | ((uint64_t)a[1] << 32) | \ 472 (((uint64_t)a[0] << 40) | ((uint64_t)a[1] << 32) | \
470 ((uint64_t)a[2] << 24) | ((uint64_t)a[3] << 16) | \ 473 ((uint64_t)a[2] << 24) | ((uint64_t)a[3] << 16) | \
471 ((uint64_t)a[4] << 8) | ((uint64_t)a[5] << 0)); \ 474 ((uint64_t)a[4] << 8) | ((uint64_t)a[5] << 0)); \
472 } while (0) 475 } while (0)
473#define UINT642ADDR(a, u) \ 476#define UINT642ADDR(a, u) \
474 do { \ 477 do { \
475 a[0] = (uint8_t)((u) >> 40); a[1] = (uint8_t)((u) >> 32); \ 478 a[0] = (uint8_t)((u) >> 40); a[1] = (uint8_t)((u) >> 32); \
476 a[2] = (uint8_t)((u) >> 24); a[3] = (uint8_t)((u) >> 16); \ 479 a[2] = (uint8_t)((u) >> 24); a[3] = (uint8_t)((u) >> 16); \
477 a[4] = (uint8_t)((u) >> 8); a[5] = (uint8_t)((u) >> 0); \ 480 a[4] = (uint8_t)((u) >> 8); a[5] = (uint8_t)((u) >> 0); \
478 } while (0) 481 } while (0)
479 482
480static void 483static void
481octeon_eth_board_mac_addr(uint8_t *enaddr, size_t size, struct octeon_eth_softc *sc) 484octeon_eth_board_mac_addr(uint8_t *enaddr, size_t size, struct octeon_eth_softc *sc)
482{ 485{
483 prop_dictionary_t dict; 486 prop_dictionary_t dict;
484 prop_data_t ea; 487 prop_data_t ea;
485 488
486 dict = device_properties(sc->sc_dev); 489 dict = device_properties(sc->sc_dev);
487 KASSERT(dict != NULL); 490 KASSERT(dict != NULL);
488 ea = prop_dictionary_get(dict, "mac-address"); 491 ea = prop_dictionary_get(dict, "mac-address");
489 KASSERT(ea != NULL); 492 KASSERT(ea != NULL);
490 memcpy(enaddr, prop_data_data_nocopy(ea), size); 493 memcpy(enaddr, prop_data_data_nocopy(ea), size);
491} 494}
492 495
493/* ---- media */ 496/* ---- media */
494 497
495static int 498static int
496octeon_eth_mii_readreg(device_t self, int phy_addr, int reg) 499octeon_eth_mii_readreg(device_t self, int phy_addr, int reg)
497{ 500{
498 struct octeon_eth_softc *sc = device_private(self); 501 struct octeon_eth_softc *sc = device_private(self);
499 502
500 return octeon_smi_read(sc->sc_smi, phy_addr, reg); 503 return octeon_smi_read(sc->sc_smi, phy_addr, reg);
501} 504}
502 505
503static void 506static void
504octeon_eth_mii_writereg(device_t self, int phy_addr, int reg, int value) 507octeon_eth_mii_writereg(device_t self, int phy_addr, int reg, int value)
505{ 508{
506 struct octeon_eth_softc *sc = device_private(self); 509 struct octeon_eth_softc *sc = device_private(self);
507 510
508 octeon_smi_write(sc->sc_smi, phy_addr, reg, value); 511 octeon_smi_write(sc->sc_smi, phy_addr, reg, value);
509} 512}
510 513
511static void 514static void
512octeon_eth_mii_statchg(struct ifnet *ifp) 515octeon_eth_mii_statchg(struct ifnet *ifp)
513{ 516{
514 struct octeon_eth_softc *sc = ifp->if_softc; 517 struct octeon_eth_softc *sc = ifp->if_softc;
515 518
516 octeon_pko_port_enable(sc->sc_pko, 0); 519 octeon_pko_port_enable(sc->sc_pko, 0);
517 octeon_gmx_port_enable(sc->sc_gmx_port, 0); 520 octeon_gmx_port_enable(sc->sc_gmx_port, 0);
518 521
519 octeon_eth_reset(sc); 522 octeon_eth_reset(sc);
520 523
521 if (ISSET(ifp->if_flags, IFF_RUNNING)) 524 if (ISSET(ifp->if_flags, IFF_RUNNING))
522 octeon_gmx_set_filter(sc->sc_gmx_port); 525 octeon_gmx_set_filter(sc->sc_gmx_port);
523 526
524 octeon_pko_port_enable(sc->sc_pko, 1); 527 octeon_pko_port_enable(sc->sc_pko, 1);
525 octeon_gmx_port_enable(sc->sc_gmx_port, 1); 528 octeon_gmx_port_enable(sc->sc_gmx_port, 1);
526} 529}
527 530
528static int 531static int
529octeon_eth_mediainit(struct octeon_eth_softc *sc) 532octeon_eth_mediainit(struct octeon_eth_softc *sc)
530{ 533{
531 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 534 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
532 prop_object_t phy; 535 prop_object_t phy;
533 536
534 sc->sc_mii.mii_ifp = ifp; 537 sc->sc_mii.mii_ifp = ifp;
535 sc->sc_mii.mii_readreg = octeon_eth_mii_readreg; 538 sc->sc_mii.mii_readreg = octeon_eth_mii_readreg;
536 sc->sc_mii.mii_writereg = octeon_eth_mii_writereg; 539 sc->sc_mii.mii_writereg = octeon_eth_mii_writereg;
537 sc->sc_mii.mii_statchg = octeon_eth_mii_statchg; 540 sc->sc_mii.mii_statchg = octeon_eth_mii_statchg;
538 ifmedia_init(&sc->sc_mii.mii_media, 0, octeon_eth_mediachange, 541 ifmedia_init(&sc->sc_mii.mii_media, 0, octeon_eth_mediachange,
539 octeon_eth_mediastatus); 542 octeon_eth_mediastatus);
540 543
541 phy = prop_dictionary_get(device_properties(sc->sc_dev), "phy-addr"); 544 phy = prop_dictionary_get(device_properties(sc->sc_dev), "phy-addr");
542 KASSERT(phy != NULL); 545 KASSERT(phy != NULL);
543 546
544 mii_attach(sc->sc_dev, &sc->sc_mii, 547 mii_attach(sc->sc_dev, &sc->sc_mii,
545 0xffffffff, prop_number_integer_value(phy), 548 0xffffffff, prop_number_integer_value(phy),
546 MII_OFFSET_ANY, MIIF_DOPAUSE); 549 MII_OFFSET_ANY, MIIF_DOPAUSE);
547 550
548 /* XXX XXX XXX */ 551 /* XXX XXX XXX */
549 if (LIST_FIRST(&sc->sc_mii.mii_phys) != NULL) { 552 if (LIST_FIRST(&sc->sc_mii.mii_phys) != NULL) {
550 /* XXX XXX XXX */ 553 /* XXX XXX XXX */
551 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 554 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO);
552 /* XXX XXX XXX */ 555 /* XXX XXX XXX */
553 } else { 556 } else {
554 /* XXX XXX XXX */ 557 /* XXX XXX XXX */
555 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_NONE, 558 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_NONE,
556 MII_MEDIA_NONE, NULL); 559 MII_MEDIA_NONE, NULL);
557 /* XXX XXX XXX */ 560 /* XXX XXX XXX */
558 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_NONE); 561 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_NONE);
559 /* XXX XXX XXX */ 562 /* XXX XXX XXX */
560 } 563 }
561 /* XXX XXX XXX */ 564 /* XXX XXX XXX */
562 565
563 return 0; 566 return 0;
564} 567}
565 568
566static void 569static void
567octeon_eth_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 570octeon_eth_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
568{ 571{
569 struct octeon_eth_softc *sc = ifp->if_softc; 572 struct octeon_eth_softc *sc = ifp->if_softc;
570 573
571 mii_pollstat(&sc->sc_mii); 574 mii_pollstat(&sc->sc_mii);
572 575
573 ifmr->ifm_status = sc->sc_mii.mii_media_status; 576 ifmr->ifm_status = sc->sc_mii.mii_media_status;
574 ifmr->ifm_active = sc->sc_mii.mii_media_active; 577 ifmr->ifm_active = sc->sc_mii.mii_media_active;
575 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 578 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) |
576 sc->sc_gmx_port->sc_port_flowflags; 579 sc->sc_gmx_port->sc_port_flowflags;
577} 580}
578 581
579static int 582static int
580octeon_eth_mediachange(struct ifnet *ifp) 583octeon_eth_mediachange(struct ifnet *ifp)
581{ 584{
582 struct octeon_eth_softc *sc = ifp->if_softc; 585 struct octeon_eth_softc *sc = ifp->if_softc;
583 586
584 mii_mediachg(&sc->sc_mii); 587 mii_mediachg(&sc->sc_mii);
585 588
586 return 0; 589 return 0;
587} 590}
588 591
589/* ---- send buffer garbage collection */ 592/* ---- send buffer garbage collection */
590 593
591static inline void 594static inline void
592octeon_eth_send_queue_flush_prefetch(struct octeon_eth_softc *sc) 595octeon_eth_send_queue_flush_prefetch(struct octeon_eth_softc *sc)
593{ 596{
594 OCTEON_ETH_KASSERT(sc->sc_prefetch == 0); 597 OCTEON_ETH_KASSERT(sc->sc_prefetch == 0);
595 octeon_fau_op_inc_fetch_8(&sc->sc_fau_done, 0); 598 octeon_fau_op_inc_fetch_8(&sc->sc_fau_done, 0);
596 sc->sc_prefetch = 1; 599 sc->sc_prefetch = 1;
597} 600}
598 601
599static inline void 602static inline void
600octeon_eth_send_queue_flush_fetch(struct octeon_eth_softc *sc) 603octeon_eth_send_queue_flush_fetch(struct octeon_eth_softc *sc)
601{ 604{
602#ifndef OCTEON_ETH_DEBUG 605#ifndef OCTEON_ETH_DEBUG
603 if (!sc->sc_prefetch) 606 if (!sc->sc_prefetch)
604 return; 607 return;
605#endif 608#endif
606 OCTEON_ETH_KASSERT(sc->sc_prefetch == 1); 609 OCTEON_ETH_KASSERT(sc->sc_prefetch == 1);
607 sc->sc_hard_done_cnt = octeon_fau_op_inc_read_8(&sc->sc_fau_done); 610 sc->sc_hard_done_cnt = octeon_fau_op_inc_read_8(&sc->sc_fau_done);
608 OCTEON_ETH_KASSERT(sc->sc_hard_done_cnt <= 0); 611 OCTEON_ETH_KASSERT(sc->sc_hard_done_cnt <= 0);
609 sc->sc_prefetch = 0; 612 sc->sc_prefetch = 0;
610} 613}
611 614
612static inline void 615static inline void
613octeon_eth_send_queue_flush(struct octeon_eth_softc *sc) 616octeon_eth_send_queue_flush(struct octeon_eth_softc *sc)
614{ 617{
615 const int64_t sent_count = sc->sc_hard_done_cnt; 618 const int64_t sent_count = sc->sc_hard_done_cnt;
616 int i; 619 int i;
617 620
618 OCTEON_ETH_KASSERT(sc->sc_flush == 0); 621 OCTEON_ETH_KASSERT(sc->sc_flush == 0);
619 OCTEON_ETH_KASSERT(sent_count <= 0); 622 OCTEON_ETH_KASSERT(sent_count <= 0);
620 623
621 for (i = 0; i < 0 - sent_count; i++) { 624 for (i = 0; i < 0 - sent_count; i++) {
622 struct mbuf *m; 625 struct mbuf *m;
623 uint64_t *gbuf; 626 uint64_t *gbuf;
624 627
625 octeon_eth_send_queue_del(sc, &m, &gbuf); 628 octeon_eth_send_queue_del(sc, &m, &gbuf);
626 629
627 octeon_fpa_buf_put(octeon_eth_fb_sg, gbuf); 630 octeon_fpa_buf_put(octeon_eth_fb_sg, gbuf);
628 OCTEON_EVCNT_INC(sc, txbufgbput); 631 OCTEON_EVCNT_INC(sc, txbufgbput);
629 632
630 m_freem(m); 633 m_freem(m);
631 } 634 }
632 635
633 octeon_fau_op_inc_fetch_8(&sc->sc_fau_done, i); 636 octeon_fau_op_inc_fetch_8(&sc->sc_fau_done, i);
634 sc->sc_flush = i; 637 sc->sc_flush = i;
635} 638}
636 639
637static inline void 640static inline void
638octeon_eth_send_queue_flush_sync(struct octeon_eth_softc *sc) 641octeon_eth_send_queue_flush_sync(struct octeon_eth_softc *sc)
639{ 642{
640 if (sc->sc_flush == 0) 643 if (sc->sc_flush == 0)
641 return; 644 return;
642 645
643 OCTEON_ETH_KASSERT(sc->sc_flush > 0); 646 OCTEON_ETH_KASSERT(sc->sc_flush > 0);
644 647
645 /* XXX XXX XXX */ 648 /* XXX XXX XXX */
646 octeon_fau_op_inc_read_8(&sc->sc_fau_done); 649 octeon_fau_op_inc_read_8(&sc->sc_fau_done);
647 sc->sc_soft_req_cnt -= sc->sc_flush; 650 sc->sc_soft_req_cnt -= sc->sc_flush;
648 OCTEON_ETH_KASSERT(sc->sc_soft_req_cnt >= 0); 651 OCTEON_ETH_KASSERT(sc->sc_soft_req_cnt >= 0);
649 /* XXX XXX XXX */ 652 /* XXX XXX XXX */
650 653
651 sc->sc_flush = 0; 654 sc->sc_flush = 0;
652} 655}
653 656
654static inline int 657static inline int
655octeon_eth_send_queue_is_full(struct octeon_eth_softc *sc) 658octeon_eth_send_queue_is_full(struct octeon_eth_softc *sc)
656{ 659{
657#ifdef OCTEON_ETH_SEND_QUEUE_CHECK 660#ifdef OCTEON_ETH_SEND_QUEUE_CHECK
658 int64_t nofree_cnt; 661 int64_t nofree_cnt;
659 662
660 nofree_cnt = sc->sc_soft_req_cnt + sc->sc_hard_done_cnt;  663 nofree_cnt = sc->sc_soft_req_cnt + sc->sc_hard_done_cnt;
661 664
662 if (__predict_false(nofree_cnt == GATHER_QUEUE_SIZE - 1)) { 665 if (__predict_false(nofree_cnt == GATHER_QUEUE_SIZE - 1)) {
663 octeon_eth_send_queue_flush(sc); 666 octeon_eth_send_queue_flush(sc);
664 OCTEON_EVCNT_INC(sc, txerrgbuf); 667 OCTEON_EVCNT_INC(sc, txerrgbuf);
665 octeon_eth_send_queue_flush_sync(sc); 668 octeon_eth_send_queue_flush_sync(sc);
666 return 1; 669 return 1;
667 } 670 }
668 671
669#endif 672#endif
670 return 0; 673 return 0;
671} 674}
672 675
673/* 676/*
674 * (Ab)use m_nextpkt and m_paddr to maintain mbuf chain and pointer to gather 677 * (Ab)use m_nextpkt and m_paddr to maintain mbuf chain and pointer to gather
675 * buffer. Other mbuf members may be used by m_freem(), so don't touch them! 678 * buffer. Other mbuf members may be used by m_freem(), so don't touch them!
676 */ 679 */
677 680
678struct _send_queue_entry { 681struct _send_queue_entry {
679 union { 682 union {
680 struct mbuf _sqe_s_mbuf; 683 struct mbuf _sqe_s_mbuf;
681 struct { 684 struct {
682 char _sqe_s_entry_pad[offsetof(struct mbuf, m_nextpkt)]; 685 char _sqe_s_entry_pad[offsetof(struct mbuf, m_nextpkt)];
683 SIMPLEQ_ENTRY(_send_queue_entry) _sqe_s_entry_entry; 686 SIMPLEQ_ENTRY(_send_queue_entry) _sqe_s_entry_entry;
684 } _sqe_s_entry; 687 } _sqe_s_entry;
685 struct { 688 struct {
686 char _sqe_s_gbuf_pad[offsetof(struct mbuf, m_paddr)]; 689 char _sqe_s_gbuf_pad[offsetof(struct mbuf, m_paddr)];
687 uint64_t *_sqe_s_gbuf_gbuf; 690 uint64_t *_sqe_s_gbuf_gbuf;
688 } _sqe_s_gbuf; 691 } _sqe_s_gbuf;
689 } _sqe_u; 692 } _sqe_u;
690#define _sqe_entry _sqe_u._sqe_s_entry._sqe_s_entry_entry 693#define _sqe_entry _sqe_u._sqe_s_entry._sqe_s_entry_entry
691#define _sqe_gbuf _sqe_u._sqe_s_gbuf._sqe_s_gbuf_gbuf 694#define _sqe_gbuf _sqe_u._sqe_s_gbuf._sqe_s_gbuf_gbuf
692}; 695};
693 696
694static inline void 697static inline void
695octeon_eth_send_queue_add(struct octeon_eth_softc *sc, struct mbuf *m, 698octeon_eth_send_queue_add(struct octeon_eth_softc *sc, struct mbuf *m,
696 uint64_t *gbuf) 699 uint64_t *gbuf)
697{ 700{
698 struct _send_queue_entry *sqe = (struct _send_queue_entry *)m; 701 struct _send_queue_entry *sqe = (struct _send_queue_entry *)m;
699 702
700 sqe->_sqe_gbuf = gbuf; 703 sqe->_sqe_gbuf = gbuf;
701 SIMPLEQ_INSERT_TAIL(&sc->sc_sendq, sqe, _sqe_entry); 704 SIMPLEQ_INSERT_TAIL(&sc->sc_sendq, sqe, _sqe_entry);
702 705
703 if ((m->m_flags & M_EXT) && m->m_ext.ext_free != NULL) 706 if ((m->m_flags & M_EXT) && m->m_ext.ext_free != NULL)
704 sc->sc_ext_callback_cnt++; 707 sc->sc_ext_callback_cnt++;
705 708
706 OCTEON_EVCNT_INC(sc, txadd); 709 OCTEON_EVCNT_INC(sc, txadd);
707} 710}
708 711
709static inline void 712static inline void
710octeon_eth_send_queue_del(struct octeon_eth_softc *sc, struct mbuf **rm, 713octeon_eth_send_queue_del(struct octeon_eth_softc *sc, struct mbuf **rm,
711 uint64_t **rgbuf) 714 uint64_t **rgbuf)
712{ 715{
713 struct _send_queue_entry *sqe; 716 struct _send_queue_entry *sqe;
714 717
715 sqe = SIMPLEQ_FIRST(&sc->sc_sendq); 718 sqe = SIMPLEQ_FIRST(&sc->sc_sendq);
716 OCTEON_ETH_KASSERT(sqe != NULL); 719 OCTEON_ETH_KASSERT(sqe != NULL);
717 SIMPLEQ_REMOVE_HEAD(&sc->sc_sendq, _sqe_entry); 720 SIMPLEQ_REMOVE_HEAD(&sc->sc_sendq, _sqe_entry);
718 721
719 *rm = (void *)sqe; 722 *rm = (void *)sqe;
720 *rgbuf = sqe->_sqe_gbuf; 723 *rgbuf = sqe->_sqe_gbuf;
721 724
722 if (((*rm)->m_flags & M_EXT) && (*rm)->m_ext.ext_free != NULL) { 725 if (((*rm)->m_flags & M_EXT) && (*rm)->m_ext.ext_free != NULL) {
723 sc->sc_ext_callback_cnt--; 726 sc->sc_ext_callback_cnt--;
724 OCTEON_ETH_KASSERT(sc->sc_ext_callback_cnt >= 0); 727 OCTEON_ETH_KASSERT(sc->sc_ext_callback_cnt >= 0);
725 } 728 }
726 729
727 OCTEON_EVCNT_INC(sc, txdel); 730 OCTEON_EVCNT_INC(sc, txdel);
728} 731}
729 732
730static inline int 733static inline int
731octeon_eth_buf_free_work(struct octeon_eth_softc *sc, uint64_t *work, 734octeon_eth_buf_free_work(struct octeon_eth_softc *sc, uint64_t *work,
732 uint64_t word2) 735 uint64_t word2)
733{ 736{
734 /* XXX when jumbo frame */ 737 /* XXX when jumbo frame */
735 if (ISSET(word2, PIP_WQE_WORD2_IP_BUFS)) { 738 if (ISSET(word2, PIP_WQE_WORD2_IP_BUFS)) {
736 paddr_t addr; 739 paddr_t addr;
737 paddr_t start_buffer; 740 paddr_t start_buffer;
738 741
739 addr = work[3] & PIP_WQE_WORD3_ADDR; 742 addr = work[3] & PIP_WQE_WORD3_ADDR;
740 start_buffer = addr & ~(2048 - 1); 743 start_buffer = addr & ~(2048 - 1);
741 744
742 octeon_fpa_buf_put_paddr(octeon_eth_fb_pkt, start_buffer); 745 octeon_fpa_buf_put_paddr(octeon_eth_fb_pkt, start_buffer);
743 OCTEON_EVCNT_INC(sc, rxbufpkput); 746 OCTEON_EVCNT_INC(sc, rxbufpkput);
744 } 747 }
745 748
746 octeon_fpa_buf_put(octeon_eth_fb_wqe, work); 749 octeon_fpa_buf_put(octeon_eth_fb_wqe, work);
747 OCTEON_EVCNT_INC(sc, rxbufwqput); 750 OCTEON_EVCNT_INC(sc, rxbufwqput);
748 751
749 return 0; 752 return 0;
750} 753}
751 754
752static inline void 755static inline void
753octeon_eth_buf_ext_free_m(struct mbuf *m, void *buf, size_t size, void *arg) 756octeon_eth_buf_ext_free_m(struct mbuf *m, void *buf, size_t size, void *arg)
754{ 757{
755 uint64_t *work = (void *)arg; 758 uint64_t *work = (void *)arg;
756#ifdef OCTEON_ETH_DEBUG 759#ifdef OCTEON_ETH_DEBUG
757 struct octeon_eth_softc *sc = (void *)(uintptr_t)work[0]; 760 struct octeon_eth_softc *sc = (void *)(uintptr_t)work[0];
758#endif 761#endif
759 int s = splnet(); 762 int s = splnet();
760 763
761 OCTEON_EVCNT_INC(sc, rxrs); 764 OCTEON_EVCNT_INC(sc, rxrs);
762 765
763 octeon_fpa_buf_put(octeon_eth_fb_wqe, work); 766 octeon_fpa_buf_put(octeon_eth_fb_wqe, work);
764 OCTEON_EVCNT_INC(sc, rxbufwqput); 767 OCTEON_EVCNT_INC(sc, rxbufwqput);
765 768
766 OCTEON_ETH_KASSERT(m != NULL); 769 OCTEON_ETH_KASSERT(m != NULL);
767 770
768 pool_cache_put(mb_cache, m); 771 pool_cache_put(mb_cache, m);
769 772
770 splx(s); 773 splx(s);
771} 774}
772 775
773static inline void 776static inline void
774octeon_eth_buf_ext_free_ext(struct mbuf *m, void *buf, size_t size, 777octeon_eth_buf_ext_free_ext(struct mbuf *m, void *buf, size_t size,
775 void *arg) 778 void *arg)
776{ 779{
777 uint64_t *work = (void *)arg; 780 uint64_t *work = (void *)arg;
778#ifdef OCTEON_ETH_DEBUG 781#ifdef OCTEON_ETH_DEBUG
779 struct octeon_eth_softc *sc = (void *)(uintptr_t)work[0]; 782 struct octeon_eth_softc *sc = (void *)(uintptr_t)work[0];
780#endif 783#endif
781 int s = splnet(); 784 int s = splnet();
782 785
783 octeon_fpa_buf_put(octeon_eth_fb_wqe, work); 786 octeon_fpa_buf_put(octeon_eth_fb_wqe, work);
784 OCTEON_EVCNT_INC(sc, rxbufwqput); 787 OCTEON_EVCNT_INC(sc, rxbufwqput);
785 788
786 octeon_fpa_buf_put(octeon_eth_fb_pkt, buf); 789 octeon_fpa_buf_put(octeon_eth_fb_pkt, buf);
787 OCTEON_EVCNT_INC(sc, rxbufpkput); 790 OCTEON_EVCNT_INC(sc, rxbufpkput);
788 791
789 OCTEON_ETH_KASSERT(m != NULL); 792 OCTEON_ETH_KASSERT(m != NULL);
790 793
791 pool_cache_put(mb_cache, m); 794 pool_cache_put(mb_cache, m);
792 795
793 splx(s); 796 splx(s);
794} 797}
795 798
796/* ---- ifnet interfaces */ 799/* ---- ifnet interfaces */
797 800
798static int 801static int
799octeon_eth_ioctl(struct ifnet *ifp, u_long cmd, void *data) 802octeon_eth_ioctl(struct ifnet *ifp, u_long cmd, void *data)
800{ 803{
801 struct octeon_eth_softc *sc = ifp->if_softc; 804 struct octeon_eth_softc *sc = ifp->if_softc;
802 struct ifreq *ifr = (struct ifreq *)data; 805 struct ifreq *ifr = (struct ifreq *)data;
803 int s, error; 806 int s, error;
804 807
805 s = splnet(); 808 s = splnet();
806 switch (cmd) { 809 switch (cmd) {
807 case SIOCSIFMEDIA: 810 case SIOCSIFMEDIA:
808 /* Flow control requires full-duplex mode. */ 811 /* Flow control requires full-duplex mode. */
809 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 812 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO ||
810 (ifr->ifr_media & IFM_FDX) == 0) { 813 (ifr->ifr_media & IFM_FDX) == 0) {
811 ifr->ifr_media &= ~IFM_ETH_FMASK; 814 ifr->ifr_media &= ~IFM_ETH_FMASK;
812 } 815 }
813 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 816 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) {
814 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 817 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) {
815 ifr->ifr_media |= 818 ifr->ifr_media |=
816 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 819 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
817 } 820 }
818 sc->sc_gmx_port->sc_port_flowflags =  821 sc->sc_gmx_port->sc_port_flowflags =
819 ifr->ifr_media & IFM_ETH_FMASK; 822 ifr->ifr_media & IFM_ETH_FMASK;
820 } 823 }
821 /* FALLTHROUGH */ 824 /* FALLTHROUGH */
822 case SIOCGIFMEDIA: 825 case SIOCGIFMEDIA:
823 /* XXX: Flow contorol */ 826 /* XXX: Flow contorol */
824 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 827 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
825 break; 828 break;
826 default: 829 default:
827 error = ether_ioctl(ifp, cmd, data); 830 error = ether_ioctl(ifp, cmd, data);
828 if (error == ENETRESET) { 831 if (error == ENETRESET) {
829 /* 832 /*
830 * Multicast list has changed; set the hardware filter 833 * Multicast list has changed; set the hardware filter
831 * accordingly. 834 * accordingly.
832 */ 835 */
833 if (ISSET(ifp->if_flags, IFF_RUNNING)) 836 if (ISSET(ifp->if_flags, IFF_RUNNING))
834 octeon_gmx_set_filter(sc->sc_gmx_port); 837 octeon_gmx_set_filter(sc->sc_gmx_port);
835 error = 0; 838 error = 0;
836 } 839 }
837 break; 840 break;
838 } 841 }
839 octeon_eth_start(ifp); 842 octeon_eth_start(ifp);
840 splx(s); 843 splx(s);
841 844
842 return (error); 845 return (error);
843} 846}
844 847
845/* ---- send (output) */ 848/* ---- send (output) */
846 849
847static inline uint64_t 850static inline uint64_t
848octeon_eth_send_makecmd_w0(uint64_t fau0, uint64_t fau1, size_t len, int segs) 851octeon_eth_send_makecmd_w0(uint64_t fau0, uint64_t fau1, size_t len, int segs)
849{ 852{
850 return octeon_pko_cmd_word0( 853 return octeon_pko_cmd_word0(
851 OCT_FAU_OP_SIZE_64, /* sz1 */ 854 OCT_FAU_OP_SIZE_64, /* sz1 */
852 OCT_FAU_OP_SIZE_64, /* sz0 */ 855 OCT_FAU_OP_SIZE_64, /* sz0 */
853 1, fau1, 1, fau0, /* s1, reg1, s0, reg0 */ 856 1, fau1, 1, fau0, /* s1, reg1, s0, reg0 */
854 0, /* le */ 857 0, /* le */
855 octeon_eth_param_pko_cmd_w0_n2, /* n2 */ 858 octeon_eth_param_pko_cmd_w0_n2, /* n2 */
856 1, 0, /* q, r */ 859 1, 0, /* q, r */
857 (segs == 1) ? 0 : 1, /* g */ 860 (segs == 1) ? 0 : 1, /* g */
858 0, 0, 1, /* ipoffp1, ii, df */ 861 0, 0, 1, /* ipoffp1, ii, df */
859 segs, (int)len); /* segs, totalbytes */ 862 segs, (int)len); /* segs, totalbytes */
860} 863}
861 864
862static inline uint64_t  865static inline uint64_t
863octeon_eth_send_makecmd_w1(int size, paddr_t addr) 866octeon_eth_send_makecmd_w1(int size, paddr_t addr)
864{ 867{
865 return octeon_pko_cmd_word1( 868 return octeon_pko_cmd_word1(
866 0, 0, /* i, back */ 869 0, 0, /* i, back */
867 FPA_GATHER_BUFFER_POOL, /* pool */ 870 FPA_GATHER_BUFFER_POOL, /* pool */
868 size, addr); /* size, addr */ 871 size, addr); /* size, addr */
869} 872}
870 873
871static inline int 874static inline int
872octeon_eth_send_makecmd_gbuf(struct octeon_eth_softc *sc, struct mbuf *m0, 875octeon_eth_send_makecmd_gbuf(struct octeon_eth_softc *sc, struct mbuf *m0,
873 uint64_t *gbuf, int *rsegs) 876 uint64_t *gbuf, int *rsegs)
874{ 877{
875 struct mbuf *m; 878 struct mbuf *m;
876 int segs = 0; 879 int segs = 0;
877 uintptr_t laddr, rlen, nlen; 880 uintptr_t laddr, rlen, nlen;
878 881
879 for (m = m0; m != NULL; m = m->m_next) { 882 for (m = m0; m != NULL; m = m->m_next) {
880 883
881 if (__predict_false(m->m_len == 0)) 884 if (__predict_false(m->m_len == 0))
882 continue; 885 continue;
883 886
884#if 0  887#if 0
885 OCTEON_ETH_KASSERT(((uint32_t)m->m_data & (PAGE_SIZE - 1)) 888 OCTEON_ETH_KASSERT(((uint32_t)m->m_data & (PAGE_SIZE - 1))
886 == (kvtophys((vaddr_t)m->m_data) & (PAGE_SIZE - 1))); 889 == (kvtophys((vaddr_t)m->m_data) & (PAGE_SIZE - 1)));
887#endif 890#endif
888 891
889 /* 892 /*
890 * aligned 4k 893 * aligned 4k
891 */ 894 */
892 laddr = (uintptr_t)m->m_data & (PAGE_SIZE - 1); 895 laddr = (uintptr_t)m->m_data & (PAGE_SIZE - 1);
893 896
894 if (laddr + m->m_len > PAGE_SIZE) { 897 if (laddr + m->m_len > PAGE_SIZE) {
895 /* XXX XXX XXX */ 898 /* XXX XXX XXX */
896 rlen = PAGE_SIZE - laddr; 899 rlen = PAGE_SIZE - laddr;
897 nlen = m->m_len - rlen; 900 nlen = m->m_len - rlen;
898 *(gbuf + segs) = octeon_eth_send_makecmd_w1(rlen, 901 *(gbuf + segs) = octeon_eth_send_makecmd_w1(rlen,
899 kvtophys((vaddr_t)m->m_data)); 902 kvtophys((vaddr_t)m->m_data));
900 segs++; 903 segs++;
901 if (segs > 63) { 904 if (segs > 63) {
902 return 1; 905 return 1;
903 } 906 }
904 /* XXX XXX XXX */ 907 /* XXX XXX XXX */
905 } else { 908 } else {
906 rlen = 0; 909 rlen = 0;
907 nlen = m->m_len; 910 nlen = m->m_len;
908 } 911 }
909 912
910 *(gbuf + segs) = octeon_eth_send_makecmd_w1(nlen, 913 *(gbuf + segs) = octeon_eth_send_makecmd_w1(nlen,
911 kvtophys((vaddr_t)(m->m_data + rlen))); 914 kvtophys((vaddr_t)(m->m_data + rlen)));
912 segs++; 915 segs++;
913 if (segs > 63) { 916 if (segs > 63) {
914 return 1; 917 return 1;
915 } 918 }
916 } 919 }
917 920
918 OCTEON_ETH_KASSERT(m == NULL); 921 OCTEON_ETH_KASSERT(m == NULL);
919 922
920 *rsegs = segs; 923 *rsegs = segs;
921 924
922 return 0; 925 return 0;
923} 926}
924 927
925static inline int 928static inline int
926octeon_eth_send_makecmd(struct octeon_eth_softc *sc, struct mbuf *m, 929octeon_eth_send_makecmd(struct octeon_eth_softc *sc, struct mbuf *m,
927 uint64_t *gbuf, uint64_t *rpko_cmd_w0, uint64_t *rpko_cmd_w1) 930 uint64_t *gbuf, uint64_t *rpko_cmd_w0, uint64_t *rpko_cmd_w1)
928{ 931{
929 uint64_t pko_cmd_w0, pko_cmd_w1; 932 uint64_t pko_cmd_w0, pko_cmd_w1;
930 int segs; 933 int segs;
931 int result = 0; 934 int result = 0;
932 935
933 if (octeon_eth_send_makecmd_gbuf(sc, m, gbuf, &segs)) { 936 if (octeon_eth_send_makecmd_gbuf(sc, m, gbuf, &segs)) {
934 log(LOG_WARNING, "%s: there are a lot of number of segments" 937 log(LOG_WARNING, "%s: there are a lot of number of segments"
935 " of transmission data", device_xname(sc->sc_dev)); 938 " of transmission data", device_xname(sc->sc_dev));
936 result = 1; 939 result = 1;
937 goto done; 940 goto done;
938 } 941 }
939 942
940 /* 943 /*
941 * segs == 1 -> link mode (single continuous buffer) 944 * segs == 1 -> link mode (single continuous buffer)
942 * WORD1[size] is number of bytes pointed by segment 945 * WORD1[size] is number of bytes pointed by segment
943 * 946 *
944 * segs > 1 -> gather mode (scatter-gather buffer) 947 * segs > 1 -> gather mode (scatter-gather buffer)
945 * WORD1[size] is number of segments 948 * WORD1[size] is number of segments
946 */ 949 */
947 pko_cmd_w0 = octeon_eth_send_makecmd_w0(sc->sc_fau_done.fd_regno, 950 pko_cmd_w0 = octeon_eth_send_makecmd_w0(sc->sc_fau_done.fd_regno,
948 0, m->m_pkthdr.len, segs); 951 0, m->m_pkthdr.len, segs);
949 if (segs == 1) { 952 if (segs == 1) {
950 pko_cmd_w1 = octeon_eth_send_makecmd_w1( 953 pko_cmd_w1 = octeon_eth_send_makecmd_w1(
951 m->m_pkthdr.len, kvtophys((vaddr_t)m->m_data)); 954 m->m_pkthdr.len, kvtophys((vaddr_t)m->m_data));
952 } else { 955 } else {
953#ifdef __mips_n32 956#ifdef __mips_n32
954 KASSERT(MIPS_KSEG0_P(gbuf)); 957 KASSERT(MIPS_KSEG0_P(gbuf));
955 pko_cmd_w1 = octeon_eth_send_makecmd_w1(segs, 958 pko_cmd_w1 = octeon_eth_send_makecmd_w1(segs,
956 MIPS_KSEG0_TO_PHYS(gbuf)); 959 MIPS_KSEG0_TO_PHYS(gbuf));
957#else 960#else
958 pko_cmd_w1 = octeon_eth_send_makecmd_w1(segs, 961 pko_cmd_w1 = octeon_eth_send_makecmd_w1(segs,
959 MIPS_XKPHYS_TO_PHYS(gbuf)); 962 MIPS_XKPHYS_TO_PHYS(gbuf));
960#endif 963#endif
961 } 964 }
962 965
963 *rpko_cmd_w0 = pko_cmd_w0; 966 *rpko_cmd_w0 = pko_cmd_w0;
964 *rpko_cmd_w1 = pko_cmd_w1; 967 *rpko_cmd_w1 = pko_cmd_w1;
965 968
966done: 969done:
967 return result; 970 return result;
968} 971}
969 972
970static inline int 973static inline int
971octeon_eth_send_cmd(struct octeon_eth_softc *sc, uint64_t pko_cmd_w0, 974octeon_eth_send_cmd(struct octeon_eth_softc *sc, uint64_t pko_cmd_w0,
972 uint64_t pko_cmd_w1) 975 uint64_t pko_cmd_w1)
973{ 976{
974 uint64_t *cmdptr; 977 uint64_t *cmdptr;
975 int result = 0; 978 int result = 0;
976 979
977#ifdef __mips_n32 980#ifdef __mips_n32
978 KASSERT((sc->sc_cmdptr.cmdptr & ~MIPS_PHYS_MASK) == 0); 981 KASSERT((sc->sc_cmdptr.cmdptr & ~MIPS_PHYS_MASK) == 0);
979 cmdptr = (uint64_t *)MIPS_PHYS_TO_KSEG0(sc->sc_cmdptr.cmdptr); 982 cmdptr = (uint64_t *)MIPS_PHYS_TO_KSEG0(sc->sc_cmdptr.cmdptr);
980#else 983#else
981 cmdptr = (uint64_t *)MIPS_PHYS_TO_XKPHYS_CACHED(sc->sc_cmdptr.cmdptr); 984 cmdptr = (uint64_t *)MIPS_PHYS_TO_XKPHYS_CACHED(sc->sc_cmdptr.cmdptr);
982#endif 985#endif
983 cmdptr += sc->sc_cmdptr.cmdptr_idx; 986 cmdptr += sc->sc_cmdptr.cmdptr_idx;
984 987
985 OCTEON_ETH_KASSERT(cmdptr != NULL); 988 OCTEON_ETH_KASSERT(cmdptr != NULL);
986 989
987 *cmdptr++ = pko_cmd_w0; 990 *cmdptr++ = pko_cmd_w0;
988 *cmdptr++ = pko_cmd_w1; 991 *cmdptr++ = pko_cmd_w1;
989 992
990 OCTEON_ETH_KASSERT(sc->sc_cmdptr.cmdptr_idx + 2 <= FPA_COMMAND_BUFFER_POOL_NWORDS - 1); 993 OCTEON_ETH_KASSERT(sc->sc_cmdptr.cmdptr_idx + 2 <= FPA_COMMAND_BUFFER_POOL_NWORDS - 1);
991 994
992 if (sc->sc_cmdptr.cmdptr_idx + 2 == FPA_COMMAND_BUFFER_POOL_NWORDS - 1) { 995 if (sc->sc_cmdptr.cmdptr_idx + 2 == FPA_COMMAND_BUFFER_POOL_NWORDS - 1) {
993 paddr_t buf; 996 paddr_t buf;
994 997
995 buf = octeon_fpa_buf_get_paddr(octeon_eth_fb_cmd); 998 buf = octeon_fpa_buf_get_paddr(octeon_eth_fb_cmd);
996 if (buf == 0) { 999 if (buf == 0) {
997 log(LOG_WARNING, 1000 log(LOG_WARNING,
998 "%s: can not allocate command buffer from free pool allocator\n", 1001 "%s: can not allocate command buffer from free pool allocator\n",
999 device_xname(sc->sc_dev)); 1002 device_xname(sc->sc_dev));
1000 result = 1; 1003 result = 1;
1001 goto done; 1004 goto done;
1002 } 1005 }
1003 OCTEON_EVCNT_INC(sc, txbufcbget); 1006 OCTEON_EVCNT_INC(sc, txbufcbget);
1004 *cmdptr++ = buf; 1007 *cmdptr++ = buf;
1005 sc->sc_cmdptr.cmdptr = (uint64_t)buf; 1008 sc->sc_cmdptr.cmdptr = (uint64_t)buf;
1006 sc->sc_cmdptr.cmdptr_idx = 0; 1009 sc->sc_cmdptr.cmdptr_idx = 0;
1007 } else { 1010 } else {
1008 sc->sc_cmdptr.cmdptr_idx += 2; 1011 sc->sc_cmdptr.cmdptr_idx += 2;
1009 } 1012 }
1010 1013
1011 octeon_pko_op_doorbell_write(sc->sc_port, sc->sc_port, 2); 1014 octeon_pko_op_doorbell_write(sc->sc_port, sc->sc_port, 2);
1012 1015
1013done: 1016done:
1014 return result; 1017 return result;
1015} 1018}
1016 1019
1017static inline int 1020static inline int
1018octeon_eth_send_buf(struct octeon_eth_softc *sc, struct mbuf *m, 1021octeon_eth_send_buf(struct octeon_eth_softc *sc, struct mbuf *m,
1019 uint64_t *gbuf) 1022 uint64_t *gbuf)
1020{ 1023{
1021 int result = 0, error; 1024 int result = 0, error;
1022 uint64_t pko_cmd_w0, pko_cmd_w1; 1025 uint64_t pko_cmd_w0, pko_cmd_w1;
1023 1026
1024 error = octeon_eth_send_makecmd(sc, m, gbuf, &pko_cmd_w0, &pko_cmd_w1); 1027 error = octeon_eth_send_makecmd(sc, m, gbuf, &pko_cmd_w0, &pko_cmd_w1);
1025 if (error != 0) { 1028 if (error != 0) {
1026 /* already logging */ 1029 /* already logging */
1027 OCTEON_EVCNT_INC(sc, txerrmkcmd); 1030 OCTEON_EVCNT_INC(sc, txerrmkcmd);
1028 result = error; 1031 result = error;
1029 goto done; 1032 goto done;
1030 } 1033 }
1031 1034
1032 error = octeon_eth_send_cmd(sc, pko_cmd_w0, pko_cmd_w1); 1035 error = octeon_eth_send_cmd(sc, pko_cmd_w0, pko_cmd_w1);
1033 if (error != 0) { 1036 if (error != 0) {
1034 /* already logging */ 1037 /* already logging */
1035 OCTEON_EVCNT_INC(sc, txerrcmd); 1038 OCTEON_EVCNT_INC(sc, txerrcmd);
1036 result = error; 1039 result = error;
1037 } 1040 }
1038 1041
1039done: 1042done:
1040 return result; 1043 return result;
1041} 1044}
1042 1045
1043static inline int 1046static inline int
1044octeon_eth_send(struct octeon_eth_softc *sc, struct mbuf *m) 1047octeon_eth_send(struct octeon_eth_softc *sc, struct mbuf *m)
1045{ 1048{
1046 paddr_t gaddr = 0; 1049 paddr_t gaddr = 0;
1047 uint64_t *gbuf = NULL; 1050 uint64_t *gbuf = NULL;
1048 int result = 0, error; 1051 int result = 0, error;
1049 1052
1050 OCTEON_EVCNT_INC(sc, tx); 1053 OCTEON_EVCNT_INC(sc, tx);
1051 1054
1052 gaddr = octeon_fpa_buf_get_paddr(octeon_eth_fb_sg); 1055 gaddr = octeon_fpa_buf_get_paddr(octeon_eth_fb_sg);
1053 if (gaddr == 0) { 1056 if (gaddr == 0) {
1054 log(LOG_WARNING, 1057 log(LOG_WARNING,
1055 "%s: can not allocate gather buffer from free pool allocator\n", 1058 "%s: can not allocate gather buffer from free pool allocator\n",
1056 device_xname(sc->sc_dev)); 1059 device_xname(sc->sc_dev));
1057 OCTEON_EVCNT_INC(sc, txerrgbuf); 1060 OCTEON_EVCNT_INC(sc, txerrgbuf);
1058 result = 1; 1061 result = 1;
1059 goto done; 1062 goto done;
1060 } 1063 }
1061 OCTEON_EVCNT_INC(sc, txbufgbget); 1064 OCTEON_EVCNT_INC(sc, txbufgbget);
1062 1065
1063#ifdef __mips_n32 1066#ifdef __mips_n32
1064 KASSERT((gaddr & ~MIPS_PHYS_MASK) == 0); 1067 KASSERT((gaddr & ~MIPS_PHYS_MASK) == 0);
1065 gbuf = (uint64_t *)(uintptr_t)MIPS_PHYS_TO_KSEG0(gaddr); 1068 gbuf = (uint64_t *)(uintptr_t)MIPS_PHYS_TO_KSEG0(gaddr);
1066#else 1069#else
1067 gbuf = (uint64_t *)(uintptr_t)MIPS_PHYS_TO_XKPHYS_CACHED(gaddr); 1070 gbuf = (uint64_t *)(uintptr_t)MIPS_PHYS_TO_XKPHYS_CACHED(gaddr);
1068#endif 1071#endif
1069 1072
1070 OCTEON_ETH_KASSERT(gbuf != NULL); 1073 OCTEON_ETH_KASSERT(gbuf != NULL);
1071 1074
1072 error = octeon_eth_send_buf(sc, m, gbuf); 1075 error = octeon_eth_send_buf(sc, m, gbuf);
1073 if (error != 0) { 1076 if (error != 0) {
1074 /* already logging */ 1077 /* already logging */
1075 octeon_fpa_buf_put_paddr(octeon_eth_fb_sg, gaddr); 1078 octeon_fpa_buf_put_paddr(octeon_eth_fb_sg, gaddr);
1076 OCTEON_EVCNT_INC(sc, txbufgbput); 1079 OCTEON_EVCNT_INC(sc, txbufgbput);
1077 result = error; 1080 result = error;
1078 goto done; 1081 goto done;
1079 } 1082 }
1080 1083
1081 octeon_eth_send_queue_add(sc, m, gbuf); 1084 octeon_eth_send_queue_add(sc, m, gbuf);
1082 1085
1083done: 1086done:
1084 return result; 1087 return result;
1085} 1088}
1086 1089
1087static void 1090static void
1088octeon_eth_start(struct ifnet *ifp) 1091octeon_eth_start(struct ifnet *ifp)
1089{ 1092{
1090 struct octeon_eth_softc *sc = ifp->if_softc; 1093 struct octeon_eth_softc *sc = ifp->if_softc;
1091 struct mbuf *m; 1094 struct mbuf *m;
1092 1095
1093 /* 1096 /*
1094 * performance tuning 1097 * performance tuning
1095 * presend iobdma request  1098 * presend iobdma request
1096 */ 1099 */
1097 octeon_eth_send_queue_flush_prefetch(sc); 1100 octeon_eth_send_queue_flush_prefetch(sc);
1098 1101
1099 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1102 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1100 goto last; 1103 goto last;
1101 1104
1102 /* XXX assume that OCTEON doesn't buffer packets */ 1105 /* XXX assume that OCTEON doesn't buffer packets */
1103 if (__predict_false(!octeon_gmx_link_status(sc->sc_gmx_port))) { 1106 if (__predict_false(!octeon_gmx_link_status(sc->sc_gmx_port))) {
1104 /* dequeue and drop them */ 1107 /* dequeue and drop them */
1105 while (1) { 1108 while (1) {
1106 IFQ_DEQUEUE(&ifp->if_snd, m); 1109 IFQ_DEQUEUE(&ifp->if_snd, m);
1107 if (m == NULL) 1110 if (m == NULL)
1108 break; 1111 break;
1109 1112
1110 m_freem(m); 1113 m_freem(m);
1111 IF_DROP(&ifp->if_snd); 1114 IF_DROP(&ifp->if_snd);
1112 OCTEON_EVCNT_INC(sc, txerrlink); 1115 OCTEON_EVCNT_INC(sc, txerrlink);
1113 } 1116 }
1114 goto last; 1117 goto last;
1115 } 1118 }
1116 1119
1117 for (;;) { 1120 for (;;) {
1118 IFQ_POLL(&ifp->if_snd, m); 1121 IFQ_POLL(&ifp->if_snd, m);
1119 if (__predict_false(m == NULL)) 1122 if (__predict_false(m == NULL))
1120 break; 1123 break;
1121 1124
1122 /* XXX XXX XXX */ 1125 /* XXX XXX XXX */
1123 octeon_eth_send_queue_flush_fetch(sc); 1126 octeon_eth_send_queue_flush_fetch(sc);
1124 1127
1125 /* 1128 /*
1126 * If no free send buffer is available, free all the sent buffer 1129 * If no free send buffer is available, free all the sent buffer
1127 * and bail out. 1130 * and bail out.
1128 */ 1131 */
1129 if (octeon_eth_send_queue_is_full(sc)) { 1132 if (octeon_eth_send_queue_is_full(sc)) {
1130 return; 1133 return;
1131 } 1134 }
1132 /* XXX XXX XXX */ 1135 /* XXX XXX XXX */
1133 1136
1134 IFQ_DEQUEUE(&ifp->if_snd, m); 1137 IFQ_DEQUEUE(&ifp->if_snd, m);
1135 1138
1136 bpf_mtap(ifp, m); 1139 bpf_mtap(ifp, m);
1137 1140
1138 /* XXX XXX XXX */ 1141 /* XXX XXX XXX */
1139 if (sc->sc_soft_req_cnt > sc->sc_soft_req_thresh) 1142 if (sc->sc_soft_req_cnt > sc->sc_soft_req_thresh)
1140 octeon_eth_send_queue_flush(sc); 1143 octeon_eth_send_queue_flush(sc);
1141 if (octeon_eth_send(sc, m)) { 1144 if (octeon_eth_send(sc, m)) {
1142 IF_DROP(&ifp->if_snd); 1145 IF_DROP(&ifp->if_snd);
1143 m_freem(m); 1146 m_freem(m);
1144 log(LOG_WARNING, 1147 log(LOG_WARNING,
1145 "%s: failed in the transmission of the packet\n", 1148 "%s: failed in the transmission of the packet\n",
1146 device_xname(sc->sc_dev)); 1149 device_xname(sc->sc_dev));
1147 OCTEON_EVCNT_INC(sc, txerr); 1150 OCTEON_EVCNT_INC(sc, txerr);
1148 } else { 1151 } else {
1149 sc->sc_soft_req_cnt++; 1152 sc->sc_soft_req_cnt++;
1150 } 1153 }
1151 if (sc->sc_flush) 1154 if (sc->sc_flush)
1152 octeon_eth_send_queue_flush_sync(sc); 1155 octeon_eth_send_queue_flush_sync(sc);
1153 /* XXX XXX XXX */ 1156 /* XXX XXX XXX */
1154 1157
1155 /* 1158 /*
1156 * send next iobdma request  1159 * send next iobdma request
1157 */ 1160 */
1158 octeon_eth_send_queue_flush_prefetch(sc); 1161 octeon_eth_send_queue_flush_prefetch(sc);
1159 } 1162 }
1160 1163
1161/* 1164/*
1162 * Don't schedule send-buffer-free callout every time - those buffers are freed 1165 * Don't schedule send-buffer-free callout every time - those buffers are freed
1163 * by "free tick". This makes some packets like NFS slower. 1166 * by "free tick". This makes some packets like NFS slower.
1164 */ 1167 */
1165#ifdef OCTEON_ETH_USENFS 1168#ifdef OCTEON_ETH_USENFS
1166 if (__predict_false(sc->sc_ext_callback_cnt > 0)) { 1169 if (__predict_false(sc->sc_ext_callback_cnt > 0)) {
1167 int timo; 1170 int timo;
1168 1171
1169 /* ??? */ 1172 /* ??? */
1170 timo = hz - (100 * sc->sc_ext_callback_cnt); 1173 timo = hz - (100 * sc->sc_ext_callback_cnt);
1171 if (timo < 10) 1174 if (timo < 10)
1172 timo = 10; 1175 timo = 10;
1173 callout_schedule(&sc->sc_tick_free_ch, timo); 1176 callout_schedule(&sc->sc_tick_free_ch, timo);
1174 } 1177 }
1175#endif 1178#endif
1176 1179
1177last: 1180last:
1178 octeon_eth_send_queue_flush_fetch(sc); 1181 octeon_eth_send_queue_flush_fetch(sc);
1179} 1182}
1180 1183
1181static void 1184static void
1182octeon_eth_watchdog(struct ifnet *ifp) 1185octeon_eth_watchdog(struct ifnet *ifp)
1183{ 1186{
1184 struct octeon_eth_softc *sc = ifp->if_softc; 1187 struct octeon_eth_softc *sc = ifp->if_softc;
1185 1188
1186 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1189 printf("%s: device timeout\n", device_xname(sc->sc_dev));
1187 1190
1188 octeon_eth_configure(sc); 1191 octeon_eth_configure(sc);
1189 1192
1190 SET(ifp->if_flags, IFF_RUNNING); 1193 SET(ifp->if_flags, IFF_RUNNING);
1191 CLR(ifp->if_flags, IFF_OACTIVE); 1194 CLR(ifp->if_flags, IFF_OACTIVE);
1192 ifp->if_timer = 0; 1195 ifp->if_timer = 0;
1193 1196
1194 octeon_eth_start(ifp); 1197 octeon_eth_start(ifp);
1195} 1198}
1196 1199
1197static int 1200static int
1198octeon_eth_init(struct ifnet *ifp) 1201octeon_eth_init(struct ifnet *ifp)
1199{ 1202{
1200 struct octeon_eth_softc *sc = ifp->if_softc; 1203 struct octeon_eth_softc *sc = ifp->if_softc;
1201 1204
1202 /* XXX don't disable commonly used parts!!! XXX */ 1205 /* XXX don't disable commonly used parts!!! XXX */
1203 if (sc->sc_init_flag == 0) { 1206 if (sc->sc_init_flag == 0) {
1204 /* Cancel any pending I/O. */ 1207 /* Cancel any pending I/O. */
1205 octeon_eth_stop(ifp, 0); 1208 octeon_eth_stop(ifp, 0);
1206 1209
1207 /* Initialize the device */ 1210 /* Initialize the device */
1208 octeon_eth_configure(sc); 1211 octeon_eth_configure(sc);
1209 1212
1210 octeon_pko_enable(sc->sc_pko); 1213 octeon_pko_enable(sc->sc_pko);
1211 octeon_ipd_enable(sc->sc_ipd); 1214 octeon_ipd_enable(sc->sc_ipd);
1212 1215
1213 sc->sc_init_flag = 1; 1216 sc->sc_init_flag = 1;
1214 } else { 1217 } else {
1215 octeon_gmx_port_enable(sc->sc_gmx_port, 1); 1218 octeon_gmx_port_enable(sc->sc_gmx_port, 1);
1216 } 1219 }
1217 octeon_eth_mediachange(ifp); 1220 octeon_eth_mediachange(ifp);
1218 1221
1219 octeon_gmx_set_filter(sc->sc_gmx_port); 1222 octeon_gmx_set_filter(sc->sc_gmx_port);
1220 1223
1221 callout_reset(&sc->sc_tick_misc_ch, hz, octeon_eth_tick_misc, sc); 1224 callout_reset(&sc->sc_tick_misc_ch, hz, octeon_eth_tick_misc, sc);
1222 callout_reset(&sc->sc_tick_free_ch, hz, octeon_eth_tick_free, sc); 1225 callout_reset(&sc->sc_tick_free_ch, hz, octeon_eth_tick_free, sc);
1223 1226
1224 SET(ifp->if_flags, IFF_RUNNING); 1227 SET(ifp->if_flags, IFF_RUNNING);
1225 CLR(ifp->if_flags, IFF_OACTIVE); 1228 CLR(ifp->if_flags, IFF_OACTIVE);
1226 1229
1227 return 0; 1230 return 0;
1228} 1231}
1229 1232
1230static void 1233static void
1231octeon_eth_stop(struct ifnet *ifp, int disable) 1234octeon_eth_stop(struct ifnet *ifp, int disable)
1232{ 1235{
1233 struct octeon_eth_softc *sc = ifp->if_softc; 1236 struct octeon_eth_softc *sc = ifp->if_softc;
1234 1237
1235 callout_stop(&sc->sc_tick_misc_ch); 1238 callout_stop(&sc->sc_tick_misc_ch);
1236 callout_stop(&sc->sc_tick_free_ch); 1239 callout_stop(&sc->sc_tick_free_ch);
1237 1240
1238 mii_down(&sc->sc_mii); 1241 mii_down(&sc->sc_mii);
1239 1242
1240 octeon_gmx_port_enable(sc->sc_gmx_port, 0); 1243 octeon_gmx_port_enable(sc->sc_gmx_port, 0);
1241 1244
1242 /* Mark the interface as down and cancel the watchdog timer. */ 1245 /* Mark the interface as down and cancel the watchdog timer. */
1243 CLR(ifp->if_flags, IFF_RUNNING | IFF_OACTIVE); 1246 CLR(ifp->if_flags, IFF_RUNNING | IFF_OACTIVE);
1244 ifp->if_timer = 0; 1247 ifp->if_timer = 0;
1245} 1248}
1246 1249
1247/* ---- misc */ 1250/* ---- misc */
1248 1251
1249#define PKO_INDEX_MASK ((1ULL << 12/* XXX */) - 1) 1252#define PKO_INDEX_MASK ((1ULL << 12/* XXX */) - 1)
1250 1253
1251static int 1254static int
1252octeon_eth_reset(struct octeon_eth_softc *sc) 1255octeon_eth_reset(struct octeon_eth_softc *sc)
1253{ 1256{
1254 octeon_gmx_reset_speed(sc->sc_gmx_port); 1257 octeon_gmx_reset_speed(sc->sc_gmx_port);
1255 octeon_gmx_reset_flowctl(sc->sc_gmx_port); 1258 octeon_gmx_reset_flowctl(sc->sc_gmx_port);
1256 octeon_gmx_reset_timing(sc->sc_gmx_port); 1259 octeon_gmx_reset_timing(sc->sc_gmx_port);
1257 1260
1258 return 0; 1261 return 0;
1259} 1262}
1260 1263
1261static int 1264static int
1262octeon_eth_configure(struct octeon_eth_softc *sc) 1265octeon_eth_configure(struct octeon_eth_softc *sc)
1263{ 1266{
1264 octeon_gmx_port_enable(sc->sc_gmx_port, 0); 1267 octeon_gmx_port_enable(sc->sc_gmx_port, 0);
1265 1268
1266 octeon_eth_reset(sc); 1269 octeon_eth_reset(sc);
1267 1270
1268 octeon_eth_configure_common(sc); 1271 octeon_eth_configure_common(sc);
1269 1272
1270 octeon_pko_port_config(sc->sc_pko); 1273 octeon_pko_port_config(sc->sc_pko);
1271 octeon_pko_port_enable(sc->sc_pko, 1); 1274 octeon_pko_port_enable(sc->sc_pko, 1);
1272 octeon_pip_port_config(sc->sc_pip); 1275 octeon_pip_port_config(sc->sc_pip);
1273 1276
1274 octeon_gmx_tx_stats_rd_clr(sc->sc_gmx_port, 1); 1277 octeon_gmx_tx_stats_rd_clr(sc->sc_gmx_port, 1);
1275 octeon_gmx_rx_stats_rd_clr(sc->sc_gmx_port, 1); 1278 octeon_gmx_rx_stats_rd_clr(sc->sc_gmx_port, 1);
1276 1279
1277 octeon_gmx_port_enable(sc->sc_gmx_port, 1); 1280 octeon_gmx_port_enable(sc->sc_gmx_port, 1);
1278 1281
1279 return 0; 1282 return 0;
1280} 1283}
1281 1284
1282static int 1285static int
1283octeon_eth_configure_common(struct octeon_eth_softc *sc) 1286octeon_eth_configure_common(struct octeon_eth_softc *sc)
1284{ 1287{
1285 static int once; 1288 static int once;
1286 1289
1287 if (once == 1) 1290 if (once == 1)
1288 return 0; 1291 return 0;
1289 once = 1; 1292 once = 1;
1290 1293
1291 octeon_ipd_config(sc->sc_ipd); 1294 octeon_ipd_config(sc->sc_ipd);
1292#ifdef OCTEON_ETH_IPD_RED 1295#ifdef OCTEON_ETH_IPD_RED
1293 octeon_ipd_red(sc->sc_ipd, RECV_QUEUE_SIZE >> 2, RECV_QUEUE_SIZE >> 3); 1296 octeon_ipd_red(sc->sc_ipd, RECV_QUEUE_SIZE >> 2, RECV_QUEUE_SIZE >> 3);
1294#endif 1297#endif
1295 octeon_pko_config(sc->sc_pko); 1298 octeon_pko_config(sc->sc_pko);
1296 1299
1297 octeon_pow_config(sc->sc_pow, OCTEON_POW_GROUP_PIP); 1300 octeon_pow_config(sc->sc_pow, OCTEON_POW_GROUP_PIP);
1298 1301
1299 return 0; 1302 return 0;
1300} 1303}
1301 1304
1302/* ---- receive (input) */ 1305/* ---- receive (input) */
1303 1306
1304static inline int 1307static inline int
1305octeon_eth_recv_mbuf(struct octeon_eth_softc *sc, uint64_t *work, 1308octeon_eth_recv_mbuf(struct octeon_eth_softc *sc, uint64_t *work,
1306 struct mbuf **rm) 1309 struct mbuf **rm)
1307{ 1310{
1308 struct mbuf *m; 1311 struct mbuf *m;
1309 void (*ext_free)(struct mbuf *, void *, size_t, void *); 1312 void (*ext_free)(struct mbuf *, void *, size_t, void *);
1310 void *ext_buf; 1313 void *ext_buf;
1311 size_t ext_size; 1314 size_t ext_size;
1312 void *data; 1315 void *data;
1313 uint64_t word1 = work[1]; 1316 uint64_t word1 = work[1];
1314 uint64_t word2 = work[2]; 1317 uint64_t word2 = work[2];
1315 uint64_t word3 = work[3]; 1318 uint64_t word3 = work[3];
1316 1319
1317 MGETHDR(m, M_NOWAIT, MT_DATA); 1320 MGETHDR(m, M_NOWAIT, MT_DATA);
1318 if (m == NULL) 1321 if (m == NULL)
1319 return 1; 1322 return 1;
1320 OCTEON_ETH_KASSERT(m != NULL); 1323 OCTEON_ETH_KASSERT(m != NULL);
1321 1324
1322 if ((word2 & PIP_WQE_WORD2_IP_BUFS) == 0) { 1325 if ((word2 & PIP_WQE_WORD2_IP_BUFS) == 0) {
1323 /* Dynamic short */ 1326 /* Dynamic short */
1324 ext_free = octeon_eth_buf_ext_free_m; 1327 ext_free = octeon_eth_buf_ext_free_m;
1325 ext_buf = &work[4]; 1328 ext_buf = &work[4];
1326 ext_size = 96; 1329 ext_size = 96;
1327 1330
1328 data = &work[4 + sc->sc_ip_offset / sizeof(uint64_t)]; 1331 data = &work[4 + sc->sc_ip_offset / sizeof(uint64_t)];
1329 } else { 1332 } else {
1330 vaddr_t addr; 1333 vaddr_t addr;
1331 vaddr_t start_buffer; 1334 vaddr_t start_buffer;
1332 1335
1333#ifdef __mips_n32 1336#ifdef __mips_n32
1334 KASSERT((word3 & ~MIPS_PHYS_MASK) == 0); 1337 KASSERT((word3 & ~MIPS_PHYS_MASK) == 0);
1335 addr = MIPS_PHYS_TO_KSEG0(word3 & PIP_WQE_WORD3_ADDR); 1338 addr = MIPS_PHYS_TO_KSEG0(word3 & PIP_WQE_WORD3_ADDR);
1336#else 1339#else
1337 addr = MIPS_PHYS_TO_XKPHYS_CACHED(word3 & PIP_WQE_WORD3_ADDR); 1340 addr = MIPS_PHYS_TO_XKPHYS_CACHED(word3 & PIP_WQE_WORD3_ADDR);
1338#endif 1341#endif
1339 start_buffer = addr & ~(2048 - 1); 1342 start_buffer = addr & ~(2048 - 1);
1340 1343
1341 ext_free = octeon_eth_buf_ext_free_ext; 1344 ext_free = octeon_eth_buf_ext_free_ext;
1342 ext_buf = (void *)start_buffer; 1345 ext_buf = (void *)start_buffer;
1343 ext_size = 2048; 1346 ext_size = 2048;
1344 1347
1345 data = (void *)addr; 1348 data = (void *)addr;
1346 } 1349 }
1347 1350
1348 /* embed sc pointer into work[0] for _ext_free evcnt */ 1351 /* embed sc pointer into work[0] for _ext_free evcnt */
1349 work[0] = (uintptr_t)sc; 1352 work[0] = (uintptr_t)sc;
1350 1353
1351 MEXTADD(m, ext_buf, ext_size, 0, ext_free, work); 1354 MEXTADD(m, ext_buf, ext_size, 0, ext_free, work);
1352 OCTEON_ETH_KASSERT(ISSET(m->m_flags, M_EXT)); 1355 OCTEON_ETH_KASSERT(ISSET(m->m_flags, M_EXT));
1353 1356
1354 m->m_data = data; 1357 m->m_data = data;
1355 m->m_len = m->m_pkthdr.len = (word1 & PIP_WQE_WORD1_LEN) >> 48; 1358 m->m_len = m->m_pkthdr.len = (word1 & PIP_WQE_WORD1_LEN) >> 48;
1356 m_set_rcvif(m, &sc->sc_ethercom.ec_if); 1359 m_set_rcvif(m, &sc->sc_ethercom.ec_if);
1357 /* 1360 /*
1358 * not readonly buffer 1361 * not readonly buffer
1359 */ 1362 */
1360 m->m_flags |= M_EXT_RW; 1363 m->m_flags |= M_EXT_RW;
1361 1364
1362 *rm = m; 1365 *rm = m;
1363 1366
1364 OCTEON_ETH_KASSERT(*rm != NULL); 1367 OCTEON_ETH_KASSERT(*rm != NULL);
1365 1368
1366 return 0; 1369 return 0;
1367} 1370}