 @@ -1,1085 +1,1085 @@
-/*	$NetBSD: if_wm.c,v 1.545 2017/11/30 03:53:24 msaitoh Exp $	*/
+/*	$NetBSD: if_wm.c,v 1.546 2017/11/30 09:24:18 msaitoh Exp $	*/
 /*
  * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed for the NetBSD Project by
  *	Wasabi Systems, Inc.
  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  *    or promote products derived from this software without specific prior
  *    written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*******************************************************************************
   Copyright (c) 2001-2005, Intel Corporation
   All rights reserved.
   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions are met:
 . Redistributions of source code must retain the above copyright notice,
       this list of conditions and the following disclaimer.
 . Redistributions in binary form must reproduce the above copyright
       notice, this list of conditions and the following disclaimer in the
       documentation and/or other materials provided with the distribution.
 . Neither the name of the Intel Corporation nor the names of its
       contributors may be used to endorse or promote products derived from
       this software without specific prior written permission.
   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************/
 /*
  * Device driver for the Intel i8254x family of Gigabit Ethernet chips.
+ *
  * TODO (in order of importance):
+ *
  *	- Check XXX'ed comments
  *	- TX Multi queue improvement (refine queue selection logic)
  *	- Split header buffer for newer descriptors
  *	- EEE (Energy Efficiency Ethernet)
  *	- Virtual Function
  *	- Set LED correctly (based on contents in EEPROM)
  *	- Rework how parameters are loaded from the EEPROM.
  *	- Image Unique ID
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.545 2017/11/30 03:53:24 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.546 2017/11/30 09:24:18 msaitoh Exp $");
 #ifdef _KERNEL_OPT
 #include "opt_net_mpsafe.h"
 #include "opt_if_wm.h"
 #endif
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/callout.h>
 #include <sys/mbuf.h>
 #include <sys/malloc.h>
 #include <sys/kmem.h>
 #include <sys/kernel.h>
 #include <sys/socket.h>
 #include <sys/ioctl.h>
 #include <sys/errno.h>
 #include <sys/device.h>
 #include <sys/queue.h>
 #include <sys/syslog.h>
 #include <sys/interrupt.h>
 #include <sys/cpu.h>
 #include <sys/pcq.h>
 #include <sys/rndsource.h>
 #include <net/if.h>
 #include <net/if_dl.h>
 #include <net/if_media.h>
 #include <net/if_ether.h>
 #include <net/bpf.h>
 #include <netinet/in.h>			/* XXX for struct ip */
 #include <netinet/in_systm.h>		/* XXX for struct ip */
 #include <netinet/ip.h>			/* XXX for struct ip */
 #include <netinet/ip6.h>		/* XXX for struct ip6_hdr */
 #include <netinet/tcp.h>		/* XXX for struct tcphdr */
 #include <sys/bus.h>
 #include <sys/intr.h>
 #include <machine/endian.h>
 #include <dev/mii/mii.h>
 #include <dev/mii/miivar.h>
 #include <dev/mii/miidevs.h>
 #include <dev/mii/mii_bitbang.h>
 #include <dev/mii/ikphyreg.h>
 #include <dev/mii/igphyreg.h>
 #include <dev/mii/igphyvar.h>
 #include <dev/mii/inbmphyreg.h>
 #include <dev/mii/ihphyreg.h>
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
 #include <dev/pci/pcidevs.h>
 #include <dev/pci/if_wmreg.h>
 #include <dev/pci/if_wmvar.h>
 #ifdef WM_DEBUG
 #define	WM_DEBUG_LINK		__BIT(0)
 #define	WM_DEBUG_TX		__BIT(1)
 #define	WM_DEBUG_RX		__BIT(2)
 #define	WM_DEBUG_GMII		__BIT(3)
 #define	WM_DEBUG_MANAGE		__BIT(4)
 #define	WM_DEBUG_NVM		__BIT(5)
 #define	WM_DEBUG_INIT		__BIT(6)
 #define	WM_DEBUG_LOCK		__BIT(7)
 int	wm_debug = WM_DEBUG_TX | WM_DEBUG_RX | WM_DEBUG_LINK | WM_DEBUG_GMII
     | WM_DEBUG_MANAGE | WM_DEBUG_NVM | WM_DEBUG_INIT | WM_DEBUG_LOCK;
 #define	DPRINTF(x, y)	if (wm_debug & (x)) printf y
 #else
 #define	DPRINTF(x, y)	/* nothing */
 #endif /* WM_DEBUG */
 #ifdef NET_MPSAFE
 #define WM_MPSAFE	1
 #define CALLOUT_FLAGS	CALLOUT_MPSAFE
 #else
 #define CALLOUT_FLAGS	0
 #endif
 /*
  * This device driver's max interrupt numbers.
  */
 #define WM_MAX_NQUEUEINTR	16
 #define WM_MAX_NINTR		(WM_MAX_NQUEUEINTR + 1)
 #ifndef WM_DISABLE_MSI
 #define	WM_DISABLE_MSI 0
 #endif
 #ifndef WM_DISABLE_MSIX
 #define	WM_DISABLE_MSIX 0
 #endif
 int wm_disable_msi = WM_DISABLE_MSI;
 int wm_disable_msix = WM_DISABLE_MSIX;
 /*
  * Transmit descriptor list size.  Due to errata, we can only have
  * 256 hardware descriptors in the ring on < 82544, but we use 4096
  * on >= 82544.  We tell the upper layers that they can queue a lot
  * of packets, and we go ahead and manage up to 64 (16 for the i82547)
  * of them at a time.
+ *
  * We allow up to 256 (!) DMA segments per packet.  Pathological packet
  * chains containing many small mbufs have been observed in zero-copy
  * situations with jumbo frames.
  */
 #define	WM_NTXSEGS		256
 #define	WM_IFQUEUELEN		256
 #define	WM_TXQUEUELEN_MAX	64
 #define	WM_TXQUEUELEN_MAX_82547	16
 #define	WM_TXQUEUELEN(txq)	((txq)->txq_num)
 #define	WM_TXQUEUELEN_MASK(txq)	(WM_TXQUEUELEN(txq) - 1)
 #define	WM_TXQUEUE_GC(txq)	(WM_TXQUEUELEN(txq) / 8)
 #define	WM_NTXDESC_82542	256
 #define	WM_NTXDESC_82544	4096
 #define	WM_NTXDESC(txq)		((txq)->txq_ndesc)
 #define	WM_NTXDESC_MASK(txq)	(WM_NTXDESC(txq) - 1)
 #define	WM_TXDESCS_SIZE(txq)	(WM_NTXDESC(txq) * (txq)->txq_descsize)
 #define	WM_NEXTTX(txq, x)	(((x) + 1) & WM_NTXDESC_MASK(txq))
 #define	WM_NEXTTXS(txq, x)	(((x) + 1) & WM_TXQUEUELEN_MASK(txq))
 #define	WM_MAXTXDMA		 (2 * round_page(IP_MAXPACKET)) /* for TSO */
 #define	WM_TXINTERQSIZE		256
 /*
  * Receive descriptor list size.  We have one Rx buffer for normal
  * sized packets.  Jumbo packets consume 5 Rx buffers for a full-sized
  * packet.  We allocate 256 receive descriptors, each with a 2k
  * buffer (MCLBYTES), which gives us room for 50 jumbo packets.
  */
 #define	WM_NRXDESC		256
 #define	WM_NRXDESC_MASK		(WM_NRXDESC - 1)
 #define	WM_NEXTRX(x)		(((x) + 1) & WM_NRXDESC_MASK)
 #define	WM_PREVRX(x)		(((x) - 1) & WM_NRXDESC_MASK)
 #ifndef WM_RX_PROCESS_LIMIT_DEFAULT
 #define	WM_RX_PROCESS_LIMIT_DEFAULT		100U
 #endif
 #ifndef WM_RX_INTR_PROCESS_LIMIT_DEFAULT
 #define	WM_RX_INTR_PROCESS_LIMIT_DEFAULT	0U
 #endif
 typedef union txdescs {
 	wiseman_txdesc_t sctxu_txdescs[WM_NTXDESC_82544];
 	nq_txdesc_t      sctxu_nq_txdescs[WM_NTXDESC_82544];
 } txdescs_t;
 typedef union rxdescs {
 	wiseman_rxdesc_t sctxu_rxdescs[WM_NRXDESC];
 	ext_rxdesc_t      sctxu_ext_rxdescs[WM_NRXDESC]; /* 82574 only */
 	nq_rxdesc_t      sctxu_nq_rxdescs[WM_NRXDESC]; /* 82575 and newer */
 } rxdescs_t;
 #define	WM_CDTXOFF(txq, x)	((txq)->txq_descsize * (x))
 #define	WM_CDRXOFF(rxq, x)	((rxq)->rxq_descsize * (x))
 /*
  * Software state for transmit jobs.
  */
 struct wm_txsoft {
 	struct mbuf *txs_mbuf;		/* head of our mbuf chain */
 	bus_dmamap_t txs_dmamap;	/* our DMA map */
 	int txs_firstdesc;		/* first descriptor in packet */
 	int txs_lastdesc;		/* last descriptor in packet */
 	int txs_ndesc;			/* # of descriptors used */
 };
 /*
  * Software state for receive buffers.  Each descriptor gets a
  * 2k (MCLBYTES) buffer and a DMA map.  For packets which fill
  * more than one buffer, we chain them together.
  */
 struct wm_rxsoft {
 	struct mbuf *rxs_mbuf;		/* head of our mbuf chain */
 	bus_dmamap_t rxs_dmamap;	/* our DMA map */
 };
 #define WM_LINKUP_TIMEOUT	50
 static uint16_t swfwphysem[] = {
 	SWFW_PHY0_SM,
 	SWFW_PHY1_SM,
 	SWFW_PHY2_SM,
 	SWFW_PHY3_SM
 };
 static const uint32_t wm_82580_rxpbs_table[] = {
 , 72, 144, 1, 2, 4, 8, 16, 35, 70, 140
 };
 struct wm_softc;
 #ifdef WM_EVENT_COUNTERS
 #define WM_Q_EVCNT_DEFINE(qname, evname)				\
 	char qname##_##evname##_evcnt_name[sizeof("qname##XX##evname")]; \
 	struct evcnt qname##_ev_##evname;
 #define WM_Q_EVCNT_ATTACH(qname, evname, q, qnum, xname, evtype)	\
 	do{								\
 		snprintf((q)->qname##_##evname##_evcnt_name,		\
 		    sizeof((q)->qname##_##evname##_evcnt_name),		\
 		    "%s%02d%s", #qname, (qnum), #evname);		\
 		evcnt_attach_dynamic(&(q)->qname##_ev_##evname,		\
 		    (evtype), NULL, (xname),				\
 		    (q)->qname##_##evname##_evcnt_name);		\
 	}while(0)
 #define WM_Q_MISC_EVCNT_ATTACH(qname, evname, q, qnum, xname)		\
 	WM_Q_EVCNT_ATTACH(qname, evname, q, qnum, xname, EVCNT_TYPE_MISC)
 #define WM_Q_INTR_EVCNT_ATTACH(qname, evname, q, qnum, xname)		\
 	WM_Q_EVCNT_ATTACH(qname, evname, q, qnum, xname, EVCNT_TYPE_INTR)
 #define WM_Q_EVCNT_DETACH(qname, evname, q, qnum)	\
 	evcnt_detach(&(q)->qname##_ev_##evname);
 #endif /* WM_EVENT_COUNTERS */
 struct wm_txqueue {
 	kmutex_t *txq_lock;		/* lock for tx operations */
 	struct wm_softc *txq_sc;	/* shortcut (skip struct wm_queue) */
 	/* Software state for the transmit descriptors. */
 	int txq_num;			/* must be a power of two */
 	struct wm_txsoft txq_soft[WM_TXQUEUELEN_MAX];
 	/* TX control data structures. */
 	int txq_ndesc;			/* must be a power of two */
 	size_t txq_descsize;		/* a tx descriptor size */
 	txdescs_t *txq_descs_u;
         bus_dmamap_t txq_desc_dmamap;	/* control data DMA map */
 	bus_dma_segment_t txq_desc_seg;	/* control data segment */
 	int txq_desc_rseg;		/* real number of control segment */
 #define	txq_desc_dma	txq_desc_dmamap->dm_segs[0].ds_addr
 #define	txq_descs	txq_descs_u->sctxu_txdescs
 #define	txq_nq_descs	txq_descs_u->sctxu_nq_txdescs
 	bus_addr_t txq_tdt_reg;		/* offset of TDT register */
 	int txq_free;			/* number of free Tx descriptors */
 	int txq_next;			/* next ready Tx descriptor */
 	int txq_sfree;			/* number of free Tx jobs */
 	int txq_snext;			/* next free Tx job */
 	int txq_sdirty;			/* dirty Tx jobs */
 	/* These 4 variables are used only on the 82547. */
 	int txq_fifo_size;		/* Tx FIFO size */
 	int txq_fifo_head;		/* current head of FIFO */
 	uint32_t txq_fifo_addr;		/* internal address of start of FIFO */
 	int txq_fifo_stall;		/* Tx FIFO is stalled */
 	/*
 	 * When ncpu > number of Tx queues, a Tx queue is shared by multiple
 	 * CPUs. This queue intermediate them without block.
 	 */
 	pcq_t *txq_interq;
 	/*
 	 * NEWQUEUE devices must use not ifp->if_flags but txq->txq_flags
 	 * to manage Tx H/W queue's busy flag.
 	 */
 	int txq_flags;			/* flags for H/W queue, see below */
 #define	WM_TXQ_NO_SPACE	0x1
 	bool txq_stopping;
 	uint32_t txq_packets;		/* for AIM */
 	uint32_t txq_bytes;		/* for AIM */
 #ifdef WM_EVENT_COUNTERS
 	WM_Q_EVCNT_DEFINE(txq, txsstall)	/* Tx stalled due to no txs */
 	WM_Q_EVCNT_DEFINE(txq, txdstall)	/* Tx stalled due to no txd */
 	WM_Q_EVCNT_DEFINE(txq, txfifo_stall)	/* Tx FIFO stalls (82547) */
 	WM_Q_EVCNT_DEFINE(txq, txdw)		/* Tx descriptor interrupts */
 	WM_Q_EVCNT_DEFINE(txq, txqe)		/* Tx queue empty interrupts */
 						/* XXX not used? */
 	WM_Q_EVCNT_DEFINE(txq, txipsum)		/* IP checksums comp. out-bound */
 	WM_Q_EVCNT_DEFINE(txq,txtusum)		/* TCP/UDP cksums comp. out-bound */
 	WM_Q_EVCNT_DEFINE(txq, txtusum6)	/* TCP/UDP v6 cksums comp. out-bound */
 	WM_Q_EVCNT_DEFINE(txq, txtso)		/* TCP seg offload out-bound (IPv4) */
 	WM_Q_EVCNT_DEFINE(txq, txtso6)		/* TCP seg offload out-bound (IPv6) */
 	WM_Q_EVCNT_DEFINE(txq, txtsopain)	/* painful header manip. for TSO */
 	WM_Q_EVCNT_DEFINE(txq, txdrop)		/* Tx packets dropped(too many segs) */
 	WM_Q_EVCNT_DEFINE(txq, tu)		/* Tx underrun */
 	char txq_txseg_evcnt_names[WM_NTXSEGS][sizeof("txqXXtxsegXXX")];
 	struct evcnt txq_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */
 #endif /* WM_EVENT_COUNTERS */
 };
 struct wm_rxqueue {
 	kmutex_t *rxq_lock;		/* lock for rx operations */
 	struct wm_softc *rxq_sc;	/* shortcut (skip struct wm_queue) */
 	/* Software state for the receive descriptors. */
 	struct wm_rxsoft rxq_soft[WM_NRXDESC];
 	/* RX control data structures. */
 	int rxq_ndesc;			/* must be a power of two */
 	size_t rxq_descsize;		/* a rx descriptor size */
 	rxdescs_t *rxq_descs_u;
 	bus_dmamap_t rxq_desc_dmamap;	/* control data DMA map */
 	bus_dma_segment_t rxq_desc_seg;	/* control data segment */
 	int rxq_desc_rseg;		/* real number of control segment */
 #define	rxq_desc_dma	rxq_desc_dmamap->dm_segs[0].ds_addr
 #define	rxq_descs	rxq_descs_u->sctxu_rxdescs
 #define	rxq_ext_descs	rxq_descs_u->sctxu_ext_rxdescs
 #define	rxq_nq_descs	rxq_descs_u->sctxu_nq_rxdescs
 	bus_addr_t rxq_rdt_reg;		/* offset of RDT register */
 	int rxq_ptr;			/* next ready Rx desc/queue ent */
 	int rxq_discard;
 	int rxq_len;
 	struct mbuf *rxq_head;
 	struct mbuf *rxq_tail;
 	struct mbuf **rxq_tailp;
 	bool rxq_stopping;
 	uint32_t rxq_packets;		/* for AIM */
 	uint32_t rxq_bytes;		/* for AIM */
 #ifdef WM_EVENT_COUNTERS
 	WM_Q_EVCNT_DEFINE(rxq, rxintr);		/* Rx interrupts */
 	WM_Q_EVCNT_DEFINE(rxq, rxipsum);	/* IP checksums checked in-bound */
 	WM_Q_EVCNT_DEFINE(rxq, rxtusum);	/* TCP/UDP cksums checked in-bound */
 #endif
 };
 struct wm_queue {
 	int wmq_id;			/* index of transmit and receive queues */
 	int wmq_intr_idx;		/* index of MSI-X tables */
 	uint32_t wmq_itr;		/* interrupt interval per queue. */
 	bool wmq_set_itr;
 	struct wm_txqueue wmq_txq;
 	struct wm_rxqueue wmq_rxq;
 	void *wmq_si;
 };
 struct wm_phyop {
 	int (*acquire)(struct wm_softc *);
 	void (*release)(struct wm_softc *);
 	int reset_delay_us;
 };
 struct wm_nvmop {
 	int (*acquire)(struct wm_softc *);
 	void (*release)(struct wm_softc *);
 	int (*read)(struct wm_softc *, int, int, uint16_t *);
 };
 /*
  * Software state per device.
  */
 struct wm_softc {
 	device_t sc_dev;		/* generic device information */
 	bus_space_tag_t sc_st;		/* bus space tag */
 	bus_space_handle_t sc_sh;	/* bus space handle */
 	bus_size_t sc_ss;		/* bus space size */
 	bus_space_tag_t sc_iot;		/* I/O space tag */
 	bus_space_handle_t sc_ioh;	/* I/O space handle */
 	bus_size_t sc_ios;		/* I/O space size */
 	bus_space_tag_t sc_flasht;	/* flash registers space tag */
 	bus_space_handle_t sc_flashh;	/* flash registers space handle */
 	bus_size_t sc_flashs;		/* flash registers space size */
 	off_t sc_flashreg_offset;	/*
 					 * offset to flash registers from
 					 * start of BAR
 					 */
 	bus_dma_tag_t sc_dmat;		/* bus DMA tag */
 	struct ethercom sc_ethercom;	/* ethernet common data */
 	struct mii_data sc_mii;		/* MII/media information */
 	pci_chipset_tag_t sc_pc;
 	pcitag_t sc_pcitag;
 	int sc_bus_speed;		/* PCI/PCIX bus speed */
 	int sc_pcixe_capoff;		/* PCI[Xe] capability reg offset */
 	uint16_t sc_pcidevid;		/* PCI device ID */
 	wm_chip_type sc_type;		/* MAC type */
 	int sc_rev;			/* MAC revision */
 	wm_phy_type sc_phytype;		/* PHY type */
 	uint32_t sc_mediatype;		/* Media type (Copper, Fiber, SERDES)*/
 #define	WM_MEDIATYPE_UNKNOWN		0x00
 #define	WM_MEDIATYPE_FIBER		0x01
 #define	WM_MEDIATYPE_COPPER		0x02
 #define	WM_MEDIATYPE_SERDES		0x03 /* Internal SERDES */
 	int sc_funcid;			/* unit number of the chip (0 to 3) */
 	int sc_flags;			/* flags; see below */
 	int sc_if_flags;		/* last if_flags */
 	int sc_flowflags;		/* 802.3x flow control flags */
 	int sc_align_tweak;
 	void *sc_ihs[WM_MAX_NINTR];	/*
 					 * interrupt cookie.
 					 * - legacy and msi use sc_ihs[0] only
 					 * - msix use sc_ihs[0] to sc_ihs[nintrs-1]
 					 */
 	pci_intr_handle_t *sc_intrs;	/*
 					 * legacy and msi use sc_intrs[0] only
 					 * msix use sc_intrs[0] to sc_ihs[nintrs-1]
 					 */
 	int sc_nintrs;			/* number of interrupts */
 	int sc_link_intr_idx;		/* index of MSI-X tables */
 	callout_t sc_tick_ch;		/* tick callout */
 	bool sc_core_stopping;
 	int sc_nvm_ver_major;
 	int sc_nvm_ver_minor;
 	int sc_nvm_ver_build;
 	int sc_nvm_addrbits;		/* NVM address bits */
 	unsigned int sc_nvm_wordsize;	/* NVM word size */
 	int sc_ich8_flash_base;
 	int sc_ich8_flash_bank_size;
 	int sc_nvm_k1_enabled;
 	int sc_nqueues;
 	struct wm_queue *sc_queue;
 	u_int sc_rx_process_limit;	/* Rx processing repeat limit in softint */
 	u_int sc_rx_intr_process_limit;	/* Rx processing repeat limit in H/W intr */
 	int sc_affinity_offset;
 #ifdef WM_EVENT_COUNTERS
 	/* Event counters. */
 	struct evcnt sc_ev_linkintr;	/* Link interrupts */
         /* WM_T_82542_2_1 only */
 	struct evcnt sc_ev_tx_xoff;	/* Tx PAUSE(!0) frames */
 	struct evcnt sc_ev_tx_xon;	/* Tx PAUSE(0) frames */
 	struct evcnt sc_ev_rx_xoff;	/* Rx PAUSE(!0) frames */
 	struct evcnt sc_ev_rx_xon;	/* Rx PAUSE(0) frames */
 	struct evcnt sc_ev_rx_macctl;	/* Rx Unsupported */
 #endif /* WM_EVENT_COUNTERS */
 	/* This variable are used only on the 82547. */
 	callout_t sc_txfifo_ch;		/* Tx FIFO stall work-around timer */
 	uint32_t sc_ctrl;		/* prototype CTRL register */
 #if 0
 	uint32_t sc_ctrl_ext;		/* prototype CTRL_EXT register */
 #endif
 	uint32_t sc_icr;		/* prototype interrupt bits */
 	uint32_t sc_itr_init;		/* prototype intr throttling reg */
 	uint32_t sc_tctl;		/* prototype TCTL register */
 	uint32_t sc_rctl;		/* prototype RCTL register */
 	uint32_t sc_txcw;		/* prototype TXCW register */
 	uint32_t sc_tipg;		/* prototype TIPG register */
 	uint32_t sc_fcrtl;		/* prototype FCRTL register */
 	uint32_t sc_pba;		/* prototype PBA register */
 	int sc_tbi_linkup;		/* TBI link status */
 	int sc_tbi_serdes_anegticks;	/* autonegotiation ticks */
 	int sc_tbi_serdes_ticks;	/* tbi ticks */
 	int sc_mchash_type;		/* multicast filter offset */
 	krndsource_t rnd_source;	/* random source */
 	struct if_percpuq *sc_ipq;	/* softint-based input queues */
 	kmutex_t *sc_core_lock;		/* lock for softc operations */
 	kmutex_t *sc_ich_phymtx;	/*
 					 * 82574/82583/ICH/PCH specific PHY
 					 * mutex. For 82574/82583, the mutex
 					 * is used for both PHY and NVM.
 					 */
 	kmutex_t *sc_ich_nvmmtx;	/* ICH/PCH specific NVM mutex */
 	struct wm_phyop phy;
 	struct wm_nvmop nvm;
 };
 #define WM_CORE_LOCK(_sc)	if ((_sc)->sc_core_lock) mutex_enter((_sc)->sc_core_lock)
 #define WM_CORE_UNLOCK(_sc)	if ((_sc)->sc_core_lock) mutex_exit((_sc)->sc_core_lock)
 #define WM_CORE_LOCKED(_sc)	(!(_sc)->sc_core_lock || mutex_owned((_sc)->sc_core_lock))
 #define	WM_RXCHAIN_RESET(rxq)						\
 do {									\
 	(rxq)->rxq_tailp = &(rxq)->rxq_head;				\
 	*(rxq)->rxq_tailp = NULL;					\
 	(rxq)->rxq_len = 0;						\
 } while (/*CONSTCOND*/0)
 #define	WM_RXCHAIN_LINK(rxq, m)						\
 do {									\
 	*(rxq)->rxq_tailp = (rxq)->rxq_tail = (m);			\
 	(rxq)->rxq_tailp = &(m)->m_next;				\
 } while (/*CONSTCOND*/0)
 #ifdef WM_EVENT_COUNTERS
 #define	WM_EVCNT_INCR(ev)	(ev)->ev_count++
 #define	WM_EVCNT_ADD(ev, val)	(ev)->ev_count += (val)
 #define WM_Q_EVCNT_INCR(qname, evname)			\
 	WM_EVCNT_INCR(&(qname)->qname##_ev_##evname)
 #define WM_Q_EVCNT_ADD(qname, evname, val)		\
 	WM_EVCNT_ADD(&(qname)->qname##_ev_##evname, (val))
 #else /* !WM_EVENT_COUNTERS */
 #define	WM_EVCNT_INCR(ev)	/* nothing */
 #define	WM_EVCNT_ADD(ev, val)	/* nothing */
 #define WM_Q_EVCNT_INCR(qname, evname)		/* nothing */
 #define WM_Q_EVCNT_ADD(qname, evname, val)	/* nothing */
 #endif /* !WM_EVENT_COUNTERS */
 #define	CSR_READ(sc, reg)						\
 	bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
 #define	CSR_WRITE(sc, reg, val)						\
 	bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
 #define	CSR_WRITE_FLUSH(sc)						\
 	(void) CSR_READ((sc), WMREG_STATUS)
 #define ICH8_FLASH_READ32(sc, reg)					\
 	bus_space_read_4((sc)->sc_flasht, (sc)->sc_flashh,		\
 	    (reg) + sc->sc_flashreg_offset)
 #define ICH8_FLASH_WRITE32(sc, reg, data)				\
 	bus_space_write_4((sc)->sc_flasht, (sc)->sc_flashh,		\
 	    (reg) + sc->sc_flashreg_offset, (data))
 #define ICH8_FLASH_READ16(sc, reg)					\
 	bus_space_read_2((sc)->sc_flasht, (sc)->sc_flashh,		\
 	    (reg) + sc->sc_flashreg_offset)
 #define ICH8_FLASH_WRITE16(sc, reg, data)				\
 	bus_space_write_2((sc)->sc_flasht, (sc)->sc_flashh,		\
 	    (reg) + sc->sc_flashreg_offset, (data))
 #define	WM_CDTXADDR(txq, x)	((txq)->txq_desc_dma + WM_CDTXOFF((txq), (x)))
 #define	WM_CDRXADDR(rxq, x)	((rxq)->rxq_desc_dma + WM_CDRXOFF((rxq), (x)))
 #define	WM_CDTXADDR_LO(txq, x)	(WM_CDTXADDR((txq), (x)) & 0xffffffffU)
 #define	WM_CDTXADDR_HI(txq, x)						\
 	(sizeof(bus_addr_t) == 8 ?					\
 	 (uint64_t)WM_CDTXADDR((txq), (x)) >> 32 : 0)
 #define	WM_CDRXADDR_LO(rxq, x)	(WM_CDRXADDR((rxq), (x)) & 0xffffffffU)
 #define	WM_CDRXADDR_HI(rxq, x)						\
 	(sizeof(bus_addr_t) == 8 ?					\
 	 (uint64_t)WM_CDRXADDR((rxq), (x)) >> 32 : 0)
 /*
  * Register read/write functions.
  * Other than CSR_{READ|WRITE}().
  */
 #if 0
 static inline uint32_t wm_io_read(struct wm_softc *, int);
 #endif
 static inline void wm_io_write(struct wm_softc *, int, uint32_t);
 static inline void wm_82575_write_8bit_ctlr_reg(struct wm_softc *, uint32_t,
 	uint32_t, uint32_t);
 static inline void wm_set_dma_addr(volatile wiseman_addr_t *, bus_addr_t);
 /*
  * Descriptor sync/init functions.
  */
 static inline void wm_cdtxsync(struct wm_txqueue *, int, int, int);
 static inline void wm_cdrxsync(struct wm_rxqueue *, int, int);
 static inline void wm_init_rxdesc(struct wm_rxqueue *, int);
 /*
  * Device driver interface functions and commonly used functions.
  * match, attach, detach, init, start, stop, ioctl, watchdog and so on.
  */
 static const struct wm_product *wm_lookup(const struct pci_attach_args *);
 static int	wm_match(device_t, cfdata_t, void *);
 static void	wm_attach(device_t, device_t, void *);
 static int	wm_detach(device_t, int);
 static bool	wm_suspend(device_t, const pmf_qual_t *);
 static bool	wm_resume(device_t, const pmf_qual_t *);
 static void	wm_watchdog(struct ifnet *);
 static void	wm_watchdog_txq(struct ifnet *, struct wm_txqueue *);
 static void	wm_tick(void *);
 static int	wm_ifflags_cb(struct ethercom *);
 static int	wm_ioctl(struct ifnet *, u_long, void *);
 /* MAC address related */
 static uint16_t	wm_check_alt_mac_addr(struct wm_softc *);
 static int	wm_read_mac_addr(struct wm_softc *, uint8_t *);
 static void	wm_set_ral(struct wm_softc *, const uint8_t *, int);
 static uint32_t	wm_mchash(struct wm_softc *, const uint8_t *);
 static void	wm_set_filter(struct wm_softc *);
 /* Reset and init related */
 static void	wm_set_vlan(struct wm_softc *);
 static void	wm_set_pcie_completion_timeout(struct wm_softc *);
 static void	wm_get_auto_rd_done(struct wm_softc *);
 static void	wm_lan_init_done(struct wm_softc *);
 static void	wm_get_cfg_done(struct wm_softc *);
 static void	wm_phy_post_reset(struct wm_softc *);
 static void	wm_write_smbus_addr(struct wm_softc *);
 static void	wm_init_lcd_from_nvm(struct wm_softc *);
 static void	wm_initialize_hardware_bits(struct wm_softc *);
 static uint32_t	wm_rxpbs_adjust_82580(uint32_t);
 static void	wm_reset_phy(struct wm_softc *);
 static void	wm_flush_desc_rings(struct wm_softc *);
 static void	wm_reset(struct wm_softc *);
 static int	wm_add_rxbuf(struct wm_rxqueue *, int);
 static void	wm_rxdrain(struct wm_rxqueue *);
 static void	wm_rss_getkey(uint8_t *);
 static void	wm_init_rss(struct wm_softc *);
 static void	wm_adjust_qnum(struct wm_softc *, int);
 static inline bool	wm_is_using_msix(struct wm_softc *);
 static inline bool	wm_is_using_multiqueue(struct wm_softc *);
 static int	wm_softint_establish(struct wm_softc *, int, int);
 static int	wm_setup_legacy(struct wm_softc *);
 static int	wm_setup_msix(struct wm_softc *);
 static int	wm_init(struct ifnet *);
 static int	wm_init_locked(struct ifnet *);
 static void	wm_unset_stopping_flags(struct wm_softc *);
 static void	wm_set_stopping_flags(struct wm_softc *);
 static void	wm_stop(struct ifnet *, int);
 static void	wm_stop_locked(struct ifnet *, int);
 static void	wm_dump_mbuf_chain(struct wm_softc *, struct mbuf *);
 static void	wm_82547_txfifo_stall(void *);
 static int	wm_82547_txfifo_bugchk(struct wm_softc *, struct mbuf *);
 static void	wm_itrs_writereg(struct wm_softc *, struct wm_queue *);
 /* DMA related */
 static int	wm_alloc_tx_descs(struct wm_softc *, struct wm_txqueue *);
 static void	wm_free_tx_descs(struct wm_softc *, struct wm_txqueue *);
 static void	wm_init_tx_descs(struct wm_softc *, struct wm_txqueue *);
 static void	wm_init_tx_regs(struct wm_softc *, struct wm_queue *,
     struct wm_txqueue *);
 static int	wm_alloc_rx_descs(struct wm_softc *, struct wm_rxqueue *);
 static void	wm_free_rx_descs(struct wm_softc *, struct wm_rxqueue *);
 static void	wm_init_rx_regs(struct wm_softc *, struct wm_queue *,
     struct wm_rxqueue *);
 static int	wm_alloc_tx_buffer(struct wm_softc *, struct wm_txqueue *);
 static void	wm_free_tx_buffer(struct wm_softc *, struct wm_txqueue *);
 static void	wm_init_tx_buffer(struct wm_softc *, struct wm_txqueue *);
 static int	wm_alloc_rx_buffer(struct wm_softc *, struct wm_rxqueue *);
 static void	wm_free_rx_buffer(struct wm_softc *, struct wm_rxqueue *);
 static int	wm_init_rx_buffer(struct wm_softc *, struct wm_rxqueue *);
 static void	wm_init_tx_queue(struct wm_softc *, struct wm_queue *,
     struct wm_txqueue *);
 static int	wm_init_rx_queue(struct wm_softc *, struct wm_queue *,
     struct wm_rxqueue *);
 static int	wm_alloc_txrx_queues(struct wm_softc *);
 static void	wm_free_txrx_queues(struct wm_softc *);
 static int	wm_init_txrx_queues(struct wm_softc *);
 /* Start */
 static int	wm_tx_offload(struct wm_softc *, struct wm_txqueue *,
     struct wm_txsoft *, uint32_t *, uint8_t *);
 static inline int	wm_select_txqueue(struct ifnet *, struct mbuf *);
 static void	wm_start(struct ifnet *);
 static void	wm_start_locked(struct ifnet *);
 static int	wm_transmit(struct ifnet *, struct mbuf *);
 static void	wm_transmit_locked(struct ifnet *, struct wm_txqueue *);
 static void	wm_send_common_locked(struct ifnet *, struct wm_txqueue *, bool);
 static int	wm_nq_tx_offload(struct wm_softc *, struct wm_txqueue *,
     struct wm_txsoft *, uint32_t *, uint32_t *, bool *);
 static void	wm_nq_start(struct ifnet *);
 static void	wm_nq_start_locked(struct ifnet *);
 static int	wm_nq_transmit(struct ifnet *, struct mbuf *);
 static void	wm_nq_transmit_locked(struct ifnet *, struct wm_txqueue *);
 static void	wm_nq_send_common_locked(struct ifnet *, struct wm_txqueue *, bool);
 static void	wm_deferred_start_locked(struct wm_txqueue *);
 static void	wm_handle_queue(void *);
 /* Interrupt */
 static int	wm_txeof(struct wm_softc *, struct wm_txqueue *);
 static void	wm_rxeof(struct wm_rxqueue *, u_int);
 static void	wm_linkintr_gmii(struct wm_softc *, uint32_t);
 static void	wm_linkintr_tbi(struct wm_softc *, uint32_t);
 static void	wm_linkintr_serdes(struct wm_softc *, uint32_t);
 static void	wm_linkintr(struct wm_softc *, uint32_t);
 static int	wm_intr_legacy(void *);
 static inline void	wm_txrxintr_disable(struct wm_queue *);
 static inline void	wm_txrxintr_enable(struct wm_queue *);
 static void	wm_itrs_calculate(struct wm_softc *, struct wm_queue *);
 static int	wm_txrxintr_msix(void *);
 static int	wm_linkintr_msix(void *);
 /*
  * Media related.
  * GMII, SGMII, TBI, SERDES and SFP.
  */
 /* Common */
 static void	wm_tbi_serdes_set_linkled(struct wm_softc *);
 /* GMII related */
 static void	wm_gmii_reset(struct wm_softc *);
 static void	wm_gmii_setup_phytype(struct wm_softc *sc, uint32_t, uint16_t);
 static int	wm_get_phy_id_82575(struct wm_softc *);
 static void	wm_gmii_mediainit(struct wm_softc *, pci_product_id_t);
 static int	wm_gmii_mediachange(struct ifnet *);
 static void	wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *);
 static void	wm_i82543_mii_sendbits(struct wm_softc *, uint32_t, int);
 static uint32_t	wm_i82543_mii_recvbits(struct wm_softc *);
 static int	wm_gmii_i82543_readreg(device_t, int, int);
 static void	wm_gmii_i82543_writereg(device_t, int, int, int);
 static int	wm_gmii_mdic_readreg(device_t, int, int);
 static void	wm_gmii_mdic_writereg(device_t, int, int, int);
 static int	wm_gmii_i82544_readreg(device_t, int, int);
 static void	wm_gmii_i82544_writereg(device_t, int, int, int);
 static int	wm_gmii_i80003_readreg(device_t, int, int);
 static void	wm_gmii_i80003_writereg(device_t, int, int, int);
 static int	wm_gmii_bm_readreg(device_t, int, int);
 static void	wm_gmii_bm_writereg(device_t, int, int, int);
 static void	wm_access_phy_wakeup_reg_bm(device_t, int, int16_t *, int);
 static int	wm_gmii_hv_readreg(device_t, int, int);
 static int	wm_gmii_hv_readreg_locked(device_t, int, int);
 static void	wm_gmii_hv_writereg(device_t, int, int, int);
 static void	wm_gmii_hv_writereg_locked(device_t, int, int, int);
 static int	wm_gmii_82580_readreg(device_t, int, int);
 static void	wm_gmii_82580_writereg(device_t, int, int, int);
 static int	wm_gmii_gs40g_readreg(device_t, int, int);
 static void	wm_gmii_gs40g_writereg(device_t, int, int, int);
 static void	wm_gmii_statchg(struct ifnet *);
 /*
  * kumeran related (80003, ICH* and PCH*).
  * These functions are not for accessing MII registers but for accessing
  * kumeran specific registers.
  */
 static int	wm_kmrn_readreg(struct wm_softc *, int, uint16_t *);
 static int	wm_kmrn_readreg_locked(struct wm_softc *, int, uint16_t *);
 static int	wm_kmrn_writereg(struct wm_softc *, int, uint16_t);
 static int	wm_kmrn_writereg_locked(struct wm_softc *, int, uint16_t);
 /* SGMII */
 static bool	wm_sgmii_uses_mdio(struct wm_softc *);
 static int	wm_sgmii_readreg(device_t, int, int);
 static void	wm_sgmii_writereg(device_t, int, int, int);
 /* TBI related */
 static void	wm_tbi_mediainit(struct wm_softc *);
 static int	wm_tbi_mediachange(struct ifnet *);
 static void	wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *);
 static int	wm_check_for_link(struct wm_softc *);
 static void	wm_tbi_tick(struct wm_softc *);
 /* SERDES related */
 static void	wm_serdes_power_up_link_82575(struct wm_softc *);
 static int	wm_serdes_mediachange(struct ifnet *);
 static void	wm_serdes_mediastatus(struct ifnet *, struct ifmediareq *);
 static void	wm_serdes_tick(struct wm_softc *);
 /* SFP related */
 static int	wm_sfp_read_data_byte(struct wm_softc *, uint16_t, uint8_t *);
 static uint32_t	wm_sfp_get_media_type(struct wm_softc *);
 /*
  * NVM related.
  * Microwire, SPI (w/wo EERD) and Flash.
  */
 /* Misc functions */
 static void	wm_eeprom_sendbits(struct wm_softc *, uint32_t, int);
 static void	wm_eeprom_recvbits(struct wm_softc *, uint32_t *, int);
 static int	wm_nvm_set_addrbits_size_eecd(struct wm_softc *);
 /* Microwire */
 static int	wm_nvm_read_uwire(struct wm_softc *, int, int, uint16_t *);
 /* SPI */
 static int	wm_nvm_ready_spi(struct wm_softc *);
 static int	wm_nvm_read_spi(struct wm_softc *, int, int, uint16_t *);
 /* Using with EERD */
 static int	wm_poll_eerd_eewr_done(struct wm_softc *, int);
 static int	wm_nvm_read_eerd(struct wm_softc *, int, int, uint16_t *);
 /* Flash */
 static int	wm_nvm_valid_bank_detect_ich8lan(struct wm_softc *,
     unsigned int *);
 static int32_t	wm_ich8_cycle_init(struct wm_softc *);
 static int32_t	wm_ich8_flash_cycle(struct wm_softc *, uint32_t);
 static int32_t	wm_read_ich8_data(struct wm_softc *, uint32_t, uint32_t,
 	uint32_t *);
 static int32_t	wm_read_ich8_byte(struct wm_softc *, uint32_t, uint8_t *);
 static int32_t	wm_read_ich8_word(struct wm_softc *, uint32_t, uint16_t *);
 static int32_t	wm_read_ich8_dword(struct wm_softc *, uint32_t, uint32_t *);
 static int	wm_nvm_read_ich8(struct wm_softc *, int, int, uint16_t *);
 static int	wm_nvm_read_spt(struct wm_softc *, int, int, uint16_t *);
 /* iNVM */
 static int	wm_nvm_read_word_invm(struct wm_softc *, uint16_t, uint16_t *);
 static int	wm_nvm_read_invm(struct wm_softc *, int, int, uint16_t *);
 /* Lock, detecting NVM type, validate checksum and read */
 static int	wm_nvm_is_onboard_eeprom(struct wm_softc *);
 static int	wm_nvm_get_flash_presence_i210(struct wm_softc *);
 static int	wm_nvm_validate_checksum(struct wm_softc *);
 static void	wm_nvm_version_invm(struct wm_softc *);
 static void	wm_nvm_version(struct wm_softc *);
 static int	wm_nvm_read(struct wm_softc *, int, int, uint16_t *);
 /*
  * Hardware semaphores.
  * Very complexed...
  */
 static int	wm_get_null(struct wm_softc *);
 static void	wm_put_null(struct wm_softc *);
 static int	wm_get_eecd(struct wm_softc *);
 static void	wm_put_eecd(struct wm_softc *);
 static int	wm_get_swsm_semaphore(struct wm_softc *); /* 8257[123] */
 static void	wm_put_swsm_semaphore(struct wm_softc *);
 static int	wm_get_swfw_semaphore(struct wm_softc *, uint16_t);
 static void	wm_put_swfw_semaphore(struct wm_softc *, uint16_t);
 static int	wm_get_nvm_80003(struct wm_softc *);
 static void	wm_put_nvm_80003(struct wm_softc *);
 static int	wm_get_nvm_82571(struct wm_softc *);
 static void	wm_put_nvm_82571(struct wm_softc *);
 static int	wm_get_phy_82575(struct wm_softc *);
 static void	wm_put_phy_82575(struct wm_softc *);
 static int	wm_get_swfwhw_semaphore(struct wm_softc *); /* For 574/583 */
 static void	wm_put_swfwhw_semaphore(struct wm_softc *);
 static int	wm_get_swflag_ich8lan(struct wm_softc *);	/* For PHY */
 static void	wm_put_swflag_ich8lan(struct wm_softc *);
 static int	wm_get_nvm_ich8lan(struct wm_softc *);
 static void	wm_put_nvm_ich8lan(struct wm_softc *);
 static int	wm_get_hw_semaphore_82573(struct wm_softc *);
 static void	wm_put_hw_semaphore_82573(struct wm_softc *);
 /*
  * Management mode and power management related subroutines.
  * BMC, AMT, suspend/resume and EEE.
  */
 #if 0
 static int	wm_check_mng_mode(struct wm_softc *);
 static int	wm_check_mng_mode_ich8lan(struct wm_softc *);
 static int	wm_check_mng_mode_82574(struct wm_softc *);
 static int	wm_check_mng_mode_generic(struct wm_softc *);
 #endif
 static int	wm_enable_mng_pass_thru(struct wm_softc *);
 static bool	wm_phy_resetisblocked(struct wm_softc *);
 static void	wm_get_hw_control(struct wm_softc *);
 static void	wm_release_hw_control(struct wm_softc *);
 static void	wm_gate_hw_phy_config_ich8lan(struct wm_softc *, bool);
 static void	wm_smbustopci(struct wm_softc *);
 static void	wm_init_manageability(struct wm_softc *);
 static void	wm_release_manageability(struct wm_softc *);
 static void	wm_get_wakeup(struct wm_softc *);
 static void	wm_ulp_disable(struct wm_softc *);
 static void	wm_enable_phy_wakeup(struct wm_softc *);
 static void	wm_igp3_phy_powerdown_workaround_ich8lan(struct wm_softc *);
 static void	wm_enable_wakeup(struct wm_softc *);
 /* LPLU (Low Power Link Up) */
 static void	wm_lplu_d0_disable(struct wm_softc *);
 /* EEE */
 static void	wm_set_eee_i350(struct wm_softc *);
 /*
  * Workarounds (mainly PHY related).
  * Basically, PHY's workarounds are in the PHY drivers.
  */
 static void	wm_kmrn_lock_loss_workaround_ich8lan(struct wm_softc *);
 static void	wm_gig_downshift_workaround_ich8lan(struct wm_softc *);
 static void	wm_hv_phy_workaround_ich8lan(struct wm_softc *);
 static void	wm_lv_phy_workaround_ich8lan(struct wm_softc *);
 static int	wm_k1_gig_workaround_hv(struct wm_softc *, int);
 static void	wm_set_mdio_slow_mode_hv(struct wm_softc *);
 static void	wm_configure_k1_ich8lan(struct wm_softc *, int);
 static void	wm_reset_init_script_82575(struct wm_softc *);
 static void	wm_reset_mdicnfg_82580(struct wm_softc *);
 static bool	wm_phy_is_accessible_pchlan(struct wm_softc *);
 static void	wm_toggle_lanphypc_pch_lpt(struct wm_softc *);
 static int	wm_platform_pm_pch_lpt(struct wm_softc *, bool);
 static void	wm_pll_workaround_i210(struct wm_softc *);
 static void	wm_legacy_irq_quirk_spt(struct wm_softc *);
 CFATTACH_DECL3_NEW(wm, sizeof(struct wm_softc),
     wm_match, wm_attach, wm_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN);
 /*
  * Devices supported by this driver.
  */
 static const struct wm_product {
 	pci_vendor_id_t		wmp_vendor;
 	pci_product_id_t	wmp_product;
 	const char		*wmp_name;
 	wm_chip_type		wmp_type;
 	uint32_t		wmp_flags;
 #define	WMP_F_UNKNOWN		WM_MEDIATYPE_UNKNOWN
 #define	WMP_F_FIBER		WM_MEDIATYPE_FIBER
 #define	WMP_F_COPPER		WM_MEDIATYPE_COPPER
 #define	WMP_F_SERDES		WM_MEDIATYPE_SERDES
 #define WMP_MEDIATYPE(x)	((x) & 0x03)
 } wm_products[] = {
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82542,
 	  "Intel i82542 1000BASE-X Ethernet",
 	  WM_T_82542_2_1,	WMP_F_FIBER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82543GC_FIBER,
 	  "Intel i82543GC 1000BASE-X Ethernet",
 	  WM_T_82543,		WMP_F_FIBER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82543GC_COPPER,
 	  "Intel i82543GC 1000BASE-T Ethernet",
 	  WM_T_82543,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544EI_COPPER,
 	  "Intel i82544EI 1000BASE-T Ethernet",
 	  WM_T_82544,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544EI_FIBER,
 	  "Intel i82544EI 1000BASE-X Ethernet",
 	  WM_T_82544,		WMP_F_FIBER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544GC_COPPER,
 	  "Intel i82544GC 1000BASE-T Ethernet",
 	  WM_T_82544,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544GC_LOM,
 	  "Intel i82544GC (LOM) 1000BASE-T Ethernet",
 	  WM_T_82544,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EM,
 	  "Intel i82540EM 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EM_LOM,
 	  "Intel i82540EM (LOM) 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP_LOM,
 	  "Intel i82540EP 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP,
 	  "Intel i82540EP 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP_LP,
 	  "Intel i82540EP 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545EM_COPPER,
 	  "Intel i82545EM 1000BASE-T Ethernet",
 	  WM_T_82545,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_COPPER,
 	  "Intel i82545GM 1000BASE-T Ethernet",
 	  WM_T_82545_3,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_FIBER,
 	  "Intel i82545GM 1000BASE-X Ethernet",
 	  WM_T_82545_3,		WMP_F_FIBER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_SERDES,
 	  "Intel i82545GM Gigabit Ethernet (SERDES)",
 	  WM_T_82545_3,		WMP_F_SERDES },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_COPPER,
 	  "Intel i82546EB 1000BASE-T Ethernet",
 	  WM_T_82546,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_QUAD,
 	  "Intel i82546EB 1000BASE-T Ethernet",
 	  WM_T_82546,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545EM_FIBER,
 	  "Intel i82545EM 1000BASE-X Ethernet",
 	  WM_T_82545,		WMP_F_FIBER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_FIBER,
 	  "Intel i82546EB 1000BASE-X Ethernet",
 	  WM_T_82546,		WMP_F_FIBER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_COPPER,
 	  "Intel i82546GB 1000BASE-T Ethernet",
 	  WM_T_82546_3,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_FIBER,
 	  "Intel i82546GB 1000BASE-X Ethernet",
 	  WM_T_82546_3,		WMP_F_FIBER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_SERDES,
 	  "Intel i82546GB Gigabit Ethernet (SERDES)",
 	  WM_T_82546_3,		WMP_F_SERDES },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER,
 	  "i82546GB quad-port Gigabit Ethernet",
 	  WM_T_82546_3,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER_KSP3,
 	  "i82546GB quad-port Gigabit Ethernet (KSP3)",
 	  WM_T_82546_3,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_PCIE,
 	  "Intel PRO/1000MT (82546GB)",
 	  WM_T_82546_3,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541EI,
 	  "Intel i82541EI 1000BASE-T Ethernet",
 	  WM_T_82541,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541ER_LOM,
 	  "Intel i82541ER (LOM) 1000BASE-T Ethernet",
 	  WM_T_82541,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541EI_MOBILE,
 	  "Intel i82541EI Mobile 1000BASE-T Ethernet",
 	  WM_T_82541,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541ER,
 	  "Intel i82541ER 1000BASE-T Ethernet",
 	  WM_T_82541_2,		WMP_F_COPPER },
 @@ -1680,2021 +1680,2021 @@ wm_attach(device_t parent, device_t self
 	pci_intr_type_t max_type;
 	const char *eetype, *xname;
 	bus_space_tag_t memt;
 	bus_space_handle_t memh;
 	bus_size_t memsize;
 	int memh_valid;
 	int i, error;
 	const struct wm_product *wmp;
 	prop_data_t ea;
 	prop_number_t pn;
 	uint8_t enaddr[ETHER_ADDR_LEN];
 	char buf[256];
 	uint16_t cfg1, cfg2, swdpin, nvmword;
 	pcireg_t preg, memtype;
 	uint16_t eeprom_data, apme_mask;
 	bool force_clear_smbi;
 	uint32_t link_mode;
 	uint32_t reg;
 	sc->sc_dev = self;
 	callout_init(&sc->sc_tick_ch, CALLOUT_FLAGS);
 	sc->sc_core_stopping = false;
 	wmp = wm_lookup(pa);
 #ifdef DIAGNOSTIC
 	if (wmp == NULL) {
 		printf("\n");
 		panic("wm_attach: impossible");
+	}
 #endif
 	sc->sc_mediatype = WMP_MEDIATYPE(wmp->wmp_flags);
 	sc->sc_pc = pa->pa_pc;
 	sc->sc_pcitag = pa->pa_tag;
 	if (pci_dma64_available(pa))
 		sc->sc_dmat = pa->pa_dmat64;
 	else
 		sc->sc_dmat = pa->pa_dmat;
 	sc->sc_pcidevid = PCI_PRODUCT(pa->pa_id);
 	sc->sc_rev = PCI_REVISION(pci_conf_read(pc, pa->pa_tag,PCI_CLASS_REG));
 	pci_aprint_devinfo_fancy(pa, "Ethernet controller", wmp->wmp_name, 1);
 	sc->sc_type = wmp->wmp_type;
 	/* Set default function pointers */
 	sc->phy.acquire = sc->nvm.acquire = wm_get_null;
 	sc->phy.release = sc->nvm.release = wm_put_null;
 	sc->phy.reset_delay_us = (sc->sc_type >= WM_T_82571) ? 100 : 10000;
 	if (sc->sc_type < WM_T_82543) {
 		if (sc->sc_rev < 2) {
 			aprint_error_dev(sc->sc_dev,
 			    "i82542 must be at least rev. 2\n");
 			return;
+		}
 		if (sc->sc_rev < 3)
 			sc->sc_type = WM_T_82542_2_0;
+	}
 	/*
 	 * Disable MSI for Errata:
 	 * "Message Signaled Interrupt Feature May Corrupt Write Transactions"
+	 *
 	 *  82544: Errata 25
 	 *  82540: Errata  6 (easy to reproduce device timeout)
 	 *  82545: Errata  4 (easy to reproduce device timeout)
 	 *  82546: Errata 26 (easy to reproduce device timeout)
 	 *  82541: Errata  7 (easy to reproduce device timeout)
+	 *
 	 * "Byte Enables 2 and 3 are not set on MSI writes"
+	 *
 	 *  82571 & 82572: Errata 63
 	 */
 	if ((sc->sc_type <= WM_T_82541_2) || (sc->sc_type == WM_T_82571)
 	    || (sc->sc_type == WM_T_82572))
 		pa->pa_flags &= ~PCI_FLAGS_MSI_OKAY;
 	if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
 	    || (sc->sc_type == WM_T_82580)
 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)
 	    || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211))
 		sc->sc_flags |= WM_F_NEWQUEUE;
 	/* Set device properties (mactype) */
 	dict = device_properties(sc->sc_dev);
 	prop_dictionary_set_uint32(dict, "mactype", sc->sc_type);
 	/*
 	 * Map the device.  All devices support memory-mapped acccess,
 	 * and it is really required for normal operation.
 	 */
 	memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA);
 	switch (memtype) {
 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
 		memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA,
 		    memtype, 0, &memt, &memh, NULL, &memsize) == 0);
 		break;
 	default:
 		memh_valid = 0;
 		break;
+	}
 	if (memh_valid) {
 		sc->sc_st = memt;
 		sc->sc_sh = memh;
 		sc->sc_ss = memsize;
 	} else {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to map device registers\n");
 		return;
+	}
 	/*
 	 * In addition, i82544 and later support I/O mapped indirect
 	 * register access.  It is not desirable (nor supported in
 	 * this driver) to use it for normal operation, though it is
 	 * required to work around bugs in some chip versions.
 	 */
 	if (sc->sc_type >= WM_T_82544) {
 		/* First we have to find the I/O BAR. */
 		for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) {
 			memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, i);
 			if (memtype == PCI_MAPREG_TYPE_IO)
 				break;
 			if (PCI_MAPREG_MEM_TYPE(memtype) ==
 			    PCI_MAPREG_MEM_TYPE_64BIT)
 				i += 4;	/* skip high bits, too */
+		}
 		if (i < PCI_MAPREG_END) {
 			/*
 			 * We found PCI_MAPREG_TYPE_IO. Note that 82580
 			 * (and newer?) chip has no PCI_MAPREG_TYPE_IO.
 			 * It's no problem because newer chips has no this
 			 * bug.
+			 *
 			 * The i8254x doesn't apparently respond when the
 			 * I/O BAR is 0, which looks somewhat like it's not
 			 * been configured.
 			 */
 			preg = pci_conf_read(pc, pa->pa_tag, i);
 			if (PCI_MAPREG_MEM_ADDR(preg) == 0) {
 				aprint_error_dev(sc->sc_dev,
 				    "WARNING: I/O BAR at zero.\n");
 			} else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO,
 , &sc->sc_iot, &sc->sc_ioh,
 					NULL, &sc->sc_ios) == 0) {
 				sc->sc_flags |= WM_F_IOH_VALID;
 			} else {
 				aprint_error_dev(sc->sc_dev,
 				    "WARNING: unable to map I/O space\n");
+			}
+		}
+	}
 	/* Enable bus mastering.  Disable MWI on the i82542 2.0. */
 	preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
 	preg |= PCI_COMMAND_MASTER_ENABLE;
 	if (sc->sc_type < WM_T_82542_2_1)
 		preg &= ~PCI_COMMAND_INVALIDATE_ENABLE;
 	pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg);
 	/* power up chip */
 	if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self,
 	    NULL)) && error != EOPNOTSUPP) {
 		aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error);
 		return;
+	}
 	wm_adjust_qnum(sc, pci_msix_count(pa->pa_pc, pa->pa_tag));
 	/* Allocation settings */
 	max_type = PCI_INTR_TYPE_MSIX;
 	/*
 	 * 82583 has a MSI-X capability in the PCI configuration space but
 	 * it doesn't support it. At least the document doesn't say anything
 	 * about MSI-X.
 	 */
 	counts[PCI_INTR_TYPE_MSIX]
 	    = (sc->sc_type == WM_T_82583) ? 0 : sc->sc_nqueues + 1;
 	counts[PCI_INTR_TYPE_MSI] = 1;
 	counts[PCI_INTR_TYPE_INTX] = 1;
 	/* overridden by disable flags */
 	if (wm_disable_msi != 0) {
 		counts[PCI_INTR_TYPE_MSI] = 0;
 		if (wm_disable_msix != 0) {
 			max_type = PCI_INTR_TYPE_INTX;
 			counts[PCI_INTR_TYPE_MSIX] = 0;
+		}
 	} else if (wm_disable_msix != 0) {
 		max_type = PCI_INTR_TYPE_MSI;
 		counts[PCI_INTR_TYPE_MSIX] = 0;
+	}
 alloc_retry:
 	if (pci_intr_alloc(pa, &sc->sc_intrs, counts, max_type) != 0) {
 		aprint_error_dev(sc->sc_dev, "failed to allocate interrupt\n");
 		return;
+	}
 	if (pci_intr_type(pc, sc->sc_intrs[0]) == PCI_INTR_TYPE_MSIX) {
 		error = wm_setup_msix(sc);
 		if (error) {
 			pci_intr_release(pc, sc->sc_intrs,
 			    counts[PCI_INTR_TYPE_MSIX]);
 			/* Setup for MSI: Disable MSI-X */
 			max_type = PCI_INTR_TYPE_MSI;
 			counts[PCI_INTR_TYPE_MSI] = 1;
 			counts[PCI_INTR_TYPE_INTX] = 1;
 			goto alloc_retry;
+		}
 	} else 	if (pci_intr_type(pc, sc->sc_intrs[0]) == PCI_INTR_TYPE_MSI) {
 		wm_adjust_qnum(sc, 0);	/* must not use multiqueue */
 		error = wm_setup_legacy(sc);
 		if (error) {
 			pci_intr_release(sc->sc_pc, sc->sc_intrs,
 			    counts[PCI_INTR_TYPE_MSI]);
 			/* The next try is for INTx: Disable MSI */
 			max_type = PCI_INTR_TYPE_INTX;
 			counts[PCI_INTR_TYPE_INTX] = 1;
 			goto alloc_retry;
+		}
 	} else {
 		wm_adjust_qnum(sc, 0);	/* must not use multiqueue */
 		error = wm_setup_legacy(sc);
 		if (error) {
 			pci_intr_release(sc->sc_pc, sc->sc_intrs,
 			    counts[PCI_INTR_TYPE_INTX]);
 			return;
+		}
+	}
 	/*
 	 * Check the function ID (unit number of the chip).
 	 */
 	if ((sc->sc_type == WM_T_82546) || (sc->sc_type == WM_T_82546_3)
 	    || (sc->sc_type ==  WM_T_82571) || (sc->sc_type == WM_T_80003)
 	    || (sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
 	    || (sc->sc_type == WM_T_82580)
 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354))
 		sc->sc_funcid = (CSR_READ(sc, WMREG_STATUS)
 		    >> STATUS_FUNCID_SHIFT) & STATUS_FUNCID_MASK;
 	else
 		sc->sc_funcid = 0;
 	/*
 	 * Determine a few things about the bus we're connected to.
 	 */
 	if (sc->sc_type < WM_T_82543) {
 		/* We don't really know the bus characteristics here. */
 		sc->sc_bus_speed = 33;
 	} else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) {
 		/*
 		 * CSA (Communication Streaming Architecture) is about as fast
 		 * a 32-bit 66MHz PCI Bus.
 		 */
 		sc->sc_flags |= WM_F_CSA;
 		sc->sc_bus_speed = 66;
 		aprint_verbose_dev(sc->sc_dev,
 		    "Communication Streaming Architecture\n");
 		if (sc->sc_type == WM_T_82547) {
 			callout_init(&sc->sc_txfifo_ch, CALLOUT_FLAGS);
 			callout_setfunc(&sc->sc_txfifo_ch,
 					wm_82547_txfifo_stall, sc);
 			aprint_verbose_dev(sc->sc_dev,
 			    "using 82547 Tx FIFO stall work-around\n");
+		}
 	} else if (sc->sc_type >= WM_T_82571) {
 		sc->sc_flags |= WM_F_PCIE;
 		if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9)
 		    && (sc->sc_type != WM_T_ICH10)
 		    && (sc->sc_type != WM_T_PCH)
 		    && (sc->sc_type != WM_T_PCH2)
 		    && (sc->sc_type != WM_T_PCH_LPT)
 		    && (sc->sc_type != WM_T_PCH_SPT)) {
 			/* ICH* and PCH* have no PCIe capability registers */
 			if (pci_get_capability(pa->pa_pc, pa->pa_tag,
 				PCI_CAP_PCIEXPRESS, &sc->sc_pcixe_capoff,
 				NULL) == 0)
 				aprint_error_dev(sc->sc_dev,
 				    "unable to find PCIe capability\n");
+		}
 		aprint_verbose_dev(sc->sc_dev, "PCI-Express bus\n");
 	} else {
 		reg = CSR_READ(sc, WMREG_STATUS);
 		if (reg & STATUS_BUS64)
 			sc->sc_flags |= WM_F_BUS64;
 		if ((reg & STATUS_PCIX_MODE) != 0) {
 			pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb;
 			sc->sc_flags |= WM_F_PCIX;
 			if (pci_get_capability(pa->pa_pc, pa->pa_tag,
 				PCI_CAP_PCIX, &sc->sc_pcixe_capoff, NULL) == 0)
 				aprint_error_dev(sc->sc_dev,
 				    "unable to find PCIX capability\n");
 			else if (sc->sc_type != WM_T_82545_3 &&
 				 sc->sc_type != WM_T_82546_3) {
 				/*
 				 * Work around a problem caused by the BIOS
 				 * setting the max memory read byte count
 				 * incorrectly.
 				 */
 				pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag,
 				    sc->sc_pcixe_capoff + PCIX_CMD);
 				pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag,
 				    sc->sc_pcixe_capoff + PCIX_STATUS);
 				bytecnt = (pcix_cmd & PCIX_CMD_BYTECNT_MASK) >>
 				    PCIX_CMD_BYTECNT_SHIFT;
 				maxb = (pcix_sts & PCIX_STATUS_MAXB_MASK) >>
 				    PCIX_STATUS_MAXB_SHIFT;
 				if (bytecnt > maxb) {
 					aprint_verbose_dev(sc->sc_dev,
 					    "resetting PCI-X MMRBC: %d -> %d\n",
 << bytecnt, 512 << maxb);
 					pcix_cmd = (pcix_cmd &
 					    ~PCIX_CMD_BYTECNT_MASK) |
 					   (maxb << PCIX_CMD_BYTECNT_SHIFT);
 					pci_conf_write(pa->pa_pc, pa->pa_tag,
 					    sc->sc_pcixe_capoff + PCIX_CMD,
 					    pcix_cmd);
+				}
+			}
+		}
 		/*
 		 * The quad port adapter is special; it has a PCIX-PCIX
 		 * bridge on the board, and can run the secondary bus at
 		 * a higher speed.
 		 */
 		if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) {
 			sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120
 								      : 66;
 		} else if (sc->sc_flags & WM_F_PCIX) {
 			switch (reg & STATUS_PCIXSPD_MASK) {
 			case STATUS_PCIXSPD_50_66:
 				sc->sc_bus_speed = 66;
 				break;
 			case STATUS_PCIXSPD_66_100:
 				sc->sc_bus_speed = 100;
 				break;
 			case STATUS_PCIXSPD_100_133:
 				sc->sc_bus_speed = 133;
 				break;
 			default:
 				aprint_error_dev(sc->sc_dev,
 				    "unknown PCIXSPD %d; assuming 66MHz\n",
 				    reg & STATUS_PCIXSPD_MASK);
 				sc->sc_bus_speed = 66;
 				break;
+			}
 		} else
 			sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33;
 		aprint_verbose_dev(sc->sc_dev, "%d-bit %dMHz %s bus\n",
 		    (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed,
 		    (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI");
+	}
 	/* clear interesting stat counters */
 	CSR_READ(sc, WMREG_COLC);
 	CSR_READ(sc, WMREG_RXERRC);
 	if ((sc->sc_type == WM_T_82574) || (sc->sc_type == WM_T_82583)
 	    || (sc->sc_type >= WM_T_ICH8))
 		sc->sc_ich_phymtx = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
 	if (sc->sc_type >= WM_T_ICH8)
 		sc->sc_ich_nvmmtx = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
 	/* Set PHY, NVM mutex related stuff */
 	switch (sc->sc_type) {
 	case WM_T_82542_2_0:
 	case WM_T_82542_2_1:
 	case WM_T_82543:
 	case WM_T_82544:
 		/* Microwire */
 		sc->nvm.read = wm_nvm_read_uwire;
 		sc->sc_nvm_wordsize = 64;
 		sc->sc_nvm_addrbits = 6;
 		break;
 	case WM_T_82540:
 	case WM_T_82545:
 	case WM_T_82545_3:
 	case WM_T_82546:
 	case WM_T_82546_3:
 		/* Microwire */
 		sc->nvm.read = wm_nvm_read_uwire;
 		reg = CSR_READ(sc, WMREG_EECD);
 		if (reg & EECD_EE_SIZE) {
 			sc->sc_nvm_wordsize = 256;
 			sc->sc_nvm_addrbits = 8;
 		} else {
 			sc->sc_nvm_wordsize = 64;
 			sc->sc_nvm_addrbits = 6;
+		}
 		sc->sc_flags |= WM_F_LOCK_EECD;
 		sc->nvm.acquire = wm_get_eecd;
 		sc->nvm.release = wm_put_eecd;
 		break;
 	case WM_T_82541:
 	case WM_T_82541_2:
 	case WM_T_82547:
 	case WM_T_82547_2:
 		reg = CSR_READ(sc, WMREG_EECD);
 		/*
 		 * wm_nvm_set_addrbits_size_eecd() accesses SPI in it only
 		 * on 8254[17], so set flags and functios before calling it.
 		 */
 		sc->sc_flags |= WM_F_LOCK_EECD;
 		sc->nvm.acquire = wm_get_eecd;
 		sc->nvm.release = wm_put_eecd;
 		if (reg & EECD_EE_TYPE) {
 			/* SPI */
 			sc->nvm.read = wm_nvm_read_spi;
 			sc->sc_flags |= WM_F_EEPROM_SPI;
 			wm_nvm_set_addrbits_size_eecd(sc);
 		} else {
 			/* Microwire */
 			sc->nvm.read = wm_nvm_read_uwire;
 			if ((reg & EECD_EE_ABITS) != 0) {
 				sc->sc_nvm_wordsize = 256;
 				sc->sc_nvm_addrbits = 8;
 			} else {
 				sc->sc_nvm_wordsize = 64;
 				sc->sc_nvm_addrbits = 6;
+			}
+		}
 		break;
 	case WM_T_82571:
 	case WM_T_82572:
 		/* SPI */
 		sc->nvm.read = wm_nvm_read_eerd;
 		/* Not use WM_F_LOCK_EECD because we use EERD */
 		sc->sc_flags |= WM_F_EEPROM_SPI;
 		wm_nvm_set_addrbits_size_eecd(sc);
 		sc->phy.acquire = wm_get_swsm_semaphore;
 		sc->phy.release = wm_put_swsm_semaphore;
 		sc->nvm.acquire = wm_get_nvm_82571;
 		sc->nvm.release = wm_put_nvm_82571;
 		break;
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82583:
 		sc->nvm.read = wm_nvm_read_eerd;
 		/* Not use WM_F_LOCK_EECD because we use EERD */
 		if (sc->sc_type == WM_T_82573) {
 			sc->phy.acquire = wm_get_swsm_semaphore;
 			sc->phy.release = wm_put_swsm_semaphore;
 			sc->nvm.acquire = wm_get_nvm_82571;
 			sc->nvm.release = wm_put_nvm_82571;
 		} else {
 			/* Both PHY and NVM use the same semaphore. */
 			sc->phy.acquire = sc->nvm.acquire
 			    = wm_get_swfwhw_semaphore;
 			sc->phy.release = sc->nvm.release
 			    = wm_put_swfwhw_semaphore;
+		}
 		if (wm_nvm_is_onboard_eeprom(sc) == 0) {
 			sc->sc_flags |= WM_F_EEPROM_FLASH;
 			sc->sc_nvm_wordsize = 2048;
 		} else {
 			/* SPI */
 			sc->sc_flags |= WM_F_EEPROM_SPI;
 			wm_nvm_set_addrbits_size_eecd(sc);
+		}
 		break;
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_82580:
 	case WM_T_I350:
 	case WM_T_I354:
 	case WM_T_80003:
 		/* SPI */
 		sc->sc_flags |= WM_F_EEPROM_SPI;
 		wm_nvm_set_addrbits_size_eecd(sc);
 		if((sc->sc_type == WM_T_80003)
 		    || (sc->sc_nvm_wordsize < (1 << 15))) {
 			sc->nvm.read = wm_nvm_read_eerd;
 			/* Don't use WM_F_LOCK_EECD because we use EERD */
 		} else {
 			sc->nvm.read = wm_nvm_read_spi;
 			sc->sc_flags |= WM_F_LOCK_EECD;
+		}
 		sc->phy.acquire = wm_get_phy_82575;
 		sc->phy.release = wm_put_phy_82575;
 		sc->nvm.acquire = wm_get_nvm_80003;
 		sc->nvm.release = wm_put_nvm_80003;
 		break;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		sc->nvm.read = wm_nvm_read_ich8;
 		/* FLASH */
 		sc->sc_flags |= WM_F_EEPROM_FLASH;
 		sc->sc_nvm_wordsize = 2048;
 		memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag,WM_ICH8_FLASH);
 		if (pci_mapreg_map(pa, WM_ICH8_FLASH, memtype, 0,
 		    &sc->sc_flasht, &sc->sc_flashh, NULL, &sc->sc_flashs)) {
 			aprint_error_dev(sc->sc_dev,
 			    "can't map FLASH registers\n");
 			goto out;
+		}
 		reg = ICH8_FLASH_READ32(sc, ICH_FLASH_GFPREG);
 		sc->sc_ich8_flash_base = (reg & ICH_GFPREG_BASE_MASK) *
 		    ICH_FLASH_SECTOR_SIZE;
 		sc->sc_ich8_flash_bank_size =
 		    ((reg >> 16) & ICH_GFPREG_BASE_MASK) + 1;
 		sc->sc_ich8_flash_bank_size -= (reg & ICH_GFPREG_BASE_MASK);
 		sc->sc_ich8_flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
 		sc->sc_ich8_flash_bank_size /= 2 * sizeof(uint16_t);
 		sc->sc_flashreg_offset = 0;
 		sc->phy.acquire = wm_get_swflag_ich8lan;
 		sc->phy.release = wm_put_swflag_ich8lan;
 		sc->nvm.acquire = wm_get_nvm_ich8lan;
 		sc->nvm.release = wm_put_nvm_ich8lan;
 		break;
 	case WM_T_PCH_SPT:
 		sc->nvm.read = wm_nvm_read_spt;
 		/* SPT has no GFPREG; flash registers mapped through BAR0 */
 		sc->sc_flags |= WM_F_EEPROM_FLASH;
 		sc->sc_flasht = sc->sc_st;
 		sc->sc_flashh = sc->sc_sh;
 		sc->sc_ich8_flash_base = 0;
 		sc->sc_nvm_wordsize =
 			(((CSR_READ(sc, WMREG_STRAP) >> 1) & 0x1F) + 1)
 			* NVM_SIZE_MULTIPLIER;
 		/* It is size in bytes, we want words */
 		sc->sc_nvm_wordsize /= 2;
 		/* assume 2 banks */
 		sc->sc_ich8_flash_bank_size = sc->sc_nvm_wordsize / 2;
 		sc->sc_flashreg_offset = WM_PCH_SPT_FLASHOFFSET;
 		sc->phy.acquire = wm_get_swflag_ich8lan;
 		sc->phy.release = wm_put_swflag_ich8lan;
 		sc->nvm.acquire = wm_get_nvm_ich8lan;
 		sc->nvm.release = wm_put_nvm_ich8lan;
 		break;
 	case WM_T_I210:
 	case WM_T_I211:
 		/* Allow a single clear of the SW semaphore on I210 and newer*/
 		sc->sc_flags |= WM_F_WA_I210_CLSEM;
 		if (wm_nvm_get_flash_presence_i210(sc)) {
 			sc->nvm.read = wm_nvm_read_eerd;
 			/* Don't use WM_F_LOCK_EECD because we use EERD */
 			sc->sc_flags |= WM_F_EEPROM_FLASH_HW;
 			wm_nvm_set_addrbits_size_eecd(sc);
 		} else {
 			sc->nvm.read = wm_nvm_read_invm;
 			sc->sc_flags |= WM_F_EEPROM_INVM;
 			sc->sc_nvm_wordsize = INVM_SIZE;
+		}
 		sc->phy.acquire = wm_get_phy_82575;
 		sc->phy.release = wm_put_phy_82575;
 		sc->nvm.acquire = wm_get_nvm_80003;
 		sc->nvm.release = wm_put_nvm_80003;
 		break;
 	default:
 		break;
+	}
 	/* Ensure the SMBI bit is clear before first NVM or PHY access */
 	switch (sc->sc_type) {
 	case WM_T_82571:
 	case WM_T_82572:
 		reg = CSR_READ(sc, WMREG_SWSM2);
 		if ((reg & SWSM2_LOCK) == 0) {
 			CSR_WRITE(sc, WMREG_SWSM2, reg | SWSM2_LOCK);
 			force_clear_smbi = true;
 		} else
 			force_clear_smbi = false;
 		break;
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82583:
 		force_clear_smbi = true;
 		break;
 	default:
 		force_clear_smbi = false;
 		break;
+	}
 	if (force_clear_smbi) {
 		reg = CSR_READ(sc, WMREG_SWSM);
 		if ((reg & SWSM_SMBI) != 0)
 			aprint_error_dev(sc->sc_dev,
 			    "Please update the Bootagent\n");
 		CSR_WRITE(sc, WMREG_SWSM, reg & ~SWSM_SMBI);
+	}
 	/*
 	 * Defer printing the EEPROM type until after verifying the checksum
 	 * This allows the EEPROM type to be printed correctly in the case
 	 * that no EEPROM is attached.
 	 */
 	/*
 	 * Validate the EEPROM checksum. If the checksum fails, flag
 	 * this for later, so we can fail future reads from the EEPROM.
 	 */
 	if (wm_nvm_validate_checksum(sc)) {
 		/*
 		 * Read twice again because some PCI-e parts fail the
 		 * first check due to the link being in sleep state.
 		 */
 		if (wm_nvm_validate_checksum(sc))
 			sc->sc_flags |= WM_F_EEPROM_INVALID;
+	}
 	if (sc->sc_flags & WM_F_EEPROM_INVALID)
 		aprint_verbose_dev(sc->sc_dev, "No EEPROM");
 	else {
 		aprint_verbose_dev(sc->sc_dev, "%u words ",
 		    sc->sc_nvm_wordsize);
 		if (sc->sc_flags & WM_F_EEPROM_INVM)
 			aprint_verbose("iNVM");
 		else if (sc->sc_flags & WM_F_EEPROM_FLASH_HW)
 			aprint_verbose("FLASH(HW)");
 		else if (sc->sc_flags & WM_F_EEPROM_FLASH)
 			aprint_verbose("FLASH");
 		else {
 			if (sc->sc_flags & WM_F_EEPROM_SPI)
 				eetype = "SPI";
 			else
 				eetype = "MicroWire";
 			aprint_verbose("(%d address bits) %s EEPROM",
 			    sc->sc_nvm_addrbits, eetype);
+		}
+	}
 	wm_nvm_version(sc);
 	aprint_verbose("\n");
 	/*
 	 * XXX The first call of wm_gmii_setup_phytype. The result might be
 	 * incorrect.
 	 */
 	wm_gmii_setup_phytype(sc, 0, 0);
 	/* Reset the chip to a known state. */
 	wm_reset(sc);
 	/* Check for I21[01] PLL workaround */
 	if (sc->sc_type == WM_T_I210)
 		sc->sc_flags |= WM_F_PLL_WA_I210;
 	if ((sc->sc_type == WM_T_I210) && wm_nvm_get_flash_presence_i210(sc)) {
 		/* NVM image release 3.25 has a workaround */
 		if ((sc->sc_nvm_ver_major < 3)
 		    || ((sc->sc_nvm_ver_major == 3)
 			&& (sc->sc_nvm_ver_minor < 25))) {
 			aprint_verbose_dev(sc->sc_dev,
 			    "ROM image version %d.%d is older than 3.25\n",
 			    sc->sc_nvm_ver_major, sc->sc_nvm_ver_minor);
 			sc->sc_flags |= WM_F_PLL_WA_I210;
+		}
+	}
 	if ((sc->sc_flags & WM_F_PLL_WA_I210) != 0)
 		wm_pll_workaround_i210(sc);
 	wm_get_wakeup(sc);
 	/* Non-AMT based hardware can now take control from firmware */
 	if ((sc->sc_flags & WM_F_HAS_AMT) == 0)
 		wm_get_hw_control(sc);
 	/*
 	 * Read the Ethernet address from the EEPROM, if not first found
 	 * in device properties.
 	 */
 	ea = prop_dictionary_get(dict, "mac-address");
 	if (ea != NULL) {
 		KASSERT(prop_object_type(ea) == PROP_TYPE_DATA);
 		KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN);
 		memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN);
 	} else {
 		if (wm_read_mac_addr(sc, enaddr) != 0) {
 			aprint_error_dev(sc->sc_dev,
 			    "unable to read Ethernet address\n");
 			goto out;
+		}
+	}
 	aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n",
 	    ether_sprintf(enaddr));
 	/*
 	 * Read the config info from the EEPROM, and set up various
 	 * bits in the control registers based on their contents.
 	 */
 	pn = prop_dictionary_get(dict, "i82543-cfg1");
 	if (pn != NULL) {
 		KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
 		cfg1 = (uint16_t) prop_number_integer_value(pn);
 	} else {
 		if (wm_nvm_read(sc, NVM_OFF_CFG1, 1, &cfg1)) {
 			aprint_error_dev(sc->sc_dev, "unable to read CFG1\n");
 			goto out;
+		}
+	}
 	pn = prop_dictionary_get(dict, "i82543-cfg2");
 	if (pn != NULL) {
 		KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
 		cfg2 = (uint16_t) prop_number_integer_value(pn);
 	} else {
 		if (wm_nvm_read(sc, NVM_OFF_CFG2, 1, &cfg2)) {
 			aprint_error_dev(sc->sc_dev, "unable to read CFG2\n");
 			goto out;
+		}
+	}
 	/* check for WM_F_WOL */
 	switch (sc->sc_type) {
 	case WM_T_82542_2_0:
 	case WM_T_82542_2_1:
 	case WM_T_82543:
 		/* dummy? */
 		eeprom_data = 0;
 		apme_mask = NVM_CFG3_APME;
 		break;
 	case WM_T_82544:
 		apme_mask = NVM_CFG2_82544_APM_EN;
 		eeprom_data = cfg2;
 		break;
 	case WM_T_82546:
 	case WM_T_82546_3:
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82583:
 	case WM_T_80003:
 	default:
 		apme_mask = NVM_CFG3_APME;
 		wm_nvm_read(sc, (sc->sc_funcid == 1) ? NVM_OFF_CFG3_PORTB
 		    : NVM_OFF_CFG3_PORTA, 1, &eeprom_data);
 		break;
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_82580:
 	case WM_T_I350:
 	case WM_T_I354: /* XXX ok? */
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
 		/* XXX The funcid should be checked on some devices */
 		apme_mask = WUC_APME;
 		eeprom_data = CSR_READ(sc, WMREG_WUC);
 		break;
+	}
 	/* Check for WM_F_WOL flag after the setting of the EEPROM stuff */
 	if ((eeprom_data & apme_mask) != 0)
 		sc->sc_flags |= WM_F_WOL;
 	if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)) {
 		/* Check NVM for autonegotiation */
 		if (wm_nvm_read(sc, NVM_OFF_COMPAT, 1, &nvmword) == 0) {
 			if ((nvmword & NVM_COMPAT_SERDES_FORCE_MODE) != 0)
 				sc->sc_flags |= WM_F_PCS_DIS_AUTONEGO;
+		}
+	}
 	/*
 	 * XXX need special handling for some multiple port cards
 	 * to disable a paticular port.
 	 */
 	if (sc->sc_type >= WM_T_82544) {
 		pn = prop_dictionary_get(dict, "i82543-swdpin");
 		if (pn != NULL) {
 			KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
 			swdpin = (uint16_t) prop_number_integer_value(pn);
 		} else {
 			if (wm_nvm_read(sc, NVM_OFF_SWDPIN, 1, &swdpin)) {
 				aprint_error_dev(sc->sc_dev,
 				    "unable to read SWDPIN\n");
 				goto out;
+			}
+		}
+	}
 	if (cfg1 & NVM_CFG1_ILOS)
 		sc->sc_ctrl |= CTRL_ILOS;
 	/*
 	 * XXX
 	 * This code isn't correct because pin 2 and 3 are located
 	 * in different position on newer chips. Check all datasheet.
+	 *
 	 * Until resolve this problem, check if a chip < 82580
 	 */
 	if (sc->sc_type <= WM_T_82580) {
 		if (sc->sc_type >= WM_T_82544) {
 			sc->sc_ctrl |=
 			    ((swdpin >> NVM_SWDPIN_SWDPIO_SHIFT) & 0xf) <<
 			    CTRL_SWDPIO_SHIFT;
 			sc->sc_ctrl |=
 			    ((swdpin >> NVM_SWDPIN_SWDPIN_SHIFT) & 0xf) <<
 			    CTRL_SWDPINS_SHIFT;
 		} else {
 			sc->sc_ctrl |=
 			    ((cfg1 >> NVM_CFG1_SWDPIO_SHIFT) & 0xf) <<
 			    CTRL_SWDPIO_SHIFT;
+		}
+	}
 	/* XXX For other than 82580? */
 	if (sc->sc_type == WM_T_82580) {
 		wm_nvm_read(sc, NVM_OFF_CFG3_PORTA, 1, &nvmword);
 		if (nvmword & __BIT(13))
 			sc->sc_ctrl |= CTRL_ILOS;
+	}
 #if 0
 	if (sc->sc_type >= WM_T_82544) {
 		if (cfg1 & NVM_CFG1_IPS0)
 			sc->sc_ctrl_ext |= CTRL_EXT_IPS;
 		if (cfg1 & NVM_CFG1_IPS1)
 			sc->sc_ctrl_ext |= CTRL_EXT_IPS1;
 		sc->sc_ctrl_ext |=
 		    ((swdpin >> (NVM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) <<
 		    CTRL_EXT_SWDPIO_SHIFT;
 		sc->sc_ctrl_ext |=
 		    ((swdpin >> (NVM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) <<
 		    CTRL_EXT_SWDPINS_SHIFT;
 	} else {
 		sc->sc_ctrl_ext |=
 		    ((cfg2 >> NVM_CFG2_SWDPIO_SHIFT) & 0xf) <<
 		    CTRL_EXT_SWDPIO_SHIFT;
+	}
 #endif
 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 #if 0
 	CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext);
 #endif
 	if (sc->sc_type == WM_T_PCH) {
 		uint16_t val;
 		/* Save the NVM K1 bit setting */
 		wm_nvm_read(sc, NVM_OFF_K1_CONFIG, 1, &val);
 		if ((val & NVM_K1_CONFIG_ENABLE) != 0)
 			sc->sc_nvm_k1_enabled = 1;
 		else
 			sc->sc_nvm_k1_enabled = 0;
+	}
 	/* Determine if we're GMII, TBI, SERDES or SGMII mode */
 	if (sc->sc_type == WM_T_ICH8 || sc->sc_type == WM_T_ICH9
 	    || sc->sc_type == WM_T_ICH10 || sc->sc_type == WM_T_PCH
 	    || sc->sc_type == WM_T_PCH2 || sc->sc_type == WM_T_PCH_LPT
 	    || sc->sc_type == WM_T_PCH_SPT || sc->sc_type == WM_T_82573
 	    || sc->sc_type == WM_T_82574 || sc->sc_type == WM_T_82583) {
 		/* Copper only */
 	} else if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
 	    || (sc->sc_type ==WM_T_82580) || (sc->sc_type ==WM_T_I350)
 	    || (sc->sc_type ==WM_T_I354) || (sc->sc_type ==WM_T_I210)
 	    || (sc->sc_type ==WM_T_I211)) {
 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
 		link_mode = reg & CTRL_EXT_LINK_MODE_MASK;
 		switch (link_mode) {
 		case CTRL_EXT_LINK_MODE_1000KX:
 			aprint_verbose_dev(sc->sc_dev, "1000KX\n");
 			sc->sc_mediatype = WM_MEDIATYPE_SERDES;
 			break;
 		case CTRL_EXT_LINK_MODE_SGMII:
 			if (wm_sgmii_uses_mdio(sc)) {
 				aprint_verbose_dev(sc->sc_dev,
 				    "SGMII(MDIO)\n");
 				sc->sc_flags |= WM_F_SGMII;
 				sc->sc_mediatype = WM_MEDIATYPE_COPPER;
 				break;
+			}
 			aprint_verbose_dev(sc->sc_dev, "SGMII(I2C)\n");
 			/*FALLTHROUGH*/
 		case CTRL_EXT_LINK_MODE_PCIE_SERDES:
 			sc->sc_mediatype = wm_sfp_get_media_type(sc);
 			if (sc->sc_mediatype == WM_MEDIATYPE_UNKNOWN) {
 				if (link_mode
 				    == CTRL_EXT_LINK_MODE_SGMII) {
 					sc->sc_mediatype = WM_MEDIATYPE_COPPER;
 					sc->sc_flags |= WM_F_SGMII;
 				} else {
 					sc->sc_mediatype = WM_MEDIATYPE_SERDES;
 					aprint_verbose_dev(sc->sc_dev,
 					    "SERDES\n");
+				}
 				break;
+			}
 			if (sc->sc_mediatype == WM_MEDIATYPE_SERDES)
 				aprint_verbose_dev(sc->sc_dev, "SERDES\n");
 			/* Change current link mode setting */
 			reg &= ~CTRL_EXT_LINK_MODE_MASK;
 			switch (sc->sc_mediatype) {
 			case WM_MEDIATYPE_COPPER:
 				reg |= CTRL_EXT_LINK_MODE_SGMII;
 				break;
 			case WM_MEDIATYPE_SERDES:
 				reg |= CTRL_EXT_LINK_MODE_PCIE_SERDES;
 				break;
 			default:
 				break;
+			}
 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
 			break;
 		case CTRL_EXT_LINK_MODE_GMII:
 		default:
 			aprint_verbose_dev(sc->sc_dev, "Copper\n");
 			sc->sc_mediatype = WM_MEDIATYPE_COPPER;
 			break;
+		}
 		reg &= ~CTRL_EXT_I2C_ENA;
 		if ((sc->sc_flags & WM_F_SGMII) != 0)
 			reg |= CTRL_EXT_I2C_ENA;
 		else
 			reg &= ~CTRL_EXT_I2C_ENA;
 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
 	} else if (sc->sc_type < WM_T_82543 ||
 	    (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) {
 		if (sc->sc_mediatype == WM_MEDIATYPE_COPPER) {
 			aprint_error_dev(sc->sc_dev,
 			    "WARNING: TBIMODE set on 1000BASE-T product!\n");
 			sc->sc_mediatype = WM_MEDIATYPE_FIBER;
+		}
 	} else {
 		if (sc->sc_mediatype == WM_MEDIATYPE_FIBER) {
 			aprint_error_dev(sc->sc_dev,
 			    "WARNING: TBIMODE clear on 1000BASE-X product!\n");
 			sc->sc_mediatype = WM_MEDIATYPE_COPPER;
+		}
+	}
 	snprintb(buf, sizeof(buf), WM_FLAGS, sc->sc_flags);
 	aprint_verbose_dev(sc->sc_dev, "%s\n", buf);
 	/* Set device properties (macflags) */
 	prop_dictionary_set_uint32(dict, "macflags", sc->sc_flags);
 	/* Initialize the media structures accordingly. */
 	if (sc->sc_mediatype == WM_MEDIATYPE_COPPER)
 		wm_gmii_mediainit(sc, wmp->wmp_product);
 	else
 		wm_tbi_mediainit(sc); /* All others */
 	ifp = &sc->sc_ethercom.ec_if;
 	xname = device_xname(sc->sc_dev);
 	strlcpy(ifp->if_xname, xname, IFNAMSIZ);
 	ifp->if_softc = sc;
 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 #ifdef WM_MPSAFE
 	ifp->if_extflags = IFEF_MPSAFE;
 #endif
 	ifp->if_ioctl = wm_ioctl;
 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
 		ifp->if_start = wm_nq_start;
 		/*
 		 * When the number of CPUs is one and the controller can use
 		 * MSI-X, wm(4) use MSI-X but *does not* use multiqueue.
 		 * That is, wm(4) use two interrupts, one is used for Tx/Rx
 		 * and the other is used for link status changing.
 		 * In this situation, wm_nq_transmit() is disadvantageous
 		 * because of wm_select_txqueue() and pcq(9) overhead.
 		 */
 		if (wm_is_using_multiqueue(sc))
 			ifp->if_transmit = wm_nq_transmit;
 	} else {
 		ifp->if_start = wm_start;
 		/*
 		 * wm_transmit() has the same disadvantage as wm_transmit().
 		 */
 		if (wm_is_using_multiqueue(sc))
 			ifp->if_transmit = wm_transmit;
+	}
 	ifp->if_watchdog = wm_watchdog;
 	ifp->if_init = wm_init;
 	ifp->if_stop = wm_stop;
 	IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN));
 	IFQ_SET_READY(&ifp->if_snd);
 	/* Check for jumbo frame */
 	switch (sc->sc_type) {
 	case WM_T_82573:
 		/* XXX limited to 9234 if ASPM is disabled */
 		wm_nvm_read(sc, NVM_OFF_INIT_3GIO_3, 1, &nvmword);
 		if ((nvmword & NVM_3GIO_3_ASPM_MASK) != 0)
 			sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
 		break;
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82574:
 	case WM_T_82583:
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_82580:
 	case WM_T_I350:
-	case WM_T_I354: /* XXXX ok? */
+	case WM_T_I354:
 	case WM_T_I210:
 	case WM_T_I211:
 	case WM_T_80003:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH2:	/* PCH2 supports 9K frame size */
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
 		/* XXX limited to 9234 */
 		sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
 		break;
 	case WM_T_PCH:
 		/* XXX limited to 4096 */
 		sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
 		break;
 	case WM_T_82542_2_0:
 	case WM_T_82542_2_1:
 	case WM_T_82583:
 	case WM_T_ICH8:
 		/* No support for jumbo frame */
 		break;
 	default:
 		/* ETHER_MAX_LEN_JUMBO */
 		sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
 		break;
+	}
 	/* If we're a i82543 or greater, we can support VLANs. */
 	if (sc->sc_type >= WM_T_82543)
 		sc->sc_ethercom.ec_capabilities |=
 		    ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING;
 	/*
 	 * We can perform TCPv4 and UDPv4 checkums in-bound.  Only
 	 * on i82543 and later.
 	 */
 	if (sc->sc_type >= WM_T_82543) {
 		ifp->if_capabilities |=
 		    IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
 		    IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
 		    IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
 		    IFCAP_CSUM_TCPv6_Tx |
 		    IFCAP_CSUM_UDPv6_Tx;
+	}
 	/*
 	 * XXXyamt: i'm not sure which chips support RXCSUM_IPV6OFL.
+	 *
 	 *	82541GI (8086:1076) ... no
 	 *	82572EI (8086:10b9) ... yes
 	 */
 	if (sc->sc_type >= WM_T_82571) {
 		ifp->if_capabilities |=
 		    IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx;
+	}
 	/*
 	 * If we're a i82544 or greater (except i82547), we can do
 	 * TCP segmentation offload.
 	 */
 	if (sc->sc_type >= WM_T_82544 && sc->sc_type != WM_T_82547) {
 		ifp->if_capabilities |= IFCAP_TSOv4;
+	}
 	if (sc->sc_type >= WM_T_82571) {
 		ifp->if_capabilities |= IFCAP_TSOv6;
+	}
 	sc->sc_rx_process_limit = WM_RX_PROCESS_LIMIT_DEFAULT;
 	sc->sc_rx_intr_process_limit = WM_RX_INTR_PROCESS_LIMIT_DEFAULT;
 #ifdef WM_MPSAFE
 	sc->sc_core_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
 #else
 	sc->sc_core_lock = NULL;
 #endif
 	/* Attach the interface. */
 	error = if_initialize(ifp);
 	if (error != 0) {
 		aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n",
 		    error);
 		return; /* Error */
+	}
 	sc->sc_ipq = if_percpuq_create(&sc->sc_ethercom.ec_if);
 	ether_ifattach(ifp, enaddr);
 	if_register(ifp);
 	ether_set_ifflags_cb(&sc->sc_ethercom, wm_ifflags_cb);
 	rnd_attach_source(&sc->rnd_source, xname, RND_TYPE_NET,
 			  RND_FLAG_DEFAULT);
 #ifdef WM_EVENT_COUNTERS
 	/* Attach event counters. */
 	evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR,
 	    NULL, xname, "linkintr");
 	evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC,
 	    NULL, xname, "tx_xoff");
 	evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC,
 	    NULL, xname, "tx_xon");
 	evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC,
 	    NULL, xname, "rx_xoff");
 	evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC,
 	    NULL, xname, "rx_xon");
 	evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC,
 	    NULL, xname, "rx_macctl");
 #endif /* WM_EVENT_COUNTERS */
 	if (pmf_device_register(self, wm_suspend, wm_resume))
 		pmf_class_network_register(self, ifp);
 	else
 		aprint_error_dev(self, "couldn't establish power handler\n");
 	sc->sc_flags |= WM_F_ATTACHED;
  out:
 	return;
+}
 /* The detach function (ca_detach) */
 static int
 wm_detach(device_t self, int flags __unused)
+{
 	struct wm_softc *sc = device_private(self);
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	int i;
 	if ((sc->sc_flags & WM_F_ATTACHED) == 0)
 		return 0;
 	/* Stop the interface. Callouts are stopped in it. */
 	wm_stop(ifp, 1);
 	pmf_device_deregister(self);
 #ifdef WM_EVENT_COUNTERS
 	evcnt_detach(&sc->sc_ev_linkintr);
 	evcnt_detach(&sc->sc_ev_tx_xoff);
 	evcnt_detach(&sc->sc_ev_tx_xon);
 	evcnt_detach(&sc->sc_ev_rx_xoff);
 	evcnt_detach(&sc->sc_ev_rx_xon);
 	evcnt_detach(&sc->sc_ev_rx_macctl);
 #endif /* WM_EVENT_COUNTERS */
 	/* Tell the firmware about the release */
 	WM_CORE_LOCK(sc);
 	wm_release_manageability(sc);
 	wm_release_hw_control(sc);
 	wm_enable_wakeup(sc);
 	WM_CORE_UNLOCK(sc);
 	mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY);
 	/* Delete all remaining media. */
 	ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY);
 	ether_ifdetach(ifp);
 	if_detach(ifp);
 	if_percpuq_destroy(sc->sc_ipq);
 	/* Unload RX dmamaps and free mbufs */
 	for (i = 0; i < sc->sc_nqueues; i++) {
 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
 		mutex_enter(rxq->rxq_lock);
 		wm_rxdrain(rxq);
 		mutex_exit(rxq->rxq_lock);
+	}
 	/* Must unlock here */
 	/* Disestablish the interrupt handler */
 	for (i = 0; i < sc->sc_nintrs; i++) {
 		if (sc->sc_ihs[i] != NULL) {
 			pci_intr_disestablish(sc->sc_pc, sc->sc_ihs[i]);
 			sc->sc_ihs[i] = NULL;
+		}
+	}
 	pci_intr_release(sc->sc_pc, sc->sc_intrs, sc->sc_nintrs);
 	wm_free_txrx_queues(sc);
 	/* Unmap the registers */
 	if (sc->sc_ss) {
 		bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_ss);
 		sc->sc_ss = 0;
+	}
 	if (sc->sc_ios) {
 		bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios);
 		sc->sc_ios = 0;
+	}
 	if (sc->sc_flashs) {
 		bus_space_unmap(sc->sc_flasht, sc->sc_flashh, sc->sc_flashs);
 		sc->sc_flashs = 0;
+	}
 	if (sc->sc_core_lock)
 		mutex_obj_free(sc->sc_core_lock);
 	if (sc->sc_ich_phymtx)
 		mutex_obj_free(sc->sc_ich_phymtx);
 	if (sc->sc_ich_nvmmtx)
 		mutex_obj_free(sc->sc_ich_nvmmtx);
 	return 0;
+}
 static bool
 wm_suspend(device_t self, const pmf_qual_t *qual)
+{
 	struct wm_softc *sc = device_private(self);
 	wm_release_manageability(sc);
 	wm_release_hw_control(sc);
 	wm_enable_wakeup(sc);
 	return true;
+}
 static bool
 wm_resume(device_t self, const pmf_qual_t *qual)
+{
 	struct wm_softc *sc = device_private(self);
 	wm_init_manageability(sc);
 	return true;
+}
 /*
  * wm_watchdog:		[ifnet interface function]
+ *
  *	Watchdog timer handler.
  */
 static void
 wm_watchdog(struct ifnet *ifp)
+{
 	int qid;
 	struct wm_softc *sc = ifp->if_softc;
 	for (qid = 0; qid < sc->sc_nqueues; qid++) {
 		struct wm_txqueue *txq = &sc->sc_queue[qid].wmq_txq;
 		wm_watchdog_txq(ifp, txq);
+	}
 	/* Reset the interface. */
 	(void) wm_init(ifp);
 	/*
 	 * There are still some upper layer processing which call
 	 * ifp->if_start(). e.g. ALTQ or one CPU system
 	 */
 	/* Try to get more packets going. */
 	ifp->if_start(ifp);
+}
 static void
 wm_watchdog_txq(struct ifnet *ifp, struct wm_txqueue *txq)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	/*
 	 * Since we're using delayed interrupts, sweep up
 	 * before we report an error.
 	 */
 	mutex_enter(txq->txq_lock);
 	wm_txeof(sc, txq);
 	mutex_exit(txq->txq_lock);
 	if (txq->txq_free != WM_NTXDESC(txq)) {
 #ifdef WM_DEBUG
 		int i, j;
 		struct wm_txsoft *txs;
 #endif
 		log(LOG_ERR,
 		    "%s: device timeout (txfree %d txsfree %d txnext %d)\n",
 		    device_xname(sc->sc_dev), txq->txq_free, txq->txq_sfree,
 		    txq->txq_next);
 		ifp->if_oerrors++;
 #ifdef WM_DEBUG
 		for (i = txq->txq_sdirty; i != txq->txq_snext ;
 		    i = WM_NEXTTXS(txq, i)) {
 		    txs = &txq->txq_soft[i];
 		    printf("txs %d tx %d -> %d\n",
 			i, txs->txs_firstdesc, txs->txs_lastdesc);
 		    for (j = txs->txs_firstdesc; ;
 			j = WM_NEXTTX(txq, j)) {
 			printf("\tdesc %d: 0x%" PRIx64 "\n", j,
 			    txq->txq_nq_descs[j].nqtx_data.nqtxd_addr);
 			printf("\t %#08x%08x\n",
 			    txq->txq_nq_descs[j].nqtx_data.nqtxd_fields,
 			    txq->txq_nq_descs[j].nqtx_data.nqtxd_cmdlen);
 			if (j == txs->txs_lastdesc)
 				break;
+			}
+		}
 #endif
+	}
+}
 /*
  * wm_tick:
+ *
  *	One second timer, used to check link status, sweep up
  *	completed transmit jobs, etc.
  */
 static void
 wm_tick(void *arg)
+{
 	struct wm_softc *sc = arg;
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 #ifndef WM_MPSAFE
 	int s = splnet();
 #endif
 	WM_CORE_LOCK(sc);
 	if (sc->sc_core_stopping)
 		goto out;
 	if (sc->sc_type >= WM_T_82542_2_1) {
 		WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC));
 		WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC));
 		WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC));
 		WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC));
 		WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC));
+	}
 	ifp->if_collisions += CSR_READ(sc, WMREG_COLC);
 	ifp->if_ierrors += 0ULL /* ensure quad_t */
 	    + CSR_READ(sc, WMREG_CRCERRS)
 	    + CSR_READ(sc, WMREG_ALGNERRC)
 	    + CSR_READ(sc, WMREG_SYMERRC)
 	    + CSR_READ(sc, WMREG_RXERRC)
 	    + CSR_READ(sc, WMREG_SEC)
 	    + CSR_READ(sc, WMREG_CEXTERR)
 	    + CSR_READ(sc, WMREG_RLEC);
 	/*
 	 * WMREG_RNBC is incremented when there is no available buffers in host
 	 * memory. It does not mean the number of dropped packet. Because
 	 * ethernet controller can receive packets in such case if there is
 	 * space in phy's FIFO.
+	 *
 	 * If you want to know the nubmer of WMREG_RMBC, you should use such as
 	 * own EVCNT instead of if_iqdrops.
 	 */
 	ifp->if_iqdrops += CSR_READ(sc, WMREG_MPC);
 	if (sc->sc_flags & WM_F_HAS_MII)
 		mii_tick(&sc->sc_mii);
 	else if ((sc->sc_type >= WM_T_82575)
 	    && (sc->sc_mediatype == WM_MEDIATYPE_SERDES))
 		wm_serdes_tick(sc);
 	else
 		wm_tbi_tick(sc);
 	callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc);
 out:
 	WM_CORE_UNLOCK(sc);
 #ifndef WM_MPSAFE
 	splx(s);
 #endif
+}
 static int
 wm_ifflags_cb(struct ethercom *ec)
+{
 	struct ifnet *ifp = &ec->ec_if;
 	struct wm_softc *sc = ifp->if_softc;
 	int rc = 0;
 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	WM_CORE_LOCK(sc);
 	int change = ifp->if_flags ^ sc->sc_if_flags;
 	sc->sc_if_flags = ifp->if_flags;
 	if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) {
 		rc = ENETRESET;
 		goto out;
+	}
 	if ((change & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
 		wm_set_filter(sc);
 	wm_set_vlan(sc);
 out:
 	WM_CORE_UNLOCK(sc);
 	return rc;
+}
 /*
  * wm_ioctl:		[ifnet interface function]
+ *
  *	Handle control requests from the operator.
  */
 static int
 wm_ioctl(struct ifnet *ifp, u_long cmd, void *data)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	struct ifreq *ifr = (struct ifreq *) data;
 	struct ifaddr *ifa = (struct ifaddr *)data;
 	struct sockaddr_dl *sdl;
 	int s, error;
 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 #ifndef WM_MPSAFE
 	s = splnet();
 #endif
 	switch (cmd) {
 	case SIOCSIFMEDIA:
 	case SIOCGIFMEDIA:
 		WM_CORE_LOCK(sc);
 		/* Flow control requires full-duplex mode. */
 		if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO ||
 		    (ifr->ifr_media & IFM_FDX) == 0)
 			ifr->ifr_media &= ~IFM_ETH_FMASK;
 		if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) {
 			if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) {
 				/* We can do both TXPAUSE and RXPAUSE. */
 				ifr->ifr_media |=
 				    IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
+			}
 			sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK;
+		}
 		WM_CORE_UNLOCK(sc);
 #ifdef WM_MPSAFE
 		s = splnet();
 #endif
 		error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
 #ifdef WM_MPSAFE
 		splx(s);
 #endif
 		break;
 	case SIOCINITIFADDR:
 		WM_CORE_LOCK(sc);
 		if (ifa->ifa_addr->sa_family == AF_LINK) {
 			sdl = satosdl(ifp->if_dl->ifa_addr);
 			(void)sockaddr_dl_setaddr(sdl, sdl->sdl_len,
 			    LLADDR(satosdl(ifa->ifa_addr)), ifp->if_addrlen);
 			/* unicast address is first multicast entry */
 			wm_set_filter(sc);
 			error = 0;
 			WM_CORE_UNLOCK(sc);
 			break;
+		}
 		WM_CORE_UNLOCK(sc);
 		/*FALLTHROUGH*/
 	default:
 #ifdef WM_MPSAFE
 		s = splnet();
 #endif
 		/* It may call wm_start, so unlock here */
 		error = ether_ioctl(ifp, cmd, data);
 #ifdef WM_MPSAFE
 		splx(s);
 #endif
 		if (error != ENETRESET)
 			break;
 		error = 0;
 		if (cmd == SIOCSIFCAP) {
 			error = (*ifp->if_init)(ifp);
 		} else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI)
+			;
 		else if (ifp->if_flags & IFF_RUNNING) {
 			/*
 			 * Multicast list has changed; set the hardware filter
 			 * accordingly.
 			 */
 			WM_CORE_LOCK(sc);
 			wm_set_filter(sc);
 			WM_CORE_UNLOCK(sc);
+		}
 		break;
+	}
 #ifndef WM_MPSAFE
 	splx(s);
 #endif
 	return error;
+}
 /* MAC address related */
 /*
  * Get the offset of MAC address and return it.
  * If error occured, use offset 0.
  */
 static uint16_t
 wm_check_alt_mac_addr(struct wm_softc *sc)
+{
 	uint16_t myea[ETHER_ADDR_LEN / 2];
 	uint16_t offset = NVM_OFF_MACADDR;
 	/* Try to read alternative MAC address pointer */
 	if (wm_nvm_read(sc, NVM_OFF_ALT_MAC_ADDR_PTR, 1, &offset) != 0)
 		return 0;
 	/* Check pointer if it's valid or not. */
 	if ((offset == 0x0000) || (offset == 0xffff))
 		return 0;
 	offset += NVM_OFF_MACADDR_82571(sc->sc_funcid);
 	/*
 	 * Check whether alternative MAC address is valid or not.
 	 * Some cards have non 0xffff pointer but those don't use
 	 * alternative MAC address in reality.
+	 *
 	 * Check whether the broadcast bit is set or not.
 	 */
 	if (wm_nvm_read(sc, offset, 1, myea) == 0)
 		if (((myea[0] & 0xff) & 0x01) == 0)
 			return offset; /* Found */
 	/* Not found */
 	return 0;
+}
 static int
 wm_read_mac_addr(struct wm_softc *sc, uint8_t *enaddr)
+{
 	uint16_t myea[ETHER_ADDR_LEN / 2];
 	uint16_t offset = NVM_OFF_MACADDR;
 	int do_invert = 0;
 	switch (sc->sc_type) {
 	case WM_T_82580:
 	case WM_T_I350:
 	case WM_T_I354:
 		/* EEPROM Top Level Partitioning */
 		offset = NVM_OFF_LAN_FUNC_82580(sc->sc_funcid) + 0;
 		break;
 	case WM_T_82571:
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_80003:
 	case WM_T_I210:
 	case WM_T_I211:
 		offset = wm_check_alt_mac_addr(sc);
 		if (offset == 0)
 			if ((sc->sc_funcid & 0x01) == 1)
 				do_invert = 1;
 		break;
 	default:
 		if ((sc->sc_funcid & 0x01) == 1)
 			do_invert = 1;
 		break;
+	}
 	if (wm_nvm_read(sc, offset, sizeof(myea) / sizeof(myea[0]), myea) != 0)
 		goto bad;
 	enaddr[0] = myea[0] & 0xff;
 	enaddr[1] = myea[0] >> 8;
 	enaddr[2] = myea[1] & 0xff;
 	enaddr[3] = myea[1] >> 8;
 	enaddr[4] = myea[2] & 0xff;
 	enaddr[5] = myea[2] >> 8;
 	/*
 	 * Toggle the LSB of the MAC address on the second port
 	 * of some dual port cards.
 	 */
 	if (do_invert != 0)
 		enaddr[5] ^= 1;
 	return 0;
  bad:
 	return -1;
+}
 /*
  * wm_set_ral:
+ *
  *	Set an entery in the receive address list.
  */
 static void
 wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx)
+{
 	uint32_t ral_lo, ral_hi, addrl, addrh;
 	uint32_t wlock_mac;
 	int rv;
 	if (enaddr != NULL) {
 		ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) |
 		    (enaddr[3] << 24);
 		ral_hi = enaddr[4] | (enaddr[5] << 8);
 		ral_hi |= RAL_AV;
 	} else {
 		ral_lo = 0;
 		ral_hi = 0;
+	}
 	switch (sc->sc_type) {
 	case WM_T_82542_2_0:
 	case WM_T_82542_2_1:
 	case WM_T_82543:
 		CSR_WRITE(sc, WMREG_RAL(idx), ral_lo);
 		CSR_WRITE_FLUSH(sc);
 		CSR_WRITE(sc, WMREG_RAH(idx), ral_hi);
 		CSR_WRITE_FLUSH(sc);
 		break;
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
 		if (idx == 0) {
 			CSR_WRITE(sc, WMREG_CORDOVA_RAL(idx), ral_lo);
 			CSR_WRITE_FLUSH(sc);
 			CSR_WRITE(sc, WMREG_CORDOVA_RAH(idx), ral_hi);
 			CSR_WRITE_FLUSH(sc);
 			return;
+		}
 		if (sc->sc_type != WM_T_PCH2) {
 			wlock_mac = __SHIFTOUT(CSR_READ(sc, WMREG_FWSM),
 			    FWSM_WLOCK_MAC);
 			addrl = WMREG_SHRAL(idx - 1);
 			addrh = WMREG_SHRAH(idx - 1);
 		} else {
 			wlock_mac = 0;
 			addrl = WMREG_PCH_LPT_SHRAL(idx - 1);
 			addrh = WMREG_PCH_LPT_SHRAH(idx - 1);
+		}
 		if ((wlock_mac == 0) || (idx <= wlock_mac)) {
 			rv = wm_get_swflag_ich8lan(sc);
 			if (rv != 0)
 				return;
 			CSR_WRITE(sc, addrl, ral_lo);
 			CSR_WRITE_FLUSH(sc);
 			CSR_WRITE(sc, addrh, ral_hi);
 			CSR_WRITE_FLUSH(sc);
 			wm_put_swflag_ich8lan(sc);
+		}
 		break;
 	default:
 		CSR_WRITE(sc, WMREG_CORDOVA_RAL(idx), ral_lo);
 		CSR_WRITE_FLUSH(sc);
 		CSR_WRITE(sc, WMREG_CORDOVA_RAH(idx), ral_hi);
 		CSR_WRITE_FLUSH(sc);
 		break;
+	}
+}
 /*
  * wm_mchash:
+ *
  *	Compute the hash of the multicast address for the 4096-bit
  *	multicast filter.
  */
 static uint32_t
 wm_mchash(struct wm_softc *sc, const uint8_t *enaddr)
+{
 	static const int lo_shift[4] = { 4, 3, 2, 0 };
 	static const int hi_shift[4] = { 4, 5, 6, 8 };
 	static const int ich8_lo_shift[4] = { 6, 5, 4, 2 };
 	static const int ich8_hi_shift[4] = { 2, 3, 4, 6 };
 	uint32_t hash;
 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
 	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)
 	    || (sc->sc_type == WM_T_PCH_SPT)) {
 		hash = (enaddr[4] >> ich8_lo_shift[sc->sc_mchash_type]) |
 		    (((uint16_t) enaddr[5]) << ich8_hi_shift[sc->sc_mchash_type]);
 		return (hash & 0x3ff);
+	}
 	hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) |
 	    (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]);
 	return (hash & 0xfff);
+}
 /*
  * wm_set_filter:
+ *
  *	Set up the receive filter.
  */
 static void
 wm_set_filter(struct wm_softc *sc)
+{
 	struct ethercom *ec = &sc->sc_ethercom;
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	struct ether_multi *enm;
 	struct ether_multistep step;
 	bus_addr_t mta_reg;
 	uint32_t hash, reg, bit;
 	int i, size, ralmax;
 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	if (sc->sc_type >= WM_T_82544)
 		mta_reg = WMREG_CORDOVA_MTA;
 	else
 		mta_reg = WMREG_MTA;
 	sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE);
 	if (ifp->if_flags & IFF_BROADCAST)
 		sc->sc_rctl |= RCTL_BAM;
 	if (ifp->if_flags & IFF_PROMISC) {
 		sc->sc_rctl |= RCTL_UPE;
 		goto allmulti;
+	}
 	/*
 	 * Set the station address in the first RAL slot, and
 	 * clear the remaining slots.
 	 */
 	if (sc->sc_type == WM_T_ICH8)
 		size = WM_RAL_TABSIZE_ICH8 -1;
 	else if ((sc->sc_type == WM_T_ICH9) || (sc->sc_type == WM_T_ICH10)
 	    || (sc->sc_type == WM_T_PCH))
 		size = WM_RAL_TABSIZE_ICH8;
 	else if (sc->sc_type == WM_T_PCH2)
 		size = WM_RAL_TABSIZE_PCH2;
 	else if ((sc->sc_type == WM_T_PCH_LPT) ||(sc->sc_type == WM_T_PCH_SPT))
 		size = WM_RAL_TABSIZE_PCH_LPT;
 	else if (sc->sc_type == WM_T_82575)
 		size = WM_RAL_TABSIZE_82575;
 	else if ((sc->sc_type == WM_T_82576) || (sc->sc_type == WM_T_82580))
 		size = WM_RAL_TABSIZE_82576;
 	else if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354))
 		size = WM_RAL_TABSIZE_I350;
 	else
 		size = WM_RAL_TABSIZE;
 	wm_set_ral(sc, CLLADDR(ifp->if_sadl), 0);
 	if ((sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT)) {
 		i = __SHIFTOUT(CSR_READ(sc, WMREG_FWSM), FWSM_WLOCK_MAC);
 		switch (i) {
 		case 0:
 			/* We can use all entries */
 			ralmax = size;
 			break;
 		case 1:
 			/* Only RAR[0] */
 			ralmax = 1;
 			break;
 		default:
 			/* available SHRA + RAR[0] */
 			ralmax = i + 1;
+		}
 	} else
 		ralmax = size;
 	for (i = 1; i < size; i++) {
 		if (i < ralmax)
 			wm_set_ral(sc, NULL, i);
+	}
 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
 	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)
 	    || (sc->sc_type == WM_T_PCH_SPT))
 		size = WM_ICH8_MC_TABSIZE;
 	else
 		size = WM_MC_TABSIZE;
 	/* Clear out the multicast table. */
 	for (i = 0; i < size; i++) {
 		CSR_WRITE(sc, mta_reg + (i << 2), 0);
 		CSR_WRITE_FLUSH(sc);
+	}
 	ETHER_LOCK(ec);
 	ETHER_FIRST_MULTI(step, ec, enm);
 	while (enm != NULL) {
 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
 			ETHER_UNLOCK(ec);
 			/*
 			 * We must listen to a range of multicast addresses.
 			 * For now, just accept all multicasts, rather than
 			 * trying to set only those filter bits needed to match
 			 * the range.  (At this time, the only use of address
 			 * ranges is for IP multicast routing, for which the
 			 * range is big enough to require all bits set.)
 			 */
 			goto allmulti;
+		}
 		hash = wm_mchash(sc, enm->enm_addrlo);
 		reg = (hash >> 5);
 		if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
 		    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
 		    || (sc->sc_type == WM_T_PCH2)
 		    || (sc->sc_type == WM_T_PCH_LPT)
 		    || (sc->sc_type == WM_T_PCH_SPT))
 			reg &= 0x1f;
 		else
 			reg &= 0x7f;
 		bit = hash & 0x1f;
 		hash = CSR_READ(sc, mta_reg + (reg << 2));
 		hash |= 1U << bit;
 		if (sc->sc_type == WM_T_82544 && (reg & 1) != 0) {
 			/*
 			 * 82544 Errata 9: Certain register cannot be written
 			 * with particular alignments in PCI-X bus operation
 			 * (FCAH, MTA and VFTA).
 			 */
 			bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2));
 			CSR_WRITE(sc, mta_reg + (reg << 2), hash);
 			CSR_WRITE_FLUSH(sc);
 			CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit);
 			CSR_WRITE_FLUSH(sc);
 		} else {
 			CSR_WRITE(sc, mta_reg + (reg << 2), hash);
 			CSR_WRITE_FLUSH(sc);
+		}
 		ETHER_NEXT_MULTI(step, enm);
+	}
 	ETHER_UNLOCK(ec);
 	ifp->if_flags &= ~IFF_ALLMULTI;
 	goto setit;
  allmulti:
 	ifp->if_flags |= IFF_ALLMULTI;
 	sc->sc_rctl |= RCTL_MPE;
  setit:
 	CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl);
+}
 /* Reset and init related */
 static void
 wm_set_vlan(struct wm_softc *sc)
+{
 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	/* Deal with VLAN enables. */
 	if (VLAN_ATTACHED(&sc->sc_ethercom))
 		sc->sc_ctrl |= CTRL_VME;
 	else
 		sc->sc_ctrl &= ~CTRL_VME;
 	/* Write the control registers. */
 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
+}
 static void
 wm_set_pcie_completion_timeout(struct wm_softc *sc)
+{
 	uint32_t gcr;
 	pcireg_t ctrl2;
 	gcr = CSR_READ(sc, WMREG_GCR);
 	/* Only take action if timeout value is defaulted to 0 */
 	if ((gcr & GCR_CMPL_TMOUT_MASK) != 0)
 		goto out;
 	if ((gcr & GCR_CAP_VER2) == 0) {
 		gcr |= GCR_CMPL_TMOUT_10MS;
 		goto out;
+	}
 	ctrl2 = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
 	    sc->sc_pcixe_capoff + PCIE_DCSR2);
 	ctrl2 |= WM_PCIE_DCSR2_16MS;
 	pci_conf_write(sc->sc_pc, sc->sc_pcitag,
 	    sc->sc_pcixe_capoff + PCIE_DCSR2, ctrl2);
 out:
 	/* Disable completion timeout resend */
 	gcr &= ~GCR_CMPL_TMOUT_RESEND;
 	CSR_WRITE(sc, WMREG_GCR, gcr);
+}
 void
 wm_get_auto_rd_done(struct wm_softc *sc)
+{
 	int i;
 	/* wait for eeprom to reload */
 	switch (sc->sc_type) {
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82583:
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_82580:
 	case WM_T_I350:
 	case WM_T_I354:
 	case WM_T_I210:
 	case WM_T_I211:
 	case WM_T_80003:
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 		for (i = 0; i < 10; i++) {
 			if (CSR_READ(sc, WMREG_EECD) & EECD_EE_AUTORD)
 				break;
 			delay(1000);
+		}
 		if (i == 10) {
 			log(LOG_ERR, "%s: auto read from eeprom failed to "
 			    "complete\n", device_xname(sc->sc_dev));
+		}
 		break;
 	default:
 		break;
+	}
+}
 void
 wm_lan_init_done(struct wm_softc *sc)
+{
 	uint32_t reg = 0;
 	int i;
 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	/* Wait for eeprom to reload */
 	switch (sc->sc_type) {
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
 		for (i = 0; i < WM_ICH8_LAN_INIT_TIMEOUT; i++) {
 			reg = CSR_READ(sc, WMREG_STATUS);
 			if ((reg & STATUS_LAN_INIT_DONE) != 0)
 				break;
 			delay(100);
+		}
 		if (i >= WM_ICH8_LAN_INIT_TIMEOUT) {
 			log(LOG_ERR, "%s: %s: lan_init_done failed to "
 			    "complete\n", device_xname(sc->sc_dev), __func__);
+		}
 		break;
 	default:
 		panic("%s: %s: unknown type\n", device_xname(sc->sc_dev),
 		    __func__);
 		break;
+	}
 	reg &= ~STATUS_LAN_INIT_DONE;
 	CSR_WRITE(sc, WMREG_STATUS, reg);
+}
 void
 wm_get_cfg_done(struct wm_softc *sc)
+{
 	int mask;
 	uint32_t reg;
 	int i;
 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	/* Wait for eeprom to reload */
 	switch (sc->sc_type) {
 	case WM_T_82542_2_0:
 	case WM_T_82542_2_1:
 		/* null */
 		break;
 	case WM_T_82543:
 	case WM_T_82544:
 	case WM_T_82540:
 	case WM_T_82545:
 	case WM_T_82545_3:
 	case WM_T_82546:
 	case WM_T_82546_3:
 	case WM_T_82541:
 	case WM_T_82541_2:
 	case WM_T_82547:
 	case WM_T_82547_2:
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82583:
 		/* generic */
 		delay(10*1000);
 		break;
 	case WM_T_80003:
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_82580:
 	case WM_T_I350:
 	case WM_T_I354:
 	case WM_T_I210:
 	case WM_T_I211:
 		if (sc->sc_type == WM_T_82571) {
 			/* Only 82571 shares port 0 */
 			mask = EEMNGCTL_CFGDONE_0;
 		} else
 			mask = EEMNGCTL_CFGDONE_0 << sc->sc_funcid;
 		for (i = 0; i < WM_PHY_CFG_TIMEOUT; i++) {
 			if (CSR_READ(sc, WMREG_EEMNGCTL) & mask)
 				break;
 			delay(1000);
+		}
 		if (i >= WM_PHY_CFG_TIMEOUT) {
 			DPRINTF(WM_DEBUG_GMII, ("%s: %s failed\n",
 				device_xname(sc->sc_dev), __func__));
+		}
 		break;
 	case WM_T_ICH8:
 	case WM_T_ICH9: