Thu Nov 30 14:21:48 2017 UTC ()
Pull up following revision(s) (requested by maxv in ticket #402):
	sys/arch/x86/x86/lapic.c: revision 1.61
Fix a bug introduced in r1.55, this should be LAPIC_BASE.


(martin)
diff -r1.58.2.2 -r1.58.2.3 src/sys/arch/x86/x86/lapic.c
cvs diff -r1.58.2.2 -r1.58.2.3 src/sys/arch/x86/x86/lapic.c (expand / switch to unified diff)

--- src/sys/arch/x86/x86/lapic.c 2017/07/14 08:41:18 1.58.2.2
+++ src/sys/arch/x86/x86/lapic.c 2017/11/30 14:21:48 1.58.2.3
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: lapic.c,v 1.58.2.2 2017/07/14 08:41:18 martin Exp $ */ 1/* $NetBSD: lapic.c,v 1.58.2.3 2017/11/30 14:21:48 martin Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2000, 2008 The NetBSD Foundation, Inc. 4 * Copyright (c) 2000, 2008 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by RedBack Networks Inc. 8 * by RedBack Networks Inc.
9 * 9 *
10 * Author: Bill Sommerfeld 10 * Author: Bill Sommerfeld
11 * 11 *
12 * Redistribution and use in source and binary forms, with or without 12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions 13 * modification, are permitted provided that the following conditions
14 * are met: 14 * are met:
@@ -22,27 +22,27 @@ @@ -22,27 +22,27 @@
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE. 31 * POSSIBILITY OF SUCH DAMAGE.
32 */ 32 */
33 33
34#include <sys/cdefs.h> 34#include <sys/cdefs.h>
35__KERNEL_RCSID(0, "$NetBSD: lapic.c,v 1.58.2.2 2017/07/14 08:41:18 martin Exp $"); 35__KERNEL_RCSID(0, "$NetBSD: lapic.c,v 1.58.2.3 2017/11/30 14:21:48 martin Exp $");
36 36
37#include "acpica.h" 37#include "acpica.h"
38#include "ioapic.h" 38#include "ioapic.h"
39#include "opt_acpi.h" 39#include "opt_acpi.h"
40#include "opt_ddb.h" 40#include "opt_ddb.h"
41#include "opt_mpbios.h" /* for MPDEBUG */ 41#include "opt_mpbios.h" /* for MPDEBUG */
42#include "opt_multiprocessor.h" 42#include "opt_multiprocessor.h"
43#include "opt_ntp.h" 43#include "opt_ntp.h"
44 44
45#include <sys/param.h> 45#include <sys/param.h>
46#include <sys/proc.h> 46#include <sys/proc.h>
47#include <sys/systm.h> 47#include <sys/systm.h>
48#include <sys/device.h> 48#include <sys/device.h>
@@ -357,27 +357,27 @@ lapic_map(paddr_t lapic_base) @@ -357,27 +357,27 @@ lapic_map(paddr_t lapic_base)
357 pt_entry_t *pte; 357 pt_entry_t *pte;
358 vaddr_t va = local_apic_va; 358 vaddr_t va = local_apic_va;
359 359
360 /* 360 /*
361 * If the CPU has an APIC MSR, use it and ignore the supplied value: 361 * If the CPU has an APIC MSR, use it and ignore the supplied value:
362 * some ACPI implementations have been observed to pass bad values. 362 * some ACPI implementations have been observed to pass bad values.
363 * Additionally, ensure that the lapic is enabled as we are committed 363 * Additionally, ensure that the lapic is enabled as we are committed
364 * to using it at this point. Be conservative and assume that the MSR 364 * to using it at this point. Be conservative and assume that the MSR
365 * is not present on the Pentium (is it?). 365 * is not present on the Pentium (is it?).
366 */ 366 */
367 if (CPUID_TO_FAMILY(curcpu()->ci_signature) >= 6) { 367 if (CPUID_TO_FAMILY(curcpu()->ci_signature) >= 6) {
368 lapic_base = (paddr_t)rdmsr(MSR_APICBASE); 368 lapic_base = (paddr_t)rdmsr(MSR_APICBASE);
369 if ((lapic_base & APICBASE_PHYSADDR) == 0) { 369 if ((lapic_base & APICBASE_PHYSADDR) == 0) {
370 lapic_base |= APICBASE_PHYSADDR; 370 lapic_base |= LAPIC_BASE;
371 } 371 }
372 wrmsr(MSR_APICBASE, lapic_base | APICBASE_EN); 372 wrmsr(MSR_APICBASE, lapic_base | APICBASE_EN);
373 lapic_base &= APICBASE_PHYSADDR; 373 lapic_base &= APICBASE_PHYSADDR;
374 } 374 }
375 375
376 x86_disable_intr(); 376 x86_disable_intr();
377 377
378 /* 378 /*
379 * Map local apic. If we have a local apic, it's safe to assume 379 * Map local apic. If we have a local apic, it's safe to assume
380 * we're on a 486 or better and can use invlpg and non-cacheable PTE's 380 * we're on a 486 or better and can use invlpg and non-cacheable PTE's
381 * 381 *
382 * Whap the PTE "by hand" rather than calling pmap_kenter_pa because 382 * Whap the PTE "by hand" rather than calling pmap_kenter_pa because
383 * the latter will attempt to invoke TLB shootdown code just as we 383 * the latter will attempt to invoke TLB shootdown code just as we