 @@ -1,14 +1,14 @@
-/* $NetBSD: sunxi_emac.c,v 1.9 2017/11/16 03:07:17 ozaki-r Exp $ */
+/* $NetBSD: sunxi_emac.c,v 1.10 2017/11/30 21:36:11 jmcneill Exp $ */
 /*-
  * Copyright (c) 2016-2017 Jared McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -23,27 +23,27 @@
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 /*
  * Allwinner Gigabit Ethernet MAC (EMAC) controller
  */
 #include "opt_net_mpsafe.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sunxi_emac.c,v 1.9 2017/11/16 03:07:17 ozaki-r Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sunxi_emac.c,v 1.10 2017/11/30 21:36:11 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/mutex.h>
 #include <sys/callout.h>
 #include <sys/gpio.h>
 #include <sys/cprng.h>
 #include <net/if.h>
 @@ -87,43 +87,44 @@ __KERNEL_RCSID(0, "$NetBSD: sunxi_emac.c
 #define	RX_NEXT(n)		(((n) + 1) & (RX_DESC_COUNT - 1))
 #define	TX_MAX_SEGS		128
 #define	SOFT_RST_RETRY		1000
 #define	MII_BUSY_RETRY		1000
 #define	MDIO_FREQ		2500000
 #define	BURST_LEN_DEFAULT	8
 #define	RX_TX_PRI_DEFAULT	0
 #define	PAUSE_TIME_DEFAULT	0x400
 /* syscon EMAC clock register */
-#define	EMAC_CLK_EPHY_ADDR	(0x1f << 20)	/* H3 */
+#define	EMAC_CLK_REG		0x30
-#define	EMAC_CLK_EPHY_ADDR_SHIFT 20
+#define	 EMAC_CLK_EPHY_ADDR		(0x1f << 20)	/* H3 */
-#define	EMAC_CLK_EPHY_LED_POL	(1 << 17)	/* H3 */
+#define	 EMAC_CLK_EPHY_ADDR_SHIFT	20
-#define	EMAC_CLK_EPHY_SHUTDOWN	(1 << 16)	/* H3 */
+#define	 EMAC_CLK_EPHY_LED_POL		(1 << 17)	/* H3 */
-#define	EMAC_CLK_EPHY_SELECT	(1 << 15)	/* H3 */
+#define	 EMAC_CLK_EPHY_SHUTDOWN		(1 << 16)	/* H3 */
-#define	EMAC_CLK_RMII_EN	(1 << 13)
+#define	 EMAC_CLK_EPHY_SELECT		(1 << 15)	/* H3 */
-#define	EMAC_CLK_ETXDC		(0x7 << 10)
+#define	 EMAC_CLK_RMII_EN		(1 << 13)
-#define	EMAC_CLK_ETXDC_SHIFT	10
+#define	 EMAC_CLK_ETXDC			(0x7 << 10)
-#define	EMAC_CLK_ERXDC		(0x1f << 5)
+#define	 EMAC_CLK_ETXDC_SHIFT		10
-#define	EMAC_CLK_ERXDC_SHIFT	5
+#define	 EMAC_CLK_ERXDC			(0x1f << 5)
-#define	EMAC_CLK_PIT		(0x1 << 2)
+#define	 EMAC_CLK_ERXDC_SHIFT		5
-#define	 EMAC_CLK_PIT_MII	(0 << 2)
+#define	 EMAC_CLK_PIT			(0x1 << 2)
-#define	 EMAC_CLK_PIT_RGMII	(1 << 2)
+#define	  EMAC_CLK_PIT_MII		(0 << 2)
-#define	EMAC_CLK_SRC		(0x3 << 0)
+#define	  EMAC_CLK_PIT_RGMII		(1 << 2)
-#define	 EMAC_CLK_SRC_MII	(0 << 0)
+#define	 EMAC_CLK_SRC			(0x3 << 0)
-#define	 EMAC_CLK_SRC_EXT_RGMII	(1 << 0)
+#define	  EMAC_CLK_SRC_MII		(0 << 0)
-#define	 EMAC_CLK_SRC_RGMII	(2 << 0)
+#define	  EMAC_CLK_SRC_EXT_RGMII	(1 << 0)
 #define	  EMAC_CLK_SRC_RGMII		(2 << 0)
 /* Burst length of RX and TX DMA transfers */
 static int sunxi_emac_burst_len = BURST_LEN_DEFAULT;
 /* RX / TX DMA priority. If 1, RX DMA has priority over TX DMA. */
 static int sunxi_emac_rx_tx_pri = RX_TX_PRI_DEFAULT;
 /* Pause time field in the transmitted control frame */
 static int sunxi_emac_pause_time = PAUSE_TIME_DEFAULT;
 enum sunxi_emac_type {
 	EMAC_A83T = 1,
 	EMAC_H3,
 @@ -879,26 +880,47 @@ sunxi_emac_ioctl(struct ifnet *ifp, u_lo
 			sunxi_emac_setup_rxfilter(sc);
 			EMAC_UNLOCK(sc);
+		}
 		break;
+	}
 #ifndef EMAC_MPSAFE
 	splx(s);
 #endif
 	return error;
+}
 static bool
 sunxi_emac_has_internal_phy(struct sunxi_emac_softc *sc)
+{
 	const char * mdio_internal_compat[] = {
 		"allwinner,sun8i-h3-mdio-internal",
 		NULL
 	};
 	int phy;
 	/* Non-standard property, for compatible with old dts files */
 	if (of_hasprop(sc->phandle, "allwinner,use-internal-phy"))
 		return true;
 	phy = fdtbus_get_phandle(sc->phandle, "phy-handle");
 	if (phy == -1)
 		return false;
 	/* For internal PHY, check compatible string of parent node */
 	return of_compatible(OF_parent(phy), mdio_internal_compat) >= 0;
+}
 static int
 sunxi_emac_setup_phy(struct sunxi_emac_softc *sc)
+{
 	uint32_t reg, tx_delay, rx_delay;
 	const char *phy_type;
 	phy_type = fdtbus_get_string(sc->phandle, "phy-mode");
 	if (phy_type == NULL)
 		return 0;
 	aprint_debug_dev(sc->dev, "PHY type: %s\n", phy_type);
 	reg = SYSCONRD4(sc, 0);
 @@ -911,27 +933,27 @@ sunxi_emac_setup_phy(struct sunxi_emac_s
 	else
 		reg |= EMAC_CLK_PIT_MII | EMAC_CLK_SRC_MII;
 	if (of_getprop_uint32(sc->phandle, "tx-delay", &tx_delay) == 0) {
 		reg &= ~EMAC_CLK_ETXDC;
 		reg |= (tx_delay << EMAC_CLK_ETXDC_SHIFT);
+	}
 	if (of_getprop_uint32(sc->phandle, "rx-delay", &rx_delay) == 0) {
 		reg &= ~EMAC_CLK_ERXDC;
 		reg |= (rx_delay << EMAC_CLK_ERXDC_SHIFT);
+	}
 	if (sc->type == EMAC_H3) {
-		if (of_hasprop(sc->phandle, "allwinner,use-internal-phy")) {
+		if (sunxi_emac_has_internal_phy(sc)) {
 			reg |= EMAC_CLK_EPHY_SELECT;
 			reg &= ~EMAC_CLK_EPHY_SHUTDOWN;
 			if (of_hasprop(sc->phandle,
 			    "allwinner,leds-active-low"))
 				reg |= EMAC_CLK_EPHY_LED_POL;
 			else
 				reg &= ~EMAC_CLK_EPHY_LED_POL;
 			/* Set internal PHY addr to 1 */
 			reg &= ~EMAC_CLK_EPHY_ADDR;
 			reg |= (1 << EMAC_CLK_EPHY_ADDR_SHIFT);
 		} else {
 			reg &= ~EMAC_CLK_EPHY_SELECT;
 @@ -1252,35 +1274,51 @@ sunxi_emac_setup_dma(struct sunxi_emac_s
 	/* Write transmit and receive descriptor base address registers */
 	WR4(sc, EMAC_TX_DMA_LIST, sc->tx.desc_ring_paddr);
 	WR4(sc, EMAC_RX_DMA_LIST, sc->rx.desc_ring_paddr);
 	return 0;
+}
 static int
 sunxi_emac_get_resources(struct sunxi_emac_softc *sc)
+{
 	const int phandle = sc->phandle;
 	bus_addr_t addr, size;
 	u_int n;
-	/* Map registers */
+	/* Map EMAC registers */
-	for (n = 0; n < _RES_NITEMS; n++) {
+	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0)
-		if (fdtbus_get_reg(phandle, n, &addr, &size) != 0)
+		return ENXIO;
 	if (bus_space_map(sc->bst, addr, size, 0, &sc->bsh[_RES_EMAC]) != 0)
 		return ENXIO;
 	/* Map SYSCON registers */
 	if (of_hasprop(phandle, "syscon")) {
 		const int syscon_phandle = fdtbus_get_phandle(phandle,
 		    "syscon");
 		if (syscon_phandle == -1)
 			return ENXIO;
 		if (fdtbus_get_reg(syscon_phandle, 0, &addr, &size) != 0)
 			return ENXIO;
-		if (bus_space_map(sc->bst, addr, size, 0, &sc->bsh[n]) != 0)
+		if (size < EMAC_CLK_REG + 4)
 			return ENXIO;
 		addr += EMAC_CLK_REG;
 		size -= EMAC_CLK_REG;
 	} else {
 		if (fdtbus_get_reg(phandle, 1, &addr, &size) != 0)
 			return ENXIO;
+	}
 	if (bus_space_map(sc->bst, addr, size, 0, &sc->bsh[_RES_SYSCON]) != 0)
 		return ENXIO;
 	/* Get clocks and resets. "ahb" is required, "ephy" is optional. */
 	if ((sc->clk_ahb = fdtbus_clock_get(phandle, "ahb")) == NULL)
 		return ENXIO;
 	sc->clk_ephy = fdtbus_clock_get(phandle, "ephy");
 	if ((sc->rst_ahb = fdtbus_reset_get(phandle, "ahb")) == NULL)
 		return ENXIO;
 	sc->rst_ephy = fdtbus_reset_get(phandle, "ephy");
 	/* Regulator is optional */
 	sc->reg_phy = fdtbus_regulator_acquire(phandle, "phy-supply");