 @@ -1,14 +1,14 @@
-/*	$NetBSD: patch.c,v 1.24 2017/10/27 23:22:01 riastradh Exp $	*/
+/*	$NetBSD: patch.c,v 1.25 2018/01/07 11:24:45 maxv Exp $	*/
 /*-
  * Copyright (c) 2007, 2008, 2009 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Andrew Doran.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -24,27 +24,27 @@
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Patch kernel code at boot time, depending on available CPU features.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: patch.c,v 1.24 2017/10/27 23:22:01 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: patch.c,v 1.25 2018/01/07 11:24:45 maxv Exp $");
 #include "opt_lockdebug.h"
 #ifdef i386
 #include "opt_spldebug.h"
 #endif
 #include <sys/types.h>
 #include <sys/systm.h>
 #include <machine/cpu.h>
 #include <machine/cpufunc.h>
 #include <machine/specialreg.h>
 @@ -120,34 +120,34 @@ patchfunc(void *from_s, void *from_e, vo
 #ifdef GPROF
 #ifdef i386
 #define	MCOUNT_CALL_OFFSET	3
 #endif
 #ifdef __x86_64__
 #define	MCOUNT_CALL_OFFSET	5
 #endif
 	/* Patch mcount call offset */
 	adjust_jumpoff((uint8_t *)from_s + MCOUNT_CALL_OFFSET, from_s, to_s);
 #endif
+}
 static inline void __unused
-patchbytes(void *addr, const int byte1, const int byte2, const int byte3)
+patchbytes(void *addr, const uint8_t *bytes, size_t size)
+{
 	uint8_t *ptr = (uint8_t *)addr;
 	size_t i;
-	((uint8_t *)addr)[0] = (uint8_t)byte1;
+	for (i = 0; i < size; i++) {
-	if (byte2 != -1)
+		ptr[i] = bytes[i];
 		((uint8_t *)addr)[1] = (uint8_t)byte2;
 	if (byte3 != -1)
 		((uint8_t *)addr)[2] = (uint8_t)byte3;
+}
 void
 x86_patch(bool early)
+{
 	static bool first, second;
 	u_long psl;
 	u_long cr0;
 	int i;
 	if (early) {
 		if (first)
 			return;
 @@ -159,31 +159,35 @@ x86_patch(bool early)
+	}
 	/* Disable interrupts. */
 	psl = x86_read_psl();
 	x86_disable_intr();
 	/* Disable write protection in supervisor mode. */
 	cr0 = rcr0();
 	lcr0(cr0 & ~CR0_WP);
 #if !defined(GPROF)
 	if (!early && ncpu == 1) {
 #ifndef LOCKDEBUG
 		const uint8_t bytes[] = {
 			X86_NOP
 		};
 		/* Uniprocessor: kill LOCK prefixes. */
 		for (i = 0; x86_lockpatch[i] != 0; i++)
-			patchbytes(x86_lockpatch[i], X86_NOP, -1, -1);
+			patchbytes(x86_lockpatch[i], bytes, sizeof(bytes));
 		for (i = 0; atomic_lockpatch[i] != 0; i++)
-			patchbytes(atomic_lockpatch[i], X86_NOP, -1, -1);
+			patchbytes(atomic_lockpatch[i], bytes, sizeof(bytes));
 #endif	/* !LOCKDEBUG */
+	}
 	if (!early && (cpu_feature[0] & CPUID_SSE2) != 0) {
 		/*
 		 * Faster memory barriers.  We do not need to patch
 		 * membar_producer to use SFENCE because on x86
 		 * ordinary non-temporal stores are always issued in
 		 * program order to main memory and to other CPUs.
 		 */
 		patchfunc(
 		    sse2_lfence, sse2_lfence_end,
 		    membar_consumer, membar_consumer_end,
 		    NULL
 @@ -227,50 +231,61 @@ x86_patch(bool early)
 #endif	/* i386 && !LOCKDEBUG */
+	}
 #endif /* !SPLDEBUG */
 	/*
 	 * On some Opteron revisions, locked operations erroneously
 	 * allow memory references to be `bled' outside of critical
 	 * sections.  Apply workaround.
 	 */
 	if (cpu_vendor == CPUVENDOR_AMD &&
 	    (CPUID_TO_FAMILY(cpu_info_primary.ci_signature) == 0xe ||
 	    (CPUID_TO_FAMILY(cpu_info_primary.ci_signature) == 0xf &&
 	    CPUID_TO_EXTMODEL(cpu_info_primary.ci_signature) < 0x4))) {
 		const uint8_t bytes[] = {
 x0F, 0xAE, 0xE8 /* lfence */
 		};
 		for (i = 0; x86_retpatch[i] != 0; i++) {
 			/* ret,nop,nop,ret -> lfence,ret */
-			patchbytes(x86_retpatch[i], 0x0f, 0xae, 0xe8);
+			patchbytes(x86_retpatch[i], bytes, sizeof(bytes));
+		}
+	}
 #ifdef amd64
 	/*
 	 * If SMAP is present then patch the prepared holes with clac/stac
 	 * instructions.
+	 *
 	 * clac = 0x0f, 0x01, 0xca
 	 * stac = 0x0f, 0x01, 0xcb
 	 */
 	if (!early && cpu_feature[5] & CPUID_SEF_SMAP) {
 		KASSERT(rcr4() & CR4_SMAP);
 		const uint8_t clac_bytes[] = {
 x0F, 0x01, 0xCA /* clac */
 		};
 		const uint8_t stac_bytes[] = {
 x0F, 0x01, 0xCB /* stac */
 		};
 		for (i = 0; x86_clacpatch[i] != NULL; i++) {
 			/* ret,int3,int3 -> clac */
-			patchbytes(x86_clacpatch[i],
+			patchbytes(x86_clacpatch[i], clac_bytes,
-x0f, 0x01, 0xca);
+			    sizeof(clac_bytes));
+		}
 		for (i = 0; x86_stacpatch[i] != NULL; i++) {
 			/* ret,int3,int3 -> stac */
-			patchbytes(x86_stacpatch[i],
+			patchbytes(x86_stacpatch[i], stac_bytes,
-x0f, 0x01, 0xcb);
+			    sizeof(stac_bytes));
+		}
+	}
 #endif
 	/* Write back and invalidate cache, flush pipelines. */
 	wbinvd();
 	x86_flush();
 	x86_write_psl(psl);
 	/* Re-enable write protection. */
 	lcr0(cr0);
+}