 @@ -1,14 +1,14 @@
-/*	$NetBSD: amd64_trap.S,v 1.16 2018/01/07 12:42:46 maxv Exp $	*/
+/*	$NetBSD: amd64_trap.S,v 1.17 2018/01/07 16:10:16 maxv Exp $	*/
 /*
  * Copyright (c) 1998, 2007, 2008, 2017 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Charles M. Hannum, by Andrew Doran and by Maxime Villard.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -56,27 +56,27 @@
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #if 0
 #include <machine/asm.h>
-__KERNEL_RCSID(0, "$NetBSD: amd64_trap.S,v 1.16 2018/01/07 12:42:46 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amd64_trap.S,v 1.17 2018/01/07 16:10:16 maxv Exp $");
 #endif
 /*
  * Trap and fault vector routines
+ *
  * On exit from the kernel to user mode, we always need to check for ASTs.  In
  * addition, we need to do this atomically; otherwise an interrupt may occur
  * which causes an AST, but it won't get processed until the next kernel entry
  * (possibly the next clock tick).  Thus, we disable interrupt before checking,
  * and only enable them again on the final `iret' or before calling the AST
  * handler.
  */
 @@ -110,50 +110,53 @@ IDTVEC_END(trap01)
+ *
  * Therefore we don't enable interrupts, because the CPU could switch to
  * another LWP, call 'iret' and unintentionally leave the NMI mode.
+ *
  * We need to be careful about %gs too, because it is possible that we were
  * running in kernel mode with a userland %gs.
  */
 IDTVEC(trap02)
 #if defined(XEN)
 	ZTRAP(T_NMI)
 #else
 	ZTRAP_NJ(T_NMI)
 	subq	$TF_REGSIZE,%rsp
 	SVS_ENTER
 	INTR_SAVE_GPRS
 	cld
 	SMAP_ENABLE
 	movw	%gs,TF_GS(%rsp)
 	movw	%fs,TF_FS(%rsp)
 	movw	%es,TF_ES(%rsp)
 	movw	%ds,TF_DS(%rsp)
 	movl	$MSR_GSBASE,%ecx
 	rdmsr
 	cmpl	$VM_MIN_KERNEL_ADDRESS_HIGH32,%edx
 	jae	.Lnoswapgs
 	swapgs
 	movq	%rsp,%rdi
 	incq	CPUVAR(NTRAP)
 	call	_C_LABEL(nmitrap)
 	SVS_LEAVE
 	swapgs
 	jmp	.Lnmileave
 .Lnoswapgs:
 	movq	%rsp,%rdi
 	incq	CPUVAR(NTRAP)
 	call	_C_LABEL(nmitrap)
 	SVS_LEAVE
 .Lnmileave:
 	movw	TF_ES(%rsp),%es
 	movw	TF_DS(%rsp),%ds
 	INTR_RESTORE_GPRS
 	addq	$TF_REGSIZE+16,%rsp
 	iretq
 #endif
 IDTVEC_END(trap02)
 IDTVEC(trap03)
 #ifndef KDTRACE_HOOKS
 	ZTRAP(T_BPTFLT)

 @@ -1,14 +1,14 @@
-#	$NetBSD: genassym.cf,v 1.64 2018/01/04 13:36:30 maxv Exp $
+#	$NetBSD: genassym.cf,v 1.65 2018/01/07 16:10:16 maxv Exp $
+#
 # Copyright (c) 1998, 2006, 2007, 2008 The NetBSD Foundation, Inc.
 # All rights reserved.
+#
 # This code is derived from software contributed to The NetBSD Foundation
 # by Charles M. Hannum, and by Andrew Doran.
+#
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions
 # are met:
 # 1. Redistributions of source code must retain the above copyright
 #    notice, this list of conditions and the following disclaimer.
 @@ -226,26 +226,28 @@ define	FRAMESIZE		sizeof(struct trapfram
 define	TSS_RSP0		offsetof(struct cpu_tss, tss.tss_rsp0)
 define	CPU_INFO_SCRATCH	offsetof(struct cpu_info, ci_scratch)
 define	CPU_INFO_SELF		offsetof(struct cpu_info, ci_self)
 define	CPU_INFO_RESCHED	offsetof(struct cpu_info, ci_want_resched)
 define	CPU_INFO_WANT_PMAPLOAD	offsetof(struct cpu_info, ci_want_pmapload)
 define	CPU_INFO_TLBSTATE	offsetof(struct cpu_info, ci_tlbstate)
 define	TLBSTATE_VALID		TLBSTATE_VALID
 define	CPU_INFO_CURLWP		offsetof(struct cpu_info, ci_curlwp)
 define	CPU_INFO_CURLDT		offsetof(struct cpu_info, ci_curldt)
 define	CPU_INFO_IDLELWP	offsetof(struct cpu_info, ci_data.cpu_idlelwp)
 define	CPU_INFO_PMAP		offsetof(struct cpu_info, ci_pmap)
 define	CPU_INFO_TSS		offsetof(struct cpu_info, ci_tss)
 define	CPU_INFO_UPDIRPA	offsetof(struct cpu_info, ci_svs_updirpa)
 define	CPU_INFO_KPDIRPA	offsetof(struct cpu_info, ci_svs_kpdirpa)
 define	CPU_INFO_NSYSCALL	offsetof(struct cpu_info, ci_data.cpu_nsyscall)
 define	CPU_INFO_NTRAP		offsetof(struct cpu_info, ci_data.cpu_ntrap)
 define	CPU_INFO_NINTR		offsetof(struct cpu_info, ci_data.cpu_nintr)
 define	CPU_INFO_CURPRIORITY	offsetof(struct cpu_info, ci_schedstate.spc_curpriority)
 define	CPU_INFO_FPCURLWP	offsetof(struct cpu_info, ci_fpcurlwp)
 define	CPU_INFO_GDT		offsetof(struct cpu_info, ci_gdt)
 define	CPU_INFO_IPENDING	offsetof(struct cpu_info, ci_ipending)
 define	CPU_INFO_IMASK		offsetof(struct cpu_info, ci_imask)
 define	CPU_INFO_IUNMASK	offsetof(struct cpu_info, ci_iunmask)
 define	CPU_INFO_ILEVEL		offsetof(struct cpu_info, ci_ilevel)
 define	CPU_INFO_IDEPTH		offsetof(struct cpu_info, ci_idepth)
 define	CPU_INFO_ISOURCES	offsetof(struct cpu_info, ci_isources)

 @@ -1,14 +1,14 @@
-/*	$NetBSD: locore.S,v 1.144 2018/01/04 13:36:30 maxv Exp $	*/
+/*	$NetBSD: locore.S,v 1.145 2018/01/07 16:10:16 maxv Exp $	*/
 /*
  * Copyright-o-rama!
  */
 /*
  * Copyright (c) 1998, 2000, 2007, 2008, 2016 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Charles M. Hannum and by Maxime Villard.
+ *
  * Redistribution and use in source and binary forms, with or without
 @@ -149,26 +149,27 @@
 #define _ALIGN_TEXT	ALIGN_TEXT
 #include <machine/asm.h>
 #include "opt_copy_symtab.h"
 #include "opt_ddb.h"
 #include "opt_ddbparam.h"
 #include "opt_modular.h"
 #include "opt_realmem.h"
 #include "opt_compat_netbsd.h"
 #include "opt_compat_netbsd32.h"
 #include "opt_xen.h"
 #include "opt_svs.h"
 #include "assym.h"
 #include "lapic.h"
 #include "ioapic.h"
 #include "ksyms.h"
 #include <sys/errno.h>
 #include <sys/syscall.h>
 #include <machine/pte.h>
 #include <machine/segments.h>
 #include <machine/specialreg.h>
 #include <machine/trap.h>
 @@ -1078,26 +1079,32 @@ ENTRY(cpu_switchto)
 	movq	%rdi,%r13	/* oldlwp */
 	movq	%rsi,%r12	/* newlwp */
 	testq	%r13,%r13	/* oldlwp = NULL ? */
 	jz	.Lskip_save
 	/* Save old context. */
 	movq	L_PCB(%r13),%rax
 	movq	%rsp,PCB_RSP(%rax)
 	movq	%rbp,PCB_RBP(%rax)
 .Lskip_save:
 #ifdef SVS
 	pushq	%rdx
 	callq	_C_LABEL(svs_lwp_switch)
 	popq	%rdx
 #endif
 	/* Switch to newlwp's stack. */
 	movq	L_PCB(%r12),%r14
 	movq	PCB_RSP(%r14),%rsp
 	movq	PCB_RBP(%r14),%rbp
 	/*
 	 * Set curlwp.  This must be globally visible in order to permit
 	 * non-interlocked mutex release.
 	 */
 	movq	%r12,%rcx
 	xchgq	%rcx,CPUVAR(CURLWP)
 	/* Skip the rest if returning to a pinned LWP. */
 @@ -1278,26 +1285,27 @@ IDTVEC(syscall)
 	movq	CPUVAR(SCRATCH),%r15
 #undef SP
 	movq	$2,TF_ERR(%rsp)		/* syscall instruction size */
 	movq	$T_ASTFLT,TF_TRAPNO(%rsp)
 #else
 	/* Xen already switched to kernel stack */
 	addq	$0x10,%rsp	/* gap to match cs:rip */
 	pushq	$2		/* error code */
 	pushq	$T_ASTFLT
 	subq	$TF_REGSIZE,%rsp
 	cld
 #endif
 	SVS_ENTER
 	INTR_SAVE_GPRS
 	movw	$GSEL(GUDATA_SEL, SEL_UPL),TF_DS(%rsp)
 	movw	$GSEL(GUDATA_SEL, SEL_UPL),TF_ES(%rsp)
 	movw	$0,TF_FS(%rsp)
 	movw	$0,TF_GS(%rsp)
 	STI(si)
 .Ldo_syscall:
 	movq	CPUVAR(CURLWP),%r14
 	incq	CPUVAR(NSYSCALL)	/* count it atomically */
 	movq	%rsp,L_MD_REGS(%r14)	/* save pointer to frame */
 	movq	L_PROC(%r14),%r15
 	andl	$~MDL_IRET,L_MD_FLAGS(%r14)   /* Allow sysret return */
 @@ -1322,26 +1330,27 @@ IDTVEC(syscall)
 	/*
 	 * Decide if we need to take a slow path. That's the case when we
 	 * want to reload %cs and %ss on a 64bit LWP (MDL_IRET set), or when
 	 * we're returning to a 32bit LWP (MDL_COMPAT32 set).
+	 *
 	 * In either case, we jump into intrfastexit and return to userland
 	 * with the iret instruction.
 	 */
 	testl	$(MDL_IRET|MDL_COMPAT32),L_MD_FLAGS(%r14)
 	jnz	intrfastexit
 	INTR_RESTORE_GPRS
 	SVS_LEAVE
 	SWAPGS
 #ifndef XEN
 	movq	TF_RIP(%rsp),%rcx	/* %rip for sysret */
 	movq	TF_RFLAGS(%rsp),%r11	/* %flags for sysret */
 	movq	TF_RSP(%rsp),%rsp
 do_sysret:
 	sysretq
 #else
 	addq	$TF_RIP,%rsp
 	pushq	$256	/* VGCF_IN_SYSCALL */
 	jmp	HYPERVISOR_iret
 #endif
 @@ -1484,29 +1493,31 @@ ENTRY(intrfastexit)
 #ifdef XEN
 	cmpw	$FLAT_RING3_CS64,TF_CS(%rsp)
 	je	.Luexit64
 #endif
 .Luexit32:
 	NOT_XEN(cli;)
 do_mov_es:
 	movw	TF_ES(%rsp),%es
 do_mov_ds:
 	movw	TF_DS(%rsp),%ds
 do_mov_fs:
 	movw	TF_FS(%rsp),%fs
 	SVS_LEAVE
 	SWAPGS
 #ifndef XEN
 do_mov_gs:
 	movw	TF_GS(%rsp),%gs
 #endif
 	jmp	.Lkexit
 .Luexit64:
 	NOT_XEN(cli;)
 	SVS_LEAVE
 	SWAPGS
 .Lkexit:
 	addq	$TF_REGSIZE+16,%rsp	/* + T_xxx and error code */
 do_iret:
 	iretq
 END(intrfastexit)

 @@ -1,14 +1,14 @@
-/*	$NetBSD: machdep.c,v 1.284 2018/01/05 08:04:20 maxv Exp $	*/
+/*	$NetBSD: machdep.c,v 1.285 2018/01/07 16:10:16 maxv Exp $	*/
 /*
  * Copyright (c) 1996, 1997, 1998, 2000, 2006, 2007, 2008, 2011
  *     The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
  * Simulation Facility, NASA Ames Research Center.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Coyote Point Systems, Inc. which was written under contract to Coyote
  * Point by Jed Davis and Devon O'Dell.
 @@ -100,39 +100,40 @@
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  *	@(#)machdep.c	7.4 (Berkeley) 6/3/91
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.284 2018/01/05 08:04:20 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.285 2018/01/07 16:10:16 maxv Exp $");
 /* #define XENDEBUG_LOW  */
 #include "opt_modular.h"
 #include "opt_user_ldt.h"
 #include "opt_ddb.h"
 #include "opt_kgdb.h"
 #include "opt_cpureset_delay.h"
 #include "opt_mtrr.h"
 #include "opt_realmem.h"
 #include "opt_xen.h"
 #include "opt_kaslr.h"
 #include "opt_svs.h"
 #ifndef XEN
 #include "opt_physmem.h"
 #endif
 #include "isa.h"
 #include "pci.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/signal.h>
 #include <sys/signalvar.h>
 #include <sys/kernel.h>
 #include <sys/cpu.h>
 #include <sys/exec.h>
 @@ -2218,13 +2219,148 @@ mm_md_direct_mapped_io(void *addr, paddr
 		*paddr = PMAP_DIRECT_UNMAP(va);
 		return true;
+	}
 	return false;
+}
 bool
 mm_md_direct_mapped_phys(paddr_t paddr, vaddr_t *vaddr)
+{
 	*vaddr = PMAP_DIRECT_MAP(paddr);
 	return true;
+}
 #endif
 /* -------------------------------------------------------------------------- */
 #ifdef SVS
 /*
  * Separate Virtual Space
+ *
  * A per-cpu L4 page is maintained in ci_svs_updirpa. During each context
  * switch to a user pmap, updirpa is populated with the entries of the new
  * pmap, minus what we don't want to have mapped in userland.
+ *
  * Note on locking/synchronization here:
+ *
  * (a) Touching ci_svs_updir without holding ci_svs_mtx first is *not*
  *     allowed.
+ *
  * (b) pm_kernel_cpus contains the set of CPUs that have the pmap loaded
  *     in their CR3 register. It must *not* be replaced by pm_cpus.
+ *
  * (c) When a context switch on the current CPU is made from a user LWP
  *     towards a kernel LWP, CR3 is not updated. Therefore, the pmap's
  *     pm_kernel_cpus still contains the current CPU. It implies that the
  *     remote CPUs that execute other threads of the user process we just
  *     left will keep synchronizing us against their changes.
+ *
  * TODO: for now, only PMAP_SLOT_PTE is unmapped.
  */
 void
 cpu_svs_init(struct cpu_info *ci)
+{
 	struct vm_page *pg;
 	KASSERT(ci != NULL);
 	pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO);
 	if (pg == 0)
 		panic("%s: failed to allocate L4 PA for CPU %d\n",
 			__func__, cpu_index(ci));
 	ci->ci_svs_updirpa = VM_PAGE_TO_PHYS(pg);
 	ci->ci_svs_updir = (pt_entry_t *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0,
 		UVM_KMF_VAONLY | UVM_KMF_NOWAIT);
 	if (ci->ci_svs_updir == NULL)
 		panic("%s: failed to allocate L4 VA for CPU %d\n",
 			__func__, cpu_index(ci));
 	pmap_kenter_pa((vaddr_t)ci->ci_svs_updir, ci->ci_svs_updirpa,
 		VM_PROT_READ | VM_PROT_WRITE, 0);
 	pmap_update(pmap_kernel());
 	ci->ci_svs_kpdirpa = pmap_pdirpa(pmap_kernel(), 0);
 	mutex_init(&ci->ci_svs_mtx, MUTEX_DEFAULT, IPL_VM);
+}
 void
 svs_pmap_sync(struct pmap *pmap, int index)
+{
 	CPU_INFO_ITERATOR cii;
 	struct cpu_info *ci;
 	cpuid_t cid;
 	KASSERT(pmap != NULL);
 	KASSERT(pmap != pmap_kernel());
 	KASSERT(mutex_owned(pmap->pm_lock));
 	KASSERT(kpreempt_disabled());
 	KASSERT(index <= 255);
 	for (CPU_INFO_FOREACH(cii, ci)) {
 		cid = cpu_index(ci);
 		if (!kcpuset_isset(pmap->pm_kernel_cpus, cid)) {
 			continue;
+		}
 		/* take the lock and check again */
 		mutex_enter(&ci->ci_svs_mtx);
 		if (kcpuset_isset(pmap->pm_kernel_cpus, cid)) {
 			ci->ci_svs_updir[index] = pmap->pm_pdir[index];
+		}
 		mutex_exit(&ci->ci_svs_mtx);
+	}
+}
 void
 svs_lwp_switch(struct lwp *oldlwp, struct lwp *newlwp)
+{
 	/* Switch rsp0 */
+}
 static inline pt_entry_t
 svs_pte_atomic_read(struct pmap *pmap, size_t idx)
+{
 	/*
 	 * XXX: We don't have a basic atomic_fetch_64 function?
 	 */
 	return atomic_cas_64(&pmap->pm_pdir[idx], 666, 666);
+}
 /*
  * We may come here with the pmap unlocked. So read its PTEs atomically. If
  * a remote CPU is updating them at the same time, it's not that bad: the
  * remote CPU will call svs_pmap_sync afterwards, and our updirpa will be
  * synchronized properly.
  */
 void
 svs_pdir_switch(struct pmap *pmap)
+{
 	struct cpu_info *ci = curcpu();
 	pt_entry_t pte;
 	size_t i;
 	KASSERT(kpreempt_disabled());
 	KASSERT(pmap != pmap_kernel());
 	ci->ci_svs_kpdirpa = pmap_pdirpa(pmap, 0);
 	mutex_enter(&ci->ci_svs_mtx);
 	for (i = 0; i < 512; i++) {
 		if (i == PDIR_SLOT_PTE) {
 			/* We don't want to have this mapped. */
 			ci->ci_svs_updir[i] = 0;
 		} else {
 			pte = svs_pte_atomic_read(pmap, i);
 			ci->ci_svs_updir[i] = pte;
+		}
+	}
 	mutex_exit(&ci->ci_svs_mtx);
+}
 #endif

 @@ -1,38 +1,38 @@
-# $NetBSD: GENERIC,v 1.476 2017/12/31 03:38:06 christos Exp $
+# $NetBSD: GENERIC,v 1.477 2018/01/07 16:10:16 maxv Exp $
+#
 # GENERIC machine description file
+#
 # This machine description file is used to generate the default NetBSD
 # kernel.  The generic kernel does not include all options, subsystems
 # and device drivers, but should be useful for most applications.
+#
 # The machine description file can be customised for your specific
 # machine to reduce the kernel size and improve its performance.
+#
 # For further information on compiling NetBSD kernels, see the config(8)
 # man page.
+#
 # For further information on hardware support for this architecture, see
 # the intro(4) man page.  For further information about kernel options
 # for this architecture, see the options(4) man page.  For an explanation
 # of each device driver in this file see the section 4 man page for the
 # device.
 include 	"arch/amd64/conf/std.amd64"
 options 	INCLUDE_CONFIG_FILE	# embed config file in kernel binary
-#ident		"GENERIC-$Revision: 1.476 $"
+#ident		"GENERIC-$Revision: 1.477 $"
 maxusers	64		# estimated number of users
 # delay between "rebooting ..." message and hardware reset, in milliseconds
 #options 	CPURESET_DELAY=2000
 # This option allows you to force a serial console at the specified
 # I/O address.   see console(4) for details.
 #options 	CONSDEVNAME="\"com\"",CONADDR=0x2f8,CONSPEED=57600
 #	you don't want the option below ON iff you are using the
 #	serial console option of the new boot strap code.
 #options 	CONS_OVERRIDE	# Always use above! independent of boot info
 @@ -65,26 +65,27 @@ options 	CPU_UCODE	# cpu ucode loading s
 # Note: SysV IPC parameters could be changed dynamically, see sysctl(8).
 options 	SYSVMSG		# System V-like message queues
 options 	SYSVSEM		# System V-like semaphores
 options 	SYSVSHM		# System V-like memory sharing
 options 	MODULAR		# new style module(7) framework
 options 	MODULAR_DEFAULT_AUTOLOAD
 options 	USERCONF	# userconf(4) support
 #options 	PIPE_SOCKETPAIR	# smaller, but slower pipe(2)
 options 	SYSCTL_INCLUDE_DESCR	# Include sysctl descriptions in kernel
 # CPU-related options
 #options 	USER_LDT	# user-settable LDT; used by WINE
 options 	SVS		# Separate Virtual Space
 # CPU features
 acpicpu*	at cpu?		# ACPI CPU (including frequency scaling)
 coretemp*	at cpu?		# Intel on-die thermal sensor
 est0		at cpu0		# Intel Enhanced SpeedStep (non-ACPI)
 #odcm0		at cpu0		# On-demand clock modulation
 powernow0	at cpu0		# AMD PowerNow! and Cool'n'Quiet (non-ACPI)
 vmt0		at cpu0		# VMware Tools
 options 	PMC		# performance-monitoring counters support
 # Alternate buffer queue strategies for better responsiveness under high
 # disk I/O load.

 @@ -1,20 +1,21 @@
-/*	$NetBSD: frameasm.h,v 1.26 2018/01/07 13:43:23 maxv Exp $	*/
+/*	$NetBSD: frameasm.h,v 1.27 2018/01/07 16:10:16 maxv Exp $	*/
 #ifndef _AMD64_MACHINE_FRAMEASM_H
 #define _AMD64_MACHINE_FRAMEASM_H
 #ifdef _KERNEL_OPT
 #include "opt_xen.h"
 #include "opt_svs.h"
 #endif
 /*
  * Macros to define pushing/popping frames for interrupts, traps
  * and system calls. Currently all the same; will diverge later.
  */
 #ifdef XEN
 #define HYPERVISOR_iret hypercall_page + (__HYPERVISOR_iret * 32)
 /* Xen do not need swapgs, done by hypervisor */
 #define swapgs
 #define iretq	pushq $0 ; jmp HYPERVISOR_iret
 #define	XEN_ONLY2(x,y)	x,y
 @@ -85,35 +86,52 @@
 	movq	TF_RCX(%rsp),%rcx	; \
 	movq	TF_R8(%rsp),%r8		; \
 	movq	TF_R9(%rsp),%r9		; \
 	movq	TF_R10(%rsp),%r10	; \
 	movq	TF_R11(%rsp),%r11	; \
 	movq	TF_R12(%rsp),%r12	; \
 	movq	TF_R13(%rsp),%r13	; \
 	movq	TF_R14(%rsp),%r14	; \
 	movq	TF_R15(%rsp),%r15	; \
 	movq	TF_RBP(%rsp),%rbp	; \
 	movq	TF_RBX(%rsp),%rbx	; \
 	movq	TF_RAX(%rsp),%rax
 #ifdef SVS
 #define SVS_ENTER \
 	pushq	%rax			; \
 	movq	CPUVAR(KPDIRPA),%rax	; \
 	movq	%rax,%cr3		; \
 	popq	%rax
 #define SVS_LEAVE \
 	pushq	%rax			; \
 	movq	CPUVAR(UPDIRPA),%rax	; \
 	movq	%rax,%cr3		; \
 	popq	%rax
 #else
 #define SVS_ENTER	/* nothing */
 #define SVS_LEAVE	/* nothing */
 #endif
 #define	INTRENTRY_L(kernel_trap, usertrap) \
 	subq	$TF_REGSIZE,%rsp	; \
 	INTR_SAVE_GPRS			; \
 	cld				; \
 	SMAP_ENABLE			; \
 	testb	$SEL_UPL,TF_CS(%rsp)	; \
 	je	kernel_trap		; \
 usertrap				; \
 	SWAPGS				; \
 	SVS_ENTER			; \
 	movw	%gs,TF_GS(%rsp)		; \
 	movw	%fs,TF_FS(%rsp)		; \
 	movw	%es,TF_ES(%rsp)		; \
 	movw	%ds,TF_DS(%rsp)
 #define	INTRENTRY \
 	INTRENTRY_L(98f,)		; \
 :
 #define INTRFASTEXIT \
 	jmp	intrfastexit
 #define INTR_RECURSE_HWFRAME \

 @@ -1,14 +1,14 @@
-/*	$NetBSD: pmap.h,v 1.40 2017/06/17 08:40:46 maxv Exp $	*/
+/*	$NetBSD: pmap.h,v 1.41 2018/01/07 16:10:16 maxv Exp $	*/
 /*
  * Copyright (c) 1997 Charles D. Cranor and Washington University.
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -208,26 +208,30 @@
 #define PG_W		PG_AVAIL1	/* "wired" mapping */
 #define PG_PVLIST	PG_AVAIL2	/* mapping has entry on pvlist */
 /* PG_AVAIL3 not used */
 #define	PG_X		0		/* XXX dummy */
 /*
  * Number of PTE's per cache line.  8 byte pte, 64-byte cache line
  * Used to avoid false sharing of cache lines.
  */
 #define NPTECL		8
 void svs_pmap_sync(struct pmap *, int);
 void svs_lwp_switch(struct lwp *, struct lwp *);
 void svs_pdir_switch(struct pmap *);
 #include <x86/pmap.h>
 #ifndef XEN
 #define pmap_pa2pte(a)			(a)
 #define pmap_pte2pa(a)			((a) & PG_FRAME)
 #define pmap_pte_set(p, n)		do { *(p) = (n); } while (0)
 #define pmap_pte_cas(p, o, n)		atomic_cas_64((p), (o), (n))
 #define pmap_pte_testset(p, n)		\
     atomic_swap_ulong((volatile unsigned long *)p, n)
 #define pmap_pte_setbits(p, b)		\
     atomic_or_ulong((volatile unsigned long *)p, b)
 #define pmap_pte_clearbits(p, b)	\
     atomic_and_ulong((volatile unsigned long *)p, ~(b))

 @@ -1,14 +1,14 @@
-/*	$NetBSD: cpu.h,v 1.87 2018/01/05 08:04:21 maxv Exp $	*/
+/*	$NetBSD: cpu.h,v 1.88 2018/01/07 16:10:16 maxv Exp $	*/
 /*
  * Copyright (c) 1990 The Regents of the University of California.
  * All rights reserved.
+ *
  * This code is derived from software contributed to Berkeley by
  * William Jolitz.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -37,26 +37,27 @@
 #ifndef _X86_CPU_H_
 #define _X86_CPU_H_
 #if defined(_KERNEL) || defined(_STANDALONE)
 #include <sys/types.h>
 #else
 #include <stdint.h>
 #include <stdbool.h>
 #endif /* _KERNEL || _STANDALONE */
 #if defined(_KERNEL) || defined(_KMEMUSER)
 #if defined(_KERNEL_OPT)
 #include "opt_xen.h"
 #include "opt_svs.h"
 #ifdef i386
 #include "opt_user_ldt.h"
 #endif
 #endif
 /*
  * Definitions unique to x86 cpu support.
  */
 #include <machine/frame.h>
 #include <machine/pte.h>
 #include <machine/segments.h>
 #include <machine/tss.h>
 #include <machine/intrdefs.h>
 @@ -177,26 +178,33 @@ struct cpu_info {
 			 */
 	const struct cpu_functions *ci_func;  /* start/stop functions */
 	struct trapframe *ci_ddb_regs;
 	u_int ci_cflush_lsize;	/* CLFLUSH insn line size */
 	struct x86_cache_info ci_cinfo[CAI_COUNT];
 #ifdef PAE
 	uint32_t	ci_pae_l3_pdirpa; /* PA of L3 PD */
 	pd_entry_t *	ci_pae_l3_pdir; /* VA pointer to L3 PD */
 #endif
 #ifdef SVS
 	pd_entry_t *	ci_svs_updir;
 	paddr_t		ci_svs_updirpa;
 	paddr_t		ci_svs_kpdirpa;
 	kmutex_t	ci_svs_mtx;
 #endif
 #if defined(XEN) && (defined(PAE) || defined(__x86_64__))
 	/* Currently active user PGD (can't use rcr3() with Xen) */
 	pd_entry_t *	ci_kpm_pdir;	/* per-cpu PMD (va) */
 	paddr_t		ci_kpm_pdirpa;  /* per-cpu PMD (pa) */
 	kmutex_t	ci_kpm_mtx;
 #if defined(__x86_64__)
 	/* per-cpu version of normal_pdes */
 	pd_entry_t *	ci_normal_pdes[3]; /* Ok to hardcode. only for x86_64 && XEN */
 	paddr_t		ci_xen_current_user_pgd;
 #endif /* __x86_64__ */
 #endif /* XEN et.al */
 #ifdef XEN
 @@ -323,26 +331,27 @@ lwp_t   *x86_curlwp(void);
 #define	X86_AST_PREEMPT		0x02
 #define aston(l, why)		((l)->l_md.md_astpending |= (why))
 #define	cpu_did_resched(l)	((l)->l_md.md_astpending &= ~X86_AST_PREEMPT)
 void cpu_boot_secondary_processors(void);
 void cpu_init_idle_lwps(void);
 void cpu_init_msrs(struct cpu_info *, bool);
 void cpu_load_pmap(struct pmap *, struct pmap *);
 void cpu_broadcast_halt(void);
 void cpu_kick(struct cpu_info *);
 void cpu_pcpuarea_init(struct cpu_info *);
 void cpu_svs_init(struct cpu_info *);
 #define	curcpu()		x86_curcpu()
 #define	curlwp			x86_curlwp()
 #define	curpcb			((struct pcb *)lwp_getpcb(curlwp))
 /*
  * Arguments to hardclock, softclock and statclock
  * encapsulate the previous machine state in an opaque
  * clockframe; for now, use generic intrframe.
  */
 struct clockframe {
 	struct intrframe cf_if;
 };

 @@ -1,14 +1,14 @@
-/*	$NetBSD: cpu.c,v 1.143 2018/01/07 10:16:13 maxv Exp $	*/
+/*	$NetBSD: cpu.c,v 1.144 2018/01/07 16:10:16 maxv Exp $	*/
 /*
  * Copyright (c) 2000-2012 NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Bill Sommerfeld of RedBack Networks Inc, and by Andrew Doran.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -52,32 +52,33 @@
  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.143 2018/01/07 10:16:13 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.144 2018/01/07 16:10:16 maxv Exp $");
 #include "opt_ddb.h"
 #include "opt_mpbios.h"		/* for MPDEBUG */
 #include "opt_mtrr.h"
 #include "opt_multiprocessor.h"
 #include "opt_svs.h"
 #include "lapic.h"
 #include "ioapic.h"
 #include <sys/param.h>
 #include <sys/proc.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <sys/cpu.h>
 #include <sys/cpufreq.h>
 #include <sys/idle.h>
 #include <sys/atomic.h>
 #include <sys/reboot.h>
 @@ -369,26 +370,30 @@ cpu_attach(device_t parent, device_t sel
+	}
 	ci->ci_self = ci;
 	sc->sc_info = ci;
 	ci->ci_dev = self;
 	ci->ci_acpiid = caa->cpu_id;
 	ci->ci_cpuid = caa->cpu_number;
 	ci->ci_func = caa->cpu_func;
 	aprint_normal("\n");
 	/* Must be before mi_cpu_attach(). */
 	cpu_vm_init(ci);
 #ifdef SVS
 	cpu_svs_init(ci);
 #endif
 	if (caa->cpu_role == CPU_ROLE_AP) {
 		int error;
 		error = mi_cpu_attach(ci);
 		if (error != 0) {
 			aprint_error_dev(self,
 			    "mi_cpu_attach failed with %d\n", error);
 			return;
+		}
 #ifdef __HAVE_PCPU_AREA
 		cpu_pcpuarea_init(ci);
 #endif
 		cpu_init_tss(ci);
 @@ -1238,26 +1243,30 @@ x86_cpu_idle_halt(void)
 	if (!__predict_false(ci->ci_want_resched)) {
 		x86_stihlt();
 	} else {
 		x86_enable_intr();
+	}
+}
 /*
  * Loads pmap for the current CPU.
  */
 void
 cpu_load_pmap(struct pmap *pmap, struct pmap *oldpmap)
+{
 #ifdef SVS
 	svs_pdir_switch(pmap);
 #endif
 #ifdef PAE
 	struct cpu_info *ci = curcpu();
 	bool interrupts_enabled;
 	pd_entry_t *l3_pd = ci->ci_pae_l3_pdir;
 	int i;
 	/*
 	 * disable interrupts to block TLB shootdowns, which can reload cr3.
 	 * while this doesn't block NMIs, it's probably ok as NMIs unlikely
 	 * reload cr3.
 	 */
 	interrupts_enabled = (x86_read_flags() & PSL_I) != 0;
 	if (interrupts_enabled)

 @@ -1,14 +1,14 @@
-/*	$NetBSD: pmap.c,v 1.277 2018/01/05 09:13:48 martin Exp $	*/
+/*	$NetBSD: pmap.c,v 1.278 2018/01/07 16:10:16 maxv Exp $	*/
 /*
  * Copyright (c) 2008, 2010, 2016, 2017 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Andrew Doran, and by Maxime Villard.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -160,32 +160,33 @@
  *     Hibler/Jolitz pmap, as modified for FreeBSD by John S. Dyson
  *     and David Greenman.
+ *
  * [3] the Mach pmap.   this pmap, from CMU, seems to have migrated
  *     between several processors.   the VAX version was done by
  *     Avadis Tevanian, Jr., and Michael Wayne Young.    the i386
  *     version was done by Lance Berc, Mike Kupfer, Bob Baron,
  *     David Golub, and Richard Draves.    the alpha version was
  *     done by Alessandro Forin (CMU/Mach) and Chris Demetriou
  *     (NetBSD/alpha).
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.277 2018/01/05 09:13:48 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.278 2018/01/07 16:10:16 maxv Exp $");
 #include "opt_user_ldt.h"
 #include "opt_lockdebug.h"
 #include "opt_multiprocessor.h"
 #include "opt_xen.h"
 #include "opt_svs.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/proc.h>
 #include <sys/pool.h>
 #include <sys/kernel.h>
 #include <sys/atomic.h>
 #include <sys/cpu.h>
 #include <sys/intr.h>
 #include <sys/xcall.h>
 #include <sys/kcore.h>
 #include <uvm/uvm.h>
 @@ -548,29 +549,31 @@ extern int end;
 extern vaddr_t pentium_idt_vaddr;
 #endif
 /*
  * Local prototypes
  */
 #ifdef __HAVE_PCPU_AREA
 static void pmap_init_pcpu(void);
 #endif
 #ifdef __HAVE_DIRECT_MAP
 static void pmap_init_directmap(struct pmap *);
 #endif
 #if !defined(XEN) && !defined(SVS)
 static void pmap_remap_global(void);
 #endif
 #ifndef XEN
 static void pmap_init_lapic(void);
 static void pmap_remap_global(void);
 static void pmap_remap_largepages(void);
 #endif
 static struct vm_page *pmap_get_ptp(struct pmap *, vaddr_t,
     pd_entry_t * const *, int);
 static struct vm_page *pmap_find_ptp(struct pmap *, vaddr_t, paddr_t, int);
 static void pmap_freepage(struct pmap *, struct vm_page *, int);
 static void pmap_free_ptp(struct pmap *, struct vm_page *, vaddr_t,
     pt_entry_t *, pd_entry_t * const *);
 static bool pmap_remove_pte(struct pmap *, struct vm_page *, pt_entry_t *,
     vaddr_t, struct pv_entry **);
 static void pmap_remove_ptes(struct pmap *, struct vm_page *, vaddr_t, vaddr_t,
     vaddr_t, struct pv_entry **);
 @@ -1276,40 +1279,42 @@ pmap_bootstrap(vaddr_t kva_start)
 	kcpuset_create(&kpm->pm_cpus, true);
 	kcpuset_create(&kpm->pm_kernel_cpus, true);
 	kpm->pm_ldt = NULL;
 	kpm->pm_ldt_len = 0;
 	kpm->pm_ldt_sel = GSYSSEL(GLDT_SEL, SEL_KPL);
 	/*
 	 * the above is just a rough estimate and not critical to the proper
 	 * operation of the system.
 	 */
-#ifndef XEN
+#if !defined(XEN) && !defined(SVS)
 	/*
 	 * Begin to enable global TLB entries if they are supported.
 	 * The G bit has no effect until the CR4_PGE bit is set in CR4,
 	 * which happens in cpu_init(), which is run on each cpu
 	 * (and happens later)
 	 */
 	if (cpu_feature[0] & CPUID_PGE) {
 		pmap_pg_g = PG_G;		/* enable software */
 		/* add PG_G attribute to already mapped kernel pages */
 		pmap_remap_global();
+	}
 #endif
 #ifndef XEN
 	/*
 	 * Enable large pages if they are supported.
 	 */
 	if (cpu_feature[0] & CPUID_PSE) {
 		lcr4(rcr4() | CR4_PSE);	/* enable hardware (via %cr4) */
 		pmap_largepages = 1;	/* enable software */
 		/*
 		 * The TLB must be flushed after enabling large pages on Pentium
 		 * CPUs, according to section 3.6.2.2 of "Intel Architecture
 		 * Software Developer's Manual, Volume 3: System Programming".
 		 */
 		tlbflushg();
 @@ -1638,27 +1643,27 @@ pmap_init_directmap(struct pmap *kpm)
 	*pte = 0;
 	pmap_update_pg(tmpva);
 	pmap_direct_base = startva;
 	pmap_direct_end = endva;
 	pmap_direct_pdpe = L4e_idx;
 	pmap_direct_npdp = nL4e;
 	tlbflush();
+}
 #endif /* __HAVE_DIRECT_MAP */
-#ifndef XEN
+#if !defined(XEN) && !defined(SVS)
 /*
  * Remap all of the virtual pages created so far with the PG_G bit.
  */
 static void
 pmap_remap_global(void)
+{
 	vaddr_t kva, kva_end;
 	unsigned long p1i;
 	size_t i;
 	/* head */
 	kva = bootspace.head.va;
 	kva_end = kva + bootspace.head.sz;
 @@ -1681,27 +1686,29 @@ pmap_remap_global(void)
 				PTE_BASE[p1i] |= PG_G;
+		}
+	}
 	/* boot space */
 	kva = bootspace.boot.va;
 	kva_end = kva + bootspace.boot.sz;
 	for ( ; kva < kva_end; kva += PAGE_SIZE) {
 		p1i = pl1_i(kva);
 		if (pmap_valid_entry(PTE_BASE[p1i]))
 			PTE_BASE[p1i] |= PG_G;
+	}
+}
 #endif
 #ifndef XEN
 /*
  * Remap several kernel segments with large pages. We cover as many pages as we
  * can. Called only once at boot time, if the CPU supports large pages.
  */
 static void
 pmap_remap_largepages(void)
+{
 	pd_entry_t *pde;
 	vaddr_t kva, kva_end;
 	paddr_t pa;
 	size_t i;
 	/* Remap the kernel text using large pages. */
 @@ -2103,33 +2110,37 @@ pmap_free_ptp(struct pmap *pmap, struct
 	vaddr_t invaladdr;
 	pd_entry_t opde;
 	KASSERT(pmap != pmap_kernel());
 	KASSERT(mutex_owned(pmap->pm_lock));
 	KASSERT(kpreempt_disabled());
 	level = 1;
 	do {
 		index = pl_i(va, level + 1);
 		opde = pmap_pte_testset(&pdes[level - 1][index], 0);
 		/*
-		 * On Xen-amd64, we need to sync the top level page
+		 * On Xen-amd64 or SVS, we need to sync the top level page
 		 * directory on each CPU.
 		 */
 #if defined(XEN) && defined(__x86_64__)
 		if (level == PTP_LEVELS - 1) {
 			xen_kpm_sync(pmap, index);
+		}
 #elif defined(SVS)
 		if (level == PTP_LEVELS - 1) {
 			svs_pmap_sync(pmap, index);
+		}
 #endif
 		invaladdr = level == 1 ? (vaddr_t)ptes :
 		    (vaddr_t)pdes[level - 2];
 		pmap_tlb_shootdown(pmap, invaladdr + index * PAGE_SIZE,
 		    opde, TLBSHOOT_FREE_PTP1);
 #if defined(XEN)
 		pmap_tlb_shootnow();
 #endif
 		pmap_freepage(pmap, ptp, level);
 		if (level < PTP_LEVELS - 1) {
 @@ -2204,33 +2215,37 @@ pmap_get_ptp(struct pmap *pmap, vaddr_t
 			KASSERT(!pt[i].new);
 			continue;
+		}
 		ptp = pt[i].pg;
 		ptp->flags &= ~PG_BUSY; /* never busy */
 		ptp->wire_count = 1;
 		pmap->pm_ptphint[i - 2] = ptp;
 		pa = VM_PAGE_TO_PHYS(ptp);
 		pmap_pte_set(&pva[index], (pd_entry_t)
 		    (pmap_pa2pte(pa) | PG_u | PG_RW | PG_V));
 		/*
-		 * On Xen-amd64, we need to sync the top level page
+		 * On Xen-amd64 or SVS, we need to sync the top level page
 		 * directory on each CPU.
 		 */
 #if defined(XEN) && defined(__x86_64__)
 		if (i == PTP_LEVELS) {
 			xen_kpm_sync(pmap, index);
+		}
 #elif defined(SVS)
 		if (i == PTP_LEVELS) {
 			svs_pmap_sync(pmap, index);
+		}
 #endif
 		pmap_pte_flush();
 		pmap_stats_update(pmap, 1, 0);
 		/*
 		 * If we're not in the top level, increase the
 		 * wire count of the parent page.
 		 */
 		if (i < PTP_LEVELS) {
 			pt[i + 1].pg->wire_count++;
+		}
+	}

 @@ -1,14 +1,14 @@
-#	$NetBSD: files.amd64,v 1.97 2018/01/01 08:14:13 maxv Exp $
+#	$NetBSD: files.amd64,v 1.98 2018/01/07 16:10:16 maxv Exp $
+#
 # new style config file for amd64 architecture
+#
 ifndef xen
 # maxpartitions must be first item in files.${ARCH}.newconf
 maxpartitions 16
 maxusers 2 16 128
 # delay before cpu_reset() for reboot.
 defparam		CPURESET_DELAY
 @@ -17,26 +17,27 @@ defparam		CPURESET_DELAY
 defparam opt_realmem.h	REALBASEMEM REALEXTMEM
 # The PHYSMEM_MAX_{SIZE,ADDR} optionms
 defparam opt_physmem.h	PHYSMEM_MAX_ADDR PHYSMEM_MAX_SIZE
+#
 # XXX these are just here at the moment so that we can share files
 # with the i386 (they include the opt_*.h for these)
+#
 defflag			PMC
 defflag			USER_LDT
 defflag			KASLR
 defflag			SVS
 defflag eisa.h EISA
 # Start code
 file	arch/amd64/amd64/locore.S		machdep
 file	arch/amd64/amd64/vector.S		machdep
 file	arch/amd64/amd64/copy.S			machdep
 file	arch/amd64/amd64/spl.S			machdep
 file	arch/amd64/amd64/amd64func.S		machdep
 file	arch/amd64/amd64/autoconf.c		machdep
 file	arch/amd64/amd64/busfunc.S		machdep
 file	arch/amd64/amd64/cpu_in_cksum.S		(inet | inet6) & cpu_in_cksum
 file	arch/amd64/amd64/cpufunc.S		machdep