 @@ -1,14 +1,14 @@
-/*	$NetBSD: machdep.c,v 1.782.6.2 2018/01/01 19:09:03 snj Exp $	*/
+/*	$NetBSD: machdep.c,v 1.782.6.3 2018/03/08 11:33:15 martin Exp $	*/
 /*-
  * Copyright (c) 1996, 1997, 1998, 2000, 2004, 2006, 2008, 2009
  *     The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Charles M. Hannum, by Jason R. Thorpe of the Numerical Aerospace
  * Simulation Facility NASA Ames Research Center, by Julio M. Merino Vidal,
  * and by Andrew Doran.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
 @@ -57,27 +57,27 @@
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  *	@(#)machdep.c	7.4 (Berkeley) 6/3/91
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.782.6.2 2018/01/01 19:09:03 snj Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.782.6.3 2018/03/08 11:33:15 martin Exp $");
 #include "opt_beep.h"
 #include "opt_compat_ibcs2.h"
 #include "opt_compat_freebsd.h"
 #include "opt_compat_netbsd.h"
 #include "opt_compat_svr4.h"
 #include "opt_cpureset_delay.h"
 #include "opt_ddb.h"
 #include "opt_ipkdb.h"
 #include "opt_kgdb.h"
 #include "opt_mtrr.h"
 #include "opt_modular.h"
 #include "opt_multiboot.h"
 @@ -568,27 +568,98 @@ i386_tls_switch(lwp_t *l)
 	if (l != ci->ci_fpcurlwp) {
 		HYPERVISOR_fpu_taskswitch(1);
+	}
 	/* Update TLS segment pointers */
 	update_descriptor(&ci->ci_gdt[GUFS_SEL],
 			  (union descriptor *) &pcb->pcb_fsd);
 	update_descriptor(&ci->ci_gdt[GUGS_SEL],
 			  (union descriptor *) &pcb->pcb_gsd);
+}
 #endif /* XEN */
 /* XXX */
 #define IDTVEC(name)	__CONCAT(X, name)
 typedef void (vector)(void);
 #ifndef XEN
 static void	tss_init(struct i386tss *, void *, void *);
 static void
 tss_init(struct i386tss *tss, void *stack, void *func)
+{
 	KASSERT(curcpu()->ci_pmap == pmap_kernel());
 	memset(tss, 0, sizeof *tss);
 	tss->tss_esp0 = tss->tss_esp = (int)((char *)stack + USPACE - 16);
 	tss->tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
 	tss->__tss_cs = GSEL(GCODE_SEL, SEL_KPL);
 	tss->tss_fs = GSEL(GCPU_SEL, SEL_KPL);
 	tss->tss_gs = tss->__tss_es = tss->__tss_ds =
 	    tss->__tss_ss = GSEL(GDATA_SEL, SEL_KPL);
 	/* %cr3 contains the value associated to pmap_kernel */
 	tss->tss_cr3 = rcr3();
 	tss->tss_esp = (int)((char *)stack + USPACE - 16);
 	tss->tss_ldt = GSEL(GLDT_SEL, SEL_KPL);
 	tss->__tss_eflags = PSL_MBO | PSL_NT;	/* XXX not needed? */
 	tss->__tss_eip = (int)func;
+}
 extern vector IDTVEC(tss_trap08);
 #if defined(DDB) && defined(MULTIPROCESSOR)
 extern vector Xintrddbipi, Xx2apic_intrddbipi;
 extern int ddb_vec;
 #endif
 void
 cpu_set_tss_gates(struct cpu_info *ci)
+{
 	struct segment_descriptor sd;
 	ci->ci_doubleflt_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0,
 	    UVM_KMF_WIRED);
 	tss_init(&ci->ci_doubleflt_tss, ci->ci_doubleflt_stack,
 	    IDTVEC(tss_trap08));
 	setsegment(&sd, &ci->ci_doubleflt_tss, sizeof(struct i386tss) - 1,
 	    SDT_SYS386TSS, SEL_KPL, 0, 0);
 	ci->ci_gdt[GTRAPTSS_SEL].sd = sd;
 	setgate(&idt[8], NULL, 0, SDT_SYSTASKGT, SEL_KPL,
 	    GSEL(GTRAPTSS_SEL, SEL_KPL));
 #if defined(DDB) && defined(MULTIPROCESSOR)
 	/*
 	 * Set up separate handler for the DDB IPI, so that it doesn't
 	 * stomp on a possibly corrupted stack.
+	 *
 	 * XXX overwriting the gate set in db_machine_init.
 	 * Should rearrange the code so that it's set only once.
 	 */
 	ci->ci_ddbipi_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0,
 	    UVM_KMF_WIRED);
 	tss_init(&ci->ci_ddbipi_tss, ci->ci_ddbipi_stack,
 	    x2apic_mode ? Xx2apic_intrddbipi : Xintrddbipi);
 	setsegment(&sd, &ci->ci_ddbipi_tss, sizeof(struct i386tss) - 1,
 	    SDT_SYS386TSS, SEL_KPL, 0, 0);
 	ci->ci_gdt[GIPITSS_SEL].sd = sd;
 	setgate(&idt[ddb_vec], NULL, 0, SDT_SYSTASKGT, SEL_KPL,
 	    GSEL(GIPITSS_SEL, SEL_KPL));
 #endif
+}
 /*
  * Set up TSS and I/O bitmap.
  */
 void
 cpu_init_tss(struct cpu_info *ci)
+{
 	struct i386tss *tss = &ci->ci_tss;
 	tss->tss_iobase = IOMAP_INVALOFF << 16;
 	tss->tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
 	tss->tss_ldt = GSEL(GLDT_SEL, SEL_KPL);
 	tss->tss_cr3 = rcr3();
 	ci->ci_tss_sel = tss_alloc(tss);
 @@ -920,28 +991,27 @@ setsegment(struct segment_descriptor *sd
 	sd->sd_lolimit = (int)limit;
 	sd->sd_lobase = (int)base;
 	sd->sd_type = type;
 	sd->sd_dpl = dpl;
 	sd->sd_p = 1;
 	sd->sd_hilimit = (int)limit >> 16;
 	sd->sd_xx = 0;
 	sd->sd_def32 = def32;
 	sd->sd_gran = gran;
 	sd->sd_hibase = (int)base >> 24;
+}
-#define	IDTVEC(name)	__CONCAT(X, name)
+/* XXX */
 typedef void (vector)(void);
 extern vector IDTVEC(syscall);
 extern vector *IDTVEC(exceptions)[];
 extern vector IDTVEC(svr4_fasttrap);
 void (*svr4_fasttrap_vec)(void) = (void (*)(void))nullop;
 krwlock_t svr4_fasttrap_lock;
 #ifdef XEN
 #define MAX_XEN_IDT 128
 trap_info_t xen_idt[MAX_XEN_IDT];
 int xen_idt_idx;
 extern union descriptor tmpgdt[];
 #endif
 void

 @@ -1,14 +1,14 @@
-/*	$NetBSD: cpu.h,v 1.71 2017/05/23 08:48:34 nonaka Exp $	*/
+/*	$NetBSD: cpu.h,v 1.71.2.1 2018/03/08 11:33:15 martin Exp $	*/
 /*-
  * Copyright (c) 1990 The Regents of the University of California.
  * All rights reserved.
+ *
  * This code is derived from software contributed to Berkeley by
  * William Jolitz.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -396,26 +396,29 @@ extern int i386_has_sse2;
 extern int x86_fpu_save;
 #define	FPU_SAVE_FSAVE		0
 #define	FPU_SAVE_FXSAVE		1
 #define	FPU_SAVE_XSAVE		2
 #define	FPU_SAVE_XSAVEOPT	3
 extern unsigned int x86_fpu_save_size;
 extern uint64_t x86_xsave_features;
 extern void (*x86_cpu_idle)(void);
 #define	cpu_idle() (*x86_cpu_idle)()
 /* machdep.c */
 #ifdef i386
 void	cpu_set_tss_gates(struct cpu_info *);
 #endif
 void	dumpconf(void);
 void	cpu_reset(void);
 void	i386_proc0_tss_ldt_init(void);
 void	dumpconf(void);
 void	cpu_reset(void);
 void	x86_64_proc0_tss_ldt_init(void);
 void	x86_64_init_pcb_tss_ldt(struct cpu_info *);
 /* longrun.c */
 u_int 	tmx86_get_longrun_mode(void);
 void 	tmx86_get_longrun_status(u_int *, u_int *, u_int *);
 void 	tmx86_init_longrun(void);
 @@ -428,59 +431,56 @@ typedef enum vm_guest {
 	VM_GUEST_NO = 0,
 	VM_GUEST_VM,
 	VM_GUEST_XEN,
 	VM_GUEST_HV,
 	VM_GUEST_VMWARE,
 	VM_GUEST_KVM,
 	VM_LAST
 } vm_guest_t;
 extern vm_guest_t vm_guest;
 /* cpu_topology.c */
 void	x86_cpu_topology(struct cpu_info *);
 /* vm_machdep.c */
 void	cpu_proc_fork(struct proc *, struct proc *);
 /* locore.s */
 struct region_descriptor;
 void	lgdt(struct region_descriptor *);
 #ifdef XEN
 void	lgdt_finish(void);
 #endif
 struct pcb;
 void	savectx(struct pcb *);
 void	lwp_trampoline(void);
 #ifdef XEN
 void	startrtclock(void);
 void	xen_delay(unsigned int);
 void	xen_initclocks(void);
 void	xen_suspendclocks(struct cpu_info *);
 void	xen_resumeclocks(struct cpu_info *);
 #else
 /* clock.c */
 void	initrtclock(u_long);
 void	startrtclock(void);
 void	i8254_delay(unsigned int);
 void	i8254_microtime(struct timeval *);
 void	i8254_initclocks(void);
 #endif
 /* cpu.c */
 void	cpu_probe_features(struct cpu_info *);
 /* vm_machdep.c */
 void	cpu_proc_fork(struct proc *, struct proc *);
 paddr_t	kvtop(void *);
 #ifdef USER_LDT
 /* sys_machdep.h */
 int	x86_get_ldt(struct lwp *, void *, register_t *);
 int	x86_set_ldt(struct lwp *, void *, register_t *);
 #endif
 /* isa_machdep.c */
 void	isa_defaultirq(void);
 int	isa_nmi(void);
 #ifdef VM86

 @@ -1,14 +1,14 @@
-/*	$NetBSD: cpu.c,v 1.130.2.2 2018/03/07 14:50:57 martin Exp $	*/
+/*	$NetBSD: cpu.c,v 1.130.2.3 2018/03/08 11:33:15 martin Exp $	*/
 /*-
  * Copyright (c) 2000-2012 NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Bill Sommerfeld of RedBack Networks Inc, and by Andrew Doran.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -52,27 +52,27 @@
  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.130.2.2 2018/03/07 14:50:57 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.130.2.3 2018/03/08 11:33:15 martin Exp $");
 #include "opt_ddb.h"
 #include "opt_mpbios.h"		/* for MPDEBUG */
 #include "opt_mtrr.h"
 #include "opt_multiprocessor.h"
 #include "lapic.h"
 #include "ioapic.h"
 #include <sys/param.h>
 #include <sys/proc.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 @@ -154,51 +154,47 @@ CFATTACH_DECL2_NEW(cpu, sizeof(struct cp
  * point at it.
  */
 #ifdef TRAPLOG
 struct tlog tlog_primary;
 #endif
 struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = {
 	.ci_dev = 0,
 	.ci_self = &cpu_info_primary,
 	.ci_idepth = -1,
 	.ci_curlwp = &lwp0,
 	.ci_curldt = -1,
 #ifdef TRAPLOG
 	.ci_tlog_base = &tlog_primary,
-#endif /* !TRAPLOG */
+#endif
 };
 struct cpu_info *cpu_info_list = &cpu_info_primary;
 static void	cpu_set_tss_gates(struct cpu_info *);
 #ifdef i386
-static void	tss_init(struct i386tss *, void *, void *);
+void		cpu_set_tss_gates(struct cpu_info *);
 #endif
 static void	cpu_init_idle_lwp(struct cpu_info *);
 uint32_t cpu_feature[7] __read_mostly; /* X86 CPUID feature bits */
 			/* [0] basic features cpuid.1:%edx
 			 * [1] basic features cpuid.1:%ecx (CPUID2_xxx bits)
 			 * [2] extended features cpuid:80000001:%edx
 			 * [3] extended features cpuid:80000001:%ecx
 			 * [4] VIA padlock features
 			 * [5] structured extended features cpuid.7:%ebx
 			 * [6] structured extended features cpuid.7:%ecx
 			 */
 extern char x86_64_doubleflt_stack[];
 #ifdef MULTIPROCESSOR
 bool x86_mp_online;
 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE;
 #endif
 #if NLAPIC > 0
 static vaddr_t cmos_data_mapping;
 #endif
 struct cpu_info *cpu_starting;
 #ifdef MULTIPROCESSOR
 void    	cpu_hatch(void *);
 static void    	cpu_boot_secondary(struct cpu_info *ci);
 static void    	cpu_start_secondary(struct cpu_info *ci);
 @@ -385,27 +381,29 @@ cpu_attach(device_t parent, device_t sel
 	ci->ci_pmap = pmap_kernel();
 	ci->ci_tlbstate = TLBSTATE_STALE;
 	/*
 	 * Boot processor may not be attached first, but the below
 	 * must be done to allow booting other processors.
 	 */
 	if (!again) {
 		atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY);
 		/* Basic init. */
 		cpu_intr_init(ci);
 		cpu_get_tsc_freq(ci);
 		cpu_init(ci);
 #ifdef i386
 		cpu_set_tss_gates(ci);
 #endif
 		pmap_cpu_init_late(ci);
 #if NLAPIC > 0
 		if (caa->cpu_role != CPU_ROLE_SP) {
 			/* Enable lapic. */
 			lapic_enable();
 			lapic_set_lvt();
 			lapic_calibrate_timer(ci);
+		}
 #endif
 		/* Make sure DELAY() is initialized. */
 		DELAY(1);
 		again = true;
+	}
 @@ -424,27 +422,29 @@ cpu_attach(device_t parent, device_t sel
 		atomic_or_32(&ci->ci_flags, CPUF_BSP);
 		cpu_identify(ci);
 		x86_errata();
 		x86_cpu_idle_init();
 		break;
 #ifdef MULTIPROCESSOR
 	case CPU_ROLE_AP:
 		/*
 		 * report on an AP
 		 */
 		cpu_intr_init(ci);
 		gdt_alloc_cpu(ci);
 #ifdef i386
 		cpu_set_tss_gates(ci);
 #endif
 		pmap_cpu_init_late(ci);
 		cpu_start_secondary(ci);
 		if (ci->ci_flags & CPUF_PRESENT) {
 			struct cpu_info *tmp;
 			cpu_identify(ci);
 			tmp = cpu_info_list;
 			while (tmp->ci_next)
 				tmp = tmp->ci_next;
 			tmp->ci_next = ci;
+		}
 		break;
 @@ -491,27 +491,26 @@ cpu_defer(device_t self)
+}
 static int
 cpu_rescan(device_t self, const char *ifattr, const int *locators)
+{
 	struct cpu_softc *sc = device_private(self);
 	struct cpufeature_attach_args cfaa;
 	struct cpu_info *ci = sc->sc_info;
 	memset(&cfaa, 0, sizeof(cfaa));
 	cfaa.ci = ci;
 	if (ifattr_match(ifattr, "cpufeaturebus")) {
 		if (ci->ci_frequency == NULL) {
 			cfaa.name = "frequency";
 			ci->ci_frequency = config_found_ia(self,
 			    "cpufeaturebus", &cfaa, NULL);
+		}
 		if (ci->ci_padlock == NULL) {
 			cfaa.name = "padlock";
 			ci->ci_padlock = config_found_ia(self,
 			    "cpufeaturebus", &cfaa, NULL);
+		}
 		if (ci->ci_temperature == NULL) {
 @@ -798,43 +797,43 @@ cpu_boot_secondary(struct cpu_info *ci)
  * this processor will enter the idle loop and start looking for work.
  */
 void
 cpu_hatch(void *v)
+{
 	struct cpu_info *ci = (struct cpu_info *)v;
 	struct pcb *pcb;
 	int s, i;
 	cpu_init_msrs(ci, true);
 	cpu_probe(ci);
 	ci->ci_data.cpu_cc_freq = cpu_info_primary.ci_data.cpu_cc_freq;
 	/* cpu_get_tsc_freq(ci); */
 	KDASSERT((ci->ci_flags & CPUF_PRESENT) == 0);
 	/*
 	 * Synchronize time stamp counters.  Invalidate cache and do twice
 	 * to try and minimize possible cache effects.  Note that interrupts
 	 * are off at this point.
 	 */
 	wbinvd();
 	atomic_or_32(&ci->ci_flags, CPUF_PRESENT);
 	tsc_sync_ap(ci);
 	/*
 	 * Wait to be brought online.  Use 'monitor/mwait' if available,
 	 * in order to make the TSC drift as much as possible. so that
 	 * we can detect it later.  If not available, try 'pause'.
 	 * We'd like to use 'hlt', but we have interrupts off.
 	 */
 	while ((ci->ci_flags & CPUF_GO) == 0) {
 		if ((cpu_feature[1] & CPUID2_MONITOR) != 0) {
 			x86_monitor(&ci->ci_flags, 0, 0);
 			if ((ci->ci_flags & CPUF_GO) != 0) {
 				continue;
+			}
 			x86_mwait(0, 0);
 		} else {
 	/*
 	 * XXX The loop repetition count could be a lot higher, but
 	 * XXX currently qemu emulator takes a _very_long_time_ to
 @@ -923,119 +922,45 @@ cpu_debug_dump(void)
+	}
+}
 #endif
 #if NLAPIC > 0
 static void
 cpu_copy_trampoline(void)
+{
 	/*
 	 * Copy boot code.
 	 */
 	extern u_char cpu_spinup_trampoline[];
 	extern u_char cpu_spinup_trampoline_end[];
 	vaddr_t mp_trampoline_vaddr;
 	mp_trampoline_vaddr = uvm_km_alloc(kernel_map, PAGE_SIZE, 0,
 	    UVM_KMF_VAONLY);
 	pmap_kenter_pa(mp_trampoline_vaddr, mp_trampoline_paddr,
 	    VM_PROT_READ | VM_PROT_WRITE, 0);
 	pmap_update(pmap_kernel());
 	memcpy((void *)mp_trampoline_vaddr,
 	    cpu_spinup_trampoline,
 	    cpu_spinup_trampoline_end - cpu_spinup_trampoline);
 	pmap_kremove(mp_trampoline_vaddr, PAGE_SIZE);
 	pmap_update(pmap_kernel());
 	uvm_km_free(kernel_map, mp_trampoline_vaddr, PAGE_SIZE, UVM_KMF_VAONLY);
+}
 #endif
 #ifdef i386
 static void
 tss_init(struct i386tss *tss, void *stack, void *func)
 	KASSERT(curcpu()->ci_pmap == pmap_kernel());
 	memset(tss, 0, sizeof *tss);
 	tss->tss_esp0 = tss->tss_esp = (int)((char *)stack + USPACE - 16);
 	tss->tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
 	tss->__tss_cs = GSEL(GCODE_SEL, SEL_KPL);
 	tss->tss_fs = GSEL(GCPU_SEL, SEL_KPL);
 	tss->tss_gs = tss->__tss_es = tss->__tss_ds =
 	    tss->__tss_ss = GSEL(GDATA_SEL, SEL_KPL);
 	/* %cr3 contains the value associated to pmap_kernel */
 	tss->tss_cr3 = rcr3();
 	tss->tss_esp = (int)((char *)stack + USPACE - 16);
 	tss->tss_ldt = GSEL(GLDT_SEL, SEL_KPL);
 	tss->__tss_eflags = PSL_MBO | PSL_NT;	/* XXX not needed? */
 	tss->__tss_eip = (int)func;
 /* XXX */
 #define IDTVEC(name)	__CONCAT(X, name)
 typedef void (vector)(void);
 extern vector IDTVEC(tss_trap08);
 #if defined(DDB) && defined(MULTIPROCESSOR)
 extern vector Xintrddbipi, Xx2apic_intrddbipi;
 extern int ddb_vec;
 #endif
 static void
 cpu_set_tss_gates(struct cpu_info *ci)
 	struct segment_descriptor sd;
 	ci->ci_doubleflt_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0,
 	    UVM_KMF_WIRED);
 	tss_init(&ci->ci_doubleflt_tss, ci->ci_doubleflt_stack,
 	    IDTVEC(tss_trap08));
 	setsegment(&sd, &ci->ci_doubleflt_tss, sizeof(struct i386tss) - 1,
 	    SDT_SYS386TSS, SEL_KPL, 0, 0);
 	ci->ci_gdt[GTRAPTSS_SEL].sd = sd;
 	setgate(&idt[8], NULL, 0, SDT_SYSTASKGT, SEL_KPL,
 	    GSEL(GTRAPTSS_SEL, SEL_KPL));
 #if defined(DDB) && defined(MULTIPROCESSOR)
 	/*
 	 * Set up separate handler for the DDB IPI, so that it doesn't
 	 * stomp on a possibly corrupted stack.
 	 * XXX overwriting the gate set in db_machine_init.
 	 * Should rearrange the code so that it's set only once.
 	 */
 	ci->ci_ddbipi_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0,
 	    UVM_KMF_WIRED);
 	tss_init(&ci->ci_ddbipi_tss, ci->ci_ddbipi_stack,
 	    x2apic_mode ? Xx2apic_intrddbipi : Xintrddbipi);
 	setsegment(&sd, &ci->ci_ddbipi_tss, sizeof(struct i386tss) - 1,
 	    SDT_SYS386TSS, SEL_KPL, 0, 0);
 	ci->ci_gdt[GIPITSS_SEL].sd = sd;
 	setgate(&idt[ddb_vec], NULL, 0, SDT_SYSTASKGT, SEL_KPL,
 	    GSEL(GIPITSS_SEL, SEL_KPL));
 #endif
 #else
 static void
 cpu_set_tss_gates(struct cpu_info *ci)
 #endif	/* i386 */
 #ifdef MULTIPROCESSOR
 int
 mp_cpu_start(struct cpu_info *ci, paddr_t target)
+{
 	unsigned short dwordptr[2];
 	int error;
 	/*
 	 * Bootstrap code must be addressable in real mode
 	 * and it must be page aligned.
 	 */
 	KASSERT(target < 0x10000 && target % PAGE_SIZE == 0);
 @@ -1295,27 +1220,27 @@ cpu_load_pmap(struct pmap *pmap, struct
 	/*
 	 * disable interrupts to block TLB shootdowns, which can reload cr3.
 	 * while this doesn't block NMIs, it's probably ok as NMIs unlikely
 	 * reload cr3.
 	 */
 	interrupts_enabled = (x86_read_flags() & PSL_I) != 0;
 	if (interrupts_enabled)
 		x86_disable_intr();
 	for (i = 0 ; i < PDP_SIZE; i++) {
 		l3_pd[i] = pmap->pm_pdirpa[i] | PG_V;
+	}
 	if (interrupts_enabled)
 		x86_enable_intr();
 	tlbflush();
 #else /* PAE */
 	lcr3(pmap_pdirpa(pmap, 0));
 #endif /* PAE */
+}
 /*
  * Notify all other cpus to halt.
  */
 void