 @@ -1,14 +1,14 @@
-/*	$NetBSD: bus.c,v 1.59 2018/01/20 17:37:15 tsutsui Exp $	*/
+/*	$NetBSD: bus.c,v 1.60 2018/03/10 03:44:43 tsutsui Exp $	*/
 /*-
  * Copyright (c) 1998 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
  * NASA Ames Research Center and by Chris G. Demetriou.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
 @@ -23,27 +23,27 @@
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include "opt_m68k_arch.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: bus.c,v 1.59 2018/01/20 17:37:15 tsutsui Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bus.c,v 1.60 2018/03/10 03:44:43 tsutsui Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/extent.h>
 #include <sys/malloc.h>
 #include <sys/mbuf.h>
 #include <sys/proc.h>
 #include <uvm/uvm.h>
 #include <machine/cpu.h>
 #include <m68k/cacheops.h>
 #define	_ATARI_BUS_DMA_PRIVATE
 @@ -538,66 +538,223 @@ _bus_dmamap_unload(bus_dma_tag_t t, bus_
 	 * No resources to free; just mark the mappings as
 	 * invalid.
 	 */
 	map->dm_maxsegsz = map->_dm_maxmaxsegsz;
 	map->dm_mapsize = 0;
 	map->dm_nsegs = 0;
+}
 /*
  * Common function for DMA map synchronization.  May be called
  * by bus-specific DMA map synchronization functions.
  */
 void
-_bus_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t off,
+_bus_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset,
     bus_size_t len, int ops)
+{
 #if defined(M68040) || defined(M68060)
-	int	i, pa_off, inc, seglen;
+	bus_addr_t p, e, ps, pe;
-	u_long	pa, end_pa;
+	bus_size_t seglen;
 	bus_dma_segment_t *seg;
 	int i;
 #endif
-	pa_off = t->_displacement;
+#if defined(M68020) || defined(M68030)
 #if defined(M68040) || defined(M68060)
 	if (cputype == CPU_68020 || cputype == CPU_68030)
 #endif
 		/* assume no L2 physical cache */
 		return;
 #endif
-	/* Flush granularity */
+#if defined(M68040) || defined(M68060)
-	inc = (len > 1024) ? PAGE_SIZE : 16;
+	/* If the whole DMA map is uncached, do nothing. */
 	if ((map->_dm_flags & BUS_DMA_COHERENT) != 0)
 		return;
 	/* Short-circuit for unsupported `ops' */
 	if ((ops & (BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)) == 0)
 		return;
-	for (i = 0; i < map->dm_nsegs && len > 0; i++) {
+	/*
-		if (map->dm_segs[i].ds_len <= off) {
+	 * flush/purge the cache.
 	 */
 	for (i = 0; i < map->dm_nsegs && len != 0; i++) {
 		seg = &map->dm_segs[i];
 		if (seg->ds_len <= offset) {
 			/* Segment irrelevant - before requested offset */
-			off -= map->dm_segs[i].ds_len;
+			offset -= seg->ds_len;
 			continue;
+		}
 		seglen = map->dm_segs[i].ds_len - off;
 		/*
 		 * Now at the first segment to sync; nail
 		 * each segment until we have exhausted the
 		 * length.
 		 */
 		seglen = seg->ds_len - offset;
 		if (seglen > len)
 			seglen = len;
 		len -= seglen;
 		pa = map->dm_segs[i].ds_addr + off - pa_off;
 		end_pa = pa + seglen;
-		if (inc == 16) {
+		ps = seg->ds_addr + offset;
-			pa &= ~15;
+		pe = ps + seglen;
 			while (pa < end_pa) {
-				DCFL(pa);
+		if (ops & BUS_DMASYNC_PREWRITE) {
-				pa += 16;
+			p = ps & ~CACHELINE_MASK;
 			e = (pe + CACHELINE_MASK) & ~CACHELINE_MASK;
 			/* flush cacheline */
 			while ((p < e) && (p & (CACHELINE_SIZE * 8 - 1)) != 0) {
 				DCFL(p);
 				p += CACHELINE_SIZE;
+			}
 		} else {
-			pa &= ~PGOFSET;
+			/* flush cachelines per 128bytes */
-			while (pa < end_pa) {
+			while ((p < e) && (p & PAGE_MASK) != 0) {
-				DCFP(pa);
+				DCFL(p);
-				pa += PAGE_SIZE;
+				p += CACHELINE_SIZE;
 				DCFL(p);
 				p += CACHELINE_SIZE;
 				DCFL(p);
 				p += CACHELINE_SIZE;
 				DCFL(p);
 				p += CACHELINE_SIZE;
 				DCFL(p);
 				p += CACHELINE_SIZE;
 				DCFL(p);
 				p += CACHELINE_SIZE;
 				DCFL(p);
 				p += CACHELINE_SIZE;
 				DCFL(p);
 				p += CACHELINE_SIZE;
+			}
 			/* flush page */
 			while (p + PAGE_SIZE <= e) {
 				DCFP(p);
 				p += PAGE_SIZE;
+			}
 			/* flush cachelines per 128bytes */
 			while (p + CACHELINE_SIZE * 8 <= e) {
 				DCFL(p);
 				p += CACHELINE_SIZE;
 				DCFL(p);
 				p += CACHELINE_SIZE;
 				DCFL(p);
 				p += CACHELINE_SIZE;
 				DCFL(p);
 				p += CACHELINE_SIZE;
 				DCFL(p);
 				p += CACHELINE_SIZE;
 				DCFL(p);
 				p += CACHELINE_SIZE;
 				DCFL(p);
 				p += CACHELINE_SIZE;
 				DCFL(p);
 				p += CACHELINE_SIZE;
+			}
 			/* flush cacheline */
 			while (p < e) {
 				DCFL(p);
 				p += CACHELINE_SIZE;
+			}
+		}
 		/*
 		 * Normally, the `PREREAD' flag instructs us to purge the
 		 * cache for the specified offset and length. However, if
 		 * the offset/length is not aligned to a cacheline boundary,
 		 * we may end up purging some legitimate data from the
 		 * start/end of the cache. In such a case, *flush* the
 		 * cachelines at the start and end of the required region.
 		 */
 		else if (ops & BUS_DMASYNC_PREREAD) {
 			/* flush cacheline on start boundary */
 			if (ps & CACHELINE_MASK) {
 				DCFL(ps & ~CACHELINE_MASK);
+			}
 			p = (ps + CACHELINE_MASK) & ~CACHELINE_MASK;
 			e = pe & ~CACHELINE_MASK;
 			/* purge cacheline */
 			while ((p < e) && (p & (CACHELINE_SIZE * 8 - 1)) != 0) {
 				DCPL(p);
 				p += CACHELINE_SIZE;
+			}
 			/* purge cachelines per 128bytes */
 			while ((p < e) && (p & PAGE_MASK) != 0) {
 				DCPL(p);
 				p += CACHELINE_SIZE;
 				DCPL(p);
 				p += CACHELINE_SIZE;
 				DCPL(p);
 				p += CACHELINE_SIZE;
 				DCPL(p);
 				p += CACHELINE_SIZE;
 				DCPL(p);
 				p += CACHELINE_SIZE;
 				DCPL(p);
 				p += CACHELINE_SIZE;
 				DCPL(p);
 				p += CACHELINE_SIZE;
 				DCPL(p);
 				p += CACHELINE_SIZE;
+			}
 			/* purge page */
 			while (p + PAGE_SIZE <= e) {
 				DCPP(p);
 				p += PAGE_SIZE;
+			}
 			/* purge cachelines per 128bytes */
 			while (p + CACHELINE_SIZE * 8 <= e) {
 				DCPL(p);
 				p += CACHELINE_SIZE;
 				DCPL(p);
 				p += CACHELINE_SIZE;
 				DCPL(p);
 				p += CACHELINE_SIZE;
 				DCPL(p);
 				p += CACHELINE_SIZE;
 				DCPL(p);
 				p += CACHELINE_SIZE;
 				DCPL(p);
 				p += CACHELINE_SIZE;
 				DCPL(p);
 				p += CACHELINE_SIZE;
 				DCPL(p);
 				p += CACHELINE_SIZE;
+			}
 			/* purge cacheline */
 			while (p < e) {
 				DCPL(p);
 				p += CACHELINE_SIZE;
+			}
 			/* flush cacheline on end boundary */
 			if (p < pe) {
 				DCFL(p);
+			}
+		}
 		offset = 0;
 		len -= seglen;
+	}
-#endif
+#endif	/* defined(M68040) || defined(M68060) */
+}
 /*
  * Common function for DMA-safe memory allocation.  May be called
  * by bus-specific DMA memory allocation functions.
  */
 int
 bus_dmamem_alloc(bus_dma_tag_t t, bus_size_t size, bus_size_t alignment,
     bus_size_t boundary, bus_dma_segment_t *segs, int nsegs, int *rsegs,
     int flags)
+{
 	return bus_dmamem_alloc_range(t, size, alignment, boundary,